ADL5206-EVALZ_技术文档

1.0 GHz DGA with 30 dB Range and

1 dB Step Size

Data Sheet

ADL5206

FEATURES

FUNCTIONAL BLOCK DIAGRAM

SPI/PARALLEL

INTERFACE

Digitally controlled VGA

VPOS EPAD PWUP

2 dB to 32 dB gain range

1 dB gain step size

ADL5206

LOGIC

MODEx

100 Ω differential input resistance

10 Ω differential output resistance

Noise figure: 5.1 dB at 300 MHz, 5 V supply, and

maximum gain

VOUT+

VOUT–

VIN–

VIN+

32dB

TO

100Ω

10Ω

2dB

OIP3 at maximum gain

39.4 dBm at 300 MHz at 5 V supply

38.1 dBm at 700 MHz at 5 V supply

Gain step accuracy: 0.2 dB

Figure 1.

−3 dB bandwidth at 32 dB: 1.0 GHz typical at 5 V supply

Multiple control interface options

Parallel 5-bit control interface with latch

3- and 4-wire SPI with fast attack

Gain step-up and step-down interface

Wide input dynamic range

Power-down control

Single 3.3 V or 5 V supply operation

112 mA quiescent current at 5 V supply

20-lead, 4 mm × 4 mm LFCSP

APPLICATIONS

Differential ADC drivers

High intermediate frequency (IF) sampling receivers

High output power IF amplification

DOCSIS FDx upstream amplifier

Instrumentation

GENERAL DESCRIPTION

The ADL5206 is a wide bandwidth, variable gain amplifier (VGA)

with digital control (also known as a digital gain amplifier (DGA))

that provides precise gain control, high output third-order

intercept (OIP3), and low noise figure over the entire gain

range. The excellent OIP3 performance of 39.4 dBm (at 300MHz,

5 V supply, and maximum gain) makes the ADL5206 an excellent

gain control device for a variety of receiver applications.

current of the ADL5206 is typically 112 mA with a 5 V supply.

When disabled, the ADL5206 consumes only 8 mA and offers

excellent input to output isolation. The gain setting is preserved

when the device is disabled.

Fabricated on the Analog Devices, Inc., high speed, silicon

germanium (SiGe), bipolar complementary metal-oxide

semiconductor (BiCMOS) process, the ADL5206 provides

precise gain adjustment capabilities with good distortion

performance. The ADL5206 amplifier comes in a compact,

thermally enhanced, 4 mm × 4 mm, 20-lead LFCSP and

operates over the temperature range of −40°C to +85°C.

For wide input dynamic range applications, the ADL5206

provides a broad 2 dB to 32 dB gain range with a 1 dB step size.

The gain is adjustable through multiple gain control and interface

options: parallel, serial peripheral interface (SPI), or gain step-up

and step-down controls.

Note that throughout this data sheet, multifunction pins, such

The ADL5206 can be powered up independently by applying

the appropriate logic level to the PWUP pin. The quiescent

CS

as /GS1/D3, are referred to by the entire pin name or by a

single function of the pin.

Rev. 0

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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

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ADL5206

Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1

Basic Structure............................................................................ 19

Control and Logic Circuitry ..................................................... 19

Common-Mode Voltage........................................................... 19

Register Summary and Details ..................................................... 20

Applications Information ............................................................. 21

Basic Connections...................................................................... 21

Digital Interface Overview........................................................ 22

SPI Read....................................................................................... 23

ADC Interfacing......................................................................... 24

Noise Figure vs. Gain Setting ................................................... 24

Outline Dimensions....................................................................... 25

Ordering Guide .......................................................................... 25

Applications ...................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications .................................................................................... 3

Timing Specifications .................................................................. 6

Absolute Maximum Ratings ........................................................... 7

Thermal Resistance...................................................................... 7

Junction to Board Thermal Impedance .................................... 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions ............................ 8

Typical Performance Characteristics........................................... 10

Theory of Operation ...................................................................... 19

REVISION HISTORY

9/2020—Revision 0: Initial Version

Rev. 0 | Page 2 of 25

Data Sheet

ADL5206

SPECIFICATIONS

T_A= 25°C, load impedance (Z_LOAD) = 100 Ω, maximum gain (gain code = 00000), frequency = 300 MHz, and 2 V p-p differential output,

unless otherwise noted.

Table 1.

3.3 V Supply¹

Min Typ Max

5 V Supply¹

Min Typ

Parameter²

Test Conditions/Comments

Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth

At 20 dB

At 25 dB

At 32 dB

1.7

1.4

1.2

4.3

1.6

1.3

1.0

4.3

GHz

V/ns

Slew Rate

INPUT STAGE

VIN+ and VIN− pins

Gain code = 11111

Maximum Input Swing³

Differential Input Resistance

Input Common-Mode Voltage

Common-Mode Rejection Ratio (CMRR)

GAIN

4

6.2

100

2.5

56

V p-p

Ω

V

100

1.65

56

dB

Voltage Gain Range

Maximum Gain

Minimum Gain

30

32

2

30

32

2

dB

Gain code = 00000

Gain code = 11110 to 11111

Gain Step Size

1

dB

Gain Step Accuracy

Gain Flatness

Gain Temperature Sensitivity

0.2

3

0.2

4

dB

dB p-p

mdB/°C

From 30 MHz to 700 MHz

Gain code = 00000 and at

700 MHz

Fast Attack Step Response Delay

For input voltage (V_IN) = 0.1 V,

FA changing from 0 to 1 with

16 dB step

5

ns

COMMON-MODE INPUTS

VCM Pin Input Resistance

OUTPUT STAGE

2.6

kΩ

VOUT+ and VOUT− pins

Output Voltage Swing

At 1 dB compression point (P1dB),

gain code = 00000

VCM pin

4.1

6.25

2.5

V p-p

Common-Mode Voltage Reference

Output Common-Mode Offset

Differential Output Resistance

Short-Circuit Current

1.2

−10

1.65

1.8

+10

1.4

−10

2.7

V

((VOUT+) + (VOUT−))/2 − VCM/2

+10 mV

10

20

10

25

Ω

mA

NOISE AND HARMONIC PERFORMANCE

10 MHz

Noise Figure

6.2

6.3

dB

Second Harmonic Distortion (HD2)

Third Harmonic Distortion (HD3)

Output Second-Order Intercept (OIP2) V_OUT= 2 V p-p composite

Third Intermodulation Distortion

(IMD3)

V_OUT= 2 V p-p

−85

−89.2

−85.6

87.1

dBc

dBm

dBc

−76.5

84.3

−78.9

V_OUT= 2 V p-p composite

−85.8

Output Third-Order Intercept (OIP3)

V_OUT= 2 V p-p composite

39.4

42.9

dBm

Rev. 0 | Page 3 of 25

ADL5206

Data Sheet

3.3 V Supply¹

Min Typ Max

5 V Supply¹

Min Typ

Parameter²

Test Conditions/Comments

Max Unit

100 MHz

Noise Figure

5.8

5.9

dB

HD2

HD3

OIP2

IMD3

OIP3

V_OUT= 2 V p-p

V_OUT= 2 V p-p composite

−75.8

−72.2

74.7

−77

−78.4

−81

76.8

−84.8

42.4

dBc

dBm

dBc

dBm

38.5

300 MHz

Noise Figure

4.6

5.1

dB

HD2

HD3

OIP2

IMD3

OIP3

V_OUT= 2 V p-p

V_OUT= 2 V p-p composite

−67.8

−56.2

70.5

−75

−77.6

−67.9

79.5

−78.8

39.4

dBc

dBm

dBc

dBm

37.5

500 MHz

Noise Figure

4.5

5

dB

HD2

HD3

OIP2

IMD3

OIP3

V_OUT= 2 V p-p

V_OUT= 2 V p-p composite

−58.7

−52.6

58.3

−68.3

34

−65.6

−66.2

65.7

−76.6

38.3

18

dBc

dBm

dBc

dBm

OP1dB

700 MHz

14.3

Noise Figure

6.7

7

dB

HD2

HD3

OIP2

IMD3

OIP3

V_OUT= 2 V p-p

V_OUT= 2 V p-p composite

−62.7

−55.4

64.2

−61.2

30.6

−69

−77.7

67.2

−76.3

38.1

dBc

dBm

dBc

dBm

1000 MHz

Noise Figure

HD2

HD3

OIP2

7.5

−60.3

−49

61.6

−56.5

28.2

7.9

−62.5

−61

63.3

−69.1

34.5

dB

V_OUT= 2 V p-p

V_OUT= 2 V p-p composite

dBc

dBm

dBc

dBm

IMD3

OIP3

1200 MHz

Noise Figure

HD2

HD3

OIP2

6.6

−53.4

−44

53.6

−54.4

27.2

7

dB

V_OUT= 2 V p-p

V_OUT= 2 V p-p composite

−57.2

−52

57.5

−66.9

33.4

dBc

dBm

dBc

dBm

IMD3

OIP3

Rev. 0 | Page 4 of 25

Data Sheet

ADL5206

3.3 V Supply¹

5 V Supply¹

Min Typ

Parameter²

Test Conditions/Comments

Min Typ

Max

Max Unit

DIGITAL INTERFACE

Input Voltage

MODE1, MODE0, PWUP,

LATCH, and SDIO pins

Logic High (V_IH)

Logic Low (V_IL)

2

0

VPOS

1.0

2

0

3.3

1.0

V

Input Leakage Current

Output Voltage

Digital V_IN= 0 V to 3.3 V

SDIO pin

3

µA

Logic High (V_OH)

Logic Low (V_OL)

Output high current (I_OH) = −2 mA 2.4

Output low current (I_OL) = 2 mA

2.4

0.5

POWER INTERFACE

Supply Voltage (V_POS

)

VPOS pin

3.15 3.3

3.45

4.75

5

5.25

V

Quiescent Current

Power-Down Current

87

8

112

8

mA

PWUP pin = low

¹The 3.3 V supply is low power mode, and the 5 V supply is high performance mode.

²When referring to a single function of a multifunction pin in the specifications table, only the portion of the pin name that is relevant to the specification is listed. For

full pin names of multifunction pins, refer to the Pin Configuration and Function Descriptions section.

³The maximum input swing of 6.2 V p-p is for the lowest gain setting of 2 dB. As the gain setting increases, the maximum input swing must be reduced correspondingly

to maintain the same maximum output swing. The maximum output swing is based on P1dB.

Rev. 0 | Page 5 of 25

ADL5206

Data Sheet

TIMING SPECIFICATIONS

Table 2. SPI Timing Parameters

Parameter Description

Min Typ Max Unit

f_SCLK

t_PWH

t_PWL

t_DS

t_DH

t_DCS

t_H

Maximum serial clock rate, 1/t_SCLK(t_SCLKis the SCLK time)

25

10

5

MHz

ns

Minimum period that SCLK is in a logic high state

Minimum period that SCLK is in a logic low state

Setup time between the data and the rising edge of SCLK

Hold time between the data and the rising edge of SCLK

5

Setup time between the falling edge of and the rising edge of SCLK

CS

10

5

ns

Hold time between the rising edge of and the last falling edge of SCLK

CS

ns

t_DV

Maximum time delay between the falling edge of SCLK and the output data valid for a read

operation

14

12

ns

t_z

Maximum time delay between

deactivation and the SDIO bus return to high impedance

ns

CS

Timing Diagrams

INSTRUCTION CYCLE

ADDRESS

DATA TRANSFER CYCLE

CS

SCLK

SDI

R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5

N

D3 D2 D1 D0

N

0

Figure 2. SPI Register Timing, MSB First

t_SCLK

t_PWL

t_PWH

SCLK

CS

t_DCS

t_H

t_DH

t_DS

t_Z

SDI

R/W

CS5

CS4

0

A_MSB

A7

A2

A1

A_LSB D_MSB

D6

D5

D1

D_LSB

Figure 3. Timing Diagram for the SPI Register Write

SCLK

CS

t_DV

D5

R/W

A_MSB

A13

A12

A11

A10

A9

A8

A7

A2

A1

A_LSB D_MSB

D6

D1

D_LSB

SDIO

Figure 4. Timing Diagram for SPI Register Read

Rev. 0 | Page 6 of 25

Data Sheet

ADL5206

ABSOLUTE MAXIMUM RATINGS

Table 3.

JUNCTION TO BOARD THERMAL IMPEDANCE

Parameter¹

Differential Output Voltage Swing ×

Bandwidth Product

5 V Supply Voltage

3.3 V Supply Voltage

Rating

The junction thermal, die to board, impedance (θ_JB) is the

thermal impedance from the die to the leads of the ADL5206.

The value given in Table 4 is based on the standard PCB described

in the JESD51-7 standard for thermal testing of surface-mount

components. PCB size and complexity (number of layers) affect

θ_JB, and more layers tend to reduce thermal impedance slightly.

4 V-GHz

3 V-GHz

5.4 V

−0.5 V to +3.6 V

−0.5 V to +3.1 V

1 V

Supply Voltage, V_POS

PWUP, D0 to D4, MODE0, MODE1, LATCH

Input Voltage (VIN+ and VIN−)

Differential Input Voltage²((VIN+) − (VIN−))

If the PCB temperature (T_B) is known, use the junction to board

thermal impedance to calculate the die temperature (also

known as the junction temperature, T_J) to ensure that the die

temperature does not exceed the specified limit of 135°C. For

example, if the PCB temperature is 85°C, the die temperature

is given by

Internal Power Dissipation (P_DISS

)

500 mW

Temperature

Maximum Junction

Operating Range

135°C

−40°C to +85°C

−65°C to +150°C

T_J= T_B+ (P_DISS× θ_JB)

Storage Range

¹When referring to a single function of a multifunction pin in the parameters,

only the portion of the pin name that is relevant to the specification is listed.

For full pin names of multifunction pins, refer to the Pin Configuration and

Function Descriptions section.

²The differential input voltage limit is significantly lower than the maximum

input swing of 6.2 V p-p with a 5 V supply. The maximum input swing is for

the lowest gain setting of 2 dB. As the gain setting increases, the maximum

input swing must be reduced correspondingly to maintain the same maximum

output swing. The maximum output swing is based on P1dB.

The worst case P_DISSfor the ADL5206 is 500 mW (5.0 V ×

110 mA, see Table 3). Therefore, T_Jis

T_J= 85°C + (0.499 W × 24.4°C/W) = 97.2°C

ESD CAUTION

Stresses at or above those listed under absolute maximum

ratings can cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

THERMAL RESISTANCE

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Careful attention to

PCB thermal design is required.

Table 4 shows the thermal resistance from the die to ambient

(θ_JA), die to board (θ_JB), and die to lead (θ_JC).

Table 4. Thermal Resistance

Package Type

θ_JA

θ_JB

θ_JC

Unit

CP-20-16

55.42 16.01

9.08

°C/W

Rev. 0 | Page 7 of 25

ADL5206

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

15 VOUT+

VCM

MODE1

14 VOUT–

ADL5206

MODE0

13 PWUP

TOP VIEW

12 DNC

SDIO/SDO

SCLK/D4

(Not to Scale)

11 LATCH/SPI_HP_LP

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THESE PINS.

2. EXPOSED PAD GROUND. THE EXPOSED PAD MUST BE

CONNECTED TO A LOW IMPEDANCE GROUND PLANE.

Figure 5. Pin Configuration (Top View)

Table 5. Pin Function Descriptions

Pin No. Mnemonic

Description

1

2

VCM

MODE1

Common-Mode Output.

The MSB for Mode Control. Use both the MODE0 and MODE1 pins to select high performance or to

select low power parallel, SPI, or up and down interface mode.

3

4

5

MODE0

SDIO/SDO

SCLK/D4

The LSB for Mode Control. Use both the MODE1 and MODE0 pins to select parallel, SPI, or UPDN mode.

Serial Data Input and Output in 3-Wire SPI Mode (SDIO). Serial data output in 4-wire SPI mode (SDO).

Serial Clock Input/Digital Bit 4. Depending on the selection of the MODE0 and MODE1 pins, this pin

has two functions. In serial or SPI mode, this pin functions as SCLK. In parallel mode, this pin

represents D4 when in the parallel gain control interface.

6

7

/GS1/D3

Chip Select (Active Low)/Gain Step 1/Digital Bit 3. Depending on the selection of the MODE0 and

CS

MODE1 pins, this pin has three functions. In serial or SPI mode, this pin becomes . When in UPDN

CS

mode, the GS1 function is enabled for this pin, which controls the MSB gain step size. In parallel

mode, this pin represents D3 when in the parallel gain control interface.

FA/GS0/D2

Fast Attack/Gain Step 0/Digital Bit 2. Depending on the selection of the MODE0 and MODE1 pins,

this pin has three functions. In serial or SPI mode, the FA function of this pin is enabled. The FA

function allows the user to define a larger attenuation jump in the digital gain control settings. The

FA pin attenuates according to an FA SPI word definition of FA0 and FA1 (the attenuation step size

bits), which is defined by the user. When in UPDN mode, the GS0 function is enabled for this pin

which controls the LSB gain step size. In parallel mode, this pin represents D2 when in the parallel

gain control interface.

8

UPDN_CLK/D1/SDI

Clock Interface for Up and Down Interface (UPDN_CLK). Depending on MODE0 and MODE1 selection,

this pin has three functions. In the up and down interface mode, this pin becomes UPDN_CLK. In

parallel mode, this pin represents Digital Bit 1 (D1) when using a parallel gain control interface. In

4-wire SPI mode, this pin is the serial data input (SDI).

9

UPDN_DAT/D0/

_4SPI Data Interface for Up and Down Interface (UPDN_DAT). Depending on MODE0 and MODE1 selection,

this pin has three functions. In up and down interface mode, this pin becomes UPDN_DAT. In parallel

mode, this pin represents Digital Bit 0 (D0) when using a parallel gain control interface. In SPI mode,

3SPI

logic low selects 3-wire SPI and logic high selects 4-wire SPI (

_4SPI).

3SPI

10, 12

DNC

Do Not Connect. Do not connect to these pins.

Rev. 0 | Page 8 of 25

Data Sheet

ADL5206

Pin No. Mnemonic

Description

11

LATCH/SPI_HP_

LP

The latch when the MODE0 and MODE1 pins are in parallel mode (LATCH). A logic low on this pin

allows the gain to change, and a logic high on this pin prevents the gain change. In SPI mode, logic

high selects high performance mode, and logic low selects low power mode (SPI_HP_ ).

LP

13

PWUP

Power-Up. PWUP remains the power-up pin function with any selection of the MODE0 and MODE1

pins. A logic high on this pin powers up, and a logic low on this pin powers down.

14

15

16, 19

17

18

VOUT−

VOUT+

VPOS

VIN+

VIN−

Negative Analog Output.

Positive Analog Output.

Positive Power Supply, 5 V.

Positive Analog Input.

Negative Analog Input.

20

DNC INTERIM

Do Not Connect. Tie DNC INTERIM to a resistor divider that is 25 kΩ to 5 V and 50 kΩ to ground or to

a pull-up that is 50 kΩ to 3.3 V.

EP

Exposed Pad Ground. The exposed pad must be connected to a low impedance ground plane. This

plane is the ground (0 V) reference for all voltages in Table 1.

Table 6. Pin Function Overview for Various Modes

Mode

Pin 2

Pin 3

Pin 4

Pin 5

Pin 6

Pin 7

Pin 8

Pin 9

Pin 11

Pin 13

Parallel

High Performance

Low Power

SPI, 3-Wire

0

1

0

1

Unused

D4

D3

D2

D1

D0

LATCH

1

High Performance

Low Power

0

1

SDIO

SCLK

CS

FA

Unused

0

1

SPI, 4-Wire

High Performance

Low Power

0

1

SDO

SCLK

CS

FA

SDI

1

0

1

Up or Down

High Performance

Low Power

1

0

Unused

GS1

GS0

UPDN_CLK

UPDN_DAT

0

1

Rev. 0 | Page 9 of 25

ADL5206

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

Nominal V_POS= 5 V, T_A= 25°C, Z_LOAD= 100 Ω, maximum gain (gain code = 00000), 2 V p-p composite differential output for IMD3 and

OIP3, 2 V p-p differential output for HD2 and HD3, and VCM = V_POS/2, unless otherwise noted.

130

125

120

115

110

105

100

95

1.2

VPOS = 4.75V

VPOS = 5V

VPOS = 5.25V

FREQUENCY = 10MHz

FREQUENCY = 100MHz

FREQUENCY = 200MHz

FREQUENCY = 300MHz

FREQUENCY = 500MHz

FREQUENCY = 700MHz

FREQUENCY = 1000MHz

FREQUENCY = 1250MHz

FREQUENCY = 1500MHz

FREQUENCY = 1750MHz

1.0

0.8

0.6

0.4

0.2

0

90

–0.2

–0.4

–0.6

–0.8

85

80

75

70

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80

TEMPERATURE (°C)

2

7

12

17

22

27

32

VOLTAGE GAIN (dB)

Figure 6. Supply Current vs. Temperature, High Performance Mode

Figure 9. Gain Step Error vs. Voltage Gain, 5 V High Performance Mode

130

55

VPOS = 3.13V

VOLTAGE GAIN = 14dB

VOLTAGE GAIN = 26dB

VOLTAGE GAIN = 32dB

VOLTAGE GAIN = 6dB

VPOS = 5V

VPOS = 3.3V

VPOS = 3.47V

VPOS = 4.75V

VPOS = 5V

125

120

115

110

105

100

95

50

45

40

35

30

25

20

15

10

VPOS = 5.25V

90

85

80

75

70

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80

TEMPERATURE (°C)

0

200 400 600 800 1000 1200 1400 1600 1800 2000

FREQUENCY (MHz)

Figure 7. Supply Current vs. Temperature, Low Power Mode

Figure 10. OIP3 vs. Frequency over VPOS = 5 V at Four Voltage Gains,

High Performance Mode

32

30

28

26

24

22

20

18

16

14

12

10

8

55

T

= –40°C

= +25°C

= +85°C

T

= –40°C

= +25°C

= +85°C

VPOS = 5V

A

50

45

40

35

30

25

20

15

10

6

4

2

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30

GAIN CODE

0

200 400 600 800 1000 1200 1400 1600 1800 2000

FREQUENCY (MHz)

Figure 8. Gain vs. Gain Code over Temperature at 500 MHz

Figure 11. OIP3 vs. Frequency over VPOS = 5 V for Three Temperatures at

Maximum Gain, High Performance Mode

Rev. 0 | Page 10 of 25

Data Sheet

ADL5206

55

50

45

40

35

30

25

20

15

10

55

50

45

40

35

30

25

20

15

10

VPOS = 3.13V

VOLTAGE GAIN = 14dB

VOLTAGE GAIN = 26dB

VOLTAGE GAIN = 32dB

VOLTAGE GAIN = 6dB

VPOS = 3.3V

VPOS = 3.47V

VPOS = 4.75V

VPOS = 5V

VPOS = 3.3V

VPOS = 5V

VPOS = 5.25V

0

200 400 600 800 1000 1200 1400 1600 1800 2000

FREQUENCY (MHz)

0

200 400 600 800 1000 1200 1400 1600 1800 2000

FREQUENCY (MHz)

Figure 12. OIP3 vs. Frequency over VPOS = 3.3 V and VPOS = 5 V at

Four Voltage Gains, Low Power Mode

Figure 15. OIP3 vs. Frequency and VPOS Variance (5%) at Maximum Gain,

Low Power Mode

55

–20

VPOS = 5V

T

= –40°C

= +25°C

= +85°C

VPOS = 3.3V

VPOS = 5V

VOLTAGE GAIN = 26dB

VOLTAGE GAIN = 14dB

VOLTAGE GAIN = 32dB

VOLTAGE GAIN = 6dB

A

–30

50

45

40

35

30

25

20

15

10

–40

–50

–60

–70

–80

–90

–100

–110

–120

0

200 400 600 800 1000 1200 1400 1600 1800 2000

FREQUENCY (MHz)

0

200 400 600 800 1000 1200 1400 1600 1800 2000

FREQUENCY (MHz)

Figure 13. OIP3 vs. Frequency over VPOS = 3.3 V and VPOS = 5 V for

Three Temperatures at Maximum Gain, Low Power Mode

Figure 16. IMD3 vs. Frequency over VPOS = 5 V for Four Voltage Gains,

High Performance Mode

55

–20

VPOS = 4.75V

VPOS = 5V

VPOS = 5.25V

VPOS = 3.3V

VPOS = 5V

VOLTAGE GAIN = 26dB

VOLTAGE GAIN = 14dB

VOLTAGE GAIN = 32dB

VOLTAGE GAIN = 6dB

–30

–40

50

45

40

35

30

25

20

15

10

–50

–60

–70

–80

–90

–100

–110

–120

0

200 400 600 800 1000 1200 1400 1600 1800 2000

FREQUENCY (MHz)

0

200 400 600 800 1000 1200 1400 1600 1800 2000

FREQUENCY (MHz)

Figure 14. OIP3 vs. Frequency and VPOS Variance (5%) at Maximum Gain,

High Performance Mode

Figure 17. IMD3 vs. Frequency over VPOS = 3.3 V and VPOS = 5 V for

Four Voltage Gains, Low Power Mode

Rev. 0 | Page 11 of 25

ADL5206

Data Sheet

–20

–30

VPOS = 3.3V

VPOS = 5V

VOLTAGE GAIN = 14dB

VOLTAGE GAIN = 26dB

VOLTAGE GAIN = 32dB

VOLTAGE GAIN = 6dB

T

= –40°C

= +25°C

= +85°C

A

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–100

–110

–120

0

200 400 600 800 1000 1200 1400 1600 1800 2000

FREQUENCY (MHz)

0

200 400 600 800 1000 1200 1400 1600 1800 2000

FREQUENCY (MHz)

Figure 18. HD2 vs. Frequency over VPOS = 5 V for Four Voltage Gains,

High Performance Mode

Figure 21. HD2 vs. Frequency over VPOS = 3.3 V and VPOS = 5 V for Three

Temperatures at Maximum Gain, 2 V p-p, Low Power Mode

–20

T

= –40°C

= +25°C

= +85°C

VPOS = 5V

A

–30

–40

–30

–40

–50

–60

–70

–80

–90

–50

–60

–70

–80

–90

–100

–110

–120

–100

–110

–120

VOLTAGE GAIN = 26dB

VOLTAGE GAIN = 14dB

VOLTAGE GAIN = 32dB

VOLTAGE GAIN = 6dB

0

200 400 600 800 1000 1200 1400 1600 1800 2000

FREQUENCY (MHz)

0

200 400 600 800 1000 1200 1400 1600 1800 2000

FREQUENCY (MHz)

Figure 19. HD2 vs. Frequency over VPOS = 5 V for Three Temperatures at

Maximum Gain, 2 V p-p, High Performance Mode

Figure 22. HD3 vs. Frequency over VPOS = 5 V for Four Voltage Gains at

2 V p-p, High Performance Mode

–20

VOLTAGE GAIN = 26dB

VOLTAGE GAIN = 14dB

VOLTAGE GAIN = 32dB

VOLTAGE GAIN = 6dB

VPOS = 3.3V

VPOS = 5V

T

= –40°C

= +25°C

= +85°C

VPOS = 5V

A

–30

–40

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–100

–110

–120

0

200 400 600 800 1000 1200 1400 1600 1800 2000

FREQUENCY (MHz)

0

200 400 600 800 1000 1200 1400 1600 1800 2000

FREQUENCY (MHz)

Figure 20. HD2 vs. Frequency over VPOS = 3.3 V and VPOS = 5 V for

Four Voltage Gains at 2 V p-p, Low Power Mode

Figure 23. HD3 vs. Frequency over VPOS = 5 V for Three Temperatures at

Maximum Gain, 2 V p-p, High Performance Mode

Rev. 0 | Page 12 of 25

Data Sheet

ADL5206

–20

20

19

18

17

16

15

14

13

12

11

10

9

VOLTAGE GAIN = 14dB

VPOS = 3.3V

VPOS = 5V

VOLTAGE GAIN = 9dB TO 2dB

VOLTAGE GAIN = 17dB TO 10dB

VOLTAGE GAIN = 32dB TO 18dB

VOLTAGE GAIN = 26dB

VOLTAGE GAIN = 32dB

VOLTAGE GAIN = 6dB

–30

–40

–50

–60

–70

–80

8

7

–90

6

5

–100

–110

–120

4

3

2

1

0

500

1000

1500

2000

0

200 400 600 800 1000 1200 1400 1600 1800 2000

FREQUENCY (MHz)

Figure 24. HD3 vs. Frequency over VPOS = 3.3 V and VPOS = 5 V for

Four Voltage Gains at 2 V p-p, Low Power Mode

Figure 27. Noise Figure vs. Frequency over Voltage Gain Ranges,

5 V Low Power Mode

–20

–30

–40

–50

–60

–70

–80

–90

–100

20

19

18

17

16

15

14

13

12

11

10

9

VOLTAGE GAIN = 9dB TO 2dB

VOLTAGE GAIN = 17dB TO 10dB

VOLTAGE GAIN = 32dB TO 18dB

8

7

6

5

4

3

2

1

0

T

= –40°C

= +25°C

= +85°C

A

–110

–120

VPOS = 3.3V

VPOS = 5V

0

200 400 600 800 1000 1200 1400 1600 1800 2000

FREQUENCY (MHz)

0

500

1000

1500

2000

FREQUENCY (MHz)

Figure 25. HD3 vs. Frequency over VPOS = 3.3 V and VPOS = 5 V for

Three Temperatures at Maximum Gain, 2 V p-p, Low Power Mode

Figure 28. Noise Figure vs. Frequency over Voltage Gain Ranges,

3.3 V Low Power Mode

20

19

10

VOLTAGE GAIN = 9dB TO 2dB

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

VOLTAGE GAIN = 17dB TO 10dB

VOLTAGE GAIN = 32dB TO 18dB

0

–10

–20

–30

–40

–50

–60

0

500

1000

1500

2000

0

2

4

6

8

10

12

FREQUENCY (MHz)

FREQUENCY (GHz)

Figure 26. Noise Figure vs. Frequency over Voltage Gain Ranges,

5 V High Performance Mode

Figure 29. SDD11 vs. Frequency at Gain = 2 dB, 5 V High Performance Mode

Rev. 0 | Page 13 of 25

ADL5206

Data Sheet

–20

–30

–40

–50

–60

–70

10

0

–10

–20

–30

–40

–50

–60

–80

0

2

4

6

8

10

12

0

2

4

6

8

10

12

FREQUENCY (GHz)

Figure 30. SDD12 vs. Frequency at Gain = 2 dB, 5 V High Performance Mode

Figure 33. SDD11 vs. Frequency at Gain = 32 dB, 5 V High Performance Mode

40

30

–20

–30

–40

–50

–60

–70

–80

20

10

0

–10

–20

–30

–40

0

2

4

6

8

10

12

0

2

4

6

8

10

12

FREQUENCY (GHz)

Figure 31. SDD21 vs. Frequency at Gain = 2 dB, 5 V High Performance Mode

Figure 34. SDD12 vs. Frequency at Gain = 32 dB, 5 V High Performance Mode

–1

–2

40

30

–3

20

–4

10

–5

–6

0

–7

–10

–20

–30

–40

–8

–9

–10

–11

0

2

4

6

8

10

12

0

2

4

6

8

10

12

FREQUENCY (GHz)

Figure 32. SDD22 vs. Frequency at Gain = 2 dB, 5 V High Performance Mode

Figure 35. SDD21 vs. Frequency at Gain = 32 dB, 5 V High Performance Mode

Rev. 0 | Page 14 of 25

Data Sheet

ADL5206

–1

–2

34

32

30

28

26

24

22

20

18

16

14

12

10

8

VOLTAGE GAIN = 32dB

–3

–4

–5

–6

6

4

2

–7

VOLTAGE GAIN = 2dB

0

–2

–4

–6

–8

–10

–12

–14

–16

–18

–20

–8

–9

–10

–11

0

2

4

6

8

10

12

10M

100M

FREQUENCY (Hz)

1G

10G

FREQUENCY (GHz)

Figure 39. Gain vs. Frequency over Voltage Gains,

3.3 V Low Power Mode

Figure 36. SDD22 vs. Frequency at Gain = 32 dB, 5 V High Performance Mode

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

4

3

2

1

0

34

VOLTAGE GAIN = 32dB

32

30

28

26

24

22

20

18

16

14

12

10

8

6

4

V oltage Gain = 2dB

2

VOLTAGE GAIN = 2dB

0

–2

–4

–6

–8

–10

–12

–14

–16

–18

–20

–1

40

–10

–5

0

5

10

15

20

25

30

35

10M

100M

FREQUENCY (Hz)

1G

10G

TIME (ns)

Figure 40. Enable Time Domain Response, 5 V High Performance Mode

Figure 37. Gain vs. Frequency over Voltage Gains,

5 V High Performance Mode

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

34

32

30

28

26

24

22

20

18

16

14

12

10

8

VOLTAGE GAIN = 32dB

6

4

2

VOLTAGE GAIN = 2dB

0

–2

–4

–6

–8

–10

–12

–14

–16

–18

–20

–0.5

–1.0

40

–10

–5

0

5

10

15

20

25

30

35

10M

100M

FREQUENCY (Hz)

1G

10G

TIME (ns)

Figure 41. Disable Time Domain Response, 5 V High Performance Mode

Figure 38. Gain vs. Frequency over Voltage Gains,

5 V Low Power Mode

Rev. 0 | Page 15 of 25

ADL5206

Data Sheet

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

4

3

2

1

0

–0.5

–1.0

–1

–10

0

10

20

30

40

50

60

–10

–5

0

5

10

15

20

25

30

TIME (ns)

Figure 42. Enable Time Domain Response, 3.3 V Low Power Mode

Figure 45. Fast Attack Disable Time Domain Response,

5 V High Performance Mode

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

4

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

4

3

2

1

0

–1

15

–1

15

–5

–3

–1

1

3

5

7

9

11

13

–5

–3

–1

1

3

5

7

9

11

13

TIME (ns)

Figure 43. Disable Time Domain Response, 3.3 V Low Power Mode

Figure 46. Fast Attack Enable Time Domain Response,

3.3 V Low Power Mode

5.0

4.5

4.00

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

5

4

3

2

1

0

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

4

3

2

1

0

–1

15

–5

–3

–1

1

3

5

7

9

11

13

TIME (ns)

Figure 44. Fast Attack Enable Time Domain Response,

5 V High Performance Mode

Figure 47. Fast Attack Disable Time Domain Response,

3.3 V Low Power Mode

Rev. 0 | Page 16 of 25

Data Sheet

ADL5206

70

400

350

300

250

200

150

100

VOLTAGE GAIN = 2dB

VOLTAGE GAIN = 32dB

60

50

40

30

20

10

0

VPOS = 3.3V, LOW POWER MODE

VPOS = 5V, HIGH PERFORMANCE MODE

–10

10M

100M

1G

10G

10M

100M

1G

2G

FREQUENCY (Hz)

Figure 48. CMRR vs. Frequency at Voltage Gain = 2 dB and Voltage Gain =

32 dB, 5 V High Performance Mode and 3.3 V Low Power Mode

Figure 51. Group Delay vs. Frequency at Maximum Gain,

5 V High Performance Mode

4.0

40

21ns TO 28ns

30

20

3.5

3.0

2.5

2.0

1.5

1.0

10

0

–10

–20

–30

–40

–10

–5

0

5

10

15

20

25

30

10M

100M

1G

2G

SETTLING TIME (ns)

FREQUENCY (Hz)

Figure 49. Output Common-Mode Voltage vs. Settling Time,

5 V High Performance Mode, Maximum Gain Transition

Figure 52. Group Delay vs. Frequency at Maximum Gain,

5 V Low Power Mode

400

3.0

2.5

2.0

1.5

1.0

0.5

0

3ns TO 4ns

350

300

250

200

150

100

10M

100M

1G

2G

–5

–3

–1

1

3

5

7

9

11

13

15

FREQUENCY (Hz)

SETTLING TIME (ns)

Figure 50. Group Delay vs. Frequency at Maximum Gain,

3.3 V Low Power Mode

Figure 53. Output Common-Mode Voltage vs. Settling Time,

3.3 V Low Power Mode, Maximum Gain Transition

Rev. 0 | Page 17 of 25

ADL5206

Data Sheet

1

2

0.5

0.1

5

M2

M3

M5

M6

0

30

0

30

M2

M3

M5

M6

–0.1

–5

–0.1

–5

GAIN = 8dB

GAIN = 14dB

GAIN = 26dB

GAIN = 32dB

GAIN = 8dB

GAIN = 14dB

GAIN = 26dB

GAIN = 32dB

–0.5

–2

–1

FREQUENCY (10MHz TO 12GHz)

Figure 54. Differential Input Reflection (SDD11) Magnitude and Phase vs.

Frequency over Four Gain

Figure 56. Differential Output Reflection (SDD22) Magnitude and Phase vs.

Frequency over Four Gains

150

3.3V, LOW POWER MODE

5.0V,HIGH PERFORMANCE MODE

145

5.0V,LOW POWER MODE

140

135

130

125

120

115

110

FREQUENCY = 100MHz

105

100

FREQUENCY = 700MHz

FREQUENCY = 1200MHz

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

VOLTAGE GAIN (dB)

Figure 55. Spurious-Free Dynamic Range (SFDR) vs. Voltage Gain

Across Power Modes and Various Frequencies

Rev. 0 | Page 18 of 25

Data Sheet

ADL5206

THEORY OF OPERATION

BASIC STRUCTURE

COMMON-MODE VOLTAGE

The ADL5206 is a differential, digitally controlled VGA, which is

also known as a DGA. The DGA consists of a 100 Ω differential

input, digitally controlled passive attenuator, followed by a

digitally controlled gain amplifier. On-chip logic circuitry maps

the gain codes such that all gain changes, from the maximum

gain to minimum gain, are accomplished by only using the

digitally controlled resistors in the feedback of the amplifier.

The ADL5206 is flexible in terms of input and output coupling.

The ADL5206 can be ac-coupled or dc-coupled at the inputs

and/or outputs within the specified output common-mode

voltage reference range of 1.2 V to 1.8 V for the 3.3 V supply

and 1.4 V to 2.7 V for the 5 V supply, depending on the supply

voltage. If no external output common-mode voltage is applied,

the input and output common-mode voltages are set internally

to half of the supply voltage.

This technique does not require a digital step attenuator (DSA)

on the input of the amplifier, thus providing SFDR increases

as gain reduces. This topology also allows all 30 dB of gain

reduction in the feedback with a total noise figure degradation

of 7 dB only over the total 30 dB gain range at 700 MHz. The

differential output impedance of the amplifier is 10 Ω.

The output common-mode voltages of the ADL5206 are

controlled by the voltages on the VCM pin. The VCM pin is

connected internally through 5 kΩ resistors to the VPOS pin

as well as to the exposed pad. As a result, the common-mode

output voltage is preset internally to half of the supply voltage at

VPOS. Alternatively, the VCM pin can be connected to the

common-mode voltage reference output from an ADC, and

thus the common-mode levels between the amplifier and the

ADC can be matched without requiring any external components.

CONTROL AND LOGIC CIRCUITRY

The ADL5206 features three different gain control interfaces:

serial, parallel, or up and down control, which is determined by

the combination of the MODE1 and MODE0 pins. For details

on controlling the gain in each of these modes, see the Digital

Interface Overview section. Typically, the gain step size is 1 dB.

Larger step sizes can be programmed, as described in the Digital

Interface Overview section. The amplifier has a maximum gain

of 32 dB (Gain Code 00000) to a minimum gain of 2 dB

(Gain Code 11110 to Gain Code 11111).

Rev. 0 | Page 19 of 25

ADL5206

Data Sheet

REGISTER SUMMARY AND DETAILS

Table 7. Register Summary

Register

Address

Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

R/W

0x0

CTL

[7:0]

RESERVED

FAST_ATTACK_CTL

GAIN_CTL

0x18

R/W

Register Address: 0x0, Reset: 0x18, Name: CTL

7

6

5

4

3

2

1

0

1

0

[7] RESERVED

[4:0] GAIN_CTL (R/W)

[6:5] FAST_ATTACK_CTL (R/W)

Table 8. Bit Descriptions for CTL

Bits Bit Name Description

RESERVED Reserved

[6:5] FAST_ATTACK_CTL Fast Attack Step Size

[4:0] GAIN_CTL Gain Control

Reset

0x0

Access

R

7

0x0

R/W

0x18

Rev. 0 | Page 20 of 25

Data Sheet

ADL5206

APPLICATIONS INFORMATION

are decoupled using 0.1 µF capacitors as well. The digital pins

(that is the mode control pins, the associated SPI and parallel

gain control pins, the power mode, and the PWUP pin) operate

at a 3.3 V voltage.

BASIC CONNECTIONS

Figure 57 shows the basic connections for operating the

ADL5206.

Apply a 3.3 V or 5 V voltage to the VPOS pins. Decouple the

supply pins with at least one low inductance, surface-mount, 0.1

µF ceramic capacitor and place the capacitor as close to the

device as possible.

To enable the ADL5206, pull the PWUP pin high (2.0 V ≤

PWUP ≤ 3.3 V).

A logic low on the PWUP pin sets the ADL5206 to sleep mode,

reducing the current consumption to approximately 7 mA. The

VCOM pin is the output common-mode voltage, and the

VCOM pin must be decoupled with a 0.1 µF capacitor for

filtering noise.

The differential outputs (VOUT+ and VOUT−) have a dc

common-mode voltage that is approximately half of the supply.

Therefore, decouple these outputs using 0.1 µF capacitors to

balance the load. The balanced differential inputs have the same

dc common-mode voltage as the outputs. Note that the inputs

BALANCED

SOURCE

AC

½R

S

0.1µF

5PO_VCC

0.1µF

ADL5206

0.1µF

15

VCOM

MODE1

EXPOSED

PAD

VOUT+

VCOM

BALANCED

LOAD

R

14

13

12

11

L

0.1µF

VOUT–

MODE1

MODE0

SDIO/SDO

SCLK/D4

PWUP

MODE0

PWUP

DNC

SDIO/SDO

SCLK/D4

LATCH/SPI_HP_LP

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THESE PINS.

2. EXPOSED PAD GROUND. THE EXPOSED PAD MUST BE

CONNECTED TO A LOW IMPEDANCE GROUND PLANE.

Figure 57. Basic Connections

Rev. 0 | Page 21 of 25

ADL5206

Data Sheet

The SPI uses a bidirectional pin (SDIO) for writing to the SPI

register and for reading from the SPI register in 3-wire SPI mode.

Whereas in 4-wire SPI mode, SDI is dedicated to writing to the

SPI register of the device, and SDO is dedicated to reading from

the SPI register of the device. To write to the SPI register, pull

DIGITAL INTERFACE OVERVIEW

The three digital control interface options for the ADL5206

DGA include the following:

•

Parallel control interface

Serial peripheral interface

Gain step-up and step-down interface

CS

the

pin low and apply 8 clock pulses to shift the 8 bits into

the corresponding SPI register, MSB first.

The digital control interface selection is made via two digital

pins, MODE1 and MODE0, as shown in Table 9.

The SPI register read back operation is described in the SPI

Read section.

The same physical pins are shared between three interfaces,

resulting in as many as three different functions per digital pin

(see Table 5).

SPI fast attack mode is controlled by the FA pin. A logic high on

the FA pin results in an attenuation selected by the FA1 and the

FA0 bits in the SPI register.

Table 9. Digital Control Interface Selection Truth Table

Table 10. SPI 2-Bit Attenuation Step Size Truth Table

MODE1

MODE0

Interface

FA1

FA0

Step Size (dB)

0

1

0

1

0

1

Parallel, high performance

Serial

Up and down

Parallel, low power

0

1

0

1

0

1

2

4

8

16

Parallel Digital Interface

Up and Down Interface

The parallel digital interface uses five gain control bits and a

latch pin. The LATCH pin controls whether the input data latch

is transparent (logic low) or latched (logic high). In transparent

mode, the gain changes as the input gain control bits change. In

latched mode, the gain is determined by the latched gain setting

and is not changed by changing the input gain control bits.

The up and down interface uses two digital pins to control the

gain. When the UPDN_DAT pin is low, the gain is increased by

a clock pulse on the UPDN_CLK pin (rising and falling edges).

When the UPDN_DAT pin is high, the corresponding gain is

decreased by a clock pulse on the UPDN_CLK pin. Reset is

detected when the rising edge of UPDN_CLK latches one

polarity on UPDN_DAT, and the falling edge latches the opposite

polarity. Reset results in a minimum gain code of 11110.

SPI

CS

The SPI uses three pins (SDIO, SCLK, and ) in 3-wire SPI

CS

mode and four pins (SDI, SDO, SCLK, and ) in 4-wire SPI

UPDN_DAT

UPDN_CLK

mode. The SPI data register consists of eight bits: five gain

control bits (D0 to D4), two attenuation step size address bits

W

(FA0 and FA1), and one read/write bit (R/ ), as shown in

UP

DN

RESET

Figure 58.

Figure 59. Up and Down Gain Control Timing

LSB

MSB LSB MSB

The step size is selectable by the GS1 and GS0 pins. The default

step size is 1 dB. The gain code count rails at the top and bottom

of the control range.

DATA

D0

D1

D2

D3

D4 FA0 FA1 R/W

READ/WRITE

FAST ATTACK

GAIN CONTROL

Table 11. Step Size Control Truth Table

GS1

GS0

Step Size (dB)

Figure 58. 8-Bit SPI Register

0

1

0

1

0

1

2

4

8

Rev. 0 | Page 22 of 25

Data Sheet

ADL5206

SPI READ

Table 12. Gain Code vs. Voltage Gain

The ADL5206 can be read back only in serial mode during a

CS CS W

high) after the R/ bit is set high

in the previous cycle. During the read cycle, data changes at

each rising edge of SCLK and can be latched using the falling

edge of SCLK. There is no continual read operation. A logic

5-Bit Binary Gain Code, D4 to D0

Voltage Gain (dB)

read cycle (from

low to

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

W

high (1) must be written into the R/ bit to enable the subsequent

W

read cycle, and once the R/ bit is set, the rest of the bits are

ignored in that write cycle.

The sequence for writing and then reading back is shown in

Figure 60 to Figure 62, showing the operation of the input and

output functions of the SDIO pin.

CS

SCLK

SDIO (IN)

SDIO (OUT)

WRITE VALUE

WRITE 0x54

R/W BIT LOW ON SDIO (IN)

DATA WRITTEN ON RISING CLOCK EDGE

Figure 60. Write Gain Control Word

CS

SCLK

8

7

6

5

4

3

2

SDIO (IN)

SDIO (OUT)

SET UP READ

WRITE 0x10

R/W BIT LOW ON SDIO (OUT)

Figure 61. Write Logic 1 into R/W Bit

CS

SCLK

SDIO (IN)

SDIO (OUT)

PERFORM READ

READ 0x54

R/W BIT HIGH

DATA READ ON FALLING CLOCK EDGE

Figure 62. Perform Read

Rev. 0 | Page 23 of 25

ADL5206

Data Sheet

ADC INTERFACING

NOISE FIGURE vs. GAIN SETTING

A typical data acquisition system using the ADL5206 together

with an antialiasing filter and an ADC is shown in Figure 63.

The main role of the filter after the amplifier is for attenuating

the broadband noise and out of band harmonics generated by

the amplifier. Component values for a 500 MHz acquisition

bandwidth are listed in Table 13. Without this filter, the out

of band noise and distortion components alias back into the

Nyquist band, resulting in a reduction of signal-to-noise ratio.

The design of the filter preceding the ADL5206 amplifier is

more specific to the system rejection requirements for the

acquisition system.

Because of the architecture of the ADL5206, the noise figure

does not degrade significantly for the first 10 dB of gain reduction

from the maximum gain setting. The noise figure increases by

0.5 dB only during the first 10 dB of gain reduction. The noise

figure changes by 7 dB over the 30 dB gain range.

45

40

35

30

REGULAR ATTENUATOR

AMPLIFIER CASCADE

25

20

15

C2A

L1A

L3A

C4

L3B

R1A

R1B

FILTER

AMP

VCM

ADC

10

L1B

C2B

ADL5206

5

AT 700MHz 5V

HIGH PERFORMANCE

0

–10

–5

0

5

10

15

20

25

30 32

Figure 63. ADC Interface (One of Two Channels Shown)

GAIN (dB)

Table 13. Component Values for a 500 MHz Acquisition System

Figure 64. Noise Figure vs. Gain

Component Value

Description/Comments

Amplifier

L1A, L1B

C2A, C2B

½ ADL5206 One channel

22 nH

6.8 pF

Q ≥ 50 at 500 MHz

Final value depends on PCB

parasitics

L3A, L3B

C4

22 nH

1.5 pF

Q ≥ 50 at 500 MHz

Final value depends on PCB

parasitics

R1A, R1B

ADC

10 Ω

½ AD9680

Not applicable

One channel, input impedance set

to 100 Ω

Rev. 0 | Page 24 of 25

Data Sheet

ADL5206

OUTLINE DIMENSIONS

DETAIL A

(JEDEC 95)

4.10

4.00 SQ

3.90

0.30

0.25

0.20

PIN 1

INDICATOR

AREA

PIN 1

NS

INDICATOR AR E A OP TIO

(SEE DETAIL A)

16

20

15

1

0.50

BSC

1.36

1.26

1.16

EXPOSED

PAD

5

11

10

6

0.50

0.45

0.40

TOP VIEW

SIDE VIEW

1.26^{BOTTOM VIEW}

1.16

1.06

0.80

0.75

0.70

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.55

0.050 MAX

0.035 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.203 REF

Figure 65. 20-Lead Lead Frame Chip Scale Package [LFCSP]

4 mm × 4 mm Body and 0.75 mm Package Height

(CP-20-16)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

ADL5206ACPZ-R7 −40°C to +85°C

Temperature Range

Package Description

Package Option

CP-20-16

20-Lead Lead Frame Chip Scale Package [LFCSP]

Evaluation Board

ADL5206ACPZ

−40°C to +85°C

ADL5206-EVALZ

¹Z = RoHS-Compliant Part.

registered trademarks are the property of their respective owners.

D24682-9/20(0)

Rev. 0 | Page 25 of 25


型号：	ADL5206-EVALZ
厂家：	ADI
描述：	1.0 GHz DGA with 30 dB Range and 1 dB Step Size
文件：	总25页 (文件大小：1010K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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