ADL5320-EVALZ [ADI]
400 MHz to 2700 MHz RF Driver Amplifier; 400 MHz至2700 MHz的RF驱动器放大器
| 型号： | ADL5320-EVALZ |
| 厂家： | 
ADI |
| 描述： | 400 MHz to 2700 MHz RF Driver Amplifier |
| 文件： | 总16页 (文件大小：685K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
400 MHz to 2700 MHz
RF Driver Amplifier
ADL5320
FUNCTIONAL BLOCK DIAGRAM
FEATURES
GND
Operation: 400 MHz to 2700 MHz
Gain of 17 dB at 880 MHz
(2)
ADL5320
OIP3 of 45 dBm at 880 MHz
P1dB of 25.4 dBm at 880 MHz
Noise figure: 4 dB at 880 MHz
Power supply: 5 V
Power supply current: 104 mA typical
Internal active biasing
BIAS
1
2
3
RF
GND RF
IN
OUT
Figure 1.
Thermally efficient SOT-89 package
ESD rating of 4 kV (Class 3A)
GENERAL DESCRIPTION
The ADL5320 is a broadband, linear driver RF amplifier that
operates at frequencies from 400 MHz to 2700 MHz. The device
can be used in a wide variety of wired and wireless applications,
including ISM, WLL, PCS, GSM, CDMA, and W-CDMA.
The ADL5320 is fabricated on a GaAs HBT process. The device
is packaged in a low cost SOT-89 that uses an exposed paddle
for excellent thermal impedance. It operates from −40°C to
+85°C, and a fully populated evaluation board is available.
The ADL5320 operates with a 5 V supply voltage and a supply
current of 104 mA.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062−9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
ADL5320
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................7
Basic Layout Connections............................................................. 11
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Typical Scattering Parameters..................................................... 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Soldering Information and Recommended PCB Land
Pattern.......................................................................................... 11
Matching Procedure................................................................... 12
W-CDMA ACPR Performance ................................................ 13
Evaluation Board ............................................................................ 14
Outline Dimensions....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
2/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADL5320
SPECIFICATIONS
VSUP = 5 V and TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
400
16.3
Typ
Max
Unit
OVERALL FUNCTION
Frequency Range
FREQUENCY = 880 MHz
Gain1
vs. Frequency
vs. Temperature
vs. Supply
Output 1 dB Compression Point
Output Third-Order Intercept
Noise Figure
2700
17.5
MHz
16.9
0.3
0.6
0.1
25.4
45
dB
dB
dB
dB
dBm
dBm
dB
50 MHz
−40°C ≤ TA ≤ +85°C
4.75 V to 5.25 V
∆f = 1 MHz, POUT = 10 dBm per tone
4.1
FREQUENCY = 2140 MHz
Gain1
12.4
11.5
4.5
13.2
0.33
0.8
0.06
25.7
42
4.4
14.0
dB
dB
dB
dB
dBm
dBm
dB
vs. Frequency
vs. Temperature
vs. Supply
Output 1 dB Compression Point
Output Third-Order Intercept
Noise Figure
50 MHz
−40°C ≤ TA ≤ +85°C
4.75 V to 5.25 V
∆f = 1 MHz, POUT = 10 dBm per tone
FREQUENCY = 2600 MHz
Gain1
12.5
0.6
1.1
0.1
27.4
37
13.4
dB
dB
dB
dB
dBm
dBm
dB
vs. Frequency
vs. Temperature
vs. Supply
Output 1 dB Compression Point
Output Third-Order Intercept
Noise Figure
100 MHz
−40°C ≤ TA ≤ +85°C
4.75 V to 5.25 V
∆f = 1 MHz, POUT = 10 dBm per tone
Pin RFOUT
5.1
POWER INTERFACE
Supply Voltage
5
5.5
V
Supply Current
vs. Temperature
Power Dissipation
104
6.0
520
124
mA
mA
mW
−40°C ≤ TA ≤ +85°C
VSUP = 5 V
1 Guaranteed maximum and minimum specified limits on this parameter are based on 6 sigma calculations.
Rev. 0 | Page 3 of 16
ADL5320
TYPICAL SCATTERING PARAMETERS
VSUP = 5 V and TA = 25°C; the effects of the test fixture have been de-embedded up to the pins of the device.
Table 2.
S11
S21
S12
S22
Freq (MHz) Magnitude (dB) Angle (°) Magnitude (dB) Angle (°) Magnitude (dB) Angle (°) Magnitude (dB) Angle (°)
400
500
550
600
650
700
750
800
−1.51
−1.38
−1.42
−1.46
−1.46
−1.50
−1.56
−1.61
−1.66
−1.72
−1.85
−1.92
−2.02
−2.20
−2.41
−2.62
−2.87
−3.16
−3.65
−4.09
−4.59
−5.28
−6.09
−6.98
−8.06
−9.38
−11.15
−13.20
−15.83
−19.87
−24.51
−22.66
−18.02
−14.34
−12.10
−10.23
−8.65
−7.90
−6.66
−6.35
−5.77
−5.51
−5.35
−5.15
−5.22
−5.06
164.18
155.33
151.34
147.66
144.12
140.66
137.19
133.97
130.74
127.65
124.15
120.90
117.54
114.21
110.72
107.22
103.77
99.97
96.51
92.23
88.76
84.62
80.71
77.02
72.69
68.92
14.18
14.03
13.79
13.72
13.53
13.45
13.21
13.29
13.04
13.03
12.92
12.93
12.92
12.76
12.97
12.69
12.98
12.87
12.94
12.87
13.04
13.00
12.89
13.13
13.07
13.00
12.97
13.18
13.03
12.84
13.08
12.86
12.88
12.63
12.45
12.65
11.82
11.84
11.55
10.97
10.36
9.65
+128.37
+118.16
+112.76
+108.71
+104.05
+98.89
+95.44
+90.33
+86.67
+81.59
+77.91
+73.13
+68.80
+64.12
+59.95
+54.62
+50.95
+44.96
+40.47
+35.36
+30.47
+24.40
+19.39
+14.80
+7.27
−32.37
−31.75
−31.68
−31.46
−31.56
−31.13
−31.12
−31.00
−30.60
−30.72
−30.31
−30.22
−29.98
−29.80
−29.39
−29.46
−29.03
−28.75
−28.81
−28.26
−28.43
−28.13
−27.96
−27.98
−27.73
−27.49
−27.78
−27.23
−27.36
−27.40
−27.26
−27.33
−27.33
−27.54
−27.77
−27.74
−28.34
−28.62
−28.92
−29.75
−30.13
−30.41
−32.29
−31.60
−33.19
−33.61
+6.77
+1.48
−3.93
−4.60
−6.81
−9.87
−3.44
−3.70
−3.79
−3.83
−3.90
−3.99
−4.02
−4.07
−4.12
−4.21
−4.25
−4.27
−4.32
−4.37
−4.43
−4.42
−4.47
−4.44
−4.45
−4.40
−4.37
−4.29
−4.20
−4.05
−3.88
−3.71
−3.59
−3.29
−3.11
−2.93
−2.69
−2.54
−2.50
−2.35
−2.44
−2.42
−2.43
−2.74
−2.62
−2.94
−3.03
−3.24
−3.41
−3.55
−3.80
−3.93
160.94
156.73
154.66
152.89
151.08
149.38
147.87
146.36
144.94
143.60
142.41
141.31
140.51
139.63
138.68
138.09
137.74
137.08
136.77
136.49
136.43
135.79
135.63
135.39
134.43
133.76
132.94
131.04
129.62
127.46
124.63
122.53
118.78
115.97
112.52
108.19
104.65
100.98
96.52
−11.14
−13.96
−14.90
−17.78
−20.23
−22.21
−24.19
−28.18
−29.56
−33.00
−37.13
−38.18
−44.64
−46.78
−49.56
−56.47
−59.31
−62.71
−69.93
−73.80
−77.79
−85.28
−89.22
−96.30
−102.96
−109.25
−117.37
−124.60
−132.56
−141.32
−149.30
−161.50
−165.89
+179.97
+170.82
+163.00
+152.20
+138.60
+135.12
+120.22
850
900
950
1000
1050
1100
1150
1200
1250
1300
1350
1400
1450
1500
1550
1600
1650
1700
1750
1800
1850
1900
1950
2000
2050
2100
2150
2200
2250
2300
2350
2400
2450
2500
2550
2600
2650
2700
+2.17
−3.27
−9.57
66.21
63.18
63.73
71.29
−17.27
−22.35
−29.10
−36.58
−43.14
−51.83
−55.83
−67.28
−73.99
−79.82
−91.28
−96.39
−108.43
−110.92
−122.10
−130.39
−132.72
−143.64
103.69
156.61
171.65
174.52
172.15
166.81
160.58
153.80
145.88
138.01
128.87
118.44
112.21
99.40
92.52
88.07
83.25
79.98
73.08
69.85
63.87
9.46
7.99
7.70
6.61
92.84
82.21
Rev. 0 | Page 4 of 16
ADL5320
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
ESD CAUTION
Rating
Supply Voltage, VSUP
6.5 V
Input Power (50 Ω Impedance)
Internal Power Dissipation (Paddle Soldered)
θJC (Junction to Paddle)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
20 dBm
683 mW
28.5°C/W
150°C
−40°C to +85°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 5 of 16
ADL5320
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RF
1
2
3
IN
ADL5320
TOP VIEW
(Not to Scale)
GND
(2)
GND
RF
OUT
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
RFIN
GND
RFOUT
RF Input. Requires a dc blocking capacitor.
Ground. Connect to a low impedance ground plane.
RF Output and Supply Voltage. DC bias is provided to this pin through an inductor that is connected
to the external power supply. RF path requires a dc blocking capacitor.
Exposed Paddle
Expose Paddle. Internally connected to GND. Solder to a low impedance ground plane.
Rev. 0 | Page 6 of 16
ADL5320
TYPICAL PERFORMANCE CHARACTERISTICS
50
50
45
40
35
30
25
20
30
OIP3 (10dBm)
OIP3 (–40°C)
45
29
28
27
26
25
24
OIP3 (+25°C)
40
35
30
OIP3 (+85°C)
P1dB
25
20
15
10
5
GAIN
P1dB (–40°C)
P1dB (+25°C)
P1dB (+85°C)
NF
0
800
820
840
860
880
900
920
940
960
800
820
840
860
880
900
920
940
960
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 3. Gain, P1dB, OIP3, and Noise Figure vs. Frequency,
800 MHz to 960 MHz
Figure 6. OIP3 and P1dB vs. Frequency and Temperature,
800 MHz to 960 MHz
19.0
50
930MHz
18.5
18.0
17.5
17.0
16.5
16.0
15.5
15.0
14.5
14.0
880MHz
46
42
38
34
30
–40°C
+25°C
830MHz
+85°C
850MHz
960MHz
–2
0
2
4
6
8
10 12 14 16 18 20 22
(dBm)
800
820
840
860
880
900
920
940
960
FREQUENCY (MHz)
P
OUT
Figure 4. Gain vs. Frequency and Temperature, 800 MHz to 960 MHz
Figure 7. OIP3 vs. POUT and Frequency, 800 MHz to 960 MHz
–25.0
–25.5
–26.0
–26.5
–27.0
–27.5
–28.0
–28.5
–29.0
0
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
–5
S22
–10
–15
–20
–25
–30
–35
–40
+85°C
+25°C
S12
–40°C
S11
700
750
800
850
900
950
1000
700
750
800
850
900
950
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 8. Noise Figure vs. Frequency and Temperature, 800 MHz to 960 MHz
Figure 5. Input Return Loss (S11), Output Return Loss (S22), and Reverse
Isolation (S12) vs. Frequency, 800 MHz to 960 MHz
Rev. 0 | Page 7 of 16
ADL5320
45
40
35
30
25
20
15
10
5
45
43
41
39
37
35
33
31
29
29.0
28.5
28.0
27.5
27.0
26.5
26.0
25.5
25.0
24.5
OIP3 (–40°C)
OIP3 (10dBm)
OIP3 (+85°C)
OIP3 (+25°C)
P1dB
P1dB (–40°C)
P1dB (+25°C)
GAIN
NF
P1dB (+85°C)
0
2060
2080
2100
2120
2140
2160
2180
2200
2220
2060
2080
2100
2120
2140
2160
2180
2200
2220
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 9. Gain, P1dB, OIP3, and Noise Figure vs. Frequency,
2060 MHz to 2200 MHz
Figure 12. OIP3 and P1dB vs. Frequency and Temperature,
2060 MHz to 2200 MHz
16
43
2190MHz
15
41
2140MHz
2060MHz
2090MHz
–40°C
14
39
+25°C
2220MHz
37
13
+85°C
35
33
31
12
11
10
2060
–2
0
2
4
6
8
10 12 14 16 18 20 22
(dBm)
2080
2100
2120
2140
2160
2180
2200
2220
FREQUENCY (MHz)
P
OUT
Figure 10. Gain vs. Frequency and Temperature, 2060 MHz to 2200 MHz
Figure 13. OIP3 vs. POUT and Frequency, 2060 MHz to 2200 MHz
8.0
7.5
7.0
6.5
6.0
–23
–24
–25
–26
–27
–28
–29
0
–5
–10
–15
–20
–25
–30
–35
–40
S22
S11
+85°C
5.5
5.0
+25°C
S12
4.5
4.0
3.5
–40°C
3.0
2.5
2.0
1900
1950
2000 2050
2100
2150
2200
2250
2300
1900
1950
2000 2050
2100 2150
2200
2250
2300
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 14. Noise Figure vs. Frequency and Temperature,
2060 MHz to 2200 MHz
Figure 11. Input Return Loss (S11), Output Return Loss (S22), and Reverse
Isolation (S12) vs. Frequency, 2060 MHz to 2200 MHz
Rev. 0 | Page 8 of 16
ADL5320
40
35
30
25
20
15
10
5
39
38
37
36
35
34
33
32
31
30
29
32
OIP3 (–40°C)
OIP3 (10dBm)
P1dB
31
OIP3 (+25°C)
30
29
28
27
26
25
OIP3 (+85°C)
P1dB (–40°C)
P1dB (+25°C)
GAIN
NF
P1dB (+85°C)
0
2500 2520 2540 2560 2580 2600 2620 2640 2660 2680 2700
2500
2550
2600
2650
2700
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 15. Gain, P1dB, OIP3, and Noise Figure vs. Frequency,
2500 MHz to 2700 MHz
Figure 18. OIP3 and P1dB vs. Frequency and Temperature,
2500 MHz to 2700 MHz
15
46
44
42
40
38
36
34
32
30
14
–40°C
13
+25°C
2600MHz
2700MHz
12
+85°C
11
10
9
2500MHz
2500
2550
2600
2650
2700
–3 –1
1
3
5
7
9
11 13 15 17 19 21 23
(dBm)
FREQUENCY (MHz)
P
OUT
Figure 16. Gain vs. Frequency and Temperature, 2500 MHz to 2700 MHz
Figure 19. OIP3 vs. POUT and Frequency, 2500 MHz to 2700 MHz
–25.0
–25.5
–26.0
–26.5
–27.0
–27.5
–28.0
–28.5
–29.0
–29.5
–30.0
0
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
–5
–10
–15
–20
–25
–30
–35
–40
+85°C
+25°C
–40°C
S22
S11
S12
2400
2450
2500 2550
2600
2650
2700
2750
2800
2400 2450
2500
2550
2600 2650
2700
2750 2800
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 17. Input Return Loss (S11), Output Return Loss (S22), and Reverse
Isolation (S12) vs. Frequency, 2500 MHz to 2700 MHz
Figure 20. Noise Figure vs. Frequency and Temperature,
2500 MHz to 2700 MHz
Rev. 0 | Page 9 of 16
ADL5320
18
16
14
12
10
8
50
40
30
20
10
0
6
4
2
0
42.0
42.8
43.6
44.4
45.2
46.0
46.8
47.6
3.80
3.88
3.96
4.04
4.12
4.20
4.28
OIP3 (dBm)
NF (dB)
Figure 21. OIP3 Distribution at 880 MHz
Figure 24. Noise Figure Distribution at 880 MHz
60
50
40
30
20
10
0
120
115
110
105
100
95
5.25V
5.0V
4.75V
90
85
80
24.4
24.8
25.2
25.6
26.0
26.4
26.8
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
P1dB (dBm)
TEMPERATURE (°C)
Figure 22. P1dB Distribution at 880 MHz
Figure 25. Supply Current vs. Supply Voltage and Temperature (Using
880 MHz Matching Components)
30
25
20
15
10
5
0
16.65
16.75
16.85
16.95
17.05
17.15
17.25
GAIN (dB)
Figure 23. Gain Distribution at 880 MHz
Rev. 0 | Page 10 of 16
ADL5320
BASIC LAYOUT CONNECTIONS
The basic connections for operating the ADL5320 are shown in
Figure 26.
SOLDERING INFORMATION AND RECOMMENDED
PCB LAND PATTERN
Table 5 lists the required matching components. Capacitors C1,
C2, C3, C4, and C7 are Murata GRM155 series (0402 size) and
Inductor L1 is a Coilcraft 0603CS series (0603 size). For all
frequency bands, the placement of C3 and C7 are critical. From
2300 MHz to 2700 MHz, the placement of C2 is also important.
Table 6 lists the recommended component placement for
various frequencies.
Figure 27 shows the recommended land pattern for the ADL5320.
To minimize thermal impedance, the exposed paddle on the
SOT-89 package underside is soldered down to a ground plane
along with Pin 2. If multiple ground layers exist, they should
be stitched together using vias. For more information on land
pattern design and layout, refer to the Application Note AN-772,
A Design and Manufacturing Guide for the Lead Frame Chip
Scale Package (LFCSP).
A 5 V dc bias is supplied through L1 which is connected to
RFOUT (Pin 3). In addition to C4, 10 nF and 10 μF power
supply decoupling capacitors are also required. The typical
current consumption for the ADL5320 is 110 mA.
1.80mm
VSUP
GND
C6 10µF
3.48mm
C5 10nF
1
(2)
ADL5320
2
0.20mm
5.56mm
C4
1
L1
1
C2
0.86mm
0.62mm
1
1
3
RF
RF
C1
2
2
λ4
2
IN
2
OUT
λ3
λ2
λ1
1
1
C7
C3
1.27mm
1
SEE TABLE 5 FOR FREQUENCY SPECIFIC COMPONENTS.
2
SEE TABLE 10 FOR RECOMMENDED COMPONENT SPACING.
1.50mm
3.00mm
Figure 26. Basic Connections
Figure 27. Recommended Land Pattern
Table 5. Recommended Components for Basic Connections
Frequency (MHz)
C1 (pF)
100
47
22
22
22
12
12
C2 (pF)
100
47
22
22
22
2.2
1.0
C3 (pF)
18
6.8
0.5
0.5
0.5
1.2
1.8
C4 (pF)
100
100
22
22
22
C7 (pF)
6.8
2.2
1.5
1.5
1.5
1.0
0.5
L1 (nH)
47
47
15
15
15
15
15
450 to 500
800 to 960
1805 to 1880
1930 to 1990
2110 to 2170
2300 to 2400
2500 to 2700
12
12
Table 6. Matching Component Spacing
Frequency (MHz)
450 to 500
800 to 960
1805 to 2170
λ1 (mils)
λ2 (mils)
λ3 (mils)
364
100
175
125
λ4 (mils)
391
200
300
225
142
75
75
75
75
75
50
350
275
125
75
2300 to 2400
2500 to 2700
89
Rev. 0 | Page 11 of 16
ADL5320
MATCHING PROCEDURE
The ADL5320 is designed to achieve excellent gain and IP3
performance. To achieve this, both input and output matching
networks must present specific impedance to the device. The
matching components listed in Table 6 were chosen to provide
−10 dB input return loss while maximizing OIP3. The load-pull
plots (Figure 28, Figure 29, and Figure 30) show the load
impedance points on the Smith chart where optimum OIP3,
gain, and output power can be achieved. These load impedance
values (that is, the impedance that the device sees when looking
into the output matching network) are listed in Table 7 and
Table 8 for maximum gain and maximum OIP3, respectively.
The contours show how each parameter degrades as it is moved
away from the optimum point.
Figure 28. Load-Pull Contours, 880 MHz
Figure 29. Load-Pull Contours, 2140 MHz
Figure 30. Load-Pull Contours, 2600 MHz
From the data shown in Table 7 and Table 8 it becomes clear that
maximum gain and maximum OIP3 do not occur at the same
impedance. This can also be seen on the load-pull contours in
Figure 28 through Figure 30. Thus, output matching generally
involves compromising between gain and OIP3. In addition,
the load-pull plots demonstrate that the quality of the output
impedance match must be compromised to optimize gain
and/or OIP3. In most applications where line lengths are short
and where the next device in the signal chain presents a low
input return loss, compromising on the output match is
acceptable.
To adjust the output match for operation at a different
frequency or if a different trade-off between OIP3, gain,
and output impedance is desired, the following procedure
is recommended.
For example, to optimize the ADL5320 for optimum OIP3 and
gain at 700 MHz use the following steps:
1. Install the recommended tuning components for a 800 MHz
to 960 MHz tuning band, but do not install C3 and C7.
2. Connect the evaluation board to a vector network analyzer
so that input and output return loss can be viewed simulta-
neously.
3. Starting with the recommended values and positions for
C3 and C7, adjust the positions of these capacitors along
the transmission line until the return loss and gain are
acceptable. Push-down capacitors that are mounted on
small sticks can be used in this case as an alternative to
soldering. If moving the component positions does not
yield satisfactory results, then the values of C3 and C7
should be increased or decreased (most likely increased
in this case as the user is tuning for a lower frequency).
Repeat the process.
4. Once the desired gain and return loss are realized, OIP3
should be measured. Most likely, it will be necessary to
go back and forth between return loss/gain and OIP3
measurements (probably compromising most on output
return loss) until an acceptable compromise is achieved.
Rev. 0 | Page 12 of 16
ADL5320
The ADL5320 achieves an ACPR of −82 dBc at 0 dBm output,
at which point device noise and not distortion is beginning to
dominate the power in the adjacent channels. At an output
power of 10 dBm, ACPR is still very low at −70 dBc making the
device particularly suitable for PA driver applications.
–30
Table 7. Load Conditions for Gain MAX
ΓLoad
Frequency (MHz)
(Magnitude) ΓLoad (°) Gain MAX (dB)
880
2140
2600
0.5147
0.6611
0.5835
159.88
134.40
133.80
17.76
13.78
12.36
–40
–50
–60
–70
–80
–90
Table 8. Load Conditions for IP3 MAX
ΓLoad
Frequency (MHz) (Magnitude) ΓLoad (°) IP3 MAX (dBm)
880
2140
2600
0.4156
0.5035
0.4595
−138.22
+110.27
+102.48
46.29
42.72
43.01
W-CDMA ACPR PERFORMANCE
Figure 31 shows a plot of adjacent channel power ratio (ACPR)
vs. POUT for the ADL5320. The signal type being used is a single
W-CDMA carrier (Test Model 1−64) at 2140 MHz. This signal
is generated by a very low ACPR source. ACPR is measured at
the output by a high dynamic range spectrum analyzer, which
incorporates an instrument noise correction function.
–20
–15
–10
–5
0
5
10
15
20
P
(dBm)
OUT
Figure 31. ACPR vs. POUT, Single Carrier W-CDMA (Test Model 1−64) at 2140
MHz Evaluation Board
Rev. 0 | Page 13 of 16
ADL5320
EVALUATION BOARD
The schematic of the ADL5320 evaluation board is shown in
Figure 32. This evaluation board uses 25 mil wide traces and is
made from FR4 material. The evaluation board comes tuned for
operation in the 1805 MHz to 2140 MHz tuning band. Tuning
options for other frequency bands are also provided in Table 9.
The recommended placement for these components is provided
in Table 10. The inputs and outputs should be ac-coupled with
appropriately sized capacitors. DC bias is provided to the
amplifier via an inductor connected to the RFOUT pin. A bias
voltage of 5 V is recommended.
10uF
10nF
22pF
C1
22pF
C2
22pF
15nH
C3
0.5pF
C7
1.5pF
GND VSUP
C6 10µF
C5 10nF
(2)
C4 22pF
ADL5320
L1
15nH
Figure 33. Evaluation Board Layout and Default Component Placement for
Operation from 1805 MHz to 2170 MHz
C2
22pF
C1
22pF
2
1
3
RF
RF
IN
OUT
λ3
λ4
λ2
λ1
C3
0.5pF
C7
1.5pF
Figure 32. Evaluation Board, 1805 MHz to 2170 MHz
Table 9. Evaluation Board Configuration Options
1805 MHz to
2170 MHz
(Default
2300 MHz to
2400 MHz
2500 MHz to
2700 MHz
Component Function
450 MHz to 500 MHz
800 MHz to 960 MHz Configuration)
C1, C2
AC coupling
capacitors
0402, 100 pF
0402, 47 pF
0402, 22pF
C1= 0402 12 pF
C2 = 0402 2.2 pF
C1 = 0402 12 pF
C2 = 0402 1.0 pF
C4, C5, C6
Power supply
bypassing
capacitors
C4 = 0603 100 pF
C5 = 0603 10 nF
C6 = 1206 10 μF
C4 = 0603 100 pF
C5 = 0603 10 nF
C6 = 1206 10 μF
C4 = 0402 22pF
C5 = 0603 10 nF
C6 = 1206 10 μF
C4 = 0603 12 pF
C5 = 0603 10 nF
C6 = 1206 10 μF
C4 = 0603 12 pF
C5 = 0603 10 nF
C6 = 1206 10 μF
L1
DC bias
inductor
0603, 47 nH
0603, 47 nH
0603, 15 nH
0603, 15 nH
0603, 15 nH
C3, C7
Tuning
capacitors
C3 = 0402 18 pF
C7 = 0402 6.8 pF
C3 = 0402 6.8 pF
C7 = 0402 2.2 pF
C3 = 0402 0.5 pF
C7 = 0402 1.5 pF
C3 = 0402 1.2 pF
C7 = 0402 1.0 pF
C3 = 0402 1.8 pF
C7 = 0402 0.5 pF
R1
R1 = 0402 0 Ω
R1 = 0402 0 Ω
VSUP, GND
Power supply
connections
VSUP red test
loop, GND black test
loop
VSUP red test
loop, GND black test
loop
VSUP red test
loop, GND black
test loop
VSUP red test
loop, GND black
test loop
VSUP red test
loop, GND black
test loop
Table 10. Recommended Component Spacing on Evaluation Board
Frequency (MHz)
λ1 (mils)
λ2 (mils)
λ3 (mils)
λ4 (mils)
50
350
275
125
450 to 500
800 to 960
1805 to 2170
2300 to 2400
2500 to 2700
391
200
300
225
75
75
75
75
75
364
100
175
125
89
142
75
Rev. 0 | Page 14 of 16
ADL5320
10uF
10uF
10nF
10nF
12pF
100pF
C1
100pF
C1
12pF
C2
100pF
15nH
47nH
C3
1.2pF
C7
6.8pF
C3
C7
1pF
R1 0Ω
C2
2.2pF
18pF
Figure 34. Evaluation Board Layout and Component Placement
450 MHz to 500 MHz Operation
Figure 36. Evaluation Board Layout and Component Placement
2300 MHz to 2400 MHz Operation
10uF
10nF
10uF
10nF
100pF
12pF
C1
47pF
C2
47pF
C1
12pF
15nH
47nH
C7
2.2pF
C2
1.0pF
C3
6.8pF
R1 0Ω
C3
1.8pF
C7
0.5pF
Figure 35. Evaluation Board Layout and Component Placement
800 MHz to 960 MHz Operation
Figure 37. Evaluation Board Layout and Component Placement
2500 MHz to 2700 MHz Operation
Rev. 0 | Page 15 of 16
ADL5320
OUTLINE DIMENSIONS
*
1.55 REF
(2)
2
4.25
3.94
2.60
2.30
1
3
1.20
1.50 TYP
0.90
3.00 TYP
4.60
4.40
1.60
1.40
0.44
0.35
END VIEW
*
0.58
0.40
*
0.52
0.32
*
COMPLIANT TO JEDEC STANDARDS TO-243 WITH
EXCEPTION TO DIMENSIONS INDICATED BY AN ASTERISK.
Figure 38. 3−Lead Small Outline Transistor Package [SOT-89]
(RK-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADL5320ARKZ-R71
ADL5320-EVALZ1
Temperature Range
−40°C to +85°C
Package Description
Package Option
3-Lead SOT-89, 7“ Tape and Reel
Evaluation Board
RK-3
1 Z = RoHS Compliant Part.
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05840-0-2/08(0)
Rev. 0 | Page 16 of 16
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