ADL5566-EVALZ_技术文档

4.5 GHz Ultrahigh Dynamic Range,

Dual Differential Amplifier

Data Sheet

ADL5566

FEATURES

FUNCTIONAL BLOCK DIAGRAM

VCC1/VCC2

ENBL1

−3 dB bandwidth of 4.5 GHz (A_V= 16 dB)

Fixed 16 dB gain

Channel-to-channel gain error: 0.1 dB at 100 MHz

Channel-to-channel phase error: 0.06° at 100 MHz

Differential or single-ended input to differential output

I/O dc-coupled or ac-coupled

Low noise input stage: 1.3 nV/√Hz RTI at A_V= 16 dB

Low broadband distortion (A_V= 16 dB), supply = 5 V

10 MHz: −103 dBc (HD2), −107 dBc (HD3)

100 MHz: −95 dBc (HD2), −100 dBc (HD3)

200 MHz: −94.5 dBc (HD2), −87 dBc (HD3)

500 MHz: −83 dBc (HD2), −64 dBc (HD3)

IMD3 of −95 dBc at 200 MHz center

R

F

VON1

R

G

VIP1

VIN1

VCOM1

G

VOP1

R

F

Maintains low single-ended distortion performance out to

500 MHz

F

Slew rate: 16 V/ns

VON2

Maintains low distortion down to 1.2 V VCOM

Fixed 16 dB gain can be reduced by adding external resistors

Fast settling and overdrive recovery of 2.5 ns

Single-supply operation: 2.8 V to 5.2 V

Power-down

R

G

VIP2

VIN2

VCOM2

G

VOP2

Low dc power consumption, 462 mW at 3.3 V supply

R

APPLICATIONS

F

Differential ADC drivers

Single-ended to differential conversion

RF/IF gain blocks

ADL5566

GND

ENBL2

Figure 1.

SAW filter interfacing

GENERAL DESCRIPTION

The ADL5566 is a high performance, dual differential amplifier

optimized for IF and dc applications. The amplifier offers low

noise of 1.3 nV/√Hz and excellent distortion performance over

a wide frequency range, making it an ideal driver for high speed

16-bit analog-to-digital converters (ADCs). The ADL5566 is

ideally suited for use in high performance, zero IF/complex

IF receiver designs. In addition, this device has excellent low

distortion for single-ended input drive applications.

The quiescent current of the ADL5566, using a 3.3 V supply, is

typically 70 mA per amplifier. When disabled, it consumes less

than 3.5 mA per amplifier and has −25 dB of input to output

isolation at 100 MHz.

The device is optimized for wideband, low distortion, and noise

performance, giving it unprecedented performance for overall

spurious-free dynamic range (SFDR). These attributes, together

with the adjustable gain capability, make this device the amplifier of

choice for driving a wide variety of ADCs, mixers, pin diode

attenuators, SAW filters, and multi-element discrete devices.

The ADL5566 provides a gain of 16 dB. For the single-ended input

configuration, the gain is reduced to 14 dB. Using two external

series resistors for each amplifier expands the gain flexibility of

the amplifier and allows for any gain selection from 0 dB to 16 dB

for a differential input and 0 dB to 14 dB for a single-ended input.

In addition, this device maintains low distortion down to output

(VOCM) levels of 1.2 V providing an added capability for driving

CMOS ADCs at ac levels up to 2 V p-p.

Fabricated on an Analog Devices, Inc., high speed SiGe process, the

ADL5566 is supplied in a compact 4 mm × 4 mm, 24-lead LFCSP

package and operates over the −40°C to +85°C temperature range.

Rev. C

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

ADL5566

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications Information.............................................................. 15

Basic Connections...................................................................... 15

Input and Output Interfacing ................................................... 16

Gain Adjustment and Interfacing ............................................ 16

ADC Interfacing......................................................................... 18

DC-Coupled Receiver Application.......................................... 18

Layout Considerations............................................................... 19

Soldering Information and Recommended Land Pattern.... 21

Evaluation Board........................................................................ 21

Outline Dimensions....................................................................... 24

Ordering Guide .......................................................................... 24

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Circuit Description......................................................................... 14

REVISION HISTORY

8/2019—Rev. B to Rev. C

12/2013—Rev. 0 to Rev. A

Changes to Figure 36...................................................................... 15

Changes to Figure 48...................................................................... 19

Updated Outline Dimensions....................................................... 24

Changes to Ordering Guide .......................................................... 24

Changes to ENBL1/ENBL2 Threshold Parameter, Table 1..........3

Change to Table 2 ..............................................................................6

11/2012—Revision 0: Initial Version

4/2019—Rev. A to Rev. B

Changes to Figure 26...................................................................... 11

Updated Outline Dimensions....................................................... 24

Rev. C | Page 2 of 24

Data Sheet

ADL5566

SPECIFICATIONS

V_S= 3.3 V, V_CM= 1.65 V, V_S= 5 V, V_CM= 2.5 V, R_L= 200 Ω differential, A_V= 16 dB, C_L= 1 pF differential, f = 100 MHz, T_A= 25°C,

parameters specified as ac-coupled differential input and differential output, unless otherwise noted.

Table 1.

Test Conditions/

Comments

3.3 V

Typ

5 V

Parameter

Min

Max Min

Typ

Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth

Bandwidth 0.1 dB Flatness

Gain Accuracy

A_V= 16 dB, V_OUT≤ 0.5 V p-p

V_OUT≤ 1.0 V p-p

4500

500

1

4500

500

1

MHz

dB

Gain Error

≤1000 MHz, Channel A to

Channel B

≤0.02

dB

Phase Error

≤1000 MHz, Channel A to

Channel B

≤0.5

Degrees

Gain Supply Sensitivity

Gain Temperature Sensitivity

Slew Rate

V_S5%

−40°C to +85°C

Rise, A_V= 16 dB, R_L= 200 Ω,

V_OUT= 2 V step

3.4

0.5

16

5.6

0.5

18

mdB/V

mdB/°C

V/ns

Fall, A_V= 16 dB, R_L= 200 Ω,

18

20

V/ns

V_OUT= 2 V step

Settling Time

Overdrive Recovery Time

2 V step to 1%

V_IN= 4 V to 0 V step,

890

2.5

750

2.5

ps

ns

V_OUT

≤ 10 mV

Reverse Isolation (S12)

Channel Isolation

75

82.5

75

82.5

dB

Channel A to Channel B

A_V= 16 dB

INPUT/OUTPUT CHARACTERISTICS

Input Common-Mode Range

Input Resistance (Differential)

Input Resistance (Single-Ended)

Input Capacitance (Single-Ended)

Input Bias Current

1.2

1.8

1.3

3.5

V

Ω

pF

A_V= 16 dB

A_V= 14 dB

160

150

1.1

5

160

150

1.1

5

µA

CMRR

44

dB

Output Common-Mode Range

Output Common-Mode Offset

Output Common-Mode Drift

Output Differential Offset Voltage

Output Differential Offset Drift

Output Resistance (Differential)

Maximum Output Voltage Swing

POWER INTERFACE

1.25

−100

1.8

+20

1.25

−100

3

+20

V

Referenced to VCC/2

−40°C to +85°C

mV

mV/°C

mV

mV/°C

Ω

2

3.5

−20

+20

−20

+20

−40°C to +85°C

1.1

11

3.4

1.7

11

5

1 dB compressed

V p-p

Supply Voltage

ENBL1/ENBL2 Threshold

2.8

3.3

5.2

0.5

2.8

1.5

5

5.2

0.6

V

nA

µA

mA

Device disabled, ENBL low

Device enabled, ENBL high 1.5

ENBL high

ENBL1/ENBL2 Input Bias Current

Quiescent Current

500

−165

140

7

500

−165

160

9

ENBL low

ENBL high

ENBL low

150

175

Rev. C | Page 3 of 24

ADL5566

Data Sheet

Test Conditions/

Comments

3.3 V

Typ

5 V

Parameter

Min

Max Min

Typ

Max Unit

NOISE/HARMONIC PERFORMANCE

10 MHz

Second/Third Harmonic

Distortion (HD2/HD3)

Output IP3/Third-Order

Intermodulation

A_V= 16 dB, R_L= 200 Ω,

−99.1/−111

−103.1/−107.3

+49.4/−101.8

dBc

V

_OUT= 2 V p-p

A_V= 16 dB, R_L= 200 Ω,

_OUT= 2 V p-p composite

+50.2/−103.3

dBm/dBc

V

Distortion (OIP3/IMD3)

(2 MHz spacing)

Output IP2 Second-Order

Intermodulation

A_V= 16 dB, R_L= 200 Ω,

dBm/dBc

+90.8/−92.1

+91.2/−92.5

V

_OUT= 2 V p-p composite

Distortion (OIP2/IMD2)

(2 MHz spacing)

1 dB Compression Point, RTO

(OP1dB)

Noise Spectral Density,

RTI (NSD)

Noise Figure (NF)

100 MHz

A_V= 16 dB

14

17.7

1.32

6.66

dBm

nV/√Hz

dB

A_V= 16 dB

1.28

6.47

Second/Third Harmonic

Distortion (HD2/HD3)

Output IP3/Third-Order

Intermodulation

A_V= 16 dB, R_L= 200 Ω,

−89/−92.1

−94.7/−100

dBc

V

_OUT= 2 V p-p

A_V= 16 dB, R_L= 200 Ω,

_OUT= 2 V p-p composite

+49.4/−101.9

+50.9/−104.7

dBm/dBc

V

Distortion (OIP3/IMD3)

(2 MHz spacing)

Output IP2 Second-Order

Intermodulation

A_V= 16 dB, R_L= 200 Ω,

+96.9/−98.2

+98.9/−100.2

dBm/dBc

V

_OUT= 2 V p-p composite

Distortion (OIP2/IMD2)

(2 MHz spacing)

1 dB Compression Point, RTO

(OP1dB)

Noise Spectral Density,

RTI (NSD)

Noise Figure (NF)

200 MHz

A_V= 16 dB

14.2

1.26

6.36

17.8

1.3

dBm

nV/√Hz

dB

A_V= 16 dB

6.58

Second/Third Harmonic

Distortion (HD2/HD3)

Output IP3/Third-Order

Intermodulation

A_V= 16 dB, R_L= 200 Ω,

−92.7/−80.2

+45.9/−94.7

−94.5/−87.2

+46/−95

dBc

V

_OUT= 2 V p-p

A_V= 16 dB, R_L= 200 Ω,

_OUT= 2 V p-p composite

dBm/dBc

V

Distortion (OIP3/IMD3)

(2 MHz spacing)

Output IP2 Second-Order

Intermodulation

A_V= 16 dB, R_L= 200 Ω,

+80.4/−81.7

+82.6/−83.9

dBm/dBc

V

_OUT= 2 V p-p composite

Distortion (OIP2/IMD2)

(2 MHz spacing)

1 dB Compression Point, RTO

(OP1dB)

Noise Spectral Density,

RTI (NSD)

Noise Figure (NF)

500 MHz

A_V= 16 dB

14.1

1.25

6.31

17.7

1.28

6.48

dBm

nV/√Hz

dB

A_V= 16 dB

Second/Third Harmonic

Distortion (HD2/HD3)

Output IP3/Third-Order

Intermodulation

A_V= 16 dB, R_L= 200 Ω,

−82.6/−60.5

+30.7/−64.7

−82.8/−64.2

+32.4/−67.8

dBc

V

_OUT= 2 V p-p

A_V= 16 dB, R_L= 200 Ω,

_OUT= 2 V p-p composite

dBm/dBc

V

Distortion (OIP3/IMD3)

(2 MHz spacing)

Output IP2 Second-Order

Intermodulation

A_V= 16 dB, R_L= 200 Ω,

+74.2/−75.5

+75.8/−77.1

dBm/dBc

V

_OUT= 2 V p-p composite

Distortion (OIP2/IMD2)

(2 MHz spacing)

Noise Spectral Density,

RTI (NSD)

Noise Figure (NF)

A_V= 16 dB

1.32

6.64

1.35

6.83

nV/√Hz

dB

A_V= 16 dB

Rev. C | Page 4 of 24

Data Sheet

ADL5566

Test Conditions/

Comments

3.3 V

Typ

5 V

Parameter

Min

Max Min

Typ

Max Unit

1000 MHz

Second/Third Harmonic

Distortion (HD2/HD3)

Output IP3/Third-Order

Intermodulation

A_V= 16 dB, R_L= 200 Ω,

−57.6/−43

−57.1/−45.9

+24.8/−52.6

dBc

V

_OUT= 2 V p-p

A_V= 16 dB, R_L= 200 Ω,

_OUT= 2 V p-p composite

+23.2/−49.4

dBm/dBc

V

Distortion (OIP3/IMD3)

(2 MHz spacing)

Output IP2 Second-Order

Intermodulation

A_V= 16 dB, R_L= 200 Ω,

+56.1/−57.4

+55.9/−57.2

dBm/dBc

V

_OUT= 2 V p-p composite

Distortion (OIP2/IMD2)

(2 MHz spacing)

Noise Spectral Density,

RTI (NSD)

Noise Figure (NF)

A_V= 16 dB

1.93

9.45

1.99

9.66

nV/√Hz

dB

A_V= 16 dB

Rev. C | Page 5 of 24

ADL5566

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 2.

THERMAL RESISTANCE

Table 3 lists the junction to air thermal resistance (θ_JA) and the

junction to paddle thermal resistance (θ_JC) for the ADL5566.

Parameter

Rating

Output Voltage Swing × Bandwidth Product 2300 V p-p MHz

Supply Voltage, V_CC

VIPx, VINx

I_OUTMaximum

Internal Power Dissipation

Maximum Junction Temperature

Operating Temperature Range

Storage Temperature Range

5.25 V

V_CC+ 0.5 V

30 mꢀ

900 mW

135°C

Table 3. Thermal Resistance

Package Type

1

2

θ_JA

34.0

θ_JC

1.8

Unit

24-Lead LFCSP

°C/W

¹Measured on ꢀnalog Devices evaluation board. For more information about

board layout, see the Soldering Information and Recommended Land Pattern

section.

−40°C to +105°C

−65°C to +150°C

²Based on simulation with JEDEC standard JESD51.

ESD CAUTION

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Rev. C | Page 6 of 24

Data Sheet

ADL5566

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

18

VON1

VIN1

VIP1

NC

17 VOP1

16

NC

ADL5566

TOP VIEW

15

NC

VIP2

VIN2

14

VOP2

13 VON2

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

2. THE EXPOSED PADDLE IS INTERNALLY CONNECTED TO

GND AND MUST BE SOLDERED TO A LOW IMPEDANCE

GROUND PLANE.

Figure 2. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic Description

1

2

VIN1

VIP1

NC

Balanced Differential Input for Amplifier 1. Biased to V_CC/2, typically ac-coupled. Input for A_V= 16 dB.

No Connect. Do not connect to this pin. Solder to ground.

3, 4, 7, 8, 12, 15,

16, 19, 23, 24

5

6

9

10

VIP2

VIN2

ENBL2

VCOM2

Balanced Differential Input for Amplifier 2. Biased to V_CC/2, typically ac-coupled. Input for A_V= 16 dB.

Enable for Amplifier 2. Apply positive voltage (1.3 V < ENBL2 < VCC2) to activate device.

Common-Mode Voltage. A voltage applied to this pin sets the common-mode voltage of the inputs and

outputs of Amplifier 2. If left open, VCOM2 = V_CC/2. Typically, it is decoupled to ground with a 0.1 µF

capacitor.

11

13

14

17

18

20

21

VCC2

VON2

VOP2

VOP1

VON1

VCC1

VCOM1

Positive Supply for Amplifier 2.

Balanced Differential Output for Amplifier 2. Biased to V_CC/2, typically ac-coupled.

Balanced Differential Output for Amplifier 1. Biased to V_CC/2, typically ac-coupled.

Positive Supply for Amplifier 1.

Common-Mode Voltage. A voltage applied to this pin sets the common-mode voltage of the inputs and

outputs of Amplifier 1. If left open, VCOM1 = V_CC/2. Typically, it is decoupled to ground with a 0.1 µF

capacitor.

22

ENBL1

EP

Enable for Amplifier 1. Apply positive voltage (1.3 V < ENBL1 < VCC1) to activate device.

The exposed paddle is internally connected to GND and must be soldered to a low impedance ground plane.

Rev. C | Page 7 of 24

ADL5566

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

V_S= 3.3 V, V_CM= 1.65 V, R_L= 200 Ω differential, A_V= 16 dB, C_L= 1 pF differential, f = 100 MHz, T_A= 25°C, parameters specified as

ac-coupled differential input and differential output, unless otherwise noted.

25

20

15

10

5

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.07

0.06

0.05

0.04

0.03

0.02

0.01

0

3.3V, 25°C

5V, 25°C

SDD21 PHASE

SDD21 MAG

0

–5

–10

–15

10M

100M

FREQUENCY (Hz)

1G

10

100

1000

FREQUENCY (MHz)

Figure 3. Gain vs. Frequency Response for 200 Ω Differential Load,

_POS= 3.3 V and V_POS= 5 V, 25°C

Figure 6. Channel-to-Channel Gain Error and Phase Error vs. Frequency

V

25

20

15

10

5

25

3.3V, –40°C

3.3V, +25°C

3.3V, +85°C

3.3V, +105°C

20

15

10

0

5V, +25°C

5V, –40°C

5V, +85°C

5V, +105°C

3.3V, +25°C

3.3V, –40°C

3.3V, +85°C

3.3V, +105°C

–5

–10

–15

5

0

10M

100M

FREQUENCY (Hz)

1G

0

50

100

150

200

250

FREQUENCY (MHz)

Figure 4. Gain vs. Frequency Response for 200 Ω Differential Load,

Four Temperatures, V_POS= 3.3 V

Figure 7. OP1dB vs. Frequency for 200 Ω Differential Load, Four

Temperatures, V_POS= 3.3 V, V_POS= 5 V

25

10.0

5V, –40°C

3.3V SUPPLY

5V SUPPLY

5V, +25°C

9.5

9.0

8.5

8.0

7.5

7.0

6.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

5V, +85°C

5V, +105°C

20

15

10

5

0

–5

–10

–15

10M

100M

FREQUENCY (Hz)

1G

10M

100M

1G

FREQUENCY (Hz)

Figure 5. Gain vs. Frequency Response for 200 Ω Differential Load,

Four Temperatures, V_POS= 5 V

Figure 8. Noise Figure vs. Frequency at V_POS= 3.3 V, V_POS= 5 V, 25°C

Rev. C | Page 8 of 24

Data Sheet

ADL5566

3.00

60

50

40

30

20

10

0

3.3V SUPPLY

5V SUPPLY

2.75

2.50

2.25

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0

OIP3, 5V, 25°C

OIP3, 3.3V, 25°C

10M

100M

1G

–6 –5 –4 –3 –2 –1

0

1

2

3

4

5

6

7

8

9

10

FREQUENCY (Hz)

P

/TONE (dBm)

OUT

Figure 9. Noise Spectral Density vs. Frequency at V_POS= 3.3 V and V_POS= 5 V

Figure 12. OIP3 vs. Output Power (P_OUT) per Tone, Frequency 200 MHz,

_POS= 3.3 V and V_POS= 5 V

V

60

0

IMD3, 3.3V, +25°C, 2V p-p

IMD3, 5V, +25°C, 2V p-p

IMD3, 3.3V, +85°C, 2V p-p

IMD3,5V, +85°C, 2V p-p

IMD3, 3.3V, –40°C, 2V p-p

IMD3, 5V, –40°C, 2V p-p

IMD3, 3.3V, +105°C, 2V p-p

IMD3, 5V, +105°C, 2V p-p

IMD3, 3.3V, +25°C, 1V p-p

IMD3, 5V, +25°C, 1V p-p

IMD3, 3.3V, +85°C, 1V p-p

IMD3, 5V, +85°C, 1V p-p

IMD3, 3.3V, –40°C, 1V p-p

IMD3, 5V, –40°C, 1V p-p

IMD3, 3.3V, +105°C, 1V p-p

IMD3, 5V, +105°C, 1V p-p

OIP3, 3.3V, 25°C, 2V p-p

OIP3, 5V, 25°C, 2V p-p

OIP3, 3.3V, 25°C, 1V p-p

50

–20

OIP3, 5V, 25°C, 1V p-p

40

30

20

10

0

–40

–60

–80

–100

–120

0

100 200 300 400 500 600 700 800 900 1000

FREQUENCY (MHz)

0

100 200 300 400 500 600 700 800 900 1000

FREQUENCY (MHz)

Figure 10. Output Third-Order Intercept (OIP3) at Output Level at 2 V p-p

Composite, R_L= 200 Ω, V_POS= 3.3 V and V_POS= 5 V

Figure 13. IMD3 vs. Frequency, Over Temperature, Output Level at

2 V p-p Composite, R_L= 200 Ω, V_POS= 3.3 V and V_POS= 5 V

60

50

40

30

–20

–30

–40

–50

–60

–70

5V

SUPPLY

3.3V

SUPPLY

–80

20

10

0

OIP3, 3.3V, +25°C, 2V p-p

OIP3, 5V, +25°C, 2V p-p

OIP3, 3.3V, +85°C, 2V p-p

OIP3, 5V, +85°C, 2V p-p

OIP3, 3.3V, –40°C, 2V p-p

OIP3, 5V, –40°C, 2V p-p

OIP3, 3.3V, +105°C, 2V p-p

OIP3, 5V, +105°C, 2V p-p

OIP3, 3.3V, +25°C, 1V p-p

OIP3, 5V, +25°C, 1V p-p

OIP3, 3.3V, +85°C, 1V p-p

OIP3, 5V, +85°C, 1V p-p

OIP3, 3.3V, –40°C, 1V p-p

OIP3, 5V, –40°C, 1V p-p

OIP3, 3.3V, +105°C, 1V p-p

OIP3, 5V, +105°C, 1V p-p

–90

–100

–110

–120

0

100 200 300 400 500 600 700 800 900 1000

FREQUENCY (MHz)

0

0.5

1.0

1.5

2.0

VCOM (V)

2.5

3.0

3.5

4.0

Figure 11. OIP3 vs. Frequency, Overtemperature, Output Level at 2 V p-p

Composite, R_L= 200 Ω, V_POS= 3.3 V and V_POS= 5 V

Figure 14. IMD3 vs. VCOM, Output Level at 2 V p-p Composite, R_L= 200 Ω,

_POS= 3.3 V and V_POS= 5 V, Frequency = 100 MHz

V

Rev. C | Page 9 of 24

ADL5566

Data Sheet

–50

0

–20

–40

IMD3 100Ω LOAD

IMD3 150Ω LOAD

IMD3 200Ω LOAD

HD3, 5V, 25°C, 1V p-p

HD3, 3.3V, 25°C, 2V p-p

HD3, 5V, 25°C, 2V p-p

HD3, 3.3V, 25°C, 1V p-p

–55

–60

–65

–70

–80

–40

–75

–80

–85

–100

–120

–140

–60

–90

–95

–80

–100

–105

–110

–115

–120

–100

–120

HD2, 3.3V, 25°C, 2V p-p

HD2, 5V, 25°C, 2V p-p

HD2, 3.3V, 25°C, 1V p-p

HD2, 5V, 25°C, 1V p-p

–160

0

50

100 150 200 250 300 350 400 450 500

FREQUENCY (MHz)

0

100 200 300 400 500 600 700 800 900 1000

FREQUENCY (MHz)

Figure 18. Harmonic Distortion (HD2/HD3) vs. Frequency,

Output Level at 2 V p-p Composite, R_L= 200 Ω, V_POS= 3.3 V and V_POS= 5 V

Figure 15. IMD3 vs. Frequency, R_L= 100 Ω, R_L= 150 Ω, and R_L= 200 Ω, V_POS= 3.3 V,

Input Common-Mode = 1.65 V, Output Common-Mode = 1.25 V, V_OUT= 1.5 V p-p

0

–40

60

55

50

45

40

35

30

25

20

HD2, 3.3V, +25°C

HD2, 3.3V, +85°C

HD2, 3.3V, –40°C

HD2, 3.3V, +105°C

HD2, 5V, +25°C

HD2, 5V, +85°C

HD2, 5V, –40°C

HD2, 5V, +105°C

–20

–60

–80

–40

–100

–120

–140

–160

–60

–80

–100

–120

HD3, 3.3V, +25°C

HD3, 5V, +25°C

HD3, 5V, +85°C

HD3, 5V, –40°C

HD3, 5V, +105°C

HD3, 3.3V, +85°C

HD3, 3.3V, –40°C

HD3, 3.3V, +105°C

0

50

100 150 200 250 300 350 400 450 500

FREQUENCY (MHz)

0

50

100 150 200 250 300 350 400 450 500

FREQUENCY (MHz)

Figure 19. Harmonic Distortion (HD2/HD3) vs. Frequency,

Output Level at 2 V p-p Composite, R_L= 200 Ω, V_POS= 3.3 V and V_POS= 5 V

Figure 16. Single-Ended OIP3 vs. Frequency, V_POS= 3.3 V,

2 V p-p Composite Output, R_L= 200 Ω

–60

0

120

100

80

60

40

20

0

3.3V, HD2, 25°C

5V, HD2, 25°C

3.3V OIP2

5V OIP2

3.3V IMD2

5V IMD2

–20

–40

–60

–80

–100

–120

–80

–20

–40

–60

–80

–100

–120

–100

–120

–140

–160

–180

3.3V, HD3, 25°C

5V, HD3, 25°C

–2

0

2

4

6

8

10

0

100 200 300 400 500 600 700 800 900 1000

P

/TONE (dBm)

OUT

FREQUENCY (MHz)

Figure 17. OIP2/IMD2 vs. Frequency

Figure 20. Harmonic Distortion (HD2/HD3) vs. Output Power (P_OUT) per Tone,

Frequency = 200 MHz, R_L= 200 Ω, V_POS= 3.3 V and V_POS= 5 V

Rev. C | Page 10 of 24

Data Sheet

ADL5566

–60

–65

0

HD2 AT 3.3V

HD3 AT 3.3V

HD2 AT 5.0V

HD3 AT 5.0V

HD2, 3.3V

HD3, 3.3V

HD2, 5V

HD3, 5V

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–70

–75

–80

–85

–90

–95

–100

–105

–110

0

100

200

300

400

500

0.5

1.0

1.5

2.0

2.5

3.0

FREQUENCY (MHz)

VCOM (V)

Figure 21. Harmonic Distortion (HD2/HD3) vs. VCOM, Output Level at

2 V p-p, R_L= 200 Ω, V_POS= 3.3 V and V_POS= 5 V, Frequency = 100 MHz

Figure 24. Single-Ended Harmonic Distortion (HD2/HD3) vs. Frequency,

V_POS= 3.3 V and V_POS= 5 V, V_OUT= 2 V p-p, R_L= 200 Ω

–50

–80

–85

–90

HD2 100Ω LOAD

HD2 200Ω LOAD

–55

–60

–65

–70

–75

HD2

–95

–100

–105

–110

–115

–120

–80

IMD3

–85

–90

–95

HD3

–100

–105

–110

–115

–120

0

50

100 150 200 250 300 350 400 450 500

FREQUENCY (MHz)

0

1

2

3

4

5

6

FREQUENCY (MHz)

Figure 22. HD2 vs. Frequency, R_L= 100 Ω and R_L= 200 Ω, V_POS= 3.3 V, Input

Common-Mode = 1.65 V, Output Common-Mode = 1.25 V, V_OUT= 1.5 V p-p

Figure 25. Low Frequency Distortion (HD2/HD3/IMD3) vs. Frequency,

Output Level at 2 V p-p, R_L= 200 Ω, V_POS= 3.3 V

–50

HD3 200Ω LOAD

HD3 100Ω LOAD

–55

–60

–65

–70

–75

–80

–85

3

–90

–95

–100

–105

–110

–115

–120

2

2ns/DIV

0

50

100 150 200 250 300 350 400 450 500

FREQUENCY (MHz)

CH2 100mV/DIV 50Ω

CH3 500mV/DIV 50Ω

8G

A CH3

1.1V

Figure 23. HD3 vs. Frequency, R_L= 100 Ω and R_L= 200 Ω, V_POS= 3.3 V, Input

Common-Mode = 1.65 V, Output Common-Mode = 1.25 V, V_OUT= 1.5 V p-p

Figure 26. ENBLx Time Domain Response, V_POS= 3.3 V

Rev. C | Page 11 of 24

ADL5566

Data Sheet

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

1

CH1 400mV 2ns

A CH1

0V

10

100

1000

FREQUENCY (MHz)

Figure 30. Reverse Isolation (S12) vs. Frequency

Figure 27. Large Signal Pulse Response Using a Slow Transient Signal

Generator, 4 V p-p, V_POS= 3.3 V

60

55

50

45

40

35

30

25

20

15

10

5

220

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

RESITANCE

CAPACITANCE

210

200

190

180

170

160

150

140

130

120

0

10

100

1000

100

1000

FREQUENCY (MHz)

Figure 31. S11 Equivalent RLC Parallel Network

Figure 28. Common-Mode Rejection Ratio (CMRR) vs. Frequency

20

18

16

14

12

10

8

10

9

8

7

6

5

4

3

2

1

0

1000

900

800

700

600

500

400

300

200

100

0

RESISTANCE

CAPACITANCE

6

4

2

0

10

100

1000

0

100 200 300 400 500 600 700 800 900 1000

FREQUENCY (MHz)

Figure 32. S22 Equivalent RLC Parallel Network

Figure 29. Group Delay vs. Frequency

Rev. C | Page 12 of 24

Data Sheet

ADL5566

0

–5

85

80

75

70

65

60

–10

–15

–20

–25

–30

–35

–40

–45

–50

–55

–60

–65

–70

–75

–80

–85

–90

–95

5V

3.3V

–100

10M

100M

FREQUENCY (Hz)

1G

10G

–40

–20

0

20

40

60

80

100

TEMPERATURE (°C)

Figure 33. Output Referred Crosstalk, Channel A to Channel B, V_POS= 3.3 V,

VCOM = 1.65 V

Figure 34. I_SUPPLYvs. Temperature, R_L= 200 Ω, V_POS= 3.3 V and V_POS= 5 V

Rev. C | Page 13 of 24

ADL5566

Data Sheet

CIRCUIT DESCRIPTION

The ADL5566 is a high gain, fully differential dual amplifier/ADC

driver that uses a 2.8 V to 5 V supply. It provides a 16 dB gain

that can be reduced by adding external series resistors. The 3 dB

bandwidth is 4.5 GHz, and it has a differential input impedance of

160 Ω. It has a differential output impedance of 10 ꢀ and an

output common-mode adjust voltage of 1.1 V to 1.8 V.

product that results in distortion levels that are the best in the

industry for power consumed at frequencies beyond 100 MHz.

This amplifier achieves greater than −69 dBc IMD3 at 500 MHz

and −100 dBc at 200 MHz for 2 V p-p operation. In addition,

the ADL5566 can also deliver 5 V p-p operation under heavy

loads. The internal gain is set at 16 dB, and the part has a noise

figure of 6.5 dB and a RTI of 1.5 nV/√Hz. When comparing noise

figure and distortion performance, this amplifier delivers the

best in category spurious-free dynamic range (SFDR).

500Ω

80Ω

5Ω

0.1µF

The ADL5566 is very flexible in terms of I/O coupling. It can be

ac- or dc-coupled. For dc coupling, the output common-mode

voltage (VCOMx) can be adjusted (using the VCOMx pin) from

1.1 V to 1.8 V output for VCCx at 3.3 V and up to 3 V with VCCx

at 5 V. For the best distortion, the common-mode output should

not go below 1.25 V at VCCx equal to 3.3 V and 1.35 V for 5 V

VCCx operation. Note that the input common-mode voltage

slaves to the VCOMx output voltage when ac-coupled at the

inputs. For dc-coupled inputs, the input common-mode voltage

should also stay between 1.25 V and 1.8 V for a 3.3 V supply and

1.35 V to 3.5 V for a 5 V supply. Note again that, for ac-coupled

applications with series capacitors at the inputs, as in Figure 37,

the output common-mode voltage, VCOMx, sets the common-

mode input to the same level. Because of the wide input common-

mode range, this part can easily be dc-coupled to many types of

mixers, demodulators, and amplifiers. Forcing a higher input

VCOMx does not affect the output VCOMx in dc-coupled mode.

Note that, if the outputs are ac-coupled (see the ADC Interfacing

section), no external VCOMx adjust is required because the

amplifier common-mode outputs are set at VCCx/2.

+

0.1µF

RL

½ R

AC

S

½

ADL5566

–

½ R

S

0.1µF

500Ω

Figure 35. Basic Structure

The ADL5566 is composed of a dual fully differential amplifier

with on-chip feedback and feed-forward resistors. The gain is fixed

at 16 dB but can be reduced by adding two resistors in series with

the two inputs (see the Gain Adjustment and Interfacing section).

The amplifier is designed to provide a high differential open-loop

gain and has an output common-mode circuit that enables the

user to change the output common-mode voltage by applying a

voltage to a VCOMx pin. The amplifier is designed to provide

superior low distortion at frequencies to and beyond 300 MHz

with low noise and low power consumption. The low distortion

and noise are realized with a 3.3 V power supply at 140 mA.

The dual amplifier has an extremely high gain bandwidth (GBW)

Rev. C | Page 14 of 24

Data Sheet

ADL5566

APPLICATIONS INFORMATION

6 (VIN2), and the output pins, Pin 13 (VON2) and Pin 14

(VOP2), are biased by applying a voltage to VCOM2. If

BASIC CONNECTIONS

Figure 36 shows the basic connections for operating the ADL5566.

Apply a voltage between 3 V and 5 V to the VCC1 and VCC2

pins through a 5.1 nH inductor and decouple the supply side of the

inductor with at least one low inductance, 0.1 μF surface-mount

ceramic capacitor. In addition, decouple the VCOM1 and VCOM2

pins (Pin 21 and Pin 10) using a 0.1 μF capacitor. The ENBL1

and ENBL2 pins (Pin 22 and Pin 9) are tied to their amplifiers

VCC_x pin to enable each amplifier. A differential signal is

applied to Amplifier 1 through Pin 1 (VIN1) and Pin 2 (VIP1)

and to Amplifier 2 through Pin 5 (VIP2) and Pin 6 (VIN2).

Each amplifier has a gain of 16 dB.

VCOM2 is left open, VCOM2 equals ½ of VCC2. The ADL5566

can be ac-coupled as shown in Figure 36 or can be dc-coupled if

within the specified input and output common-mode voltage

ranges (see the Circuit Description section). To enable the

ADL5566, the ENBL1 and ENBL2 pins must be pulled high.

Pulling the ENBL1/ENBL2 pins low puts the ADL5566 in sleep

mode, reducing the current consumption to 7 mA at ambient.

A series 5.1 nH inductor can be connected to the VCCx pins with

the V_CCdecoupling capacitor connected to the V_CCbus side (see

Figure 36 and Figure 53). This inductor with the internal

capacitance of the amplifier results in a two pole low-pass

network and reduces the amplifier V_CCnoise.

The input pins, Pin 1 (VIN1) and Pin 2 (VIP1), and the output

pins, Pin 18 (VON1) and Pin 17 (VOP1), are biased by

applying a voltage to Pin 21 (VCOM1). If VCOM1 is left open,

VCOM1 equals ½ of VCC1. The input pins, Pin 5 (VIP2) and Pin

VCC

+

10µF

0.01µF

5.1nH

VCC1

0.01µF

5.1nH

VCC2

118

2108

EXPOSED PAD

R

F

0.01µF

VON1

18

21

½ R

0.01µF

S

R

G

VCOM1

0.01µF

VIP1

VIN1

2

1

BALANCED

LOAD

BALANCED

SOURCE

R

G

½ R

S

VOP1

17

R

0.01µF

F

ENBL1

ENBL2

222

91

VCC

ADL5566

R

F

0.01µF

VON2

13

10

½ R

0.01µF

S

R

G

VCOM2

VIP2

VIN2

5

6

BALANCED

LOAD

BALANCED

SOURCE

0.01µF

R

G

0.01µF

½ R

S

VOP2

14

R

0.01µF

F

NC

3

24

4

7

8

12 15 16 19 23

NOTES

1. EXPOSED PADDLE IS INTERNALLY CONNECTED TO GND AND MUST BE SOLDERED

TO A LOW IMPEDANCE GROUND PLANE.

Figure 36. Basic Connections

Rev. C | Page 15 of 24

ADL5566

Data Sheet

VCC

+

INPUT AND OUTPUT INTERFACING

The ADL5566 can be configured as a differential input to

differential output driver, as shown in Figure 37. The 36 Ω

resistors, R1 and R2, combined with the ETC1-1-13 balun

transformer, provide a 50 ꢀ input match for the 160 Ω input

impedance. The input and output 0.1 μF capacitors isolate the

V_CC/2 bias from the source and balanced load. The load should

equal 200 Ω to provide the expected ac performance (see the

Specifications section).

R2

0.1µF

R

½ RL

S

½

77Ω

ADL5566

AC

–

+

0.1µF

R1

30Ω

Figure 39. Single-Ended Input to Differential Output Configuration

VCC

The single-ended gain configuration of the ADL5566 is dependent

on the source impedance and load, as shown in Figure 40.

ETC1-1-13

+

0.1µF

50Ω

AC

R2

½ RL

½

ADL5566

500Ω

–

80Ω

5Ω

+

R1

R2

0.1µF

R

½ RL

S

½

77Ω

ADL5566

AC

Figure 37. Differential Input to Differential Output Configuration

–

The differential gain of the ADL5566 is dependent on the source

impedance and load, as shown in Figure 38.

+

0.1µF

R1

500Ω

30Ω

500Ω

Figure 40. Single-Ended Input Loading Circuit

80Ω

5Ω

0.1µF

The single-ended gain can be determined by the following two

equations:

+

0.1µF

RL

½ R

AC

S

½

ADL5566

R2131

R2 131

R_MATCH



–

½ R

S

0.1µF

R_MATCH R_S

R_MATCH

R_L

10  R_L

500

R2

R_S R2

0.1µF

500Ω

A

_V1















R_SR2

R_S R2

80 

Figure 38. Differential Input Loading Circuit

The differential gain can be determined by

500 R^L

80 10  RL

GAIN ADJUSTMENT AND INTERFACING

The effective gain of the ADL5566 can be reduced by adding two

resistors in series with the inputs to reduce the 16 dB gain.

(1)

A^V



Single-Ended Input to Differential Output

500Ω

The ADL5566 can also be configured in a single-ended input to

differential output driver, as shown in Figure 39. In this

R

SERIES

80Ω

5Ω

+

configuration, the gain of the part is reduced due to the application

of the signal to only one side of the amplifier. The input and output

0.1 μF capacitors isolate the V_CC/2 bias from the source and the

balanced load. R2 is used to match the single-ended input

impedance of the amplifier (131 Ω) with the 50 Ω source. R1 is

selected to balance the input of the amplifier. See the Application

Note AN-0990 for more information on terminating single-ended

inputs. The performance for this configuration is shown in

Figure 16 and Figure 24.

0.1µF

RL

0.1µF

R

½ R

AC

S

½

ADL5566

SHUNT

0.1µF

–

½ R

S

R

SERIES

0.1µF

500Ω

Figure 41. Gain Adjustment Using a Series Resistor Show

Rev. C | Page 16 of 24

Data Sheet

ADL5566

To find R_SERIESfor a given A_Vgain and R_L, use the following:

The necessary shunt component, R_SHUNT, to match to the source

impedance, R_S, can be expressed with the following:









1

(5)

R_SHUNT

=

1

−

R_S2R_SERIES+160

500

R_SERIES

=

−80

(3)









The voltage gain for multiple shunt resistor values are summarized

in Table 5. The source resistance and input impedance need

careful attention when using Equation 5. The reactance of the

input impedance of the ADL5566 and the ac coupling capacitors

must be considered before assuming that they make a negligible

contribution.

A_V

R_L

10 + R_L

















 



 



To calculate the A_Vgain for a given R_SERIESand R_L, use the following:

–50

HD2 3.3V

500

SERIES +80

R

L







 

 







–55

–60

HD3 3.3V

IMD 3.3V

HD2 5V

HD3 5V

IMD 5V

(4)

AGAIN

=

×

 

R

10 + R

L

20

19

18

17

16

15

14

13

12

11

10

9

–65

–70

–75

–80

–85

–90

–95

8

–100

–105

–110

–115

–120

7

6

5

4

3

2

1

0

50

100 150 200 250 300 350 400 450 500

FREQUENCY (MHz)

–1

–2

–3

–4

–5

Figure 43. IMD, HD2, and HD3 vs. Frequency, A_V= 6 dB, 2 V p-p Output,

_POS= 3.3 and V_POS= 5 V

1M

10M

100M

1G

10G

V

FREQUENCY (Hz)

Figure 42. SDD21, V_POS= 3.3 V, Three Gains, 25°C

Table 5. Differential Gain Adjustment Using Series Resistor

Target Gain (dB)

Actual Gain (dB)

R_S(Ω)

50

R_SERIES(Ω)¹

396.2

344.4

298.3

257.1

220.5

187.8

158.7

132.7

109.6

89

70.6

54.2

39.6

26.6

15

4.8

R_SHUNT(Ω)¹

52.8

53.1

53.5

54

54.5

55.1

55.8

56.7

57.6

58.7

60

0

−0.1

1

+1.2

2

+2.1

3

+2.9

4

+4.1

5

+5.1

6

+6.1

7

+6.9

8

+8.1

9

+8.9

10

11

12

13

14

15

+10

+11.1

+12

+12.8

+14

61.4

63.2

65.3

67.9

70.9

+15.1

+15.8

16

50

0

72.7

¹The resistor values are rounded to the nearest real resistor value.

Rev. C | Page 17 of 24

ADL5566

Data Sheet

FUNDAMENTAL1 = –7.03dBFS

FUNDAMENTAL2 = –7.05dBFS

IMD (2f1 – f2) = –90.53dBc

IMD (2f2 + f1) = –96.81dBc

NOISE FLOOR = –114.703dB

ADC INTERFACING

0

–15

The ADL5566 is a dual high output linearity amplifier that is

optimized for ADC interfacing. One option of applying the

ADL5566 to drive an ADC is shown in Figure 47. The wideband

1:1 transmission line balun provides a differential input to the

amplifier, and the 36 Ω resistors provide a 50 Ω match to the

source. The ADL5566 is ac-coupled from the input and output

to avoid common-mode loading. A reference voltage is

required to bias the AD9268 inputs and is delivered through

the 200 Ω resistors. These, in parallel with the 400 Ω resistor,

create the low frequency amplifier load of 200 Ω. The 56 nH

inductors and the 56 pF capacitor are used to create a 70 MHz

low-pass filter. The two 25 Ω resistors are added to raise the

ADL5566 output impedance, which reduces peaking when the

filter drives a light load. The two 25 Ω resistors provide isolation to

the switching currents of the ADC sample-and-hold circuitry.

The AD9268 dual ADC presents a 6 kΩ differential load

impedance and requires a 1 V p-p to 2 V p-p input signal to

reach full scale. The system frequency response is shown in

Figure 46. By applying a 2 V p-p, 32 MHz single-tone signal from

the ADL5566 in a gain of 16 dB, an SFDR of 94.6 dBc is achieved.

By applying two half scale signals of 32 MHz and 33 MHz from

the ADL5566 in a gain of 16 dB, an SFDR of 90.5 dBc is

realized.

–30

–45

–60

–75

–90

–105

–120

–135

–150

0

6

12

18

24

30

36

42

48

54

60

FREQUENCY (MHz)

Figure 45. Measured Two-Tone Performance of the Circuit in Figure 47 for a

32 MHz and 33 MHz Input Signals

2

1

0

–1

–2

–3

–4

–5

–6

–7

–8

–9

–10

–11

–12

–13

–14

–15

–16

–17

–18

–19

–20

0

SNR = 74.28dB

FUND FREQ = 32.123MHz

FUND POWER = –1.014dBFS

–15

SECOND HARM = –94.629dBc

THIRD HARM = –95.19dBc

FOURTH HARM = –99.98dBc

FIFTH HARM = –104.971dBc

SIXTH HARM = –107.105dBc

–30

–45

0

20

40

60

80

100

120

140

160

FREQUENCY (MHz)

–60

Figure 46. Measured Relative Frequency Response of the Wideband ADC

Interface Depicted in Figure 47

–75

–90

3

+

2

–105

–120

–135

–150

4

5

6

0

6

12

18

24

30

36

42

48

54

60

FREQUENCY (MHz)

Figure 44. Measured Single-Tone Performance of the Circuit in Figure 47 for a

32 MHz Input Signal

VCC

0.1µF

ETC1-1

VIN_1

VIP_1

25Ω

+

0.1µF

50Ω

AC

36Ω

200Ω

½

16

AD9268

V

56pF

REF

400Ω

ADL5566

SIDE A

200Ω

25Ω

–

0.1µF

Figure 47. Wideband ADC Interfacing Example Featuring the AD9268

Rev. C | Page 18 of 24

Data Sheet

ADL5566

DC-COUPLED RECEIVER APPLICATION

The ADL5566 is well suited for dc-coupled applications, such

as zero-IF direct conversion receivers. An example receiver

configuration is shown in Figure 48, consisting of the ADL5380

quadrature demodulator and the ADL5566 dual differential

amplifier. This is an ideal combination because of the wide RF

input bandwidth from 400 MHz to 6 GHz, the high linearity of the

ADL5566, and when operating on a 5 V supply, level shifting to

align the common-mode voltage is not required.

performance. When using the ADL5566 as shown in Figure 48,

the OIP3s at the outputs are improved due to the high OIP3 of

the amplifier pair (see Table 6). In a real-world receiver where

blockers are present, it is advantageous to insert a low-pass

filter between the ADL5380 and the ADL5566 to remove

these undesired signals.

If the ADL5566 is followed by an ADC, insert an antialiasing

filter between the ADL5566 and the ADC to prevent broadband

noise from aliasing back in band. For more information on this

interface, see the ADC Interfacing section.

The interface between the ADL5380 and the ADL5566 is

straight forward because the impedance presented by the

ADL5566 is sufficiently high enough to permit directly

connecting the two devices without any degradation in

The cascade of the performance of the circuit shown in Figure 48 is

presented in Table 6.

V

S

VCC

+

0.1µF

10µF

0.01µF

5.1nH

0.01µF

5.1nH

VCC2

100pF

1.5kΩ

VCC1

118

2108

6

13

24

19

R

F

NC

12

7

0.01µF

ILO

VON1

4

3

18

21

R

ENBL

G

VCOM1

0.01µF

IHI

VIP1

VIN1

2

1

BALANCED

LOAD

GND3

G

23

9

VOP1

17

100pF

R

0.01µF

F

TC1-1-13

RFIP

RFIN

ENBL1

ENBL2

22

21

100pF

222

91

TC1-1-13

VCC

LOIP

90°

ADL5566

0Ω

R

F

0°

LOIN

R4

0Ω

10

20

0.01µF

VON2

GND3

13

10

GND3

1

2

R

G

VCOM2

VIP2

VIN2

5

6

BALANCED

LOAD

0.01µF

QHI

GND1

16

15

R

G

VOP2

NC

QLO

14

24

R

0.01µF

F

5

NC

GND3

3

18

4

7

8

12 15 16 19 23

8

11

14

17

Figure 48. DC-Coupled Interface Example Featuring the ADL5380

Table 6. Cascade Performance of the ADL5380 and ADL5566

IF Frequency = 200 MHz, R_L= 200 Ω, V_OUT= 2 V p-p Composite

Frequency (MHz) HD2 (dBc) HD3 (dBc) OIP3 (dBm) ADL5380 OIP3 (dBm)¹OIP2 (dBm) Voltage Gain (dB) Power Gain (dB)

900

1900

2700

−79.3

−82.2

−80.7

−84.2

−80.5

−73.9

44.9

40.8

39.6

26.2

26.5

25.7

91.8

83.9

75.6

18.1

12.0

¹Output referred IP3 of the ADL5380, P_IN= −14 dBm, and R_L= 200 Ω.

Rev. C | Page 19 of 24

ADL5566

Data Sheet

LAYOUT CONSIDERATIONS

High-Q inductive drives and loads, as well as stray transmission

line capacitance in combination with package parasitics, can

potentially form a resonant circuit at high frequencies, resulting

in excessive gain peaking or possible oscillation. If RF transmission

lines connecting the input or output are used, design them such

that stray capacitance at the input/output pins is minimized. In

many board designs, the signal trace widths should be minimal

where the driver/receiver is no more than one-eighth of the wave-

length from the amplifier. This nontransmission line configuration

requires that underlying and adjacent ground and low impedance

planes be dropped from the signal lines.

VCC

+

0.1µF

5.1nH

VIN_1

0.1µF

ETC1-1

84.5Ω

34.8Ω

+

0.1µF

50Ω

AC

36Ω

½

50Ω

ANALYZER

ADL5566

AMPLIFIER 1

VIP_1

84.5Ω

34.8Ω

–

0.1µF

Figure 49. General-Purpose Characterization Circuit

VCC

+

0.1µF

5.1nH

0.1µF

+

0.1µF

+

VIN_1

VIP_1

50Ω

PORT 1

PORT 3

+

50Ω

AC

50Ω

AC

½

ADL5566

AMPLIFIER 1

36Ω

PORT 2

–

PORT 4

+

0.1µF

50Ω

AC

50Ω

AC

Figure 50. Differential Characterization Circuit Using Agilent E8357A Four-Port PNA

INPUT

COMMON-MODE V

ADJUST

VCC

+

0.1µF

2kΩ 2kΩ

0.1µF

5.1nH

VIN_1

0.1µF

ETC1-1

84.5Ω

34.8Ω

ETC1-1

+

50Ω

AC

36Ω

50Ω

ANALYZER

ADL5566

AMPLIFIER 1

84.5Ω

34.8Ω

VIP_1

–

0.1µF

VCOM

OUTPUT

Figure 51. Distortion Measurement Circuit for Various Common-Mode Voltages

Rev. C | Page 20 of 24

Data Sheet

ADL5566

SOLDERING INFORMATION AND RECOMMENDED

LAND PATTERN

EVALUATION BOARD

Figure 53 shows the schematic of the ADL5566 evaluation board.

The board is powered by a single supply in the 3 V to 5 V range.

The power supply is decoupled by 10 µF and 0.1 µF capacitors.

The L1 and L2 inductors decouple the ADL5566 from the power

supply.

Figure 52 shows the recommended land pattern for the ADL5566.

The ADL5566 is contained in a 4 mm × 4 mm LFCSP package,

which has an exposed ground paddle (EPAD). This paddle is

internally connected to the ground of the chip. To minimize

thermal impedance and ensure electrical performance, solder

the paddle to the low impedance ground plane on the printed

circuit board (PCB). To further reduce thermal impedance, it

is recommended that the ground planes on all layers under the

paddle be stitched together with vias.

Table 7 details the various configuration options of the evaluation

board. Figure 54 and Figure 55 show the component and circuit

side layouts of the evaluation board.

The balanced input and output interfaces are converted to single

ended with a pair of baluns (M/A-COM ETC1-1-13). The baluns

at the input, T1 and T2, provide a 50 Ω single-ended-to-differential

transformation. The output baluns, T3 and T4, and the matching

components are configured to provide a 200 Ω to 50 Ω impedance

transformation with an insertion loss of about 11 dB.

For more information on land pattern design and layout, refer

to the AN-772 Application Note, A Design and Manufacturing

Guide for the Lead Frame Chip Scale Package (LFCSP).

This land pattern, on the ADL5566 evaluation board, provides a

measured thermal resistance (θ_JA) of 34.0°C/W. To measure θ_JA,

the temperature at the top of the LFCSP package is found with

an IR temperature gun. Thermal simulation suggests a junction

temperature 1.5°C higher than the top of package temperature.

With additional ambient temperature and I/O power measure-

ments, θ_JAcan be determined.

91 MILS

13 MILS

13.7 MILS

39 MILS

19.7 MILS

12 MILS

Figure 52. Recommended Land Pattern

Rev. C | Page 21 of 24

ADL5566

Data Sheet

ENBL_1

V

VCOM-1

C6

CC

V

CC

+

GND

0.1µF

V

C7

0.1µF

POS

V

CC

C21

10µF

C3

0.1µF

L2

5.1nH

2

C10

DNI

C12

DNI

24

23

22

21

20

19

VOP1

C18

R18

R10

36Ω

C13

VIN1

R14

R5

0Ω

0.01µF

34.8Ω

0.01µF

84.5Ω

T1

T3

VON1

VIIN1

VIP1

NC

18

17

16

15

1

C17

R27

DNI

R8

0Ω

VON1

DNI

0.01µF

R1

VIP1

VIP2

VOP1

NC

2

3

4

5

6

DNI

R13

84.5Ω

R25

R9

36Ω

R17

34.8Ω

C14

0.01µF

ADL5566

R3

0Ω

VON2

NC

C20

0.01µF

C15

0.01µF

R20

34.8Ω

R11

36Ω

R16

84.5Ω

R21

0Ω

EXPOSED PADDLE

T2

T4

VOP2 14

VIP2

VIN2

DNI

R28

R24

0Ω

R2

DNI

VOP2

DNI

VIN2

DNI

VON2

12

13

R19

34.8Ω

R15

84.5Ω

R26

0Ω

R12

36Ω

C19

0.01µF

R4

0Ω

C16

0.01µF

7

8

9

10

11

2

C1

DNI

C11

DNI

L1

5.1nH

C4

0.1µF

V

POS

C2

0.1µF

C5

0.1µF

ENBL_2

VCOM-2

V

CC

Figure 53. Evaluation Board Schematic

Table 7. Evaluation Board Configuration Options

Component

Description

Default Condition

V_POS, GND

Ground and supply test loops.

V_POS, GND = installed

C5, C7, C21, L1, Power supply decoupling. The supply decoupling consists of a 10 μF capacitor (C21) and C21 = 10 μF (Size D),

L2

two 0.1ꢀF capacitors, C5 and C7, connected between the supply lines and ground.

L1 and L2 decouple the ADL5566 from the power supply.

C5, C7 = 0.1 μF (Size 0402),

L1, L2 = 5.1 nH (Size 0603)

VIN1, VIP1, VIP2, Input interface. The SMA labeled VIN1 is the input to Amplifier 1. T1 is a 1:1

VIN2, R1, R2, R3, impedance ratio balun to transform a single-ended input into a balanced differential

VIN1, VIP2 = installed,

VIP1, VIN2 = not installed,

R1, R2 = DNI,

R4, R5, R8, R9,

R10, R11, R12,

R21, R24, C13,

C1, C12, C14,

C15, C16, T1, T2

signal. Removing R3, installing R1 (0 Ω), and installing an SMA connector (VIP1) allow

driving from a differential source. C13 and C14 provide ac coupling. C12 is an

optional bypass capacitor. R9 and R10 provide a differential 50 Ω input termination. The (Size 0402),

SMA labeled VIP2 is the input to Amplifier 2. T2 is a 1:1 impedance ratio balun to

transform a single-ended input into a balanced differential signal. Removing R4,

installing R2 (0 Ω), and installing an SMA connector (VIN2) allow driving from a

R3, R4, R5, R8, R21, R24 = 0 Ω

R9, R10, R11, R12 = 36 Ω (Size 0402),

C13, C14, C15, C16 = 0.01 μF

(Size 0402),

differential source. C15 and C16 provide ac coupling. C1 is an optional by pass capacitor. C1, C12 = DNI,

R11 and R12 provide a differential 50 Ω input termination.

T1, T2 = ETC1-1-13 (M/A-COM)

VOP1, VON1,

VON2, VOP2,

C10, C11, C17,

C18, C19, C20,

R13, R14, R15,

R16, R17, R18,

R19, R20, R25,

R26, R27, R28,

T3, T4

Output interface. The SMA labeled VOP1 is the output for Amplifier 1. T3 is a 1:1

impedance ratio balun used to transform a balanced differential signal to a single-

ended signal. Removing R25, installing R27 (0 Ω), and installing an SMA connector

(VON1) allow differential loading. C10 is an optional bypass capacitor. C17 and C18

provide ac coupling. R13, R14, R17, and R16 are provided for generic placement of

matching components.

VOP1, VON2 = installed,

VON1, VOP2 = not installed,

R13, R14, R15, R16 = 84.5 Ω

(Size 0402),

R17, R18, R19, R20 = 34.8 Ω

(Size 0402),

The SMA labeled VON2 is the output for Amplifier 2. T4 is a 1:1 impedance ratio balun

R25, R26 = 0 Ω (Size 0402),

used to transform a balanced differential signal to a single-ended signal. Removing R26, R27, R28 = DNI (Size 0402),

installing R28 (0 Ω), and installing an SMA connector (VOP2) allow differential loading. C10, C11 = DNI (Size 0402),

C11 is an optional bypass capacitor. C19 and C20 provide ac coupling. R15, R16, R19, C17, C18 = 0.01 μF (Size 0402),

and R20 are provided for generic placement of matching components.

The evaluation board is configured to provide a 200 Ω to 50 Ω impedance

transformation with an insertion loss of 11 dB.

C19, C20 = 0.01 ꢀF (Size 0402),

T3, T4 = ETC1-1-13 (M/A-COM)

Rev. C | Page 22 of 24

Data Sheet

ADL5566

Component

Description

Default Condition

ENBL_1, ENBL_2 = installed,

ENBL_1,

Device enable. ENBL_1 is the enable for Amplifier 1. Connecting a jumper between

ENBL_2, C3, C4 Pin 2 and V_POSenables Amplifier 1. C3 is a bypass capacitor. ENBL_2 is the enable for C3, C4 = 0.1 µF (Size 0402)

Amplifier 2. Connecting a jumper between Pin 2 and V_POSenables Amplifier 2. C4 is

a bypass capacitor.

VCOM-1,

Common-mode voltage interface. VCOM1 is the common-mode interface for

VCOM-1, VCOM-2 = installed

C2, C6 = 0.1 µF (Size 0402)

VCOM-2, C2, C6 Amplifier 1. A voltage applied to this pin sets the common-mode voltage of the output

of Amplifier 1. VCOM2 is the common-mode interface for Amplifier 2. A voltage applied

to this pin sets the common-mode voltage of the output of Amplifier 2. Typically

decoupled to ground with a 0.1 µF capacitor (C2 and C6). With no reference applied,

input and output common mode float to midsupply (V_CC/2).

Figure 55. Layout of Evaluation Board, Circuit Side

Figure 54. Layout of Evaluation Board, Component Side

Rev. C | Page 23 of 24

ADL5566

Data Sheet

OUTLINE DIMENSIONS

DETAIL A

(JEDEC 95)

4.10

4.00 SQ

3.90

0.30

0.25

0.20

PIN 1

INDICATOR

AREA

PIN 1

IONS

INDICATOR AR EA OP T

(SEE DETAIL A)

24

19

18

1

0.50

BSC

2.44

2.30 SQ

2.16

EXPOSED

PAD

13

12

6

7

0.50

0.40

0.30

0.20 MIN

TOP VIEW

SIDE VIEW

BOTTOM VIEW

0.80

0.75

0.70

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.203 REF

COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8

Figure 56. 24-Lead Lead Frame Chip Scale Package [LFCSP]

4 mm × 4 mm Body and 0.75 mm Package Height

(CP-24-14)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Package Option

ADL5566ACPZ-R7

ADL5566-EVALZ

−40°C to +85°C

24-Lead Lead Frame Chip Scale Package [LFCSP], 7” Tape and Reel

Evaluation Board

CP-24-14

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D10916-0-8/19(C)

Rev. C | Page 24 of 24


型号：	ADL5566-EVALZ
厂家：	ADI
描述：	4.5 GHz Ultrahigh Dynamic Range, Dual Differential Amplifier
文件：	总24页 (文件大小：885K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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