ADL5580BCCZ [ADI]
Fully Differential, 10 GHz ADC Driver with 10 dB Gain;
| 型号： | ADL5580BCCZ |
| 厂家： | 
ADI |
| 描述： | Fully Differential, 10 GHz ADC Driver with 10 dB Gain |
| 文件： | 总22页 (文件大小：783K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Fully Differential, 10 GHz ADC Driver
with 10 dB Gain
Data Sheet
ADL5580
FEATURES
−3 dB bandwidth: 10.0 GHz
FUNCTIONAL BLOCK DIAGRAM
5V
Preset 10 dB gain, can be reduced by adding external
resistors
ADL5580
2
4
14
12
VINP
= 100Ω DIFFERENTIAL
VINN
VOUTP
Differential or single-ended input to differential output
Internally dc-coupled inputs and outputs
Input voltage noise (NSD, RTI): 2.25 nV/√Hz at 100 MHz
Low noise input stage: 11.3 dB noise figure at 1 GHz
Low distortion with +5.0 V and −1.8 V supplies and 1.4 V p-p
output differential with a 50 Ω||1 pF load differential
2 GHz: −59.4 dBc (HD2), −54.3 dBc (HD3), −68.2 dBc (IMD3)
6 GHz: −66 dBc (HD2), −88.1 dBc (HD3), −48.3 dBc (IMD3)
276 mA positive supply current at 5.0 V typical
−224 mA negative supply current at −1.8 V typical
Power disable
A
= 10dB
Z
Z
= 50Ω DIFFERENTIAL
V
IN
OUT
VOUTN
–1.8V
Figure 1.
APPLICATIONS
Instrumentation and defense applications
GENERAL DESCRIPTION
The ADL5580 is a high performance, single-ended or differential
amplifier with 10 dB of voltage gain, optimized for applications
spanning from dc to 10.0 GHz. The amplifier offers a low referred
to input (RTI) noise spectral density (NSD) of 2.24 nV/√Hz (at
1000 MHz) and is optimized for distortion performance over a
wide frequency range, making the device an ideal driver for
high speed 12-bit to 16-bit analog-to-digital converters (ADCs).
The ADL5580 is suited for use in high performance, zero
intermediate frequency (IF), and complex IF receiver designs.
In addition, this device has low distortion for single-ended
input driver applications.
Operating from a +5 V and −1.8 V supply, the positive and
negative supply current of the ADL5580 is typically +276 mA
and −224 mA, respectively. The device has a power disable
feature, and when disabled, the amplifier consumes 2 mA.
The ADL5580 is optimized for wideband, low distortion, and
low noise operation at the dc to 10.0 GHz frequency range.
These attributes, together with its adjustable gain capability,
make this device an optimal choice for driving a wide variety of
ADCs, mixers, pin diode attenuators, surface acoustic wave
(SAW) filters, and a multiplicity of discrete RF devices.
Fabricated on an Analog Devices, Inc., high speed silicon
germanium (SiGe) process, the ADL5580 is supplied in a
compact 4 mm × 4 mm, 20-terminal land grid array (LGA)
package and operates over the −40°C to +85°C temperature
range.
By using two external series resistors, the gain selection from
10 dB for a differential input can be modified to a lower gain.
The device maintains low distortion through its output
common-mode voltage (VCM) of 0.5 V, providing a flexible
capability for driving ADCs with full-scale levels up to 1.4 V p-p.
Rev. 0
Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice.
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Devices. Trademarks and registeredtrademarks are the propertyof their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2020 Analog Devices, Inc. All rights reserved.
www.analog.com
ADL5580
Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
RF Input and Output with Common-Mode Network.......... 15
RF Signal Chain.......................................................................... 15
Programmability Guide............................................................. 15
SPI ................................................................................................ 15
Applications Information ............................................................. 16
Basic Connections...................................................................... 16
Input and Output Interfacing................................................... 17
Layout .......................................................................................... 17
Register Summary .......................................................................... 18
Register Details ............................................................................... 19
Outline Dimensions....................................................................... 22
Ordering Guide .......................................................................... 22
Applications ...................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications .................................................................................... 3
Digital Logic Timing.................................................................... 6
Absolute Maximum Ratings ........................................................... 8
Thermal Resistance...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions ............................ 9
Typical Performance Characteristics........................................... 10
Theory of Operation ...................................................................... 15
REVISION HISTORY
12/2020—Revision 0: Initial Version
Rev. 0 | Page 2 of 22
Data Sheet
ADL5580
SPECIFICATIONS
Positive supply voltage (VS) = +5.0 V, negative VS = −1.8 V, input VCM = 1.7 V, output VCM = 0.5 V, source impedance (RS) = 100 Ω
differential, load impedance (RL) = 50 Ω differential, output voltage (VOUT) = 1.4 V p-p composite, peak capacitance (CPEAK) = 3, TA =
25°C, and signal spacing = 2 MHz for two-tone measurements, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth1
Bandwidth, 1.0 dB Flatness
Voltage Gain (AV)
VOUT ≤ 1.4 V p-p
VOUT ≤ 1.4 V p-p
10.0
6
GHz
GHz
Differential Input
RL = 50 Ω||1 pF differential
RL = 50 Ω||1 pF differential
Positive VS 5% and negative VS 5%
TA = −40°C to +85°C
Rising, VOUT = 1.4 V p-p step
Falling, VOUT = 1.4 V p-p step
1.4 V step to 1%
10
10
128
10.7
24
dB
dB
Single-Ended Input
Gain Supply Sensitivity
Gain Temperature Sensitivity
Slew Rate
mdB/V
mdB/°C
V/ns
V/ns
ns
24
Settling Time
Overdrive Settling Time
EN Response Time
2.4
640
20
Differential output voltage 2.8 V p-p
From shutdown mode
ps
ns
To shutdown mode
6
ns
Reverse Isolation (SDD12)
Input to Output Isolation when Disabled
Frequency = 1000 MHz
Frequency = 1000 MHz, EN pin set to low
−70
−87
dB
dBc
INPUT AND OUTPUT CHARACTERISTICS
Input VCM
VCMI
1.7
V
Input Resistance
Differential
Single-Ended
Common-Mode Rejection Ratio (CMRR)
Output VCM
100
100
32.9
0.5
50
Ω
Ω
dB
V
Ω
Frequency = 1000 MHz
VCMO
Output Resistance (Differential)
VCMI and VCMO Input Impedance
10
kΩ
Input Common-Mode
Offset
97.7
mV
Drift
TA = 25°C to 85°C
0.188
mV/°C
Input Differential Offset
Voltage
0.4
mV
Drift
TA = −40°C to +25°C
TA = −40°C to +25°C
3.076
µV/°C
Output Common-Mode
Offset
Drift
6.6
0.119
mV
mV/°C
Output Differential Offset
Voltage
Drift
0.4
6.666
5
mV
µV/°C
V p-p
TA = 25°C to 85°C
Frequency = 1000 MHz, 1 dB compression point
Maximum Output Voltage Swing
Rev. 0 | Page 3 of 22
ADL5580
Data Sheet
Parameter
Test Conditions/Comments
Min Typ
Max
Unit
NOISE AND HARMONIC PERFORMANCE
Input Signal Frequency, 100 MHz
Second Harmonic Distortion (HD2)
−77.2
dBc
Third Harmonic Distortion (HD3)
Output Third-Order Intercept (OIP3)
Third-Order Intermodulation Distortion (IMD3)
Output Second-Order Intercept (OIP2)
Second-Order Intermodulation Distortion (IMD2)
Output 1 dB Compression Point (OP1dB)
Noise Figure
NSD, RTI2
−74.2
43.6
−84.7
77.7
−76.4
17.5
11.3
dBc
dBm
dBc
dBm
dBc
dBm
dB
2.25
nV/√Hz
Input Signal Frequency, 500 MHz
HD2
HD3
OIP3
IMD3
OIP2
IMD2
OP1dB
−66.4
−66.1
40.3
−78.2
66.8
−65.6
17.5
11.2
dBc
dBc
dBm
dBc
dBm
dBc
dBm
dB
nV/√Hz
Noise Figure
NSD, RTI2
2.23
Input Signal Frequency, 1000 MHz
HD2
HD3
OIP3
IMD3
OIP2
IMD2
OP1dB
−66.3
−61.1
38.1
−73.5
65.9
−64.7
17.5
11.3
dBc
dBc
dBm
dBc
dBm
dBc
dBm
dB
nV/√Hz
Noise Figure
NSD, RTI2
2.24
Input Signal Frequency, 2000 MHz
HD2
HD3
OIP3
IMD3
OIP2
IMD2
OP1dB
Noise Figure
NSD, RTI2
−59.4
−54.3
35.3
−68.2
60.2
−59.1
17.5
11.4
dBc
dBc
dBm
dBc
dBm
dBc
dBm
dB
nV/√Hz
2.26
Rev. 0 | Page 4 of 22
Data Sheet
ADL5580
Parameter
Input Signal Frequency, 3000 MHz
Test Conditions/Comments
Min Typ
−60.6
Max
Unit
HD2
dBc
HD3
OIP3
IMD3
OIP2
IMD2
OP1dB
Noise Figure
NSD, RTI2
−47.1
32.8
−63.2
69.8
−68.6
17.5
10.9
dBc
dBm
dBc
dBm
dBc
dBm
dB
2.13
nV/√Hz
Input Signal Frequency, 4000 MHz
HD2
−58
dBc
HD3
OIP3
IMD3
OIP2
IMD2
OP1dB
Noise Figure
NSD, RTI2
−54.8
30.7
−53.9
58.6
−57.3
18.0
10.3
dBc
dBm
dBc
dBm
dBc
dBm
dB
1.96
nV/√Hz
Input Signal Frequency, 5000 MHz
HD2
−60
dBc
HD3
OIP3
IMD3
OIP2
IMD2
OP1dB
Noise Figure
NSD, RTI2
−72.1
28.1
−53.9
60.9
−59.7
17.5
10.0
dBc
dBm
dBc
dBm
dBc
dBm
dB
1.90
nV/√Hz
Input Signal Frequency, 6000 MHz
HD2
HD3
OIP3
IMD3
OIP2
IMD2
OP1dB
NF
−66
dBc
dBc
dBm
dBc
dBm
dBc
−88.1
25.4
−48.3
67.3
−66.1
17.0
9.5
dBm
dB
NSD, RTI2
DIGITAL LOGIC
Input Voltage
1.78
nV/√Hz
SCLK, SDIO, , and EN
CS
High (VIH)
Low (VIL)
1.07
V
V
0.68
Input Current
High (IIH)
Low (IIL)
−100 μA
100 μA
Rev. 0 | Page 5 of 22
ADL5580
Data Sheet
Parameter
Output Voltage
At 1.8 V
Test Conditions/Comments
SDIO
Register 0x200, Bit 0 = 0x0
Min Typ
Max
Unit
High (VOH)
Output high current (IOH) = −100 µA or
−1 mA static load
Output low current (IOL) = 100 μA or 1 mA static load
Register 0x200, Bit 0 = 0x1
IOH = −100 μA or −1 mA static load
IOL = 100 μA or 1 mA static load
1.5
V
V
Low (VOL)
At 3.3 V
VOH
VOL
0.2
0.2
2.7
V
V
SUPPLY AND POWER SPECIFICATIONS
Power
Shutdown Power
Shutdown Current
Positive Supply
1.76
11
2
W
mW
mA
At room temperature
At room temperature
Voltage (VPAVCC
Current (IPAVCC
Negative Supply
Voltage (VMAVEE
Current (IMAVEE
)
5%
5%
4.75 5.0
276
5.25
V
mA
)
)
−1.7 −1.8
−224
−1.89
V
mA
)
1 S parameters are taken with the device under test (DUT) itself. The printed circuit board (PCB) is not used in the measurement.
2 NSD RTI is calculated from noise figure as follows, assuming that RS = RL:
NSD (RTI) = ½ × 4kT × (10NF/10 −1) × RIN
where:
k is Boltzmann's constant, which equals 1.381 × 10−23J/K.
T is the standard absolute temperature for evaluating noise figure, which equals 290 K.
RIN is the differential input impedance of the amplifier, which equals 100 Ω.
DIGITAL LOGIC TIMING
Table 2.
Parameter Description
Min Typ Max Unit
fSCLK
tPWH
tPWL
tDS
Maximum serial clock rate, 1/tSCLK (tSCLK is the SCLK time)
25
10
10
5
MHz
ns
ns
ns
ns
Minimum period that SCLK is in logic high state
Minimum period that SCLK is in logic low state
Setup time between data and rising edge of SCLK
Hold time between data and rising edge of SCLK
tDH
5
tDCS
tH
Setup time between falling edge of
and rising edge of SCLK
10
10
ns
CS
Hold time between rising edge of
and the last falling edge of SCLK
ns
CS
Maximum time delay between falling edge of SCLK and output data valid for a read operation
Maximum time delay between deactivation and SDIO bus return to high impedance
tDV
tz
5
14
12
ns
ns
CS
Timing Diagrams
INSTRUCTION CYCLE
ADDRESS
DATA TRANSFER CYCLE
CS
SCLK
SDI
R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5
N
D3 D2 D1 D0
0
N
N
0
0
0
Figure 2. Serial Port Interface Register Timing, MSB First
Rev. 0 | Page 6 of 22
Data Sheet
ADL5580
tSCLK
tPWH
tPWL
SCLK
tDCS
tH
CS
tDH
tDS
tZ
SDI
R/W
CS5
CS4
0
0
0
0
A_MSB
A7
A2
A1
A_LSB D_MSB
D6
D5
D1
D_LSB
Figure 3. Timing Diagram for the Serial Port Interface Register Write
SCLK
CS
tDV
D5
R/W
A_MSB
A13
A12
A11
A10
A9
A8
A7
A2
A1
A_LSB D_MSB
D6
D1
D_LSB
SDIO
Figure 4. Timing Diagram for Serial Port Interface Register Read
Rev. 0 | Page 7 of 22
ADL5580
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
THERMAL RESISTANCE
Thermal performance is directly linked to PCB design and
operating environment. Careful attention to PCB thermal
design is required.
Parameter
Supply Voltage
At PAVCC
Rating
5.5 V
At MAVEE
−1.98 V
350 mV
−0.3 V to +3.6 V
Table 4. Thermal Resistance
RF Input Power (VINP and VINN) at 100 Ω
Package
, SCLK, SDIO, and EN
CS
Type1
θJA
θJCTOP θJCBOTTOM θJB
ψJT ψJB
Unit
Temperature
Operating Range
Maximum Junction
Storage
CC-20-7
53.5
24.3 20.9 24.2 6.0 25.5 °C/W
−40°C to +85°C
125°C
150°C
1 Thermal resistance values specified are simulated based on JEDEC
specifications in compliance with JESD-51.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
ESD CAUTION
Rev. 0 | Page 8 of 22
Data Sheet
ADL5580
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADL5580
20
19
18
17
16
1
2
3
4
5
15
14
13
12
11
GND
GND
VINP
GND
VINN
GND
PAD 1
PAVCC
PAD 4
PAVCC
VOUTP
GND
TOP VIEW
PAD 2
MAVEE
PAD 3
MAVEE
VOUTN
GND
6
7
8
9
10
NOTES
1. PAD 1 AND PAD 4 ARE THE POSITIVE VOLTAGE SUPPLY, 5.0V.
2. PAD 2 AND PAD 3 ARE THE NEGATIVE VOLTAGE SUPPLY, –1.8V.
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No
Mnemonic Description
1, 3, 5, 6, 10, 11, 13, 15, 16, 20 GND
Ground. Connect the GND pins to ground.
2
VINP
Positive RF Input (RFIN) Signal. VINP is the positive side of the amplifier balanced differential
inputs.
4
7
VINN
CS
Negative RFIN Signal. VINN is the negative side of the amplifier balanced differential inputs.
Serial Peripheral Interface (SPI) Chip Select.
SPI Serial Clock. SCLK is a digital input.
is a digital input.
CS
8
9
12
SCLK
SDIO
VOUTN
SPI Serial Data Input and Output. SDIO is a digital input and output.
Negative RF Output (RFOUT) Signal. VOUTN is the negative side of the amplifier balanced
differential outputs.
14
17
18
VOUTP
VCMO
VCMI
Positive RFOUT Signal. VOUTP is the positive side of the amplifier balanced differential outputs.
VCM for the RF Output Signal.
VCM for the RF Input Signal.
19
EN
Digital Input Power Enable.
PAD1, PAD4
PAD2, PAD3
PAVCC
MAVEE
Positive Voltage Supply, 5.0 V.
Negative Voltage Supply, −1.8 V.
Rev. 0 | Page 9 of 22
ADL5580
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5.0 V, negative VS = −1.8 V, input VCM = 1.7 V, output VCM = 0.5 V, RS = 100 Ω differential, RL = 50 Ω differential VOUT = 1.4 V p-p
composite, CPEAK = 3, TA = 25°C, and signal spacing = 2 MHz for two-tone measurements, unless otherwise noted.
25
20
15
10
5
20
18
16
14
12
10
8
VINN TERMINATED
VINP TERMINATED
6
4
2
0
10
0
10
100
1000
10000
100
1000
10000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 6. Gain vs. Frequency for CPEAK = 0 Through CPEAK = 7,
Supply = Nominal, Temperature = 25°C
Figure 9. Single-Ended Gain vs. Frequency, Temperature = 25°C, CPEAK = 3,
Supply = Nominal
20
25
20
15
PAVCC = 5V, MAVEE = –1.8V
PAVCC = 5.25V, MAVEE = –1.89V
PAVCC = 4.75V, MAVEE = –1.71V
18
16
14
12
10
8
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
10
25
6
0
4
–5
–10
C
C
C
= 0
= 3
= 7
PEAK
PEAK
PEAK
2
0
10
100
1000
10000
10
100
1000
10000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 7. Gain vs. Frequency over Supply, CPEAK = 3, Temperature = 25°C
Figure 10. Output P1dB vs. Frequency over Temperature, Supply = Nominal,
CPEAK = 0, CPEAK = 3, and CPEAK = 7
25
25
20
15
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
20
15
10
5
PAVCC = 5V, MAVEE = –1.8V
PAVCC = 5.25V, MAVEE = –1.89V
PAVCC = 4.75V, MAVEE = –1.71V
10
5
0
–5
C
C
C
= 0
= 3
= 7
PEAK
PEAK
PEAK
0
10
–10
100
1000
10000
10
100
1000
10000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 8. Gain vs. Frequency over Temperature, CPEAK = 3, Supply = Nominal
Figure 11. Output P1dB vs. Frequency over Supply, Temperature = 25°C,
CPEAK = 0, CPEAK = 3, and CPEAK = 7
Rev. 0 | Page 10 of 22
Data Sheet
ADL5580
16
14
12
10
8
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
T
T
T
= +85°C
= +25°C
= –40°C
PAVCC = 5V, MAVEE = –1.8V
PAVCC = 5.25V, MAVEE = –1.89V
PAVCC = 4.75V, MAVEE = –1.71V
A
A
A
6
4
2
0
10
100
1000
10000
10
100
1000
10000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 12. Noise Figure vs. Frequency over Temperature,
PEAK = 3, Supply = Nominal
Figure 15. NSD, RTI vs. Frequency over Supply, Temperature = 25°C, CPEAK = 3
C
16
14
12
10
8
120
110
100
90
180
170
160
150
140
130
120
110
100
90
PAVCC = 5V, MAVEE = –1.8V
PAVCC = 5.25V, MAVEE = –1.89V
PAVCC = 4.75V, MAVEE = –1.71V
80
70
T
T
T
= +85°C
= +25°C
= –40°C
60
A
A
A
50
40
6
30
20
80
4
10
70
0
60
50
40
2
–10
–20
0
10
100
1000
10000
0
1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 13. Noise Figure vs. Frequency over Supply,
PEAK = 3, Temperature = 25°C
Figure 16. OIP2 Lower and OIP2 Higher vs. Frequency over Temperature,
Supply = Nominal, CPEAK = 7
C
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
50
T
T
T
= +85°C
= +25°C
= –40°C
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
A
A
A
45
40
35
30
25
20
15
10
5
0
10
100
1000
10000
0
1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 14. NSD, RTI vs. Frequency over Temperature, Supply = Nominal,
PEAK = 3
Figure 17. OIP3 vs. Frequency over Temperature, Supply = Nominal, CPEAK = 7
C
Rev. 0 | Page 11 of 22
ADL5580
Data Sheet
–30
–40
–10
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
–40
–50
30
–50
–60
–20
10
–60
–30
–40
–70
–10
–30
–50
–70
–80
–70
–90
–80
–50
–60
–100
–110
–120
–130
–140
–150
–160
–170
–180
–90
–100
–110
–120
–130
–70
–80
RF SINGLE-ENDED INPUT = VINN, TA = +85°C
RF SINGLE-ENDED INPUT = VINP, TA = +85°C
RF SINGLE-ENDED INPUT = VINN, TA = +25°C
RF SINGLE-ENDED INPUT = VINP, TA = +25°C
RF SINGLE-ENDED INPUT = VINN, TA = –40°C
RF SINGLE-ENDED INPUT = VINP, TA = –40°C
–90
–90
–110
–100
0
1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
0
1000
2000
3000
4000
5000
6000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 18. IMD2 Lower and IMD2 Higher vs. Frequency over Temperature,
Supply = Nominal, CPEAK = 7
Figure 21. HD2 Lower and HD3 Lower vs. Frequency over Temperature,
PEAK = 7
C
0
–40
–10
–20
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
–50
–60
–10
–20
–30
–40
–50
–60
–70
–80
–90
–30
–40
–70
–80
–50
–60
–90
–100
–110
–120
–130
–70
–80
PAVCC = 4.75V, MAVEE = –1.71V, T = +25°C
A
–90
PAVCC = 5V, MAVEE = –1.8V, T = +25°C
A
PAVCC = 5.25V, MAVEE = –1.89V, T = +25°C
A
–100
0
1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
FREQUENCY (MHz)
0
1000
2000
3000
4000
5000
6000
FREQUENCY (MHz)
Figure 19. IMD3 vs. Frequency over Temperature,
Supply = Nominal and CPEAK = 7
Figure 22. HD2 and HD3 vs. Frequency, Temperature = Nominal,
Supply = Nominal, and CPEAK = 7
50
45
40
35
30
25
20
15
10
–40
–10
–20
–50
–60
–30
–40
–70
–80
–50
–60
–90
–100
–110
–120
–130
–70
–80
RF SINGLE-ENDED INPUT = VINN, T = +85°C
A
RF SINGLE-ENDED INPUT = VINP, T = +85°C
A
RF SINGLE-ENDED INPUT = VINN, T = +25°C
A
PAVCC = 5V, MAVEE = –1.8V, T = +85°C
A
RF SINGLE-ENDED INPUT = VINP, T = +25°C
A
PAVCC = 5V, MAVEE = –1.8V, T = +25°C
–90
5
0
A
RF SINGLE-ENDED INPUT = VINN, T = –40°C
A
PAVCC = 5V, MAVEE = –1.8V, T = –40°C
A
RF SINGLE-ENDED INPUT = VINP, T = –40°C
A
–100
0
1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
FREQUENCY (MHz)
0
1000
2000
3000
4000
5000
6000
FREQUENCY (MHz)
Figure 20. Single-Ended OIP3 vs. Frequency over Temperature
Figure 23. Single-Ended HD2 and HD3 vs. Frequency over Temperature
Rev. 0 | Page 12 of 22
Data Sheet
ADL5580
250
200
a
b
M1
3
150
100
50
CH3 1.0V/DIV
M1 200mV
50
M10.0ns
6.1ns
A CH3
960mV
0
2
4
6
8
10
12
T
B/W: 4.0G
FREQUENCY (GHz)
Figure 27. Group Delay vs. Frequency
Figure 24. Enable Time Domain Response (Channel 3 (3) Is the Enable
Voltage, and Marker 1 (M1) Is the Output Voltage)
–20
–30
2000
C
C
C
= 0
= 3
= 7
PEAK
PEAK
PEAK
1500
1000
500
–40
–50
–60
–70
–80
–90
–100
0
–500
–1000
–1500
–2000
C
C
C
= 0
= 3
= 7
PEAK
PEAK
PEAK
–110
–10
–8
–6
–4
–2
0
2
4
6
8
10
1
10
100
1000
10000
TIME (ns)
FREQUENCY (MHz)
Figure 25. Large Signal Pulse Response
Figure 28. SDD12 vs. Frequency (Red: CPEAK = 0, Green: CPEAK = 3,
and Blue: CPEAK = 7)
50
45
40
35
30
25
20
15
10
5
280
–220
279
278
277
276
275
274
273
272
–221
–222
–223
–224
–225
–226
–227
–228
–229
–230
271
270
0
10
100
1000
10000
FREQUENCY (MHz)
TEMPERATURE (°C)
Figure 26. CMRR vs. Frequency
Figure 29. PAVCC Current (PIACC) and MAVEE Current (MAIEE) vs.
Temperature
Rev. 0 | Page 13 of 22
ADL5580
Data Sheet
1.0
1.0
2.0
2.0
H
0.5
0.5
H
5.0
5.0
0.2
0.2
10
10
20
20
0.5
1.0
2.0
5.0
10 20
0.5
1.0
2.0
5.0
10 20
–20
–10
–20
–10
–0.2
–0.2
–5.0
–5.0
–0.5
–0.5
–2.0
–2.0
–1.0
FREQUENCY (1.000MHz TO 10.00GHz)
–1.0
FREQUENCY (1.000MHz TO 10.00GHz)
Figure 30. SDD11 Impedance vs. Frequency (Red: CPEAK = 0, Green: CPEAK = 3,
and Blue: CPEAK = 7) (SDD11 Is the Differential S11)
Figure 31. SDD22 Impedance vs. Frequency (Red: CPEAK = 0, Green: CPEAK = 3,
and Blue: CPEAK = 7)
Rev. 0 | Page 14 of 22
Data Sheet
ADL5580
THEORY OF OPERATION
The ADL5580 is a fixed voltage gain (10 dB), fully differential,
high linearity amplifier, and ADC driver that operates on a dual
power supply voltage, +5 V and −1.8 V.
bandwidth is critical, the ADL5580 offers tuning options
through the peaking control bits, PRG_CPEAK_1P8V
(Register 0x101, Bits[6:4]).
The small signal −3 dB bandwidth is 10.0 GHz, and all of the
integrated building blocks of the ADL5580 are programmable via
the SPI.
Enable
The enable bits (EN_AMP_1P8V and EN_REF_1P8V) are
located in Register 0x101, Bit 1 and Bit 0, respectively. These
particular enable bits control enabling the amplifier (EN_
AMP_1P8V) and the reference (EN_REF_1P8V). The ADL5580
can be enabled or disabled by using the EN pin (Pin 19), a real-
time external pin with no SPI latency
RF INPUT AND OUTPUT WITH COMMON-MODE
NETWORK
The input impedance is 100 Ω differential, and the output
impedance is 50 Ω differential, which allows users to drive
ADCs like the AD9213 directly without any matching networks,
that is at a 50 Ω differential input. For load conditions other
than 50 Ω differential, external termination networks are
required.
PROGRAMMABILITY GUIDE
Viewing the register map at the highest level, the registers are
subdivided into three memory map functional blocks (see Table 6).
See Table 9 for a complete list of all the registers on the
ADL5580.
The input and output termination blocks have four operation
modes that allow users to set the input and output common-
mode operation through Register 0x100, Bits[7:0], see Table 7.
Table 6. Memory Map Functional Blocks
Register Address
Functional Blocks
In Mode 00, the VCM terminal must be provided externally on
the input termination and the output termination blocks.
0x000 to 0x011
0x100 to 0x101, 0x200 Signal path configuration, enable
Analog Devices SPI configuration
0x300
Optional linearity optimization
For Mode 01, the internal voltage generator (the voltage controlled
by two bits) is activated, and the VCM terminal input and output
termination blocks are driven to the internal reference voltage.
If the internal reference voltage and the connecting termination
blocks have a different VCM, the behavior of the system is
undefined and must be avoided.
SPI
The SPI of the ADL5580 allows the user to configure the device
for specific functions or operations via a 3-wire SPI port. It
includes enable blocks, the bias current level, transfer function
peaking, change input and output termination block operation
modes, and change input and output VCM termination for
certain operation modes. This SPI provides users with added
flexibility and customization and consists of three control lines:
Mode 10 is identical to Mode 01 except that the VCMO and
VCMI pins are driven to the internal reference voltage to
convey the internal VCM to the connecting termination blocks.
Use Mode 11 to set the internal VCM termination to externally
provide the voltage for the VCMx pins.
CS
SCLK, SDIO, and . The timing requirements for the SPI port
are shown in Table 2.
RF SIGNAL CHAIN
The ADL5580 input logic level for the write cycle is with a 1.8 V
logic level.
The ADL5580 provides another level of control to optimize
flatness or wider bandwidth. In applications where flatness is
critical, the ADL5580 offers flatness optimization at the
expense of the operating bandwidth. However, if the operating
On a read cycle, the SDIO is configurable for 1.8 V (default) or
3.3 V output levels by setting the SPI_1P8_3P3_CTRL bit
(Register 0x200, Bit 0).
Table 7. Common-Mode Setup Modes
Register 0x100, Bits[7:6]
Mode Output VCM (V)
Register 0x100, Bits[5:4]
Register 0x100, Bits[3:2]
Input VCM (V)
Register 0x100, Bits[1:0]
Output Internal VCM VCMO Pin
Input Internal VCM
VCMI Pin
Disconnect
Disconnect
Export
00
01
10
11
0.41
0.51
0.60
0.70
Disabled
Enabled
Enabled
Disabled
Disconnect 1.39
Disconnect 1.53
Export
Import
Disabled
Enabled
Enabled
Disabled
1.67
1.80
Import
Rev. 0 | Page 15 of 22
ADL5580
Data Sheet
APPLICATIONS INFORMATION
Figure 32 shows the basic connection diagram, and Table 8
describes the operation of the ADL5580.
manner without any glitches to avoid issues with the internal
digital logic.
The ADL5580 is sensitive to power supplies. Power rail voltages
must be brought up and applied in a monotonically increasing
The ADL5580 can be ac-coupled, as shown in Figure 32, or the
device can be dc-coupled if within the specified input and
output VCM ranges.
BASIC CONNECTIONS
0.1µF
0.1µF
½ R
S
VINP
VINN
2
4
14
VOUTP
+
BALANCED
AC
R
BALANCED
LOAD
ADL5580
L
0.1µF
0.1µF
12
17
VOUTN
VCMO
–
½ R
S
0.1µF
EN
19
7
8
9
CS
0.1µF
GND
SCLK
SDIO
1, 3, 5, 6, 10, 11, 13, 15, 16, 20
18
VCMI
0.1µF
PAD1
PAD2
PAD3
PAD4
PAVCC MAVEE MAVEE PAVCC
0.1µF
0.1µF
+5V
–1.8V
Figure 32. Basic Connection Diagram
Table 8. Basic Connections of the ADL5580
Functional Blocks Pin No. Mnemonic Description
Basic Connection
5 V
PAD1, PAD4
PAVCC
Amplifier analog supply
voltage, 5 V
Decouple each PAVCC pad via 100 pF, 1 µF capacitors
to ground. Ensure that the decoupling capacitors are
located close to the pads.
−1.8 V
RF Input
PAD2, PAD3
MAVEE
Amplifier analog supply
voltage, −1.8 V
Decouple each MAVEE pad via 100 pF, 1 µF capacitors
to ground. Ensure that the decoupling capacitors are
located close to the pads.
Differential RF inputs
Positive RF Input
Connect these pins to a differential configuration.
2
4
18
VINP
VINN
VCMI
Negative RF Input
VCM for the RF input signal
Differential RF outputs
Negative RF output
Positive RF output
VCM for the RF output signal
Chip select active low
SPI clock
RF Output
Serial Port
Connect the RF outputs to a power meter, network
analyzer, noise figure meter, or spectrum analyzer.
12
14
17
7
VOUTN
VOUTP
VCMO
CS
1.8 V to 3.3 V tolerant logic levels.
1.8 V to 3.3 V tolerant logic levels.
1.8 V to 3.3 V tolerant logic levels.
1.8 V to 3.3 V tolerant logic levels.
Connect the GND pins to the ground of the PCB.
8
9
SCLK
SDIO
EN
SPI data input output
Amplifier enable
AMP Control
Ground
19
1, 3, 5, 6, 10, 11, GND
13, 15, 16, 20
Ground
Rev. 0 | Page 16 of 22
Data Sheet
ADL5580
Single-Ended Input to Differential Output
INPUT AND OUTPUT INTERFACING
The ADL5580 can also be configured in a single-ended input to
differential output configuration. In this configuration, the gain
of the device is reduced due to the application of the signal to
only one side of the amplifier. The input and output 0.1 µF
capacitors isolate the VCM on input and output pins from the
source and balanced load.
Differential Input to Differential Output
The ADL5580 can be configured as a differential input to
differential output driver (see Figure 33). The 50 Ω resistors,
R1 and R2, combined with the 100 Ω input impedance provide
a 50 Ω input match with the 1:1 balun. The input and output
0.1 µF capacitors isolate the common-mode bias voltage (VBIAS
on input and output pins from the source and balanced load.
The load is 50 Ω to provide the expected ac performance.
)
0.1µF
0.1µF
+
½ R
½ R
L
50Ω
R2
ADL5580
0.1µF
0.1µF
L
AC
–
0.1µF
0.1µF
1:1BALUN
R1
+
R2
50Ω
50Ω
½ R
½ R
+ 5V
L
ADL5580
Figure 35. Single-Ended Input to Differential Output Configuration
L
0.1µF
0.1µF
AC
–
The ADL5580 is a high output linearity, fixed gain dc-coupled
amplifier for multigigasample ADC interfacing. The open-loop
architecture anticipates a 50 Ω differential dc output load. The
maximum linear output swing is optimized for 1.4 V p-p
differential.
R1
50Ω
–1.8V
Figure 33. Differential Input to Differential Output Configuration
The differential gain of the ADL5580 is dependent on the source
impedance and load, as shown in Figure 34.
LAYOUT
0.1µF
Solder the four exposed power supply pads on the underside of
the ADL5580 to a low thermal and electrical impedance power
plane. These pads are typically soldered to exposed opens in the
solder mask on the evaluation board. Notice the use of 4 via holes
on each exposed power pad of the ADL5580-EVALZ. Connect
these power vias to power layers on the evaluation board to
maximize heat dissipation from the device package. For more
information on the evaluation board, see the ADL5580-EVALZ
product page.
0.1µF
0.1µF
½ R
S
+
R
ADL5580
L
AC
–
½ R
S
0.1µF
Figure 34. Differential Input Loading Circuit
Ensure that the decoupling capacitors are located close to the
supply voltage pins.
Rev. 0 | Page 17 of 22
ADL5580
Data Sheet
REGISTER SUMMARY
Table 9.
Reg
Name
Bits
[7:0]
[7:0]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
0x00
0x00
R/W
R/W
R/W
0x000
0x001
ADI_SPI_CONFIG
REG_0X0001
SOFTRESET_
LSB_FIRST_
CSB_STALL
ENDIAN_
SDOACTIVE_
SDOACTIVE
ENDIAN
LSB_FIRST
SOFTRESET
SINGLE_
INTSTRUCTION
MASTER_
SLAVE_
RB
RESERVED
SOFT_RESET
MASTER_
SLAVE_
TRANSFER
0x003
0x004
0x005
0x00A
0x00B
0x010
0x011
0x100
0x101
0x200
CHIPTYPE
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
CHIPTYPE
PRODUCT_ID_L
PRODUCT_ID_H
SCRATCHPAD
SPI_REV
0x01
0x03
0x00
0x00
0x00
0x00
0x00
0x78
0x33
0x01
R
PRODUCT_ID_L
PRODUCT_ID_H
SCRATCHPAD
SPI_REV
R
R
R/W
R
VARIANT_FEOL
BEOL_SIF
FEOL
SIF
VARIANT
BEOL
R
R
GEN_CTL0
PRG_OTRM_1P8V
RESERVED
MS_OTRM_1P8V
PRG_CPEAK_1P8V
RESERVED
PRG_ITRM_1P8V
RESERVED
MS_ITRM_1P8V
R/W
R/W
R/W
GEN_CTL1
EN_AMP_1P8V
EN_REF_1P8V
SPI_CTL
SPI_1P8_
3P3_CTRL
Rev. 0 | Page 18 of 22
Data Sheet
ADL5580
REGISTER DETAILS
Address: 0x000, Reset: 0x00, Name: ADI_SPI_CONFIG
Table 10. Bit Descriptions for ADI_SPI_CONFIG
Bit(s)
Bit Name
Description
Reset
Access
7
SOFTRESET_
Soft Reset
0x00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0: reset asserted
1: reset not asserted
LSB First
0: LSB first
1: MSB first
6
5
4
3
2
1
0
LSB_FIRST_
ENDIAN_
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Endian
0: little endian
1: big endian
SDO Active
0: SDO inactive
1: SDO active
SDO Active
0: SDO inactive
1: SDO active
Endian
0: little endian
1: big endian
LSB First
SDOACTIVE_
SDOACTIVE
ENDIAN
LSB_FIRST
SOFTRESET
0: LSB first
1: MSB first
Soft Reset
0: reset asserted
1: reset not asserted
Address: 0x001, Reset: 0x00, Name: REG_0X0001
Table 11. Bit Descriptions for REG_0X0001
Bit(s)
7
6
Bit Name
SINGLE_INTSTRUCTION
CSB_STALL
Description
Single Instruction
Chip Select ( ) Stall
CS
Reset
0x00
0x00
Access
R/W
R/W
5
MASTER_SLAVE_RB
RESERVED
Master Slave Read Back (RB)
Reserved
0x00
0x00
0x00
0x00
R/W
R
[4:3]
[2:1]
0
SOFT_RESET
Soft Reset
R/W
R/W
MASTER_SLAVE_TRANSFER
Master Slave Transfer
Address: 0x003, Reset: 0x01, Name: CHIPTYPE
Table 12. Bit Descriptions for CHIPTYPE
Bit(s)
[7:0]
Bit Name
CHIPTYPE
Description
Chip Type, Read Only
Reset
0x01
Access
R
Rev. 0 | Page 19 of 22
ADL5580
Data Sheet
Address: 0x004, Reset: 0x03, Name: PRODUCT_ID_L
Table 13. Bit Descriptions for PRODUCT_ID_L
Bit(s)
Bit Name
Description
Reset
Access
[7:0]
PRODUCT_ID_L
Product_ID_L, Lower 8 Bits
0x03
R
Address: 0x005, Reset: 0x00, Name: PRODUCT_ID_H
Table 14. Bit Descriptions for PRODUCT_ID_H
Bit(s)
Bit Name
Description
Reset
Access
[7:0]
PRODUCT_ID_H
Product_ID_H, Higher 8 Bits
0x00
R
Address: 0x00A, Reset: 0x00, Name: SCRATCHPAD
Table 15. Bit Descriptions for SCRATCHPAD
Bit(s)
[7:0]
Bit Name
SCRATCHPAD
Description
Scratch Pad
Reset
0x00
Access
R/W
Address: 0x00B, Reset: 0x00, Name: SPI_REV
Table 16. Bit Descriptions for SPI_REV
Bit(s)
[7:0]
Bit Name
SPI_REV
Description
SPI Register Map Revision
Reset
0x00
Access
R
Address: 0x010, Reset: 0x00, Name: VARIANT_FEOL
Table 17. Bit Descriptions for VARIANT_FEOL
Bit(s)
[7:4]
[3:0]
Bit Name
FEOL
Description
Front End of Line (FEOL)
Variant
Reset
0x00
0x00
Access
R
R
VARIANT
Address: 0x011, Reset: 0x00, Name: BEOL_SIF
Table 18. Bit Descriptions for BEOL_SIF
Bit(s)
[7:4]
[3:0]
Bit Name
SIF
Description
Stress Intensity Factor (SIF) Version
Back End of Line (BEOL) Version
Reset
0x00
0x00
Access
R
R
BEOL
Address: 0x100, Reset: 0x78, Name: GEN_CTL0
Table 19. Bit Descriptions for GEN_CTL0
Bit(s) Bit Name
Description
Reset Access
[7:6]
[5:4]
[3:2]
[1:0]
PRG_OTRM_1P8V These bits set up the output VCM
.
0x1
0x3
0x2
0x0
R/W
R/W
R/W
R/W
MS_OTRM_1P8V
PRG_ITRM_1P8V
MS_ITRM_1P8V
These bits set VCM to internal or external and set the VCMO pin definition.
These bits set up the input VCM
These bits set VCM to internal or external and set the VCMI pin definition.
.
Rev. 0 | Page 20 of 22
Data Sheet
ADL5580
Address: 0x101, Reset: 0x33, Name: GEN_CTL1
Table 20. Bit Descriptions for GEN_CTL1
Bit(s) Bit Name
Description
Reserved.
Reset
Access
R
7
RESERVED
0x0
0x3
0x0
0x1
0x1
[6:4]
[3:2]
1
PRG_CPEAK_1P8V
RESERVED
These bits set up CPEAK
Reserved.
.
R/W
R
EN_AMP_1P8V
EN_REF_1P8V
Enable Amplifier Block.
Enable Reference Block.
R/W
R/W
0
Address: 0x200, Reset: 0x01, Name: SPI_CTL
Table 21. Bit Descriptions for SPI_CTL
Bit(s)
[7:1]
0
Bit Name
RESERVED
Description
Reserved
Reset
0x0
Access
R
SPI_1P8_3P3_CTRL
SPI Supply Control
0: 1.8 V readback
1: 3.3 V readback
0x1
R/W
Rev. 0 | Page 21 of 22
ADL5580
Data Sheet
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
0.30
0.27
0.24
PIN 1
INDICATOR
0.39
0.36
0.33
0.275
PIN 1
CORNER AREA
REF
20
16
15
1
0.80 BSC
SQ
2.00 REF
SQ
0.48
BSC
11
5
1.00
REF
0.50
BSC
6
10
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.96
BSC
0.52
0.45
0.38
0.89
0.81
0.73
FOR PROPER CONNECTION OF
THE EXPOSED PADS, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.396
0.356
0.316
SECTION OF THIS DATA SHEET
Figure 36. 20-Terminal Land Grid Array [LGA]
(CC-20-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADL5580BCCZ
ADL5580BCCZ-R7
ADL5580-EVALZ
AD-FMCADC20-DC-EBZ
AD-FMCADC20-EBZ
Temperature Range Package Description
Package Option
CC-20-7
CC-20-7
−40°C to +85°C
−40°C to +85°C
20-Terminal Land Grid Array [LGA]
20-Terminal Land Grid Array [LGA]
Evaluation Board
DC-Coupled Combination AD9213 and ADL5580 Reference Design
AC-Coupled Combination AD9213 and ADL5580 Reference Design
1 Z = RoHS-Compliant Part.
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D17004-12/20(0)
Rev. 0 | Page 22 of 22
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