ADL5811 [ADI]
High IP3, 700 MHz to 2800 MHz, Double Balanced, Passive Mixer, IF Amplifier, and Wideband LO Amplifier; 高IP3 ， 700 MHz至2800 MHz的双平衡无源混频器， IF放大器和宽带LO放大器
| 型号： | ADL5811 |
| 厂家： | 
ADI |
| 描述： | High IP3, 700 MHz to 2800 MHz, Double Balanced, Passive Mixer, IF Amplifier, and Wideband LO Amplifier |
| 文件： | 总28页 (文件大小：639K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High IP3, 700 MHz to 2800 MHz, Double Balanced,
Passive Mixer, IF Amplifier, and Wideband LO Amplifier
ADL5811
FUNCTIONAL BLOCK DIAGRAM
FEATURES
RF frequency: 700 MHz to 2800 MHz continuous
LO frequency: 250 MHz to 2800 MHz, high-side or
low-side inject
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
NC
RFCT
NC
NC
IF range: 30 MHz to 450 MHz
NC
Power conversion gain of 7.5 dB at 1900 MHz
SSB noise figure of 10.7 dB at 1900 MHz
Input IP3 of 27.5 dBm at 1900 MHz
Input P1dB of 12.7 dBm at 1900 MHz
Typical LO drive of 0 dBm
ADL5811
NC
RFIN
NC
LOIP
LOIN
LE
NC
SERIAL
PORT
INTERFACE
Single-ended, 50 Ω RF port
BIAS
GEN
NC
DATA
CLK
Single-ended or balanced LO input port
Single-supply operation: 3.6 V to 5.0 V
Serial port interface control on all functions
Exposed paddle 5 mm × 5 mm, 32-lead LFCSP package
NC
9
10
11
12
13
14
15
16
Figure 1.
APPLICATIONS
Multiband/multistandard cellular base station receivers
Wideband radio link diversity downconverters
Multimode cellular extenders and broadband receivers
GENERAL DESCRIPTION
The ADL5811 uses revolutionary new broadband, square
wave limiting, local oscillator (LO) amplifiers to achieve an
unprecedented radio frequency (RF) bandwidth of 700 MHz
to 2800 MHz. Unlike conventional narrow-band sine wave LO
amplifier solutions, this permits the LO to be applied either
above or below the RF input over an extremely wide bandwidth.
Because energy storage elements are not used, the dc current
consumption also decreases with decreasing LO frequency.
wideband applications where in-band blocking signals may
otherwise result in the degradation of dynamic range. Blocker
noise figure performance is comparable to narrow-band passive
mixer designs. High linearity IF buffer amplifiers follow the
passive mixer cores, yielding typical power conversion gains of
7.5 dB, and can be used with a wide range of output
impedances. For low voltage applications, the ADL5811 is
capable of operation at voltages down to 3.6 V with
substantially reduced current. Two logic bits are provided to
power down (<1.5 mA) the circuit when desired.
The ADL5811 uses highly linear, doubly balanced, passive
mixer cores along with integrated RF and LO balancing circuits
to allow single-ended operation. The ADL5811 incorporates
programmable RF baluns, allowing optimal performance over a
700 MHz to 2800 MHz RF input frequency. The balanced passive
mixer arrangement provides outstanding LO-to-RF and LO-to-
IF leakages, excellent RF-to-IF isolation, and excellent
All features of the ADL5811 are controlled via a 3-wire serial
port interface, resulting in optimum performance and
minimum external components.
The ADL5811 is fabricated using a BiCMOS high performance
IC process. The device is available in a 32-lead, 5mm × 5mm,
LFCSP package and operates over a −40°C to +85°C
intermodulation performance over the full RF bandwidth.
The balanced mixer cores also provide extremely high input
linearity, allowing the device to be used in demanding
temperature range. An evaluation board is also available.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2011 Analog Devices, Inc. All rights reserved.
ADL5811
TABLE OF CONTENTS
Features .............................................................................................. 1
RF Subsystem.............................................................................. 20
LO Subsystem ............................................................................. 21
Applications Information.............................................................. 22
Basic Connections...................................................................... 22
IF Port .......................................................................................... 22
Bias Resistor Selection ............................................................... 22
VGS Programming .................................................................... 22
Low-Pass Filter Programming.................................................. 23
RF Balun Programming ............................................................ 23
Register Structure........................................................................... 24
Evaluation Board ............................................................................ 25
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
3.6 V Performance...................................................................... 16
Spurious Performance................................................................ 17
Circuit Description......................................................................... 20
REVISION HISTORY
7/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
ADL5811
SPECIFICATIONS
VS = 5 V, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, RF power = −10 dBm, LO power = 0 dBm, R1 = 910 Ω, ZO = 50 Ω, optimum SPI settings,
unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min Typ
Max
Unit
RF INPUT INTERFACE
Return Loss
Tunable to >20 dB broadband via serial port
15
50
dB
Ω
MHz
Input Impedance
RF Frequency Range
OUTPUT INTERFACE
Output Impedance
IF Frequency Range
DC Bias Voltage1
700
2800
450
Differential impedance, f = 200 MHz
Externally generated
260||1.0
Ω||pF
MHz
V
30
VS
LO INTERFACE
LO Power
Return Loss
−6
0
13
50
+10
dBm
dB
Ω
Input Impedance
LO Frequency Range
DYNAMIC PERFORMANCE
Power Conversion Gain
Voltage Conversion Gain
SSB Noise Figure
Low-side or high-side LO
250
2800
MHz
Including 4:1 IF port transformer and PCB loss
ZSOURCE = 50 Ω, differential ZLOAD = 200 Ω differential
7.5
dB
dB
dB
dB
13.9
10.7
20.7
SSB Noise Figure Under Blocking
5 dBm blocker present 10 MHz from wanted RF input,
LO source filtered
Input Third-Order Intercept
Input Second-Order Intercept
fRF1 = 1900 MHz, fRF2 = 1901 MHz, fLO = 1697 MHz,
each RF tone at −10 dBm
fRF1 = 1900 MHz, fRF2 = 2000 MHz, fLO = 1697 MHz,
each RF tone at −10 dBm
27.5
62
dBm
dBm
Input 1 dB Compression Point
LO-to-IF Output Leakage
LO-to-RF Input Leakage
RF-to-IF Output Isolation
IF/2 Spurious
12.7
−40
−25
26
−73
−75
dBm
dBm
dBm
dB
dBc
dBc
Unfiltered IF output
−10 dBm input power
−10 dBm input power
IF/3 Spurious
POWER INTERFACE
Supply Voltage, VS
3.6
5
5.5
V
Quiescent Current
Power-Down Current
Resistor programmable IF current
185
1.4
mA
mA
1 Supply voltage must be applied from external circuit through choke inductors.
Rev. 0 | Page 3 of 28
ADL5811
TIMING CHARACTERISTICS
Low logic level ≤ 0.4 V, and high logic level ≥ 1.4 V.
Table 2. Serial Interface Timing
Parameter
Limit
Unit
Test Conditions/Comments
LE setup time
DATA-to-CLK setup time
DATA-to-CLK hold time
CLK high duration
CLK low duration
CLK-to-LE setup time
LE pulse width
t1
t2
t3
t4
t5
t6
t7
20
10
10
25
25
10
20
ns minimum
ns minimum
ns minimum
ns minimum
ns minimum
ns minimum
ns minimum
Timing Diagram
t4
t5
CLK
t2
t3
DB2
(CONTROL BIT C3)
DB1
DB0 (LSB)
(CONTROL BIT C1)
DB23 (MSB)
DB22
DATA
LE
(CONTROL BIT C2)
t6
t7
t1
Figure 2. Timing Diagram
Rev. 0 | Page 4 of 28
ADL5811
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3.
Parameter
Rating
Supply Voltage, VPOS
5.5 V
CLK, DATA, LE
5.5 V
IF Output Bias
6.0 V
RF Input Power
LO Input Power
20 dBm
13 dBm
1.1 W
25°C/W
150°C
ESD CAUTION
Internal Power Dissipation
θJA (Exposed Paddle Soldered Down)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
−40°C to +85°C
−65°C to +150°C
Rev. 0 | Page 5 of 28
ADL5811
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC
RFCT
NC
RFIN
NC
NC
NC
NC
1
2
3
4
5
6
7
8
24 NC
23
22 NC
21 LOIP
20 LOIN
NC
ADL5811
TOP VIEW
(Not to Scale)
19
LE
18 DATA
17 CLK
NOTES
1. NC = NO CONNECT. CAN BE GROUNDED.
2. EXPOSED PAD MUST BE CONNECTED
TO GROUND.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 3, 5 to 8, 22 to 24, 27, 30
2
4
NC
RFCT
RFIN
No Connect. Can be grounded.
RF Balun Center Tap (AC Ground).
RF Input. Should be ac-coupled.
9, 11, 13, 15
10, 12, 14, 16, 25
17, 18, 19
20
VLO4, VLO3, VLO2, VLO1
Positive Supply Voltages for LO Amplifier.
Ground.
Serial Port Interface Control.
COMM
CLK, DATA, LE
LOIN
Ground Return for LO Input.
21
26
LOIP
IFGD
LO Input. Should be ac-coupled.
Supply Return for IF Amplifier. Must be grounded.
28, 29
IFOP, IFON
IF Differential Open-Collector Outputs. Should be pulled up to VCC using
external inductors.
31
32
IFGM
VPIF
EPAD
IF Amplifier Bias Control.
Supply Voltage for IF Amplifier.
Exposed pad must be connected to ground.
Rev. 0 | Page 6 of 28
ADL5811
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, RF power = −10 dBm, LO power = 0 dBm, R1 = 910 Ω, ZO = 50 Ω, optimum SPI settings,
unless otherwise noted.
220
210
200
190
180
170
160
150
140
130
120
90
80
70
60
50
40
30
20
10
T
T
T
= –40°C
= +25°C
= +85°C
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
A
A
A
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 4. Supply Current vs. RF Frequency
Figure 7. Input IP2 vs. RF Frequency
20
18
16
14
12
10
8
10
9
T
T
T
= –40°C
= +25°C
= +85°C
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
A
A
A
8
7
6
5
6
4
4
3
2
0
2
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 8. Input P1dB vs. RF Frequency
Figure 5. Power Conversion Gain vs. RF Frequency
16
15
14
13
12
11
10
9
45
40
35
30
25
20
15
10
T
T
T
= –40°C
= +25°C
= +85°C
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
A
A
A
8
7
6
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 9. SSB Noise Figure vs. RF Frequency
Figure 6. Input IP3 vs. RF Frequency
Rev. 0 | Page 7 of 28
ADL5811
235
80
75
70
65
60
55
50
45
40
35
30
RF = 1900MHz
RF = 1900MHz
V
V
V
= 4.75V
= 5.00V
= 5.25V
V
V
V
= 4.75V
= 5.00V
= 5.25V
POS
POS
POS
POS
POS
POS
225
215
205
195
185
175
165
155
145
135
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
Figure 10. Supply Current vs. Temperature
Figure 13. Input IP2 vs. Temperature
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
20
18
16
14
12
10
8
RF = 1900MHz
RF = 1900MHz
V
V
V
= 4.75V
= 5.00V
= 5.25V
V
V
V
= 4.75V
= 5.00V
= 5.25V
POS
POS
POS
POS
POS
POS
6
4
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
Figure 14. Input P1dB vs. Temperature
Figure 11. Power Conversion Gain vs. Temperature
35
33
31
29
27
25
23
21
19
17
15
15
14
13
12
11
10
9
RF = 1900MHz
RF = 1900MHz
V
V
V
= 4.75V
= 5.00V
= 5.25V
V
V
V
= 4.75V
= 5.00V
= 5.25V
POS
POS
POS
POS
POS
POS
8
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
Figure 12. Input IP3 vs. Temperature
Figure 15. SSB Noise Figure vs. Temperature
Rev. 0 | Page 8 of 28
ADL5811
200
195
190
185
180
175
170
165
160
80
70
60
50
40
30
20
10
0
RF = 900MHz
RF = 1900MHz
RF = 2500MHz
T
= 25°C
T
= 25°C
A
A
RF = 900MHz
RF = 1900MHz
RF = 2500MHz
30
80
130
180
230
280
330
380
430
30
80
130
180
230
280
330
380
430
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 16. Supply Current vs. IF Frequency
Figure 19. Input IP2 vs. IF Frequency
11
10
9
18
16
14
12
10
8
T
= 25°C
RF = 900MHz
RF = 1900MHz
RF = 2500MHz
T
= 25°C
RF = 900MHz
RF = 1900MHz
RF = 2500MHz
A
A
8
7
6
6
5
4
4
30
2
30
80
130
180
230
280
330
380
430
80
130
180
230
280
330
380
430
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 17. Power Conversion Gain vs. IF Frequency
Figure 20. Input P1dB vs. IF Frequency
30
39
28
27
26
25
24
23
22
20
18
16
14
12
10
8
T
= 25°C
RF = 900MHz
RF = 900MHz
RF = 1900MHz
RF = 2500MHz
T
= 25°C
A
A
RF = 1900MHz
RF = 2500MHz
6
4
30
30
80
130
180
230
280
330
380
430
80
130
180
230
280
330
380
430
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 21. SSB Noise Figure vs. IF Frequency
Figure 18. Input IP3 vs. IF Frequency
Rev. 0 | Page 9 of 28
ADL5811
11
20
18
16
14
12
10
8
T
= 25°C
RF = 900MHz
RF = 1900MHz
RF = 2500MHz
T
= 25°C
RF = 900MHz
RF = 1900MHz
RF = 2500MHz
A
A
10
9
8
7
6
5
4
6
3
4
–
6
–4
–2
0
2
4
6
8
10
10
10
–6
–4
–2
0
2
4
6
8
10
LO POWER (dBm)
LO POWER (dBm)
Figure 22. Power Conversion Gain vs. LO Power
Figure 25. Input P1dB vs. LO Power
35
33
31
29
27
25
23
21
19
17
15
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
T
T
T
= –40°C
= +25°C
= +85°C
T
= 25°C
RF = 900MHz
RF = 1900MHz
RF = 2500MHz
A
A
A
A
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
–6
–4
–2
0
2
4
6
8
RF FREQUENCY (MHz)
LO POWER (dBm)
Figure 23. Input IP3 vs. LO Power
Figure 26. IF/2 Spurious vs. RF Frequency, RF Power = −10 dBm
80
70
60
50
40
30
20
10
–55
T
= 25°C
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
A
–60
–65
–70
–75
–80
–85
–90
RF = 900MHz
RF = 1900MHz
RF = 2500MHz
–
6
–4
–2
0
2
4
6
8
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
LO POWER (dBm)
RF FREQUENCY (MHz)
Figure 24. Input IP2 vs. LO Power
Figure 27. IF/3 Spurious vs. RF Frequency, RF Power = −10 dBm
Rev. 0 | Page 10 of 28
ADL5811
500
400
300
200
100
0
10
100
T
= 25°C
RF = 900MHz
MEAN: 7.5
SD: 0.12%
A
RF = 1900MHz
RF = 2500MHz
8
6
4
2
0
80
60
40
20
0
7.1
7.3
7.5
7.7
7.9
30
80
130
180
230
280
330
380
430
CONVERSION GAIN (dB)
IF FREQUENCY (MHz)
Figure 28. Conversion Gain Distribution
Figure 31. IF Output Impedance (R Parallel C Equivalent)
100
0
MEAN: 27.5
SD: 0.36%
T = +25°C
A
–5
80
60
40
20
0
–10
–15
–20
–25
–30
–35
–40
700 900 1100 1300 1500 1700 1900 2100 2300 2500
2700
23.5
25.5
27.5
29.5
31.5
RF FREQUENCY (MHz)
INPUT IP3 (dBm)
Figure 32. RF Port Return Loss, Fixed IF vs. RF Frequency
Figure 29. Input IP3 Distribution
0
–3
100
MEAN: 11.68
SD: 0.36%
T = 25°C
A
80
60
40
20
0
–6
–9
–12
–15
–18
–21
–24
10.5
11.0
11.5
12.0
12.5
500 700 900 1100 1300 1500 1700 1900 2100 2300 2500
INPUT P1dB (dBm)
LO FREQUENCY (MHz)
Figure 33. LO Return Loss
Figure 30. Input P1dB Distribution
Rev. 0 | Page 11 of 28
ADL5811
0
T
0
–10
–20
–30
–40
–50
–60
–70
= –40°C
= +25°C
= +85°C
2LO-TO-IF
2LO-TO-RF
T
= 25°C
A
T
T
A
A
A
–10
–20
–30
–40
–50
–60
–70
–80
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
500 700 900 1100 1300 1500 1700 1900 2100 2300 2500
RF FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 34. RF-to-IF Isolation vs. RF Frequency
Figure 37. 2XLO Leakage vs. LO Frequency
0
–10
–20
–30
–40
–50
–60
–70
–80
–10
–20
–30
–40
–50
–60
–70
–80
T
T
T
= –40°C
= +25°C
= +85°C
T = 25°C
A
3LO-TO-IF
3LO-TO-RF
A
A
A
500 700 900 1100 1300 1500 1700 1900 2100 2300 2500
500 700 900 1100 1300 1500 1700 1900 2100 2300 2500
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 38. 3XLO Leakage vs. LO Frequency
Figure 35. LO-to-IF Leakage vs. LO Frequency
0
–10
–20
–30
–40
–50
–60
–70
–80
14
13
12
11
10
9
16
15
14
13
12
11
10
9
T
T
T
= –40°C
= +25°C
= +85°C
T = +25°C
A
A
A
A
NOISE FIGURE
8
7
GAIN
6
8
5
7
VGS = 0
VGS = 1
VGS = 2
VGS = 3
VGS = 4
VGS = 5
VGS = 6
VGS = 7
4
500 700 900 1100 1300 1500 1700 1900 2100 2300 2500
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
LO FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 36. LO-to-RF Leakage vs. LO Frequency
Figure 39. Power Conversion Gain and SSB Noise Figure vs. RF Frequency
for All VGS Settings
Rev. 0 | Page 12 of 28
ADL5811
35
30
25
20
15
10
5
27
24
21
18
15
12
9
240
220
200
180
160
140
120
100
VGS = 0
VGS = 1
VGS = 2
VGS = 3
VGS = 4
VGS = 5
VGS = 6
VGS = 7
T = 25°C
A
T
= +25°C
RF = 900MHz
RF = 1900MHz
RF = 2500MHz
A
INPUT IP3
INPUT P1dB
0
6
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800
IF BIAS RESISTOR VALUE (Ω)
Figure 40. Input IP3 and Input P1dB vs. RF Frequency for All VGS Settings
Figure 42. Supply Current vs. IF Bias Resistor Value
35
20
18
16
14
12
10
8
32
RF = 900MHz
T
= 25°C
RF = 900MHz
RF = 1900MHz
RF = 2500MHz
A
RF = 1900MHz
RF = 2500MHz
30
INPUT IP3
28
24
20
16
12
8
25
20
15
10
5
NOISE FIGURE
GAIN
6
4
T
= +25°C
5 10
A
4
0
0
–30
–25
–20
–15
–10
–5
0
600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800
BLOCKER POWER (dBm)
IF BIAS RESISTOR VALUE (Ω)
Figure 41. SSB Noise Figure vs. 10 MHz Offset Blocker Level
Figure 43. Power Conversion Gain, SSB Noise Figure, and Input IP3 vs.
IF Bias Resistor Value
Rev. 0 | Page 13 of 28
ADL5811
18
17
16
15
14
13
12
11
10
9
11
RFB = 0
RFB = 0
RFB = 1
RFB = 2
RFB = 3
RFB = 4
RFB = 5
RFB = 6
RFB = 7
T
= +25°C
T
= +25°C
A
A
RFB = 1
RFB = 2
RFB = 3
RFB = 4
RFB = 5
RFB = 6
RFB = 7
10
9
8
7
6
5
4
3
2
1
8
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 46. Input P1dB vs. RF Frequency for All RFB Settings
Figure 44. Conversion Gain vs. RF Frequency for All RFB Settings
16
32
RFB = 0
T
= +25°C
RFB = 0
A
T
= +25°C
RFB = 1
RFB = 2
RFB = 3
RFB = 4
RFB = 5
RFB = 6
RFB = 7
A
RFB = 1
RFB = 2
RFB = 3
RFB = 4
RFB = 5
RFB = 6
RFB = 7
15
14
13
12
11
10
9
31
30
29
28
27
26
25
24
23
22
8
7
6
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 47. SSB Noise Figure vs. RF Frequency for All RFB Settings
Figure 45. Input IP3 vs. RF Frequency for All RFB Settings
Rev. 0 | Page 14 of 28
ADL5811
21
19
17
15
13
11
9
12
10
8
LPF = 0
LPF = 1
LPF = 2
LPF = 3
LPF = 0
LPF = 1
LPF = 2
LPF = 3
T
= +25°C
T
= +25°C
A
A
RFB0
RFB0
6
RFB7
4
2
RFB7
0
7
5
–2
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 50. Input P1dB vs. RF Frequency for All LPF Settings at RFB7 and RFB0
Figure 48. Conversion Gain vs. RF Frequency for All LPF Settings at
RFB7 and RFB0
20
35
LPF = 0
LPF = 1
LPF = 2
LPF = 3
T
= +25°C
T
= +25°C
A
A
33
31
29
27
25
23
21
19
17
15
18
16
14
12
10
8
RFB0
RFB0
RFB7
RFB7
6
LPF = 0
LPF = 1
LPF = 2
LPF = 3
4
2
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 51. SSB Noise Figure vs. RF Frequency for
All LPF Settings at RFB7 and RFB0
Figure 49. Input IP3 vs. RF Frequency for All LPF Settings at RFB7 and RFB0
Rev. 0 | Page 15 of 28
ADL5811
3.6 V PERFORMANCE
VS = 3.6 V, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, RF power = −10 dBm, LO power = 0 dBm, R1 = 800 Ω, ZO = 50 Ω, optimum SPI settings,
unless otherwise noted.
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
T
T
T
= –40°C
= +25°C
= +85°C
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
A
A
A
80
70
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 52. Supply Current vs. RF Frequency at 3.6 V
Figure 55. Input IP2 vs. RF Frequency at 3.6 V
14
12
10
8
24
21
18
15
12
9
T
T
T
= –40°C
= +25°C
= +85°C
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
A
A
A
6
4
6
2
3
0
0
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 56. Input P1dB vs. RF Frequency at 3.6 V
Figure 53. Power Conversion Gain vs. RF Frequency at 3.6 V
24
21
18
15
12
9
35
30
25
20
15
10
5
T
T
T
= –40°C
= +25°C
= +85°C
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
A
A
A
6
3
0
0
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 57. SSB Noise Figure vs. RF Frequency at 3.6 V
Figure 54. Input IP3 vs. RF Frequency at 3.6 V
Rev. 0 | Page 16 of 28
ADL5811
SPURIOUS PERFORMANCE
(N × fRF) − (M × fLO) spur measurements were made using the standard evaluation board. Mixer spurious products are measured in
dBc from the IF output power level. Data was measured only for frequencies less than 6 GHz. Typical noise floor of the measurement
system = −100 dBm.
5 V Performance
VS = 5 V, TA = 25°C, RF power = −10 dBm, LO power = 0 dBm, R1 = 910 Ω, ZO = 50 Ω, optimum SPI settings, unless otherwise noted.
Table 5. RF = 900 MHz, LO = 697 MHz
M
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
−54.2
0.0
−31.4
−38.7
−69.6
−41.5
−19.6
−53.4
−29.4
−51.6
−72.5
−58.5
−38.0
−82.3
−49.3
−62.9
−93.5
−70.5
−52.4
−97.4
−52.9
−70.2
−93.0
1
−37.8
−65.0
−94.0
−57.9
−98.8
2
−54.4
−86.7
<−100 <−100
3
<−100 −91.0
<−100 −95.3
<−100 <−100 <−100 <−100 <−100 <−100 <−100
4
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
5
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
6
7
N
8
9
10
11
12
13
14
15
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100
Table 6. RF = 1900 MHz, LO = 1697 MHz
M
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
−34.9
0.0
−30.7 −66.0
−56.6 −51.3
−71.5 −85.2
1
−33.2
−75.0
−77.8
−80.3
−94.8
2
−78.5
<−100
3
<−100 <−100 <−100 −89.5
<−100 <−100 <−100
<−100
<−100 <−100
4
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
5
6
7
N
8
9
10
11
12
13
14
15
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100
<−100 <−100 <−100
<−100 <−100
Rev. 0 | Page 17 of 28
ADL5811
Table 7. RF = 2500 MHz, LO = 2297 MHz
M
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
−28.6
0.0
−45.7
−53.0
−60.5
1
−32.5
−91.2
−52.4
−80.8
2
−82.8
−97.3
3
<−100 <−100 −87.7
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100
<−100 <−100
4
5
6
7
N
8
9
10
11
12
13
14
15
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100
<−100 <−100 <−100
<−100 <−100
3.6 V Performance
VS = 3.6 V, TA = 25°C, RF power = −10 dBm, LO power = 0 dBm, R1 = 800 Ω, ZO = 50 Ω, optimum SPI settings, unless otherwise noted.
Table 8. RF = 900 MHz, LO = 697 MHz
M
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
−45.5
0.0
−35.1
−37.3
−78.2
−44.1
−18.9
−54.8
−30.2
−54.8
−62.8
−89.6
−49.9
−40.4
−83.1
−79.4
−48.7
−62.4
−78.3
−66.6
−53.2
−96.1
−66.5
−73.0
−79.5
1
−41.0
−59.2
−90.0
−66.8
−96.2
2
−54.7
−81.9
−96.2
<−100
3
<−100 −73.9
<−100 −95.3
<−100 <−100 <−100 <−100 <−100
4
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
5
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
6
7
N
8
9
10
11
12
13
14
15
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100
Rev. 0 | Page 18 of 28
ADL5811
Table 9. RF = 1900 MHz, LO = 1697 MHz
M
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
−46.6
0.0
−30.5
−57.0
−69.2
−78.5
−53.8
−72.8
1
−33.4
−68.9
−79.5
−75.2
−94.0
2
−77.2
<−100
3
<−100 <−100 <−100 −74.4
<−100 <−100
4
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
5
6
7
N
8
9
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
10
11
12
13
14
15
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100
<−100 <−100 <−100
<−100 <−100
Table 10. RF = 2500 MHz, LO = 2297 MHz
M
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
−30.0
0.0
−51.1
−53.6
−65.5
1
−32.1
−89.0
−51.7
−72.9
2
−78.0
−88.2
3
<−100 <−100 −73.5
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100
<−100 <−100
4
5
6
7
N
8
9
10
11
12
13
14
15
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100
<−100 <−100 <−100
<−100 <−100
Rev. 0 | Page 19 of 28
ADL5811
CIRCUIT DESCRIPTION
The ADL5811 consists of two primary components: the RF
subsystem and the LO subsystem. The combination of design,
process, and packaging technology allows the functions of these
subsystems to be integrated into a single die, using mature
packaging and interconnection technologies to provide a high
performance device with excellent electrical, mechanical, and
thermal properties. The wideband frequency response and
flexible frequency programming simplifies the receiver design,
saves on-board space, and minimizes the need for external
components.
The resulting balanced RF signal is applied to a passive mixer
that commutates the RF input in accordance with the output of the
LO subsystem. The passive mixer is essentially a balanced, low
loss switch that adds minimum noise to the frequency translation.
The only noise contribution from the mixer is due to the resistive
loss of the switches, which is in the order of a few ohms.
Because the mixer is inherently broadband and bidirectional, it
is necessary to properly terminate all idler (M × N product)
frequencies generated by the mixing process. Terminating the
mixer avoids the generation of unwanted intermodulation
products and reduces the level of unwanted signals at the input
of the IF amplifier, where high peak signal levels can compromise
the compression and intermodulation performance of the
system. This termination is accomplished by the addition of a
programmable low-pass filter network between the IF amplifier
and the mixer and in the feedback elements in the IF amplifier.
The RF subsystem consists of an integrated, tunable, low loss RF
balun; a double balanced, passive MOSFET mixer; a tunable sum
termination network; and an IF amplifier.
The LO subsystem consists of a multistage limiting LO amplifier.
The purpose of the LO subsystem is to provide a large, fixed
amplitude, balanced signal to drive the mixer independent of
the level of the LO input. A block diagram of the device is
shown in Figure 58.
The IF amplifier is a balanced feedback design that simultaneously
provides the desired gain, noise figure, and input impedance
that is required to achieve the overall performance. The balanced
open-collector output of the IF amplifier, with an impedance
modified by the feedback within the amplifier, permits the
output to be connected directly to a high impedance filter, a
differential amplifier, or an analog-to-digital converter (ADC)
input while providing optimum second-order intermodulation
suppression. The differential output impedance of the IF amplifier
is approximately 200 Ω. If operation in a 50 Ω system is desired,
the output can be transformed to 50 Ω by using a 4:1 transformer
or an LC impedance matching network.
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
NC
RFCT
NC
NC
NC
ADL5811
NC
RFIN
NC
LOIP
LOIN
LE
NC
SERIAL
PORT
INTERFACE
BIAS
GEN
NC
DATA
CLK
The intermodulation performance of the design is generally
limited by the IF amplifier. The IP3 performance can be optimized
by adjusting the low-pass filter between the mixer and the IF
amplifier. Further optimization can be made by adjusting the IF
current with an external resistor. Figure 42 and Figure 43
illustrate how various IF resistors affect the performance with a 5 V
supply. Additionally, dc current can be saved by increasing the
IF resistor. It is permissible to reduce the IF amplifier’s dc
supply voltage to as low as 3.3 V, further reducing the dissipated
power of the part. (Note that no performance enhancement is
obtained by reducing the value of these resistors, and excessive
dc power dissipation may result.)
NC
9
10
11
12
13
14
15
16
Figure 58. Block Diagram
RF SUBSYSTEM
The single-ended, 50 Ω RF input is internally transformed to a
balanced signal using a tunable, low loss, unbalanced-to-balanced
(balun) transformer. This transformer is made possible by an
extremely low loss metal stack, which provides both excellent
balance and dc isolation for the RF port. Although the port can
be dc connected, it is recommended that a blocking capacitor be
used to avoid running excessive dc current through the part.
The RF balun can easily support an RF input frequency range of
700 MHz to 2800 MHz. This balun is tuned over the frequency
range by SPI controlled switched capacitor networks at the
input and output of the RF balun.
Because the mixer is bidirectional, the tuning of the RF and IF
ports is linked and it is possible for the user to optimize gain,
noise figure, IP3, and impedance match via the SPI. This feature
permits high performance operation and is achieved entirely
using SPI control. Additionally, the performance of the mixer can
be improved by setting the optimum gate voltage on the passive
mixer, which is also controlled by the SPI to enable optimum
performance of the part. See the Applications Information
section for examples of this tuning.
Rev. 0 | Page 20 of 28
ADL5811
obtained with a 0 dBm input level; however, the circuit continues to
function at considerably lower levels of LO input power.
LO SUBSYSTEM
The LO amplifier is designed to provide a large signal level to
the mixer to obtain optimum intermodulation and compression
performance. The resulting LO amplifier provides very high
performance over a wide range of LO input frequencies.
The performance of this amplifier is critical in achieving a high
intercept passive mixer without degrading the noise floor of the
system. This is a critical requirement in an interferer rich
environment, such as cellular infrastructure, where blocking
interferers can limit mixer performance. Blocking dynamic
range can benefit from a higher level of LO drive, which pushes
the LO amplifier stages harder into compression and causes them
to switch harder and to limit the small signal gain of the chain.
Both of these conditions are beneficial to low noise figure under
blocking. NF under blocking can be improved several decibels
for LO input power levels above 0 dBm.
The ideal waveshape for switching the passive mixer is a square
wave at the LO frequency to cause the mixer to switch through
its resistive region (from on to off and off to on) as rapidly as
possible. While it has always been possible to generate such a
square wave, the amount of dc current required to generate a
large amplitude square wave at high frequencies has made it
impractical to create such a mixer. Novel circuitry within the
ADL5811 permits the generation of a near-square wave output
at frequencies of up to 2800 MHz with dc current that compares
favorably with that employed by narrow-band passive mixers.
The LO amplifier topology inherently minimizes the dc current
based on the LO operating voltage and the LO operating frequency.
It is permissible to reduce the LO supply voltage down as low as
3.6 V, which drops the dc current rapidly. The mixer dynamic
range varies accordingly with the LO supply voltage. No external
biasing resistor is required for optimizing the LO amplifier.
The input stages of the LO amplifier provide common-mode
rejection, permitting the LO input to be driven either single ended
or balanced. For a single-ended input, either LOIP or LOIN can
be grounded. It is desirable to dc block the LO inputs to avoid
damaging the part by the accidental application of a large dc
voltage to the part. In addition, the LO inputs are internally dc
blocked.
In addition, the ADL5811 has a power-down mode that can be
used with any supply voltage applied to the part.
All of the SPI inputs are designed to work with any logic family that
provides a Logic 0 input level of less than 0.4 V and a Logic 1 input
level that exceeds 1.4 V.
Because the LO amplifier is inherently wideband, the ADL5811
can be driven with either high-side or low-side LO by simply
setting the optimum RF balun and LPF inputs to the SPI.
All pins, including the RF pins, are ESD protected and have been
tested up to a level of 2000 V HBM and 1250 V CDM.
The LO amplifier converts a variable level, single or balanced input
signal (−6 dBm to +10 dBm) to a hard voltage limited, balanced
signal internally to drive the mixer. Excellent performance can be
Rev. 0 | Page 21 of 28
ADL5811
APPLICATIONS INFORMATION
BASIC CONNECTIONS
BIAS RESISTOR SELECTION
An external resistor, R1, is used to adjust the bias current of the
integrated amplifier at the IF terminal. It is necessary to have a
sufficient amount of current to bias both the internal IF amplifier to
optimize dc current vs. optimum input IP3 performance. Figure 42
and Figure 43 provide the reference for the bias resistor selection
when lower power consumption is considered at the expense of
conversion gain and input IP3 performance.
The ADL5811 mixer is designed to downconvert radio
frequencies (RF) primarily between 700 MHz and 2800 MHz
to lower intermediate frequencies (IF) between 30 MHz and
450 MHz. Figure 59 depicts the basic connections of the mixer.
It is recommended to ac couple RF and LO input ports to
prevent nonzero dc voltages from damaging the RF balun or LO
input circuit. A RFIN capacitor value of 22 pF is recommended.
VGS PROGRAMMING
IF PORT
The ADL5811 allows programmability for internal gate-to-source
voltages for optimizing mixer performance over the desired
frequency bands. The ADL5811 defaults the VGS setting to 0.
Power conversion gain, input IP3, NF, and input P1dB can be
optimized, as shown in Figure 39 and Figure 40.
The mixer differential IF interface requires pull-up choke inductors
to bias the open-collector outputs and to set the output match.
The shunting impedance of the choke inductors used to couple
dc current into the IF amplifier should be selected to provide
the desired output return loss.
The real part of the output impedance is approximately 200 Ω,
as seen in Figure 31, which matches many commonly used SAW
filters without the need for a transformer. This results in a voltage
conversion gain that is approximately 6 dB higher than the power
conversion gain. When a 50 Ω output impedance is needed, use a
4:1 impedance transformer, as shown in Figure 59.
L1
C3
T1
IFOP
IFON
120pF
470nH
TC4-1W+
VCC
L2
470nH
R20
C1
0.1µF
OPEN
C5
120pF
C4
120pF
C2
0.1µF
R21
0ꢀ
R1
910ꢀ
C8
0.1µF
PAD
C7
1
24
23
22
21
20
19
18
17
NC
RFCT
NC
RFIN
NC
NC
NC
NC
NC
LOIP
LOIN
LE
DATA
CLK
100pF
2
3
4
5
6
7
8
C17
22pF
LOIP
RFIN
ADL5811
C6
22pF
LE
DATA
CLK
NC
NC
VCC
C23
10pF
VCC
VCC
C18
10pF
C19
10pF
VCC
C20
10pF
AGND
VPOS
BLK
RED
VCC
Figure 59. Basic Connections
Rev. 0 | Page 22 of 28
ADL5811
LOW-PASS FILTER PROGRAMMING
RF BALUN PROGRAMMING
The ADL5811 allows programmability for the low-pass filter
terminating the mixer output. This filter helps to block sum term
mixing products at the expense of some noise figure and gain
and can significantly increase input IP3. The ADL5811 defaults the
LPF setting to 0. Power conversion gain, input IP3, NF, and input
P1dB can be optimized, as shown in Figure 48 to Figure 51.
The ADL5811 allows programmability for the RF balun by
allowing capacitance to be switched into both the input and the
output, which allows the balun to be tuned to cover the entire
frequency band (700 MHz to 2800 MHz). Under most circum-
stances, the input and output can be tuned together though
sometimes it may be advantageous for matching reasons to tune
them separately. The ADL5811 defaults the RFB setting to 0. Power
conversion gain, input IP3, NF, and input P1dB can be optimized,
as shown in Figure 44 to Figure 47.
Rev. 0 | Page 23 of 28
ADL5811
REGISTER STRUCTURE
Figure 60 illustrates the register map of the ADL5811. The
ADL5811 only uses Register 5. Because of this, set all of the
control bits to 5. When set to 0, the ENBL bit, DB7, enables the
part. By setting this bit to 1, the mixer is powered down. The
RFB IN CAP DAC and RFB OUT CAP DAC bits are used to tune
the RF balun. In most cases, they are tuned together with the
higher settings, 7, tuning for the low frequencies, and with the
lower settings, 0, tuning for the high frequencies. There are
times where it becomes advantageous to tune the input and
output of the RF balun separately and that ability is provided.
The LPF bits control the low-pass filter settings at the IF output.
The ability to tune the low-pass filter allows some trade-off
between gain, noise figure, and input IP3 with higher settings,
7, providing higher input IP3 at the cost of some gain and noise
figure, and lower settings, 0, providing higher gain and lower
NF at the cost of lower input IP3. The VGS bits control the VGS
settings of the mixer core and allow further tuning of the device.
Table 11 lists the optimum settings characterized for each
frequency band. All register bits default to 0.
RESERVED
VGS
LPF
RFB OUT CAP DAC
RFB IN CAP DAC
ENBL
RESERVED
CONTROL BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6
DB5 DB4 DB3 DB2 DB1 DB0
C3(1) C2(0) C1(1)
0
0
VGS2 VGS1 VGS0 LPF1 LPF0
0
CDO2 DCDO1 CDO0
0
CDI2 CDI1 CDI0
0
EN
0
0
0
0
VGS2 VGS1 VGS0
VGS SETTING
0
'
0
'
0
'
0
'
1
1
1
7
MEN
0
1
MAIN ENABLE
DEVICE ENABLED
DEVICE DISABLED
LPF1 LPF0 LOW PASS FILTER SETTING
0
'
0
'
0
'
CDI2 CDI1 CDI0 RF BALUN INTPUT TUNING
1
1
3
0
'
0
'
0
'
0
'
1
1
1
7
CDO2 CDO1 CDO0 RF BALUN OUTPUT TUNING
0
'
0
'
0
'
0
'
1
1
1
7
Figure 60. ADL5811 Register Maps
Table 11. Optimum Settings
RF Frequency (MHz)
700
800
900
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
LO Frequency (MHz)
497
597
697
797
897
997
1097
1197
1297
1397
1497
1597
1697
1797
1897
1997
2097
2197
2297
2397
2497
2597
VGS
3
1
2
1
3
3
3
3
3
3
3
3
3
3
3
2
LPF
1
1
1
1
1
3
3
3
3
3
3
3
3
3
3
3
2
2
3
2
2
2
RFB OUT CAP DAC
RFB IN CAP DAC
7
6
6
4
7
5
5
4
4
3
3
3
2
2
1
2
2
2
1
2
2
1
7
6
6
4
7
5
5
4
4
3
3
3
2
2
1
2
2
2
1
2
2
1
3
2
3
3
1
3
Rev. 0 | Page 24 of 28
ADL5811
EVALUATION BOARD
An evaluation board is available for the ADL5811. The standard
evaluation board schematic is presented in Figure 61. The USB
interface circuitry schematic is presented in Figure 64. The
evaluation board layout is shown in Figure 62 and Figure 63.
The evaluation board is fabricated using Rogers® 3003 material.
Table 12 details the configuration for the mixer characterization.
The evaluation board software is available on www.analog.com.
C3
L1
T1
IFOP
IFON
120pF
470nH
TC4-1W+
VCC
3
4
L2
470nH
R20
C1
0.1µF
2
1
OPEN
6
C5
120pF
C4
120pF
C2
0.1µF
R21
0ꢀ
R1
910ꢀ
C8
0.1µF
PAD
C7
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
NC
RFCT
NC
RFIN
NC
NC
NC
NC
NC
LOIP
LOIN
LE
DATA
CLK
100pF
C17
22pF
LOIP
RFIN
ADL5811
C6
22pF
LE
DATA
CLK
NC
NC
VCC
C23
10pF
VCC
VCC
C18
10pF
C19
10pF
VCC
C20
10pF
AGND
VPOS
BLK
RED
VCC
Figure 61. Evaluation Board Schematic
Table 12. Evaluation Board Configuration
Components Description
C1, C2, C8, C18, C19, Power supply decoupling. Nominal supply decoupling consists of a
Default Conditions
C1, C2 = 0.1 μF (size 0402),
C20, C23
0.1 μF capacitor to ground in parallel with a 10 pF capacitor to
ground positioned as close to the device as possible.
C8, C18, C19, C20, C23 = 10 pF (size 0402)
C6, C7, RFIN
RF input interface. The input channel is ac-coupled through C6.
C7 provides bypassing for the center tap of the RF input balun.
C6 = 22 pF (size 0402), C7 = 100 pF (size 0402)
C3, C4, C5, L1, L2,
R20, R21, T1, IFOP,
IFON
IF output interface. The open-collector IF output interfaces are
biased through pull-up choke inductors, L1 and L2. T1 is a 4:1
impedance transformer used to provide a single-ended IF output
interface, with C5 providing center-tap bypassing. Remove R21 for
balanced output operation.
C3, C4, C5 = 120 pF (size 0402),
L1, L2 = 470 nH (size 0603),
R20 = open,
R21 = 0 Ω (size 0402),
T1 = TC4-1W+ (Mini-Circuits®)
C17, LOIP
R1
LO interface. C17 provides ac coupling for the LOIP local oscillator input.
Bias control. R1 sets the bias point for the internal IF amplifier.
C17 = 22 pF (size 0402)
R1 = 910 Ω (size 0402)
Rev. 0 | Page 25 of 28
ADL5811
Figure 62. Evaluation Board Top Layer
Figure 63. Evaluation Board Bottom Layer
Rev. 0 | Page 26 of 28
ADL5811
Y2
24.000000MHZ
1
3
5V_USB
C41
CASE
22PF
2
4
C40
22PF
DGND
DGND
DGND
J6
C34
1
2
3
4
5
3V3_USB
10PF
C35
3V3_USB
C36
U7
8
DGND
0.1UF
5
G1
G2
G3
G4
10PF
C37
VCC
1
R7
2K
R8
2K
A0
A1
GND
PINS
2
3
6
7
3V3_USB
VCC
A2
SCL
DGND
0.1UF
SDA
897-43-005-00-100001
DGND
WC_N
GND
U6
P1
4
AVCC
24LC64-I-SN
4
8
9
13
54
29
30
31
1
2
3
XTALOUT
DPLUS
DMINUS
IFCLK
SAMTECTSW10608GS3PIN
LE
DGND
CLKOUT
CTL0_FLAGA
CTL1_FLAGB
CTL2_FLAGC
R11
0
R17
0
15
16
SCL
33
34
35
36
37
38
39
40
PA0_INT0_N
PA1_INT1_N
PA2_SLOE
R12
0
R18
0
SDA
DATA
R9
3V3_USB
R10
100K
PA3_WU2
100K
PA4_FIFOADR0
PA5_FIFOADR1
PA6_PKTEND
5
R13
R19
0
XTALIN
RESET_N
CLK
42
C38
0.1UF
C39
0.1UF
0
PA7_FLAGD_SLCS_N
C49
C50
R15
1K
18
19
20
21
22
23
24
25
45
46
47
48
49
50
51
52
R14
1K
R16
1K
C51
TBD0402
330PF
PB0_FD0
PB1_FD1
PB2_FD2
PB3_FD3
PB4_FD4
PB5_FD5
PB6_FD6
PB7_FD7
PD0_FD8
PD1_FD9
PD2_FD10
PD3_FD11
PD4_FD12
PD5_FD13
PD6_FD14
PD7_FD15
TBD0402
330PF
DNI
TBD0402
330PF
DNI
44
14
WAKEUP
RESERVED
DGND
DNI
DNI
DNI
DNI
DGND
DGND
DGND
DGND
DGND
DGND
1
2
RDY0_SLRD
RDY1_SLWR
DGND
DGND
AGND
GND
PAD
CY7C68013A-56LTXC
DGND
3V3_USB
5V_USB
3P3V
ORG
3V3_USB
1
DNI
U5
DECOUPLING FOR U6
C31
1.0UF
C33
1.0UF
R4
2K
C32
1000PF
R6
140K
R3
7
8
6
1
2
3
IN1
OUT1
0
DGND
IN2 OUT2
DGND
A
SD_N
PAD
FB
GND
DGND
AGND
C42
0.1UF
C43
0.1UF
C44
0.1UF
C45
0.1UF
C46
0.1UF
C47
0.1UF
C48
0.1UF
PAD
5
D1
C
R5
78.7K
DGND
DGND
1
BLK
DGND
DNI
DGND
DGND
DGND
ADP3334ACPZ
Figure 64. USB Interface Circuitry on the Evaluation Board
Rev. 0 | Page 27 of 28
ADL5811
OUTLINE DIMENSIONS
5.10
5.00 SQ
4.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
25
32
24
1
0.50
BSC
3.45
3.30 SQ
3.15
EXPOSED
PAD
17
8
16
9
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.
Figure 65. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5 mm Body, Very Very Thin Quad (CP-32-13)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
Quantity
ADL5811ACPZ-R7
ADL5811-EVALZ
−40°C to +85°C
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Evaluation Board
CP-32-13
1500
1 Z = RoHS Compliant Part.
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09912-0-7/11(0)
Rev. 0 | Page 28 of 28
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