ADM1014 [ADI]
Dual PCI Hot-PlugTM Controller; 双PCI热PlugTM控制器
| 型号： | ADM1014 |
| 厂家： | 
ADI |
| 描述： | Dual PCI Hot-PlugTM Controller |
| 文件： | 总12页 (文件大小：165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual PCI Hot-PlugTM Controller
ADM1014
a
Preliminary Technical Data
PAUXONA 30
3.3V Cmos
Input
7
AUXGA
+3.3VAux
31
AUXINA
S
G
P-CHANNEL
MOSFET
Q
RESET
FAULT
LATCH
SET
3.3V Cmos
Output
D
OVERCURRENT AND
UNDERVOLTAGE
COMPARATORS
FOR +3.3VAUX
FAUXA
8
AUXOA
5
Q
AUXINA
AUXINA
3.3VAUX
POWER-ON
RESET
EXTERNAL
N-CHANNEL
POWER
LOW WHEN
AUXINA < 2.5V
CHANNEL A
100µA
VOCSET
MOSFETS
6
OCSET
COMMON TO BOTH CHANNELS
+5V
IN
+3.3V
IN
CIRCUIT OPERATES FROM 3.3VAUX POWER SUPPLY
CIRCUIT OPERATES FROM 3.3VAUX AND +12V POWER SUPPLY
3V5VGA
33
5VSA
34
35
OVERCURRENT AND
UNDERVOLTAGE
COMPARATORS
FOR +5V
RSENSE5A
CHANNEL A
5VISENA
3VSA
OVERCURRENT AND
UNDERVOLTAGE
COMPARATORS
FOR +3.3V
36
PWRONA
FLTNA
GND
3
RSENSE3A
3VISENA
37
9
12VGA
Q
RESET
FAULT
LATCH
SET
+3.3V
OUTA
+5V
OUTA
29
12VIN
A
S
G
P-CHANNEL
MOSFET
4
Q
OVERCURRENT AND
UNDERVOLTAGE
COMPARATORS
FOR +12V
D
10
2
12VOA
-12VGA
-12VINA
12VIN
A
12V IN
POWER-ON
RESET
12VIN
A
5V
COMBINING
LOGIC
REGULATOR
38
32
S
LOW WHEN
12VINA <
10V
G
N-CHANNEL
MOSFET
COMMON TO BOTH CHANNELS
OVERCURRENT
COMPARATOR
FOR -12V
D
1
-12VOA
EXTERNAL
N-CHANNEL
POWER
MOSFETS
14
26
13
AUXGB
AUXINB
+3.3V
IN
+5V
IN
AUXOB
3V5VGB
PAUXONB
27
25
+3.3VAux
5VSB
24
23
CHANNEL B
RSENSE5B
5VISENB
FAUXB
15
17
( IDENTICAL TO CHANNEL A )
3VSB
22
21
RSENSE3B
PWRONB
3VISENB
12VGB
12VINB
12
28
+5V
OUTA
+3.3V
OUTA
11
12VOB
FLTNB
16
18
20
-12VGB
-12VINB
19 -12VOB
FUNC TIO NAL BLO C K D IAGRAM
REV. PrN 1/02
T M
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
Hot Plug is a trademark of Core International, Inc.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:
Fax: 781/326-8703
781/329-4700
www.analog.com
© Analog Devices, Inc., 2002
ADM1014–SPECIFICATIONS
T he ADM1014 operates from a +12V and +3.3V AUX supply
and controls five independent supplies (+3.3V, +3.3VAUX,
+5V, +12V and –12V) on two separate channels (A and B).
T he power switches for the +3.3VAUX, +12V and –12V
supplies are integrated onto the chip, and internal current
limiting is provided. For the +3.3V and +5V supplies, the
device drives external, N-channel, power MOSFET s, and
provides overcurrent protection by sensing the voltage drop
across external current-sense resistors.
FEATURES
Co n t ro ls Tw o P CI S lo t s
Co n t ro ls a ll Fo u r P CI S u p p lie s , +3 .3 V, +5 V, +1 2 V,
-1 2 V, p lu s 3 .3 V a u xilia ry s u p p ly
In t e rn a l MOS FET S w it c h e s fo r +3 .3 V AUX, +1 2 V
a n d –1 2 V o u t p u t s
Ad ju s t a b le Ove rc u rre n t P ro t e c t io n fo r a ll Ou t p u t s
Un d e rvo lt a g e P ro t e c t io n o n +3 .3 V, +5 V, +1 2 V a n d
+3 .3 V AUX S u p p lie s
Op e n -Dra in Fa u lt Ou t p u t w it h Ad ju s t a b le De la y
Lo g ic Co n t ro l o f Ou t p u t s
Ad ju s t a b le S o ft -s t a rt
T he current limits for all 10 supplies are set by a single resistor
to GND, connected to the OCSET pin.
Undervoltage sensing is provided on the +3.3V, +5V, +12V
and +3.3VAux supplies. Overcurrent sensing is provided on all
supplies. In the event of an overcurrent or undervoltage fault on
any of the outputs of either channel, all outputs on that channel
will be turned off.
AP P LICATIONS
Co m p a c t P CI
P CI Ho t -P lu g TM
GE NE RAL D E SC RIP TIO N
Turn-on slew rate may be controlled using eight external
capacitors, connected to the gate drives of all of the supplies.
T he ADM1014 is a dual PCI voltage bus controller that allows
hot-plugging of adapter cards into and out of an active or pas-
sive backplane. T he device requires only four external power
MOSFET s and a few discrete components for a complete
power-control solution for two PCI slots.
Logic control of the four main outputs is provided by the
PWRONA and PWRONB pins. When these pins are high, the
outputs are turned on, when low, the outputs are turned off.
T he +3.3VAUX supplies have their own control inputs,
PAUXA and PAUXB.
(Specifications are for each channel, 3.3VAUX=AUXINA=3.3V, V = 12VIN = +12V, -12VIN = -12V, Nominal 3.3V and 5V supplies to external
CC
MOSFETs, T = 0oC to +70oC, unless otherwise noted.)
A
Parameter
Min
T yp
Max
Units
T est Conditions/Comments
5V/ 3.3V SUP P LY CO NTRO L
5V Overcurrent T hreshold
-
8
42
80
4.65
110
9.75
-
A
See T ypical Application Diagram
VOCSET = 0.6V
VOCSET = 1.2V
5V Overcurrent T hreshold Voltage
5V Overcurrent T hreshold Voltage
5V Undervoltage T rip T hreshold
5V Undervoltage Fault Response T ime
5V T urn-On T ime
33
70
4.42
-
50
90
4.7
160
-
mV
mV
V
ns
ms
-
C3V5VG = 0.033µF, C5VOUT = 2000µF,
RL = 1⍀
See T ypical Application Diagram
OCSET = 0.6V
(PWRON High to 5VOUT = 4.75V)
3V Overcurrent T hreshold
-
10
52
98
2.86
110
9.6
-
A
3V Overcurrent T hreshold Voltage
3V Overcurrent T hreshold Voltage
3V Undervoltage T rip T hreshold
3V Undervoltage Fault Response T ime
3V5VG Undervoltage Enable T hreshold
Voltage
41
89
2.74
-
62
108
2.9
160
-
mV
mV
V
ns
V
OCSET = 1.2V
-
3V T urn-On T ime
(PWRON High to 3VOUT = 3.00V)
3V5VG Vout High
Gate Output Charge Current
Gate T urn-On T ime
-
9.75
-
ms
C3V5VG = 0.033µF, C3VOUT = 2000µF,
RL = 0.43⍀
PWRON = High, FLT N = High
PWRON = High, V3V5VG = 4V
C3V5VG = 0.033µF,3V5VG Rising 10% to 90%
11.5
19
-
11.8
25.0
280
-
29
-
V
µA
µs
(PWRON High to 3V5VG = 11V)
Gate T urn-Off T ime
-
2
-
µs
C3V5VG = 0.033µF, 3V5VG Falling 90% to 10%
+12V SUP P LY CO NTRO L
On Resistance of Internal PMOS
On Resistance of Internal PMOS
Overcurrent T hreshold
Overcurrent T hreshold
12V Undervoltage T rip T hreshold
Undervoltage Fault Response T ime
-
-
0.3
0.35
0.5
0.9
1.8
10.8
-
⍀
⍀
A
A
V
ns
PWRON = High, ID = 0.5A, TA= TJ= 25oC
PWRON = High, ID = 0.5A, TA= TJ= 70oC
VOCSET = 0.6V
0.35
0.75
1.50
10.6
110
0.6
1.25
10.25
-
VOCSET = 1.2V
–2–
REV. PrN 1/02
ADM1014–SPECIFICATIONS (Continued)
(Specifications are for each channel, 3.3VAUX=AUXINA=3.3V, V = 12VIN = +12V, -12VIN = -12V, Nominal 3.3V and 5V supplies to external
CC
MOSFETs, T = 0oC to +70oC, unless otherwise noted.)
A
Parameter
Min
T yp
Max
Units
T est Conditions/Comments
Gate Charge Current
T urn-On T ime
19
-
25.0
16
29
-
µA
ms
PWRON = High, V 12VG = 10V
C12VG = 0.033µF, 12VG Falling 90% - 10%
(PWRON High to 12VG = 1V)
T urn-Off T ime
-
4.5
-
µs
C12VG = 0.033µF, 12VG Rising 10% - 90%
-12V SUP P LY CO NTRO L
On Resistance of Internal NMOS
On Resistance of Internal NMOS
Overcurrent T hreshold
Overcurrent T hreshold
Gate Output Charge Current
T urn-On T ime
-
-
0.7
1
0.18
0.38
25
1
⍀
⍀
A
A
µA
ms
PWRON = High, ID = 0.1A, TA=TJ=25oC
PWRON = High, ID = 0.1A, TA=TJ=70oC
VOCSET = 0.6V
VOCSET = 1.2V
PWRON = High, VM12VG = -10V
CM12VG = 0.033µF, CM12VO= 50µF,RL= 120⍀
1.3
0.25
0.52
29
0.13
0.23
19
-
16
-
(PWRON High to M12VO = -10.8V)
T urn-Off T ime
M12VIN Input Bias Current
-
-
3
2.5
-
5
µs
mA
CM12VG=0.033µF,M12VG Falling 90% -10%
PWRON = High
+3.3VAUX SUP P LY CO NTRO L
On Resistance of Internal PMOS
On Resistance of Internal PMOS
Overcurrent T hreshold
-
-
-
-
-
-
19
0.25
0.25
0.5
1.0
2.9
T BD
T BD
T BD
T BD
T BD
-
⍀
⍀
A
A
V
PAUXON = High, ID = 0.375A, TA=TJ=25oC
PAUXON = High, ID = 0.375A, TA=TJ=70oC
VOCSET = 0.6V
Overcurrent T hreshold
VOCSET = 1.2V
3.3VAUX Undervoltage T rip T hreshold
Undervoltage Fault Response T ime
Gate Charge Current
110
25.0
ns
µA
29
PAUXON = High, VAUXG = 3V
T urn-On T ime
(PAUXON High to AUXG = 1V)
T urn-Off T ime
3.3VAUX Power On Reset T hreshold
-
-
-
16
3
2.5
-
-
-
ms
µs
V
CAUXG = 0.033µF
CAUXG = 0.033µF, AUXG Rising 10% - 90%
AUXIN Voltage Rising
CO NTRO L P INS
12VIN Supply Current
AUXIN Supply Current
OCSET Current
Overcurrent to Fault Response T ime
PWRONA/B, PAUXA/B Threshold Voltage
12V Power On Enable T hreshold
12V Power On Reset T hreshold
-
-
5.3
3
100
500
1.6
10
8
mA
mA
µA
ns
V
V
T BD
107
960
2.1
10.2
9.3
93
-
1.0
9.4
8.9
12VINA Voltage Rising
12VINA Voltage Falling
9.1
V
FAULT O /P P INS
FLTA/B Output Low Voltage
FLTA/B Output High Voltage
FLTA/B, Output Latch Threshold
FAUXA/B Output Low Voltage
FAUXA/B Output High Voltage
FAUXA/B Output Latch Threshold
-
0.5
0.7
V
V
V
V
V
V
IFLT = 2mA
IFLT = 0
IFLT High to Low transition
IFAUX = 2mA
IFAUX = 0
AUXIN-0.5 AUXIN-0.1 -
T BD
-
AUXIN-0.5 AUXIN-0.1 -
T BD
1.6
0.5
T BD
0.7
1.6
T BD
IFAUX High to Low transition
N OT ES
Specifications subject to change without notice.
REV. PrN 1/02
–3–
ADM1014–SPECIFICATIONS
ABSO LUTE MAXIMUM RATINGS*
O RD ERING GUID E
T em perature
Range
0°C to +70°C
(T A = +25°C unless otherwise noted)
P ackage
Description
P ackage
Option
VCC , 12VIN . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +14.0V
12VO, 12VG, 3V5VG . . . . . . . . . . -0.5V to V 12VIN +0.5V
-12VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . -14.0V to +0.5V
-12VO, -12VG . . . . . . . . . . . . . . . . . . . V-12VIN -0.5V to +0.5V
3VISEN, 5VISEN . . . -0.5V to the Lesser of 12VIN or +7.0V
Voltage, Any Other Pin . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3A
-12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8A
Continuous Power Dissipation (TA = +70oC) . . . . . . 667mW
Model
ADM1014JRU
38-Pin T SSOP
RU-38
P IN CO NFIGURATIO N
1
2
38 M12VINA
37 3VISENA
36 3VSA
M12VOA
M12VGA
PWRONA
FLTNA
T SSOP (derate 8.3mW/o
C above +70oC)
Operating T emperature Range
Commercial (J Version) . . . . . . . . . . . . . . . . 0°C to +70°C
Storage T emperature Range . . . . . . . . . . . –65°C to +150°C
Lead T emperature (Soldering, 10 sec) . . . . . . . . . . . +300°C
3
35 5VISENA
34 5VSA
4
FAUXA
5
33 3V5VGA
OCSET
6
GND
32
7
AUXGA
AUXOA
12VGA
31 AUXINA
8
*T his is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operation sections of this speci-
fication is not implied. Exposure to absolute maximum rating conditions for
extended periods of time may affect reliability.
30 PAUXONA
9
ADM1014
12VINA
29
10
11
12
13
14
15
16
17
18
19
TOP VIEW
12VOA
(Not to Scale)
28 12VINB
12VOB
27
26
25
24
23
22
21
PAUXONB
AUXINB
3V5VGB
5VSB
12VGB
AUXOB
AUXGB
FAUXB
FLTNB
TH E RMAL C H ARAC TE RISTIC S
38-Pin T SSOP Package:
qJA = 100°C/Watt, qJC = 10°C/Watt
5VISENB
3VSB
PWRONB
M12VGB
M12VOB
3VISENB
20 M12VINB
–4–
REV. PrN 1/02
ADM1014
P IN FUNC TIO N D E SC RIP TIO N
P in
1
Mnem onic
M12VOA
M12VGA
Function
Switched -12V output for channel A. Rated for 100mA.
2
Gate of channel A internal NMOS transistor. A capacitor connected from this pin to -12VOA (pin 1)
sets the start-up ramp for the +12V supply. During turn-on, this capacitor is charged from a 25µA
current source.
3
4
PWRONA
FLT NA
Power on control for channel A. 3.3V CMOS-compatible logic input controls all four main supplies.
PWRONA high = outputs on, PWRONA low = outputs off.
Active-low, 5V compatible, Open Drain fault output for channel A. A pull-up resistor connects the
pin to 3.3VAux. 4.7k⍀ is recommended for this function. An optional capacitor may be connected
from this pin to GND to provide improved immunity to power supply transients.
5
6
FAUXA
OCSET
Active-low, 3.3V compatible, Open Drain fault output for Aux channel A. T he same pull-up resistor
as that on FLT NA connects the pin to 3.3VAux.
Overcurrent set for all 10 outputs. A resistor connected from this pin to ground sets the overcurrent
trip point of all eight supplies. All eight overcurrent trip-points can be programmed by changing the
value of this resistor. T he default value of 6.04k⍀, ±1% is compatible with the maximum currents
allowed by the PCI specification.
7
AUXGA
Gate of channel A +3.3VAUX internal PMOS transistor. A capacitor connected from this pin to
AUXOA (pin 8) sets the start-up ramp for the +3.3VAUX supply. During turn-on, this capacitor is
charged from a 25µA current source.
8
9
AUXOA
12VGA
Switched 3.3V auxiliary output for channel A. Rated for 0.375A.
Gate of channel A internal PMOS transistor. A capacitor connected from this pin to 12VOA (pin 10)
sets the start-up ramp for the +12V supply. During turn-on, this capacitor is charged from a 25µA
current source. The undervoltage circuitry is disabled when the voltage on 12VGA rises above 1.2V.
If the capacitor on pin 7 (AUXGA) or pin 33 (3V5VGA) is more than 25% larger than the capacitor on
pin 9 (12VGA) a false undervoltage condition may be detected during startup.
10
11
12
12VOA
12VOB
12VGB
Switched 12V output for channel A. Rated for 0.5A.
Switched 12V output for channel B. Rated for 0.5A.
Gate of channel B internal PMOS transistor. A capacitor connected from this pin to 12VOB (pin 11)
sets the start-up ramp for the +12V supply. During turn-on, this capacitor is charged from a 25µA
current source. The undervoltage circuitry is disabled when the voltage on 12VGB rises above 1.2V.
If the capacitor on the pin 25 (3V5VGB) or pin 14 (AUXGB) is more than 25% larger than the
capacitor on pin 12 (12VGB) a false undervoltage condition may be detected during startup.
13
14
AUXOB
AUXGB
Switched 3.3V auxiliary output for channel B. Rated for 0.375A.
Gate of channel B +3.3VAUX internal PMOS transistor. A capacitor connected from this pin to
AUXOB (pin 13) sets the start-up ramp for the +3.3VAUX supply. During turn-on, this capacitor is
charged from a 25µA current source.
15
16
FAUXB
FLT NB
Active-low, 3.3V compatible, Open Drain fault output for Aux channel B. T he same pull-up resistor
as that on FLT NA connects the pin to 3.3VAux.
Active-low, 5V compatible, Open Drain fault output for channel B. A pull-up resistor connects the
pin to 3.3VAux. 4.7k⍀ is recommended for this function. An optional capacitor may be connected
from this pin to GND to provide improved immunity to power supply transients.
17
18
PWRONB
M12VGB
Power on control for channel B. 3.3V CMOS-compatible logic input controls all four main supplies.
PWRONB high = outputs on, PWRONB low = outputs off.
Gate of channel B internal NMOS transistor. A capacitor connected from this pin to -12VOB (pin 19)
sets the start-up ramp for the +12V supply. During turn-on, this capacitor is charged from a 25µA
current source.
19
M12VOB
Switched -12V output for channel B. Rated for 100mA.
REV. PrN 1/02
–5–
ADM1014
PIN FUNCTIO N D ESCRIP TIO N (CO NTINUED )
P in
20
Mnem onic
Function
M12VINB
3VISENB
-12V supply input for channel B. Also provides power to the -12V overcurrent circuitry.
21
3.3V current sense for channel B. A current-sensing resistor is connected between this pin and 3VSB
(pin 22). Connect to the load side of the current sense resistor.
22
23
24
25
3VSB
3.3V source for channel B. T he source of the 3.3V MOSFET is connected to this pin and a
current-sensing resistor is connected between this pin and pin 21.
5VISENB
5VSB
5V current sense for channel B. A current-sensing resistor is connected between this pin and 5VSB
(pin 24). Connect to the load side of the current sense resistor.
5V source for channel B. T he source of the 5V MOSFET is connected to this pin and a
current-sensing resistor is connected between this pin and pin 23.
3V5VGB
3.3V and 5V gate output for channel B, drives the gates of the external 3.3V and 5V MOSFET s.
A capacitor connected from this pin to GND sets the start-up ramp for the 3.3V and 5V supplies.
During turn-on, this capacitor is charged from a 25µA current source. The undervoltage circuitry is
disabled when the voltage on 3V5VGB falls below 12VIN-1.2V.
26
27
AUXINB
+3.3V auxiliary supply input for channel B.
PAUXONB
Power on control for channel B +3.3V auxiliary output. 3.3V CMOS-compatible logic input.
PAUXONB high = outputs on, PAUXONB low = outputs off.
28
29
30
12VINB
Switched +12V supply input for channel B.
12VINA
Switched +12V supply input for channel A and for OCSET and power-on RESET circuits.
PAUXONA
Power on control for channel A +3.3V auxiliary output. 3.3V CMOS-compatible logic input.
PAUXONA high = outputs on, PAUXONA low = outputs off.
31
32
33
AUXINA
GND
+3.3V auxiliary supply input for channel A.
Ground for all chip circuits. Connect to common of power supplies.
3V5VGA
3.3V and 5V gate output for channel A, drives the gates of the external 3.3V and 5V MOSFET s. A
capacitor connected from this pin to GND sets the start-up ramp for the 3.3V and 5V supplies.
During turn-on, this capacitor is charged from a 25µA current source. The undervoltage circuitry is
disabled when the voltage on 3V5VGA falls below 12VIN-1.2V.
34
35
36
37
38
5VSA
5V source for channel A. T he source of the 5V MOSFET is connected to this pin and a
current-sensing resistor is connected between this pin and pin 35.
5VISENA
3VSA
5V current sense for channel A. A current-sensing resistor is connected between this pin and 5VSA
(pin 34). Connect to the load side of the current sense resistor.
3.3V source for channel A. T he source of the 3.3V MOSFET is connected to this pin and a
current-sensing resistor is connected between this pin and pin 37.
3VISENA
M12VINA
3.3V current sense for channel A. A current-sensing resistor is connected between this pin and 3VSA
(pin 36). Connect to the load side of the current sense resistor.
-12V supply input for channel A. Also provides power to the -12V overcurrent circuitry.
REV. PrN 1/02
–6–
ADM1014
FAUX
AUXG
V
C
AUXIN
V
C
C
C
PAUXON
CURRENT
TRACKING
AND
AUXO
V
/1.2
OCSET
I-V CONVERTER
COMP
4.6V
2.9V
COMP
INHIBIT
COMP
INHIBIT
FLT
10.8V
COMP
INHIBIT
5VISEN
5VS
V
/14.5
OCSET
COMP
V
CC
3V5VG
ZENER
REFERENCE
3VISEN
3VS
V
/11.5
OCSET
COMP
V
COMMON
TO BOTH
CC
CHANNELS
12VG
12VIN
V
100µA
CC
OCSET
VOCSET
V
CC
CURRENT TRACKING
AND
I-V CONVERTER
LOW WHEN
12VO
12V IN
POWER-ON
RESET
V
< 10V
CC
V
/0.8
OCSET
COMP
-12VG
-12VIN
GND
-12VIN
V
CC
PWRON
CURRENT
TRACKING
AND
-12VO
V
V
/3.3
CC
OCSET
COMP
I-V CONVERTER
3V5VG
CIRCUIT OF ONE CHANNEL SHOWN, BOTH CHANNELS ARE IDENTICAL. RESET AND OCSET CIRCUITRY WITHIN DASHED LINE IS COMMEON TO BOTH CHANNELS
Figure 1. Sim plified Schem atic
REV. PrN 1/02
–7–
ADM1014
FUNC TIO NAL D E SC RIP TIO N
Note: T he OCSET current source obtains its power supply
from 12VINA.
VO LTAGE O UTP UTS
T he ADM1014 consists of two independent, identical chan-
nels, A and B, each of which controls four main power supply
voltages and an auxiliary voltage. As the channels are identical,
the following description applies to either channel, except
where otherwise stated.
An on-chip PMOS transistor connected between 12VIN and
12VO switches the +12V supply at currents up to 1.5A, whilst
an on-chip NMOS transistor connected between -12VIN and
-12VO switches the –12V supply at currents up to 0.38A. T he
+3.3V and +5V supplies are switched by external, N-channel
MOSFET s, whose gate drive is provided by the 3V5VG pins.
Using suitable MOSFET s, singly or in parallel, currents of
several amps may be switched with very low voltage drops.
INTE RNAL C URRE NT LIMIT
The +3.3VAUX, +12V and –12V supplies have the power
MOSFET switches on-chip. These devices are protected and
overcurrent shutdown is provided by a completely self-contained
current sensing system. The output current through the on-chip
power MOSFET is tracked at a lower level by a second, smaller
MOSFET. T he current through this MOSFET is then con-
verted to a voltage, which is compared to a reference voltage
determined by RSET. In the case of the +12V and -12V outputs,
if the current-sense voltage exceeds this reference voltage, the
comparator output will go high, the fault latch will be set and
all four main outputs and the auxiliary output will be turned
off. Similarly in the case of the auxiliary output, if the current-
sense voltage exceeds the reference voltage, the comparator
output will go high, the fault latch will be set, FAUXN/FLT N
will go low, and the auxiliary output and the four main outputs
will turn off.
T he four main power supplies may be switched on and off
under control of the PWRON pin.
T he 3.3V auxiliary supply has an on-chip PMOS transistor,
which can switch currents at up to 1A. T his supply is con-
trolled independently of the other four supplies by the
PAUXON pin.
The typical internal limiting currents may be calculated as follows:
ILIMIT (+3.3VAUX) = VOCSET /1.2
All five supplies are protected against overcurrent and the four
positive supplies are also protected against undervoltage.
= (10-4 ϫ RSET)/1.2
ILIMIT (+12V)
ILIMIT (-12V)
Where:
= 1.25 ϫ VOCSET
= 1.25 ϫ 10-4 ϫ RSET
= VOCSET /3.3
E XTE RNAL C URRE NT LIMIT
T he external power MOSFET s are protected and overcurrent
shutdown is provided on the +3.3V and +5V supplies by exter-
nal current-sense resistors and on-chip comparators.
= (10-4 ϫ RSET)/3.3
Current-sensing resistors are connected between the +5V out-
put pin and the 5VISEN pin, and between the +3.3V output
pin and the 3.3VISEN pin. T he sense pins are connected to
the inverting inputs of the current-limit comparator directly,
while the voltage outputs are connected to the non-inverting
inputs via a reference voltage proportional to the voltage on the
OCSET pin. T his voltage is VOCSET /14.5 in the case of the 5V
output and VOCSET/11.5 in the case of the 3.3V output. T hese
values were chosen so that the 3.3V and 5V sense resistors
could both be 5m⍀ in PCI applications.
ILIMIT = current limit in Amps
RSET is resistor from OCSET to GND in ⍀
Due to tolerances in the current tracking FET s, the variations
in the internal current limit are quite wide, typically ±20% of
the calculated value for the +12V supply and +35/-20% of the
calculated value for the –12V supply.
C H O IC E O F RSET AND RSENSE
When the voltage drop across the current-sensing resistor ex-
ceeds the reference voltage, the output of the comparator will
go high, the fault latch will be set and all four main outputs and
the auxiliary output on the channel will be turned off. T he
other main channel and auxiliary channel will remain on.
Using the above equations, RSET is chosen to set the required
current limits for the +3.3VAUX, +12V and -12V supplies. Once
RSET has been chosen, RSENSE3 and RSENSE5 can be chosen to set the
current limits for the 3.3V and 5V outputs.
For PCI applications RSET should be 6.04k⍀ and the current
sense resistors should both be 5m⍀±1%. T his will set the cur-
rent limits to the maximum values for the PCI specification.
For other applications, the following limits should be noted.
T he reference voltages for the current-limit comparators are set
by connecting a resistor between the OCSET pin and GND.
An on-chip, 100µA current source generates a voltage across
this resistor. T he current limit may also be adjusted by the
choice of current-sensing resistor.
1. T he minimum value of RSET is limited by the minimum
voltage the current–limit comparators can reliably sense,
which is determined by noise, comparator offset voltage and
the overdrive required to switch the comparator. T he refer-
ence voltage set by RSET should not be less than 33mV for
the 5V output, which has the smallest reference voltage.
T he minimum recommended value for RSET is 6k⍀, which
gives a reference voltage of 35mV for the 5V output and
45mV for the 3.3V output.
I
LIMIT(3.3V) = VOCSET/(11.5 ϫ RSENSE3
= (RSET ϫ 10-4)/(11.5 ϫ RSENSE3
= VOCSET/(14.5 ϫ RSENSE5
= (RSET ϫ 10-4)/(14.5 ϫ RSENSE5
)
)
)
I
LIMIT(5V)
)
Where:
ILIMIT = current limit in Amps
2. T he maximum value of RSET is limited by the junction tem-
perature. T his is determined by the power dissipated in the on-
chip MOSFET s, (which is dependent upon the current passed
RSET is resistor from OCSET to GND in ⍀
RSENSE is current-sense resistor in ⍀
REV. PrN 1/02
–8–
ADM1014
by the devices and their on-resistance), the thermal resistance
of the package (100oC/W), and the ambient temperature.
T he maximum on-resistance of the +3.3VAUX MOSFET is
0.65⍀, that of the +12V MOSFET is 0.35⍀ and that of the –
12V MOSFET is 0.9⍀, so the power dissipation will be:
PD = (0.65 ϫ (I+3.3VAUX)2 + 0.35 ϫ (I+12V)2 + 0.9 ϫ (I-12V)2)
Where:
PD is power dissipation in Watts
I is current in Amps
Under normal operating conditions the maximum recom-
mended value for RSET is 15k⍀.
Figure 2. FLTN and 3V5VG Delay
TABLE 1. FLT AND 3V5VG D E LAY VS. CFLT
UND E RVO LTAGE SE NSING
Undervoltage sensing of the +3.3V, +5V, +12V and
+3.3VAUX supplies is carried out by four voltage comparators.
T he supply voltages being monitoring are applied to the
inverting inputs of these comparators, whilst reference voltages
of 2.9V, 4.6V, 10.8V and 2.9V (derived from an on-chip zener
reference) are applied to their non-inverting inputs. Should any
of the output voltages fall below the corresponding reference
voltage, the output of the comparator will go high, the fault
latch will be set, turning off all the supplies (main and auxiliary)
on that channel.
CFLT
tA
t2A
OPEN
0.001µF
0.01µF
0.1µF
0.1µs
0.44µs
2.9µs
28µs
0.05µs
0.22µs
1.5µs
14µs
P O WE R C O NTRO L INP UTS
T he PWRONA and PWRONB inputs are 3.3V CMOS-com-
patible logic inputs, which may be used to switch all four main
outputs on and off, and is also used to reset the fault latch and
turn the outputs back on after an overcurrent or undervoltage
shutdown.
FLTN AND FAUXN O UTP UTS
T he FLT N and FAUXN outputs are active-low, 3.3V compatible,
Open- Drain fault outputs. T hese outputs are shorted together and
then connected to the 3.3VAux supply using a 4.7k⍀ pull-up
resistors. Should an overcurrent or undervoltage event occur on one
of the supplies, main or auxiliary, then the fault latch will be set,
FLT A and FAUXA or FLT B and FAUXB will go low and all
outputs on the faulting channel will be turned off.
When PWRON is high, the four main supplies are turned on.
With PWRON held low, the supplies are turned off. After an
overcurrent or undervoltage shutdown, PWRON should be
toggled low then high again to reset the fault latch and turn on
the outputs.
PAUXONA and PAUXONB are also 3.3V CMOS-compatible
logic inputs which perform a similar function for the +3.3V
auxiliary supplies.
P RO GRAMMABLE FAULT LATC H D E LAY
T he delay between an overcurrent or undervoltage fault occur-
ring and the outputs shutting down may be set by connecting a
capacitor between a FLT N or FAUXN output and GND. T his
delays the start of the FLT N/FAUXN output 1 to 0 transition
and slows down the fall time of the FLT N/FAUXN output,
thus delaying shutdown of the outputs. If the fault latch thresh-
old (~1.6V) is reached on FLT N/FAUXN then the fault latch
will be set and the four supply outputs and the auxiliary output
will be shut down. If the fault disappears before the latching
threshold is reached, the fault latch will not be set and the
FLT N/FAUXN output will return to a high state.
P O WE R-O N SE Q UE NC E AND SO FT START
When the device is powered on with PWRON held high, the
outputs are inhibited by the power-on reset circuit and will not
become active until VCC exceeds 10V. During this time the
undervoltage comparators are inhibited and the fault latch is
held in a reset condition.
Note: the power-on reset circuit monitors 12VINA.
After the power-on delay, all five outputs are turned on simulta-
neously. T he undervoltage comparators are enabled when the
voltage on the gate of the internal PMOS transistor, 12VG, has
fallen below about 400mV.
This adjustable delay allows the ADM1014 to ignore overcurrent
and undervoltage transients that might otherwise cause an un-
wanted shutdown. It should be noted that if a fault is asserted
on FLT N and FAUXN at the same time, then the delay is
halved, as shown in fig. 2 and T able 1.
T he rise time of the outputs may be controlled by connecting
capacitors between the gate and output pins of the +3.3VAUX,
+12V and -12V outputs, and from the 3V5VG pin to GND.
During output turn-on, these capacitors are charged from a
nominal 25µA current source. Limiting the output rise times
also limits the charging currents drawn by any supply
decoupling capacitors in the circuits being driven. With fast
turn-on these currents might be excessive and cause
overcurrent faults at power-on.
Care must be taken when choosing these capacitors. If the
capacitor on AUXG or 3V5VG is more than 25% larger than
REV. PrN 1/02
–9–
ADM1014
AP P LIC ATIO NS INFO RMATIO N
the capacitor on 12VG, the +3.3VAUX, 3.3V and 5V outputs
may not have exceeded their undervoltage thresholds by the
time the undervoltage comparators are enabled, and a false
undervoltage condition may be detected. For this reason it is
recommended to use the same value for all three gate capaci-
tors.
AP P LIC ATIO N C IRC UIT
Figure 3 shows a typical circuit configuration for the ADM1014 in
a PCI application, controlling supply voltages of +3.3V at up to
7.6A, +5V at up to 5A, +12V at up to 0.5A and –12V at up to
0.1A. In this circuit, two external MOSFET s are connected in
parallel for the 3.3V and 5V outputs to minimise on-resistance.
For PCI applications the minimum recommended value is
0.033µF. Smaller values may cause overcurrent faults at power-
up due to excessive charging currents drawn by decoupling
capacitors.
T he maximum value of the gate capacitors is determined by the
need to discharge them quickly when turning off the outputs
under fault conditions. If the capacitors are too large the
ADM1014 may be unable to protect the power bus or the ex-
ternal MOSFET s. With 0.033µF capacitors, the turn-off time
will be less than 6µs.
5V
3.3V
-12V
SLOT 1
+3.3Vaux
12V
AUXINA
AUXGA
C1
C2
AUXOA
5VISENA
5VSA
M12VINA
M12GA
R1
M12VOA
Q1
3V5VGA
3V5VGB
M12VINB
M12GB
Q2
R2
C3
C4
5VSB
M12VOB
5VISENB
12VINA
12VGA
3VISENA
3VSA
ADM1014
12VOA
R3
Q3
12VINB
12VGB
C5
C6
12VOB
Q4
3VSB
AUXINB
AUXGB
R4
FROM
SYSTEM
3VISENB
AUXOB
CONTROLLER
C7
C8
PAUXONA
PWRONA
PWRONB
PAUXONB
FAUXB
FAUXA
FLTNB
FLTNA
GND
OCSET
R5
C9
C10
C11
C12
R11
R12
TO SYSTEM CONTROLLER
5V
3.3V
12V -12V
+3.3Vaux
SLOT 2
Figure 3. Typical Application Circuit
REV. PrN 1/02
–10–
ADM1014
RL1
+12V
250mA
50mA
C1
RL2
-12V
C2
RL3
3.3Vaux
375mA
C3
GND
RL4
5.0V
2A
C4
RL5
3.3V
3A
C5
Figure 4. Load Board for Typical Application Circuit
Load Boar d Com ponents
M a in Boa r d C om ponents
Item Qty Ref Des
Descr iption
Item Qty Ref Des
Descr iption
1
2
3
4
5
6
7
8
1
3
2
1
1
1
1
1
PCB
EVAL-ADM1014Load Board
100uF 16V Electrolytic Caps
2200uF 16V Electrolytic Caps
1
2
3
4
5
6
7
8
1
1
4
4
4
2
2
2
8
4
3
1
8
2
4
1
1
4
1
4
U1
ADM1014
CL1-CL3
CL4-CL5
RL1
RL2
RL3
SKT 1
Q1-4
D1-4
R1-4
R5-6
R7-8
R9-10
C1-8
C9-12
C13-15
S1
38 Pin T ssop Socket
IRF7413 Power Mosfet
Green SMD LED
47
⍀
6W (W22 Series) Res
240
10⍀
⍀
2.5W (W21 Series) Res
6W (W22 Series) Res
12W (W24 Series) Res
5m
⍀
Metal Strip Resistor
470
⍀ 0805 chip resistor
RL4
RL5
2.2
⍀
1K5
6K04
⍀
0805 chip resistor
0805 chip resistor
⍀
1⍀ 12W (W24 Series) Res
9
CAP,0.033UF
CAP,0.47UF
10
11
12
13
14
15
16
17
18
19
20
Electrolytic capacitor space
SPDT Slide Switch
T estpoint
20 Pin Edge Conn Skt
4mm 10A PCB Sockets-Red
4mm 10A PCB Sockets-Green
4mm 10A PCB Sockets-Black
SMB
T 1-8
P1-2
J1 J4-J6
J2
J3
P4-7
PCB
R11-12
EVAL-ADM1014 Main Board
4K7
⍀ 0805 chip resistor
21
2
Load Board Fully Assembled Load Board
REV. PrN 1/02
–11–
ADM1014
CURRENT
SENSE
RESISTORS
LAYO UT C O NSID E RATIO NS
Any circuits supplied by the ADM1014 are outside the control
loops of the main system power supplies, which means that any
series resistance between the four supply inputs and the out-
puts will cause a degradation of the supply load regulation. T his
includes connector contact resistance, PCB trace resistance, on-
resistance of MOSFET s (both external and on-chip) and
current sense resistors.
35
34
37
36
VSENSE
Care must therefore be taken to ensure that:
a) PCB traces are as heavy as possible.
22
21
24
23
VSENSE
34
b)External MOSFET s have low-on resistance.
c) Current sense resistors are as small as possible.
ADM1014
CORRECT
T he current sense resistors have very small values (5m⍀ in the
preceding example) to minimise the voltage drop across them.
Because of this, PCB trace resistance can be a significant per-
centage of the sense resistance. It is therefore essential to en-
sure that the ADM1014 senses the voltage drop directly across
the sense resistors and not across any current-carrying trace
resistance in series with them. Connections from the ADM1014 to
the sense resistors must go directly to the ends of the resistors.
Figure 4 shows examples of good and bad practice
CURRENT
SENSE
RESISTORS
ADDITIONAL
VOLTAGE DROP
21
37
36
35
34
VSENSE
ADDITIONAL
VOLTAGE DROP
ADDITIONAL
VOLTAGE DROP
22
21
24
23
VSENSE
ADDITIONAL
VOLTAGE DROP
ADM1014
INCORRECT
Figure 4. Good and Bad Practice For Sense Resistor
Connection
O UTLINE D IME NSIO NS
D imensions shown in inches and (mm).
38-P in TSSO P (RU-38)
0.386 (9.80)
0.378 (9.60)
20
38
0.177(4.50)
0.169(4.30)
0.256 (6.50)
0.246 (6.25)
1
19
PIN 1
0.006(0.15)
0.002(0.05)
0.0433(1.10)
MAX
88
08
0.0106(0.27)
0.0067(0.17)
0.0200(0.50)
BSC
0.028 (0.70)
0.020 (0.50)
0.0079 (0.20)
0.0035 (0.090)
SEATING
PLANE
REV. PrN 1/02
–12–
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