ADM1062ASU [ADI]
Multisupply Supervisor/Sequencer with Margining Control and Temperature Monitoring; 多电源监控器/排序与裕度控制和温度监测
| 型号： | ADM1062ASU |
| 厂家： | 
ADI |
| 描述： | Multisupply Supervisor/Sequencer with Margining Control and Temperature Monitoring |
| 文件： | 总32页 (文件大小：1335K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Multisupply Supervisor/Sequencer with Margining
Control and Temperature Monitoring
Preliminary Technical Data
ADM1062
FEATURES
APPLICATIONS
10 supply fault detectors enabling supervision of supplies to
better than 1% accuracy
Central office systems
Servers/routers
5 selectable input attenuators allow supervision:
Supplies up to 14.4 V on VH
Supplies up to 6 V on VP1-4
Multivoltage system line cards
DSP/FPGA supply sequencing
In circuit testing of margined supplies
5 dual function inputs VX1-5:
High impedance input to supply fault detector with
thresholds between 0.573 V and 1.375 V
FUNCTIONAL BLOCK DIAGRAM
General-purpose logic input
Device powered by the highest of VP1–4, VH
2.048 V reference ( 0.25%ꢀ on REFOUT pin
12-bit ADC for read-back of all supervised voltages
Reference input, REFIN—2 input options:
Driven directly from REFOUT
More accurate external reference for improved ADC
performance
6 voltage output 8-bit DACs (0.300 V to 1.551 Vꢀ
Internal temperature sensor
Remote temperature sensor
10 programmable output drivers (PDO1-10ꢀ
Open collector with external pull-up
Push-pull output, driven to VDDCAP or VPn
Open collector with weak pull-up to VDDCAP or VPn
Internally charge pumped high drive for use with external
N-FET (PDO1–6 onlyꢀ
Sequencing Engine (SEꢀ implements State Machine control
of PDO outputs:
State changes conditional on input events
Can enable complex control of boards
Power up and power down sequence control
Fault event handling
Figure 1.
GENERAL DESCRIPTION
Interrupt generation on warnings
The ADM1062 is a configurable supervisory/sequencing device
which offers a single chip solution for supply monitoring and
sequencing in multiple supply systems.
Watchdog function can be integrated in SE
Program software control of sequencing through SMBus
User EEPROM—256 Bytes
Industry standard 2-wire bus interface (SMBusꢀ
Guaranteed PDO low with VH, VPn = 1.2V
40-lead LFCSP and 48-lead TQFP packages
(continued on Page 3)
Rev. PrJ
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However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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registered trademarks are the property of their respective owners.
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Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
ADM1062
Preliminary Technical Data
TABLE OF CONTENTS
General Description......................................................................... 3
Timeout Detector....................................................................... 21
Closed Loop Supply Margining................................................ 21
Writing to the DACs .................................................................. 22
Choosing the Size of the Feedback Resistor ........................... 22
DAC Limiting/Other Safety Features ...................................... 22
Temperature Measurement System.............................................. 23
Remote Temperature Measurement ........................................ 23
Communicating with the ADM1062........................................... 25
Configuration Download at Power-Up................................... 25
Updating the Configuration of the ADM1062....................... 25
Updating the Sequencing Engine of the ADM1062 .............. 26
Internal Registers of the ADM1062......................................... 26
ADM1062 EEPROM.................................................................. 26
Serial Bus Interface..................................................................... 27
Identifying the ADM1062 on the SMBUS .............................. 27
General SMBUS Timing............................................................ 27
SMbus Protocols for RAM and EEPROM .............................. 27
ADM1062 WRITE Operations................................................. 29
ADM1062 READ Operations................................................... 30
Outline Dimensions....................................................................... 32
Ordering Guide .......................................................................... 32
ADM1062 Specifications................................................................. 5
Pin Configurations and Functional Descriptions ........................ 8
Absolute Maximum Ratings............................................................ 9
Thermal Characteristics .............................................................. 9
ESD Caution.................................................................................. 9
Typical Performance Characteristics ........................................... 10
ADM1062 Inputs............................................................................ 13
Powering the ADM1062............................................................ 13
Supply Supervision..................................................................... 14
Input Comparator Hysteresis.................................................... 14
Input Glitch Filtering ................................................................. 14
Supply Supervision with VXN Inputs...................................... 15
Supply Supervision Using the ADC......................................... 15
VXN Pins as Digital Inputs....................................................... 16
ADM1062 Outputs......................................................................... 17
ADM1062 Sequencing Engine...................................................... 19
Warnings ...................................................................................... 19
SW Flow-Unconditional Jump ................................................. 19
End of Step Detector.................................................................. 20
Monitoring Fault Detector ........................................................ 20
REVISION HISTORY
Revision PrJ: Preliminary Version
Rev. PrJ | Page 2 of 32
Preliminary Technical Data
ADM1062
GENERAL DESCRIPTION
(continued from Page 1)
up to a +12V output for driving the gate of an N- Channel FET
which may be placed in the path of a supply.
In addition to these functions the ADM1062 integrates a 12-bit
ADC and six 8-bit voltage output DACs. These circuits can be
used to implement a closed loop margining system. This
enables supply adjustment by altering either the feedback node
or reference of a DC/DC Converter using the DAC outputs. The
supply margining can be performed, with a minimum of
external components, to an accuracy of 0.5%. The margining
loop can be used at In Circuit Testing of a board during
production (to verify the board’s functionality at say −5% of
nominal supplies), or can be used dynamically to accurately
control the output voltage of a DC/DC converter.
Temperature measurement is possible with the ADM1062. The
device contains one internal temperature sensor and a
differential input for a remote thermal diode. These are
measured using the 12- bit ADC.
The logical core of the device is a Sequencing Engine. This is a
state machine based construction, providing up to 63 different
states. This enables very flexible sequencing of the outputs,
based on the condition of the inputs.
The device also provides up to ten programmable inputs for
monitoring Under, Over, or out-of-window faults on up to ten
supplies. In addition, ten programmable outputs are provided.
These can be used as logic enables. Six of them can also provide
The device is controlled via configuration data which can
programmed into an EEPROM. All of this configuration can be
programmed using an intuitive GUI based software package
provided by ADI.
Rev. PrJ | Page 3 of 32
ADM1062
Preliminary Technical Data
Figure 2. Detailed Block Diagram
Rev. PrJ | Page 4 of 32
Preliminary Technical Data
ADM1062
ADM1062 SPECIFICATIONS1
VH = 3.0 V to 14.4 V, VPn = 3.0 V to 6.0 V2, TA = −40°C to 85°C, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
POWER SUPPLY ARBITRATION
VH, VPn
VP
VH
3.0
V
V
V
Min. of VDDCAP=2.7V required
Max VDDCAP= 5.1V, Typical
VDDCAP = 4.75V
6.0
14.4
POWER SUPPLY
Supply Current, IVH, IVPn (DAC’s,
Temp Sensor and ADC off)
6
mA
VDDCAP=4.75V, no PDO FET Drivers on, no loaded PDO pullups
to VDDCAP
Additional Currents
All PDO FET Drivers on
Current available from
VDDCAP
4
2
mA
mA
VDDCAP=4.75V, (loaded with 1µA), no PDO pullups to VDDCAP.
Max. additional load that can be drawn from PDO pullups to
VDDCAP
DAC’s Supply Current
ADC Supply Current
EEPROM Erase Current
2
1
mA
mA
mA
6 DAC’s on with 100µA max load on each
Running Round Robin loop
1ms duration only
10
SUPPLY FAULT DETECTORS VH
Pin
Input Impedance
Input attenuator error
Detection Ranges
High Range
26.7
kΩ
%
From VH to GND
Low, Mid and High ranges on VH, VPn
0.25
6
2.5
14.4
6
V
V
Mid Range
VPn Pins
Input Impedance
Detection Ranges
Mid Range
Low Range
Ultra Low Range
VX Pins
80
kΩ
From VPn to GND
2.5
1.25
0.573
6
3
V
V
V
1.375
Input Impedance
Detection Ranges
Ultra Low Range
Absolute Accuracy
1
MΩ
0.573
1.375
1
V
%
Input attenuator error +
Vref Error + DAC Non Linearity +
Comparator Offset Error
Threshold Resolution
Digital Glitch Filter
8
bits
µs
0
100
See Figure x. 8 filter length options
Temperature Sensor
Local Sensor Accuracy
2
2
°C
Die temp higher than ambient due to ADM1062 power
consumption
0°C <= TDIODE<=120°C
High Level
Remote Sensor Accuracy
Remote Sensor Source Current
°C
200
12
0
µA
µA
°C
Low Level
Temperature for 800h code out
Temperature for C00h code out
128
°C
Rev. PrJ | Page 5 of 32
ADM1062
Preliminary Technical Data
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Analog to Digital Converter
Signal Range
0
VREFIN
V
The ADC can convert signals presented to the VH, VPn and
VX_GPIn pins.VPn and VH input signals are attenuated
depending on selected range. A signal at the pin corresponding
to the selected range will be between 0.573V and 1.375V at the
ADC input.
Input reference voltage on
REFIN pin, VREFIN
2.048
12
TBD
TBD
V
VDDCAP=2.7V
V
VDDCAP=4.75V
Resolution
INL
DNL
Gain Error
Offset Error
Input Noise
bits
lsb
lsb
lsb
lsb
lsbrms
1.5
1
2
End-point corrected, VREFIN=2.048V
VREFIN = 2.048V
VREFIN = 2.048V
VREFIN = 2.048V
Direct input (no attenuator)
2
0.25
8
Buffered voltage output DACs
Resolution
bits
Code 80h output voltage
6 DAC’s are individually selectable to be centered on one of four
output voltage ranges
Range 1
0.6
V
Range 2
0.8
V
Range 3
1
V
Range 4
Output voltage range
lsb step size
INL
DNL
1.25
601.25
2.36
V
mV
mV
lsb
lsb
lsb
%
Same range independent of centre point
0.25
0.2
0.5
0.4
100
100
50
Mid code error
Gain Error
Max Load Current (source)
Max Load Current(sink)
Max load Capacitance
Settling time into 50pF load3
Load regulation
µA
C
pF
µs
mV
dB
dB
mV
2
2.5
per mA
DC
3
PSRR
80
40
3
100mV step in 20ns with 50pF load
Absolute Accuracy on any code
Reference Output
Reference Output
2.044
2.048
20
2.052
200
100
V
No Load
Max load current (source)
Max load current (sink)
Min load capacitance
Load regulation
µA
µA
nF
mA
dB
100
75
Cap required for decoupling, stability
per mA
DC
3
PSRR
Programmable Driver Outputs
High Voltage (Charge Pump)
Mode (PDO1-6)
Output Impedance
VOH
500
12.5
12
kΩ
V
V
11
10.5
14
IOH =0
IOH =1µA
2V < VOH< 7V
Ioutavg
20
µA
Standard (Digital Output Mode
(PDO1-10)
VOH
2.4
V
VPU(Pullup to VDDCAP or VPN) = 2.7V, IOH = 0.5mA
Rev. PrJ | Page 6 of 32
Preliminary Technical Data
ADM1062
Parameter
Min
Typ
Max
Unit
V
V
V
V
Test Conditions/Comments
VPU to Vpn = 6.0V, IOH = 0mA
VPU< = 2.7V, IOH = 1mA
IOL = 4mA
IOL = 10mA
IOL = 20mA
Max sink current per PDO pin
Max total sink for all PDOs
Internal pullup
Current Load on any VPn pull- ups (ie) total source current
available through any number of PDO pull-up switches
configured on to any one
4.5
VPU−0.3
VOL
0.1
0.25
0.5
20
V
IOL
ISINK
RPULLUP
ISOURCE(VPn)
mA
mA
kΩ
mA
60
20
2
Tristate Output Leakage
Current
10
µA
VPDO= 14.4V
DIGITAL INPUTS (VXn,A0,A1)
Input High Voltage, VIH
Input Low Voltage, VIL
Input High Current, IIH
Input Low Current, IIL
Input Capacitance
2.0
−1
V
V
µA
µA
pF
µA
Max. VIN=5.5V
Max. VIN=5.5V
VIN= 5.5V
0.8
1
VIN= 0
TBD
Programmable Pulldown
Current, IPULLDOWN
10
If known logic state required
SERIAL BUS DIGITAL INPUTS
(SDA,SCL)
Input High Voltage, VIH
Input Low Voltage, VIL
Output Low Voltage, VOL
SERIAL BUS TIMING
Clock Frequency, fSCLK
Bus Free Time, tBUF
Start Setup Time, tSU;STA
Start Hold Time, tHD;STA
SCL Low Time, tLOW
SCL High Time, tHIGH
SCL, SDA Rise Time, tr
SCL, SDA Fall Time, tf
Data Setup Time, tSU;DAT
Data Hold Time, tHD;DAT
2.0
V
V
V
0.8
0.4
IOUT = -3.0mA
400
KHz
µs
µs
µs
µs
µs
µs
µs
ns
ns
4.7
4.7
4
4.7
4
1000
300
250
300
1 These are target specifications and subject to change.
2 At least one of the VH, VP1-4 pins must be ≥ 3.0V to maintain device supply on VDDCAP.
3 Guaranteed by Characterization.
4 Guaranteed by Design.
Rev. PrJ | Page 7 of 32
ADM1062
Preliminary Technical Data
PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS
Figure 3. LFCSP Pin Configuration
Figure 4. TQFP Pin Configuration
Table 2. Pin Functional Descriptions
Pin Number
Mnemonic
NC
Description
LFCSP
TQFP
1
No connection.
1–5
6–9
2-6
VX1–5
High impedance inputs to supply fault detectors. Fault thresholds can be set at between
0.573V and 1.375V. Alternatively these pins can be used as general purpose digital inputs.
Low voltage inputs to supply fault detectors. Three input ranges can be set by altering the
input attenuation on a potential divider connected to these pins, the output of which connects
to a supply fault detector; these allow thresholds between 2.5V-6V, 1.25V-3V and 0.573V-
1.375V.
High voltage input to supply fault detectors. Three input ranges can be set by altering the
input attenuation on a potential divider connected to this pin, the output of which connects to
a supply fault detector; these allow thresholds between 6V-14.4V,2.5V-6V and 1.25V-3V.
7-10
11
VP1–4
VH
10
12-13
14
15
16
17
18-23
24-25
26-35
36-37
38
NC
No connection.
11
12
13
14
AGND
REFGND
REFIN
REFOUT
DAC1–6
NC
PDO10–1
NC
PDOGND
VCCP
Ground return for input attenuators.
Ground return for on-chip reference circuits.
Reference input for ADC, nominally 2.048V.
2.048V reference output.
Voltage output DACs. Default to high impedance at power-up.
No connection.
Programmable output drivers.
No connection.
Ground return for output drivers
15–20
21–30
31
32
39
Central charge pump voltage of 5.25V. A reservoir capacitor must be connected between this
pin and GND.
33
34
35
36
37
38
39
40
41
42
43
44
45
46
A0
A1
SCL
SDA
DN
Logic input which sets the 7th bit of the SMBus interface address.
Logic input which sets the 6th bit of the SMBus interface address.
SMBus clock pin. Open drain output requiring external resistive pull-up.
SMBus data i/o pin. Open drain output requiring external resistive pull-up.
External Thermal Diode Cathode Connection
External Thermal Diode Anode Connection
Device supply voltage. Linearly regulated from the highest of the VP1-4,VH pins and clamped
to a maximum of 4.75V
DP
VDDCAP
40
47
48
GND
NC
Supply ground.
No connection.
Rev. PrJ | Page 8 of 32
Preliminary Technical Data
ADM1062
ABSOLUTE MAXIMUM RATINGS
Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Voltage on VH Pin
17 V
Voltage on VP Pins
7 V
Voltage on Any Other Input
Input Current at any pin
Package Input Current
Maximum Junction Temperature (TJmax
Storage Temperature Range
Lead Temperature, Soldering
Vapor Phase, 60 s
−0.3 V to +6.5 V
5 mA
20 mA
150°C
−65°C to +150°C
)
THERMAL CHARACTERISTICS
40-pin LFCSP Package:
215°C
ESD Rating all pins
2000 V
θJA = TBD°C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrJ | Page 9 of 32
ADM1062
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 8. IDD vs. VVP1 (Supply)
Figure 5. DNL for on- chip 12- bit ADC
Figure 9. IVP1 vs. VVP1 (Not Supply)
Figure 6. INL for on- chip 12- bit ADC
Figure 10. IDD vs. VVH
Figure 7. VVDDCAP vs. VVH and VVP1
Rev. PrJ | Page 10 of 32
Preliminary Technical Data
ADM1062
14
13.5
13
0uA LOAD
12.5
12
11.5
11
1uA LOAD
10.5
10
-40
-25
-10
5
20
35
50
65
80
Temper at ur e ( o C)
Figure 11. IVH vs. VVH (Not Supply)
Figure 14. PDO Output (FET Drive Mode) vs. Temperature
4. 5
4
3. 5
3
V
V P 1 =5 V
2. 5
2
V V P 1 =3. 3V
1. 5
1
0. 5
0
0
0.5
1
Iload ( mA)
1. 5
2
Figure 12. IVX1 vs. VVX1
Figure 15. PDO Output (Strong Pull-up to VP1) vs. Load Curr.
4. 5
4
3. 5
3
V V P 1 =5 V
2. 5
2
V V P 1 =3 . 3 V
1. 5
1
0. 5
0
0
10
20
30
40
Iload ( uA)
Figure 13. Percentage Deviation in VTHRESH vs. Temperature
Figure 16. PDO Output (Weak Pull-up to VP1) vs. Load Current
Rev. PrJ | Page 11 of 32
ADM1062
Preliminary Technical Data
Figure 17. PDO Output (Strong Pull-Down) vs. Load Current
Figure 20. VCCP vs. Load Current
2
1. 8
1. 6
1. 4
1. 2
1
0. 8
0. 6
0. 4
0. 2
0
0
20
40
60
80
Iload ( uA)
Figure 18. PDO Output (Weak Pull-Down) vs. Load Current
Figure 21. VXn (Digital Input Mode) Threshold vs. Temperature
Figure 19. Oscillator Frequency vs. Temperature
Rev. PrJ | Page 12 of 32
Preliminary Technical Data
ADM1062
ADM1062 INPUTS
POWERING THE ADM1062
The ADM1062 is powered from the highest voltage input on
either the Positive Only supply inputs (VPn) or the High
Voltage supply input (VH). The same pins are used for supply
fault detection (discussed below) . A VDD Arbitrator on the
device chooses which supply to use. The arbitrator can be
considered an OR’ing of five LDO’s together. A supply
comparator chooses which of the inputs is highest and selects
this one to provide the on- chip supply. There is minimal
switching loss with this architecture (~0.2V), resulting in the
ability to power the ADM1062 from a supply as low as 3.0V.
Note that the supply on the VXn pins cannot be used to power
the device.
An external cap to GND is required to decouple the on chip
supply from noise. This cap should be connected to the
VDDCAP pin, as shown in Figure 22. The cap has another use
during “brown outs” (momentary loss of power). Under these
conditions, where the input supply, VPn or VH, dips transiently
below VDD, the synchronous rectifier switch immediately turns
off so that it doesn’t pull VDD down. The VDD cap can then act
like a reservoir and keep the device active until the next highest
supply takes over the powering of the device. 10µF is
Figure 22. VDD Arbitrator Operation
The ADM1062 has ten programmable inputs. Five of these are
dedicated Supply Fault Detectors (SFD’s). These dedicated
inputs are called VH and VP1-4 by default. The other five inputs
have dual functionality. They can either be used as Supply Fault
Detectors, with similar functionality to VH and VP1-4, or they
can be used as CMOS/TTL compatible logic inputs to the
devices. Thus, the ADM1062 can have up to ten analog inputs, a
minimum of five analog inputs and five digital inputs, or a mix.
Note that if an input is used as an analog input, it cannot be
used as a digital input. Thus, a configuration requiring ten
analog inputs would have no digital inputs available. Table 4
shows the details of each of the inputs.
recommended for this reservoir/decoupling function.
Note that in the case where there are two or more supplies
within 100mV of each other, the supply which takes control of
VDD first will keep control (e.g) if VP1 is connected to a 3.3V
supply, then VDD will power up to approximately 3.1V through
VP1. If VP2 is then connected to another 3.3V supply, VP1 will
still power the device, unless VP2 goes 100mV higher than VP1.
Table 4. Input Functions, Thresholds and Ranges
Input
Function
Voltage Range
Max Hysteresis
425mV
1.16V
Voltage Resolution
13.7mV
37.6mV
Glitch Filter
0-100µs
0-100µs
0-100µs
0-100µs
0-100µs
0-100µs
0-100µs
VH
High V Analog Input
2.5V to 6V
4.8V to 14.4V
0.573 to 1.375V
1.25 to 3V
VPn
VXn
Positive Analog Input
97.5mV
212mV
425mV
97.5mV
N/A
3.14mV
6.8mV
13.7mV
2.5 to 6V
High Z Analog Input
Digital Input
0.573 to 1.375V
0 to 5V
3.14mV
N/A
Rev. PrJ | Page 13 of 32
ADM1062
Preliminary Technical Data
Reversing the equation, the code for a desired threshold is given
by
N = 255 ×
VT −VB VR
For example, if the user wishes to set a 5V OV threshold on
VP1, the code to be programmed in the PS1OVTH register
(discussed in AN-698) would be
N = 255 ×
(
5 − 2.5
)
3.5
Figure 23. Supply Fault Detector Block
Thus N = 182
10110110 Bin, or 0xB6
SUPPLY SUPERVISION
The ADM1062 has up to ten Supply Fault Detectors (SFDs) on
its ten input channels. These are highly programmable reset
generators. This enables the supervision of up to ten supply
voltages. These supplies can be as low as 0.573V and as high as
14.4V. The inputs can be configured to detect an Undervoltage
fault (where the input voltage droops below a preprogrammed
value), an Overvoltage fault (where the input voltage rises above
a preprogrammed value) or an Out-Of-Window fault
(undervoltage OR overvoltage). The thresholds can be
programmed to 8-bit resolution in registers provided in the
ADM1062. This translates into a voltage resolution which is
dependent on the range selected. The
INPUT COMPARATOR HYSTERESIS
The UV and OV comparators shown in Figure 22 are always
looking at VPn. In order to avoid chattering (multiple
transitions when the input is very close to the set threshold
level), these comparators have digitally programmable
hysteresis. The hysteresis can be programmed up to the values
shown in Table 4. The hysteresis is added after a supply voltage
goes out of tolerance. Thus, the user can program how much
above the UV threshold the input must rise again before a UV
fault is de-asserted. Similarly, the user can program how much
below the OV threshold an input must fall again before an OV
fault is de-asserted.
resolution is given by
The hysteresis figure is given by
Step Size =Theshold Rang 255
VHYST =VR × NTHREST 255
Thus, if the high range were selected on VH, the UV and
where:
14.4V − 4.8V 255 = 37.6mV
V
N
HYST is the desired hysteresis voltage.
THRESH is the decimal value of the 5 bit hysteresis code.
Listed below are the upper and lower limit of each range
available, the bottom of each range and the range itself. The
threshold value required is given by
Note that NTHRESH has a maximum value of 31. The maximum
hysteresis for each of the ranges is quoted in Table 4.
VT =
VRX
N
255 +VB
INPUT GLITCH FILTERING
The final stage of the SFD’s is a glitch filter. This block provides
time domain filtering on the output of the SFD comparators.
This allows the user to remove any spurious transitions (such as
supply bounce at turn-on). The glitch filter function is
additional to the digitally programmable hysteresis of the SFD
comparators. The glitch filter timeout is programmable up to
100µs. The functionality of the block is best explained using an
example. A glitch filter timeout of 100µs means that pulses
which appear on the input of the glitch filter block and are less
than 100_s in duration will be prevented from appearing on the
output of the glitch filter block. Any input pulse which is longer
in duration than 100µs will appear on the output of the glitch
filter block. The output will be delayed with respect to the input
by 100µs. The filtering process is shown in Figure 24.
Table 5.
Voltage Range
0.573 to 1.375V
1.25 to 3V
VB(Vꢀ
0.573
1.25
2.5
VR(Vꢀ
0.802
1.75
3.5
2.5 to 6V
4.8 to 14.4V
4.8
9.6
where:
VT is the desired threshold voltage (UV or OV).
VR is the voltage range.
N is the decimal value of the 8-bit code.
VB is the bottom of the range.
Rev. PrJ | Page 14 of 32
Preliminary Technical Data
ADM1062
SUPPLY SUPERVISION USING THE ADC
A further level of supervision is provided by the on- chip 12 bit
ADC. The ADC has a twelve channel analog mux on the front
end. The twelve channels are the ten SFD inputs, the external
temperature sensor and the internal temperature sensor. Any or
all of these inputs can be selected to be read by the ADC. Thus
the ADC can be setup to continuously read the selected
channels. The circuit controlling this operation is called the
“Round Robin”. The user selects which channels they wish to
operate on, and the ADC performs a conversion on each in
turn. Averaging can be turned on, which will set the Round
Robin to take 16 conversions on each channel, otherwise a
single conversion is made on each channel. At the end of this
cycle the results are all written to the output registers and, at the
same time, compared with pre-set thresholds to generate any
warnings as required. Limit registers are provided on the
ADM1062 which the user can program to a maximum or
minimum allowable threshold. Only one register is provided for
each input channel so an UV or OV threshold but not both can
be set for a given channel. Exceeding the threshold generates a
Warning which can be read back from the status registers or
input into the SE via an OR gate. The round robin can be
enabled either via an SMBus write, or can be programmed to
turn on at any particular point in the SE program, for instance it
can be set to start once a powerup sequence is complete and all
supplies are known to be within expected fault limits. Note that
there is a latency built into this supervision which is dictated by
the conversion time of the ADC. ADC conversions take
different times for different input channels due to the sample
times being different. With all twelve channels selected the total
time for the round robin operation (averaging off) will be
approximately 20ms, with the dominant contribution to this
being due to the temperature sensor measurement times.
Supervision using the ADC, therefore, does not provide the
same real time response as the SFD’s.
Figure 24. Input Glitch Filter Function
SUPPLY SUPERVISION WITH VXN INPUTS
The VXn inputs have two functions. They can either be used as
Supply Fault Detectors or as digital logic inputs. When selected
to be an analog (SFD) input, the VXn pins have very similar
functionality to the VH and VPn pins. The major difference is
that the VXn pins have only one input range, 0.573V to 1.375V.
Therefore, these inputs can only supervise very low supplies
directly. However, the input impedance of the VXn pins is high,
allowing an external resistor divide network to be connected to
the pin. Thus, any supply can be potentially divided down into
the input range of the VXn pin and supervised. This enables
other supplies such as +24V, +48V, −5V to be monitored by the
ADM1062.
An additional Supply Supervision function is available when the
VXn pins are selected as digital inputs. In this case, the analog
function is available to be used as a second detector on each of
the dedicated analog inputs, VP1-4 and VH. THe analog
function of VX1 is mapped to VP1, VX2 is mapped to VP2 etc.
VX5 is mapped to VH. In this case, these SFD’s can be viewed as
a secondary or “Warning” SFD. These secondary SFD’s are fixed
to the same input range as the primary SFD. They are used to
indicate Warning levels rather than Failure levels. This allows
faults and warnings to be generated on a single supply using
only one pin. For example, if VP1 was set to output a fault if a
3.3V supply drooped to 3.0V, VX1 could be set to output a
warning at 3.1V. Warning outputs are available for readback
from the status registers. They are also OR’ed together and fed
into the Sequencing Engine (SE), allowing Warnings to generate
interrupts on the PDO’s. Thus, in the example above, if the
supply drooped to 3.1V, a warning would be generated, and
remedial action could be taken before the supply dropped out
of tolerance.
The ADC samples single-sided inputs wrt the AGND pin. A 0V
input gives out code 0 and an input equal to the voltage on
REFIN gives out full code (4095 (dec))
The inputs to the ADC come directly from the VXn pins and
from the back of the input attenuators on the VPn and VH pins.
The range of voltages expected on these nodes for the
supervising functions is the 0.573V to 1.375V of the “Ultra-
Low” supervisory range.
It is normal to supply the reference to the ADC on the REFIN
pin simply by connecting the REFOUT pin to the REFIN pin.
REFOUT provides a 2.048V reference accurate to 0.2%. As
such, the supervising range covers less that half of the normal
ADC range. It is possible to provide the ADC with a more
accurate external reference for improved read-back accuracy.
Also, it is possible to connect supplies to the input pins purely
for ADC read-back even though they may go above the
Rev. PrJ | Page 15 of 32
ADM1062
Preliminary Technical Data
expected supervisory range limits (though not above 6V as this
would violate the absolute maximum ratings on these pins). For
instance a 1.5V supply connected to the VX1 pin would
correctly read out as an ADC code of approximately 3/4 Full
scale but would always sit above any supervisory limits that
could be set on that pin.
programmable width is outputted from the digital block. The
width is programmable from 0µs to a maximum of 100µs. The
digital blocks feature the same glitch filter function available on
the SFD’s. This enables the user to ignore spurious transitions
on the inputs. For example, the filter can be used to debounce a
manual reset switch. When configured as digital inputs, each of
the VXn pins has a weak (10µA) pull-down current source
available for placing the input in a known condition, even if left
floating. The current source, if selected, weakly pulls the input
to GND.
It is not possible to set REFIN to higher than 2.048V.
VXN PINS AS DIGITAL INPUTS
As outlined previously, the VXn inputs pins on the ADM1062
have dual functionality. The second function is as a digital input
to the device. Thus, the ADM1062 can be configured to have up
to five digital inputs. These inputs are TTL/CMOS compatible.
Standard logic signals can be applied to the pins: RESET from
reset generators, PWRGOOD signals, fault flags, manual resets,
and so on. These signals are available as inputs to the SE, and so
can be used to control the status of the PDO’s. The inputs can
be configured to detect either a change in level or an edge.
When configured for level detect, the output of the digital block
is simply a buffered version of the input. When configured for
edge detect, once the logic transition is detected, a pulse of
Figure 25. VXn Digital Input Function
Rev. PrJ | Page 16 of 32
Preliminary Technical Data
ADM1062 OUTPUTS
SUPPLY SEQUENCING THROUGH CONFIGURABLE
OUTPUT DRIVERS
ADM1062
than 10.5V into a 1µA load). The pull-down switches may be
used to drive status LEDs.
Supply sequencing is achieved with the ADM1062 by using the
Programmable Driver Outputs (PDO’s) on the device as control
signals for supplies. The Output drivers can either be used as
logic enables or as FET drivers.
The data driving each of the PDO’s can come from one of three
sources. The source can be enabled in the PnPDOCFG
configuration register (refer to AN-698).
The sequence in which the PDO’s are asserted (and, thus, the
supplies are turned on) is controlled by the Sequencing Engine
(SE). The SE determines what action is to be taken with the
PDO’s based on the condition of the inputs of the ADM1062.
Thus, the PDO’s can be set up to assert when the SFD’s are in
tolerance, the correct input signals are received on the VXn
digital pins, there are no warnings from any of the inputs of the
device, and so on. The PDO’s can be used for a number of
functions: the primary function is to provide Enable signals for
LDO’s or DC/DC convertors which generate supplies locally on
a board. The PDO’s can also be used to provide a
The data sources are:
• An output from the SE.
• Directly from the SMBus. A PDO can be configured so that
the SMBus has direct control over it. This enables software
control of the PDO’s. Thus, a microcontroller could be used
to initiate a software power-up/power-down sequence.
• An On- Chip Clock. A 100KHz clock is generated on the
device. This clock can be made available on any of the PDO’s.
It could be used to clock an external device such as a LED, for
example.
POWER_GOOD signal when all of the SFD’s are in tolerance or
provide a RESET output if one of the SFD’s goes out of spec
(this can be used as a status signal for a DSP, FPGA or other
microcontroller).
The default condition of the PDO’s is to be pulled to GND by a
weak (20kΩ) on-chip pull-down resistor. This is also the
condition of the PDO’s on power-up until the configuration is
downloaded from EEPROM and the programmed setup is
latched. The outputs are actively pulled low once there is a
supply 1V or greater on VPn or VH. The outputs remain high
impedance prior to 1V appearing on VPn or VH. This provides
a known condition for the PDO’s during power-up. The internal
pull-down can be overdriven with an external pull-up of
suitable value tied from the PDO pin to the required pullup
voltage. The 20kΩ resistor must be accounted for in calculating
a suitable value. For example, if it was required to pull PDOn up
to 3.3V, and 5V was available as an external supply, the pull-up
resistor value is given by:-
The PDO’s can be programmed to pull- up to a number of
different options. The outputs can be programmed as:–
• Open Drain (allowing the user to connect an external pull-up
resistor)
• Open Drain with weak pull-up to VDD
• Push Pull to VDD
• Open-drain with weak pull-up to VPn
• Push-pull to VPn
• Strong pull-down to GND
3.3V = 5V × 20kΩ
RUP + 20kΩ
• Internally charge- pumped high drive (12V- PDO 1- 6 Only)
Therefore,
RUP
The last option (available only on PDO’s 1 to 6) allows the user
to directly drive a voltage high enough to fully enhance an
external N-fet which is used to isolate, for example, a card-side
voltage from a backplane supply (a PDO will sustain greater
=
(100kΩ − 66kΩ
)
3.3 = 10kΩ
Rev. PrJ | Page 17 of 32
ADM1062
Preliminary Technical Data
Figure 26. Programmable Driver Output
Rev. PrJ | Page 18 of 32
Preliminary Technical Data
ADM1062
ADM1062 SEQUENCING ENGINE
The ADM1062 incorporates a Sequencing Engine (SE) which
provides the user with powerful and flexible control of
sequencing. The SE implements a state machine control of the
PDO outputs, with state changes conditional on input events. SE
programs can enable complex control of boards, such as
powerup and power down sequence control, fault event
handling, interrupt generation on warnings etc. A watchdog
function, to verify the continued operation of a processor clock,
can be integrated into the SE program. The SE can also be
controlled via the SMBus, giving software or firmware control
of the board sequencing
• the transition from one state to the next is made in less than
20µs. This is the time taken to download a state definition
from EEPROM to the SE.
Figure 27. State Cell
Considering the function of the SE from an applications
viewpoint it is most instructive to think of the SE as providing a
“state” for a state machine. This state has the following
attributes:
The ADM1062 offers up to 63 such state definitions. The signals
being monitored to indicate the status of the input pins are the
outputs of the SFD’s.
WARNINGS
• it is used to monitor signals indicating the status of the 10
input pins, VP1-4, VH and VX1-VX5
The SE is also monitoring the Warnings. These are generated by
ADC readings violating their limit register value or by the
secondary voltage monitors on VP1-4, VH. These are all OR’ed
together and available as a single “Warnings” input to each of
the three blocks which enable exiting from a state.
• it can be entered from any other state
• there are three exit routes which move the state machine on
to a “next state”, these are:
SW FLOW-UNCONDITIONAL JUMP
1. End of Step detection
2. Monitoring fault
3. Timeout
The SE can be forced to advance to the next state
unconditionally. This enables the user to force the SE to
advance. Examples where this might be used include moving to
a margining state or as a method of debugging a sequence. The
SW Flow or Go to command can be seen as another input to
End of Step and Timeout blocks which provide an exit from
each state.
• delay timers for the End of Step and Timeout blocks above
can be programmed independently and will change with each
state change. The range of timeouts is from 0ms to 400ms
• the output condition of the 10 PDO pins is defined and fixed
within a state
Table 6. Example Sequence States Entries
State
IDLE1
IDLE2
EN3V3
End of Step
Timeout
Monitor
If VX1 is LOW then go to State IDLE2
If VP1 is OK then go to State EN3V3
If VP2 is OK then go to State EN2V5
If VP2 is NOT OK after 10ms then
goto State DIS3V3
If VP1 is NOT OK then goto State IDLE1
DIS3V3
EN2V5
If VX1 is HIGH then go to State IDLE1
If VP3 is OK then go to State PWRGD
If VP3 is NOT OK after 20ms then
goto State DIS2V5
If VP1 OR VP2 is NOT OK then goto State
FSEL2
DIS2V5
FSEL1
If VX1 is HIGH the go to State IDLE1
If VP3 is NOT OK then go to State
DIS2V5
If VP1 OR VP2 is NOT OK then goto State
FSEL2
FSEL2
If VP2 is NOT OK then go to State
DIS3V3
If VP1 is NOT OK then goto State IDLE1
PWRGD
If VX1 is HIGH then go to State DIS2V5
If VP1 OR VP2 OR VP3 is NOT OK then goto
State FSEL1
Rev. PrJ | Page 19 of 32
ADM1062
Preliminary Technical Data
SEQUENCING ENGINE APPLICATION EXAMPLE
An example application will be considered here to demonstrate
the operation of the SE. Figure 28 below shows how the simple
building block of a single SE state can be used to build up a
power-up sequence for a 3–supply system. Table 6 below
textually describes the same SE implementation. In this system
the presence of a “good” 5V supply on VP1, and the VX1 pin
being held low, are the trigger required for an up sequence to
start. The sequence intends to turn on the 3.3V supply next,
then the 2.5V supply (assuming successful turn-on of the 3.3V
supply). Once all 3 supplies are good the PWRGD state is
entered, where the SE will remain until a fault occurs on one of
the 3 supplies, or it is instructed to go through a power-down
sequence by VX1 going high.
Figure 29. PDO outputs for each state
END OF STEP DETECTOR
This block is used to detect when a step in a sequence has been
completed. It is simply looking for one of the inputs to SE to
change state and is most often used to be the gate on successful
progress through an up or down sequence. A timer block is
included, in this detector- it can be thought of as a way to insert
delays into an up or down sequence, if required. Timer delays
can be set from 10µs to 400ms. Figure 30 shows a block diagram
of the End of Step Detector.
Faults are dealt with on the way through the up sequence on a
case-by case basis. The text below which describes the
individual blocks will use the example application to
demonstrate what the state machine is doing.
Figure 30. End-of-Step Detector
It is also possible to use the End of Step Detector to help
identify monitoring faults. In the example application shown in
Figure 28 it can be seen how the FSEL1 and FSEL2 states are
being used to identify which of VP1,VP2 or VP3 has faulted and
to take the appropriate action.
MONITORING FAULT DETECTOR
This block is used to detect a failure on any one of a number of
inputs. The logical function implementing this is a wide OR
gate which is used to detect when any one of a number of inputs
deviates from its’ expected condition. The clearest
demonstration of the use of this block is in the PWRGD state
where the monitor block will indicate that a failure on any one
of the VP1,VP2 and VP3 inputs has occurred. There is no
programmable delay available in this block. This is because, the
triggering of a fault condition is likely to be caused by a supply
falling out of tolerance, a situation to which the user will want
to react to as quickly as possible. There is some latency in
moving out of this state, however, since it takes a finite time
(~20µs) for the state configuration to download from EEPROM
into the SE. Figure 31 below shows a block diagram of the
Monitoring Fault Detector.
Figure 28. Flow Diagram
Rev. PrJ | Page 20 of 32
Preliminary Technical Data
ADM1062
which will allow any dc-dc supply to be set to any voltage,
accurate to within 0.5% of the target.
Figure 32. Closed Loop Margining System using ADM1062
Figure 31. Monitoring Fault Detector
The simplest circuit to implement this function is an
attenuation resistor to connect the DACn pin to the feedback
node of a dc-dc converter. When the DACn output voltage is set
equal to the feedback voltage, no current is fed in to this node
and the dc-dc output voltage will not change. Taking DACn
above the feedback voltage forces current into the feedback
node and the output of the dc-dc converter will be forced to fall
to compensate for this. The dc-dc output can be forced high by
setting the DACn output voltage lower than the feedback node
voltage. The series resistor can be split in two and node between
them decoupled with a capacitor to ground. This will help to
decouple any noise picked up from the board. PSRR from
ADM1062 supply to the dac output is greater than 80dB at dc
but decoupling to a ground local to the dc-dc converter is also
recommended.
TIMEOUT DETECTOR
This block is included to allow the user to trap a failure to make
proper progress through an up or down sequence.
In the example application we can see the timeout next state
transition being used from the EN3V3 and EN2V5 states. In the
case of the EN3V3 state, the signal 3V3ON is asserted on entry
to this state (on the PDO1 output pin) to turn on a 3.3V supply.
This supply rail is connected to the VP2 pin and the End of Step
detector is looking for the VP2 to go “good” (going above its’ UV
threshold, which will be set on the Supply Fault Detector (SFD)
attached to that pin). Progress forward in the up sequence is
made when this change is detected.
If, however, the supply failed to go “good” – perhaps because of a
short circuit over-loading this supply – then the timeout block
allows this problem to be trapped. In the example shown, if the
3.3V supply does not go good within 10ms then the SE moves
to the DIS3V3 state and turns off this supply by bringing PDO1
low. It also indicates that a fault has occurred by taking PDO3
high. Timeout delays of between 0µs and 400ms can be
programmed.
Then the simplest algorithm to implement closed loop
margining is as follows:
1. Disable the six DACn outputs.
2. Set DAC output voltage equal to the voltage on the
feedback node.
3. Enable the DAC.
CLOSED LOOP SUPPLY MARGINING
It is often necessary for the system designer to be able to adjust
supplies, either to optimize their level, or to force them away
from nominal values to characterize the system performance
under these conditions. This is a function typically performed at
In- Circuit Test (ICT), for instance, where the manufacturer
wishes to guarantee that the product under test functions
correctly at, say, nominal supplies −10%. The ADM1062
incorporates all the circuits required to do this, with a 12-bit
successive approximation ADC to read back the level of any of
the supervised voltages, and six voltage output DACs (DAC1–
DAC6) which can be used to adjust supply levels. These circuits
can be used along with some other “intelligence” such as a
microcontroller to implement a closed loop margining system
4. Read the voltage at the dc-dc output (which will be
connected to one of the VP1–4,VH or VX1–5 pins).
5. If necessary, modify the DACn output code up or down to
adjust the dc-dc output voltage, otherwise, stop since target
voltage has been reached.
6. Set the DAC output voltage to a value which alters the
supply output by the required amount (eg) 5%.
7. Repeat from 4.
Steps 1-3 ensure that when the DACn output buffer is turned on
it has very little effect on the dc-dc output. The dac output
buffer has been designed to power up without glitching. It does
Rev. PrJ | Page 21 of 32
ADM1062
Preliminary Technical Data
this by first powering up the buffer to follow the pin voltage and
does not drive out on to the pin at this time. Once the output
buffer is properly enabled, the buffer input is switched over to
the dac, and the output stage of the buffer is turned on. Output
glitching is negligible.
output voltage, feedback node voltage and the feedback resistor
between these two nodes. Choosing the resistor in this way
gives the most resolution out of the dac – in other words, with
one dac code change the smallest effect on the dc-dc output
voltage is induced. If the resistor is sized up to use code,say ,
27(dec) to 227(dec) to move the dc-dc output by 5%, then that
is 100 codes to move 5% i.e. each code moves the output by
0.05%. This is beyond the readback accuracy shouldn’t prevent
the user building their circuit to use the most resolution.
WRITING TO THE DACs
Four DAC ranges are offered and these are placed with mid-
code (code 0x7F) at 0.6V, 0.8V, 1.0V and 1.25V. These voltages
are placed to correspond to the most common feedback
voltages. Centering the dac outputs in this way provides the best
use of the dac resolution i.e. for most supplies it will be possible
to place the dac mid-code at the point where the dc-dc output is
not modified, thus giving a full half of the dac range to margin
up and down. The dac output voltage is set by the code written
to the DACn register. The voltage is linear with the unsigned
binary number in this register. The code 0x7F is placed at the
mid-code voltage as described above. The output voltage is
given by the following equation:
DAC LIMITING/OTHER SAFETY FEATURES
Limit registers (called DPLIMn and DNLIMn) on the device
offer the user some protection from firmware bugs which could
cause catastrophic board problems by forcing supplies beyond
their allowable output ranges. Essentially the DAC code written
into the DACn register is clipped such that the code used to set
the DAC voltage is actually given by
DAC Code
= DACn, DACn ≥ DNLIMn and DACn ≤ DPLIMn
= DNLIMn,
= DPLIMn,
DACn < DNLIMn
DACn > DPLIMn
Dac output =
DACn − 0x7F 255 ∗ 0.6015 + VOFF
In addition, the DAC output buffer is tri-stated if DNLIMn >
DPLIMn. In this way it is possible for the user to make it very
difficult for the DAC output buffers to be turned on at all in
normal system operation by programming the limit registers in
this way (these are among the registers downloaded from
EEPROM at startup).
where VOFF is one of the four “offset voltages” described above.
CHOOSING THE SIZE OF THE FEEDBACK RESISTOR
If the full dac output range is used to margin a supply by a fixed
amount positive and negative, then it is possible to calculate the
size of the resistor which is required. It will depend on the dc-dc
Rev. PrJ | Page 22 of 32
Preliminary Technical Data
ADM1062
TEMPERATURE MEASUREMENT SYSTEM
The ADM1062 contains an on-chip band gap temperature
sensor, whose output is digitized by the on-chip 12-bit ADC.
Theoretically, the temperature sensor and ADC can measure
temperatures from −128°C to +127°C with a resolution of
0.125°C. However, this exceeds the operating temperature range
of the device, so local temperature measurements outside this
range are not possible. Temperature measurement from −127°C
to +127°C is possible using a remote sensor. The code out is in
offset binary format, with −128°C given by code 400h, 0°C given
by 800h and +127°C given by C00h. As with the other analog
inputs to the ADC, a limit register is provided for each of the
temperature input channels. Thus, a temperature limit can be
set, such that if it is exceeded, a Warning is generated and is
available as an input to the sequencing engine. This enables the
user to control their sequence or monitor functions based on an
over temperature or under temperature event.
Figure 33 shows the input signal conditioning used to measure
the output of a remote temperature sensor. This figure shows
the external sensor as a substrate transistor, provided for
temperature monitoring on some microprocessors, but it could
equally well be a discrete transistor such as a 2N3904/06.
If a discrete transistor is used, the collector will not be
grounded, and should be linked to the base. If a PNP transistor
is used the base is connected to the DN input and the emitter to
the DP input. If an NPN transistor is used, the emitter is
connected to the DN input and the base to the DP input.
Figure 34 and Figure 35 shows how to connect the ADM1062 to
an NPN or PNP transistor for temperature measurement. To
prevent ground noise interfering with the measurement, the
more negative terminal of the sensor is not referenced to
ground, but is biased above ground by an internal diode at the
DN input.
REMOTE TEMPERATURE MEASUREMENT
To measure ∆Vbe, the sensor is switched between operating
currents of I and N × I. The resulting waveform is passed
through a 65kHz low pass filter to remove noise, and to a
chopper-stabilized amplifier that performs the functions of
amplification and rectification of the waveform to produce a
DC voltage proportional to ∆Vbe,. This voltage is measured by
the ADC to give a temperature output in 12-bit offset binary. To
further reduce the effects of noise, digital filtering is performed
by averaging the results of 16 measurement cycles. A remote
temperature measurement takes nominally 600µs. The results of
remote temperature measurements are stored in 12 bit, offset
binary format, as illustrated in. This gives temperature readings
with a resolution of 0.125°C.
The ADM1062 can measure the temperature of a remote diode
sensor or diode-connected transistor, connected to pins 37 and
38 on the LFCSP package and pins 44 and 45 on the TQFP
package (pins DN and DP).
The forward voltage of a diode or diode-connected transistor,
operated at a constant current, exhibits a negative temperature
coefficient of about −2mV/°C. Unfortunately, the absolute
value of Vbe varies from device to device, and individual
calibration is required to null this out, so the technique is
unsuitable for mass-production. The technique used in the
ADM1062 is to measure the change in Vbe when the device is
operated at two different currents.
This is given by:
∆Vbe = KT q × In
(N)
where:
K is Boltzmann’s constant.
q is charge on the carrier.
T is absolute temperature in Kelvin.
N is ratio of the two currents.
Rev. PrJ | Page 23 of 32
ADM1062
Preliminary Technical Data
Figure 33. Signal Conditioning for Remote Diode temperature Sensors
Table 7. Temperature Data Format
Temperature Digital Output (Hexꢀ
Digital Output (Binꢀ
010000000000
010000011000
010011100000
010110101000
011000000000
011001110000
011110110000
100000000000
100001010010
100011001100
100110010110
101001011000
101101001000
101111101000
110000000000
−128°C
−125°C
−100°C
−75°C
400
418
4E0
5A8
600
670
7B0
800
852
8CC
996
A58
B48
BE8
C00
−50°C
−25°C
−10°C
0°C
Figure 34. Measuring Temperature Using a NPN Transistor
+10.25°C
+25.5°C
+50.75°C
+75°C
+100°C
+125°C
+128°C
Figure 35. Measuring Temperature Using a PNP Transistor
Rev. PrJ | Page 24 of 32
Preliminary Technical Data
ADM1062
COMMUNICATING WITH THE ADM1062
CONFIGURATION DOWNLOAD AT POWER-UP
The configuration of the ADM1062– the UV/OV thresholds,
glitch filter timeouts, PDO configurations etc, is dictated by the
contents of RAM. The RAM is comprised of digital latches
which are local to each of the functions on the device. The
latches are “double buffered” and actually comprised of two
identical latches, Latch A and Latch B. Thus, the update of a
function first updates the contents of Latch A and then updates
the contents of Latch B with identical data. The advantage of the
architecture is explained in detail below. These latches are
volatile memory and lose their contents at power- down.
Therefore, at power- up the configuration in the RAM must be
restored. This is achieved by downloading the contents of the
EEPROM (non- volatile memory) to the local latches. This
download occurs in a number of steps.
The ADM1062 provides a number of options which allow the
user to update the configuration differently over the SMBus
interface. All of these options are controlled in the register
UPDCFG. The options are:
1. Update the configuration in real time. The user writes to
RAM across the SMBus and the configuration is updated
immediately.
2. Update A Latches without updating the B Latches. With
this method, the configuration of the ADM1062 will
remain unchanged and continue to operate in the original
setup until the instruction is given to update the B Latches.
3. Change EEPROM register contents without changing the
RAM contents, and then download the revised EEPROM
contents to the RAM registers. Again, with this method, the
configuration of the ADM1062 will remain unchanged and
continue to operate in the original setup until the
1. With no power applied to the device, the PDO’s are all high
impedance.
2. Once 1V appears on any of the inputs connected to the
VDD Arbitrator (VH or VPn), the PDO’s are all weakly
pulled to GND with a 20kΩ impedance.
instruction is given to update the RAM.
The instruction to download from the EEPROM in option 3
above is also a useful way to restore the original EEPROM
contents if revisions to the configuration are unsatisfactory. If
the user alters, say, an OV threshold they can do this by
updating the RAM register as described in 1 above. If they are
not satisfied with this change and wish to revert to the original
programmed value, then the device controller can issue a
command to download the EEPROM contents to the RAM
again, thus restoring the ADM1062 to its original configuration.
3. Once the supply rises above the Under voltage Lockout of
the device (UVLO is 2.5V), the EEPROM starts to
download to the RAM.
4. The EEPROM downloads its contents to all Latch A’s.
5. Once the contents of the EEPROM are completely
downloaded to Latch A’s, the device controller signals all
Latch A’s to download to all Latch B’s simultaneously, thus
completing the configuration download.
This type of operation is possible because of the topology of the
ADM1062. The Local (volatile) registers, or RAM, are all double
buffered latches. Setting bit 0 of the UPDCFG register to 1
leaves the double buffered latches open at all times. If bit 0 is set
to 0, then when RAM write occurs across the SMBus only the
first side of the double buffered latch is written to. The user
must then write a 1 to bit 1 of the UPDCFG register. This
generates a pulse to update all of the second latches at once.
Similarly with EEPROM writes.
6. 0.5ms after the configuration download, the first state
definition is downloaded from EEPROM into the
Sequencing Engine
Note– Any attempt to communicate with the device prior to
this download completion will result in a NACK being issued
from the ADM1062.
UPDATING THE CONFIGURATION OF THE
ADM1062
A final bit in this register is used to enable EEPROM page
erasure. If this bit is set high, then the contents of an EEPROM
page can all be set to 1. If low, then the contents of a page
cannot be erased, even if the command code for page erasure is
programmed across the SMBus. The bitmap for register
UPDCFG is shown in AN-698. A flow chart for download at
power up and subsequent configuration updates is shown in
Figure 36 overleaf.
Once powered up, with all of the configuration settings loaded
from EEPROM into the RAM registers, the user may wish to
alter the configuration of functions on the ADM1062 (eg)
change the UV or OV limit of an SFD, change the fault output
of an SFD, change the rise time delay of one of the PDO’s etc.
Rev. PrJ | Page 25 of 32
ADM1062
Preliminary Technical Data
Figure 36. Configuration Update Flow Diagram
(EEPROM), from register addresses F800h to FBFFh. This may
be used for permanent storage of data that will not be lost when
the ADM1062 is powered down, one EEPROM cell containing
the configuration data of the device, the other containing the
State definitions for the Sequencing Engine. Although referred
to as Read Only Memory, the EEPROM can be written to (as
well as read from) via the serial bus in exactly the same way as
the other registers. The only major differences between the
E2PROM and other registers are:
UPDATING THE SEQUENCING ENGINE OF THE
ADM1062
The update of the SE functions differently to the regular
configuration latches. The SE has its own dedicated 512 byte
EEPROM for storing State definitions, providing 63 individual
states with a 64- bit word each (one state is reserved). At power-
up, the first state is loaded from the SE EEPROM into the
engine itself. When the conditions of this state are met, the next
state is loaded from EEPROM into the engine, and so on. The
loading of each new state takes approximately 20µs. If a state is
to be altered, then the required changes must be made directly
to EEPROM. RAM for each state does not exist. The relevant
alterations must be made to the 64- bit word, which is then
uploaded directly to EEPROM.
1. An EEPROM location must be blank before it can be
written to. If it contains data, it must first be erased.
2. Writing to EEPROM is slower than writing to RAM.
3. Writing to the EEPROM should be restricted because it has
a limited write/cycle life of typically 10,000 write
operations, due to the usual EEPROM wear-out
mechanisms.
INTERNAL REGISTERS OF THE ADM1062
The ADM1062 contains a large number of data registers. A brief
description of the principal registers is given below.
The first EEPROM is split into 16 (0 to 15) pages of 32 Bytes
each. Pages 0 to 6, starting at address F800, hold the
configuration data for the applications on the ADM1062 (the
SFD’s, PDO’s etc.). These EEPROM addresses are the same as
the RAM register addresses, prefixed by F8. Page 7 is reserved.
Pages 8 to 15 are for customer use. Data can be downloaded
from EEPROM to RAM in one of two ways:–
Address Pointer Register: This register contains the address
that selects one of the other internal registers. When writing to
the ADM1062, the first byte of data is always a register address,
which is written to the Address Pointer Register.
Configuration Registers: Provide control and configuration for
various operating parameters of the ADM1062.
1. At Power- up, pages 0 to 6 are downloaded.
ADM1062 EEPROM
The ADM1062 has two 512 byte cells of non-volatile,
Electrically-Erasable Programmable Read-Only Memory
2. Setting bit 0 of the UDOWNLD Register (D8h) performs a
user download of pages 0 to 6.
Rev. PrJ | Page 26 of 32
Preliminary Technical Data
ADM1062
master will write to the slave device. If the R/ bit is a 1
W
SERIAL BUS INTERFACE
the master will read from the slave device.
Control of the ADM1062 is carried out via the serial System
Management Bus (SMBus). The ADM1062 is connected to this
bus as a slave device, under the control of a master device. It
takes approximately 1ms after power up for the ADM1062 to
download from it's EEPROM. Therefore access is restricted to
the ADM1062 until the download is completed.
2. Data is sent over the serial bus in sequences of 9 clock
pulses, 8 bits of data followed by an Acknowledge Bit from
the slave device. Data transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, as a low to high transition
when the clock is high may be interpreted as a STOP
signal. If the operation is a write operation, the first data
byte after the slave address is a command byte. This tells
the slave device what to expect next. It may be an
IDENTIFYING THE ADM1062 ON THE SMBUS
The ADM1060 has a 7-bit serial bus slave address. When the
device is powered up, it will do so with a default serial bus
address. The five MSB's of the address are set to 00101, the two
LSB's are determined by the logical states of pin A1 and A0.
This allows the connection of 4 ADM1062’s to the one SMBus.
The device also has a number of identification registers (read
only) which can be read across the SMBus. Table 8 lists these
registers, their values, and functions.
instruction such as telling the slave device to expect a block
write, or it may simply be a register address that tells the
slave where subsequent data is to be written. Since data can
flow in only one direction as defined by the R/ bit, it is
W
not possible to send a command to a slave device during a
read operation. Before doing a read operation, it may first
be necessary to do a write operation to tell the slave what
sort of read operation to expect and/or the address from
which data is to be read.
Table 8.
Name Address Value Function
MANID F4h
REVID F5h
MARK1 F6h
MARK2 F7h
41h
--h
--h
--h
Manufacturer ID for Analog Devices
Silicon Revision
S/w brand
3. When all data bytes have been read or written, stop
conditions are established. In WRITE mode, the master will
pull the data line high during the 10th clock pulse to assert
a STOP condition. In READ mode, the master device will
release the SDA line during the low period before the 9th
clock pulse, but the slave device will not pull it low. This is
known as No Acknowledge. The master will then take the
data line low during the low period before the 10th clock
pulse, then high during the 10th clock pulse to assert a
STOP condition
S/w brand
GENERAL SMBUS TIMING
Figure 37, Figure 38 and Figure 39 show timing diagrams for
general read and write operations using the SMBus. The SMBus
specification defines specific conditions for different types of
read and write operation, which are discussed later.
The general SMBus protocol operates as follows:
SMBUS PROTOCOLS FOR RAM AND EEPROM
1. The master initiates data transfer by establishing a START
condition, defined as a high to low transition on the serial
data line SDA whilst the serial clock line SCL remains high.
This indicates that a data stream will follow. All slave
peripherals connected to the serial bus respond to the
START condition, and shift in the next 8 bits, consisting of
The ADM1062 contains volatile registers (RAM) and non-
volatile EEPROM. User RAM occupies address locations from
00h to DFh, whilst EEPROM occupies addresses from F800h to
FBFFh.
Data can be written to and read from both RAM and EEPROM
as single data bytes.
a 7-bit slave address (MSB first) plus a R/ bit, which
W
determines the direction of the data transfer, i.e. whether
data will be written to or read from the slave device (0 =
write, 1 = read).
Data can only be written to unprogrammed EEPROM locations.
To write new data to a programmed location it is first necessary
to erase it. EEPROM erasure cannot be done at the byte level,
the EEPROM is arranged as 32 pages of 32 bytes, and an entire
page must be erased.
The peripheral whose address corresponds to the
transmitted address responds by pulling the data line low
during the low period before the ninth clock pulse, known
as the Acknowledge Bit, and holding it low during the high
period of this clock pulse. All other devices on the bus now
remain idle whilst the selected device waits for data to be
Page erasure is enabled by setting bit 2 in register UPDCFG
(address 90h) to 1. If this is not set then page erasure cannot
occur, even if the command byte (FEh) is programmed across
the SMBus.
read from or written to it. If the R/ bit is a 0 then the
W
Rev. PrJ | Page 27 of 32
ADM1062
Preliminary Technical Data
Figure 37. General SMBus Write Timing Diagram
Figure 38. General SMBus Read Timing Diagram
Figure 39. Diagram for Serial Bus Timing
Rev. PrJ | Page 28 of 32
Preliminary Technical Data
ADM1062
for page erasure to take place, the page address has to be
given in the previous write word transaction (see write byte
below). Also, bit 2 in register UPDCFG (address 90h) must
be set to 1.
ADM1062 WRITE OPERATIONS
The SMBus specification defines several protocols for different
types of read and write operations. The ones used in the
ADM1062 are discussed below. The following abbreviations are
used in the diagrams:
S
–
–
–
–
–
–
START
Figure 41. EEPROM Page Erasure
P
STOP
As soon as the ADM1062 receives the command byte, page
erasure begins. The master device can send a STOP
command as soon as it sends the command byte. Page
erasure takes approximately 20ms. If the ADM1062 is
accessed before erasure is complete, it will respond with a
NACK.
R
W
A
A
READ
WRITE
ACKNOWLEDGE
NO ACKNOWLEDGE
Write Byte/Word
In this operation the master device sends a command byte and
one or two data bytes to the slave device, as follows:
The ADM1062 uses the following SMBus write protocols:
Send Byte
1. The master device asserts a start condition on SDA.
In this operation the master device sends a single command
byte to a slave device, as follows:
2. The master sends the 7-bit slave address followed by the
write bit (low).
1. The master device asserts a start condition on SDA.
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master sends a data byte.
7. The slave asserts ACK on SDA.
6. The master asserts a STOP condition on SDA and the
transaction ends.
8. The master sends a data byte (or may assert STOP at this
point).
In the ADM1062, the send byte protocol is used for two
purposes.
9. The slave asserts ACK on SDA.
10. The master asserts a STOP condition on SDA to end the
transaction.
1. To write a register address to RAM for a subsequent single
byte read from the same address or block read or write
starting at that address. This is illustrated in Figure 40.
In the ADM1062, the write byte/word protocol is used for three
purposes.
1. Write a single byte of data to RAM. In this case the
command byte is the RAM address from 00h to DFh and
the (only) data byte is the actual data. This is illustrated in
Figure 42
Figure 40. Setting A RAM Address For Subsequent Read
2. Erase a page of EEPROM memory. EEPROM memory can
be written to only if it is unprogrammed. Before writing to
one or more EEPROM memory locations that are already
programmed, the page or pages containing those locations
must first be erased. EEPROM memory is erased by
writing a command byte.
Figure 42. Single Byte Write To RAM
2. Set up a two byte EEPROM address for a subsequent read,
write, block read, block write or page erase. In this case the
command byte is the high byte of the EEPROM address
from F8h to FBh. The (only) data byte is the low byte of the
The master sends a command code that tells the slave
device to erase the page. The ADM1062 command code for
a pages(s) erasure is FEh (11111110). Note that, in order
Rev. PrJ | Page 29 of 32
ADM1062
Preliminary Technical Data
EEPROM address. This is illustrated in Figure 43.
10. The master asserts a STOP condition on SDA to end the
transaction.
Figure 43. Setting An EEPROM Address
Figure 45. Block Write To EEPROM Or RAM
Note for page erasure that as a page consists of 32 bytes
only the three MSB’s of the address low byte are important.
The lower 5 bits of the EEPROM address low byte only
specify addresses within a page and are ignored during an
erase operation.
Unlike some EEPROM devices which limit block writes to
within a page boundary, there is no limitation on the start
address when performing a block write to EEPROM, except:
1. There must be at least N locations from the start address to
the highest EEPROM address (FBFFh), to avoiding writing
to invalid addresses.
3. Write a single byte of data to EEPROM. In this case the
command byte is the high byte of the EEPROM address
from F8h to FBh. The first data byte is the low byte of the
EEPROM address and the second data byte is the actual
data. This is illustrated in Figure 44
2. If the addresses cross a page boundary, both pages must be
erased before programming.
Note that the ADM1062 features a clock extend function for
writes to EEPROM. Programming an EEPROM byte takes
approximately 250µs, which would limit the SMBus clock for
repeated or block write operations. The ADM1062 pulls SCL
low and extends the clock pulse when it cannot accept any more
data.
Figure 44. Single Byte Write To EEPROM
Block Write
ADM1062 READ OPERATIONS
The ADM1062 uses the following SMBus read protocols:
Receive Byte
In this operation the master device writes a block of data to a
slave device. The start address for a block write must previously
have been set. In the case of the ADM1062 this is done by a
Send Byte operation to set a RAM address or a Write Byte/Word
operation to set an EEPROM address.
In this operation the master device receives a single byte
from a slave device, as follows:
1. The master device asserts a START condition on SDA.
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
read bit (high).
2. The master sends the 7-bit slave address followed by
the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master receives a data byte.
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code that tells the slave
device to expect a block write. The ADM1062 command
code for a block write is FCh (11111100).
5. The master asserts NO ACK on SDA.
6. The master asserts a STOP condition on SDA and the
transaction ends.
5. The slave asserts ACK on SDA.
6. The master sends a data byte that tells the slave device how
many data bytes will be sent. The SMBus specification
allows a maximum of 32 data bytes to be sent in a block
write.
In the ADM1062, the receive byte protocol is used to read a
single byte of data from a RAM or EEPROM location whose
address has previously been set by a send byte or write
byte/word operation. This is illustrated in Figure 46.
7. The slave asserts ACK on SDA.
8. The master sends N data bytes.
Figure 46. Single Byte Read From EEPROM Or RAM
9. The slave asserts ACK on SDA after each data byte.
Rev. PrJ | Page 30 of 32
Preliminary Technical Data
ADM1062
Block Read
In this operation the master device reads a block of data from a
slave device. The start address for a block read must previously
have been set. In the case of the ADM1062 this is done by a
Send Byte operation to set a RAM address, or a Write
Byte/Word operation to set an EEPROM address. The block
read operation itself consists of a Send Byte operation that
sends a block read command to the slave, immediately followed
by a repeated start and a read operation that reads out multiple
data bytes, as follows:
Figure 47. Block Read From EEPROM or RAM
Error Correction
The ADM1062 provides the option of issuing a PEC (Packet
Error Correction) byte after a write to RAM, a write to
EEPROM, a block write to RAM/EEPROM or a block read from
RAM/EEPROM. This enables the user to verify that the data
received by or sent from the ADM1062 is correct. The PEC byte
is an optional byte sent after that last data byte has been written
to or read from the ADM1062. The protocol is as follows:–
1. The master device asserts a START condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
1. The ADM1062 issues a PEC byte to the master. The master
should check the PEC byte and issue another block read if
the PEC byte is incorrect.
4. The master sends a command code that tells the slave
device to expect a block read. The ADM1062 command
code for a block read is FDh (11111101).
2. A NACK is generated after the PEC byte to signal the end
of the read.
5. The slave asserts ACK on SDA.
6. The master asserts a repeat start condition on SDA.
Note: The PEC byte is calculated using CRC-8. The Frame
Check Sequence (FCS) conforms to CRC-8 by the polynomial:–
7. The master sends the 7-bit slave address followed by the
read bit (high).
C x
( )
= x8 + x 2 + x1 + 1
8. The slave asserts ACK on SDA.
Consult SMBus 1.1 specification for more information. An
example of a block read with the optional PEC byte is shown in
Figure 48 below.
9. The ADM1062 sends a byte count data byte that tells the
master how many data bytes to expect. The ADM1062 will
always return 32 data bytes (20h), which is the maximum
allowed by the SMBus 1.1 specification.
10. The master asserts ACK on SDA.
11. The master receives 32 data bytes.
Figure 48. Block Read From EEPROM or RAM with PEC
12. The master asserts ACK on SDA after each data byte.
13. The master asserts a STOP condition on SDA to end the
transaction.
Rev. PrJ | Page 31 of 32
ADM1062
Preliminary Technical Data
OUTLINE DIMENSIONS
Figure 49. 40-Lead 6×6 Chip Scale Package
(CP-40)
Dimensions shown in millimeters
Figure 50. 48-Lead 7×7 TQFP Package
(SU-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADM1062ACP
ADM1062ASU
Temperature Range
Package Description
40-Lead LFCS
48-Lead TQFP
Package Option
CP-40
SU-48
−40°C to +85°C
−40°C to +85°C
©
2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C04433–0–12/03(PrJꢀ
Rev. PrJ | Page 32 of 32
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