ADM1232AARNZ-REEL [ADI]
Microprocessor Supervisory Circuit;
| 型号： | ADM1232AARNZ-REEL |
| 厂家： | 
ADI |
| 描述： | Microprocessor Supervisory Circuit 光电二极管 |
| 文件： | 总9页 (文件大小：187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Microprocessor
Supervisory Circuit
ADM1232A
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Precision 5 V voltage monitor with 5% or 10% tolerance options
5%/10%
TOLERANCE
SELECT
V
RESET
CC
STROBE
Adjustable
options
monitor with 150 ms, 600 ms, or 1.2 sec
TOLERANCE
VREF
STROBE
Fast (20 ns)
pulse width
RESET
No external components required
Packaged in 8-Lead SOIC
Specified from −40°C to +85°C
PB RESET
DEBOUNCE
WATCHDOG
TIMER
WATCHDOG
TIMEBASE
SELECT
STROBE
TD
ADM1232A
GND
APPLICATIONS
Figure 1.
Microprocessor systems
Portable equipment
Computers
Controllers
Intelligent instruments
Automotive systems
Protection against damage caused by microprocessor failure
GENERAL DESCRIPTION
5V
5V
The ADM1232A is pin-compatible to the MAX1232, DS1232LP,
and DS1232. The ADM1232A can detect strobe pulse widths as
narrow as 20 ns, making it compatible with high speed
microprocessors. The Analog Devices, Inc., ADM1232A is a
microprocessor monitoring circuit that monitors micro-
processor supply voltage. It can also detect if a microprocessor
has locked up or an external interrupt has been issued. The
ADM1232A is available in an 8-lead narrow body SOIC and is
specified over the −40°C to +85°C temperature range.
10kΩ
ADM1232A
MICROPROCESSOR
I/O
STROBE
RESET
GND TD TOLERANCE
RESET
Figure 2. Typical Supply Monitoring Application
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©1999–2009 Analog Devices, Inc. All rights reserved.
ADM1232A* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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DESIGN RESOURCES
• ADM1232A Material Declaration
• PCN-PDN Information
DOCUMENTATION
• Quality And Reliability
Data Sheet
• Symbols and Footprints
• ADM1232A: Microprocessor Supervisory Circuit Data
Sheet
DISCUSSIONS
View all ADM1232A EngineerZone Discussions.
REFERENCE MATERIALS
Product Selection Guide
SAMPLE AND BUY
Visit the product page to see pricing options.
• Supervisory Devices Complementary Parts Guide for
Altera FPGAs
• Supervisory Devices Complementary Parts Guide for
Xilinx FPGAs
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
Solutions Bulletins & Brochures
• Voltage Monitoring Products Applications Guide
DOCUMENT FEEDBACK
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ADM1232A
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configuration and Function Descriptions..............................5
Circuit Information...........................................................................6
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
PB RESET
.......................................................................................6
Timeout Selection.........................................................6
STROBE
TOLERANCE ................................................................................6
RESET
RESET and
Outputs.........................................................6
Outline Dimensions..........................................................................7
Ordering Guide .............................................................................7
REVISION HISTORY
1/09—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Deleted RM-8, N-8, R-16 Packages..................................Universal
Changes to Features and General Description Sections.............. 1
Changes to Table 3............................................................................ 5
Changes to Tolerance Section......................................................... 6
Changes to Ordering Guide ............................................................ 8
7/99—Revision 0: Initial Version
Rev. A | Page 2 of 8
ADM1232A
SPECIFICATIONS
VCC = full operating range, TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
TA = TMIN to TMAX
TEMPERATURE RANGE
POWER SUPPLY
Voltage
−40
+85
°C
.
4.5
5.0
20
200
5.5
50
500
V
μA
μA
Current
VIL, VIH = CMOS levels.
VIL, VIH = TTL levels.
STROBE AND PB RESET INPUTS
Input High Level
Input Low Level
2.0
−0.3
VCC + 0.3
+0.8
V
V
INPUT LEAKAGE CURRENT
(STROBE, TOLERANCE)
−1.0
+1.0
μA
μA
TD
1.6
OUTPUT CURRENT
RESET
RESET, RESET
8
10
mA
mA
When VCC is at 4.5 V to 5.5 V.
When VCC is at 4.5 V to 5.5 V.
−8
−12
OUTPUT VOLTAGE
RESET/RESET
VCC − 0.5
VCC − 0.1
V
While sourcing less than 500 μA, RESET remains within
0.5 V of VCC on power-down until VCC drops below 2.0 V.
While sinking less than 500 μA, RESET remains within 0.5 V
of GND on power-down until VCC drops below 2.0 V.
RESET/RESET High Level
RESET/RESET Low Level
0.4
V
V
2.4
1 V OPERATION
RESET Output Voltage
RESET Output Voltage
VCC − 0.1
0.1
V
V
While sourcing less than 50 μA.
While sinking less than 50 μA.
VCC TRIP POINT
5%
10%
4.5
4.25
4.62
4.37
4.74
4.49
V
V
TOLERANCE = GND.
TOLERANCE = VCC.
CAPACITANCE
Input (STROBE, TOLERANCE)
Output (RESET, RESET)
5
7
pF
pF
TA = 25°C.
TA = 25°C.
PB RESET
Time
Delay
20
1
ms
ms
ms
PB RESET must be held low for a minimum of 20 ms to
guarantee a reset.
4
20
RESET ACTIVE TIME
STROBE
250
610
1000
Pulse Width
Timeout Period
20
ns
62.5
250
500
150
600
1200
250
1000
2000
ms
ms
ms
TD = 0 V.
TD = floating.
TD = VCC.
VCC
Fall Time
Rise Time
10
0
μs
μs
Guaranteed by design.
Guaranteed by design.
VCC FAIL DETECT TO RESET
OUTPUT DELAY
RESET and RESET Are
Logically Correct
50
1000
μs
ms
After VCC falls below the set tolerance voltage (see Figure 7).
After VCC rises above the set tolerance voltage.
250
610
Rev. A | Page 3 of 8
ADM1232A
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
TA = 25°C, unless otherwise noted.
Table 2.
Parameter
Rating
VCC
5.5 V
Logic Inputs
−0.3 V to VCC + 0.3 V
−65°C to +150°C
300°C
215°C
220°C
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
ESD CAUTION
Power Dissipation
900 μW
Derate by 12 mW/°C Above 25°C
θJA Thermal Impedance (Still Air)
153°C/W
Rev. A | Page 4 of 8
ADM1232A
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PB RESET
TD
1
2
3
4
8
7
6
5
V
CC
ADM1232A
STROBE
RESET
RESET
TOLERANCE
GND
TOP VIEW
(Not to Scale)
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1
PB RESET
Push Button Reset Input. This debounced input ignores pulses of less than 1 ms and is guaranteed to respond
to pulses greater than 20 ms.
2
TD
Time Delay Set. This pin allows the user to select the maximum amount of time the ADM1232A allows the
STROBE input to remain inactive (that is, STROBE is not receiving any high-to-low transitions), without forcing
the ADM1232A to generate a RESET pulse. (See Table 1, the strobe timeout settings in Table 4, and Figure 6.)
3
TOLERANCE
Tolerance Input. This input determines how much the supply voltage will be allowed to decrease (as a percentage
tolerance) before a RESET is asserted. Connect to VCC for 10% tolerance and GND for 5% tolerance.
4
5
GND
RESET
0 V ground reference for all signals.
Active High Logic Output. This pin is asserted when VCC decreases below the amount specified by the
TOLERANCE input, or PB RESET is forced low, or if there are no high-to-low transitions within the limits set by
TD at STROBE, or during power-up.
6
7
RESET
Open Drain, Active Low Logic Output. The inverse of RESET.
STROBE
The STROBE input is used to monitor the activity of a microprocessor. If there are no high-to-low transitions
within the time specified by TD, a reset is asserted.
8
VCC
Power Supply Input +5 V.
Rev. A | Page 5 of 8
ADM1232A
CIRCUIT INFORMATION
PB RESET
Table 4. Strobe Timeout Settings
Condition
Min
62.5
250
500
Typ
150
600
1200
Max
250
Unit
PB RESET
The
input makes it possible to manually reset a
TD = 0 V
ms
ms
ms
system using either a standard push-button switch or a logic low
input. An internal debounce circuit provides glitch immunity
when used with a switch, reducing the effects of glitches on the
line. The debounce circuit is guaranteed to cause the ADM1232A
TD = floating
TD = VCC
1000
2000
PB RESET
to assert a reset if
is brought low for more than 20
STROBE
PULSE WIDTH
ms and is guaranteed to ignore low inputs of less than 1 ms.
V
V
CC
STROBE
TD
CC
ADM1232A
MICROPROCESSOR
I/O
STROBE TIMEOUT PERIOD
STROBE
STROBE
Figure 6.
Parameters
PB RESET
GND
RESET
RESET
TOLERANCE
5V
5V
V
4.5V (5% TRIP POINT)
CC
4.25V (10% TRIP POINT)
RESET OUTPUT DELAY
RESET OUTPUT DELAY
WHEN V IS RISING
Figure 4. Typical Push-Button Reset Application
WHEN V IS FALLING
CC
CC
RESET
RESET
PB RESET TIME
PB RESET
PB RESET
DELAY
V
IH
Figure 7. Reset Output Delay
V
IL
RESET ACTIVE
TIME
TOLERANCE
The TOLERANCE input is used to determine the level VCC
can vary below 5 V without the ADM1232A asserting a reset.
Connecting TOLERANCE to ground selects a −5% tolerance
level and causes the ADM1232A to generate a reset if VCC falls
below 4.75 V. If TOLERANCE is connected to VCC, a −10%
tolerance level is selected and causes the ADM1232A to
generate a reset if VCC falls below 4.5 V. Check the parameters
for the VCC trip point in the Specifications section for more
information.
RESET
RESET
PB RESET
Figure 5.
STROBE TIMEOUT SELECTION
TD or time delay set is used to set the strobe timeout period.
The strobe timeout period is defined as being the maximum
time between high-to-low transitions that
before a reset is asserted (see Figure 6). The strobe timeout
settings are listed in Table 4.
STROBE
accepts
RESET AND RESET OUTPUTS
While RESET is capable of sourcing and sinking current,
RESET
is an open drain MOSFET which sinks current only.
RESET
Therefore, it is necessary to pull
output high.
Rev. A | Page 6 of 8
ADM1232A
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 8. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
ADM1232AARNZ1
Temperature Range
−40°C to +85°C
Package Description
Package Option
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
R-8
R-8
ADM1232AARNZ-REEL1 −40°C to +85°C
1 Z = RoHS Compliant Part.
Rev. A | Page 7 of 8
ADM1232A
NOTES
©1999–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00061-0-1/09(A)
Rev. A | Page 8 of 8
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