ADM3062EACPZ-R7 [ADI]
3.0 V to 5.5 V with VIO, ±12 kV IEC ESD Protected, Half Duplex 500 kbps RS-485 Transceiver;
| 型号： | ADM3062EACPZ-R7 |
| 厂家： | 
ADI |
| 描述： | 3.0 V to 5.5 V with VIO, ±12 kV IEC ESD Protected, Half Duplex 500 kbps RS-485 Transceiver 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总25页 (文件大小：536K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.0 V to 5.5 V, ±12 kV IEC ESD Protected,
500 kbps/50 Mbps RS-485 Transceiver
ADM3061E/ADM3062E/ADM3065E/ADM3066E
FUNCTIONAL BLOCK DIAGRAMS
Data Sheet
FEATURES
V
CC
TIA/EIA RS-485 compliant over full supply range
3.0 V to 5.5 V operating voltage range on VCC
1.62 V to 5.5 V VIO logic supply
R
RO
RE
ESD protection on the bus pins
A
B
IEC 61000-4-2 ≥ 12 kV contact discharge
IEC 61000-4-2 ≥ 12 kV air discharge
HBM ≥ 30 kV
DE
DI
D
Full hot swap support (glitch free power-up/power-down)
High-speed 50 Mbps data rate (ADM3065E/ADM3066E)
Low speed 500 kbps data rate for long cables (ADM3061E/
ADM3062E)
Full receiver short-circuit, open circuit, and bus idle fail-safe
Extended temperature range up to 125°C
Profibus compliant at VCC ≥ 4.5 V
ADM3061E/ADM3065E
GND
Figure 1. ADM3061E/ADM3065E Functional Block Diagram
V
CC
V
IO
Half duplex
R
RO
RE
Allows connection of up to 128 nodes onto the bus
Space-saving package options
A
B
LEVEL
TRANSLATOR
10-lead, 3 mm × 3 mm LFCSP
8-lead and 10-lead MSOP
8-lead, narrow body SOIC package
DE
DI
D
ADM3062E/ADM3066E
APPLICATIONS
GND
Industrial fieldbuses
Process control
Figure 2. ADM3062E/ADM3066E Functional Block Diagram
Table 1. Summary of the ADM3061E/ADM3062E/ADM3065E/
ADM3066E Operating Conditions—Data Rate Capability
Across Temperature, Power Supply, and Package
Building automation
Profibus networks
Motor control servo drives and encoders
Maximum
Data Rate1
Maximum Maximum
Package
Description
VCC (V)
Temperature
50 Mbps
50 Mbps
5.5
5.5
−40°C to +125°C 10-lead LFCSP
−40°C to +105°C 8-lead SOIC_N,
8-lead MSOP, and
10-lead MSOP
50 Mbps
500 kbps
3.6
5.5
−40°C to +125°C 8-lead SOIC_N,
8-lead MSOP, and
10-lead MSOP
−40°C to +125°C 8-lead SOIC_N,
8-lead MSOP, 10-lead
MSOP, 10-lead LFCSP
1 The ADM3065E/ADM3066E data input (DI) is transmitting 50 Mbps (or 500 kbps
for the ADM3061E/ADM3062E) clock data, and the ADM3061E/ADM3062E/
ADM3065E/ADM3066E driver enable (DE) is enabled for 50% of the DI transmit
time.
Rev. C
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ADM3061E/ADM3062E/ADM3065E/ADM3066E
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 17
IEC ESD Protected RS-485 ....................................................... 17
High Driver Differential Output Voltage................................ 17
IEC 61000-4-2 ESD Protection ................................................ 17
Truth Tables................................................................................. 18
Receiver Fail-Safe ....................................................................... 18
Hot Swap Capability................................................................... 19
128 Transceivers on the Bus...................................................... 19
Driver Output Protection.......................................................... 19
Applications Information.............................................................. 20
Isolated High Speed RS-485 Node........................................... 21
Outline Dimensions....................................................................... 23
Ordering Guide .......................................................................... 25
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
General Description......................................................................... 3
Specifications..................................................................................... 4
ADM3061E/ADM3062E Timing Specifications...................... 6
ADM3065E/ADM3066E Timing Specifications...................... 8
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution.................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Test Circuits..................................................................................... 12
Typical Performance Characteristics ........................................... 13
REVISION HISTORY
2/2018—Rev. B to Rev. C
Added Figure 24, Figure 25, Figure 26, Figure 27, and Figure 28...14
Changed High Speed IEC ESD Protected RS-485 Section to IEC
ESD Protected RS-485 Section..............................................................17
Changes to IEC ESD Protected RS-485 Section ................................17
Added Endnote 4, Table 9 ......................................................................18
Changes to Table 10.................................................................................18
Changes to Figure 44...............................................................................21
Changes to Figure 45...............................................................................22
Changes to Ordering Guide.......................................................... 25
Added ADM3062E.............................................................Universal
Changes to Figure 2 and Table 1 .............................................................1
Changes to ADM3061E/ADM3062E Timing Specifications
Section and Figure 3................................................................................6
Changes to Figure 5 and Figure 6 ...........................................................7
Changes to Figure 9 and Figure 10 .......................................................11
Changes to Figure 16 and Figure 17.....................................................12
Changes to Figure 44...............................................................................21
Changes to Figure 45...............................................................................22
Changes to Ordering Guide...................................................................25
5/2017—Rev. 0 to Rev. A
Added ADM3066E.............................................................Universal
Changes to Features Section, Figure 1, and Table 1 ......................1
Added Figure 2; Renumbered Sequentially ...................................1
Moved General Description Section...............................................3
Changes to General Description Section .......................................3
Changes to Specifications Section and Table 2 ..............................4
Changes to Timing Specifications Section and Figure 3..............5
Changes to Figure 4, Figure 5, and Figure 6 ..................................6
Added VIO to GND Parameter, Table 4...........................................7
Changes to Thermal Resistance Section and Table 5 ...................7
Added Figure 8...................................................................................8
Changes to Table 6.............................................................................8
Added Figure 9 and Figure 10 .........................................................9
Added Table 7; Renumbered Sequentially .....................................9
Changes to Figure 14, Figure 16, and Figure 17......................... 10
Changes to Table 8 and Table 9 .................................................... 15
Added Figure 42 and Figure 43 .................................................... 20
Changes to Ordering Guide.......................................................... 21
12/2017—Rev. A to Rev. B
Added ADM3061E.............................................................Universal
Changes to Product Title, Features Section, Figure 1, and Table 1...1
Changes to General Description Section ...................................... 3
Changes to Table 2 ............................................................................ 4
Added ADM3061E Timing Specification Section and Table 3;
Renumbered Sequentially................................................................ 6
Moved Figure 3 ................................................................................. 6
Moved Figure 4, Figure 5, and Figure 6......................................... 7
Changes to ADM3065E/ADM3066E Timing Specification
Section Title....................................................................................... 8
Added 10-Lead MSOP Parameter and 10-Lead LFCSP Parameter,
Table 5 ................................................................................................. 9
Changes to Operating Temperature Range Parameter, Table 5
and Table 6......................................................................................... 9
Changes to Figure 7, Figure 8, and Table 7 .................................... 10
Changes to Table 8 .......................................................................... 11
Changes to Figure 11...................................................................... 12
Added Figure 23; Renumbered Sequentially .............................. 13
3/2017—Revision 0: Initial Version
Rev. C | Page 2 of 25
ADM3061E/ADM3062E/ADM3065E/ADM3066E
Data Sheet
GENERAL DESCRIPTION
The ADM3065E is a 3.0 V to 5.5 V, IEC electrostatic discharge
(ESD) protected RS-485 transceiver, allowing the device to
withstand 12 kV contact discharges on the transceiver bus
pins without latch-up or damage. The ADM3066E/ADM3062E
features a VIO logic supply pin allowing a flexible digital interface
capable of operating as low as 1.62 V.
The RS-485 transceivers are available in a number of space-
saving packages, such as a 10-lead, 3 mm × 3 mm LFCSP, an 8-lead,
3 mm × 3 mm MSOP, a 10-lead, 3 mm × 3 mm MSOP, and an 8-
lead, narrow body SOIC package. Models with operating
temperature ranges of −40°C to +125°C and −40°C to +85°C
are available.
The ADM3065E/ADM3066E are suitable for high speed,
50 Mbps, bidirectional data communication on multipoint bus
transmission lines. The
ADM3061E/ADM3062E/ADM3065E/ADM3066E feature a ¼
unit load input impedance, which allows up to 128 transceivers
on a bus. The ADM3061E/ADM3062E models offer all of the
same features as the ADM3065E/ADM3066E models, but at a
low 500 kbps data rate suitable for operation over long cable
runs.
Excessive power dissipation caused by bus contention or by
output shorting is prevented by a thermal shutdown circuit. If,
during fault conditions, a significant temperature increase is
detected in the internal driver circuitry, this feature forces the
driver output into a high impedance state.
The ADM3061E/ADM3062E/ADM3065E/ADM3066E
guarantee a logic high receiver output when the receiver inputs
are shorted, open, or connected to a terminated transmission
line with all drivers disabled.
The ADM3061E/ADM3062E/ADM3065E/ADM3066E are half-
duplex RS-485 transceivers, fully compliant to the Profibus®
Table 1 presents an overview of the ADM3061E/ADM3062E/
ADM3065E/ADM3066E data rate capability across temperature,
power supply, and package options. Refer to the Ordering Guide
for model numbering.
standard with increased 2.1 V bus differential voltage at VCC
≥
4.5 V.
Rev. C | Page 3 of 25
ADM3061E/ADM3062E/ADM3065E/ADM3066E
SPECIFICATIONS
Data Sheet
VCC = 3.0 V to 5.5 V, VIO = 1.62 V to VCC, TA = TMIN (−40°C) to TMAX (+125°C), unless otherwise noted. All typical specifications are at
TA = 25°C, VIO = VCC = 3.3 V unless otherwise noted.
Table 2.
Parameter
Symbol Min
Typ Max
Unit Test Conditions/Comments
POWER SUPPLY
Supply Current
ICC
2
7.5
7.5
4.5
172
75
mA No load, DE = VCC, RE = 0 V
mA No load, DE = VCC, RE = VCC
mA No load, DE = 0 V, RE = 0 V
mA 50 Mbps, load resistance (RL) = 54 Ω, DE = VCC, RE = 0 V
mA 50 Mbps, RL = 54 Ω, DE = VCC, RE = 0 V (VCC = 3.0 V)
mA 500 kbps, RL = 54 Ω, DE = VCC, RE = 0 V
mA 500 kbps, RL = 54 Ω, DE = VCC, RE = 0 V (VCC = 3.0 V)
67
165
74
Supply Current in Shutdown Mode
VIO Shutdown Current
ISHDN
450
50
µA
µA
DE = 0 V, RE = VCC
DE = 0 V, RE = VIO
IIOSHDN
DRIVER
Differential Outputs
Output Voltage, Loaded
|VOD2
|VOD2
|VOD2
|VOD2
|VOD3
|VOD3
|
|
|
|
|
|
2.0
1.5
2.1
2.1
1.5
2.1
VCC
VCC
VCC
VCC
VCC
VCC
0.2
V
V
V
V
V
V
V
VCC ≥ 3.0 V, RL = 50 Ω, see Figure 11
VCC ≥ 3.0 V, RL = 27 Ω (RS-485), see Figure 11
VCC ≥ 4.5 V, RL = 50 Ω, see Figure 11
VCC ≥ 4.5 V, RL = 27 Ω (RS-485), see Figure 11
VCC ≥ 3.0 V, −7 V ≤ VCM ≤ +12 V, see Figure 12
VCC ≥ 4.5 V, −7 V ≤ VCM ≤ +12 V, see Figure 12
RL = 27 Ω or 50 Ω, see Figure 11
∆|VOD| for Complementary Output
States
∆|VOD|
Common-Mode Output Voltage
∆|VOC| for Complementary Output
States
VOC
∆|VOC|
3.0
0.2
V
V
RL = 27 Ω or 50 Ω, see Figure 11
RL = 27 Ω or 50 Ω, see Figure 11
Output Short-Circuit Current
Logic Inputs (DE, RE, DI)
Input Voltage
IOS
−250
250
mA −7 V < output voltage (VOUT) < +12 V
Low
VIL
VIH
II
0.33 ×
VIO
V
DE, RE, DI, 1.62 V ≤ VIO ≤ 5.5 V
DE, RE, DI, 1.62 V ≤ VIO ≤ 5.5 V
High
0.67 ×
VIO
−2
V
Input Current
+2
µA
DE, RE, DI, 1.62 V ≤ VIO ≤ 5.5 V, 0 V ≤ input voltage
(VIN) ≤ VIO
Rev. C | Page 4 of 25
ADM3061E/ADM3062E/ADM3065E/ADM3066E
Data Sheet
Parameter
Symbol Min
Typ Max
Unit Test Conditions/Comments
RECEIVER
Differential Inputs
Differential Input Threshold Voltage
Input Voltage Hysteresis
Input Current (A, B)
VTH
VHYS
II
−200
−125 −30
30
mV −7 V < common-mode voltage (VCM) < +12 V
mV −7 V < VCM < +12 V
mA DE = 0 V, VCC = powered/unpowered, VIN = 12 V
mA DE = 0 V, VCC = powered/unpowered, VIN = −7 V
0.25
−0.20
48
Line Input Resistance
Logic Outputs
Output Voltage
Low
RIN
kΩ
−7 V ≤ VCM ≤ +12 V
1
VOL
0.4
V
VIO = 3.6 V, output current (IOUT) = +2 mA, VID
−0.2 V
≤
0.4
0.2
V
V
V
V
V
VIO = 2.7 V, IOUT = +1 mA, VID ≤ −0.2 V
VIO = 1.95 V, IOUT = +500 µA, VID ≤ −0.2 V
VIO = 3.0 V, IOUT = −2 mA, VID ≥ +0.2 V
VIO = 2.3 V, IOUT = −1 mA, VID ≥ +0.2 V
VIO = 1.65 V, IOUT = −500 µA, VID ≥ +0.2 V
High
VOH
2.4
2.0
VIO −
0.2
Short-Circuit Current
Three-State Output Leakage
85
2
mA VOUT = GND or VCC
µA RO = 0 V or VCC
IOZR
1 VID is the receiver input differential voltage.
Rev. C | Page 5 of 25
ADM3061E/ADM3062E/ADM3065E/ADM3066E
Data Sheet
ADM3061E/ADM3062E TIMING SPECIFICATIONS
VCC = 3.0 V to 5.5 V, VIO = 1.62 V to VCC, TA = TMIN (−40°C) to TMAX (+125°C), unless otherwise noted. All typical specifications are at
TA = 25°C, VIO = VCC = 3.3 V, unless otherwise noted.
Table 3.
Parameter
Symbol
Min Typ
Max Unit
Test Conditions/Comments
DRIVER
Maximum Data Rate1
Propagation Delay
Skew
500
220
5
kbps
tDPLH, tDPHL
tDSKEW
tDR, tDF
tDZH
tDZL
tDLZ
800
100
800
ns
ns
ns
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 13
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 13
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 13
RL = 110 Ω, CL = 50 pF, see Figure 14
RL = 110 Ω, CL = 50 pF, see Figure 14
RL = 110 Ω, CL = 50 pF, see Figure 14
RL = 110 Ω, CL = 50 pF, see Figure 14
RL = 110 Ω, CL = 50 pF, see Figure 14
RL = 110 Ω, CL = 50 pF, see Figure 14
Rise/Fall Times
120
Enable to Output High
Enable to Output Low
Disable Time from Low
Disable Time from High
Enable Time from Shutdown to High tDZH(SHDN)
Enable Time from Shutdown to Low tDZL(SHDN)
1000 ns
1000 ns
2000 ns
2000 ns
2000 ns
2000 ns
tDHZ
RECEIVER
Maximum Data Rate
Propagation Delay
Skew/Pulse Width Distortion
Enable to Output High
500
Kbps
ns
ns
ns
tRPLH, tRPHL
tRSKEW
tRZH
200
50
50
CL = 15 pF, |VID| ≥ 1.5 V, see Figure 15
CL = 15 pF, |VID| ≥ 1.5 V, VCM = 1.5 V, see Figure 15
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, DE high,
see Figure 17
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, DE high,
see Figure 17
10
10
Enable to Output Low
tRZL
50
ns
Disable Time from Low
Disable Time from High
Enable from Shutdown to High
Enable from Shutdown to Low
TIME TO SHUTDOWN
tRLZ
tRHZ
tRZH(SHDN)
tRZL(SHDN)
tSHDN
10
10
50
50
ns
ns
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 17
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 17
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 16
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 16
2000 ns
2000 ns
ns
40
1 Maximum data rate assumes a ratio of tDR:tBIT:tDF equal to 1:0.5:1.
Timing Diagrams
V
CC
1/2V
1/2V
CC
CC
tSKEW
= tDPLH – tDPHL
0V
B
tDPLH
tDPHL
1/2V
OD
V
OD
A
+V
OD
90% POINT
10% POINT
90% POINT
V
= V – V
(A) (B)
OD
V
OD
10% POINT
–V
OD
tDF
tDR
NOTES
1. V IS THE DIFFERENCE BETWEEN A AND B,
OD
WITH +V BEING THE MAXIMUM POINT OF V
,
OD
OD
AND –V BEING THE MINIMUM POINT OF V
.
OD
OD
2. V = V FOR ADM3066E/ADM3062E.
CC
IO
Figure 3. Driver Propagation Delay Rise and Fall Timing Diagram
Rev. C | Page 6 of 25
ADM3061E/ADM3062E/ADM3065E/ADM3066E
Data Sheet
V
IO
1/2V
tDLZ
DE
IO
1/2V
IO
0V
tDZL
V
IO
1/2 (V – V
)
IO
OL
A OR B
V
+ 0.5V
– 0.5V
OL
V
V
OL
tDZH
tDHZ
OH
V
A OR B
NOTES
OH
1/2V
OH
0V
1. V = V FOR ADM3065E/ADM3061E.
IO
CC
Figure 4. Driver Enable and Disable Timing Diagram
A – B
0V
0V
tRPLH
tRPHL
V
V
OH
1/2V
1/2V
CC
CC
RO
tRSKEW
= |tRPLH – tRPHL|
OL
NOTES
1. V
= V FOR ADM3066E/ADM3062E.
CC
IO
Figure 5. Receiver Propagation Delay Timing Diagram
0.7V
CC
1/2V
tRZL
0.5V
CC
CC
.3V
CC
tRLZ
1/2V
1/2V
CC
V
V
+ 0.5V
OL
OUTPUT LOW
V
V
OL
tRHZ
tRZH
OUTPUT HIGH
CC
OH
– 0.5V
OH
NOTES
1. V = V FOR ADM3066E/ADM3062E.
CC
IO
Figure 6. Receiver Enable and Disable Timing Diagram
Rev. C | Page 7 of 25
ADM3061E/ADM3062E/ADM3065E/ADM3066E
Data Sheet
ADM3065E/ADM3066E TIMING SPECIFICATIONS
VCC = 3.0 V to 5.5 V, VIO = 1.62 V to VCC, TA = TMIN (−40°C) to TMAX (+125°C), unless otherwise noted. All typical specifications are at
TA = 25°C, VIO = VCC = 3.3 V, unless otherwise noted.
Table 4.
Parameter
Symbol
Min Typ
Max Unit
Test Conditions/Comments
DRIVER
Maximum Data Rate1
Propagation Delay
Skew
50
Mbps
tDPLH, tDPHL
tDSKEW
tDR, tDF
tDZH
tDZL
tDLZ
9
1
4
10
10
10
10
15
2
ns
ns
ns
ns
ns
ns
ns
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 13
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 13
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 13
RL = 110 Ω, CL = 50 pF, see Figure 14
RL = 110 Ω, CL = 50 pF, see Figure 14
RL = 110 Ω, CL = 50 pF, see Figure 14
RL = 110 Ω, CL = 50 pF, see Figure 14
RL = 110 Ω, CL = 50 pF, see Figure 14
RL = 110 Ω, CL = 50 pF, see Figure 14
Rise/Fall Times
6.7
30
30
30
30
Enable to Output High
Enable to Output Low
Disable Time from Low
Disable Time from High
Enable Time from Shutdown to High tDZH(SHDN)
Enable Time from Shutdown to Low tDZL(SHDN)
tDHZ
2000 ns
2000 ns
RECEIVER
Maximum Data Rate
Propagation Delay
Skew/Pulse Width Distortion
Enable to Output High
50
Mbps
ns
ns
ns
tRPLH, tRPHL
tRSKEW
tRZH
35
3
35
CL = 15 pF, |VID| ≥ 1.5 V, see Figure 15
CL = 15 pF, |VID| ≥ 1.5 V, VCM = 1.5 V, see Figure 15
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, DE high,
see Figure 17
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, DE high,
see Figure 17
10
10
Enable to Output Low
tRZL
35
ns
Disable Time from Low
Disable Time from High
Enable from Shutdown to High
Enable from Shutdown to Low
TIME TO SHUTDOWN
tRLZ
tRHZ
tRZH(SHDN)
tRZL(SHDN)
tSHDN
10
10
35
35
ns
ns
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 17
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 17
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 16
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 16
2000 ns
2000 ns
ns
40
1 Maximum data rate assumes a ratio of tDR:tBIT:tDF equal to 1:1:1.
Rev. C | Page 8 of 25
ADM3061E/ADM3062E/ADM3065E/ADM3066E
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 5.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required. θJA is the natural convection
junction to ambient thermal resistance measured in a one cubic
foot sealed enclosure. θJC is the junction to case thermal
resistance.
Parameter
Rating
VCC to GND
VIO to GND
Digital Input/Output Voltage (DE, RE,
DI, and RO)
Driver Output/Receiver Input Voltage
Operating Temperature Range
6 V
−0.3 V to +6 V
−0.3 V to VCC + 0.3 V
−9 V to +14 V
−40°C to +85°C
−40°C to +125°C
−65°C to + 150°C
Table 6. Thermal Resistance
1
1
Package Type
θJA
θJC
Unit
°C/W
°C/W
°C/W
°C/W
Storage Temperature Range
Continuous Total Power Dissipation
8-Lead SOIC_N
8-Lead MSOP
10-Lead MSOP
10-Lead LFCSP
Maximum Junction Temperature
Lead Temperature
Soldering (10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
R-8
RM-8
RM-10
CP-10-9
110.88
165.69
165.69
55.65
58.63
49.61
49.61
33.22
0.225 W
0.151 W
0.151 W
0.450 W
150°C
1 Thermal impedance simulated values are based on JEDEC 2S2P thermal test
board with no bias. See JEDEC JESD-51.
ESD CAUTION
300°C
215°C
220°C
ESD on the Bus Pins (A and B)
IEC 61000-4-2 Contact Discharge
IEC 61000-4-2 Air Discharge
12 kV
Ten Positive and Ten Negative
Discharges
Three Positive or Negative
Discharges
12 kV
15 kV
ESD Human Body Model (HBM)
On the Bus Pins (A and B)
All Other Pins
> 30 kV
8 kV
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. C | Page 9 of 25
ADM3061E/ADM3062E/ADM3065E/ADM3066E
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
RO
RE
DE
DI
1
2
3
4
8
7
6
5
V
CC
RO
RE
DE
DI
1
2
3
4
8
7
6
5
V
CC
ADM3061E/
ADM3065E
B
ADM3061E/
ADM3065E
B
A
TOP VIEW
A
(Not to Scale)
TOP VIEW
GND
(Not to Scale)
GND
Figure 8. ADM3061E/ADM3065E 8-Lead MSOP Pin Configuration
Figure 7. ADM3061E/ADM3065E 8-Lead Narrow Body SOIC_N Pin
Configuration
Table 7. ADM3061E/ADM3065E Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
RO
RE
Receiver Output Data. This output is high when (A − B) ≥ −30 mV and low when (A − B) ≤ −200 mV. This output is
tristated when the receiver is disabled; that is, when RE is driven high.
Receiver Enable Input. This is an active low input. Driving this input low enables the receiver, and driving it high
disables the receiver.
Driver Output Enable. A high level on this pin enables the driver differential outputs, A and B. A low level places
the driver output into a high impedance state.
DE
4
5
6
DI
GND
A
Transmit Data Input. Data to be transmitted by the driver is applied to this input.
Ground.
Noninverting Driver Output/Receiver Input. When the driver is disabled, or when VCC is powered down, Pin A is put
into a high impedance state to avoid overloading the bus.
7
8
B
Inverting Driver Output/Receiver Input. When the driver is disabled, or when VCC is powered down, Pin B is put into
a high impedance state to avoid overloading the bus.
3.0 V to 5.5 V Power Supply. Adding a 0.1 µF decoupling capacitor between the VCC pin and the GND pin is
recommended.
VCC
Rev. C | Page 10 of 25
ADM3061E/ADM3062E/ADM3065E/ADM3066E
Data Sheet
V
1
2
3
4
5
10
9
V
CC
IO
V
1
10 V
CC
IO
RO
DE
RE
DI
B
ADM3066E/
ADM3062E
RO 2
DE 3
RE 4
DI 5
9
8
7
6
B
ADM3066E/
ADM3062E
8
A
A
7
NC
GND
TOP VIEW
(Not to Scale)
TOP VIEW
(Not to Scale)
NC
GND
6
NOTES
1. NC = NO CONNECT.
NOTES
1. NC = NO CONNECT.
2. EXPOSED PAD. THE EXPOSED PAD
MUST BE CONNECTED TO GROUND.
Figure 10. ADM3066E/ADM3062E 10-Lead MSOP Pin Configuration
Figure 9. ADM3066E/ADM3062E 10-Lead LFCSP Pin Configuration
Table 8. ADM3066E/ADM3062E Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
4
VIO
RO
DE
RE
1.62 V to 5.5 V Logic Supply. Adding a 0.1 µF decoupling capacitor between the VIO pin and the GND pin is
recommended.
Receiver Output Data. This output is high when (A − B) ≥ −30 mV and low when (A − B) ≤ −200 mV. This output is
tristated when the receiver is disabled; that is, when RE is driven high.
Driver Output Enable. A high level on this pin enables the driver differential outputs, A and B. A low level places
the driver output into a high impedance state.
Receiver Enable Input. This is an active low input. Driving this input low enables the receiver, and driving it high
disables the receiver.
5
6
7
8
DI
Transmit Data Input. Data to be transmitted by the driver is applied to this input.
Ground.
No Connect. Do not connect to this pin.
Noninverting Driver Output/Receiver Input. When the driver is disabled, or when VCC is powered down, Pin A is put
into a high impedance state to avoid overloading the bus.
GND
NC
A
9
B
Inverting Driver Output/Receiver Input. When the driver is disabled, or when VCC is powered down, Pin B is put into
a high impedance state to avoid overloading the bus.
10
VCC
EPAD
3.0 V to 5.5 V Power Supply. Adding a 0.1 µF decoupling capacitor between the VCC pin and the GND pin is
recommended.
Exposed Pad. The exposed pad must be connected to ground.
Rev. C | Page 11 of 25
ADM3061E/ADM3062E/ADM3065E/ADM3066E
TEST CIRCUITS
Data Sheet
A
B
R
L
INPUT
GENERATOR
V
V
V
DI
OD2
IN
OUT
RE
C
L
R
V
L
OC
RE = 0V
Figure 11. Driver Voltage Measurements
Figure 15. Receiver Propagation Delay/Skew
+1.5V
–1.5V
375Ω
V
CC
S1
R
V
L
V
CM
DI
OD3
60Ω
S2
RE
L
OUT
375Ω
RE IN
NOTES
1. V
= V FOR ADM3066E/ADM3062E.
CC
IO
Figure 12. Driver Voltage Measurements over Common-Mode Range
Figure 16. Receiver Enable/Disable from Shutdown
V
CC
V
CC
C
C
L1
DE
DI
R
LDIFF
DI
S1
D
L2
V
CC
A
B
Figure 13. Driver Propagation Delay
V
R
OUT
L
S2
R
C
V
L
CC
RE
R
L
RE IN
0V OR V
S2
S1
IO
DE
C
NOTES
1. V = V FOR ADM3066E/ADM3062E.
L
CC
IO
DE IN
NOTES
1. V = V FOR ADM3065E/ADM3061E.
IO CC
Figure 17. Receiver Enable/Disable
Figure 14. Driver Enable/Disable
Rev. C | Page 12 of 25
ADM3061E/ADM3062E/ADM3065E/ADM3066E
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
400
0.12
0.10
350
V
V
V
= 5.5V
= 4.5V
= 3.3V
CC
CC
CC
V
= 5.5V
CC
300
250
200
150
100
50
0.08
0.06
0.04
0.02
0
V
= 5.0V
CC
V
= 3.3V
CC
0
–40 –25 –10
5
20
35
50
65
80 95 110 125
0
5
10
15
20
25
30
35
40
45
50
TEMPERATURE (°C)
DATA RATE (Mbps)
Figure 18. Shutdown Current (ISHDN) vs. Temperature
Figure 21. Supply Current (ICC) vs. Data Rate with 54 Ω Load Resistance
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
0.08
0.07
0.06
0.05
R
= 54Ω
L
R
= 120Ω
L
V
= 5.5V
CC
NO LOAD
0.04
0.03
0.02
0.01
0
V
= 5.0V
CC
V
= 3.3V
CC
–40 –25 –10
5
20
35
50
65
80 95 110 125
0
5
10
15
20
25
30
35
40
45
50
TEMPERATURE (°C)
DATA RATE (Mbps)
Figure 19. Supply Current (ICC) vs. Temperature, Data Rate = 50 Mbps, VCC = 3.3 V
Figure 22. Supply Current (ICC) vs. Data Rate with No Load Resistance
0.10
0.12
V
V
V
V
= 3.3V, NO LOAD
= 3.3V, 54Ω LOAD
= 5V, NO LOAD
= 5V, 54Ω LOAD
CC
CC
CC
CC
R
= 54Ω
L
0.10
0.08
0.06
0.04
0.02
0
0.08
0.06
0.04
0.02
0
R
= 120Ω
L
NO LOAD
0
50
100 150 200 250 300 350 400 450 500
DATA RATE (kbps)
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
Figure 20. Supply Current (ICC) vs. Temperature, Data Rate = 50 Mbps, VCC = 5.0 V
Figure 23. Supply Current (ICC) vs. Data Rate with 54 Ω Load Resistance and
No Load Resistance
Rev. C | Page 13 of 25
ADM3061E/ADM3062E/ADM3065E/ADM3066E
Data Sheet
60
50
40
30
20
10
0
V
ID
1
R
OUT
2
B
B
W
CH1 1.0V
A CH1
0V
–55
–35
–15
5
25
45
65
85
105
125
CH2 1.0V
W
TEMPERATURE (°C)
Figure 24. Supply Current (ICC) vs. Temperature,
Data Rate = 500 kbps, VCC = 3.0 V
Figure 27. Receiver Propagation Delay (Oscilloscope Plot)
500 kbps VID ≥ 1.5 V
140
DI
120
100
80
60
40
20
0
1
A
B
2
M1
V
OD
B
B
B
W
CH1 3.0V
CH3 2.0V
CH2 2.0V
M1 2.5V
A CH1
1.98V
W
W
–60 –40 –20
0
20
40
60
80
100 120 140
TEMPERATURE (°C)
Figure 25. Supply Current (ICC) vs. Temperature,
Data Rate = 500 kbps, VCC = 5.5 V
Figure 28. Driver Propagation Delay (Oscilloscope Plot) 500 kbps
300
280
260
240
220
200
180
160
140
12
11
10
9
T
T
T
T
AT 5.5V
AT 5.5V
AT 3.0V
AT 3.0V
DPLH
DPHL
DPLH
DPHL
8
7
tDPHL
tDPLH
tDPHL
tDPLH
V
V
V
V
= 3.0V
= 3.0V
= 5.5V
= 5.5V
,
,
,
,
CC
CC
CC
CC
6
5
4
–60 –40 –20
0
20
40
60
80
100 120 140
–40 –25 –10
5
20
35
50
65
80 95 110 125
TEMPERATURE (⁰C)
TEMPERATURE (°C)
Figure 29. Driver Differential Propagation Delay vs. Temperature, 50 Mbps
Figure 26. Driver Differential Propagation Delay vs. Temperature
(500 kbps models)
Rev. C | Page 14 of 25
ADM3061E/ADM3062E/ADM3065E/ADM3066E
Data Sheet
0.04
V
= V = 3.3 V
CC
IO
DI
0.02
0
1
–0.02
–0.04
–0.06
–0.08
–0.10
V
OD
2
B
B
C1 1.0V/DIV
C2 2.0V/DIV
50Ω
50Ω
: 1.5G
: 1.5G
20ns/DIV
5.0GS/s
200ps/pt
A C1 1.34V
W
W
–7 –6 –5 –4 –3 –2 –1
0
1
2
3
4
5
DRIVER OUTPUT HIGH VOLTAGE (V)
Figure 30. Driver Propagation Delay at 50 Mbps
Figure 33. Driver Output Current vs. Driver Output High Voltage
0.10
0.04
0.02
V
= V = 3.3 V
IO CC
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
0
–0.02
–0.04
–0.06
–0.08
–0.10
–0.12
V
V
V
= 5.5V
= 4.5V
= 3.0V
CC
CC
CC
0
2
4
6
8
10
12
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
DRIVER DIFFERENTIAL OUTPUT VOLTAGE (V)
DRIVER OUTPUT LOW VOLTAGE (V)
Figure 31. Driver Output Current vs. Driver Differential Output Voltage
Figure 34. Driver Output Current vs. Driver Output Low Voltage
3.2
3.0
V
ID
V
= 4.5V
CC
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1
R
OUT
V
= 3.0V
CC
2
B
C1 1.0V/DIV
C2 1.0V/DIV
50Ω
50Ω
: 1.5G
: 1.5G
20ns/DIV
5.0GS/s
200ps/pt
A C1 0.0V
W
–40 –25 –10
5
20
35
50
65
80 95 110 125
B
W
TEMPERATURE (°C)
Figure 32. Driver Differential Output Voltage vs. Temperature
Figure 35. Receiver Propagation Delay at 50 Mbps, |VID| ≥ 1.5 V
Rev. C | Page 15 of 25
ADM3061E/ADM3062E/ADM3065E/ADM3066E
Data Sheet
6.0
5.8
5.6
5.4
5.2
5.0
28
26
tRPHL
24
tRPLH
22
20
18
16
–40 –25 –10
5
20
35
50
65
80 95 110 125
–40 –25 –10
5
20
35
50
65
80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 36. Receiver Propagation Delay vs. Temperature, 50 Mbps
Figure 39. Receiver Output High Voltage vs. Temperature
0.035
0.25
0.20
0.15
0.10
0.05
0
V
= 3.3V
CC
0.030
0.025
0.020
0.015
0.010
0.005
0
–40 –25 –10
5
20
35
50
65
80 95 110 125
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
TEMPERATURE (°C)
RECEIVER OUTPUT LOW VOLTAGE (V)
Figure 40. Receiver Output Low Voltage vs. Temperature
Figure 37. Receiver Output Current vs. Receiver Output Low Voltage (VCC = 3.3 V)
0
V
= 3.3V
CC
–0.005
–0.010
–0.015
–0.020
–0.025
–0.030
–0.035
–0.040
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
RECEIVER OUTPUT HIGH VOLTAGE (V)
Figure 38. Receiver Output Current vs. Receiver Output High Voltage (VCC = 3.3 V)
Rev. C | Page 16 of 25
ADM3061E/ADM3062E/ADM3065E/ADM3066E
Data Sheet
THEORY OF OPERATION
I
PEAK
IEC ESD PROTECTED RS-485
30A
90%
The ADM3065E/ADM3066E are 3.0 V to 5.5 V, 50 Mbps RS-485
transceivers with IEC 61000-4-2 Level 4 ESD protection on the
bus pins. The ADM3065E/ADM3066E can withstand up to
12 ꢀV contact discharge on transceiver bus pins (A and B)
without latch-up or damage. The ADM3061E/ADM3062E has
the same robust IEC 61000-4-2 ESD protection as the ADM3065E/
ADM3066E models and operate at a lower 500 ꢀbps data rate.
16A
I
I
30ns
60ns
8A
HIGH DRIVER DIFFERENTIAL OUTPUT VOLTAGE
10%
The ADM3061E/ADM3062E/ADM3065E/ADM3066E have
characteristics optimized for use in Profibus applications. When
powered at VCC ≥ 4.5 V, the ADM3061E/ADM3062E/ADM3065E/
ADM3066E driver output differential voltage meets or exceeds the
Profibus requirements of 2.1 V with a 54 Ω load.
TIME
60ns
30ns
tR = 0.7ns TO 1ns
Figure 41. IEC 61000-4-2 ESD Waveform (8 kV)
Figure 42 shows the 8 ꢀV contact discharge current waveform
from the IEC 61000-4-2 standard compared to the HBM ESD
8 ꢀV waveform. Figure 42 shows that the two standards specify a
different waveform shape and peaꢀ current. The peaꢀ current
associated with an IEC 61000-4-2 8 ꢀV pulse is 30 A, whereas
the corresponding peaꢀ current for HBM ESD is more than five
times less, at 5.33 A. The other difference is the rise time of the
initial voltage spiꢀe, with the IEC 61000-4-2 ESD waveform having
a much faster rise time of 1 ns, compared to the 10 ns associated
with the HBM ESD waveform. The amount of power associated
with an IEC ESD waveform is much greater than that of an
HBM ESD waveform. The HBM ESD standard requires the
EUT to be subjected to three positive and three negative
discharges, while in comparison, the IEC ESD standard requires
10 positive and 10 negative discharge tests.
IEC 61000-4-2 ESD PROTECTION
ESD is the sudden transfer of electrostatic charge between
bodies at different potentials caused by near contact or induced
by an electric field. It has the characteristics of high current in a
short time period. The primary purpose of the IEC 61000-4-2
test is to determine the immunity of systems to external ESD
events outside the system during operation. IEC 61000-4-2
describes testing using two coupling methods: contact discharge
and air discharge. Contact discharge implies a direct contact
between the discharge gun and the equipment under test (EUT).
During air discharge testing, the charged electrode of the
discharge gun is moved toward the EUT until a discharge
occurs as an arc across the air gap. The discharge gun does not
maꢀe direct contact with the EUT. A number of factors affect
the results and repeatability of the air discharge test, including
humidity, temperature, barometric pressure, distance, and rate
of approach to the EUT. This method is a better representation
of an actual ESD event but is not as repeatable. Therefore,
contact discharge is the preferred test method.
The ADM3061E/ADM3062E/ADM3065E/ADM3066E with IEC
61000-4-2 ESD ratings is better suited for operation in harsh
environments compared to other RS-485 transceivers that state
varying levels of HBM ESD protection.
I
PEAK
During testing, the data port is subjected to at least 10 positive
and 10 negative single discharges. Selection of the test voltage is
dependent on the system end environment.
30A
90%
Figure 41 shows the 8 ꢀV contact discharge current waveform
as described in the IEC 61000-4-2 specification. Some of the
ꢀey waveform parameters are rise times of less than 1 ns and
pulse widths of approximately 60 ns.
IEC 61000-4-2 ESD 8kV
16A
8A
I
I
30ns
60ns
5.33A
HBM ESD 8kV
10%
TIME
60ns
10ns
tR = 0.7ns TO 1ns
30ns
Figure 42. IEC 61000-4-2 ESD Waveform 8 kV Compared to HBM ESD
Waveform 8 kV
Rev. C | Page 17 of 25
ADM3061E/ADM3062E/ADM3065E/ADM3066E
Data Sheet
TRUTH TABLES
RECEIVER FAIL-SAFE
The ADM3061E/ADM3062E/ADM3065E/ADM3066E guarantee
a logic high receiver output when the receiver inputs are
shorted, open, or connected to a terminated transmission line
with all drivers disabled; set the receiver input threshold
between −30 mV and −200 mV. If the differential receiver input
voltage (A − B) is greater than or equal to −30 m V, the RO pin
is logic high.
Table 9. Transmitting Truth Table
Supply Status
Inputs
Outputs
4
RE
VIO
VCC
On
On
On
On
Off
Off
Off
On
Off
DE
1
1
0
0
1
1
0
X1
X1
DI
1
0
X1
X1
1
A
B
0
1
On
On
On
On
On
On
On
Off
Off
X1
X1
0
1
0
High-Z2
High-Z2
I3
I3
I3
High-Z2
High-Z2
High-Z2
1
High-Z2
If the A − B input is less than or equal to −200 mV, RO is logic
low. In the case of a terminated bus with all transmitters
disabled, the receiver differential input voltage is pulled to 0 V
by the termination, resulting in a logic high with a 30 mV
minimum noise margin.
X1
X1
X1
X1
X1
I3
0
I3
X1
X1
X1
I3
High-Z2
High-Z2
1 X means don't care.
2 High-Z means high impedance.
3 I means indeterminate.
4 For the ADM3061E and ADM3065E, the VIO pin is not applicable.
Table 10. Receiving Truth Table
Supply Status
Inputs
Outputs
DE RO
4
RE
VIO
On
On
Off
Off
VCC
On
On
On
On
A − B
>−0.03 V
<−0.2 V
>−0.03 V
<−0.2 V
0
0
0
0
X1
X1
X1
X1
1
0
I3
I3
−0.2 V ≤ A – B ≤
−0.03 V
On
On
0
X1
I3
−0.2 V ≤ A – B ≤
−0.03 V
Inputs open/shorted
Off
On
Off
On
On
Off
Off
On
On
On
On
On
On
Off
0
0
0
1
1
1
X1
X1
X1
X1
0
I3
1
Inputs open/shorted
High-Z2
High-Z2
Shutdown
I3
X1
X1
X1
X1
X1
X1 X1
High-Z2
1 X means don't care.
2 High-Z means high impedance.
3 I means indeterminate.
4 For the ADM3061E and ADM3065E, the VIO pin is not applicable.
Rev. C | Page 18 of 25
ADM3061E/ADM3062E/ADM3065E/ADM3066E
Data Sheet
HOT SWAP CAPABILITY
DRIVER OUTPUT PROTECTION
Hot Swap Inputs
The ADM3061E/ADM3062E/ADM3065E/ADM3066E features
two methods to prevent excessive output current and power
dissipation caused by faults or by bus contention. Current-limit
protection on the output stage provides immediate protection
against short circuits over the whole common-mode voltage range.
In addition, a thermal shutdown circuit forces the driver outputs
into a high impedance state if the die temperature rises excessively.
This circuitry is designed to disable the driver outputs when a die
temperature of 150°C is reached. As the device cools, the drivers are
reenabled at a temperature of 140°C.
When a circuit board is inserted into a powered (or hot)
backplane, differential disturbances to the data bus can lead to
data errors. During this period, processor logic output drivers
RE
are high impedance and are unable to drive the DE and
inputs
of the RS-485 transceivers to a defined logic level. Leakage currents
up to 10 µA from the high impedance state of the processor logic
drivers can cause standard CMOS enable inputs of a transceiver to
drift to an incorrect logic level. Additionally, parasitic circuit board
capacitance can cause coupling of VCC or GND to the enable inputs.
Without the hot swap capability, these factors can improperly
enable the driver or receiver of the transceiver. When VCC or VIO
RE
rises, an internal pull-down circuit holds DE low and
high.
After the initial power-up sequence, the pull-down circuit
becomes transparent resetting the hot swap tolerable input.
128 TRANSCEIVERS ON THE BUS
The standard RS-485 receiver input impedance is 12 kΩ
(1 unit load), and the standard driver can drive up to 32 unit
loads. The ADM3061E/ADM3062E/ADM3065E/ADM3066E
transceivers have a ¼ unit load receiver input impedance (48
kΩ), allowing up to 128 transceivers to be connected in parallel
on one communication line. Any combination of these devices
and other RS-485 transceivers with a total of 32 unit loads or
fewer can be connected to the line.
Rev. C | Page 19 of 25
ADM3061E/ADM3062E/ADM3065E/ADM3066E
Data Sheet
APPLICATIONS INFORMATION
The ADM3061E/ADM3065E transceiver is designed for
bidirectional data communications on multipoint bus transmission
lines. Figure 43 shows a typical network applications circuit.
To minimize reflections, terminate the line at both ends with a
termination resistor (the value of the termination resistor must
be equal to the characteristic impedance of the cable used) and
keep stub lengths off the main line as short as possible.
V
V
CC
CC
ADM3061E/
ADM3065E
ADM3061E/
ADM3065E
R
R
RO
RE
RO
RE
A
A
R
R
T
T
DE
DI
DE
DI
B
B
D
D
GND
GND
V
V
CC
CC
ADM3061E/
ADM3065E
ADM3061E/
ADM3065E
R
R
RO
RE
RO
RE
A
B
A
B
DE
DI
DE
DI
D
D
GND
GND
NOTES
1. THE MAXIMUM NUMBER OF NODES IS 128.
2. R IS EQUAL TO THE CHARACTERISTIC IMPEDANCE OF THE CABLE USED.
T
Figure 43. ADM3061E/ADM3065E Typical Half-Duplex RS-485 Communications Network
Rev. C | Page 20 of 25
Data Sheet
ADM3061E/ADM3062E/ADM3065E/ADM3066E
If 5 V operation is desired, VSEL on ADuM6000 can be tied to
ISOLATED HIGH SPEED RS-485 NODE
VISO, and the maximum supported data rate becomes lower (for
Galvanic isolation, with reinforced insulation and 5 kV rms
transient withstand voltage, can be added to the ADM3065E using
Analog Devices, Inc., iCoupler® and isoPower® technology. The
ADuM6401 provides the required quad channels of 5 kV rms
signal isolation, operating at rates up to 25 Mbps, together with
an integrated dc-to-dc converter. The ADuM6401 combines
with the ADM3065E (shown in Figure 44) with the VISO pin
configured for 3.3 V by connecting the VSEL pin to GNDISO and
a 5 V supply connected to VDD1. Operation at 3.3 V ensures the
ADM3065E remains within the load capability of ADuM6401
even at 25 Mbps.
example, <10 Mbps). Refer to the Typical Performance
Characteristics section, ADuM241D data sheet, and the
ADuM6000 data sheet.
The dc-to-dc converters in the ADuM6401 and ADuM6000
isoPower devices provide regulated, isolated power to the
ADM3065E (and the ADuM241D). These isoPower devices use
high frequency switching elements to transfer power through
their transformers. Take care during PCB layout to meet
emissions standards. See the AN-0971 Application Note for
PCB layout recommendations.
Operation at 50 Mbps data rates with isolation of the ADM3065E
can be implemented using the ADuM241D quad-channel digital
isolator and the ADuM6000 isolated dc-to-dc converter, as shown
in Figure 45. The ADuM241D can operate at a data rate of up to
150 Mbps, offering the precise timing required to fully support the
ADM3065E at 50 Mbps. Operation of ADM3065E at 3.3 V allows
operation at the 50 Mbps data rate.
V
CC
5V
10nF
0.1µF
ADM3065E
V
V
ISO
DD1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
0.1µF
GND
GND
1
ISO
RO
RE
R
V
FERRITE
BEAD
OA
V
IA
IB
IC
A
B
V
OB
V
V
4-CHANNEL iCOUPLER CORE
V
V
ADuM6401
OC
DE
DI
5V
ID
V
OD
D
V
V
SEL
DDL
0.1µF
GND
GND
ISO
1
GND
Figure 44. Signal and Power Isolated 25 Mbps RS-485 Solution (Simplified Diagram—All Connections Not Shown)
Rev. C | Page 21 of 25
ADM3061E/ADM3062E/ADM3065E/ADM3066E
Data Sheet
+5V
V
FERRITE BEAD
V
ISO
DD1
OSC
RECT REG
0.1µF
10nF 0.1µF
GND
ISO
GND
1
FERRITE BEAD
NC
NC
RC
IN
V
SEL
RC
NC
OUT
RC
SEL
NC
+5V
FERRITE BEAD
V
ISO
0.1µF
10nF
10nF
GND
ISO
GND
1
ADuM6000
FERRITE BEAD
+5V
V
CC
V
V
DD2
DD1
0.1µF
ADuM241D
GND
V
GND
1
2
0.1µF
RO
R
V
OA
IA
IB
IC
ENCODE
ENCODE
ENCODE
DECODE
DECODE
A
B
V
V
V
OB
RE
DE
DECODE
DECODE
ENCODE
V
V
OC
V
ID
OD
D
DISABLE /VE
1
DISABLE /VE
2 2
GND
DI
1
1
GND
2
ADM3065E
GND
Figure 45. Signal and Power Isolated 50 Mbps RS-485 Solution (Simplified Diagram—All Connections Not Shown)
Rev. C | Page 22 of 25
Data Sheet
ADM3061E/ADM3062E/ADM3065E/ADM3066E
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 46. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.15
0.05
0.23
0.09
6°
0°
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 47. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Rev. C | Page 23 of 25
ADM3061E/ADM3062E/ADM3065E/ADM3066E
Data Sheet
3.10
3.00
2.90
10
1
6
5
5.15
4.90
4.65
3.10
3.00
2.90
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.70
0.55
0.40
0.15
0.05
0.23
0.13
6°
0°
0.30
0.15
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 48. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
DETAIL A
(JEDEC 95)
2.48
2.38
2.23
3.10
3.00 SQ
0.50 BSC
2.90
10
6
PIN 1 INDEX
AREA
EXPOSED
PAD
1.74
1.64
1.49
0.50
0.40
0.30
0.20 MIN
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
1
5
BOTTOM VIEW
TOP VIEW
SIDE VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.25
0.20
0.20 REF
Figure 49. 10-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-10-9)
Dimensions shown in millimeters
Rev. C | Page 24 of 25
Data Sheet
ADM3061E/ADM3062E/ADM3065E/ADM3066E
ORDERING GUIDE
Model1
ADM3061EARZ
ADM3061EARZ-R7
ADM3061EBRZ
ADM3061EBRZ-R7
ADM3061EARMZ
ADM3061EARMZ-R7
ADM3061EBRMZ
ADM3061EBRMZ-R7
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
R-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
RM-8
ADM3062EACPZ
ADM3062EACPZ-R7
ADM3062EBCPZ
ADM3062EBCPZ-R7
ADM3062EARMZ
ADM3062EARMZ-R7
ADM3062EBRMZ
ADM3062EBRMZ-R7
ADM3065EARZ
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
10-Lead Lead Frame Chip Scale Package [LFCSP]
10-Lead Lead Frame Chip Scale Package [LFCSP]
10-Lead Lead Frame Chip Scale Package [LFCSP]
10-Lead Lead Frame Chip Scale Package [LFCSP]
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
CP-10-9
CP-10-9
CP-10-9
CP-10-9
RM-10
RM-10
RM-10
RM-10
R-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
RM-8
ADM3065EARZ-R7
ADM3065EBRZ
ADM3065EBRZ-R7
ADM3065EARMZ
ADM3065EARMZ-R7
ADM3065EBRMZ
ADM3065EBRMZ-R7
ADM3066EACPZ
ADM3066EACPZ-R7
ADM3066EBCPZ
ADM3066EBCPZ-R7
ADM3066EARMZ
ADM3066EARMZ-R7
ADM3066EBRMZ
ADM3066EBRMZ-R7
EVAL-ADM3061EEBZ
EVAL-ADM3061EEB1Z
EVAL-ADM3062EEBZ
EVAL-ADM3062EEB1Z
EVAL-ADM3065EEBZ
EVAL-ADM3065EEB1Z
EVAL-ADM3066EEBZ
EVAL-ADM3066EEB1Z
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
10-Lead Lead Frame Chip Scale Package [LFCSP]
10-Lead Lead Frame Chip Scale Package [LFCSP]
10-Lead Lead Frame Chip Scale Package [LFCSP]
10-Lead Lead Frame Chip Scale Package [LFCSP]
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
8-Lead SOIC Evaluation Board
8-Lead MSOP Evaluation Board
10-Lead MSOP Evaluation Board
10-Lead LFCSP Evaluation Board
8-Lead SOIC Evaluation Board
CP-10-9
CP-10-9
CP-10-9
CP-10-9
RM-10
RM-10
RM-10
RM-10
8-Lead MSOP Evaluation Board
10-Lead MSOP Evaluation Board
10-Lead LFCSP Evaluation Board
1 Z = RoHS Compliant Part.
©2017–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14666-0-2/18(C)
Rev. C | Page 25 of 25
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