ADM4168EBRUZ-RL7 [ADI]

15 kV ESD Protected Dual RS-422 Transceiver; 15千伏ESD保护的双路RS-422收发器
ADM4168EBRUZ-RL7
型号: ADM4168EBRUZ-RL7
厂家: ADI    ADI
描述:

15 kV ESD Protected Dual RS-422 Transceiver
15千伏ESD保护的双路RS-422收发器

文件: 总12页 (文件大小:290K)
中文:  中文翻译
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15 kV ESD Protected  
Dual RS-422 Transceiver  
Data Sheet  
ADM4168E  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
V
CC  
Dual transceivers for RS-422  
ESD protection on bus input/output pins  
15 kV human body model (HBM)  
8 kV IEC 61000-4-2, contact discharge  
8 kV IEC 61000-4-2, air discharge  
Complies with TIA/EIA-422-B and ITU-T recommendation V.11  
Open-circuit fail-safe  
Suitable for 5 V power supply applications  
Low supply current operation: 9 mA maximum  
Low driver output skew  
ADM4168E  
DI1  
Y1  
Z1  
B1  
A1  
R1  
D1  
RO1  
DE1  
DE2  
Z2  
RO2  
A2  
Receiver input impedance: 30 kΩ  
R2  
D2  
B2  
Y2  
Receiver common-mode range: −7 V to +7 V  
Power-up/power-down without glitches  
16-pin TSSOP package  
DI2  
GND  
Operating temperature range: −40°C to +85°C  
Figure 1.  
APPLICATIONS  
RS-422 interfaces  
High data rate motor control  
Single-ended-to-differential signal conversion  
Point-to-point and multidrop transmission systems  
GENERAL DESCRIPTION  
The ADM4168E has dual RS-422 transceivers suitable for  
high speed communication on point-to-point and multidrop  
transmission lines. The ADM4168E is designed for balanced  
transmission lines and complies with TIA/EIA-422-B.  
The receivers of the ADM4168E contain a fail-safe feature that  
results in a logic high output state if the inputs are unconnected  
(floating).  
The ADM4168E is fully specified over the commercial and  
industrial temperature ranges and is available in a 16-pin  
TSSOP package.  
The differential driver outputs and receiver inputs feature electro-  
static discharge circuitry that provides protection up to 15 kV  
HBM and 8 kV IEC 61000-4-2 (contact and air discharge).  
The ADM4168E operates from a single 5 V power supply.  
Excessive power dissipation caused by bus contention or output  
shorting is prevented by short-circuit protection circuitry. Short-  
circuit protection circuits limit the maximum output current to  
150 mA during fault conditions.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rightsof third parties that may result fromits use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks andregisteredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2012 Analog Devices, Inc. All rights reserved.  
 
 
 
 
ADM4168E  
Data Sheet  
TABLE OF CONTENTS  
Features .............................................................................................. 1  
Pin Configuration and Function Descriptions..............................6  
Typical Performance Characteristics ..............................................7  
Test Circuits and Switching Characteristics...................................9  
Driver Measurements ...................................................................9  
Receiver Measurements................................................................9  
Theory of Operation ...................................................................... 10  
Truth Tables................................................................................. 10  
Outline Dimensions....................................................................... 11  
Ordering Guide .......................................................................... 11  
Applications....................................................................................... 1  
Functional Block Diagram .............................................................. 1  
General Description ......................................................................... 1  
Revision History ............................................................................... 2  
Specifications..................................................................................... 3  
Timing Specifications .................................................................. 4  
Absolute Maximum Ratings............................................................ 5  
Thermal Resistance ...................................................................... 5  
ESD Caution.................................................................................. 5  
REVISION HISTORY  
9/12—Revision 0: Initial Version  
Rev. 0 | Page 2 of 12  
 
Data Sheet  
ADM4168E  
SPECIFICATIONS  
4.5 V ≤ VCC ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted.  
All typical specifications are at TA = 25°C, VCC = 5.0 V, unless otherwise noted.  
Table 1.  
Parameter  
Symbol Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
No load, drivers enabled  
VI = VCC or GND  
SUPPLY CURRENT  
Total Package  
ICC  
4
5
6
9
mA  
mA  
VI = 2.4 V or 0.5 V1  
DRIVER  
Differential Outputs (Y1, Z1, Y2, Z2 Pins)  
Input Clamp Voltage  
Output Voltage High  
Output Voltage Low  
Differential Output Voltage  
No Load  
VIK  
VOH  
VOL  
−1.5  
0.4  
V
V
V
II = −18 mA  
VIH = 2 V, VIL = 0.8 V, IOH = −20 mA  
VIH = 2 V, VIL = 0.8 V, IOL = 20 mA  
2.4  
3.5  
0.2  
|VOD1  
|VOD2  
|
|
2.0  
2.0  
6.0  
V
V
V
V
IO = 0 mA  
Outputs Loaded2  
3.7  
RL = 100 Ω (see Figure 11)  
RL = 100 Ω (see Figure 11)  
RL = 100 Ω (see Figure 11)  
RL = 100 Ω (see Figure 11)  
DE = 0 V, VCC = 0 V or 5 V, VO = 6 V  
DE = 0 V, VCC = 0 V or 5 V, VO = −0.25 V  
VO = VCC or GND  
Δ|VOD| for Complementary Output States ∆|VOD|  
Common-Mode Output Voltage VOC  
Δ|VOC| for Complementary Output States Δ|VOC|  
0.4  
3.0  
0.4  
V
Output Leakage Current  
IO  
100  
µA  
µA  
mA  
pF  
−100  
−30  
Output Current (Short Circuit)3  
Input Capacitance  
IOS  
CI  
−150  
6
Logic Inputs (DI, DE Pins)  
Input Voltage High  
Input Voltage Low  
Input Current High  
Input Current Low  
VIH  
VIL  
IIH  
2.0  
V
V
µA  
µA  
0.8  
1
−1  
VI = VCC or VIH  
VI = GND or VIL  
IIL  
RECEIVER  
Differential Inputs (A1, B1, A2, B2 Pins)  
Differential Input Threshold Voltage2  
Input Voltage Hysteresis  
VTH  
VHYS  
II  
−200  
+200  
mV  
mV  
mA  
mA  
kΩ  
60  
30  
Input Current  
1.5  
−2.5  
VI = 7 V, other input at 0 V  
VI = −7 V, other input at 0 V  
VIC = −7 V to +7 V, other input at 0 V  
Line Input Resistance  
Logic Outputs (RO1, RO2 Pins)  
Output Voltage High  
RIN  
12  
VOH  
VOL  
3.8  
4.2  
0.1  
V
V
VID = 200 mV, IOH = −6 mA  
VID = −200 mV, IOL = 6 mA  
Output Voltage Low  
0.3  
1 Measured per input with other inputs at VCC or GND.  
2 For exact conditions, see TIA/EIA-422-B.  
3 No more than one output shorted at any time, with the duration of the short not to exceed 1 second.  
Rev. 0 | Page 3 of 12  
 
 
ADM4168E  
Data Sheet  
TIMING SPECIFICATIONS  
4.5 V ≤ VCC ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted.  
All typical specifications are at TA = 25°C, VCC = 5.0 V, unless otherwise noted.  
Table 2.  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
DRIVER  
R1, R2 = 50 Ω; R3 = 500 Ω; C1, C2, C3 = 40 pF  
S1 open (see Figure 12 and Figure 13)  
S1 open (see Figure 12 and Figure 13)  
S1 open (see Figure 12 and Figure 13)  
S1 closed (see Figure 13 and Figure 14)  
S1 closed (see Figure 13 and Figure 14)  
Propagation Delay  
Driver Output Skew  
Rise Time/Fall Time  
Enable Time  
Disable Time  
RECEIVER1  
tDPLH, tDPHL  
tSK  
tDR, tDF  
tZH, tZL  
tHZ, tLZ  
8
1.5  
5
10  
7
16  
4
10  
19  
16  
ns  
ns  
ns  
ns  
ns  
Propagation Delay  
Transition Time  
tRPLH, tRPHL  
tTLH, tTHL  
9
15  
4
27  
9
ns  
ns  
CL = 50 pF (see Figure 15 and Figure 16)  
VIC = 0 V, CL = 50 pF (see Figure 15 and Figure 16)  
1 Measured per input with other inputs at VCC or GND.  
Rev. 0 | Page 4 of 12  
 
 
Data Sheet  
ADM4168E  
ABSOLUTE MAXIMUM RATINGS  
THERMAL RESISTANCE  
Table 3.  
θJA is specified for the worst-case conditions, that is, a device  
soldered in a circuit board for surface-mount packages.  
Parameter  
Rating  
VCC  
−0.3 V to +7 V  
−0.3 V to +7 V  
−0.3 V to +7 V  
−0.3 V to VCC + 0.3 V  
−0.3 V to +7 V  
−14 V to +14 V  
−40°C to +85°C  
−65°C to +150°C  
Digital Input Voltage (DE1, DE2)  
Driver Input Voltage (DI1, DI2)  
Receiver Output Voltage (RO1, RO2)  
Driver Output Voltage (Y1, Z1, Y2, Z2)  
Receiver Input Voltage (A1, B1, A2, B2)  
Operating Temperature Range  
Storage Temperature Range  
ESD Protection on Ax, Bx, Yx, and Zx  
Human Body Model (HBM)  
IEC 61000-4-2, Contact Discharge  
IEC 61000-4-2, Air Discharge  
Table 4. Thermal Resistance  
Package Type  
θJA  
Unit  
16-Lead TSSOP  
113  
°C/W  
ESD CAUTION  
15 kV  
8 kV  
8 kV  
Stresses above those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. This is a stress  
rating only; functional operation of the device at these or any  
other conditions above those indicated in the operational  
section of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
device reliability.  
Rev. 0 | Page 5 of 12  
 
 
 
ADM4168E  
Data Sheet  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
1
2
3
4
5
6
7
8
16  
15  
14  
V
CC  
B1  
A1  
DI1  
Y1  
RO1  
DE1  
RO2  
A2  
ADM4168E 13  
Z1  
TOP VIEW  
12  
DE2  
Z2  
(Not to Scale)  
11  
10  
9
Y2  
B2  
DI2  
GND  
Figure 2. Pin Configuration  
Table 5. Pin Function Descriptions  
Pin No.  
Mnemonic  
Description  
1
2
3
4
B1  
A1  
RO1  
DE1  
Inverting Receiver Input B, Transceiver 1.  
Noninverting Receiver Input A, Transceiver 1.  
Receiver Output, Transceiver 1.  
Driver Output Enable, Transceiver 1. A logic high enables the differential driver outputs, Y1 and Z1; a logic low  
places the differential driver outputs in a high impedance state.  
5
6
7
8
9
RO2  
A2  
B2  
GND  
DI2  
Receiver Output, Transceiver 2.  
Noninverting Receiver Input A, Transceiver 2.  
Inverting Receiver Input B, Transceiver 2.  
Ground.  
Driver Input, Transceiver 2. When the driver is enabled, a logic low on DI2 forces Y2 low and Z2 high, whereas  
a logic high on DI2 forces Y2 high and Z2 low.  
10  
11  
12  
Y2  
Z2  
DE2  
Noninverting Driver Output Y, Transceiver 2.  
Inverting Driver Output Z, Transceiver 2.  
Driver Output Enable, Transceiver 2. A logic high enables the differential driver outputs, Y2 and Z2; a logic low  
places the differential driver outputs in a high impedance state.  
13  
14  
15  
Z1  
Y1  
DI1  
Inverting Driver Output Z, Transceiver 1.  
Noninverting Driver Output Y, Transceiver 1.  
Driver Input, Transceiver 1. When the driver is enabled, a logic low on DI1 forces Y1 low and Z1 high, whereas  
a logic high on DI1 forces Y1 high and Z1 low.  
16  
VCC  
Power Supply (5 V 10%).  
Rev. 0 | Page 6 of 12  
 
Data Sheet  
ADM4168E  
TYPICAL PERFORMANCE CHARACTERISTICS  
120  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
100Ω LOAD  
100Ω LOAD  
UNLOADED  
100  
UNLOADED  
80  
60  
40  
20  
0
–40  
–20  
0
20  
40  
60  
80  
1
2
3
4
5
6
7
8
9
10  
TEMPERATURE (°C)  
DATA RATE (Mbps)  
Figure 3. Supply Current vs. Temperature, Data Rate = 10 Mbps  
Figure 6. Supply Current vs. Data Rate  
4.3  
4.1  
3.9  
3.7  
3.5  
3.3  
3.1  
2.9  
2.7  
2.5  
4.0  
TRANSCEIVER 1  
TRANSCEIVER 1  
TRANSCEIVER 2  
TRANSCEIVER 2  
3.9  
3.8  
3.7  
3.6  
3.5  
3.4  
3.3  
3.2  
3.1  
3.0  
4.5  
4.6  
4.7  
4.8  
4.9  
5.0  
5.1  
CC  
5.2  
5.3  
5.4  
5.5  
–40  
–20  
0
20  
40  
60  
80  
SUPPLY VOLTAGE, V (V)  
TEMPERATURE (°C)  
Figure 7. Driver Differential Output Voltage vs. Supply Voltage  
Figure 4. Driver Differential Output Voltage vs. Temperature  
500  
6
TRANSCEIVER 1  
TRANSCEIVER 2  
TRANSCEIVER 1  
TRANSCEIVER 2  
450  
5
400  
350  
300  
250  
200  
150  
100  
50  
4
3
2
1
0
0
–40  
–20  
0
20  
40  
60  
80  
–40  
–20  
0
20  
40  
60  
80  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
Figure 8. Receiver Output Voltage Low vs. Temperature  
Figure 5. Receiver Output Voltage High vs. Temperature  
Rev. 0 | Page 7 of 12  
 
ADM4168E  
Data Sheet  
DI  
A
1
B
2
4
RO  
Y
Z
3
CH2 2V  
CH4 2V  
CH3 2V  
M100ns  
A CH2  
2.28V  
CH1 2V  
CH3 2V  
CH2 2V  
M100ns  
A CH1  
2.48V  
Figure 9. Driver Output  
Figure 10. Receiver Output  
Rev. 0 | Page 8 of 12  
Data Sheet  
ADM4168E  
TEST CIRCUITS AND SWITCHING CHARACTERISTICS  
DRIVER MEASUREMENTS  
Y
R
Y
Z
Y
L
C
2
R
1
R
2
3
DI  
V
OD  
DI  
V
C
1
1.5V  
OD2  
S1  
R
L
R
2
Z
2
DE  
V
OC  
Z
C
3
NOTES  
1. C , C , C INCLUDE PROBE/INSTRUMENT CAPACITANCE.  
1
2
3
Figure 11. Driver Voltage Measurements  
Figure 13. Driver Timing Circuit  
5V  
5V  
DE  
INPUT  
1.3V  
tZL  
1.3V  
1.3V  
1.3V  
0V  
0V  
tDPLH  
tDPHL  
tLZ  
1.5V  
V
OH  
0.8V  
V
+ 0.3V  
OL  
OUT  
50%  
50%  
1.3V  
Y
1.3V  
V
V
OL  
OH  
V
V
OL  
tZH  
tHZ  
tSK  
tSK  
OUT  
OH  
2V  
V
– 0.3V  
OH  
50%  
1.3V  
Z
50%  
1.3V  
1.5V  
NOTES  
V
OL  
1. INPUT PULSE GENERATOR: PPR 1MHz; 50% DUTY CYCLE; tR  
,
tF ≤ 6ns.  
tDPHL  
tDPLH  
Figure 14. Driver Enable/Disable Timing  
+V  
O
90% POINT  
90% POINT  
V
OD  
10% POINT  
10% POINT  
–V  
O
tDR  
tDF  
NOTES  
1. INPUT PULSE GENERATOR: PPR 1MHz; 50% DUTY CYCLE; tR  
,
tF ≤ 6ns.  
Figure 12. Driver Propagation Delay and Rise/Fall Timing  
RECEIVER MEASUREMENTS  
A
2.5V  
V
B
O
0V  
0V  
B
(A = 0V)  
C
L
–2.5V  
NOTES  
tRPLH  
tRPHL  
1. C INCLUDES PROBE/INSTRUMENT CAPACITANCE.  
L
V
OH  
Figure 16. Receiver Timing Circuit  
90%  
90%  
RO  
50%  
50%  
10%  
10%  
V
OL  
tTLH  
tTHL  
NOTES  
1. INPUT PULSE GENERATOR: PPR 1MHz; 50% DUTY CYCLE; tR  
,
tF ≤ 6ns.  
Figure 15. Receiver Propagation Delay and Transition Timing  
Rev. 0 | Page 9 of 12  
 
 
 
 
 
 
 
 
 
ADM4168E  
Data Sheet  
THEORY OF OPERATION  
The ADM4168E is a dual RS-422 transceiver that operates from  
a single 5 V 10% power supply. The ADM4168E is intended for  
balanced data transmission and complies with TIA/EIA-422-B  
and ITU-T recommendation V.11. Each device contains two  
differential line drivers and two differential line receivers and  
is suitable for full-duplex data transmission.  
Table 7. Transmitting (Each Driver)  
Inputs  
Outputs  
DE  
H
H
DI  
H
L
Z
L
H
Z
Y
H
L
L
X
Z
The receivers contain a fail-safe feature that results in a logic  
high output state if the inputs are unconnected (floating).  
Table 8. Receiving (Each Receiver)  
The ADM4168E features a low propagation delay, ensuring  
maximum baud rate operation. The balanced driver ensures  
distortion-free transmission.  
Inputs  
Output  
A − B  
RO  
H
L
≥ +0.2 V  
≤ −0.2 V  
Another important specification is a measure of the skew  
between the complementary outputs. Low skew enhances  
the noise immunity of the system and decreases the amount  
of electromagnetic interference (EMI).  
−0.2 V < A − B < +0.2 V  
Inputs open  
I
H
TRUTH TABLES  
Table 6. Abbreviations in Truth Tables  
Letter  
Description  
H
I
L
X
Z
High level  
Indeterminate  
Low level  
Irrelevant  
High impedance (off)  
Rev. 0 | Page 10 of 12  
 
 
Data Sheet  
ADM4168E  
OUTLINE DIMENSIONS  
5.10  
5.00  
4.90  
16  
9
8
4.50  
4.40  
4.30  
6.40  
BSC  
1
PIN 1  
1.20  
MAX  
0.15  
0.05  
0.20  
0.09  
0.75  
0.60  
0.45  
8°  
0°  
0.30  
0.19  
0.65  
BSC  
SEATING  
PLANE  
COPLANARITY  
0.10  
COMPLIANT TO JEDEC STANDARDS MO-153-AB  
Figure 17. 16-Lead Thin Shrink Small Outline Package [TSSOP]  
(RU-16)  
Dimensions shown in millimeters  
ORDERING GUIDE  
Model1  
Temperature Range  
−40°C to +85°C  
−40°C to +85°C  
Package Description  
Package Option  
ADM4168EBRUZ  
ADM4168EBRUZ-RL7  
EVAL-ADM4168EEBZ  
16-Lead Thin Shrink Small Outline Package [TSSOP]  
16-Lead Thin Shrink Small Outline Package [TSSOP]  
Evaluation Board  
RU-16  
RU-16  
1 Z = RoHS Compliant Part.  
Rev. 0 | Page 11 of 12  
 
 
ADM4168E  
NOTES  
Data Sheet  
©2012 Analog Devices, Inc. All rights reserved. Trademarks and  
registered trademarks are the property of their respective owners.  
D10820-0-9/12(0)  
Rev. 0 | Page 12 of 12  

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