ADM6821WYRJZ-RL7 [ADI]
1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO5, LEAD FREE, SOT-23, 5 PIN;
| 型号： | ADM6821WYRJZ-RL7 |
| 厂家： | 
ADI |
| 描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO5, LEAD FREE, SOT-23, 5 PIN 输入元件 光电二极管 |
| 文件： | 总12页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Voltage Supervisory Circuits with
Watchdog and Manual Reset in 5-Lead SOT-23
ADM6821/ADM6822/ADM6823/ADM6824/ADM6825
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Precision low voltage monitoring
9 reset threshold options: 1.58 V to 4.63 V
140 ms (min) reset timeout
Watchdog timer with 1.6 sec timeout
Manual reset input
ADM6823
V
CC
V
CC
RESET
GENERATOR
RESET
V
REF
Reset output stages
DEBOUNCE
MR
Push-pull active-low
WATCHDOG
DETECTOR
Open-drain active-low
Push-pull active-high
Low power consumption (7 μA)
Guaranteed reset output valid to VCC = 1 V
Power supply glitch immunity
Specified from −40°C to +125°C
5-lead SOT-23 package
GND
WDI
Figure 1.
APPLICATIONS
Microprocessor systems
Computers
Controllers
Intelligent instruments
Portable equipment
GENERAL DESCRIPTION
The ADM682x are supervisory circuits that monitor power
supply voltage levels and code execution integrity in
Each part is available in nine reset threshold options, ranging
from 1.58 V to 4.63 V. The reset and watchdog timeout periods
are fixed at 140 ms (min) and 1.6 sec (typ), respectively.
microprocessor-based systems. As well as providing power-on
reset signals, an on-chip watchdog timer can reset the
microprocessor if it fails to strobe within a preset timeout
period. A reset signal can also be asserted by means of an
external push-button through a manual reset input. The parts
feature different combinations of watchdog input and manual
reset input and output stage configurations, as shown in Table 1.
The ADM682x are available in 5-lead SOT-23 packages and
typically consume only 7 μA, making them suitable for use in
low power, portable applications.
Table 1. Selection Table
Output Stage
RESET
Part No.
Watchdog Timer
Manual Reset
RESET
Push-Pull
-
ADM6821
ADM6822
ADM6823
ADM6824
ADM6825
Yes
Yes
Yes
Yes
-
Yes
Yes
Yes
-
-
Open-Drain
Push-Pull
Push-Pull
Push-Pull
-
Push-Pull
Push-Pull
Yes
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
ADM6821/ADM6822/ADM6823/ADM6824/ADM6825
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Circuit Description........................................................................... 9
Reset Output ................................................................................. 9
Manual Reset Input ...................................................................... 9
Watchdog Input .............................................................................9
Application Information................................................................ 10
Watchdog Input Current ........................................................... 10
Negative-Going VCC Transients ................................................ 10
Ensuring Reset Valid to VCC = 0 V........................................... 10
Watchdog Software Considerations......................................... 10
Outline Dimensions....................................................................... 11
Ordering Guide .......................................................................... 11
REVISION HISTORY
6/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 12
ADM6821/ADM6822/ADM6823/ADM6824/ADM6825
SPECIFICATIONS
VCC = 4.5 V to 5.5 V for ADM682_L/M; VCC = 2.7 V to 3.6 V for ADM682_T/S/R; VCC = 2.1 V to 2.75 V for ADM682_Z/Y; VCC = 1.53 V
to 2.0 V for ADM682_W/V; TA = –40°C to +125°C, unless otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SUPPLY
VCC Operating Voltage Range
Supply Current
1
5.5
20
16
V
μA
μA
10
7
WDI and MR unconnected, VCC = 5.5 V
WDI and MR unconnected, VCC = 3.6 V
RESET THRESHOLD VOLTAGE
ADM682xL
ADM682xM
ADM682xT
ADM682xS
ADM682xR
ADM682xZ
ADM682xY
ADM682xW
4.50
4.25
3.00
2.85
2.55
2.25
2.12
1.62
1.52
4.63
4.38
3.08
2.93
2.63
2.32
2.19
1.67
1.58
60
4.75
4.50
3.15
3.00
2.70
2.38
2.25
1.71
1.62
V
V
V
V
V
V
V
V
ADM682xV
V
RESET THRESHOLD TEMPERATURE COEFFICIENT
RESET THRESHOLD HYSTERESIS
VCC TO RESET DELAY
ppm/°C
mV
2 x VTH
20
μs
VTH − VCC = 100 mV
RESET TIMEOUT PERIOD
RESET Output Voltage
140
200
280
ms
VOL (Push-Pull or Open-Drain)
0.3
0.3
0.3
0.4
V
V
V
V
V
V
V
VCC > = 1 V, ISINK = 50 μA
VCC > = 1.2 V, ISINK = 100 μA
VCC > = 2.55 V, ISINK = 1.2 mA
VCC > = 4.25 V, ISINK = 3.2 mA
VCC > = 1.8 V, ISOURCE = 200 μA
VCC > = 3.15 V, ISOURCE = 500 μA
VCC > = 4.75 V, ISOURCE = 800 μA
RESET not asserted
VOH (Push-Pull Only)
0.8 × VCC
0.8 × VCC
0.8 × VCC
RESET OUTPUT LEAKAGE CURRENT (Open-Drain
Only)
1
μA
RESET OUTPUT VOLTAGE (Push-Pull Only)
VOH
0.8 × VCC
0.8 × VCC
0.8 × VCC
0.8 × VCC
V
V
V
V
V
V
V
VCC > = 1 V, ISOURCE = 1 μA
VCC > = 1.5 V, ISOURCE = 100 μA
VCC > = 2.55 V, ISOURCE = 500 μA
VCC > = 4.25 V, ISOURCE = 800 μA
VCC > = 1.8 V, ISINK = 500 μA
VCC > = 3.15 V, ISINK = 1.2 mA
VCC > = 4.75 V, ISINK = 3.2 mA
VOL
0.3
0.3
0.4
MANUAL RESET INPUT
(ADM6821/ADM6822/ADM6823/ADM6825)
MR Input Threshold
VIL
0.3 × VCC
V
VIH
0.7 × VCC
1
V
MR Input Pulse Width
MR Glitch Rejection
MR to Reset Delay
MR Pull-Up Resistance
μs
ns
ns
kΩ
100
200
50
25
75
Rev. 0 | Page 3 of 12
ADM6821/ADM6822/ADM6823/ADM6824/ADM6825
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
WATCHDOG INPUT
(ADM6821/ADM6822/ADM6823/ADM6824)
Watchdog Timeout Period
WDI Pulse Width
WDI Input Threshold
VIL
1.12
50
1.6
2.40
sec
ns
0.3 × VCC
160
V
V
μA
μA
VIH
0.7 × VCC
WDI Input Current
120
VWDI = VCC
VWDI = 0
−20
−15
Rev. 0 | Page 4 of 12
ADM6821/ADM6822/ADM6823/ADM6824/ADM6825
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
Parameter
Rating
VCC
−0.3 V to +6 V
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Output Current (RESET, RESET)
Operating Temperature Range
Storage Temperature Range
20 mA
−40°C to +125°C
−65°C to +150°C
170°C/W
θJA Thermal Impedance
Soldering Temperature
Sn/Pb
Pb-Free
240°C, 30 sec
260°C, 40 sec
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 5 of 12
ADM6821/ADM6822/ADM6823/ADM6824/ADM6825
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
RESET
GND
MR
1
2
3
5
V
RESET
GND
1
2
3
5
4
V
CC
CC
ADM6821
TOP VIEW
ADM6824
TOP VIEW
(Not to Scale)
(Not to Scale)
4
WDI
RESET
WDI
Figure 2. ADM6821 Pin Configuration
Figure 4. ADM6824 Pin Configuration
RESET
GND
MR
1
2
3
5
V
RESET
GND
1
2
3
5
V
CC
CC
ADM6822/
ADM6823
ADM6825
TOP VIEW
(Not to Scale)
TOP VIEW
(Not to Scale)
4
WDI
RESET
4
MR
Figure 3. ADM6822/ADM6823 Pin Configuration
Figure 5. ADM6825 Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Name
Description
1
RESET
Active-Low Reset Output. Asserted whenever VCC is below the reset threshold, VTH
Open-Drain Output Stage for the ADM6822.
Push-Pull Output Stage for the ADM6823/ADM6824/ADM6825.
Active-High Push-Pull Reset Output.
.
(ADM6822/ADM6823/ADM6824/ADM6825)
RESET (ADM6821)
2
3
GND
Ground.
MR (ADM6821/ADM6822/ADM6823)
Manual Reset Input. This is an active-low input, which, when forced low for at
least 1 μs, generates a reset. It features a 50 kΩ internal pull-up.
RESET (ADM6824/ADM6825)
WDI
Active-High Push-Pull Reset Output.
Watchdog Input. Generates a reset if the voltage on the pin remains low or high
4
5
(ADM6821/ADM6822/ADM6823/ADM6824) for the duration of the watchdog timeout. The timer is cleared if a logic transition
occurs on this pin or if a reset is generated.
MR (ADM6825)
VCC
Manual Reset Input.
Power Supply Voltage Being Monitored.
Rev. 0 | Page 6 of 12
ADM6821/ADM6822/ADM6823/ADM6824/ADM6825
TYPICAL PERFORMANCE CHARACTERISTICS
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
1.20
1.15
1.10
1.05
1.00
0.95
0.90
V
= 5V
CC
V
= 3.3V
CC
V
= 1.5V
CC
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 6. Supply Current vs. Temperature
Figure 9. Normalized Watchdog Timeout Period vs. Temperature
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
0.95
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. Normalized RESET Timeout Period vs. Temperature
Figure 10. Normalized RESET Threshold vs. Temperature
100
160
140
120
100
80
90
80
70
60
50
40
30
20
10
0
60
40
V
= 4.63V
CC
V
= 2.93V
20
CC
0
10
–40
–20
0
20
40
60
80
100
120
100
1000
TEMPERATURE (°C)
RESET THRESHOLD OVERDRIVE (mV)
Figure 11. Maximum VCC Transient Duration vs. RESET Threshold Overdrive
Figure 8. VCC to RESET Output Delay vs. Temperature
Rev. 0 | Page 7 of 12
ADM6821/ADM6822/ADM6823/ADM6824/ADM6825
0.20
0.15
0.10
0.05
0
2.92
2.90
2.88
2.86
2.84
2.82
V
= 2.9V
V
= 2.9V
CC
CC
0
1
2
3
4
5
6
7
0
0.2
0.4
0.6
(mA)
0.8
1.0
I
(mA)
I
SOURCE
SINK
Figure 12. Voltage Output Low vs. ISINK
Figure 13. Voltage Output High vs. ISOURCE
Rev. 0 | Page 8 of 12
ADM6821/ADM6822/ADM6823/ADM6824/ADM6825
CIRCUIT DESCRIPTION
The ADM682x provide microprocessor supply voltage
MANUAL RESET INPUT
supervision by controlling the microprocessor’s reset input.
Code execution errors are avoided during power-up, power-
down, and brownout conditions by asserting a reset signal when
the supply voltage is below a preset threshold. In addition, the
ADM682x allow supply voltage stabilization with a fixed
timeout before the reset deasserts after the supply voltage rises
above the threshold.
The ADM6821/ADM6822/ADM6823/ADM6825 feature a
manual reset input (
), which, when driven low, asserts the
MR
reset output. When
transitions from low to high, reset
MR
remains asserted for the duration of the reset active timeout
period before deasserting. The input has a 50 kΩ internal
MR
pull-up so that the input is always high when unconnected. An
external push-button switch can be connected between and
MR
Problems with microprocessor code execution can be
monitored and corrected with a watchdog timer (ADM6821/
ADM6822/ADM6823/ADM6824). When watchdog strobe
instructions are included in microprocessor code, a watchdog
timer detects if the microprocessor code breaks down or
becomes stuck in an infinite loop. If this happens, the watchdog
timer asserts a reset pulse, which restarts the microprocessor in
a known state.
ground so that the user can generate a reset. Debounce circuitry
is integrated on-chip for this purpose. Noise immunity is
provided on the
input, and fast, negative-going transients of
MR
up to 100 ns (typ) are ignored. A 0.1 μF capacitor between
and ground provides additional noise immunity.
MR
WATCHDOG INPUT
The ADM6821/ADM6822/ADM6823/ADM6824 feature a
watchdog timer, which monitors microprocessor activity. A
timer circuit is cleared with every low-to-high or high-to-low
logic transition on the watchdog input pin (WDI), which
detects pulses as short as 50 ns. If the timer counts through the
preset watchdog timeout period (tWD), reset is asserted. The
microprocessor is required to toggle the WDI pin to avoid
being reset. Failure of the microprocessor to toggle WDI within
the timeout period therefore indicates a code execution error,
and the reset pulse generated restarts the microprocessor in a
known state.
If the user detects a problem with the system’s operation,
a manual reset input is available (ADM6821/ADM6822/
ADM6823/ADM6825) to reset the microprocessor by means
of an external push-button, for example.
RESET OUTPUT
The ADM6821 features an active-high push-pull reset output.
The ADM6822 features an active-low open-drain reset output,
while the ADM6823 features an active-low push-pull output.
The ADM6824/ADM6825 feature dual active-low and active-
high push-pull reset outputs. For active-low and active-high
outputs, the reset signal is guaranteed to be logic low and logic
high, respectively, for VCC down to 1 V.
In addition to logic transitions on WDI, the watchdog timer is
also cleared by a reset assertion due to an undervoltage condi-
tion on VCC or
being pulled low. When reset is asserted, the
MR
watchdog timer is cleared and does not begin counting again
until reset deassserts. The watchdog timer can be disabled by
leaving WDI floating or by three-stating the WDI driver.
The reset output is asserted when VCC is below the reset
threshold (VTH), when
is driven low, or when WDI is not
MR
serviced within the watchdog timeout period (tWD). Reset
remains asserted for the duration of the reset active timeout
period (tRP) after VCC rises above the reset threshold, after
V
CC
V
TH
V
CC
MR
1V
0V
transitions from low to high, or after the watchdog timer times
out. Figure 14 shows the reset outputs.
V
CC
RESET
WDI
tRP
tWD
tRD
0V
V
CC
V
CC
V
V
TH
TH
V
CC
0V
1V
0V
V
CC
Figure 15. Watchdog Timing Diagram
RESET
RESET
tRP
tRD
0V
V
CC
tRP
1V
0V
tRD
Figure 14. Reset Timing Diagram
Rev. 0 | Page 9 of 12
ADM6821/ADM6822/ADM6823/ADM6824/ADM6825
APPLICATION INFORMATION
WATCHDOG INPUT CURRENT
WATCHDOG SOFTWARE CONSIDERATIONS
To minimize watchdog input current (and minimize overall
power consumption), leave WDI low for the majority of the
watchdog timeout period. When driven high, WDI can draw as
much as 160 μA. Pulsing WDI low-high-low at a low duty cycle
reduces the effect of the large input current. When WDI is
unconnected, a window comparator disconnects the watchdog
timer from the reset output circuitry so that reset is not asserted
when the watchdog timer times out.
In implementing the microprocessor’s watchdog strobe code,
quickly switching WDI low-high and then high-low
(minimizing WDI high time) is desirable for current
consumption reasons. However, a more effective way of using
the watchdog function can be considered.
A low-high-low WDI pulse within a given subroutine prevents
the watchdog from timing out. However, if the subroutine
becomes stuck in an infinite loop, the watchdog could not
detect this because the subroutine continues to toggle WDI. A
more effective coding scheme for detecting this error involves
using a slightly longer watchdog timeout. In the program that
calls the subroutine, WDI is set high. The subroutine sets WDI
low when it is called. If the program executes without error,
WDI is toggled high and low with every loop of the program. If
the subroutine enters an infinite loop, WDI is kept low, the
watchdog times out, and the microprocessor is reset.
NEGATIVE-GOING VCC TRANSIENTS
To avoid unnecessary resets caused by fast power supply
transients, the ADM682x are equipped with glitch rejection
circuitry. The typical performance characteristic in Figure 11
plots VCC transient duration versus. the transient magnitude.
The curves show combinations of transient magnitude and
duration for which a reset is not generated for the 4.63 V and
2.93 V reset threshold parts. For example, with the 2.93 V
threshold, a transient that goes 100 mV below the threshold and
lasts 8 μs typically does not cause a reset, but if the transient is
any bigger in magnitude or duration, a reset is generated. An
optional 0.1 μF bypass capacitor mounted close to VCC provides
additional glitch rejection.
START
SET WDI
HIGH
RESET
PROGRAM
CODE
ENSURING RESET VALID TO VCC = 0 V
Both active-low and active-high reset outputs are guaranteed to
be valid for VCC as low as 1 V. However, by using an external
resistor with push-pull configured reset outputs, valid outputs
for VCC as low as 0 V are possible. For an active-low reset
INFINITE LOOP:
WATCHDOG
TIMES OUT
SUBROUTINE
SET WDI
LOW
output, a resistor connected between
and ground pulls
RESET
the output low when it is unable to sink current. For the active-
high case, a resistor connected between RESET and VCC pulls
the output high when it is unable to source current. A large
resistance such as 100 kΩ should be used so that it does not
overload the reset output when VCC is above 1 V.
RETURN
Figure 17. Watchdog Flow Diagram
V
V
CC
CC
V
CC
100kΩ
ADM6822/
ADM6823/
ADM6824/
ADM6825
RESET
RESET
ADM6821/
ADM6824/
ADM6825
RESET
ADM6823
μP
RESET
MR
WDI
I/O
100kΩ
GND
GND
Figure 18. Typical Application Circuit
Figure 16. Ensuring Reset Valid to VCC = 0 V
Rev. 0 | Page 10 of 12
ADM6821/ADM6822/ADM6823/ADM6824/ADM6825
OUTLINE DIMENSIONS
2.90 BSC
5
4
3
2.80 BSC
1.60 BSC
1
2
PIN 1
0.95 BSC
1.90
BSC
1.30
1.15
0.90
1.45 MAX
0.22
0.08
10°
5°
0°
0.15 MAX
0.50
0.30
0.60
0.45
0.30
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-178-AA
Figure 19. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
ADM682 x x YRJZ -RL7
GENERIC NUMBER
ORDERING QUANTITY
RL7: 3,000 PIECE REEL
(1 TO 5)
RESET
Z: LEAD-FREE
THRESHOLD
NUMBER
L: 4.63V
M: 4.38V
T: 3.08V
S: 2.93V
R: 2.63V
Z: 2.32V
Y: 2.19V
W: 1.67V
V: 1.58V
TEMPERATURE RANGE
Y: –40°C TO +125°C
PACKAGE CODE
RJ: 5-LEAD SOT-23
Figure 20. Ordering Code Structure
ORDERING GUIDE
Standard Models1
Reset Threshold (V) Reset Timeout (ms) Temperature Range Quantity Package Option Branding
ADM6821SYRJZ-
2.93
140
3k
RJ-5
N0A
−40°C to +125°C
RL72
ADM6822SYRJZ-RL72 2.93
ADM6822TYRJZ-RL72 3.08
140
140
140
140
140
140
140
140
3k
3k
3k
3k
3k
3k
3k
3k
RJ-5
RJ-5
RJ-5
RJ-5
RJ-5
RJ-5
RJ-5
RJ-5
N0B
N0B
N0C
N0Q
N0C
N0Q
N0D
N0E
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
ADM6823SYRJ-R7
ADM6823SYRJZ-RL72 2.93
ADM6823TYRJ-R7 3.08
ADM6823TYRJZ-RL72 3.08
2.93
ADM6824TYRJZ-R72
ADM6825TYRJZ-R72
3.08
3.08
1 If ordering nonstandard models, complete the ordering code shown in Figure 20 by inserting the part number and reset threshold suffixes. Contact Sales for
availability of nonstandard models.
2 Z = Pb-free part.
Rev. 0 | Page 11 of 12
ADM6821/ADM6822/ADM6823/ADM6824/ADM6825
NOTES
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04535–0–6/05(0)
Rev. 0 | Page 12 of 12
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