ADM6824TYRJZ-RL7 [ADI]
1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, LEAD FREE, MO-178AA, SOT-23, 5 PIN;
| 型号： | ADM6824TYRJZ-RL7 |
| 厂家： | 
ADI |
| 描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, LEAD FREE, MO-178AA, SOT-23, 5 PIN 光电二极管 |
| 文件： | 总11页 (文件大小：159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Voltage Supervisory Circuits with
Watchdog and Manual Reset in 5-Lead SOT-23
Preliminary Technical Data
ADM6821–ADM6825
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Precision low voltage monitoring down to 1.8 V
9 reset threshold options:
1.58 V to 4.63 V
140 ms (min) reset timeout
Watchdog timer with 1.6s timeout
Manual reset input
VCC
ADM6823
V
CC
RESET
GENERATOR
RESET
V
REF
MR
DEBOUNCE
Reset output stages
Push-pull active-low
Open-drain active-low
WATCHDOG
DETECTOR
Push-pull active-high
Low power consumption (3 µA)
Guaranteed reset output valid to VCC = 1 V
Power supply glitch immunity
Specified from –40°C to +125°C
5-lead SOT-23 package
GND
WDI
Figure 1.
APPLICATIONS
Microprocessor systems
Computers
Controllers
Intelligent instruments
Portable equipment
GENERAL DESCRIPTION
input and output stage configuration, as shown in table 1.
The ADM6821–ADM6825 are supervisory circuits that monitor
power supply voltage levels and code execution integrity in
microprocessor-based systems. As well as providing power on
reset signals, an on-chip watchdog timer can reset the
microprocessor if it fails to strobe within a preset timeout
period. A reset signal can also be asserted by means of an
external push-button, through a manual reset input. The parts
feature different combinations of watchdog input, manual reset
Each part is available in a choice of nine reset threshold options
ranging from 1.58 V to 4.63 V. The reset and watchdog timeout
periods are fixed at 140 ms (min) and 1.6s (typ), respectively.
The ADM6821–ADM6825 are available in 5-lead SOT-23
packages and typically consume only 3 µA, making them
suitable for use in low power portable applications.
Table 1. Selection Table
Output Stage
Part No.
Watchdog Timer
Manual Reset
RESET
RESET
ADM6821
ADM6822
ADM6823
ADM6824
ADM6825
Yes
Yes
Yes
Yes
-
Yes
Yes
Yes
-
-
Push-Pull
-
Open-Drain
Push-Pull
Push-Pull
Push-Pull
-
Push-Pull
Push-Pull
Yes
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
ADM6821–ADM6825
Preliminary Technical Data
TABLE OF CONTENTS
Specifications..................................................................................... 3
Watchdog Input .............................................................................9
Application Information................................................................ 10
Watchdog Input Current ........................................................... 10
Negative-Going VCC Transients ................................................ 10
Ensuring Reset Valid to VCC = 0 V............................................ 10
Watchdog Software Considerations......................................... 10
Outline Dimensions....................................................................... 11
ORDERING GUIDE.................................................................. 11
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configurations And Functional Descriptions ....................... 6
Typical Performance Characteristics ............................................. 7
Circuit Description........................................................................... 9
Reset Output ................................................................................. 9
Manual Reset Input ...................................................................... 9
REVISION HISTORY
Revision 0: Initial Version
Rev. PrB | Page 2 of 11
Preliminary Technical Data
SPECIFICATIONS
ADM6821–ADM6825
Table 1. VCC = 4. 5 V to 5.5 V for ADM682_L/M, VCC = 2.7 V to 3.6 V for ADM682_T/S/R, VCC = 2.1 V to 2.75 V for
ADM682_Z/Y, VCC = 1.53 V to 2.0 V for ADM682_W/V, TA = –40°C to +125°C, unless otherwise noted
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SUPPLY
VCC Operating Voltage Range
1
1.2
5.5
20
16
V
V
µA
TA = 0°C to +85°C
TA = -40°C to 125°C
Supply Current
10
7
MR
WDI and
CC=5.5V
WDI and
CC=3.6V
unconnected,
V
µA
MR
unconnected,
V
RESET THRESHOLD VOLTAGE
ADM682_L
4.50
4.25
3.00
2.85
2.55
2.25
2.13
1.62
1.52
4.63
4.38
3.08
2.93
2.63
2.32
2.19
1.67
4.75
4.50
3.15
3.00
2.70
2.38
2.25
1.71
1.62
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
ADM682_M
ADM682_T
ADM682_S
ADM682_R
ADM682_Z
ADM682_Y
ADM682_W
ADM682_V
1.58
60
V
RESET THRESHOLD TEMPERATURE COEFFICIENT
RESET THRESHOLD HYSTERESIS
RESET TIMEOUT PERIOD
ppm/°C
mV
ms
10
140
200
40
280
VCC TO RESET DELAY
µs
VTH − VCC = 100mV
RESET
Output Voltage
VOL
0.3
0.3
0.3
0.4
V
V
V
V
V
V
V
VCC >=1V, ISINK = 50µA
VCC >=1.2V, ISINK = 100µA
VCC >=2.55V, ISINK = 1.2mA
VCC>=4.25V, ISINK = 3.2mA
VCC>=1.8V, ISOURCE = 200µA
VCC>=3.15V, ISOURCE = 500µA
VCC>=4.75V, ISOURCE = 800µA
VOH
0.8 × VCC
0.8 × VCC
0.8 × VCC
RESET
1
µA
RESET
not asserted
Output leakage Current
RESET Output Voltage
VOL
0.3
0.3
0.4
V
V
V
V
V
V
V
VCC >=1.8V, ISINK = 500µA
VCC >=3.15V, ISINK = 1.2mA
VCC >=4.75V, ISINK = 3.2mA
VCC > = 1V, ISOURCE = 1µA
VCC>=1.5V, ISOURCE = 100µA
VCC>=2.55V, ISOURCE = 500µA
VCC>=4.25V, ISOURCE = 800µA
VOH
0.8 × VCC
0.8 × VCC
0.8 × VCC
0.8 × VCC
WATCHDOG INPUT (ADM6821/2/3/4)
Watchdog Timeout Period
1.12
1.6
2.40
s
Rev. PrB | Page 3 of 11
ADM6821–ADM6825
Preliminary Technical Data
Parameter
WDI Pulse Width
WDI Input Threshold
VIL
Min
Typ
Max
Unit
Test Conditions/Comments
50
ns
VIL = 0.4 V, VIH = 0.8×VCC
0.3 × VCC
160
V
V
µA
µA
VIH
0.7 × VCC
−20
WDI Input Current
120
−15
VWDI = VCC, time average
VWDI = 0, time average
MANUAL RESET INPUT (ADM6821/2/3/5)
MR
0.3 × VCC
V
Input Threshold
0.7 × VCC
1
V
µs
ns
MR
MR
MR
MR
Input Pulse Width
Glitch Rejection
Pull-up Resistance
to Reset Delay
100
52
25
75
k⍀
ns
200
Rev. PrB | Page 4 of 11
Preliminary Technical Data
ADM6821–ADM6825
ABSOLUTE MAXIMUM RATINGS
Table 2. TA = 25°C, unless otherwise noted
Parameter
Rating
VCC
−0.3 V to +6 V
20 mA
RESET
Output Current (RESET,
)
Operating Temperature Range
Storage Temperature Range
−40°C to +125°C
−65°C to +150°C
270°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
θJA Thermal Impedance
Lead Temperature
Soldering (10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
300°C
215°C
220°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrB | Page 5 of 11
ADM6821–ADM6825
Preliminary Technical Data
PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS
RESET
GND
MR
1
2
3
5
V
RESET
GND
MR
1
2
3
5
V
CC
CC
ADM6821
TOP VIEW
ADM6822/
ADM6823
(Not to Scale)
TOP VIEW
(Not to Scale)
4
WDI
4
WDI
Figure 2. ADM6821. Pin Configuration
Figure 3. ADM6822/ ADM6823 Pin Configuration
RESET
GND
1
2
3
5
V
RESET
GND
1
2
3
5
V
CC
CC
ADM6824
TOP VIEW
(Not to Scale)
ADM6825
TOP VIEW
(Not to Scale)
RESET
4
WDI
RESET
4
MR
Figure 4. ADM6824 Pin Configuration
Figure 5. ADM6825 Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Name
Description
1
RESET
Active-Low Reset Output. Asserted whenever VCC is below the reset threshold, VTH
Open-Drain Output Stage for ADM6822.
Push-Pull Output Stage for ADM6823/ADM6824/ADM6825.
Active-High, Push Pull Reset Output
.
(ADM6822/ADM6823/ADM6824/
ADM6825)
RESET (ADM6821)
GND
2
3
Ground
MR
Manual Reset Input. This is an active-low input which, when forced low for at least 1 µs,
generates a reset.
(ADM6821/ADM6822/ADM6823)
Features a 52 k⍀ internal pull-up.
RESET (ADM6824/ADM6825)
Active-High Push-Pull Reset Output.
4
5
WDI
Watchdog Input. Generates a reset if the voltage on the pin remains low or high for the
duration of the watchdog timeout. The timer is cleared if a logic transition occurs on this
pin or if a reset is generated.
(ADM6821/ADM6822/ADM6823/
ADM6824)
MR
VCC
Manual Reset Input.
(ADM6825)
Power Supply Voltage Being Monitored.
Rev. PrB | Page 6 of 11
Preliminary Technical Data
ADM6821–ADM6825
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 6. Supply Current vs. Temperature
Figure 7. Normalized RESET Timeout Period vs. Temperature
Figure 8. VCC to RESET Output Delay vs. Temperature
Figure 9. Normalized Watchdog Timeout Period vs. Temperature
Figure 10. Normalised RESET Threshold vs. Temperature
Figure 11.Maximum VCC Transient Duration vs. RESET Threshold Overdrive
Rev. PrB | Page 7 of 11
ADM6821–ADM6825
Preliminary Technical Data
Figure 12. Voltage Output Low vs. ISINK
Figure 13. Voltage Output High vs. ISOURCE
Rev. PrB | Page 8 of 11
Preliminary Technical Data
CIRCUIT DESCRIPTION
ADM6821–ADM6825
The ADM6821/2/3/4/5 provide microprocessor supply voltage
supervision by controlling the microprocessor’s reset input.
Code-execution errors are avoided during power-up, power-
down, and brownout conditions by asserting a reset signal when
the supply voltage is below a preset threshold and by allowing
supply voltage stabilization with a fixed-timeout reset pulse
after the supply voltage rises above the threshold. In addition,
problems with microprocessor code execution can be
monitored and corrected with a watchdog timer
MANUAL RESET INPUT
The ADM6821/2/3/5 feature a manual reset input (
) which,
transitions
MR
when driven low, asserts the reset output. When
MR
from low to high, reset remains asserted for the duration of the
reset active timeout period before deasserting. The input
MR
has a 52 k⍀ internal pull-up so that the input is always high
when unconnected. An external push-button switch can be
connected between
and ground so that the user can
MR
generate a reset. Debounce circuitry is integrated on-chip for
this purpose. Noise immunity is provided on the input and
(ADM6821/2/3/4). By including watchdog strobe instructions
in microprocessor code, a watchdog timer can detect if the
microprocessor code breaks down or becomes stuck in an
infinite loop. If this happens, the watchdog timer asserts a reset
pulse that restarts the microprocessor in a known state. If the
user detects a problem with the system’s operation, a manual
reset input is available (ADM6821/2/3/5) to reset the
microprocessor by means of an external push-button, for
example.
MR
fast, negative-going transients of up to 100 ns (typ) are ignored.
A 0.1 µF capacitor between
and ground provides additional
MR
noise immunity.
WATCHDOG INPUT
The ADM6821/2/3/4 feature a watchdog timer which monitors
microprocessor activity. A timer circuit is cleared with every
low-to-high or high-to-low logic transition on the watchdog
input pin (WDI), which detects pulses as short as 50 ns. If the
timer counts through the preset watchdog timeout period (tWD),
reset is asserted. The microprocessor is required to toggle the
WDI pin to avoid being reset. Failure of the microprocessor to
toggle WDI within the timeout period therefore indicates a
code execution error, and the reset pulse generated restarts the
microprocessor in a known state.
RESET OUTPUT
The ADM6821/3 feature an active-low, push-pull reset output
while the ADM6822 features an active-low open drain reset
output. The ADM6824/5 feature dual active-low and active-
high push-pull reset outputs. For active-low and active-high
outputs, the reset signal is guaranteed to be logic low and logic
high respectively for VCC down to 1 V.
The reset output is asserted when VCC is below the reset
In addition to logic transitions on WDI, the watchdog timer is
also cleared by a reset assertion due to an undervoltage condi-
threshold (VTH), when
is driven low or when WDI is not
MR
tion on VCC or
being pulled low. When reset is asserted, the
MR
serviced within the watchdog timeout period (tWD). Reset
remains asserted for the duration of the reset active timeout
period (tRP) after VCC rises above the reset threshold, after
transitions from low-to-high, or after the watchdog timer times
out. Figure 14 illustrates the behavior of the reset outputs.
watchdog timer is cleared and does not begin counting again
until reset deassserts. The watchdog timer can be disabled by
leaving WDI floating or by three-stating the WDI driver.
MR
V
CC
V
TH
V
CC
1V
0V
V
CC
V
V
TH
TH
V
CC
V
1V
0V
CC
RESET
WDI
tRP
tWD
tRD
0V
V
CC
V
RESET
RESET
tRP
CC
tRD
0V
0V
V
CC
tRP
1V
0V
Figure 15. Watchdog Timing Diagram
tRD
Figure 14. Reset Timing Diagram
Rev. PrB | Page 9 of 11
ADM6821–ADM6825
Preliminary Technical Data
APPLICATION INFORMATION
WATCHDOG INPUT CURRENT
WATCHDOG SOFTWARE CONSIDERATIONS
In order to minimize watchdog input current (and minimize
overall power consumption), leave WDI low for the majority of
the watchdog timeout period. When driven high, WDI can draw
as much as 160 µA. Pulsing WDI low-high-low at a low duty
cycle reduces the effect of the large input current. When WDI is
unconnected, a window comparator disconnects the watchdog
timer from the reset output circuitry so that reset is not asserted
when the watchdog timer times out.
In implementing the microprocessor’s watchdog strobe code,
quickly switching WDI low-high and then high-low
(minimizing WDI high time) is desirable for current
consumption reasons. However, a more effective way of using
the watchdog function can be considered.
A low-high-low WDI pulse within a given subroutine prevents
the watchdog timing out. However, if the subroutine becomes
stuck in an infinite loop, the watchdog could not detect this
because the subroutine continues to toggle WDI. A more
effective coding scheme for detecting this error involves using a
slightly longer watchdog timeout. In the program that calls the
subroutine, WDI is set high. The subroutine sets WDI low when
it is called. If the program executes without error, WDI is
toggled high and low with every loop of the program. If the
subroutine enters an infinite loop, WDI is kept low, the
watchdog times out, and the microprocessor is reset.
NEGATIVE-GOING VCC TRANSIENTS
To avoid unnecessary resets caused by fast power supply
transients, the ADM6821/2/3/4/5 are equipped with glitch
rejection circuitry. The typical performance characteristic in
Error! Reference source not found. plots VCC transient
duration versus the transient magnitude. The curves show
combinations of transient magnitude and duration for which a
reset is not generated for 4.63 V and 2.93 V reset threshold
parts. For example, with the 2.93 V threshold, a transient that
goes 100 mV below the threshold and lasts 8 µs typically does
not cause a reset, but if the transient is any bigger in magnitude
or duration, a reset is generated. An optional 0.1 µF bypass
capacitor mounted close to VCC provides additional glitch
rejection.
START
SET WDI
HIGH
RESET
PROGRAM
CODE
ENSURING RESET VALID TO VCC = 0 V
INFINITE LOOP:
WATCHDOG
TIMES OUT
Both active-low and active-high reset outputs are guaranteed to
be valid for VCC as low as 1V. However, by using an external
resistor with push-pull configured reset outputs, valid outputs
for VCC as low as 0 V are possible. For an active-low reset output,
SUBROUTINE
SET WDI
LOW
a resistor connected between
and ground pulls the
RESET
RETURN
output low when it is unable to sink current. For the active-high
case, a resistor connected between RESET and VCC pulls the
output high when it is unable to source current. A large
resistance such as 100 kΩ should be used so that it does not
overload the reset output when VCC is above 1 V.
Figure 17. Watchdog Flow Diagram
V
CC
V
V
CC
CC
100k⍀
RESET
RESET
RESET
RESET
mP
ADM6823
ADM6822/3/4/5
ADM6821/4/5
100k⍀
MR
WDI
I/O
GND
GND
Figure 16. Ensuring Reset Valid to VCC = 0 V
Figure 18. Typical Application Circuit
TBD
Rev. PrB | Page 10 of 11
Preliminary Technical Data
OUTLINE DIMENSIONS
ADM6821–ADM6825
2.90 BSC
5
4
3
2.80 BSC
1.60 BSC
2
PIN 1
0.95 BSC
1.90
BSC
1.30
1.15
0.90
1.45 MAX
0.22
0.08
10°
5°
0°
0.15 MAX
0.50
0.30
0.60
0.45
0.30
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-178AA
Figure 19. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
ORDERING GUIDE
Table 4. ADM6821/2/3/4/5 Ordering Guide
ADM682_ _YRJZ-RL7
GENERIC NUMBER
ORDERING QUANTITY
RL7: 3,000 PIECE REEL
(1 TO 5)
RESET
THRESHOLD
NUMBER
L: 4.63V
Z: LEAD FREE
TEMPERATURE RANGE
PACKAGE CODE
RJ: 5-LEAD SOT-23
o
o
Y: -40 C TO +125 C
M: 4.38V
T: 3.08V
S: 2.93V
R: 2.63V
Z: 2.32V
Y: 2.19V
W: 1.67V
V: 1.58V
Figure 2. Ordering Code Structure
Model1,2
Reset
Threshold (V)
Reset Timeout
(ms)
Temperature
Range
Quantity Package
Type
Branding
ADM6823TYRJZ-RL7
ADM6823SYRJZ-RL7
3.08
2.93
140
140
–40°C to +125°C
–40°C to +125°C
3k
3k
RJ-5
RJ-5
N0C
N0C
1
1 Complete the ordering code by inserting the part number and reset threshold suffixes from Table 4.
1 Contact Sales for the availability of nonstandard models.
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.
Printed in the U.S.A. PR04535-0-3/05(PrB)
Rev. PrB | Page 11 of 11
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