ADM690 [ADI]
Microprocessor Supervisory Circuits; 微处理器监控电路
| 型号： | ADM690 |
| 厂家： | 
ADI |
| 描述： | Microprocessor Supervisory Circuits |
| 文件： | 总16页 (文件大小：286K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Microprocessor
Supervisory Circuits
a
ADM690–ADM695
FEATURES
FUNCTIO NAL BLO CK D IAGRAMS
Superior Upgrade for MAX690–MAX695
Specified Over Tem perature
VBATT
Low Pow er Consum ption (5 m W)
Precision Voltage Monitor
Reset Assertion Dow n to 1 V VCC
Low Sw itch On-Resistance 1.5 ⍀ Norm al,
20 ⍀ in Backup
VOUT
VCC
RESET
4.65V1
GENERATOR2
RESET
High Current Drive (100 m A)
Watchdog Tim er—100 m s, 1.6 s, or Adjustable
600 nA Standby Current
Autom atic Battery Backup Pow er Sw itching
Extrem ely Fast Gating of Chip Enable Signals (5 ns)
Voltage Monitor for Pow er Fail
WATCHDOG
TRANSITION DETECTOR
(1.6s)
WATCHDOG
INPUT (WDI)
ADM690
ADM692
ADM694
POWER FAIL
INPUT (PFI)
POWER FAIL
OUTPUT (PFO)
APPLICATIONS
1.3V
Microprocessor System s
Com puters
1VOLTAGE DETECTOR = 4.65V (ADM690, ADM694)
4.40V (ADM692)
Controllers
Intelligent Instrum ents
Autom otive System s
2RESET PULSE WIDTH = 50ms (ADM690, ADM692)
200ms (ADM694)
BATT ON
VBATT
GENERAL D ESCRIP TIO N
T he ADM690–ADM695 family of supervisory circuits offers
complete single chip solutions for power supply monitoring and
battery control functions in microprocessor systems. T hese
functions include µP reset, backup battery switchover, watchdog
timer, CMOS RAM write protection, and power failure warn-
ing. T he complete family provides a variety of configurations to
satisfy most microprocessor system requirements.
VOUT
ADM691
ADM693
ADM695
VCC
CEIN
CEOUT
LOW LINE
4.65V1
RESET
RESET
T he ADM690, ADM692 and ADM694 are available in 8-pin
DIP packages and provide:
RESET &
RESET
OSC IN
WATCHDOG
GENERATOR
OSC SEL
TIMEBASE
1. Power-on reset output during power-up, power-down and
brownout conditions. T he RESET output remains opera-
tional with VCC as low as 1 V.
WATCHDOG
TIMER
WATCHDOG
WATCHDOG
INPUT (WDI)
WATCHDOG
OUTPUT (WDO)
TRANSITION DETECTOR
2. Battery backup switching for CMOS RAM, CMOS
microprocessor or other low power logic.
POWER FAIL
INPUT (PFI)
POWER FAIL
OUTPUT (PFO)
3. A reset pulse if the optional watchdog timer has not been
toggled within a specified time.
1.3V
1VOLTAGE DETECTOR = 4.65V (ADM691, ADM695)
4.40V (ADM693)
4. A 1.3 V threshold detector for power fail warning, low battery
detection, or to monitor a power supply other than +5 V.
T he ADM690–ADM695 family is fabricated using an advanced
epitaxial CMOS process combining low power consumption
(5 mW), extremely fast Chip Enable gating (5 ns) and high reli-
ability. RESET assertion is guaranteed with VCC as low as 1 V.
In addition, the power switching circuitry is designed for mini-
mal voltage drop thereby permitting increased output current
drive of up to 100 mA without the need for an external pass
transistor.
T he ADM691, ADM693 and ADM695 are available in 16-pin
DIP and small outline packages and provide three additional
functions.
1. Write protection of CMOS RAM or EEPROM.
2. Adjustable reset and watchdog timeout periods.
3. Separate watchdog timeout, backup battery switchover, and
low VCC status outputs.
REV. A
© Analog Devices, Inc., 1996
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
BATT = +2.8 V, T = TMIN to
ADM690–ADM695–SPECIFICATIONS (V = Full Operating Range, V
TMAX unless otherwise noted)
CC
A
P aram eter
Min
Typ
Max
Units
Test Conditions/Com m ents
BAT T ERY BACKUP SWIT CHING
VCC Operating Voltage Range
ADM690, ADM691, ADM694, ADM695
ADM692, ADM693
4.75
4.5
5.5
5.5
V
V
VBAT T Operating Voltage Range
ADM690, ADM691, ADM694, ADM695
ADM692, ADM693
2.0
2.0
4.25
4.0
V
V
VOUT Output Voltage
VCC – 0.05 VCC – 0.025
VCC – 0.5 VCC – 0.25
V
V
IOUT = 1 mA
IOUT ≤ 100 mA
VOUT in Battery Backup Mode
Supply Current (Excludes IOUT
Supply Current in Battery Backup Mode
Battery Standby Current
VBAT T – 0.05 VBAT T – 0.02
V
mA
µA
IOUT = 250 µA, VCC < VBAT T – 0.2 V
IOUT = 100 mA
VCC = 0 V, VBAT T = 2.8 V
5.5 V > VCC > VBAT T + 0.2 V
)
1
0.6
1.95
1
(+ = Discharge, – = Charge)
–0.1
–1.0
70
+0.02
+0.02
µA
µA
mV
mV
mV
V
T A = +25°C
Battery Switchover T hreshold
VCC – VBAT T
Battery Switchover Hysteresis
BAT T ON Output Voltage
BAT T ON Output Short Circuit Current
Power Up
Power Down
50
20
0.3
25
ISINK = 3.2 mA
BAT T ON = VOUT = 4.5 V Sink Current
BAT T ON = 0 V Source Current
35
mA
µA
0.5
1
RESET AND WAT CHDOG T IMER
Reset Voltage T hreshold
ADM690, ADM691, ADM694, ADM695
ADM692, ADM693
Reset T hreshold Hysteresis
4.5
4.25
4.65
4.4
40
4.73
4.48
V
V
mV
Reset T imeout Delay
ADM690, ADM691, ADM692, ADM693
ADM694, ADM695
Watchdog T imeout Period, Internal Oscillator
35
50
70
ms
ms
s
ms
Cycles
Cycles
ns
mV
V
V
OSC SEL = HIGH, VCC = 5 V, TA = +25°C
OSC SEL = HIGH, VCC = 5 V, TA = +25°C
Long Period, VCC = 5 V, T A = +25°C
Short Period, VCC = 5 V, T A = +25°C
Long Period
Short Period
VIL = 0.4, VIH = 3.5 V
ISINK = 10 µA, VCC = 1 V
ISINK = 1.6 mA, VCC = 4.25 V
ISOURCE = 1 µA, VCC = 5 V
ISINK = 1.6 mA, VCC = 5 V
ISOURCE = 1 µA, VCC = 4.25 V
140
1.0
70
3840
768
50
200
1.6
100
280
2.25
140
4097
1025
Watchdog T imeout Period, External Clock
Minimum WDI Input Pulse Width
RESET Output Voltage @ VCC = +1 V
RESET, LOW LINE Output Voltage
4
200
0.4
3.5
RESET, WDO Output Voltage
0.4
25
V
V
µA
mA
3.5
1
Output Short Circuit Source Current
Output Short Circuit Sink Current
WDI Input T hreshold
Logic Low
Logic High
WDI Input Current
3
25
VCC = 5 V1
0.8
50
V
V
µA
µA
3.5
20
–15
WDI = VOUT, T A = +25°C
WDI = 0 V, T A = +25°C
–50
POWER FAIL DET ECT OR
PFI Input T hreshold
PFI Input Current
1.25
–25
1.3
±0.01
1.35
+25
0.4
V
nA
V
VCC = +5 V
PFO Output Voltage
ISINK = 3.2 mA
3.5
1
V
µA
mA
ISOURCE = 1 µA
PFI = Low, PFO = 0 V
PFI = High, PFO = VOUT
PFO Short Circuit Source Current
PFO Short Circuit Sink Current
3
25
25
CHIP ENABLE GAT ING
CEIN T hreshold
0.8
0.4
9
V
V
µA
V
V
VIL
VIH
3.0
CEIN Pull-Up Current
CEOUT Output Voltage
3
5
ISINK = 3.2 mA
ISOURCE = 3.0 mA
ISOURCE = 1 µA, VCC = 0 V
VOUT – 1.5
VOUT – 0.05
V
ns
CE Propagation Delay
REV. A
–2–
ADM690–ADM695
P aram eter
Min
Typ
Max
Units
Test Conditions/Com m ents
OSCILLAT OR
OSC IN Input Current
±2
µA
OSC SEL Input Pull-Up Current
OSC IN Frequency Range
OSC IN Frequency with External Capacitor
5
µA
kHz
kHz
0
250
OSC SEL = 0 V
OSC SEL = 0 V, COSC = 47 pF
4
NOT E
1WDI is a three level input which is internally biased to 38% of VCC and has an input impedance of approximately 125 kΩ.
Specifications subject to change without notice.
ABSO LUTE MAXIMUM RATINGS*
O RD ERING GUID E
(T A = +25°C unless otherwise noted)
Model
Tem perature Range
P ackage O ption
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
VBAT T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
All Other Inputs . . . . . . . . . . . . . . . . . . –0.3 V to VOUT + 0.5 V
Input Current
ADM690AN
ADM690AQ
ADM690SQ
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
N-8
Q-8
Q-8
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
VBAT T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Power Dissipation, N-8 DIP . . . . . . . . . . . . . . . . . . . . 400 mW
ADM691AN
ADM691AR
ADM691AQ
ADM691SQ
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
N-16
R-16
Q-16
Q-16
ADM692AN
ADM692AQ
ADM692SQ
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
N-8
Q-8
Q-8
θ
JA T hermal Impedance . . . . . . . . . . . . . . . . . . . . . 120°C/W
Power Dissipation, Q-8 DIP . . . . . . . . . . . . . . . . . . . . 500 mW
JA T hermal Impedance . . . . . . . . . . . . . . . . . . . . . 125°C/W
Power Dissipation, N-16 DIP . . . . . . . . . . . . . . . . . . . 600 mW
JA T hermal Impedance . . . . . . . . . . . . . . . . . . . . . 135°C/W
Power Dissipation, Q-16 DIP . . . . . . . . . . . . . . . . . . . 600 mW
JA T hermal Impedance . . . . . . . . . . . . . . . . . . . . . 100°C/W
Power Dissipation, R-16 SOIC . . . . . . . . . . . . . . . . . . 600 mW
JA T hermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W
θ
ADM693AN
ADM693AR
ADM693AQ
ADM693SQ
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
N-16
R-16
Q-16
Q-16
θ
θ
ADM694AN
ADM694AQ
ADM694SQ
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
N-8
Q-8
Q-8
θ
Operating T emperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead T emperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
Storage T emperature Range . . . . . . . . . . . . . –65°C to +150°C
ADM695AN
ADM695AR
ADM695AQ
ADM695SQ
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
N-16
R-16
Q-16
Q-16
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum ratings for extended periods of time may affect device reliability.
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADM690–ADM695 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. T herefore,
proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–3–
ADM690–ADM695
P IN FUNCTIO N D ESCRIP TIO N
Mnem onic
Function
VCC
Power Supply Input: +5 V Nominal.
VBAT T
VOUT
Backup Battery Input. Connect to Ground if a backup battery is not used.
Output Voltage, VCC or VBAT T is internally switched to VOUT depending on which is at the highest potential. VOUT
can supply up to 100 mA to power CMOS RAM. Connect VOUT to VCC if VOUT and VBAT T are not used.
GND
0 V. Ground reference for all signals.
RESET
Logic Output. RESET goes low if
1. VCC falls below the Reset T hreshold
2. VCC falls below VBAT T
3. T he watchdog timer is not serviced within its timeout period.
T he reset threshold is typically 4.65 V for the ADM690/ADM691/ADM694/ADM695 and 4.4 V for the ADM692 and
ADM693. RESET remains low for 50 ms (ADM690/ADM691/ADM692/ADM693) or 200 ms (ADM694/ADM695)
after VCC returns above the threshold. RESET also goes low for 50 (200) ms if the watchdog timer is enabled but not
serviced within its timeout period. T he RESET pulse width can be adjusted on the ADM691/ADM693/ADM695 as
shown in T able I. T he RESET output has an internal 3 µA pull up, and can either connect to an open collector
Reset bus or directly drive a CMOS gate without an external pull-up resistor.
WDI
Watchdog Input. WDI is a three level input. If WDI remains either high or low for longer than the watchdog timeout
period, RESET pulses low and WDO goes low. T he timer resets with each transition on the WDI line. T he watchdog
timer may be disabled if WDI is left floating or is driven to midsupply.
PFI
Power Fail Input. PFI is the noninverting input to the Power Fail Comparator when PFI is less than 1.3 V, PFO
goes low. Connect PFI to GND or VOUT when not used.
PFO
Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI is less than 1.3 V. T he
comparator is turned off and PFO goes low when VCC is below VBAT T
.
CEIN
Logic Input. T he input to the CE gating circuit. Connect to GND or VOUT if not used.
CEOUT
Logic Output. CEOUT is a gated version of the CEIN signal. CEOUT tracks CEIN when VCC is above the reset
threshold. If VCC is below the reset threshold, CEOUT is forced high. See Figures 5 and 6.
BAT T ON
Logic Output. BAT T ON goes high when VOUT is internally switched to the VBAT T input. It goes low when VOUT
is internally switched to VCC. T he output typically sinks 35 mA and can directly drive the base of an external
PNP transistor to increase the output current above the 100 mA rating of VOUT
.
LOW LINE Logic Output. LOW LINE goes low when VCC falls below the reset threshold. It returns high as soon as VCC rises
above the reset threshold.
RESET
Logic Output. RESET is an active high output. It is the inverse of RESET.
OSC SEL
Logic Oscillator Select Input. When OSC SEL is unconnected (floating) or driven high, the internal oscillator sets
the reset active time and watchdog timeout period. When OSC SEL is low, the external oscillator input, OSC IN,
is enabled. OSC SEL has a 3 µA internal pull up, (see T able I).
OSC IN
Oscillator Logic Input. With OSC SEL low, OSC IN can be driven by an external clock signal or an external
capacitor can be connected between OSC IN and GND. T his sets both the reset active pulse timing and the watch-
dog timeout period (see T able I and Figure 4). With OSC SEL high or floating, the internal oscillator is enabled
and the reset active time is fixed at 50 ms typ. (ADM691/ADM693) or 200 ms typ (ADM695). In this mode the
OSC IN pin selects between fast (100 ms) and slow (1.6 s) watchdog timeout periods. In both modes, the timeout
period immediately after a reset is 1.6 s typical.
WDO
Logic Output. T he Watchdog Output, WDO, goes low if WDI remains either high or low for longer than the
watchdog timeout period. WDO is set high by the next transition at WDI. If WDI is unconnected or at midsupply,
the watchdog timer is disabled and WDO remains high. WDO also goes high when LOW LINE goes low.
–4–
REV. A
ADM690–ADM695
P IN CO NFIGURATIO NS
V
1
2
3
4
5
6
7
8
RESET
16
BATT
V
15 RESET
OUT
ADM691
ADM693
ADM695
V
14
13
12
WDO
V
OUT
1
8
7
V
CC
ADM690
ADM692
ADM694
BATT
GND
BATT ON
LOW LINE
OSC IN
V
CE
IN
RESET
WDI
2
3
CC
TOP VIEW
(Not to Scale)
CE
GND
PFI
6
5
OUT
TOP VIEW
(Not to Scale)
11 WDI
10 PFO
PFO
4
OSC SEL
9
PFI
P RO D UCT SELECTIO N GUID E
P art
Num ber
Nom inal Reset
Tim e
Nom inal VCC
Reset Threshold
Nom inal Watchdog
Tim eout P eriod
Battery Backup
Switching
Base D rive
Ext P NP
Chip Enable
Signals
ADM690
ADM691
ADM692
ADM693
ADM694
ADM695
50 ms
50 ms or ADJ
50 ms
50 ms or ADJ
200 ms
200 ms or ADJ
4.65 V
4.65 V
4.4 V
4.4 V
4.65 V
4.65 V
1.6 s
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
100 ms, 1.6 s, ADJ
1.6 s
100 ms, 1.6 s, ADJ
1.6 s
100 ms, 1.6 s, ADJ
CIRCUIT INFO RMATIO N
Batter y Switchover Section
If the continuous output current requirement at VOUT exceeds
100 mA or if a lower VCC–VOUT voltage differential is desired,
an external PNP pass transistor may be connected in parallel
with the internal transistor. T he BAT T ON output (ADM691/
ADM693/ADM695) can directly drive the base of the external
transistor.
T he battery switchover circuit compares VCC to the VBAT T
input, and connects VOUT to whichever is higher. Switchover
occurs when VCC is 50 mV higher than VBAT T as VCC falls, and
when VCC is 70 mV greater than VBAT T as VCC rises. T his
20 mV of hysteresis prevents repeated rapid switching if VCC
falls very slowly or remains nearly equal to the battery voltage.
A 20 Ω MOSFET switch connects the VBAT T input to VOUT
during battery backup. T his MOSFET has very low input-to-
output differential (dropout voltage) at the low current levels
required for battery back up of CMOS RAM or other low
power CMOS circuitry. T he supply current in battery back up
is typically 0.6 µA.
T he ADM690/ADM691/ADM694/ADM695 operates with
battery voltages from 2.0 V to 4.25 V and the ADM692/ADM693
operates with battery voltages from 2.0 V to 4.0 V. High value
capacitors, either standard electrolytic or the farad size double
layer capacitors, can also be used for short-term memory back
up. A small charging current of typically 10 nA (0.1 µA max)
flows out of the VBAT T terminal. T his current is useful for
maintaining rechargeable batteries in a fully charged condition.
T his extends the life of the back up battery by compensating
for its self discharge current. Also note that this current poses
no problem when lithium batteries are used for back up since
the maximum charging current (0.1 µA) is safe for even the
smallest lithium cells.
Figure 1. Battery Switchover Schem atic
During normal operation with VCC higher than VBAT T, VCC is in-
ternally switched to VOUT via an internal PMOS transistor
switch. T his switch has a typical on-resistance of 1.5 Ω and can
supply up to 100 mA at the VOUT terminal. VOUT is normally
used to drive a RAM memory bank which may require instanta-
neous currents of greater than 100 mA. If this is the case then a
bypass capacitor should be connected to VOUT . T he capacitor
will provide the peak current transients to the RAM. A capaci-
tance value of 0.1 µF or greater may be used.
If the battery-switchover section is not used, VBAT T should be
connected to GND and VOUT should be connected to VCC
.
REV. A
–5–
ADM690–ADM695
P O WER FAIL RESET O UTP UT
Watchdog Tim er RESET
RESET is an active low output which provides a RESET signal
to the Microprocessor whenever VCC is at an invalid level. When
VCC falls below the reset threshold, the RESET output is forced
low. T he nominal reset voltage threshold is 4.65 V (ADM690/
ADM691/ADM694/ADM695) or 4.4 V (ADM692/ADM693).
T he watchdog timer circuit monitors the activity of the micro-
processor in order to check that it is not stalled in an indefinite
loop. An output line on the processor is used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within the
selected timeout period, a RESET pulse is generated. T he
nominal watchdog timeout period is preset at 1.6 seconds on the
ADM690/ADM692/ADM694. The ADM691/ADM693/ADM695
may be configured for either a fixed “short” 100 ms or a “long”
1.6 second timeout period or for an adjustable timeout period.
If the “short” period is selected, some systems may be unable to
service the watchdog timer immediately after a reset, so the
ADM691/ADM693/ADM695 automatically selects the “long”
timeout period directly after a reset is issued. T he watchdog
timer is restarted at the end of reset, whether the reset was
caused by lack of activity on WDI or by VCC falling below the
reset threshold.
V
V2
V2
CC
V1
V1
t1
t
1
RESET
LOW LINE
t1 = RESET TIME.
T he normal (short) timeout period becomes effective following
the first transition of WDI after RESET has gone inactive. T he
watchdog timeout period restarts with each transition on the
WDI pin. T o ensure that the watchdog timer does not time out,
either a high-to-low or low-to-high transition on the WDI pin
must occur at or less than the minimum timeout period. If WDI
remains permanently either high or low, reset pulses will be
issued after each “long” timeout period (1.6 s). T he watchdog
monitor can be deactivated by floating the Watchdog Input
(WDI) or by connecting it to midsupply.
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1
Figure 2. Power Fail Reset Tim ing
On power-up RESET will remain low for 50 ms (200 ms for
ADM694 and ADM695) after VCC rises above the appropriate
reset threshold. T his allows time for the power supply and mi-
croprocessor to stabilize. On power-down, the RESET output
remains low with VCC as low as 1 V. T his ensures that the
microprocessor is held in a stable shutdown condition.
WDI
T his RESET active time is adjustable on the ADM691/ADM693/
ADM695 by using an external oscillator or by connecting an
external capacitor to the OSC IN pin. Refer to T able I and
Figure 4.
WDO
T he guaranteed minimum and maximum thresholds of the
ADM690/ADM691/ADM694/ADM695 are 4.5 V and 4.73 V,
while the guaranteed thresholds of the ADM692/ADM693 are
4.25 V and 4.48 V. The ADM690/ADM691/ADM694/ADM695
is, therefore, compatible with 5 V supplies with a +10%, –5%
tolerance while the ADM692/ADM693 is compatible with 5 V
± 10% supplies. T he reset threshold comparator has approxi-
mately 50 mV of hysteresis. T he response time of the reset volt-
age comparator is less than 1 µs. If glitches are present on the
VCC line which could cause spurious reset pulses, then VCC
should be decoupled close to the device.
t2
t3
RESET
t1
t1
t1
t
t
t
1 = RESET TIME.
2 = NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD.
3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET.
In addition to RESET the ADM691/ADM693/ADM695 con-
tain an active high RESET output. T his is the complement of
RESET and is intended for processors requiring an active high
RESET signal.
Figure 3. Watchdog Tim eout Period and Reset Active
Tim e
–6–
REV. A
ADM690–ADM695
Table I. AD M691, AD M693, AD M695 Reset P ulse Width and Watchdog Tim eout Selections
Watchdog Tim eout P eriod
Im m ediately
Reset Active P eriod
O SC SEL
O SC IN
Norm al
After Reset
AD M691/AD M693
AD M695
Low
Low
External Clock Input
External Capacitor
1024 CLKS
260 ms × C/47 pF 1.04 s × C/47 pF
100 ms
1.6 s
4096 CLKS
512 CLKS
130 ms × C/47 pF
50 ms
2048 CLKS
520 ms × C/47 pF
200 ms
Floating or High Low
Floating or High Floating or High
1.6 s
1.6 s
50 ms
200 ms
NOT E
With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor can be connected between OSC IN and GND. T he nominal
internal oscillator frequency is 10.24 kHz. T he nominal oscillator frequency with external capacitor is: F OSC (Hz) = 184,000/C (pF).
T he watchdog timeout period is fixed at 1.6 seconds, and the
reset pulse width is fixed at 50 ms on the ADM690/ADM692.
8
OSC SEL
On the ADM694 the watchdog timeout period is also 1.6 sec-
ADM691
onds but the reset pulse width is fixed at 200 ms. The ADM691/
ADM693/ADM695 allow these times to be adjusted as shown
in T able I. Figure 4 shows the various oscillator configurations
which can be used to adjust the reset pulse width and watchdog
timeout period.
ADM693
ADM695
7
OSC IN
COSC
T he internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects between the 1.6 second
and 100 ms watchdog timeout periods. With OSC IN connected
high or floating, the 1.6 second timeout period is selected; while
with it connected low, the 100 ms timeout period is selected. In
either case, immediately after a reset, the timeout period is 1.6
seconds. T his gives the microprocessor time to reinitialize the
system. If OSC IN is low, then the 100 ms watchdog period be-
comes effective after the first transition of WDI. T he software
should be written such that the I/O port driving WDI is left in
its power-up reset state until the initialization routines are com-
pleted and the microprocessor is able to toggle WDI at the mini-
mum watchdog timeout period of 70 ms.
Figure 4b. External Capacitor
8
NC
NC
OSC SEL
ADM691
ADM693
ADM695
7
OSC IN
Watchdog O utput (WD O )
Figure 4c. Internal Oscillator (1.6 Second Watchdog)
T he Watchdog Output WDO (ADM691/ADM693/ADM695)
provides a status output which goes low if the watchdog timer
“times out” and remains low until set high by the next transition
on the Watchdog Input. WDO is also set high when VCC goes
below the reset threshold.
8
NC
OSC SEL
ADM691
ADM693
ADM695
8
OSC SEL
ADM691
ADM693
ADM695
7
OSC IN
CLOCK
0 TO 250kHz
7
OSC IN
Figure 4d. Internal Oscillator (100 m s Watchdog)
Figure 4a. External Clock Source
REV. A
–7–
ADM690–ADM695
CE Gating and RAM Wr ite P r otection (AD M691/AD M693/
AD M695)
P ower Fail War ning Com par ator
An additional comparator is provided for early warning of failure
in the microprocessor’s power supply. T he Power Fail Input
(PFI) is compared to an internal +1.3 V reference. T he Power
Fail Output (PFO) goes low when the voltage at PFI is less than
1.3 V. T ypically PFI is driven by an external voltage divider
which senses either the unregulated dc input to the system’s 5 V
regulator or the regulated 5 V output. T he voltage divider ratio
can be chosen such that the voltage at PFI falls below 1.3 V sev-
eral milliseconds before the +5 V power supply falls below the
reset threshold. PFO is normally used to interrupt the micropro-
cessor so that data can be stored in RAM and the shut down
procedure executed before power is lost
T he ADM691/ADM693/ADM695 products include memory
protection circuitry which ensures the integrity of data in mem-
ory by preventing write operations when VCC is at an invalid
level. T here are two additional pins, CEIN and CEOUT , which
may be used to control the Chip Enable or Write inputs of
CMOS RAM. When VCC is present, CEOUT is a buffered replica
of CEIN, with a 5 ns propagation delay. When VCC falls below
the reset voltage threshold or VBAT T , an internal gate forces
CEOUT high, independent of CEIN
.
CEOUT typically drives the CE, CS, or write input of battery
backed up CMOS RAM. T his ensures the integrity of the data
in memory by preventing write operations when VCC is at an in-
valid level. Similar protection of EEPROMs can be achieved by
using the CEOUT to drive the store or write inputs.
INPUT
POWER
R
1
If the 5 ns typical propagation delay of CEOUT is excessive, con-
nect CEIN to GND and use the resulting CEOUT to control a
high speed external logic gate.
1.3V
PFO
POWER
FAIL
OUTPUT
POWER
FAIL
INPUT
R
ADM69x
2
ADM69x
CE
IN
CE
OUT
V
V
LOW = 0
OK = 1
CC
CC
Figure 7. Power Fail Com parator
Table II. Input and O utput Status In Battery Backup Mode
Signal
Status
Figure 5. Chip Enable Gating
VOUT
VOUT is connected to VBAT T via an internal
PMOS switch.
V
V2
V2
CC
V1
V1
RESET
Logic low.
t1
t
1
RESET
RESET
Logic high. T he open circuit output voltage is
equal to VOUT
.
LOW LINE
Logic low.
LOW LINE
BAT T ON
Logic high. T he open circuit voltage is equal to
VOUT.
WDI
WDI is ignored. It is internally disconnected
from the internal pull-up resistor and does not
source or sink current as long as its input voltage
is between GND and VOUT . T he input voltage
does not affect supply current.
CE
IN
WDO
Logic high. T he open circuit voltage is equal
to VOUT
.
CE
OUT
PFI
T he Power Fail Comparator is turned off and
has no effect on the Power Fail Output.
t1 = RESET TIME.
PFO
CEIN
Logic low.
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1
CEIN is ignored. It is internally disconnected
from its internal pull-up and does not source or
sink current as long as its input voltage is
between GND and VOUT . T he input voltage
does not affect supply current.
Figure 6. Chip Enable Tim ing
CEOUT
Logic high. T he open circuit voltage is equal to
VOUT
.
OSC IN
OSC IN is ignored.
OSC SEL is ignored.
OSC SEL
–8–
REV. A
Typical Performance Curves–ADM690–ADM695
5.00
2.80
V
T
= 5V
= +25°C
CC
V
V
T
= 0V
= +2.8V
= +25°C
A4
3.36 V
A
CC
BATT
100
90
4.95
4.90
4.85
2.79
2.78
A
SLOPE = 1.5Ω
SLOPE = 20Ω
10
2.77
2.76
0%
1V
1V
500ms
4.80
0
20
40
60
80
100
0
200
400
600
800
1000
I
– µA
I
– mA
OUT
OUT
Figure 10. Reset Output Voltage vs.
Supply Voltage
Figure 9. VOUT vs. IOUT Battery
Backup
Figure 8. VOUT vs. IOUT Norm al
Operation
4.70
1.303
53
V
= +5V
CC
V
= +5V
CC
4.68
4.66
1.302
1.301
52
51
POWER-UP
ADM690
ADM691
ADM694
ADM695
ADM690
ADM691
ADM692
4.64
4.62
1.300
1.299
50
49
ADM693
POWER-DOWN
20
40
60
80
100
120
20
40
60
80
100
120
20
40
60
80
100
120
TEMPERATURE – °C
TEMPERATURE –
°C
TEMPERATURE –
°C
Figure 13. Reset Voltage Threshold
vs. Tem perature
Figure 12. Reset Active Tim e vs.
Tem perature
Figure 11. PFI Input Threshold vs.
Tem perature
6
6
6
VCC = 5V
A = +25
VCC = 5V
5
V
T
= 5V
= +25°C
CC
5
4
5
T
°
C
TA = +25°C
A
4
4
+5V
3
2
3
2
3
2
VPFI
1.3V
PFO
V
10k
PFI
30pF
VPFI
PFO
1
0
1.3V
1
0
PFO
1
0
30pF
1.3V
30pF
1.35
1.25
0
1.35
1.25
1.35
1.25
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
0
10 20 30 40 50 60 70 80 90
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
TIME – µs
TIME – µs
TIME – µs
Figure 16. Power Fail Com parator
Response Tim e with Pull-Up Resistor
Figure 15. Power Fail Com parator
Response Tim e
Figure 14. Power Fail Com parator
Response Tim e
REV. A
–9–
ADM690–ADM695
+AP P LICATIO N INFO RMATIO N
Incr easing the D r ive Cur r ent
When PFO is low, resistor R3 sinks current from the summing
junction at the PFI pin. When PFO is high, the series combina-
tion of R3 and R4 source current into the PFI summing junc-
tion. T his results in differing trip levels for the comparator.
If the continuous output current requirements at VOUT exceed
100 mA or if a lower VCC–VOUT voltage differential is desired,
an external PNP pass transistor may be connected in parallel
with the internal transistor. T he BAT T ON output (ADM691/
ADM693/ADM695) can directly drive the base of the external
transistor.
+5V
7805
+7V TO +15V
INPUT
V
POWER
CC
R
4
R
1
2
1.3V
PNP TRANSISTOR
PFO
+5V
TO
µP NMI
INPUT
POWER
0.1µF
0.1µF
PFI
R
ADM69x
BATT
ON
V
OUT
V
CC
R
3
V
BATT
ADM691
ADM693
ADM695
BATTERY
5V
Figure 17. Increasing the Drive Current
PFO
Using a Rechar geable Batter y for Back Up
If a capacitor or a rechargeable battery is used for back up then
the charging resistor should be connected to VOUT since this
eliminates the discharge path that would exist during power
0V
V
V
H
0V
L
V
IN
down if the resistor is connected to VCC
.
R
1
R
1
V
H
= 1.3V
= 1.3V
(
1+ ––– + –––
)
R
R
VOUT – VBATT
3
2
I =
R
+5V
INPUT
POWER
R
(5V – 1.3V)
R
1
1
V
L
(
1+ ––– – –––––––––––––
)
0.1µF
R
1.3V (R R )
2
3 +
4
R
0.1µF
ASSUMING R < <
R THEN
3
4
R
1
HYSTERESIS V – V = 5V
(
–––
)
H
L
R
2
V
V
OUT
CC
V
BATT
Figure 19. Adding Hysteresis to the Power Fail Com parator
RECHARGEABLE
BATTERY
ADM69x
Monitor ing the Status of the Batter y
T he power fail comparator can be used to monitor the status of
the backup battery instead of the power supply if desired. T his
is shown in Figure 20. T he PFI input samples the battery volt-
age and generates an active low PFO signal when the battery
voltage drops below a chosen threshold. It may be necessary to
apply a test load in order to determine the loaded battery volt-
age. T his can be done under processor control using CEOUT .
Since CEOUT is forced high during the battery backup mode, the
test load will not be applied to the battery while it is in use, even
if the microprocessor is not powered.
Figure 18. Rechargeable Battery
Adding H yster esis to the P ower Fail Com par ator
For increased noise immunity, hysteresis may be added to the
power fail comparator. Since the comparator circuit is nonin-
verting, hysteresis can be added simply by connecting a resistor be-
tween the PFO output and the PFI input as shown in Figure 19.
–10–
REV. A
ADM690–ADM695
+5V INPUT
POWER
CONTROL
INPUT*
OSC SEL
V
V
CC
BATT
PFO
ADM69x
D1
D2
LOW BATTERY
SIGNAL TO
µP I/O PIN
10MΩ
10MΩ
BATTERY
ADM69x
PFI
OSC IN
CE
IN
20kΩ
OPTIONAL
TEST LOAD
FROM µP I/O PIN
APPLIES TEST LOAD
TO BATTERY
CE
OUT
*LOW = INTERNAL TIMEOUT
HIGH = EXTERNAL TIMEOUT
Figure 21b. Program m ing the Watchdog Input
Figure 20. Monitoring the Battery Status
Replacing the Backup Batter y
Alter nate Watchdog Input D r ive Cir cuits
When changing the backup battery with system power on, spuri-
ous resets can occur when the battery is removed. T his occurs
because the leakage current flowing out of the VBAT T pin will
charge up the stray capacitance. If the voltage on VBAT T reaches
within 50 mV of VCC, a reset pulse is generated.
T he watchdog feature can be enabled and disabled under pro-
gram control by driving WDI with a 3-state buffer (Figure 21a).
When three-stated, the WDI input will float thereby disabling
the watchdog timer.
WATCHDOG
STROBE
WDI
If spurious resets during battery replacement are acceptable,
then no action is required. If not, then one of the following
solutions should be considered:
ADM69x
CONTROL
INPUT
1. A capacitor from VBAT T to GND. T his gives time while the
capacitor is charging up to replace the battery. T he leakage
current will charge up the external capacitor towards the VCC
level. T he time taken is related to the charging current, the
size of external capacitor and the voltage differential between
the capacitor and the charging voltage supply.
Figure 21a. Program m ing the Watchdog Input
T his circuit is not entirely foolproof, and it is possible that a
software fault could erroneously 3-state the buffer. T his would
then prevent the ADM69x from detecting that the microproces-
sor is no longer operating correctly. In most cases a better
method is to extend the watchdog period rather than disabling
the watchdog. T his may be done under program control using
the circuit shown in Figure 21b. When the control input is high,
the OSC SEL pin is low and the watchdog timeout is set by the
external capacitor. A 0.01 µF capacitor sets a watchdog timeout
delay of 100 seconds. When the control input is low, the OSC
SEL pin is driven high, selecting the internal oscillator. T he
100 ms or the 1.6 s period is chosen, depending on which diode
in Figure 21b is used. With D1 inserted the internal timeout is
set at 100 ms, while with D2 inserted the timeout is set at 1.6 s.
t = CEXT × VDIFF/I
T he maximum leakage (charging) current is 1 µA over tem-
perature and VDIFF = VCC–VBAT T. T herefore, the capacitor
size should be chosen such that sufficient time is available to
make the battery replacement.
CEXT = TREQD (1 µA/(VCC–VBATT))
If a replacement time of 5 seconds is allowed and assuming a
VCC of 4.5 V and a VBAT T of 3 V
CEXT = 3.33 µF
VBATT
CEXT
BATTERY
ADM69x
Figure 22a. Preventing Spurious RESETS During
Battery Replacem ent
2. A resistor from VBAT T to GND. T his will prevent the voltage
on VBAT T from rising to within 50 mV of VCC during battery
replacement.
REV. A
–11–
ADM690–ADM695
R =(VCC – 50 mV)/1 µA
+5V
Note that the resistor will discharge the battery slightly. With a
VCC supply of 4.5 V, a suitable resistor is 4.3 MΩ. With a 3 V
battery this will draw around 700 nA. T his will be negligible in
most cases.
R1
VCC
µP POWER
CMOS RAM
VOUT
PFI
POWER
ADM690
ADM692
ADM694
0.1µF
µP SYSTEM
R2
V
BATT
µP RESET
µP NMI
RESET
PFO
BATTERY
R
VBATT
+
ADM69x
BATTERY
I/O LINE
WDI
GND
Figure 23a. ADM690/ADM692/ADM694 Typical Application
Circuit A
Figure 22b. Preventing Spurious RESETS During Battery
Replacem ent
Figure 23b shows a similar application but in this case the PFI
input monitors the unregulated input to the 7805 voltage regu-
lator. T his gives an earlier warning of an impending power fail-
ure. It is useful with processors operating at low speeds or
TYP ICAL AP P LICATIO NS
AD M690, AD M692 AND AD M694
Figure 23 shows the ADM690/ADM692/ADM694 in a typical
power monitoring, battery backup application. VOUT powers the
CMOS RAM. Under normal operating conditions with VCC
present, VOUT is internally connected to VCC. If a power failure
occurs, VCC will decay and VOUT will be switched to VBAT T
thereby maintaining power for the CMOS RAM. A RESET
pulse is also generated when VCC falls below 4.65 V for the
ADM690/ADM694 or 4.4 V for the ADM692. RESET will
remain low for 50 ms (200 ms for ADM694) after VCC returns
to 5 V.
where there are a significant number of housekeeping tasks to be
completed before the power is lost.
+5V
7805
INPUT
POWER
V > 8V
0.1µF
R
1
2
V
µP POWER
CMOS RAM
CC
V
OUT
PFI
POWER
ADM690
ADM692
ADM694
0.1µF
µP SYSTEM
R
T he watchdog timer input (WDI) monitors an I/O line from the
µP system. T his line must be toggled once every 1.6 seconds to
verify correct software execution. Failure to toggle the line indi-
cates that the µP system is not correctly executing its program
and may be tied up in an endless loop. If this happens, a reset
pulse is generated to initialize the processor.
µP RESET
µP NMI
RESET
V
BATT
PFO
BATTERY
I/O LINE
WDI
GND
If the watchdog timer is not needed, the WDI input should be
left floating.
Figure 23b. ADM690/ADM692/ADM694 Typical Application
Circuit B
T he Power Fail Input, PFI, monitors the input power supply via
a resistive divider network. T he voltage on the PFI input is com-
pared with a precision 1.3 V internal reference. If the input volt-
age drops below 1.3 V, a power fail output (PFO) signal is
generated. T his warns of an impending power failure and may
be used to interrupt the processor so that the system may be
shut down in an orderly fashion. T he resistors in the sensing
network are ratioed to give the desired power fail threshold
voltage VT .
AD M691, AD M693, AD M695
A typical connection for the ADM691/ADM693/ADM695 is
shown in Figure 24. CMOS RAM is powered from VOUT . When
5 V power is present this is routed to VOUT . If VCC fails then
VBAT T is routed to VOUT . VOUT can supply up to 100 mA from
VCC, but if more current is required, an external PNP transistor
can be added. When VCC is higher than VBAT T , the BAT T ON
output goes low, providing up to 25 mA of base drive for the
external transistor. A 0.1 µF capacitor is connected to VOUT to
supply the transient currents for CMOS RAM. When VCC is
lower than VBAT T , an internal 20 Ω MOSFET connects the
VT = (1.3 R1/R2) + 1.3 V
R1/R2 = (VT/1.3) – 1
backup battery to VOUT
.
–12–
REV. A
ADM690–ADM695
INPUT POWER
+5V
RAM Wr ite P r otection
T he ADM691/ADM693/ADM695 CEOUT line drives the Chip
Select inputs of the CMOS RAM. CEOUT follows CEIN as long
as VCC is above the 4.65 V (4.4 V for ADM693) reset threshold.
0.1µF
0.1µF
V
V
BATT
ON
OUT
CC
CMOS
RAM
If VCC falls below the reset threshold, CEOUT goes high, inde-
pendent of the logic level at CEIN. T his prevents the micropro-
cessor from writing erroneous data into RAM during power-up,
power-down, brownouts and momentary power interruptions.
3V
BATTERY
V
CE
BATT
OUT
R
1
ADM691
ADM693
ADM695
ADDRESS
DECODE
CE
IN
PFI
A0–A15
I/O LINE
GND
Watchdog Tim er
WDI
PFO
R
2
T he microprocessor drives the Watchdog Input (WDI) with an
I/O line. When OSC IN and OSC SEL are unconnected, the
microprocessor must toggle the WDI pin once every 1.6 sec-
onds to verify proper software execution. If a hardware or soft-
ware failure occurs such that WDI not toggled, the ADM691/
ADM693 will issue a 50 ms (200 ms for ADM695) RESET
pulse after 1.6 seconds. T his typically restarts the micro-
processor’s power-up routine. A new RESET pulse is issued
every 1.6 seconds until WDI is again strobed. If a different
watchdog timeout period is required, then a capacitor should be
connected to OSC IN or an external clock may be used. Please
refer to T able I and Figure 4.
OSC IN
µP
NC
NMI
OSC SEL
RESET
RESET
LOW LINE WDO
RESET
0.1µF
SYSTEM STATUS
INDICATORS
Figure 24. ADM691/ADM693/ADM695 Typical Application
Reset O utput
T he internal voltage detector monitors VCC and generates a
RESET output to hold the microprocessor’s Reset line low
when VCC is below 4.65 V (4.4 V for ADM693). An internal
timer holds RESET low for 50 ms (200 ms for the ADM695)
after VCC rises above 4.65 V (4.4 V for ADM693). T his prevents
repeated toggling of RESET even if the 5 V power drops out
and recovers with each power line cycle.
T he WAT CHDOG OUT PUT (WDO) goes low if the watch-
dog timer is not serviced within its timeout period. Once WDO
goes low, it remains low until a transition occurs at WDI. T he
watchdog timer feature can be disabled by leaving WDI
unconnected.
T he crystal oscillator normally used to generate the clock for mi-
croprocessors can take several milliseconds to stabilize. Since
most microprocessors need several clock cycles to reset, RESET
must be held low until the microprocessor clock oscillator has
started. T he power-up RESET pulse lasts 50 ms (200 ms for the
ADM695) to allow for this oscillator start-up time. If a different
reset pulse width is required, then a capacitor should be con-
nected to OSC IN or an external clock may be used. Please refer
to T able I and Figure 4. T he manual reset switch and the 0.1 µF
capacitor connected to the reset line can be omitted if a manual
reset is not needed. An inverted, active high, RESET output is
also available.
T he RESET output has an internal 3 µA pull-up, and can either
connect to an open collector reset bus or directly drive a CMOS
gate without an external pull-up resistor.
P ower Fail D etector
T he +5 V VCC power line is monitored via a resistive potential
divider connected to the Power Fail Input (PFI). When the
voltage at PFI falls below 1.3 V, the Power Fail Output (PFO)
drives the processor’s NMI input low. If for example a Power
Fail threshold of 4.8 V is set with resistors R1 and R2, the micro-
processor will have the time when VCC falls from 4.8 V to 4.65 V
to save data into RAM. An earlier power fail warning can be
generated if the unregulated dc input to the 5 V regulator is
available for monitoring. T his will allow more time for micro-
processor housekeeping tasks to be completed before power is
lost.
REV. A
–13–
ADM690–ADM695
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
8-P in P lastic D IP (N-8)
8
5
0.280 (7.11)
0.240 (6.10)
PIN 1
1
4
0.325 (8.25)
0.300 (7.62)
0.430 (10.92)
0.348 (8.84)
0.060 (1.52)
0.015 (0.38)
0.195 (4.95)
0.115 (2.93)
0.210
(5.33)
MAX
0.150
(3.81)
MIN
0.015 (0.381)
0.008 (0.204)
0.160 (4.06)
0.115 (2.93)
SEATING
PLANE
0.100
(2.54)
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
BSC
16-Lead P lastic D IP (N-16)
16
1
9
0.280 (7.11)
0.240 (6.10)
PIN 1
8
0.325 (8.25)
0.300 (7.62)
0.840 (21.33)
0.745 (18.93)
0.060 (1.52)
0.015 (0.38)
0.195 (4.95)
0.115 (2.93)
0.210
(5.33)
0.150
(3.81)
0.200 (5.05)
0.125 (3.18)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
8-P in Cerdip (Q-8)
5
8
0.310 (7.87)
0.220 (5.59)
PIN 1
1
4
0.320 (8.13)
0.420 (10.67)
MAX
0.290 (7.37)
0.060 (1.52)
0.015 (0.38)
0.200
(5.08)
MAX
0.150
(3.81)
MIN
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.100 (2.54)
BSC
0.070 (1.78)
0.30 (0.76)
–14–
REV. A
ADM690–ADM695
16-Lead Cerdip (Q-16)
9
16
0.310 (7.87)
0.220 (5.59)
PIN 1
1
8
0.320 (8.13)
0.290 (7.37)
0.840 (21.34) MAX
0.060 (1.52)
0.015 (0.38)
0.200
(5.08)
MAX
0.150
(3.81)
MIN
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.100 (2.54)
BSC
0.070 (1.78)
0.30 (0.76)
16-Lead SO IC (R-16)
16
9
0.419
(10.65)
0.299
(7.60)
1
8
0.030
(0.75)
0.413 (10.50)
0.012
(0.3)
0.104
(2.65)
0.042
(1.07)
0.05 (1.27)
REF
0.019 (0.49)
0.013
(0.32)
REV. A
–15–
–16–
相关型号：
ADM690AARM-REEL
IC 3-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, MICRO, SOIC-8, Power Management Circuit
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ADM690AARMZ-REEL
µP Supervisor with Backup Battery Switchover, Watchdog Feature, Power Fail Warning, 4.65V Threshold Voltage, Active Low Reset
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