ADM8324WAH29ARJZR7 [ADI]
Supervisory Circuit with Windowed Watchdog, Manual Reset, and Active-Low Open-Drain Reset Output;
| 型号： | ADM8324WAH29ARJZR7 |
| 厂家： | 
ADI |
| 描述： | Supervisory Circuit with Windowed Watchdog, Manual Reset, and Active-Low Open-Drain Reset Output 光电二极管 |
| 文件： | 总16页 (文件大小：279K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Supervisory Circuits with Windowed
Watchdog and Manual Reset in 5-Lead SOT-23
Data Sheet
ADM8323/ADM8324
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Windowed watchdog, 8 timeout options
26 reset threshold options
ADM8323
V
CC
2.5 V to 5 V in 100 mV increments
4 reset timeout options
1 ms, 20 ms, 140 ms, and 1120 ms (minimum)
Manual reset input
V
CC
RESET
RESET
GENERATOR
V
REF
DEBOUNCE
MR
RESET
Open-drain or push-pull
Low power consumption
outputs
WINDOWED
WATCHDOG
DETECTOR
Specified over wide temperature range (−40°C to +125°C)
Qualified for automotive applications
5-lead SOT-23 package
GND
WDI
Figure 1.
APPLICATIONS
ADM8324
Automotive
Microprocessor systems
Computers
Controllers
RESET
V
CC
RESET
GENERATOR
V
REF
Intelligent instruments
Portable equipment
MR
DEBOUNCE
WINDOWED
WATCHDOG
DETECTOR
GND
WDI
Figure 2.
GENERAL DESCRIPTION
The ADM8323/ADM8324 are supervisory circuits that monitor
power supply voltage levels and code execution integrity in
microprocessor-based systems. An on-chip watchdog timer checks
for activity within a preset timeout window. A reset signal can also
be asserted by an external push-button switch through a manual
Each device is available in a choice of 26 reset threshold options
from 2.5 V to 5 V in 100 mV increments. There are also four reset
timeout options of 1 ms, 20 ms, 140 ms, and 1120 ms (minimum).
The ADM8323/ADM8324 are available in a 5-lead SOT-23
package and typically consume only 10 μA, making them suitable
for use in low power portable applications.
reset input. The
output is either push-pull (ADM8323)
RESET
or open-drain (ADM8324).
A watchdog failure results in a low output on the
pin. A
RESET
failure can be triggered either by a fast watchdog error (watchdog
pulses too close together) or by a slow watchdog error (no watchdog
pulse within the timeout period). This effectively gives a window
to observe the watchdog pulse. The watchdog timeout is measured
from the last falling edge of the watchdog input (WDI). There are
eight different watchdog windows available, as shown in Table 5.
Rev. A
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ADM8323/ADM8324
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
RESET
Output.......................................................... 10
Push-Pull
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 10
Circuit Description..................................................................... 10
RESET
Open-Drain
Output ..................................................... 10
Manual Reset Input.................................................................... 10
Windowed Watchdog Input...................................................... 10
Applications Information.............................................................. 11
Watchdog Input Current ........................................................... 11
Negative Going VCC Transients................................................. 11
RESET
Ensuring
Valid to VCC = 0 V........................................ 11
Model Options................................................................................ 12
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
Automotive Products................................................................. 14
REVISION HISTORY
3/16—Rev. 0 to Rev. A
10/13—Revision 0: Initial Version
Change to Model Options Section Title...................................... 12
Changes to Table 7.......................................................................... 13
Rev. A | Page 2 of 16
Data Sheet
ADM8323/ADM8324
SPECIFICATIONS
VCC = (VTH + 1.5%) to 5.5 V, TA = −40°C to +125°C, unless otherwise noted. Typical values are at TA = 25°C.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SUPPLY
VCC Operating Voltage Range1
VCC that Guarantees Valid Output
Supply Current
0.9
0.9
5.5
V
10
10
20
18
µA
µA
VCC = 5.5 V, WDI = 0 V
VCC = 3.6 V, WDI = 0 V
TA = 25°C
RESET THRESHOLD VOLTAGE2
VTH
VTH + 1%
VTH + 1.5%
V
VTH − 1%
VTH − 1.5%
VTH
V
TA = −40°C to +125°C
RESET THRESHOLD TEMPERATURE COEFFICIENT
RESET THRESHOLD HYSTERESIS
RESET TIMEOUT PERIOD
20
ppm/°C
mV
2.5 × VTH
See Table 4
Reset Timeout Option A
Reset Timeout Option B
Reset Timeout Option C
Reset Timeout Option D
1
20
140
1120
1.4
28
200
1600
90
1.8
36
260
2080
ms
ms
ms
ms
µs
VCC TO RESET DELAY, tRD
VCC falling at 1 mV/µs
PUSH-PULL OUTPUT (ADM8323)
RESET Output Voltage
0.2
0.2
0.2
0.3
V
V
V
V
V
V
ns
VCC ≥ 0.9 V, ISINK = 25 µA
VCC ≥ 1.2 V, ISINK = 100 µA
VCC ≥ 2.7 V, ISINK = 1.2 mA
VCC ≥ 4.5 V, ISINK = 3.2 mA
VCC ≥ 2.7 V, ISOURCE = 500 µA
VCC ≥ 4.5 V, ISOURCE = 800 µA
From 10% to 90% VCC, CL = 5 pF, VCC = 3.3 V
0.9 × VCC
0.9 × VCC
50
100
RESET Rise Time
OPEN-DRAIN OUTPUT (ADM8324)
RESET Output Voltage
0.2
0.2
0.2
0.3
1
V
VCC ≥ 0.9 V, ISINK = 25 µA
VCC ≥ 1.2 V, ISINK = 100 µA
VCC ≥ 2.7 V, ISINK = 1.2 mA
VCC ≥ 4.5 V, ISINK = 3.2 mA
V
V
V
µA
Open-Drain Reset Output Leakage Current
WATCHDOG INPUT
See Table 5
Watchdog Timeout Period (Fast), tWD-FAST
Watchdog Timeout Option A
Watchdog Timeout Option B
Watchdog Timeout Option C
Watchdog Timeout Option D
Watchdog Timeout Option E
Watchdog Timeout Option F
Watchdog Timeout Option G
Watchdog Timeout Option H
Watchdog Timeout Period (Slow), tWD-SLOW
Watchdog Timeout Option A
Watchdog Timeout Option B
Watchdog Timeout Option C
Watchdog Timeout Option D
Watchdog Timeout Option E
Watchdog Timeout Option F
Watchdog Timeout Option G
Watchdog Timeout Option H
1
1.5
15
15
15
15
24
41
768
ms
ms
ms
ms
ms
ms
ms
ms
10
10
10
10
16
27
512
10
15
ms
ms
ms
sec
sec
ms
ms
sec
100
300
10
60
44
150
450
15
90
66
76
1.24
114
1.86
Rev. A | Page 3 of 16
ADM8323/ADM8324
Data Sheet
Parameter
Min
Typ
Max
Unit
ns
ns
V
µA
µA
Test Conditions/Comments
WDI Pulse Width
WDI Glitch Immunity
WDI Input Threshold
WDI Input Current
200
VIL = 0.3 × VCC, VIH = 0.7 × VCC
100
0.3 × VCC
−1
0.7 × VCC
1
0.35
VWDI = VCC
VWDI = 0 V
−0.35
MANUAL RESET INPUT
VIL
0.8
V
VIH
2.0
1
V
µs
ns
kΩ
ns
MR Input Pulse Width
MR Glitch Rejection
MR Pull-Up Resistance
MR to Reset Delay
100
75
35
125
350
VCC = 5 V
1 The device switches from undervoltage reset to normal operation when 1.5 V < VCC < 2.5 V.
2 The device monitors VCC through an internal factory trimmed voltage divider, which programs the nominal reset threshold. Factory trimmed reset thresholds are
available in approximately 100 mV increments from 2.5 V to 5 V.
Rev. A | Page 4 of 16
Data Sheet
ADM8323/ADM8324
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 2.
Parameter
Rating
VCC
−0.3 V to +6 V
−0.3 V to (VCC + 0.3 V)
20 mA
All Other Pins
Output Current (RESET)
Operating Temperature Range
Storage Temperature Range
θJA Thermal Impedance, SOT-23
Lead Temperature
Soldering (10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
−40°C to +125°C
−65°C to +150°C
270°C/W
ESD CAUTION
300°C
215°C
220°C
Rev. A | Page 5 of 16
ADM8323/ADM8324
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
RESET
GND
MR
5
V
CC
ADM8323/
ADM8324
TOP VIEW
(Not to Scale)
4
WDI
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
RESET
Active Low Reset Output. Asserted whenever VCC is below the reset threshold, VTH. This pin is a push-pull
output stage for the ADM8323 and an open-drain output stage for the ADM8324.
2
3
GND
MR
Ground.
Manual Reset Input. This is an active low input that, when forced low for greater than the glitch filter time,
generates a reset. It features a 75 kΩ internal pull-up resistor.
4
5
WDI
VCC
Watchdog Input. Generates a reset if the WDI pulse is not within the watchdog window.
Power Supply Voltage Being Monitored.
Rev. A | Page 6 of 16
Data Sheet
ADM8323/ADM8324
TYPICAL PERFORMANCE CHARACTERISTICS
14
13
12
100
90
80
70
60
50
40
30
20
10
0
V
= 5.0V
11
10
9
CC
V
= 5V
V
= 3.0V
TH
CC
8
V
= 2.93V
= 2.5V
TH
V
= 1.5V
7
CC
6
V
TH
5
4
3
2
1
0
–40 –30–20 –10
0
10 20 30 40 50 60 70 80 90 100 110 120130
TEMPERATURE (°C)
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 4. Supply Current (ICC) vs. Temperature
Figure 7. VCC to Reset Delay vs. Temperature
35
30
500
450
400
350
300
250
200
150
100
50
V
= 2.5V
TH
25
20
15
10
5
V
= 2.93V
TH
V
= 5V
TH
0
0
–40
–20
0
20
40
60
80
100
120
0
0.3 0.9 1.1 1.5 1.8 2.1 2.7 3.0 3.6 3.9 4.2 4.5 4.8 5.1 5.4
V
(V)
TEMPERATURE (°C)
CC
Figure 8. Manual Reset to Reset Propagation Delay vs. Temperature
Figure 5. Supply Current (ICC) vs. Supply Voltage (VCC)
1.20
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
0.95
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. Normalized Reset Timeout vs. Temperature
Figure 6. Normalized Reset Threshold vs. Temperature
Rev. A | Page 7 of 16
ADM8323/ADM8324
Data Sheet
1.20
WDI
1.15
1.10
2
RESET
1.05
1.00
1
0.95
0.90
CH1 2.0V
M 4.0ms 125kS/s 8.0µs/pt
A CH2 1.48V
CH2 2.0V
–40 –30–20 –10
0
10 20 30 40 50 60 70 80 90 100 110 120130
TEMPERATURE (°C)
Figure 10. Normalized Watchdog Timeout vs. Temperature, Fast Timeout
Figure 13. Slow Watchdog Timeout Period, Watchdog Timeout Option A
160
1.20
RESET ASSERTED ABOVE CURVE
140
1.15
1.10
V
= 2.93V
TH
120
100
80
60
40
20
0
V
= 5V
TH
1.05
1.00
V
= 4.63V
TH
0.95
0.90
–40 –30–20 –10
0
10 20 30 40 50 60 70 80 90 100 110 120130
TEMPERATURE (°C)
10
100
OVERDRIVE VOLTAGE (mV)
1000
Figure 11. Normalized Watchdog Timeout vs. Temperature, Slow Timeout
Figure 14. Maximum VCC Transient Duration vs. Reset Threshold Overdrive
850
840
830
820
810
WDI
V
= 2.93V
800
790
780
770
760
750
740
730
720
710
700
690
680
670
660
650
TH
2
V
= 2.5V
TH
RESET
1
V
= 5V
TH
CH1 2.0V
M400µs 1.25MS/s 800ns/pt
A CH1 1.48V
CH2 2.0V
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 12. Fast Watchdog Timeout Period, Watchdog Timeout Option A
MR
Figure 15. Manual Reset ( ) Minimum Pulse Width vs. Temperature
Rev. A | Page 8 of 16
Data Sheet
ADM8323/ADM8324
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.308
0.258
0.208
0.158
0.108
0.058
0.008
I
I
= 3.2mA
= 800µA
SOURCE
SOURCE
I
I
= 3.2mA
= 800µA
SINK
SINK
1.1
1.3
1.5
1.7
1.9
2.1
2.3
2.5
2.7
2.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
2.5
2.7
2.9
V
VOLTAGE (V)
V
VOLTAGE (V)
CC
CC
RESET
RESET
Push-Pull VOH Voltage vs. VCC Voltage (VTH = 3 V)
Figure 16.
Open-Drain VOL Voltage vs. VCC Voltage (VTH = 3 V)
Figure 18.
25
24
23
22
21
20
19
18
17
16
0.30
I
I
= 3.2mA
= 800µA
SINK
SINK
0.25
0.20
0.15
0.10
0.05
0
2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4
1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9
V
VOLTAGE (V)
V
VOLTAGE (V)
CC
CC
RESET
Figure 17.
Push-Pull VOL Voltage vs. VCC Voltage (VTH = 4 V)
RESET
Figure 19. Push-Pull Rise Time vs. VCC Voltage
Rev. A | Page 9 of 16
ADM8323/ADM8324
Data Sheet
THEORY OF OPERATION
MR
Noise immunity is provided on the
input, and fast, negative
CIRCUIT DESCRIPTION
going transients of up to 100 ns (typical) are ignored. A 0.1 µF
The ADM8323/ADM8324 provide microprocessor supply
voltage supervision by controlling the microprocessor reset input.
Code execution errors are avoided during power-up, power-down,
and brownout conditions by asserting a reset signal when the
supply voltage is below a preset threshold and by allowing supply
voltage stabilization with a fixed timeout reset pulse after the
supply voltage rises above the threshold. In addition, problems with
microprocessor code execution can be monitored and corrected
with a windowed watchdog timer. If the user detects a problem
with system operation, a manual reset input is available to reset
the microprocessor, for example, by means of an external push-
button switch.
MR
capacitor between
immunity.
and ground provides additional noise
WINDOWED WATCHDOG INPUT
The ADM8323/ADM8324 feature a windowed watchdog timer
that monitors microprocessor activity. A timer circuit is cleared
with every high to low logic transition on the watchdog input pin
(WDI), which detects pulses as short as 200 ns. If this watchdog
pulse does not occur within the defined time window, a reset
asserts. Failure of the microprocessor to toggle WDI within the
watchdog window indicates a code execution error and, therefore,
the generated reset pulse restarts the microprocessor in a
known state.
PUSH-PULL RESET OUTPUT
The ADM8323 features an active low push-pull reset output.
The reset signal is guaranteed to be valid for VCC down to 0.9 V.
As well as logic transitions on WDI, the watchdog timer is also
cleared by a reset assertion due to an undervoltage condition on
MR
V
CC or due to
being pulled low. When a reset is asserted, the
The reset output is asserted when VCC is below the reset thresh-
watchdog timer is cleared and does not begin counting again until
the reset deasserts. The windowed watchdog timer cannot
be disabled.
MR
old (VTH), when
is driven low, or when WDI is not serviced
within the watchdog timeout window. Reset remains asserted for
the duration of the reset active timeout period (tRP) after VCC rises
MR
above the reset threshold and
transitions from low to high or
All WDI input pulses are ignored while a reset is asserted. After
the reset deasserts, the first WDI falling edge is ignored for the
fast fault condition.
after the watchdog timer fault occurs. Figure 20 illustrates the
behavior of the reset output.
tWDI < tWD-FASTmin
V
CC
V
V
TH
TH
V
CC
1V
0V
V
CC
RESET
tRP
tRD
WDI
0V
Figure 20. Reset Timing Diagram
tRP
RESET
OPEN-DRAIN RESET OUTPUT
Figure 21. Watchdog Fast Timeout Fault
The ADM8324 has an active low, open-drain reset output. This
output structure requires an external pull-up resistor to connect
the reset output to a voltage rail no higher than Vcc. Use a resistor
that complies with the logic low and logic high voltage level
requirements of the microprocessor while supplying input current
tWDI > tWD-SLOWmax
WDI
RESET
and leakage paths on the
in most situations.
line. A 10 kΩ resistor is adequate
tRP
RESET
MANUAL RESET INPUT
Figure 22. Watchdog Slow Timeout Fault
MR
The ADM8323/ADM8324 feature a manual reset input ( ),
tWD-FASTmax < tWDI< tWD-SLOWmin
MR
which when driven low, asserts the reset output. When
transitions from low to high, the reset output remains asserted for
the duration of the reset active timeout period before deasserting.
WDI
MR
The
input is always high when unconnected. An external push-button
MR
input has a 75 kΩ, internal pull-up resistor so that the
switch can be connected between
and ground so the user
RESET
can generate a reset. Debounce circuitry for this purpose is
integrated on chip.
Figure 23. Normal Watchdog Operation
Rev. A | Page 10 of 16
Data Sheet
ADM8323/ADM8324
APPLICATIONS INFORMATION
WATCHDOG INPUT CURRENT
ENSURING RESET VALID TO VCC = 0 V
There is no way to disable the windowed watchdog functional-
ity. Do not leave the WDI pin floating because this is not a valid
mode of operation. If the WDI pin is not in a defined state at
startup, this can lead to high supply current until the microproces-
sor is enabled and takes control of the WDI pin. A solution to
this is to add a 100 kΩ pull-up or pull-down resistor on the
WDI pin to hold it in a defined state until the microprocessor
is enabled.
The reset output is guaranteed valid for VCC as low as 0.9 V.
However, by using an external resistor with the push-pull
configured reset output on the ADM8323, a valid output for VCC
as low as 0 V is possible. For this active low reset output, a resistor
RESET
connected between
and ground pulls the output low
when it is unable to sink current. Use a large resistance, such as
100 kΩ, so that it does not overload the reset output when VCC
is above 0.9 V.
V
CC
NEGATIVE GOING VCC TRANSIENTS
To avoid unnecessary resets caused by fast power supply transients,
the ADM8323/ADM8324 are equipped with glitch rejection
circuitry. The typical performance characteristic in Figure 14
plots VCC transient duration vs. reset threshold overdrive. The
curves show combinations of reset threshold overdrive and
duration for which a reset is not generated for 5 V, 4.63 V, and
2.93 V reset threshold devices. For example, with the 2.93 V
threshold, a transient that goes 100 mV below the threshold and
lasts 80 µs typically does not cause a reset. However, if the transient
is any larger in reset threshold overdrive or duration, a reset
generates. An optional 0.1 µF bypass capacitor mounted near
RESET
ADM8323
100kΩ
RESET
Figure 24. Ensuring
Valid to VCC = 0 V
V
CC
RESET
RESET
V
CC provides additional glitch rejection.
ADM8323
MICROPROCESSOR
I/O
MR
WDI
Figure 25. ADM8323 Typical Application Circuit
Rev. A | Page 11 of 16
ADM8323/ADM8324
MODEL OPTIONS
Data Sheet
Table 4. Reset Timeout Options
Suffix
Minimum
Typical
1.4
28
Maximum
1.8
36
Unit
ms
ms
A
B
1
20
C
D
140
1120
200
1600
260
2080
ms
ms
Table 5. Watchdog Timeout Options
Fast
Slow
Suffix
Maximum
Unit
ms
ms
ms
ms
ms
ms
ms
ms
Minimum
10
100
300
10
60
44
76
1.24
Unit
ms
ms
ms
sec
sec
ms
ms
sec
A
B
C
D
E
F
G
H
1.5
15
15
15
15
24
41
768
Table 6. Reset Voltage Threshold Options
TA = 25°C
TA = −40°C to +125°C
Reset Threshold Number
Minimum
4.950
4.851
4.752
4.653
4.584
4.455
4.346
4.257
4.158
4.059
3.960
3.861
3.762
3.663
3.564
3.465
3.366
3.267
3.168
3.049
2.970
2.901
2.772
2.673
2.604
2.475
Typical
Maximum
5.050
4.949
4.848
4.747
4.676
4.545
4.434
4.343
4.242
4.141
4.040
3.939
3.838
3.737
3.636
3.535
3.434
3.333
3.232
3.111
3.030
2.959
2.828
2.727
2.656
2.525
Minimum
4.925
4.826
4.728
4.629
4.560
4.432
4.324
4.235
4.137
4.038
3.940
3.841
3.743
3.644
3.546
3.447
3.349
3.250
3.152
3.033
2.955
2.886
2.758
2.659
2.590
2.462
Maximum
5.075
4.974
4.872
4.771
4.700
4.568
4.456
4.365
4.263
4.162
4.060
3.959
3.857
3.756
3.654
3.553
3.451
3.350
3.248
3.127
3.045
2.974
2.842
2.741
2.670
2.538
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
5.000
4.900
4.800
4.700
4.630
4.500
4.390
4.300
4.200
4.100
4.00
3.900
3.800
3.700
3.600
3.500
3.400
3.300
3.200
3.080
3.000
2.930
2.800
2.700
2.630
2.500
Rev. A | Page 12 of 16
Data Sheet
ADM8323/ADM8324
Table 7. Standard Models
Model
Reset Threshold (V) Maximum Fast Timeout (ms) Minimum Slow Timeout (ms) Minimum Reset Timeout (ms)
ADM8323WCC29ARJZR7 2.93
ADM8323WCC46ARJZR7 4.63
ADM8324WAH29ARJZR7 2.93
ADM8324WCA29ARJZR7 2.93
ADM8324WCA46ARJZR7 4.63
15
15
768
1.5
1.5
300
300
1240
10
140
140
1
140
140
10
Rev. A | Page 13 of 16
ADM8323/ADM8324
Data Sheet
OUTLINE DIMENSIONS
3.00
2.90
2.80
5
1
4
3
3.00
2.80
2.60
1.70
1.60
1.50
2
0.95 BSC
1.90
BSC
1.30
1.15
0.90
0.20 MAX
0.08 MIN
1.45 MAX
0.95 MIN
0.55
0.45
0.35
0.15 MAX
0.05 MIN
10°
5°
0°
SEATING
PLANE
0.60
BSC
0.50 MAX
0.35 MIN
COMPLIANT TO JEDEC STANDARDS MO-178-AA
Figure 26. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
ADM83
W
ARJZR7
ORDERING QUANTITY
R7: 3000-PIECE REEL, RoHS COMPLIANT
GENERIC NUMBER
(23 OR 24)
Z: RoHS COMPLIANT
W: AUTOMOTIVE QUAL
PACKAGE CODE
RJ: 5-LEAD SOT-23
RESET TIMEOUT PERIOD
TEMPERATURE RANGE
A: –40°C TO +125°C
A: 1ms (MIN)
B: 20ms (MIN)
C: 140ms (MIN)
D: 1120ms (MIN)
RESET THRESHOLD NUMBER
(25 TO 50)
WINDOWEDWATCHDOG
TIMEOUT PERIOD (A-H)
Figure 27. Ordering Code Structure
ORDERING GUIDE
Model1, 2, 3, 4
ADM8323WxxxxARJZR7
ADM8324WxxxxARJZR7
Temperature Range
−40°C to +125°C
−40°C to +125°C
Ordering Quantity5
Package Description
Package Option
Branding
LNO
LMU
3,000
3,000
5-Lead SOT-23
5-Lead SOT-23
RJ-5
RJ-5
1 Complete the ordering code by inserting reset timeout, watchdog timeout, and reset threshold suffixes from Table 4 to Table 6.
2 W = Qualified for Automotive Applications.
3 Z = RoHS Compliant Part.
4 Contact sales for the availability of nonstandard models. See Table 7 for a list of standard models.
5 A minimum of 12,000 (four reels) must be ordered for nonstandard models.
AUTOMOTIVE PRODUCTS
The ADM8323W/ADM8324W model are available with controlled manufacturing to support the quality and reliability requirements of
automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore,
designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for
use in automotive applications. Contact your local Analog Devices, Inc., account representative for specific product ordering information
and to obtain the specific Automotive Reliability reports for these models.
Rev. A | Page 14 of 16
Data Sheet
NOTES
ADM8323/ADM8324
Rev. A | Page 15 of 16
ADM8323/ADM8324
NOTES
Data Sheet
©2013–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11802-0-3/16(A)
Rev. A | Page 16 of 16
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