ADM8693ARN [ADI]
Microprocessor Supervisory Circuits; 微处理器监控电路
| 型号： | ADM8693ARN |
| 厂家： | 
ADI |
| 描述： | Microprocessor Supervisory Circuits |
| 文件： | 总16页 (文件大小：209K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Microprocessor
Supervisory Circuits
a
ADM8690–ADM8695
FEATURES
FUNCTIO NAL BLO CK D IAGRAMS
Upgrade for ADM690/ ADM695, MAX690–MAX695
Specified Over Tem perature
Low Pow er Consum ption (0.7 m W)
Precision Voltage Monitor
V
BATT
V
OUT
Reset Assertion Dow n to 1 V VCC
Low Sw itch On-Resistance 0.7 ⍀ Norm al,
7 ⍀ in Backup
V
CC
RESET
GENERATOR
1
RESET
4.65V
High Current Drive (100 m A)
2
Watchdog Tim er—100 m s, 1.6 s, or Adjustable
400 nA Standby Current
Autom atic Battery Backup Pow er Sw itching
Extrem ely Fast Gating of Chip Enable Signals (3 ns)
Voltage Monitor for Pow er Fail
Available in TSSOP Package
ADM8690
ADM8692
ADM8694
WATCHDOG
TRANSITION DETECTOR
(1.6s)
WATCHDOG
INPUT (WDI)
POWER FAIL
INPUT (PFI)
POWER FAIL
OUTPUT (PFO)
1.3V
APPLICATIONS
Microprocessor System s
Com puters
1
2
VOLTAGE DETECTOR = 4.65V (ADM8690, ADM8694)
4.40V (ADM8692)
RESET PULSE WIDTH = 50ms (AD8690, ADM8692)
200ms (ADM8694)
Controllers
Intelligent Instrum ents
Autom otive System s
BATT ON
V
BATT
GENERAL D ESCRIP TIO N
V
OUT
T he ADM8690–ADM8695 family of supervisory circuits offers
complete single chip solutions for power supply monitoring and
battery control functions in microprocessor systems. T hese
functions include µP reset, backup battery switchover, watchdog
timer, CMOS RAM write protection and power failure warning.
T he complete family provides a variety of configurations to sat-
isfy most microprocessor system requirements.
ADM8691
ADM8693
ADM8695
V
CC
CE
IN
CE
OUT
LOW LINE
RESET
1
4.65V
OSC IN
RESET AND
RESET
T he ADM8690, ADM8692 and ADM8694 are available in
8-pin DIP packages and provide:
WATCHDOG
GENERATOR
TIMEBASE
RESET
OSC SEL
1. Power-on reset output during power-up, power-down and
brownout conditions. T he RESET output remains opera-
tional with VCC as low as 1 V.
WATCHDOG
INPUT (WDI)
WATCHDOG
TIMER
WATCHDOG
TRANSITION DETECTOR
WATCHDOG
OUTPUT (WDO)
POWER FAIL
INPUT (PFI)
POWER FAIL
2. Battery backup switching for CMOS RAM, CMOS
microprocessor or other low power logic.
OUTPUT (PFO)
1.3V
3. A reset pulse if the optional watchdog timer has not been
toggled within a specified time.
1
VOLTAGE DETECTOR = 4.65V (ADM8691, ADM8695)
4.40V (ADM8693)
4. A 1.3 V threshold detector for power fail warning, low battery
detection or to monitor a power supply other than +5 V.
T he ADM8690–ADM8695 family is fabricated using an ad-
vanced epitaxial CMOS process combining low power con-
sumption (0.7 mW), extremely fast Chip Enable gating (3 ns)
and high reliability. RESET assertion is guaranteed with VCC as
low as 1 V. In addition, the power switching circuitry is de-
signed for minimal voltage drop thereby permitting increased
output current drive of up to 100 mA without the need of an
external pass transistor.
T he ADM8691, ADM8693 and ADM8695 are available in
16-pin DIP and small outline packages (including T SSOP) and
provide three additional functions:
1. Write protection of CMOS RAM or EEPROM.
2. Adjustable reset and watchdog timeout periods.
3. Separate watchdog timeout, backup battery switchover, and
low VCC status outputs.
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1997
(V = Full Operating Range, VBATT = +2.8 V, T = TMIN to
CC
A
T
MAX unless otherwise noted)
ADM8690–ADM8695–SPECIFICATIONS
P aram eter
Min
Typ
Max
Units
Test Conditions/Com m ents
BAT T ERY BACKUP SWIT CHING
VCC Operating Voltage Range
ADM8690, ADM8691, ADM8694, ADM8695
ADM8692, ADM8693
4.75
4.5
5.5
5.5
V
V
VBAT T Operating Voltage Range
ADM8690, ADM8691, ADM8694, ADM8695
ADM8692, ADM8693
2.0
2.0
4.25
4.0
V
V
VOUT Output Voltage
VCC – 0.005 VCC – 0.0025
VCC – 0.2 VCC – 0.125
V
V
IOUT = 1 mA
IOUT ≤ 100 mA
VOUT in Battery Backup Mode
Supply Current (Excludes IOUT
VBAT T – 0.005 VBAT T – 0.002
V
µA
µA
IOUT = 250 µA, VCC < VBAT T – 0.2 V
IOUT = 100 µA
VCC = 0 V, VBAT T = 2.8 V
5.5 V > VCC > VBAT T + 0.2 V
T A = +25°C
)
140
0.4
200
1
Supply Current in Battery Backup Mode
Battery Standby Current
(+ = Discharge, – = Charge)
Battery Switchover T hreshold
VCC – VBAT T
Battery Switchover Hysteresis
BAT T ON Output Voltage
BAT T ON Output Short Circuit Current
–0.1
+0.02
µA
70
50
20
mV
mV
mV
V
mA
µA
Power-Up
Power-Down
0.3
25
ISINK = 3.2 mA
BAT T ON = VOUT = 4.5 V Sink Current
BAT T ON = 0 V Source Current
55
0.5
2.5
RESET AND WAT CHDOG T IMER
Reset Voltage T hreshold
ADM8690, ADM8691, ADM8694, ADM8695
ADM8692, ADM8693
Reset T hreshold Hysteresis
4.5
4.25
4.65
4.4
40
4.73
4.48
V
V
mV
Reset T imeout Delay
ADM8690, ADM8691, ADM8692, ADM8693
ADM8694, ADM8695
Watchdog T imeout Period, Internal Oscillator
35
50
200
1.6
100
4064
1011
70
ms
ms
s
OSC SEL = HIGH
OSC SEL = HIGH
Long Period
140
1.0
70
3840
768
50
280
2.25
140
4097
1025
ms
Short Period
Watchdog T imeout Period, External Clock
Cycles Long Period
Cycles Short Period
ns
mV
V
Minimum WDI Input Pulse Width
RESET Output Voltage @ VCC = +1 V
RESET, LOW LINE Output Voltage
VIL = 0.4, VIH = 3.5 V
4
0.05
20
0.4
ISINK = 10 µA, VCC = 1 V
ISINK = 1.6 mA, VCC = 4.25 V
ISOURCE = 1 µA
3.5
V
RESET, WDO Output Voltage
0.4
25
V
V
µA
mA
ISINK = 1.6 mA
ISOURCE = 1 µA
3.5
1
Output Short Circuit Source Current
Output Short Circuit Sink Current
WDI Input T hreshold
Logic Low
Logic High
WDI Input Current
10
25
Note 1
0.8
10
V
V
µA
µA
3.5
1
–1
WDI = VOUT
WDI = 0 V
–10
POWER FAIL DET ECT OR
PFI Input T hreshold
PFI Input Current
1.25
–25
1.3
±0.01
1.35
+25
0.4
V
nA
V
VCC = +5 V
PFO Output Voltage
ISINK = 3.2 mA
3.5
1
V
µA
mA
ISOURCE = 1 µA
PFI = Low, PFO = 0 V
PFI = High, PFO = VOUT
PFO Short Circuit Source Current
PFO Short Circuit Sink Current
3
25
25
CHIP ENABLE GAT ING
CEIN T hreshold
0.8
0.4
7
V
V
µA
V
V
VIL
VIH
3.0
CEIN Pull-Up Current
CEOUT Output Voltage
3
3
ISINK = 3.2 mA
ISOURCE = 3.0 mA
ISOURCE = 1 µA, VCC = 0 V
VOUT – 1.5
VOUT – 0.05
V
ns
CE Propagation Delay
REV. 0
–2–
ADM8690–ADM8695
P aram eter
Min
Typ
Max
Units
Test Conditions/Com m ents
OSCILLAT OR
OSC IN Input Current
±2
µA
OSC SEL Input Pull-Up Current
OSC IN Frequency Range
OSC IN Frequency with External Capacitor
5
µA
kHz
kHz
0
500
OSC SEL = 0 V
OSC SEL = 0 V, C OSC = 47 pF
4
NOT E
1WDI is a three level input which is internally biased to 38% of VCC and has an input impedance of approximately 5 M Ω.
Specifications subject to change without notice.
ABSO LUTE MAXIMUM RATINGS*
O RD ERING GUID E
(T A = +25°C unless otherwise noted)
Model
Tem perature Range
P ackage O ptions*
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
VBAT T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
All Other Inputs . . . . . . . . . . . . . . . . . . –0.3 V to VOUT + 0.5 V
Input Current
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
VBAT T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Power Dissipation, N-8 DIP . . . . . . . . . . . . . . . . . . . . 400 mW
ADM8690AN
ADM8690ARN
–40°C to +85°C
–40°C to +85°C
N-8
SO-8
ADM8691AN
ADM8691ARN
ADM8691ARW
ADM8691ARU
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
N-16
R-16A
R-16
RU-16
ADM8692AN
ADM8692ARN
–40°C to +85°C
–40°C to +85°C
N-8
SO-8
θ
JA T hermal Impedance . . . . . . . . . . . . . . . . . . . . . 120°C/W
Power Dissipation, N-16 DIP . . . . . . . . . . . . . . . . . . . 600 mW
JA T hermal Impedance . . . . . . . . . . . . . . . . . . . . . 135°C/W
Power Dissipation, RU-16 DIP . . . . . . . . . . . . . . . . . . 600 mW
JA T hermal Impedance . . . . . . . . . . . . . . . . . . . . . 158°C/W
Power Dissipation, R-16 SOIC . . . . . . . . . . . . . . . . . . 600 mW
JA T hermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W
ADM8693AN
ADM8693ARN
ADM8693ARW
ADM8693ARU
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
N-16
R-16A
R-16
θ
θ
RU-16
ADM8694AN
ADM8694ARN
–40°C to +85°C
–40°C to +85°C
N-8
SO-8
θ
Operating T emperature Range
ADM8695AN
ADM8695ARW
–40°C to +85°C
–40°C to +85°C
N-16
R-16
Industrial (A Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead T emperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
Storage T emperature Range . . . . . . . . . . . . . –65°C to +150°C
*N = Plastic DIP; R = Small Outline (Wide); R = Small Outline (Narrow);
RU = T hin Shrink Small Outline; SO = Small Outline.
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. T his is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum ratings for
extended periods of time may affect device reliability.
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADM8690–ADM8695 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. T herefore,
proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
ADM8690–ADM8695
P IN FUNCTIO N D ESCRIP TIO N
Mnem onic
Function
VCC
Power Supply Input: +5 V Nominal.
Backup Battery Input.
VBAT T
VOUT
Output Voltage, VCC or VBAT T is internally switched to VOUT depending on which is at the highest potential. VOUT
can supply up to 100 mA to power CMOS RAM. Connect VOUT to VCC if VOUT and VBAT T are not used.
GND
0 V. Ground reference for all signals.
RESET
Logic Output. RESET goes low if
1. VCC falls below the Reset T hreshold
2. T he watchdog timer is not serviced within its timeout period.
The reset threshold is typically 4.65 V for the ADM8690/ADM8691/ADM8694/ADM8695 and 4.4 V for the ADM8692
and ADM8693. RESET remains low for 50 ms (ADM8690/ADM8691/ADM8692/ADM8693) or 200 ms (ADM8694/
ADM8695) after VCC returns above the threshold. RESET also goes low for 50 (200) ms if the watchdog timer is
enabled but not serviced within its timeout period. The RESET pulse width can be adjusted on the ADM8691/ADM8693/
ADM8695 as shown in T able I. T he RESET output has an internal 3 µA pull up, and can either connect
to an open collector Reset bus or directly drive a CMOS gate without an external pull-up resistor.
WDI
Watchdog Input. WDI is a three level input. If WDI remains either high or low for longer than the watchdog timeout
period, RESET pulses low and WDO goes low. T he timer resets with each transition on the WDI line. T he watchdog
timer may be disabled if WDI is left floating or is driven to midsupply.
PFI
Power Fail Input. PFI is the noninverting input to the Power Fail Comparator when PFI is less than 1.3 V, PFO
goes low. Connect PFI to GND or VOUT when not used.
PFO
Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI is less than 1.3 V. T he
comparator is turned off and PFO goes low when VCC is below VBAT T
.
CEIN
Logic Input. T he input to the CE gating circuit. Connect to GND or VOUT if not used.
CEOUT
Logic Output. CEOUT is a gated version of the CEIN signal. CEOUT tracks CEIN when VCC is above the reset
threshold. If VCC is below the reset threshold, CEOUT is forced high. See Figures 5 and 6.
BAT T ON
Logic Output. BAT T ON goes high when VOUT is internally switched to the VBAT T input. It goes low when VOUT
is internally switched to VCC. T he output typically sinks 35 mA and can directly drive the base of an external
PNP transistor to increase the output current above the 100 mA rating of VOUT
.
LOW LINE Logic Output. LOW LINE goes low when VCC falls below the reset threshold. It returns high as soon as VCC rises
above the reset threshold.
RESET
Logic Output. RESET is an active high output. It is the inverse of RESET.
OSC SEL
Logic Oscillator Select Input. When OSC SEL is unconnected (floating) or driven high, the internal oscillator sets
the reset active time and watchdog timeout period. When OSC SEL is low, the external oscillator input, OSC IN,
is enabled. OSC SEL has a 3 µA internal pull-up (see T able I).
OSC IN
Oscillator Logic Input. With OSC SEL low, OSC IN can be driven by an external clock signal or an external
capacitor can be connected between OSC IN and GND. T his sets both the reset active pulse timing and the watch-
dog timeout period (see T able I and Figure 4). With OSC SEL high or floating, the internal oscillator is enabled
and the reset active time is fixed at 50 ms typ. (ADM8691/ADM8693) or 200 ms typ (ADM8695). In this mode the
OSC IN pin selects between fast (100 ms) and slow (1.6 s) watchdog timeout periods. In both modes, the timeout
period immediately after a reset is 1.6 s typical.
WDO
Logic Output. T he Watchdog Output, WDO, goes low if WDI remains either high or low for longer than the
watchdog timeout period. WDO is set high by the next transition at WDI. If WDI is unconnected or at midsupply,
the watchdog timer is disabled and WDO remains high. WDO also goes high when LOW LINE goes low.
–4–
REV. 0
ADM8690–ADM8695
P IN CO NFIGURATIO NS
V
1
2
3
4
5
6
7
8
16 RESET
RESET
BATT
V
V
BATT
1
2
3
4
8
7
6
5
15
OUT
V
OUT
ADM8690
ADM8692
ADM8694
ADM8691
ADM8693
ADM8695
TOP VIEW
(Not to Scale)
V
RESET
WDI
CC
V
14 WDO
CC
GND
PFI
GND
13 CE
IN
TOP VIEW
(Not to Scale)
PFO
BATT ON
CE
OUT
12
11
10
9
WDI
PFO
PFI
LOW LINE
OSC IN
OSC SEL
P RO D UCT SELECTIO N GUID E
P art
Num ber
Nom inal Reset
Tim e
Nom inal VCC
Reset Threshold
Nom inal Watchdog
Tim eout P eriod
Battery Backup
Switching
Base D rive
Ext P NP
Chip Enable
Signals
ADM8690
ADM8691
ADM8692
ADM8693
ADM8694
ADM8695
50 ms
50 ms or ADJ
50 ms
50 ms or ADJ
200 ms
200 ms or ADJ
4.65 V
4.65 V
4.4 V
4.4 V
4.65 V
4.65 V
1.6 s
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
100 ms, 1.6 s, ADJ
1.6 s
100 ms, 1.6 s, ADJ
1.6 s
100 ms, 1.6 s, ADJ
CIRCUIT INFO RMATIO N
Batter y Switchover Section
If the continuous output current requirement at VOUT exceeds
100 mA, or if a lower VCC–VOUT voltage differential is desired,
an external PNP pass transistor may be connected in parallel with
the internal transistor. T he BAT T ON output (ADM8691/
ADM8693/ADM8695) can directly drive the base of the exter-
nal transistor.
T he battery switchover circuit compares VCC to the VBAT T
input, and connects VOUT to whichever is higher. Switchover
occurs when VCC is 50 mV higher than VBAT T as VCC falls, and
when VCC is 70 mV greater than VBAT T as VCC rises. T his
20 mV of hysteresis prevents repeated rapid switching if VCC
falls very slowly or remains nearly equal to the battery voltage.
A 7 Ω MOSFET switch connects the VBAT T input to VOUT dur-
ing battery backup. T his MOSFET has very low input-to-out-
put differential (dropout voltage) at the low current levels
required for battery back up of CMOS RAM or other low power
CMOS circuitry. T he supply current in battery back up is typi-
cally 0.4 µA.
V
CC
V
OUT
V
BATT
T he ADM8690/ADM8691/ADM8694/ADM8695 operates with
battery voltages from 2.0 V to 4.25 V, and the ADM8692/
ADM8693 operates with battery voltages from 2.0 V to 4.0 V.
High value capacitors, either standard electrolytic or the farad
size double layer capacitors, can also be used for short-term
memory backup. A small charging current of typically 10 nA
(0.1 µA max) flows out of the VBAT T terminal. T his current is
useful for maintaining rechargeable batteries in a fully charged
condition. T his extends the life of the backup battery by com-
pensating for its self discharge current. Also note that this cur-
rent poses no problem when lithium batteries are used for
backup since the maximum charging current (0.1 µA) is safe for
even the smallest lithium cells.
GATE DRIVE
100
mV
BATT ON
(ADM8690,
ADM8695)
INTERNAL
SHUTDOWN SIGNAL
WHEN
700
mV
V
> (V + 0.7V)
BATT
CC
Figure 1. Battery Switchover Schem atic
During normal operation, with VCC higher than VBAT T, VCC is
internally switched to VOUT via an internal PMOS transistor
switch. T his switch has a typical on-resistance of 0.7 Ω and can
supply up to 100 mA at the VOUT terminal. VOUT is normally
used to drive a RAM memory bank which may require instanta-
neous currents of greater than 100 mA. If this is the case then a
bypass capacitor should be connected to VOUT . T he capacitor
will provide the peak current transients to the RAM. A capaci-
tance value of 0.1 µF or greater may be used.
If the battery switchover section is not used, VBAT T should be
connected to GND and VOUT should be connected to VCC
.
REV. 0
–5–
ADM8690–ADM8695
P ower Fail RESET O utput
Watchdog Tim er RESET
RESET is an active low output that provides a RESET signal
to the Microprocessor whenever VCC is at an invalid level.
When VCC falls below the reset threshold, the RESET output
is forced low. T he nominal reset voltage threshold is 4.65 V
(ADM8690/ADM8691/ADM8694/ADM8695) or 4.4 V
(ADM8692/ADM8693).
T he watchdog timer circuit monitors the activity of the micro-
processor in order to check that it is not stalled in an indefinite
loop. An output line on the processor is used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within the
selected timeout period, a RESET pulse is generated. T he
nominal watchdog timeout period is preset at 1.6 seconds on the
ADM8690/ADM8692/ADM8694. The ADM8691/ADM8693/
ADM8695 may be configured for either a fixed “short” 100 ms
or a “long” 1.6 second timeout period or for an adjustable
timeout period. If the “short” period is selected, some systems
may be unable to service the watchdog timer immediately after a
reset, so the ADM8691/ADM8693/ADM8695 automatically se-
lects the “long” timeout period directly after a reset is issued.
T he watchdog timer is restarted at the end of reset, whether the
reset was caused by lack of activity on WDI or by VCC falling be-
low the reset threshold.
V2
V2
V
V1
V1
CC
t1
t1
RESET
LOW LINE
t1 = RESET TIME
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1
T he normal (short) timeout period becomes effective following
the first transition of WDI after RESET has gone inactive. T he
watchdog timeout period restarts with each transition on the
WDI pin. T o ensure that the watchdog timer does not time out,
either a high-to-low or low-to-high transition on the WDI pin
must occur at or less than the minimum timeout period. If WDI
remains permanently either high or low, reset pulses will be
issued after each “long” (1.6 s) timeout period. T he watchdog
monitor can be deactivated by floating the Watchdog Input
(WDI) or by connecting it to midsupply.
Figure 2. Power Fail Reset Tim ing
On power-up, RESET will remain low for 50 ms (200 ms for
ADM8694 and ADM8695) after VCC rises above the appropri-
ate reset threshold. T his allows time for the power supply and
microprocessor to stabilize. On power-down, the RESET out-
put remains low with VCC as low as 1 V. T his ensures that the
microprocessor is held in a stable shutdown condition.
This RESET active time is adjustable on the AD M 8691/
ADM8693/ADM8695 by using an external oscillator or by
connecting an external capacitor to the OSC IN pin. Refer to
T able I and Figure 4.
WDI
T he guaranteed minimum and maximum thresholds of the
ADM8690/ADM8691/ADM8694/ADM8695 are 4.5 V and
4.73 V, while the guaranteed thresholds of the ADM8692/
ADM8693 are 4.25 V and 4.48 V. The ADM8690/ADM8691/
ADM8694/ADM8695 is, therefore, compatible with 5 V sup-
plies with a +10%, –5% tolerance while the ADM8692/
ADM8693 is compatible with 5 V ± 10% supplies. T he reset
threshold comparator has approximately 50 mV of hysteresis.
T he response time of the reset voltage comparator is less than 1
µs. If glitches are present on the VCC line which could cause
spurious reset pulses, then VCC should be decoupled close to
the device.
WDO
t2
t3
RESET
t1
t1
t1
t1 = RESET TIME
t2 = NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD
t3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET
Figure 3. Watchdog Tim eout Period and Reset Active
Tim e
In addition to RESET the ADM8691/ADM8693/ADM8695
contain an active high RESET output. T his is the complement
of RESET and is intended for processors requiring an active
high RESET signal.
–6–
REV. 0
ADM8690–ADM8695
Table I. AD M8691, AD M8693, AD M8695 Reset P ulse Width and Watchdog Tim eout Selections
Watchdog Tim eout P eriod
Im m ediately
Reset Active P eriod
O SC SEL
O SC IN
Norm al
After Reset
AD M8691/AD M8693
AD M8695
Low
Low
External Clock Input
External Capacitor
1024 CLKS
400 ms × C/47 pF
100 ms
4096 CLKS
1.6 s × C/47 pF
1.6 s
512 CLKS
200 ms × C/47 pF
50 ms
2048 CLKS
520 ms × C/47 pF
200 ms
Floating or High Low
Floating or High Floating or High
1.6 s
1.6 s
50 ms
200 ms
NOT E
With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor can be connected between OSC IN and GND. T he nominal
internal oscillator frequency is 10.24 kHz. T he nominal oscillator frequency with external capacitor is: F OSC (Hz) = 184,000/C (pF)
On the ADM8690/ADM8692 the watchdog timeout period is
fixed at 1.6 seconds and the reset pulse width is fixed at 50 ms.
On the ADM8694 the watchdog timeout period is also 1.6 sec-
onds but the reset pulse width is fixed at 200 ms. The ADM8691/
ADM8693/ADM8695 allow these times to be adjusted as
shown in T able I. Figure 4 shows the various oscillator configu-
rations that can be used to adjust the reset pulse width and
watchdog timeout period.
8
7
OSC SEL
ADM8691
ADM8693
ADM8695
OSC IN
C
OSC
Figure 4b. External Capacitor
T he internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects between the 1.6 second
and 100 ms watchdog timeout periods. With OSC IN connected
high or floating, the 1.6 second timeout period is selected; while
with it connected low, the 100 ms timeout period is selected. In
either case, immediately after a reset the timeout period is 1.6
seconds. T his gives the microprocessor time to reinitialize the
system. If OSC IN is low, then the 100 ms watchdog period be-
comes effective after the first transition of WDI. T he software
should be written such that the I/O port driving WDI is left in
its power-up reset state until the initialization routines are com-
pleted and the microprocessor is able to toggle WDI at the mini-
mum watchdog timeout period of 70 ms.
8
OSC SEL
NC
ADM8691
ADM8693
ADM8695
7
OSC IN
NC
Figure 4c. Internal Oscillator (1.6 Second Watchdog)
8
OSC SEL
NC
Watchdog O utput (WD O )
T he Watchdog Output WDO (ADM8691/ADM8693/
ADM8695) provides a status output which goes low if the
watchdog timer “times out” and remains low until set high by
the next transition on the Watchdog Input. WDO is also set
high when VCC goes below the reset threshold.
ADM8691
ADM8693
ADM8695
7
OSC IN
Figure 4d. Internal Oscillator (100 m s Watchdog)
8
OSC SEL
ADM8691
ADM8693
ADM8695
CLOCK
0 TO 500kHz
7
OSC IN
Figure 4a. External Clock Source
REV. 0
–7–
ADM8690–ADM8695
(PFI) is compared to an internal +1.3 V reference. T he Power
Fail Output (PFO) goes low when the voltage at PFI is less than
1.3 V. T ypically PFI is driven by an external voltage divider that
senses either the unregulated dc input to the system’s 5 V regu-
lator or the regulated 5 V output. T he voltage divider ratio can
be chosen such that the voltage at PFI falls below 1.3 V several
milliseconds before the +5 V power supply falls below the reset
threshold. PFO is normally used to interrupt the microprocessor
so that data can be stored in RAM and the shut down procedure
executed before power is lost
CE Gating and RAM Wr ite P r otection (AD M8691/AD M8693/
AD M8695)
T he ADM8691/ADM8693/ADM8695 products include
memory protection circuitry which ensures the integrity of data
in memory by preventing write operations when VCC is at an in-
valid level. T here are two additional pins, CEIN and CEOUT
,
which may be used to control the Chip Enable or Write inputs
of CMOS RAM. When VCC is present, CEOUT is a buffered rep-
lica of CEIN, with a 3 ns propagation delay. When VCC falls be-
low the reset voltage threshold or VBAT T, an internal gate forces
CEOUT high, independent of CEIN
.
INPUT
POWER
ADM869x
CEOUT typically drives the CE, CS or write input of battery
backed up CMOS RAM. T his ensures the integrity of the data
in memory by preventing write operations when VCC is at an in-
valid level. Similar protection of EEPROMs can be achieved by
using the CEOUT to drive the store or write inputs.
R1
R2
1.3V
POWER
FAIL
PFO
OUTPUT
POWER
FAIL
INPUT
Figure 7. Power Fail Com parator
Table II. Input and O utput Status In Battery Backup Mode
ADM869x
CE
IN
CE
OUT
Signal
Status
V
V
LOW = 0
OK = 1
CC
CC
VOUT
VOUT is connected to VBAT T via an internal
PMOS switch.
Figure 5. Chip Enable Gating
RESET
Logic low.
RESET
Logic high. T he open circuit output voltage is
V2
V2
equal to VOUT
.
V
V1
V1
CC
LOW LINE
Logic low.
BAT T ON
Logic high. T he open circuit voltage is equal to
VOUT.
t1
t1
RESET
WDI
WDI is ignored. It is internally disconnected
from the internal pull-up resistor and does not
source or sink current as long as its input voltage
is between GND and VOUT . T he input voltage
does not affect supply current.
LOW LINE
WDO
Logic high. T he open circuit voltage is equal
to VOUT
.
CE
IN
PFI
T he Power Fail Comparator is turned off and
has no effect on the Power Fail Output.
PFO
CEIN
Logic low.
CE
OUT
CEIN is ignored. It is internally disconnected
from its internal pull-up and does not source or
sink current as long as its input voltage is
between GND and VOUT . T he input voltage
does not affect supply current.
t1 = RESET TIME
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1
CEOUT
Logic high. T he open circuit voltage is equal to
Figure 6. Chip Enable Tim ing
P ower Fail War ning Com par ator
An additional comparator is provided for early warning of fail-
ure in the microprocessor’s power supply. T he Power Fail Input
VOUT
.
OSC IN
OSC IN is ignored.
OSC SEL is ignored.
OSC SEL
–8–
REV. 0
Typical Performance Curves–ADM8690–ADM8695
2.8
5.00
4.99
4.98
4.97
4.96
4.95
4.94
A4
3.36 V
2.798
2.796
2.794
2.792
2.79
100
90
10
0%
2.788
2.786
1V
1V
500ms
150 250 350 450 550 650 750 850 950 1050
– µA
10 20 30 40 50 60 70 80 90 100
– mA
I
I
OUT
OUT
Figure 10. Reset Output Voltage vs
Supply Voltage
Figure 8. VOUT vs. IOUT Norm al
Operation
Figure 9. VOUT vs. IOUT Battery
Backup
4.69
1.315
1.31
53
V
= +5V
CC
V
= +5V
4.67
4.65
4.63
4.61
4.59
4.57
4.55
CC
52
51
50
49
1.305
1.3
1.295
ADM8690
ADM8691
ADM8692
ADM8693
1.29
1.285
1.28
–60
–30
0
30
60
90
120
–60
–30
0
30
60
90
120
20
40
60
80
100
120
TEMPERATURE –
°
C
TEMPERATURE –
°C
TEMPERATURE –
°C
Figure 13. Reset Voltage Threshold
vs. Tem perature
Figure 11. PFI Input Threshold vs.
Tem perature
Figure 12. Reset Active Tim e vs.
Tem perature
6
6
6
V
T
= 5V
CC
= +25
V
T
= 5V
V
T
= 5V
CC
CC
5
4
3
2
1
0
5
4
3
2
1
0
5
4
3
2
1
0
°
C
A
= +25°C
= +25°C
A
A
V
PFI
+5V
10kΩ
30pF
PFO
1.3V
30pF
V
PFI
V
PFO
PFI
1.3V
PFO
30pF
1.3V
1.35
1.25
1.35
1.25
1.35
1.25
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
TIME – µs
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
TIME – µs
0
10 20 30 40 50 60 70 80 90
TIME – µs
Figure 16. Power Fail Com parator
Response Tim e with Pull-Up Resistor
Figure 14. Power Fail Com parator
Response Tim e
Figure 15. Power Fail Com parator
Response Tim e
REV. 0
–9–
ADM8690–ADM8695
Monitor ing the Status of the Batter y
+AP P LICATIO N INFO RMATIO N
T he power fail comparator can be used to monitor the status of
the backup battery instead of the power supply if desired. T his
is shown in Figure 20. T he PFI input samples the battery volt-
age and generates an active low PFO signal when the battery
voltage drops below a chosen threshold. It may be necessary to
apply a test load in order to determine the loaded battery volt-
age. T his can be done under processor control using CEOUT .
Since CEOUT is forced high during the battery backup mode, the
test load will not be applied to the battery while it is in use, even
if the microprocessor is not powered.
Incr easing the D r ive Cur r ent
If the continuous output current requirements at VOUT exceed
100 mA, or if a lower VCC–VOUT voltage differential is desired,
an external PNP pass transistor may be connected in parallel
with the internal transistor. T he BAT T ON output (ADM8691/
ADM8693/ADM8695) can directly drive the base of the exter-
nal transistor.
PNP TRANSISTOR
+5V INPUT
POWER
0.1µF
0.1µF
V
BATT
ON
V
OUT
CC
+5V INPUT
POWER
V
ADM8691
ADM8693
ADM8695
BATT
BATTERY
V
CC
V
BATT
PFO
BATTERY
10MΩ
10MΩ
LOW BATTERY
SIGNAL TO
µP I/O PIN
PFI
ADM869x
Figure 17. Increasing the Drive Current
20kΩ
OPTIONAL
TEST LOAD
CE
IN
Using a Rechar geable Batter y for Backup
FROM µP I/O PIN
APPLIES TEST LOAD
TO BATTERY
If a capacitor or a rechargeable battery is used for backup then
the charging resistor should be connected to VOUT since this
eliminates the discharge path that would exist during power-
CE
OUT
down if the resistor is connected to VCC
.
Figure 20. Monitoring the Battery Status
V
– V
BATT
OUT
Alter nate Watchdog Input D r ive Cir cuits
I =
R
+5V INPUT
POWER
T he watchdog feature can be enabled and disabled under pro-
gram control by driving WDI with a three-state buffer (Figure
21a). When three-stated, the WDI input will float, thereby dis-
abling the watchdog timer.
0.1µF
R
0.1µF
V
V
OUT
CC
V
BATT
RECHARGEABLE
BATTERY
ADM869x
WATCHDOG
WDI
STROBE
ADM869x
CONTROL
INPUT
Figure 18. Rechargeable Battery
Adding H yster esis to the P ower Fail Com par ator
Figure 21a. Program m ing the Watchdog Input
For increased noise immunity, hysteresis may be added to the
power fail comparator. Since the comparator circuit is nonin-
verting, hysteresis can be added simply by connecting a resistor be-
tween the PFO output and the PFI input as shown in Figure 19.
When PFO is low, resistor R3 sinks current from the summing
junction at the PFI pin. When PFO is high, the series combina-
tion of R3 and R4 source current into the PFI summing junc-
tion. T his results in differing trip levels for the comparator.
T his circuit is not entirely foolproof, and it is possible that a
software fault could erroneously three-state the buffer. T his
would then prevent the ADM869x from detecting that the mi-
croprocessor is no longer operating correctly. In most cases a
better method is to extend the watchdog period rather than dis-
abling the watchdog. T his may be done under program control
using the circuit shown in Figure 21b. When the control input is
high, the OSC SEL pin is low and the watchdog timeout is set
by the external capacitor. A 0.01 µF capacitor sets a watchdog
timeout delay of 100 seconds. When the control input is low,
the OSC SEL pin is driven high, selecting the internal oscillator.
The 100 ms or the 1.6 s period is chosen, depending on which di-
ode in Figure 21b is used. With D1 inserted, the internal timeout is
set at 100 ms; with D2 inserted the timeout is set at 1.6 s.
+5V
+7V TO +15V
7805
INPUT
POWER
R
V
4
CC
R
1
2
1.3V
PFO
TO µP NMI
PFI
ADM869x
R
R
3
CONTROL
OSC SEL
INPUT*
R
R
R
1
1
5V
V
V
= 1.3V
= 1.3V
(
1+
+
–
)
ADM869x
H
D 1
D 2
R
2
3
OSC IN
R
R
R
(5V – 1.3V)
1
1
PFO
(1+
)
4
L
1.3V (R + R )
2
3
*LOW = INTERNAL TIMEOUT
HIGH = EXTERNAL TIMEOUT
ASSUMING R < < R THEN
4
3
0V
R
R
0V
V
V
H
1
L
HYSTERESIS V – V = 5V
(
)
H
L
V
IN
2
Figure 21b. Program m ing the Watchdog Input
Figure 19. Adding Hysteresis to the Power Fail Com parator
–10–
REV. 0
ADM8690–ADM8695
TYP ICAL AP P LICATIO NS
AD M8690, AD M8692 and AD M8694
Figure 22b shows a similar application but in this case the PFI
input monitors the unregulated input to the 7805 voltage regu-
lator. T his gives an earlier warning of an impending power fail-
ure. It is useful with processors operating at low speeds or where
there are a significant number of housekeeping tasks to be com-
pleted before the power is lost.
Figure 22a shows the ADM8690/ADM8692/ADM8694 in a
typical power monitoring, battery backup application. VOUT
powers the CMOS RAM. Under normal operating conditions
with VCC present, VOUT is internally connected to VCC. If a
power failure occurs, VCC will decay and VOUT will be switched
to VBAT T thereby maintaining power for the CMOS RAM. A
RESET pulse is also generated when VCC falls below 4.65 V for
the ADM8690/ADM8694 or 4.4 V for the ADM8692. RESET
will remain low for 50 ms (200 ms for ADM8694) after VCC re-
turns to 5 V.
INPUT
POWER
V > 8V
+5V
7805
0.1µF
0.1µF
R
1
2
µP POWER
CMOS RAM
V
CC
V
PFI
OUT
POWER
R
ADM8690
ADM8692
ADM8694
µP SYSTEM
T he watchdog timer input (WDI) monitors an I/O line from the
µP system. T his line must be toggled once every 1.6 seconds to
verify correct software execution. Failure to toggle the line indi-
cates that the µP system is not correctly executing its program
and may be tied up in an endless loop. If this happens, a reset
pulse is generated to initialize the processor.
µP RESET
RESET
PFO
V
BATT
µP NMI
+
BATTERY
I/O LINE
WDI
GND
Figure 22b. ADM8690/ADM8692/ADM8694 Typical Applica-
tion Circuit B
If the watchdog timer is not needed, the WDI input should be
left floating.
AD M8691, AD M8693 and AD M8695
A typical connection for the ADM8691/ADM8693/ADM8695
is shown in Figure 23. CMOS RAM is powered from VOUT
T he Power Fail Input, PFI, monitors the input power supply via
a resistive divider network. T he voltage on the PFI input is com-
pared with a precision 1.3 V internal reference. If the input volt-
age drops below 1.3 V, a power fail output (PFO) signal is
generated. T his warns of an impending power failure and may
be used to interrupt the processor so that the system may be
shut down in an orderly fashion. T he resistors in the sensing
network are ratioed to give the desired power fail threshold
voltage VT .
.
When 5 V power is present this is routed to VOUT . If VCC fails
then VBAT T is routed to VOUT . VOUT can supply up to 100 mA
from VCC, but if more current is required, an external PNP tran-
sistor can be added. When VCC is higher than VBAT T, the BAT T
ON output goes low, providing up to 25 mA of base drive for
the external transistor. A 0.1 µF capacitor is connected to VOUT
to supply the transient currents for CMOS RAM. When VCC is
lower than VBAT T, an internal 20 Ω MOSFET connects the
VT = (1.3 R1/R2) + 1.3 V
R1/R2 = (VT/1.3) – 1
backup battery to VOUT
.
INPUT POWER
+5V
+5V
R
R
1
V
CC
µP POWER
CMOS RAM
0.1µF
0.1µF
V
PFI
OUT
V
V
BATT
ON
CC
OUT
POWER
CMOS
RAM
ADM8690
ADM8692
ADM8694
0.1µF
CE
3V
2
OUT
V
BATT
BATTERY
µP SYSTEM
ADM8691
ADM8693
ADM8695
ADDRESS
DECODE
R
R
CE
1
IN
µP RESET
RESET
V
BATT
PFI
µP NMI
PFO
A0–A15
I/O LINE
+
GND
BATTERY
WDI
I/O LINE
2
WDI
GND
µP
NC
OSC IN
PFO
NMI
OSC SEL
RESET
RESET
LOW LINE WDO
RESET
Figure 22a. ADM8690/ADM8692/ADM8694 Typical Applica-
tion Circuit A
0.1µF
SYSTEM STATUS
INDICATORS
Figure 23. ADM8691/ADM8693/ADM8695 Typical
Application
REV. 0
–11–
ADM8690–ADM8695
RESET O utput
RAM Wr ite P r otection
T he internal voltage detector monitors VCC and generates a
RESET output to hold the microprocessor’s Reset line low
when VCC is below 4.65 V (4.4 V for ADM8693). An internal
timer holds RESET low for 50 ms (200 ms for the ADM8695)
after VCC rises above 4.65 V (4.4 V for ADM8693). T his pre-
vents repeated toggling of RESET even if the 5 V power drops
out and recovers with each power line cycle.
T he ADM8691/ADM8693/ADM8695 CEOUT line drives the
Chip Select inputs of the CMOS RAM. CEOUT follows CEIN as
long as VCC is above the 4.65 V (4.4 V for ADM8693) reset
threshold.
If VCC falls below the reset threshold, CEOUT goes high, inde-
pendent of the logic level at CEIN. T his prevents the micropro-
cessor from writing erroneous data into RAM during power-up,
power-down, brownouts and momentary power interruptions.
T he crystal oscillator normally used to generate the clock for
microprocessors can take several milliseconds to stabilize. Since
most microprocessors need several clock cycles to reset, RESET
must be held low until the microprocessor clock oscillator has
started. T he power-up RESET pulse lasts 50 ms (200 ms for the
ADM8695) to allow for this oscillator start-up time. If a differ-
ent reset pulse width is required, then a capacitor should be
connected to OSC IN or an external clock may be used. Please
refer to T able I and Figure 4. T he manual reset switch and the
0.1 µF capacitor connected to the reset line can be omitted if a
manual reset is not needed. An inverted, active high, RESET
output is also available.
Watchdog Tim er
T he microprocessor drives the Watchdog Input (WDI) with an
I/O line. When OSC IN and OSC SEL are unconnected, the
microprocessor must toggle the WDI pin once every 1.6 seconds
to verify proper software execution. If a hardware or software
failure occurs such that WDI is not toggled, the ADM8691/
ADM8693 will issue a 50 ms (200 ms for ADM8695) RESET
pulse after 1.6 seconds. T his typically restarts the micro-
processor’s power-up routine. A new RESET pulse is issued
every 1.6 seconds until WDI is again strobed. If a different
watchdog timeout period is required, then a capacitor should be
connected to OSC IN or an external clock may be used. Please
refer to T able I and Figure 4.
P ower Fail D etector
T he +5 V VCC power line is monitored via a resistive potential
divider connected to the Power Fail Input (PFI). When the
voltage at PFI falls below 1.3 V, the Power Fail Output (PFO)
drives the processor’s NMI input low. If for example a Power
Fail threshold of 4.8 V is set with resistors R1 and R2, the micro-
processor will have the time when VCC falls from 4.8 V to 4.65 V
to save data into RAM. An earlier power fail warning can be gen-
erated if the unregulated dc input to the 5 V regulator is avail-
able for monitoring. T his will allow more time for micro-
processor housekeeping tasks to be completed before power is
lost.
T he Watchdog Output (WDO) goes low if the watchdog timer
is not serviced within its timeout period. Once WDO goes low,
it remains low until a transition occurs at WDI. T he watchdog
timer feature can be disabled by leaving WDI unconnected.
T he RESET output has an internal 3 µA pull-up, and can either
connect to an open collector reset bus or directly drive a CMOS
gate without an external pull-up resistor.
–12–
REV. 0
ADM8690–ADM8695
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
8-P in P lastic D IP
(N-8)
0.430 (10.92)
0.348 (8.84)
8
5
4
0.280 (7.11)
0.240 (6.10)
1
0.325 (8.25)
0.300 (7.62)
0.060 (1.52)
0.015 (0.38)
PIN 1
0.195 (4.95)
0.115 (2.93)
0.210 (5.33)
MAX
0.150
(3.81)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
SEATING
PLANE
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
0.008 (0.204)
16-Lead P lastic D IP
(N-16)
0.840 (21.33)
0.745 (18.93)
16
1
9
8
0.280 (7.11)
0.240 (6.10)
0.325 (8.25)
0.300 (7.62)
0.195 (4.95)
0.115 (2.93)
PIN 1
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
0.150
(3.81)
0.200 (5.05)
0.125 (3.18)
0.015 (0.381)
0.008 (0.204)
0.070 (1.77) SEATING
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
PLANE
0.045 (1.15)
REV. 0
–13–
ADM8690–ADM8695
8-Lead Sm all O utline
(SO -8)
0.1968 (5.00)
0.1890 (4.80)
8
1
5
4
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.0688 (1.75)
0.0532 (1.35)
0.0196 (0.50)
0.0099 (0.25)
x 45°
0.0098 (0.25)
0.0040 (0.10)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
16-Lead Sm all O utline (Wide Body)
(R-16)
0.413 (10.50)
16
9
8
0.419
(10.65)
0.299
(7.60)
1
0.104
(2.65)
PIN 1
0.030 (0.75)
0.013 (0.32)
0.012
(0.3)
0.042 (1.07)
0.05 (1.27)
BSC
0.019 (0.49)
SEATING
PLANE
16-Lead Sm all O utline (Narrow Body)
(R-16A)
0.3937 (10.00)
0.3859 (9.80)
16
1
9
8
0.1574 (4.00)
0.1497 (5.80)
0.2550 (6.20)
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
PIN 1
0.0196 (0.50)
0.0099 (0.25)
x 45°
0.0098 (0.25)
0.0040 (0.10)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
SEATING
PLANE
0.0500 (1.27)
0.0160 (0.41)
0.0099 (0.25)
0.0075 (0.19)
0.0138 (0.35)
–14–
REV. 0
ADM8690–ADM8695
16-Lead Thin Shr ink Sm all O utline
(RU-16)
0.201 (5.10)
0.193 (4.90)
16
9
1
8
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0433
(1.10)
MAX
0.028 (0.70)
0.020 (0.50)
8°
0°
0.0118 (0.30)
0.0075 (0.19)
0.0256
(0.65)
BSC
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
REV. 0
–15–
–16–
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