ADM8697_15 [ADI]
Microprocessor Supervisory Circuits;
| 型号： | ADM8697_15 |
| 厂家： | 
ADI |
| 描述： | Microprocessor Supervisory Circuits |
| 文件： | 总13页 (文件大小：290K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Microprocessor
Supervisory Circuits
a
ADM8696/ADM8697
FUNCTIO NAL BLO CK D IAGRAMS
FEATURES
Upgrade for ADM696/ ADM697, MAX696/ MAX697
Specified Over Tem perature
BATT ON
V
Adjustable Low Line Voltage Monitor
Pow er OK/ Reset Tim e Delay
BATT
V
OUT
Reset Assertion Dow n to 1 V VCC
Watchdog Tim er—100 m s, 1.6 s, or Adjustable
Low Sw itch On Resistance
0.7 ⍀ Norm al, 7 ⍀ in Backup
400 nA Standby Current
Autom atic Battery Backup Sw itching (ADM8696)
Fast On-Board Gating of Chip Enable Signals (ADM8697)
Voltage Monitor for Pow er Fail or Low Battery Warning
Also Available in TSSOP Package
Qualified for Automotive Applications
V
CC
LL
IN
LOW LINE
RESET
RESET GENERATOR
RESET
OSC IN
TIMEBASE FOR RESET
AND WATCHDOG
OSC SEL
WATCHDOG
OUTPUT (WDO)
WATCHDOG
TIMER
APPLICATIONS
Microprocessor Systems
Computers
Controllers
Intelligent Instruments
Automotive Systems
Critical µP Power Monitoring
WATCHDOG
INPUT (WDI)
WATCHDOG
TRANSITION DETECTOR
ADM8696
POWER FAIL
INPUT (PFI)
POWER FAIL
OUTPUT (PFO)
1.3V
GENERAL D ESCRIP TIO N
CE
LL
IN
CE
T he ADM8696/ADM8697 supervisory circuits offer complete
single chip solutions for power supply monitoring and battery
control functions in microprocessor systems. T hese functions
include µP reset, backup battery switchover, watchdog timer,
CMOS RAM write protection and power failure warning.
OUT
IN
LOW LINE
RESET
RESET GENERATOR
RESET
T he ADM8696/ADM8697 are available in 16-pin DIP and small
outline packages (including T SSOP) and provide the following
functions:
OSC IN
TIMEBASE FOR RESET
AND WATCHDOG
OSC SEL
WATCHDOG
OUTPUT (WDO)
WATCHDOG
TIMER
1. Power-On Reset output during power-up, power-down and
brownout conditions. T he RESET voltage threshold is
adjustable using an external voltage divider. T he RESET out-
put remains operational with VCC as low as 1 V.
WATCHDOG
INPUT (WDI)
WATCHDOG
TRANSITION DETECTOR
ADM8697
POWER FAIL
INPUT (PFI)
POWER FAIL
OUTPUT (PFO)
2. A Reset pulse if the optional watchdog timer has not been
toggled within specified time.
1.3V
3. Separate watchdog timeout and low line status outputs.
4. Adjustable reset and watchdog timeout periods.
T he ADM8696/ADM8697 is fabricated using an advanced
epitaxial CMOS process combining low power consumption
(0.7 mW), extremely fast Chip Enable gating (2 ns) and high re-
liability. RESET assertion is guaranteed with VCC as low as 1 V.
In addition, the power switching circuitry is designed for mini-
mal voltage drop thereby permitting increased output current drive
of up to 100 mA without the need for an external pass transistor.
5. A 1.3 V threshold detector for power fail warning, low battery
detection or to monitor a power supply other than VCC
.
6. Battery backup switching for CMOS RAM, CMOS micro-
processor or other low power logic (ADM8696).
7. Write protection of CMOS RAM or EEPROM (ADM8697).
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
©1997-2010 Analog Devices, Inc. All rights reserved.
(V = Full Operating Range, VBATT = +2.8 V, T = TMIN to T
MAX
CC
A
ADM8696/ADM8697–SPECIFICATIONS unless otherwise noted.)
P
aram eter
Min
Typ
Max
Units Test Conditions/Com m ents
VCC Operating Voltage Range
VBAT T Operating Voltage Range
3.0
2.0
5.5
VCC – 0 3
V
V
BAT T ERY BACKUP SWITCHING (ADM8696)
VOUT Output Voltage
VCC – 0.005
VCC – 0.2
VCC – 0.0025
VCC – 0.125
V
V
IOUT = 1 mA
IOUT ≤ 100 mA
VOUT in Battery Backup Mode
Supply Current (Excludes IOUT
Supply Current in Battery Backup Mode
Battery Standby Current
VBAT T – 0.005 VBAT T – 0.002
V
µA
µA
IOUT = 250 µA, VCC < VBAT T – 0.2 V
IOUT = 100 mA
VCC = 0 V, VBAT T = 2.8 V
5.5 V > VCC > VBAT T + 0.2 V
)
115
0.4
200
1
(+ = Discharge, – = Charge)
Battery Switchover T hreshold
VCC – VBAT T
Battery Switchover Hysteresis
BAT T ON Output Voltage
BAT T ON Output Short Circuit Current
–0.1
+0.02
µA
70
50
20
mV
mV
mV
V
mA
µA
Power-Up
Power-Down
0.3
25
ISINK = 3.2 mA
BAT T ON = VOUT = 2.4 V Sink Current
BAT T ON = VOUT, VCC = 0 V, Source Current
30
2.5
0.5
RESET AND WAT CHDOG T IMER
Low Line T hreshold (LLIN
Reset T imeout Delay
)
1.25
35
1.0
70
4032
960
50
1.3
50
1.6
100
4063
1011
1.35
70
2.25
140
4097
1025
V
ms
s
OSC SEL = HIGH
Long Period
Short Period
Watchdog T imeout Period, Internal Oscillator
Watchdog T imeout Period, External Clock
Minimum WDI Input Pulse Width
ms
Cycles Long Period
Cycles Short Period
ns
ns
ns
mV
V
V
V
V
V
VIL = 0.8, VIH = 3.75 V, VCC = 5 V
100
VIL = 0.8, VIH = 3.5 V, VCC = 5 V
VIL = 0.8, VIH = 2.6 V, VCC = 3 V
ISINK = 10 µA, VCC = 1 V
ISINK = 400 µA, VCC = 2 V, VBAT T = 0 V
ISINK = 3.2 mA, 3 V < VCC < 5.5 V
ISOURCE = 1 µA, VCC = 5 V
ISOURCE = 1 µA, VCC = 3 V
ISINK = 3.2 mA,
100
4
0.1
0.1
RESET Output Voltage @ VCC = +1 V
RESET , RESET Output Voltage
20
0.4
0.4
3.5
2.7
LOW LINE, WDO Output Voltage
0.4
3.5
1
V
V
µA
ISOURCE = 1 µA, VCC = 5 V
ISOURCE = 1 µA, VCC = 3 V
VCC = 5 V
2.7
10
Output Short Circuit Source Current
WDI Input T hreshold1
Logic Low
25
0.8
V
Logic High
3.5
V
V
µA
µA
VCC = 5 V
VCC = 3 V
WD1 = VOUT, (VCC
WD1 = 0 V
1.2
1
–1
WDI Input Current
10
)
–10
POWER FAIL DET ECT OR
PFI Input T hreshold
1.2
1.3
1.4
V
PFI–LLIN T hreshold Difference
PFI Input Current
LLIN Input Current
–50
–25
–50
±15
±0.01
±0.01
+50
+25
+50
0.4
mV
nA
nA
V
PFO Output Voltage
ISINK = 3.2 mA
3.5
1
V
V
µA
ISOURCE = 1 µA
ISOURCE = 1 µA, VCC = 3 V
PFI = Low, PFO = 0 V
2.7
10
PFO Short Circuit Source Current
25
CHIP ENABLE GAT ING (ADM8697)
CEIN T hreshold
0.8
V
VIL
3.0
V
VIH
1.2
3
V
µA
V
V
ns
ns
VCC = 3 V
CEIN Pull-Up Current
CEOUT Output Voltage
0.4
7
ISINK = 3.2 mA
ISOURCE = 800 µA
VCC = 5.0 V
VCC – 0.5
CE Propagation Delay
2
4
VCC = 3.0 V
OSCILLAT OR
OSC IN Input Current
±2
µA
µA
kHz
kHz
OSC SEL Input Pull-Up Current
OSC IN Frequency Range
OSC IN Frequency with Ext. Capacitor
5
0
500
OSC SEL = 0 V
OSC SEL = 0 V, COSC = 47 pF
4
NOT E
1WDI is a three-level input internally biased to 38% of VCC and has an input impedance of approximately 5 M Ω.
Specifications subject to change without notice.
REV. A
–2–
ADM8696/ADM8697
Power Dissipation, R-16 SOIC . . . . . . . . . . . . . . . . . . 600 mW
θJA T hermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W
Operating T emperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead T emperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
Storage T emperature Range . . . . . . . . . . . . . –65°C to +150°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. T his is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum ratings for
extended periods of time may affect device reliability.
ABSO LUTE MAXIMUM RATINGS*
(T A = +25°C unless otherwise noted)
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
VBAT T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
All Other Inputs . . . . . . . . . . . . . . . . . . –0.3 V to VOUT + 0.5 V
Input Current
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
VBAT T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Power Dissipation, N-16 DIP . . . . . . . . . . . . . . . . . . . 600 mW
θJA T hermal Impedance . . . . . . . . . . . . . . . . . . . . . 135°C/W
Power Dissipation, RU-16 T SSOP . . . . . . . . . . . . . . . 500 mW
θJA T hermal Impedance . . . . . . . . . . . . . . . . . . . . . 158°C/W
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADM8696/ADM8697 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. T herefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
P IN CO NFIGURATIO NS
1
2
3
4
5
6
16
15
14
V
RESET
RESET
WDO
BATT
V
OUT
V
CC
ADM8696
TOP VIEW
(Not to Scale)
GND
LL
IN
13
12
11
10
9
NC
BATT ON
LOW LINE
WDI
PFO
PFI
7
8
OSC IN
OSC SEL
16
15
14
13
TEST
NC
1
RESET
RESET
WDO
2
3
4
5
6
7
8
V
CC
ADM8697
TOP VIEW
(Not to Scale)
LL
IN
CE
IN
12
11
10
9
CE
GND
OUT
LOW LINE
WDI
PFO
PFI
OSC IN
OSC SEL
REV. A
–3–
ADM8696/ADM8697
P IN FUNCTIO N D ESCRIP TIO N
P in No.
Mnem onic AD M8696 AD M8697 Function
VCC
3
1
2
3
Power Supply Input +3 V to +5 V.
Backup Battery Input.
VBAT T
VOUT
—
—
Output Voltage, VCC or VBAT T is internally switched to VOUT depending on which is at
the highest potential. When VCC is higher than VBAT T and LLIN is higher than the reset
threshold, VCC is switched to VOUT . When VCC is lower than VBAT T and LLIN is below the
reset threshold, VBAT T is switched to VOUT . VOUT can supply up to 100 mA to power CMOS
RAM. Connect VOUT to VCC if VOUT and VBAT T are not used.
GND
4
5
0 V. Ground reference for all signals.
RESET
15
15
Logic Output. RESET goes low whenever LLIN falls below 1.3 V and remains low for 50 ms
after LLIN goes above 1.3 V. RESET also goes low for 50 ms if the watchdog timer is en-
abled but not serviced within its timeout period. T he RESET pulse width can be adjusted as
shown in T able I.
WDI
11
11
Watchdog Input, WDI is a three level input. If WDI remains either high or low for longer
than the watchdog timeout period, RESET pulses low and WDO goes low. T he timer resets
with each transition at the WDI input. T he watchdog timer is disabled when WDI is left
floating or is driven to midsupply.
PFI
9
9
Power Fail Input. PFI is the noninverting input to the Power Fail Comparator when PFI is
less than 1.3 V, PFO goes low. Connect PFI to GND or VOUT when not used. See Figure 1.
PFO
10
10
Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI
is less than 1.3 V. T he comparator is turned off and PFO goes low when VCC is below
VBAT T
.
CEIN
—
—
13
12
Logic Input. T he input to the CE gating circuit. Connect to GND or VOUT if not used.
CEOUT
Logic Output. CEOUT is a gated version of the CEIN signal. CEOUT tracks CEIN when LLIN
is above 1.3 V. If LLIN is below 1.3 V, CEOUT is forced high.
BAT T ON
5
—
Logic Output. BAT T ON goes high when VOUT is internally switched to the VBAT T input.
It goes low when VOUT is internally switched to VCC. T he output typically sinks 7 mA and
can directly drive the base of an external PNP transistor to increase the output current above
the 100 mA rating of VOUT
.
LOW LINE
6
6
Logic Output. LOW LINE goes low when LLIN falls below 1.3 V. It returns high as soon as
LLIN rises above 1.3 V.
RESET
16
8
16
8
Logic Output. RESET is an active high output. It is the inverse of RESET.
OSC SEL
Logic Oscillator Select Input. When OSC SEL is unconnected or driven high, the internal
oscillator sets the reset time delay and watchdog timeout period. When OSC SEL is low, the
external oscillator input, OSC IN, is enabled. OSC SEL has a 3 µA internal pull-up. See
T able I and Figure 4.
OSC IN
7
7
Logic Oscillator Input. When OSC SEL is low, OSC IN can be driven by an external clock
to adjust both the reset delay and the watchdog timeout period. T he timing can also be
adjusted by connecting an external capacitor to this pin. See Table I and Figure 4. When
OSC SEL is high or floating, OSC IN selects between fast and slow watchdog timeout periods.
WDO
14
14
Logic Output. T he Watchdog Output, WDO, goes low if WDI remains either high or low
for longer than the watchdog timeout period. WDO is set high by the next transition at
WDI. If WDI is unconnected or at midsupply, WDO remains high. WDO also goes high
when LOW LINE goes low.
NC
12
13
2
4
No Connect. It should be left open.
LLIN
Voltage Sensing Input. T he voltage on the low line input, LLIN, is compared with a 1.3 V
reference voltage. T his input is normally used to monitor the power supply voltage. T he
output of the comparator generates a LOW LINE output signal. It also generates a
RESET /RESET output. The comparator output also controls the battery switchover circuitry.
T EST
—
1
T his is a special test pin using during device manufacture. It should be connected to GND.
REV. A
–4–
ADM8696/ADM8697
CIRCUIT INFO RMATIO N
Batter y Switchover Section (AD M8696)
Low Line RESET O UTP UT
RESET is an active low output that provides a RESET signal to
the microprocessor whenever the Low Line Input (LLIN) is be-
low 1.3 V. T he LLIN input is normally used to monitor the
power supply voltage. An internal timer holds RESET low for
50 ms after the voltage on LLIN rises above 1.3 V. T his is in-
tended as a power-on RESET signal for the processor. It allows
time for the power supply and microprocessor to stabilize. On
power-down, the RESET output remains low, with VCC as low
as 1 V. T his ensures that the microprocessor is held in a stable
shutdown condition.
The battery switchover circuit is designed to switch over to
battery backup in the event of a power failure. When LLIN
is below the reset threshold and VCC is below VBAT T , then
VBAT T is switched to VOUT
.
During normal operation, with VCC higher than VBAT T, VCC is
internally switched to VOUT via an internal PMOS transistor
switch. T his switch has a typical on resistance of 0.7 Ω and can
supply up to 100 mA at the VOUT terminal. VOUT is normally
used to drive a RAM memory bank which may require instanta-
neous currents of greater than 100 mA. If this is the case, then
a bypass capacitor should be connected to VOUT . T he capacitor
will provide the peak current transients to the RAM. A capaci-
tance value of 0.1 µF or greater may be used.
T he LLIN comparator has approximately 12 mV of hysteresis
for enhanced noise immunity.
In addition to RESET, an active high RESET output is also
available. T his is the complement of RESET and is useful for
processors requiring an active high RESET .
If the continuous output current requirement at VOUT exceeds
100 mA or if a lower VCC–VOUT voltage differential is desired,
an external PNP pass transistor may be connected in parallel
with the internal transistor. T he BAT T ON output can directly
drive the base of the external transistor.
V2
V2
LLIN
V1
V1
A 7 Ω MOSFET switch connects the VBAT T input to VOUT dur-
ing battery backup. T his MOSFET has very low input-to-out-
put differential (dropout voltage) at the low current levels
required for battery backup of CMOS RAM or other low power
CMOS circuitry. T he supply current in battery backup is typi-
cally 0.4 µA.
t1
t
1
RESET
LOW LINE
t1 = RESET TIME
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1
T he ADM8696 operates with battery voltages from 2.0 V to
VCC–0.3 V). High value capacitors, either standard electrolytic
or the farad-size double layer capacitors, can also be used for
short-term memory backup. A small charging current of typi-
cally 10 nA (0.1 µA max) flows out of the VBAT T terminal. T his
current is useful for maintaining rechargeable batteries in a fully
charged condition. T his extends the life of the backup battery
by compensating for its self-discharge current. Also note that
this current poses no problem when lithium batteries are used
for backup since the maximum charging current (0.1 µA) is safe
for even the smallest lithium cells.
Figure 2. Power-Fail Reset Tim ing
Watchdog Tim er RESET
T he watchdog timer circuit monitors the activity of the micro-
processor in order to check that it is not stalled in an indefinite
loop. An output line on the processor is used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within
the selected timeout period, a RESET pulse is generated. T he
ADM8696/ADM8697 may be configured for either a fixed
“short” 100 ms or a “long” 1.6 second timeout period or for an
adjustable timeout period. If the “short” period is selected,
some systems may be unable to service the watchdog timer im-
mediately after a reset, so a “long” timeout is automatically ini-
tiated directly after a reset is issued. T he watchdog timer is
restarted at the end of Reset, whether the Reset was caused by
lack of activity on WDI or by LLIN falling below the reset
threshold.
If the battery switchover section is not used, VBAT T should be
connected to GND and VOUT should be connected to VCC
.
V
CC
V
OUT
V
BATT
GATE DRIVE
100
T he normal (short) timeout period becomes effective following
the first transition of WDI after RESET has gone inactive. T he
watchdog timeout period restarts with each transition on the
WDI pin. T o ensure that the watchdog timer does not time out,
either a high-to-low or low-to-high transition on the WDI pin
must occur at or less than the minimum timeout period. If WDI
remains permanently either high or low, reset pulses will be is-
sued after each timeout period (1.6 s). T he watchdog monitor
can be deactivated by floating the Watchdog Input (WDI) or by
connecting it to midsupply.
mV
BATT ON
(ADM8691, ADM8693,
ADM8695, ADM8696)
700
mV
INTERNAL
SHUTDOWN SIGNAL
WHEN
V
> (V + 0.7V)
BATT
CC
Figure 1. Battery Switchover Schem atic
REV. A
–5–
ADM8696/ADM8697
Table I. AD M8696, AD M8697 Reset P ulse Width and Watchdog Tim eout Selections
Watchdog Tim eout P eriod
Im m ediately After Reset
Reset Active P eriod
O SC SEL
O SC IN
Norm al
Low
Low
Floating or High
Floating or High
External Clock Input
External Capacitor
Low
1024 CLKS
400 ms × C/47 pF
100 ms
4096 CLKS
1.6 s × C/47 pF
1.6 s
512 CLKS
200 ms × C/47 pF
50 ms
Floating or High
1.6 s
1.6 s
50 ms
NOT E
With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor can be connected between OSC IN and GND. T he nominal
internal oscillator frequency is 10.24 kHz. T he nominal oscillator frequency with external capacitor is: F OSC (Hz) = 184,000/C (pF).
WDI
8
7
OSC SEL
OSC IN
ADM869x
WDO
COSC
t3
t2
Figure 4b. External Capacitor
RESET
t1
t1
1 = RESET TIME
2 = NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD
3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET
t1
NC
8
7
OSC SEL
OSC IN
t
t
t
ADM869x
NC
Figure 3. Watchdog Tim eout Period and Reset Active Tim e
T he watchdog timeout period defaults to 1.6 s and the reset
pulse width defaults to 50 ms, but these times to be adjusted as
shown in T able I. Figure 4 shows the various oscillator configu-
rations that can be used to adjust the reset pulse width and
watchdog timeout period.
Figure 4c. Internal Oscillator (1.6 s Watchdog)
NC
8
7
OSC SEL
OSC IN
ADM869x
T he internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects between the 1.6 second
and 100 ms watchdog timeout periods. In either case, immedi-
ately after a reset the timeout period is 1.6 s. T his gives the mi-
croprocessor time to reinitialize the system. If OSC IN is low,
the 100 ms watchdog period becomes effective after the first
transition of WDI. T he software should be written such that the
I/O port driving WDI is left in its power-up reset state until the
initialization routines are completed and the microprocessor is
able to toggle WDI at the minimum watchdog timeout period of
70 ms.
Figure 4d. Internal Oscillator (100 m s Watchdog)
Watchdog O utput (WDO)
T he Watchdog Output WDO provides a status output that goes
low if the watchdog timer “times out” and remains low until set
high by the next transition on the watchdog input. WDO is also
set high when LLIN goes below the reset threshold.
8
7
OSC SEL
OSC IN
ADM869x
CLOCK
0 TO 500kHz
Figure 4a. External Clock Source
REV. A
–6–
ADM8696/ADM8697
CE Gating and RAM Wr ite P r otection (AD M8697)
can be chosen such that the voltage at PFI falls below 1.3 V
several milliseconds before the +5 V power supply falls below
the reset threshold. PFO is normally used to interrupt the
microprocessor so that data can be stored in RAM and the shut-
down procedure executed before power is lost.
T he ADM8697 contains memory protection circuitry that
ensures the integrity of data in memory by preventing write
operations when LLIN is below the threshold voltage. When
LLIN is greater than 1.3 V, CEOUT is a buffered replica of CEIN
,
with a 2 ns propagation delay. When LLIN falls below the 1.3 V
threshold, an internal gate forces CEOUT high, independent of
INPUT
ADM869x
POWER
CEIN
.
R1
1.3V
PFO
CEOUT typically drives the CE, CS or Write input of battery
backed up CMOS RAM. T his ensures the integrity of the data
in memory by preventing write operations when VCC is at an in-
valid level.
POWER
FAIL
OUTPUT
POWER
FAIL
INPUT
R2
Figure 7. Power Fail Com parator
Table II. Input and O utput Status In Battery Backup Mode
ADM8697
CE
IN
CE
OUT
LL LOW = 0
IN
Signal
Status
LL OK = 1
IN
VOUT
(ADM8696) VOUT is connected to VBAT T via an
internal PMOS switch.
Figure 5. Chip Enable Gating
RESET
Logic low.
RESET
Logic high. T he open circuit output voltage is
V2
V2
LL
V1
equal to VOUT
.
IN
V1
LOW LINE Logic low.
t1
t
1
RESET
BAT T ON
WDI
(ADM8696) Logic high. T he open circuit volt-
age is equal to VOUT
.
WDI is ignored. It is internally disconnected
from the internal pull-up resistor and does not
source or sink current as long as its input voltage
is between GND and VOUT . T he input voltage
does not affect supply current.
LOW LINE
CE
IN
WDO
Logic high. T he open circuit voltage is equal to
VOUT
.
CE
PFI
T he Power Fail Comparator is turned off and
has no effect on the Power Fail Output.
OUT
t1 = RESET TIME
PFO
CEIN
Logic low.
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1
CEIN is ignored. It is internally disconnected
from its internal pull-up and does not source or
sink current as long as its input voltage is be-
tween GND and VOUT . T he input voltage does
not affect supply current.
Figure 6. Chip Enable Tim ing
P ower Fail War ning Com par ator
An additional comparator is provided for early warning of fail-
ure in the microprocessor’s power supply. T he Power Fail Input
(PFI) is compared to an internal +1.3 V reference. T he Power
CEOUT
Logic high. T he open circuit voltage is equal to
VOUT
.
Fail Output (PFO) goes low when the voltage at PFI is less than
1.3 V. T ypically PFI is driven by an external voltage divider
which senses either the unregulated dc input to the system’s 5 V
regulator or the regulated 5 V output. T he voltage divider ratio
OSC IN
OSC IN is ignored.
OSC SEL is ignored.
OSC SEL
REV. A
–7–
ADM8696/ADM8697–Typical Performance Curves
5
53
V
CC
= +5V
4.99
4.98
4.97
4.96
4.95
4.94
52
51
50
49
10
20
30
40
50
I
60
70
80
90
100
– mA
20
40
60
80
100
120
OUT
TEMPERATURE –
°C
Figure 8. VOUT vs. IOUT Norm al Operation
Figure 11. RESET Active Tim e vs. Tem perature
2.8
A4
3.36 V
2.798
100
90
2.796
2.794
2.792
2.79
10
2.788
2.786
0%
150
250
350
450
550
I
650
– µA
750
850
950 1050
1V
500ms
1V
OUT
Figure 9. VOUT vs. IOUT Battery Backup
Figure 12. RESET Output Voltage vs. Supply Voltage
1.32
1.31
1.30
1.29
5.5
T
= +25°C
A
5.0
4.5
4.0
3.5
3.0
2.5
2.0
20
40
60
80
100
120
10
100
1000
10000
TEMPERATURE –
°
C
TIME DELAY – ms
Figure 10. PFI Input Threshold vs. Tem perature
Figure 13. RESET Tim eout Delay vs. VCC
REV. A
–8–
ADM8696/ADM8697
AP P LICATIO NS INFO RMATIO N
Incr easing the D r ive Cur r ent (AD M8696)
T his circuit is not entirely foolproof and it is possible a software
fault could erroneously three-state the buffer. T his would pre-
vent the ADM869x from detecting that the microprocessor is no
longer operating correctly. In most cases, a better method is to
If the continuous output current requirements at VOUT exceeds
100 mA or if a lower VCC–VOUT voltage differential is desired,
an external PNP pass transistor may be connected in parallel
with the internal transistor. The BATT ON output (ADM8696)
can directly drive the base of the external transistor.
+7V TO +15V
INPUT
+5V
7805
POWER
PNP
TRANSISTOR
V
CC
R4
+5V
INPUT
POWER
R1
R2
1.3V
PFO
TO
µP NMI
0.1µF
0.1µF
PFI
V
V
BATT
ON
OUT
CC
ADM869x
V
BATT
R3
ADM8696
BATTERY
R
R
1
1
V
H
= 1.3V (1+ ––– + ––– )
R
R
R
3
2
R
(5V – 1.3V)
Figure 14. Increasing the Drive Current
1
1
V
L
= 1.3V (1+ ––– – ––––––––––––– )
R
1.3V (R R )
2
3 +
4
Using a Rechar geable Batter y for Backup (AD M8696)
If a capacitor or a rechargeable battery is used for backup, the
charging resistor should be connected to VOUT since this elimi-
nates the discharge path that would exist during power-down if
ASSUMING R < < R THEN
4
3
R
1
HYSTERESIS V – V = 5V (––– )
H
L
R
2
Figure 16. Adding Hysteresis to the Power Fail Com parator
the resistor is connected to VCC
.
extend the watchdog period rather than disabling the watchdog.
T his may be done under program control using the circuit
shown in Figure 17b. When the control input is high, the OSC
SEL pin is low and the watchdog timeout is set by the external
capacitor. A 0.01 µF capacitor sets a watchdog timeout delay of
100 s. When the control input is low, the OSC SEL pin is
driven high, selecting the internal oscillator. T he 100 ms or the
1.6 s period is chosen, depending on which diode in Fig-
ure 17b is used. With D1 inserted, the internal timeout is set at
100 ms while with D2 inserted the timeout is set at 1.6 s.
VOUT – VBATT
I =
R
+5V
INPUT
POWER
R
0.1µF
0.1µF
VCC
VBATT
VOUT
RECHARGABLE
BATTERY
ADM8696
WATCHDOG
Figure 15. Rechargeable Battery
WDI
STROBE
ADM869x
Adding H yster esis to the P ower Fail Com par ator
CONTROL
INPUT
For increased noise immunity, hysteresis may be added to the
power fail comparator. Since the comparator circuit is nonin-
verting, hysteresis can be added by connecting a resistor be-
tween the PFO output and the PFI input as shown in Fig-
ure 16. When PFO is low, resistor R3 sinks current from the
summing junction at the PFI pin. When PFO is high, the series
combination of R3 and R4 source current into the PFI summing
junction. T his results in differing trip levels for the comparator.
Figure 17a. Program m ing the Watchdog Input
CONTROL
OSC SEL
INPUT*
ADM869x
D1
D2
OSC IN
Alter nate Watchdog Input D r ive Cir cuits
T he watchdog feature can be enabled and disabled under pro-
gram control by driving WDI with a three-state buffer (Figure
17a). When three-stated, the WDI input will float, thereby dis-
abling the watchdog timer.
*LOW = INTERNAL TIMEOUT
HIGH = EXTERNAL TIMEOUT
Figure 17b. Program m ing the Watchdog Input
REV. A
–9–
ADM8696/ADM8697
TYP ICAL AP P LICATIO NS
AD M8696
Figure 18b shows a similar application for the ADM8696 but in
this case the PFI input monitors the unregulated input to the
7805 voltage regulator. T his gives an earlier warning of an im-
pending power failure. It is useful with processors operating at
low speeds or where there are a significant number of house-
keeping tasks to be completed before the power is lost.
Figure 18 shows the ADM8696 in a typical power monitoring,
battery backup application. VOUT powers the CMOS RAM.
Under normal operating conditions with VCC present, VOUT is
internally connected to VCC. If a power failure occurs, VCC will
decay and VOUT will be switched to VBAT T, thereby maintaining
power for the CMOS RAM.
INPUT
POWER
7805
P ower Fail RESET
T he VCC power supply is also monitored by the Low Line In-
put, LLIN. A RESET pulse is generated when LLIN falls below
1.3 V. RESET will remain low for 50 ms after LLIN returns
above 1.3 V. T his allows for a power-on reset and prevents re-
peated toggling of RESET if the VCC power supply is unstable.
Resistors R3 and R4 should be chosen to give the desired VCC
reset threshold.
0.1µF
0.1µF
V
BATT
ON
V
OUT
CC
3V
BATTERY
V
CC
V
BATT
CMOS RAM
R1
R2
ADM8696
PFI
µP
POWER
A0–A15
I/O LINE
NMI
GND
WDI
Watchdog Tim er
R3
R4
OSC IN
PFO
µP
T he Watchdog T imer Input (WDI) monitors an I/O line from
the µP system. T his line must be toggled once every 1.6 s to
verify correct software execution. Failure to toggle the line indi-
cates that the µP system is not correctly executing its program
and may be tied up in an endless loop. If this happens, a reset
pulse is generated to initialize the processor.
NC
OSC SEL
RESET
RESET
LL
IN
RESET
LOW LINE WDO
SYSTEM STATUS
INDICATORS
If the watchdog timer is not needed the WDI input should be
left floating.
Figure 18b. ADM8696 Typical Application Circuit B
P ower Fail D etector
T his application also shows an optional external transistor that
T he Power Fail Input, PFI, monitors the input power supply via
a resistive divider network R1 and R2. T his input is intended as
an early warning power fail input. T he voltage on the PFI input
is compared with a precision 1.3 V internal reference. If the in-
put voltage drops below 1.3 V, a power fail output (PFO) signal
is generated. T his warns of an impending power failure and may
be used to interrupt the processor so that the system may be
shut down in an orderly fashion. T he resistors in the sensing
network are ratioed to give the desired power fail threshold volt-
age VT . T he threshold should be set at a higher voltage than the
RESET threshold so there is sufficient time available to com-
plete the shutdown procedure before the processor is RESET
and power is lost.
may be used to provide in excess of 100 mA current on VOUT
When VCC is higher than VBAT T, the BAT T ON output goes
low, providing 25 mA of base drive for the external PNP transis-
tor. T he maximum current available is dependent on the power
rating of the external transistor.
.
RAM Wr ite P r otection
T he ADM8697 CEOUT line drives the Chip Select inputs of the
CMOS RAM. CEOUT follows CEIN as long as LLIN is above the
reset threshold. If LLIN falls below the reset threshold, CEOUT
goes high, independent of the logic level at CEIN. T his prevents
the microprocessor from writing erroneous data into RAM dur-
ing power-up, power-down, brownouts and momentary power
interruptions.
+5V
R1
R3
µP POWER
V
CC
CMOS RAM
POWER
V
PFI
LL
OUT
IN
RESET
µP SYSTEM
R2
R4
ADM8696
RESET
µP RESET
µP NMI
PFO
WDI
V
BATT
+
I/O LINE
BATTERY
GND
Figure 18a. ADM8696 Typical Application Circuit A
REV. A
–10–
ADM8696/ADM8697
OUTLINE DIMENSIONS
0.800 (20.32)
0.790 (20.07)
0.780 (19.81)
5.10
5.00
4.90
16
1
9
8
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
16
9
8
4.50
4.40
4.30
6.40
BSC
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
1
0.060 (1.52)
MAX
0.210 (5.33)
MAX
PIN 1
1.20
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.15
0.05
0.20
0.09
0.75
0.60
0.45
PLANE
SEATING
PLANE
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
COPLANARITY
0.10
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MO-153-AB
COMPLIANT TO JEDEC STANDARDS MS-001-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 19. 16-Lead Plastic Dual In-Line Package [PDIP]
Figure 20. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Narrow Body
(N-16)
Dimensions shown in inches and (millimeters)
Dimensions shown in millimeters
10.50 (0.4134)
10.10 (0.3976)
16
1
9
8
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
45°
1.27 (0.0500)
BSC
2.65 (0.1043)
0.25 (0.
0098)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 21. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
Rev. A | Page 11 of 13
ADM8696/ADM8697
ORDERING GUIDE
Model1,2
Notes
Temperature Range
−40°C to + 85°C
−40°C to + 85°C
−40°C to + 85°C
−40°C to + 85°C
−40°C to + 85°C
−40°C to + 85°C
−40°C to + 85°C
−40°C to + 85°C
−40°C to + 85°C
−40°C to + 85°C
−40°C to + 85°C
−40°C to + 85°C
−40°C to + 85°C
−40°C to + 85°C
−40°C to + 85°C
Package Description
Package Option
N-16
N-16
RW-16
RW-16
RW-16
RW-16
RU-16
RU-16
N-16
ADM8696AN
ADM8696ANZ
16-Lead Plastic Dual In-Line Package [PDIP]
16-Lead Plastic Dual In-Line Package [PDIP]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Plastic Dual In-Line Package [PDIP]
16-Lead Plastic Dual In-Line Package [PDIP]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
ADM8696ARW
ADM8969ARW-REEL
ADM8696ARWZ
ADM8696ARWZ-REEL
ADM8696ARU
ADM8696ARU-REEL
ADM8697AN
ADM8697ANZ
ADM8697ARW
ADM8697ARW-REEL
ADM8697ARWZ
ADM8697ARU
N-16
RW-16
RW-16
RW-16
RU-16
RU-16
3
3
ADM8697ARU-REEL
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
3 Contact sales for availability and quotation.
AUTOMOTIVE PRODUCTS
The ADM8696/ADM8697 models are available with controlled manufacturing to support the quality and reliability requirements of
automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore,
designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available
for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information
and to obtain the specific Automotive Reliability reports for these models.
12 of 13
Rev. A | Page 12 of 13
ADM8696/ADM8697
REVISION HISTORY
6/10—Rev. 0 to Rev. A
Changes to Ordering Guide...........................................................12
©1997-2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09139-0-6/10(A)
13 of 13
Rev. A | Page
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