ADM8830ARUZ [ADI]

Please see the ADM8832.;
ADM8830ARUZ
型号: ADM8830ARUZ
厂家: ADI    ADI
描述:

Please see the ADM8832.

光电二极管
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中文:  中文翻译
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Charge Pump Regulator  
for Color TFT Panel  
ADM8830  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
3 OutputVoltages (+5.1V, +15.3V, 10.2V) from  
One 3V Input Supply  
Power Efficiency Optimized for Use withTFT in  
Mobile Phones  
C5  
2.2F  
V
CC  
C1+  
VOLTAGE  
DOUBLER  
C1  
2.2F  
Low Quiescent Current  
Low Shutdown Current (<1 A)  
FastTransient Response  
C1–  
ADM8830  
VOUT  
LDO IN  
OSCILLATOR  
CLKIN  
C6  
2.2F  
Shutdown Function  
LDO  
VOLTAGE  
Power Saving during Blanking Period  
Option to Use External LDO  
REGULAT
SCAN/BLANK  
LDO_ON/OFF  
+5VOUT  
+5VIN  
CONT
L
+5.1V  
C7  
2.2F  
APPLICATIONS  
C2+  
DOUBLE  
TRIPLE  
C2  
Handheld Instruments  
TFT LCD Panels  
Cellular Phones  
C2–  
C3+  
C3–  
1F  
TIMING  
GERATOR  
C3  
1F  
+15VOUT  
+15.3V  
C8  
1F  
VLTAGE  
IPLER  
C4+  
C4  
VOLTAGE  
INVERTER  
C4–  
1F  
OWN  
NTROL  
DISCHARGE  
SHDN  
–10VOUT  
GENERAL DESCRIPTION  
–10.2V  
C9  
The ADM8830 is a charge pump regulator used for color thin  
film transistor (TFT) liquid crystal displays (LCDs). Usi
charge pump technology, the device can be used to gen
output voltages (+5.1V ± 2%, +15.3V, 10.2V) from
3V input supply.These outputs are then used to provi
supplies for the LCD controller (5.1V) and thte driv
the transistors in the panel (+15.3V and –.2V). Only a few  
external capacitors are needed for the chapumfficient  
low dropout voltage regulator also ensures the powe
efficiency is high and provides a lople 5.1V outpuThis  
LDO can be shut down and an LDO usregulate  
the 5V doubler output and dhe charge pump  
section, which generates the +V outputs if so  
required by the user.  
GND  
1F  
seamlessly maintained when switching from scanning mode to  
blanking mode or vice versa.  
The ADM8830 has a number of power saving features, including  
low power shutdown and reduced quiescent current consumption  
during the blanking periods mentioned above.The 5.1V output  
consumes the most power, so power efficiency is also maximized  
on this output with an oscillator enabling scheme (Green Idle™).  
This effectively senses the load current that is flowing and turns  
on the charge pump only when charge needs to be delivered to  
the 5V pump doubler output.  
The ADM8830 ha100 kscillator for use in  
scanning mode, bbe clocked by an external clock  
source in blankinode.The internal oscillator is  
used to clock the curing scanning mode where the  
current is highest. Durking periods, the ADM8830  
switches to use an external, lower frequency clock.This allows the  
user to vary the frequency and maximize power efficiency during  
blanking periods.The tolerances on the output voltages are  
The ADM8830 is fabricated using CMOS technology for minimal  
power consumption.The part is packaged in 20-lead LFCSP  
andTSSOP packages.  
REV.B  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed byAnalog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
that may result from its use. No license is granted by implication or oth-  
erwise under any patent or patent rights of Analog Devices.Trademarks  
and registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
www.analog.com  
© 2003 Analog Devices, Inc. All rights reserved.  
(VCC = 2.6 V to 3.6 V, TA = –40C to +85C, unless otherwise noted, C1, C5, C6,  
C7 = 2.2 F, C2, C3, C4, C8, C9 = 1 F, CLKIN = 1 kHz in blanking mode.)  
ADM8830–SPECIFICATIONS  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions  
INPUTVOLTAGE,VCC  
SUPPLY CURRENT, ICC  
2.6  
3.6  
V
150  
70  
400  
140  
1
µA  
µA  
µA  
Unloaded, Scanning Period  
Unloaded, Blanking Period  
Shutdown Mode,TA = 25°C  
+5.1V OUTPUT  
OutputVoltage  
Output Current  
5.0  
5.1  
4
5
50  
80  
70  
10  
5
5.2  
5
8
V
IL = 10 µA to 8 mA  
Scanning Period  
Scanning Period,VCC > 2.7V  
Blanking Period  
VCC = 3V, IL = 5 mA (canning)  
VCC = 3V, IL = 200 (Blanking)  
8 mA Load  
mA  
mA  
µA  
%
%
mV p-p  
µs  
200  
Power Efficiency  
Output Ripple  
Transient Response  
IL Stepped from µA t8 mA  
+15.3V OUTPUT  
OutputVoltage  
Output Current  
14.4  
15.3  
50  
1
15.6  
100  
10  
V
µA  
µA  
mV p-p  
IL = 1 µ100 µA  
Scanng Pod  
Blanking Peri
L = 100 µA  
Output Ripple  
50  
–10.2V OUTPUT  
OutputVoltage  
Output Current  
–10.4  
–100  
–10  
–10.2  
–50  
–1  
–9.6  
V
µA  
µA  
mV p-p  
I–1 µA to –100 µA  
anning riod  
BkiPeriod  
IL = 100 µA  
Output Ripple  
50  
POWER EFFICIENCY  
(+15.3V and –10.2V Outputs)  
90  
80  
%
elative to 5.1V Output, IL = 100 µA (Scanning)  
Relative to 5.1V Output, IL =10 µA (Blanking)  
CHARGE PUMP FREQUENCY  
60  
100  
kHz  
Scanning Period  
CONTROL PINS  
SHDN  
InputVoltage,VSHDN  
V
V
SHDN Low = Shutdown Mode  
SHDN High = Normal Mode  
0.7VC
Digital Input Current  
Digital Input Capacitance*  
SCAN/BLANK  
±1  
0  
µA  
pF  
InputVoltage  
0.3VCC  
V
Low = BLANK Period  
0.7VCC  
V
µA  
pF  
High = SCAN Period  
Digital Input Current  
Digital Input Capacita
LDO_ON/OFF  
±1  
10  
InputVoltage  
0.3VCC  
V
V
µA  
pF  
Low = External LDO  
High = Internal LDO  
Digital Input Curr
Digital Input Capacita
CLKIN  
±1  
10  
Minimum Frequency  
0.9  
1
kHz  
Duty Cycle = 50%, Rise/FallTimes = 20 ns  
InputVoltage  
VIL  
0.3VCC  
V
VIH  
0.7VCC  
V
µA  
pF  
Digital Input Current  
Digital Input Capacitance*  
±1  
10  
*Guaranteed by design. Not 100% production tested.  
Specifications are subject to change without notice.  
–2–  
REV. B  
ADM8830  
(VCC = 2.6 V to 3.6 V, TA = –40C to +85C, unless otherwise noted, C1, C5, C6,  
C7 = 2.2 F, C2, C3, C4, C8, C9 = 1 F, CLKIN = 1 kHz in blanking mode.)  
TIMING SPECIFICATIONS  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions  
POWER-UP SEQUENCE  
+5V RiseTime, tR5V  
+15V RiseTime, tR15V  
–10V FallTime, tF10V  
Delay between –10V Fall  
and +15V, tDELAY  
300  
8
12  
µs  
ms  
ms  
10% to 90%, Figure 2  
10% to 90%, Figure 2  
90% to 10%, Figure 2  
3
ms  
Figure 2  
POWER-DOWN SEQUENCE  
+5V FallTime, tF5V  
+15V FallTime, tF15V  
–10V RiseTime, tR10V  
75  
40  
40  
ms  
ms  
ms  
90% to 10%, Fige 2  
90% to 10%, gure 2  
10% to 90Figure
Specifications are subject to change without notice.  
ABSOLUTE MAXIMUM RATINGS*  
THERMAL CARAERISTICS  
(TA = 25°C, unless otherwise noted.)  
20-LeadTSSOP Packag
SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +4.0V  
InputVoltage to Digital Inputs . . . . . . . . . . . . . –0.3V to +4.0V  
Output Short Circuit Duration to GND . . . . . . . . . . . . . 10 sec  
OutputVoltage  
A = 7C/W  
20-LeLFCSPackage:  
A 31°C
J
J
+5.1V Output . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +6V  
–10.2V Output . . . . . . . . . . . . . . . . . . . . . . . .–12V to +0.3V  
+15.3V Output . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +17V  
OperatingTemperature Range . . . . . . . . . . . . –40°C to +85°C  
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(Derate 33 mW/°C above 25°C)  
StorageTemperature Range . . . . . . . . . . . . . –65°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
*This is a stress rating only; functional operation of the dt these o
conditions above those indicated in the operational sions of this specificatiis  
not implied. Exposure to absolute maximum rating cditions ed periods  
of time may affect reliability.  
ORDERING GUIDE  
Model  
ture Range Package Description  
Package Option  
ADM8830ACP  
ADM883L7  
ADM88
ADM88
ADM883
EVAL-ADM
to +85ºC  
C to +85ºC  
–40ºC to +85ºC  
–40ºC to +85ºC  
–40ºC to +85ºC  
Lead Frame Chip Scale Package  
Lead Frame Chip Scale Package  
Thin Shrink Small Outline Package  
Thin Shrink Small Outline Package  
Thin Shrink Small Outline Package  
Evaluation Board  
CP-20-1  
CP-20-1  
RU-20  
RU-20  
RU-20  
CAUTION  
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate  
on the human body and test equipment and can discharge without detection. Although the ADM8830  
features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high  
energy electrostatic discharges.Therefore, proper ESD precautions are recommended to avoid performance  
degradation or loss of functionality.  
REV. B  
–3–  
ADM8830  
PIN CONFIGURATIONS  
TSSOP  
LFCSP  
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
C1–  
C1+  
GND  
–10VOUT  
C4+  
3
V
CC  
VOUT  
LDO_IN  
+5VOUT  
+5VIN  
4
C4–  
PIN 1  
15 C4–  
14 C2+  
13 C2–  
12 C3+  
11 C3–  
V
1
CC  
INDICATOR  
5
C2+  
ADM8830  
TOP VIEW  
(Not to Scale)  
VOUT 2  
LDO_IN 3  
+5VOUT 4  
+5VIN 5  
ADM8830  
TOPVIEW  
6
C2–  
7
C3+  
8
C3–  
LDO_ON/OFF  
SHDN  
9
+15VOUT  
CLKIN  
10  
SCAN/BLANK  
PIN FUNCTION DESCRIPTIONS  
Pin Number  
TSSOP LFCSP Mnemonic  
Function  
1, 2  
3
19, 20  
C1–, C1+  
VCC  
External capacitor C1 is connected betweeese piA 2.2 µF capacitor is recommended.  
Positive SupplyVoltage Input. Connect this pin tsupply with a 2.2 µF decoupling capacitor.  
1
2
4
VOUT  
Voltage Doubler Output.This derived by doubling the 3V supply. A 2.2 µF capacitor to  
ground is required on this pin.  
5
6
7
8
3
4
5
6
LDO_IN  
Voltage Regulator ser hoption to bypass this circuit using the  
LDO_ON/OFF
+5VOUT  
+5VIN  
+5.1V Output Pd by doubling and regulating the 3V supply. A 2.2 µF ca-  
pacitor to ground this pin to stabilize the regulator.  
+5.1Input Pin.This is he input to the voltage tripler and doubler inverter charge pump  
circs.  
LDO_ON/OFF  
Control Logic Inp3V CMOS logic. A logic high selects the internal LDO for regulation of  
e 5V voltage dbler output. A logic low isolates the internal LDO from the rest of the charge  
mp circuits.This allows the use of an external LDO to regulate the 5V voltage doubler  
he output of this LDO is then fed back into the voltage tripler and doubler/inverter  
f the ADM8830.  
9
7
8
SH
l Input. 3V CMOS logic. Active low shutdown control.This shuts down the timing  
erator and enables the discharge circuit to dissipate the charge on the voltage outputs,  
thus driving them to 0V.  
10  
Drive Mode Input. 3V CMOS logic. A logic high places the part in scan (high current) mode  
and the charge pump is driven by the internal oscillator. A logic low places the part in blanking  
(low current) mode and the charge pump is driven by the (slower) external oscillator.This is  
a power saving feature on the ADM8830.  
11  
12  
9
CLKIN  
External CLOCK Input. During a blanking period, the oscillator circuit selects this pin to drive  
the charge pump circuit.This is at a lower frequency than the internal oscillator, resulting in  
lower quiescent current consumption, thus saving power.  
10  
+15VOUT  
+15.3V Output Pin.This is derived by tripling the +5.1V regulated output. A 1 µF capacitor  
is required on this pin.  
13, 14  
15, 16  
17, 18  
19  
11, 12  
13, 14  
15, 16  
17  
C3–, C3+  
C2–, C2+  
C4–, C4+  
–10VOUT  
External capacitor C3 is connected between these pins. A 1 µF capacitor is recommended.  
External capacitor C2 is connected between these pins. A 1 µF capacitor is recommended.  
External capacitor C4 is connected between these pins. A 1 µF capacitor is recommended.  
–10.2V Output Pin.This is derived by doubling and inverting the +5.1V regulated output.  
A 1 µF capacitor is required on this pin.  
20  
18  
GND  
Device Ground Pin.  
–4–  
REV. B  
Typical Performance Characteristics–ADM8830  
80  
70  
60  
50  
40  
30  
20  
10  
5.104  
5.0752  
5.0750  
5.0748  
5.0746  
5.0744  
5.0742  
5.0740  
5.0738  
5.0736  
5.0734  
5.102  
5.100  
5.098  
5.096  
5.094  
5.092  
5.090  
0
2
3
I
4
5
6
7
8
10 30 50 70 90 110 130 150 170 190  
100  
1000  
10000  
– mA  
OUTPUT CURRENT – A  
BLANKING FREQUENCY – Hz  
LOAD  
TPC 1. LDO Efficiency in Blanking  
Mode with VCC = 3 V  
TPC 2. LDO OutputVoltage (Unloaded)  
vs. Blanking Mode Frequency  
TP. LDO/P Voltage vs. Load  
CurreScanniMode, VCC = 3.3V  
85  
84  
83  
82  
100  
90  
100  
9
80  
70  
60  
50  
40  
80  
81  
80  
79  
78  
70  
60  
0
1
2
3
4
5
6
7
8
8
10  
0
20  
40  
60  
80  
100  
OUTPUT CURRENT – mA  
RRENT – A  
OUTPUT CURRENT – A  
TPC 4. LDO Efficiency in Scanning  
Mode with VCC = 3 V  
TPC 5. +15VV Efficiency vs. Output  
Cun Blanking Mode, VCC = 3 V  
TPC 6. +15V/–10V Efficiency vs. Output  
Current in Scanning Mode,VCC = 3V  
5.30  
5.25  
250  
200  
V
OUT  
5.20  
E 1 @ +
5.15  
I
(SCAN)  
CC  
DEVICE 1 @ +
5V OUTPUT RIPPLE  
5.10  
150  
100  
50  
5.05  
V
RIPPLE  
CC  
@ –40C  
I
(BLANK)  
CC  
5.00  
4.95  
4.90  
0
2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6  
2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6  
V
–V  
CC  
V
–V  
CC  
TPC 9. Output Ripple on LDO  
(5 V Output)  
TPC 7. LDO Variation over Supply  
andTemperature  
TPC 8. Supply Current vs. Voltage  
REV. B  
–5–  
ADM8830  
+15V OUTPUT  
LOAD DISABLE  
5V OUTPUT  
LOAD ENABLE  
5V OUTPUT  
–10V OUTPUT  
5VOUT  
TPC 11. 5V OutputTransient Response,  
Load Disconnected  
TPC 12. +1and –10 V Outputs at  
Power-U
TPC 10. 5 V OutputTransient  
Response for Maximum Load  
Current  
20.1  
20.0  
19.9  
19.8  
19.7  
19.6  
+15V OUTPUT  
–10V OUTPUT  
5VOUT  
19.5  
19.4  
40  
C  
80  
–40  
–20  
TPC 13. +15 V and –10 V Outputs at  
Power-Down (Unloaded)  
TPC 14. Pon overTem-  
perature, VCC nning Mode  
th All O/Ps at mum Load  
–6–  
REV. B  
ADM8830  
SCANNING AND BLANKING  
V
ATFT LCD panel is essentially made up of a bank of capacitors,  
each representing a pixel in the display.These capacitors store  
different levels of charge, depending on the amount of lumines-  
cence required for a given pixel.When a picture is being displayed  
on the panel, a scan of all the pixel capacitors is performed, placing  
different levels of charge on each in order to create the image.The  
process of updating the display like this is called “scanning.” Once  
scanned, an image will be held by pixel capacitance and the con-  
troller and source line drivers can be put into a low power mode.  
This low power mode is referred to as the blanking mode on the  
ADM8830. Over a finite period of time, this pixel charge will leak  
and the capacitors will have to be refreshed in order to maintain  
the image.  
CC  
SHDN  
tR5V  
90%  
10%  
tF5V  
+5V  
tR15V  
tF15V  
+15V  
–10V  
tDELAY  
–3V  
90%  
10%  
tR10V  
tF10V  
LOAD  
The ADM8830 caters to the two modes of operation described  
above as follows.When theTFT LCD panel is in scanning mode,  
a logic high on the SCAN/BLANK input places the device in high  
current power mode, providing extra power (extra current) to the  
LCD controller and the source line drivers. If the panel continues  
to be updated (as when a moving picture is being displayed), then  
the ADM8830 can be continually operated in scanning mode. If  
the same image is kept on the panel, a logic low is applied to the  
SCAN/BLANK input and the ADM8830 enters blanking (low  
current) mode. Depending on how often the image is being updated,  
the ADM8830 can be operated with a variable SCAN/BLANK  
duty cycle.This helps to maximize power efficiency and therefore  
extends the battery life.  
SCAN/BLANK  
EXTERNAL CLOCK  
Figu. Power Sequence  
TRANSNT RESPONSE  
The M883eatures extremely fast transient response, making  
it very safor fast mage updates onTFT LCD panels.This  
means thaen unr changing load conditions there is still very  
effective reguof the 5V output.TPCs 10 and 11 show how  
the 5.1V output responds when a maximum load is dynamically  
onnected d disconnected. Note that the output settles within  
5 to lthan 1% of the output level.  
EXTERNAL CLOCK  
The ADM8830 has an internal 100 kHz oscillator, but an external  
clock source can also be used to clock the part.This clock source  
must be applied to the CLKIN pin. Power is saved during blank-  
ing periods by disabling the internal oscillator and switching to  
the lower frequency external clock source.To achieve optimum  
performance of the charge pump circuitry, it is important that the  
duty cycle of the external clock source be 50% and that the rise  
and fall times be less than 20 ns.  
tR  
tF  
tRE  
tF: FALLTIME  
tH  
tH  
tT  
@ 100CYCLE  
tT  
Figure 1. Duty CyClock  
0.28  
0.4  
3.10  
0.75  
POWER SEQUEN
0.9  
The gate drive suequenced such that the –10V  
supply is up befoply for theTFT panel to power  
up correctly.The Arols this sequence.When the  
device is turned on (a on SHDN), the ADM8830 allows  
the –10V output to ramp immediately but holds off the +15V  
output. It continues to do this until the negative output has reached  
3V. At this point, the positive output is enabled and allowed to  
ramp up to +15V.This sequence is highlighted in Figure 2.  
0.25  
0.5  
1.95  
2.10  
SOLDER MASK  
BOARD METALLIZATION  
0.25  
0.2  
DIMENSIONS IN  
MILLIMETERS  
Figure 3. Suggested LFCSP 4 mm 4 mm 20-Lead  
Land Pattern  
REV. B  
–7–  
ADM8830  
OUTLINE DIMENSIONS  
20-LeadThin Shrink Small Outline Package [TSSOP]  
(RU-20)  
Dimensions shown in millimeters  
6.60  
6.50  
6.40  
20  
11  
10  
4.50  
4.40  
4.30  
6.40 BSC  
1
PIN 1  
0.65  
BSC  
1.20  
MAX  
0.15  
0.05  
0.20  
0.09  
.75  
60  
8  
0  
0.30  
0.19  
SEATING  
PLANE  
COPLANARITY  
0.10  
COMPLIANT TO JEDEC STANDARDS MO-153
20-Lead Lead Frame Chip Scale Packa[LCSP]  
4 mm 4 mm Body  
(CP-20-1)  
Dimensions shown illimeters  
0.60  
MAX  
4.0  
BSC SQ  
0.60  
MAX  
16  
15  
20  
1
5
PIN 1  
2.25  
2.10 S  
1.95  
INDICATOR  
TOP  
BOTTOM  
VIEW  
VIEW  
11  
10  
0.75  
0.55  
0.35  
6
0.25 MI  
0 MAX  
0.65 TYP  
0.30  
0.23  
0.18  
12MAX  
1.00  
0.05 MAX  
0.02 NOM  
0.20  
REF  
COPLANARITY  
0.08  
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1  
Revision History  
Location  
Page  
10/03—Data Sheet chV. A to REV. B.  
Changes to GENERAL ION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
3/03—Data Sheet changed from REV. SpA to REV. A.  
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Edits toTPC 12 andTPC 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
11/02—Data Sheet changed from REV. 0 to REV. SpA.  
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Changes toTHERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Edits to captions ofTPCs 2, 3, and 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Edits to caption ofTPC 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
AddedTPC 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
–8–  
REV. B  

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