ADMP441_1209 [ADI]
Omnidirectional Microphone with Bottom Port and I2S Digital Output; 全向麦克风与底部端口和I2S数字输出
| 型号： | ADMP441_1209 |
| 厂家： | 
ADI |
| 描述： | Omnidirectional Microphone with Bottom Port and I2S Digital Output |
| 文件： | 总16页 (文件大小：397K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Omnidirectional Microphone with
Bottom Port and I2S Digital Output
Data Sheet
ADMP441
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Digital I²S interface with high precision 24-bit data
High SNR of 61 dBA
High sensitivity of −26 dBFS
Flat frequency response from 60 Hz to 15 kHz
Low current consumption of 1.4 mA
High PSR of −75 dBFS
ADMP441
FILTER
ADC
SCK
SD
2
I S
SERIAL
PORT
POWER
MANAGEMENT
HARDWARE
CONTROL
WS
Small 4.72 mm × 3.76 mm × 1 mm surface-mount package
Compatible with Sn/Pb and Pb-free solder processes
RoHS/WEEE compliant
Figure 1.
APPLICATIONS
Teleconferencing systems
Gaming consoles
Mobile devices
Laptops
Tablets
Security systems
BOTTOM
TOP
Figure 2. Isometric Views of ADMP441 Microphone Package
GENERAL DESCRIPTION
The ADMP4411 is a high performance, low power, digital output,
omnidirectional MEMS microphone with a bottom port. The
complete ADMP441 solution consists of a MEMS sensor, signal
conditioning, an analog-to-digital converter, antialiasing filters,
power management, and an industry standard 24-bit I²S inter-
face. The I²S interface allows the ADMP441 to connect directly
to digital processors, such as DSPs and microcontrollers, with-
out the need for an audio codec in the system.
The ADMP441 has a high SNR and high sensitivity, making it
an excellent choice for far field applications. The ADMP441 has
a flat wideband frequency response, resulting in natural sound
with high intelligibility.
The ADMP441 is available in a thin 4.72 mm × 3.76 mm ×
1 mm surface-mount package. It is reflow solder compatible
with no sensitivity degradation. The ADMP441 is halide free.
1 Protected by U.S. Patents 7,449,356; 7,825,484; 7,885,423; and 7,961,897. Other patents are pending.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2012 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADMP441
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Understanding Sensitivity............................................................8
Power Management.......................................................................8
Startup.............................................................................................8
I²S Data Interface ..........................................................................8
Digital Filter Characteristics..................................................... 10
Applications Information .............................................................. 11
Power Supply Decoupling ......................................................... 11
Handling Instructions................................................................ 11
Supporting Documentation...................................................... 11
Layout and Design Recommendations........................................ 12
Outline Dimensions....................................................................... 13
Ordering Guide .......................................................................... 13
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
I²S Digital Input/Output.............................................................. 4
Timing Diagram ........................................................................... 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ........................................................................ 8
REVISION HISTORY
10/12—Rev. A to Rev. B
1/12—Rev. 0 to Rev. A
Changes to General Description Section ...................................... 1
Changes to Pick-and-Place Equipment Section, Evaluation
Board User Guide Section, Circuit Note Section, and
Application Note Section............................................................... 11
Changes to Circuit Note Title....................................................... 11
Updated Outline Dimensions....................................................... 13
Deleted Figure 18............................................................................ 13
10/11—Revision 0: Initial Version
Rev. B | Page 2 of 16
Data Sheet
ADMP441
SPECIFICATIONS
TA = 25°C, VDD = 2.4 V, SCK = 3.072 MHz, SPL = 104 dB (3.16 Pa rms), unless otherwise noted. All minimum and maximum
specifications are guaranteed. Typical specifications are not guaranteed.
Table 1.
Parameter
Symbol Test Conditions/Comments
Min Typ
Omni
Max
Unit
PERFORMANCE
Directionality
Sensitivity at 94 dB SPL1
Signal-to-Noise Ratio
Equivalent Input Noise
Dynamic Range
1 kHz, 104 dB SPL
−29 −26
−23
dBFS
dBA
dBA SPL
dB
Hz
kHz
SNR
EIN
20 kHz bandwidth, A-weighted
20 kHz bandwidth, A-weighted
Derived from EIN and maximum acoustic input
Low frequency –3 dB point
61
33
87
60
15
Frequency Response2
High frequency –3 dB point
Deviation limits from flat response within pass band
104 dB SPL
217 Hz, 100 mV p-p square wave superimposed on VDD
Peak
−3/+2
dB
%
dBFS
dB SPL
dBFS
Total Harmonic Distortion
Power Supply Rejection
Maximum Acoustic Input
Noise Floor
THD
PSR
3
−75
120
−87
20 Hz to 20 kHz, A-weighted, rms
POWER SUPPLY
Supply Voltage
Supply Current
VDD = 1.8 V
VDD
IDD
1.8
3.3
V
Normal Mode
Standby
Power-Down
VDD = 3.3 V
Normal Mode
Standby
1.4
2.2
1.6
0.8
2
mA
mA
µA
2.5
0.8
4.5
mA
mA
µA
Power-Down
DIGITAL FILTER
Group Delay
17.25/fS
359
1078
sec
µs
µs
fS = 48 kHz
fS = 16 kHz
Pass-Band Ripple
Stop-Band Attenuation
Pass Band
0.04 dB
60
20.3
dB
kHz
0.423 × fS
1 The peak-to-peak amplitude is relative to peak-to-peak amplitude of 224 − 1. The stimulus is a 104 dB SPL sinusoid having rms amplitude of 3.1623 Pa. Sensitivity is
relative to 1 Pa.
2 See Figure 6 and Figure 8.
Rev. B | Page 3 of 16
ADMP441
Data Sheet
I²S DIGITAL INPUT/OUTPUT
–40°C < TA < +85°C, 1.8 V < VDD < 3.3 V, unless otherwise noted.
Table 2.
Limit1
Max
Parameter
Symbol
Test Conditions/Comments
Min
Unit
DIGITAL INPUT
0.25 × VDD
VDD
Voltage Input Low (L/R, WS, SCK)
Voltage Input High (L/R, WS, SCK)
SD DIGITAL OUTPUT
Voltage Output Low
Voltage Output Low
Voltage Output High
Voltage Output High
Voltage Output Low
Voltage Output Low
Voltage Output High
Voltage Output High
VIL
VIH
0
V
V
0.7 × VDD
VOL
VOL
VOH
VOH
VOL
VOL
VOH
VOH
VDD = 1.8 V, ISINK = 0.25 mA
VDD = 1.8 V, ISINK = 0.7 mA
VDD = 1.8 V, ISINK = 0.7 mA
VDD = 1.8 V, ISINK = 0.25 mA
VDD = 3.3 V, ISINK = 0.5 mA
VDD = 3.3 V, ISINK = 1.7 mA
VDD = 3.3 V, ISINK = 1.7 mA
VDD = 3.3 V, ISINK = 0.5 mA
0.1 × VDD
0.3 × VDD
V
V
V
V
V
V
V
V
0.7 × VDD
0.9 × VDD
0.1 × VDD
0.3 × VDD
0.7 × VDD
0.9 × VDD
1 Limits based on characterization results; not production tested.
Table 3. Serial Data Port Timing Specifications
Parameter
Description
Min
50
Max
Unit
ns
tSCH
SCK high
tSCL
SCK low
50
ns
tSCP
fSCK
tWSS
SCK period
SCK frequency
WS setup
312
0.5
0
ns
MHz
ns
3.2
tWSH
WS hold
20
ns
fWS
WS frequency
7.8
49.3
kHz
TIMING DIAGRAM
tSCP
tSCH
SCK
WS
SD
tWSS
tSCL
tWSH
Figure 3. Serial Data Port Timing
Rev. B | Page 4 of 16
Data Sheet
ADMP441
ABSOLUTE MAXIMUM RATINGS
Table 4.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Supply Voltage (VDD)
Sound Pressure Level
Mechanical Shock
Vibration
−0.3 V to +3.6 V
160 dB
10,000 g
Per MIL-STD-883 Method
2007, Test Condition B
−40°C to +85°C
Operating Temperature Range
Digital Pin Input Voltage
−0.3 V to VDD + 0.3 V or 3.6 V,
whichever is less
ESD CAUTION
CRITICAL ZONE
tP
T
TO T
L
P
T
P
RAMP-UP
T
L
tL
T
SMAX
T
SMIN
tS
RAMP-DOWN
PREHEAT
t25°C TO PEAK
TIME
Figure 4. Recommended Soldering Profile Limits
Table 5. Recommended Soldering Profile Limits
Profile Feature
Sn63/Pb37
Pb-Free
Average Ramp Rate (TL to TP)
Preheat
1.25°C/sec max
1.25°C/sec max
Minimum Temperature (TSMIN
)
100°C
100°C
Maximum Temperature (TSMAX
)
150°C
200°C
Time (TSMIN to TSMAX), tS
Ramp-Up Rate (TSMAX to TL)
Time Maintained Above Liquidous (tL)
Liquidous Temperature (TL)
60 sec to 75 sec
1.25°C/sec
45 sec to 75 sec
183°C
60 sec to 75 sec
1.25°C/sec
~50 sec
217°C
Peak Temperature (TP)
Time Within 5°C of Actual Peak Temperature (tP)
Ramp-Down Rate
215°C +3°C/−3°C
20 sec to 30 sec
3°C/sec max
260°C +0°C/−5°C
20 sec to 30 sec
3°C/sec max
5 minute max
Time 25°C (t25°C) to Peak Temperature
5 minute max
Rev. B | Page 5 of 16
ADMP441
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADMP441
L/R
WS
4
3
2
1
6 GND
7 V
DD
SD
8 CHIPEN
9 GND
SCK
BOTTOM VIEW
(Not to Scale)
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Type
Description
Serial Data Clock for I²S Interface.
Serial Data Output for I²S Interface. This pin tristates when not actively driving the appropriate
output channel. The SD trace should have a 100 kΩ pull-down resistor to discharge the line during
the time that all microphones on the bus have tristated their outputs.
1
2
SCK
SD
Input
Output
3
4
WS
L/R
Input
Input
Serial Data-Word Select for I²S Interface.
Left/Right Channel Select. When set low, the microphone outputs its signal in the left channel of
the I²S frame; when set high, the microphone outputs its signal in the right channel.
5
6
7
8
GND
GND
VDD
Ground
Ground
Power
Input
Ground. Connect to ground on the PCB.
Ground. Connect to ground on the PCB.
Power, 1.8 to 3.3 V. This pin should be decoupled to Pin 6 with a 0.1 μF capacitor.
Microphone Enable. When set low (ground), the microphone is disabled and put in power-down
mode. When set high (VDD), the microphone is enabled.
CHIPEN
9
GND
Ground
Ground. Connect to ground on the PCB.
Rev. B | Page 6 of 16
Data Sheet
ADMP441
TYPICAL PERFORMANCE CHARACTERISTICS
10
10
8
6
4
0
2
0
–2
–4
–6
–8
–10
–10
–20
10
100
1k
10k
50
100
1k
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 8. Typical Frequency Response (Measured)
Figure 6. Frequency Response Mask
0
–10
–20
–30
–40
–50
–60
–70
–80
100
1k
10k
FREQUENCY (Hz)
Figure 7. Typical Power Supply Rejection vs. Frequency
Rev. B | Page 7 of 16
ADMP441
Data Sheet
THEORY OF OPERATION
The ADMP441 is a high performance, low power, digital
output, omnidirectional MEMS microphone with a bottom
port. The complete ADMP441 solution consists of a MEMS
sensor, signal conditioning, an analog-to-digital converter, anti-
aliasing filters, power management, and an industry standard
24-bit I²S interface.
Power-Down Mode
The microphone enters power-down mode when CHIPEN is
low, regardless of the SCK operation. Normal mode operation
resumes 217 SCK clock cycles (43 ms with SCK at 3.072 MHz)
after CHIPEN returns high while SCK is active.
It always takes 217 clock cycles to restart the ADMP441 after VDD
is applied.
The ADMP441 complies with the TIA-920 Telecommunications
Telephone Terminal Equipment Transmission Requirements for
Wideband Digital Wireline Telephones standard.
It is not recommended to supply active clocks (WS and SCK) to
the ADMP441 while there is no power supplied to VDD. Doing
this continuously turns on ESD protection diodes, which may
affect long-term reliability of the microphone.
UNDERSTANDING SENSITIVITY
The casual user of digital microphones may have difficulty
understanding the sensitivity specification. Unlike an analog
microphone (whose specification is easily confirmed with an
oscilloscope), the digital microphone output has no obvious
unit of measure.
STARTUP
The microphones have zero output for the first 218 SCK clock
cycles (85 ms with SCK at 3.072 MHz) following power-up.
I²S DATA INTERFACE
The ADMP441 has a nominal sensitivity of −26 dBFS at 1 kHz
with an applied sound pressure level of 94 dB. The units are in
decibels referred to full scale. The ADMP441 default full-scale
peak output word is 223 – 1 (integer representation), and
−26 dBFS of that scale is (223 − 1) × 10(−26/20) = 420,426. A pure
acoustic tone at 1 kHz having a 1 Pa rms amplitude results in an
output digital signal whose peak amplitude is 420,426.
The slave serial data port’s format is I²S, 24-bit, twos comple-
ment. There must be 64 SCK cycles in each WS stereo frame, or
32 SCK cycles per data-word. The L/R control pin determines
whether the ADMP441 outputs data in the left or right channel.
For a stereo application, the SD pins of the left and right
ADMP441 microphones should be tied together as shown in
Figure 9. The format of a stereo I²S data stream is shown in
Figure 10. Figure 11 and Figure 12 show the formats of a mono
microphone data stream for left and right microphones,
respectively.
Although the industry uses a standard specification of 94 dB
SPL, the ADMP441 test method applies a 104 dB SPL signal.
The higher sound pressure level reduces noise and improves
repeatability. The ADMP441 has excellent gain linearity, and
the sensitivity test result at 94 dB is derived with very high
confidence from the test data.
Data Output Mode
The output data pin (SD) is tristated when it is not actively
driving I²S output data. SD immediately tristates after the LSB
is output so that another microphone can drive the common
data line.
POWER MANAGEMENT
The ADMP441 has three different power states: normal
operation, standby mode, and power-down mode.
The SD trace should have a pull-down resistor to discharge the
line during the time that all microphones on the bus have
tristated their outputs. A 100 kΩ resistor is sufficient for this, as
shown in Figure 9.
Normal Operation
The microphone becomes operational 218 clock cycles (85 ms
with SCK at 3.072 MHz) after initial power-up. The CHIPEN
pin then controls the power modes. The part is in normal opera-
tion mode when SCK is active and the CHIPEN pin is high.
Data-Word Length
The output data-word length is 24 bits per channel. The
ADMP441 must always have 64 clock cycles for every stereo
data-word (fSCK = 64 × fWS).
Standby Mode
The microphone enters standby mode when the serial data
clock SCK stops and CHIPEN is high. Normal operation
resumes 214 clock cycles (5 ms with SCK at 3.072 MHz) after
SCK restarts.
Data-Word Format
The default data format is I²S (twos complement), MSB-first. In
this format, the MSB of each word is delayed by one SCK cycle
from the start of each half-frame.
The ADMP441 should not be transitioned from standby to
power-down mode, or vice versa. Standby mode is only
intended to be entered from the normal operation state.
Rev. B | Page 8 of 16
Data Sheet
ADMP441
FROM VOLTAGE
REGULATOR
(1.8V TO 3.3V)
SYSTEM MASTER
(DSP, MICROCONTROLLER,
CODEC)
0.1µF
0.1µF
V
V
DD
DD
V
V
DD
DD
CHIPEN
L/R
SCK
WS
SD
SCK
CHIPEN
L/R
WS
SD
LEFT
RIGHT
ADMP441
ADMP441
100kΩ
GND GND GND
GND GND GND
Figure 9. System Block Diagram
1
2
3
3
3
4
24
25
26
32
33
34
35
36
56
57
58
58
58
64
WS
SCK (64 × fS
)
SD (24-BIT)
MSB
LSB
MSB
LSB
HIGH-Z
LEFT CHANNEL
HIGH-Z
RIGHT CHANNEL
HIGH-Z
Figure 10. Stereo Output I²S Format
1
2
4
24
25
26
32
33
34
35
36
56
57
64
WS
SCK (64 × fS
)
SD (24-BIT)
MSB
LSB
HIGH-Z
HIGH-Z
LEFT CHANNEL
Figure 11. Mono Output I²S Format Left Channel (L/R = 0)
1
2
4
24
25
26
32
33
34
35
36
56
57
64
WS
SCK (64 × fS
)
SD (24-BIT)
MSB
LSB
HIGH-Z
RIGHT CHANNEL
HIGH-Z
Figure 12. Mono Output I²S Format Right Channel (L/R = 1)
Rev. B | Page 9 of 16
ADMP441
Data Sheet
wide dynamic range. However, it does require a good quality
low-pass filter to eliminate the high frequency noise.
DIGITAL FILTER CHARACTERISTICS
The ADMP441 has an internal digital band-pass filter. A
high-pass filter eliminates unwanted low frequency signals.
A low-pass filter allows the user to scale the pass band with
the sampling frequency as well as perform required noise
reduction.
Figure 13 shows the response of this digital low-pass filter
included in the microphone. The pass band of the filter extends
to 0.423 × fS and, in that band, has an unnoticeable 0.04 dB of
ripple. The high frequency cutoff of −6 dB occurs at 0.5 × fS. A
48 kHz sampling rate results in a pass band of 20.3 kHz and a
half amplitude corner at 24 kHz; the stop-band attenuation of
the filter is greater than 60 dB. Note that these filter specifica-
tions scale with sampling frequency.
High-Pass Filter
The ADMP441 incorporates a high-pass filter to remove unwanted
dc and very low frequency components. Table 7 shows the high-
pass characteristics for a nominal sampling rate of 48 kHz. The
cutoff frequency scales with changes in sampling rate.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
Table 7. High-Pass Filter Characteristics
Frequency
Attenuation
3.7 Hz
–3.0 dB
10.4 Hz
21.6 Hz
–0.5 dB
–0.1 dB
This digital filter response is in addition to the natural high-
pass response of the ADMP441 MEMS acoustic transducer that
has a −3 dB cutoff of 60 Hz.
Low-Pass Filter
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
The analog-to-digital converter in the ADMP441 is a single-bit,
high order, sigma-delta (Σ-Δ) running at a high oversampling
ratio. The noise shaping of the converter pushes the majority of
the noise well above the audio band and gives the microphone a
NORMALIZED FREQUENCY (fS
)
Figure 13. Digital Low-Pass Filter Magnitude Response
Rev. B | Page 10 of 16
Data Sheet
ADMP441
APPLICATIONS INFORMATION
Reflow Solder
POWER SUPPLY DECOUPLING
For best results, the soldering profile should be in accordance
with the recommendations of the manufacturer of the solder
paste used to attach the MEMS microphone to the PCB. It is
recommended that the solder reflow profile does not exceed the
limit conditions specified in Figure 4 and Table 5.
For best performance and to avoid potential parasitic artifacts,
placing a 0.1 µF ceramic type X7R or better capacitor between
Pin 7 (VDD) and ground is strongly recommended. The
capacitor should be placed as close to Pin 7 as possible.
The connections to each side of the capacitor should be as short
as possible, and the trace should stay on a single layer with no
vias. For maximum effectiveness, locate the capacitor equidistant
from the power and ground pins or, when equidistant placement
is not possible, slightly closer to the power pin. Thermal connec-
tions to the ground planes should be made on the far side of the
capacitor, as shown in Figure 14.
Board Wash
When washing the PCB, ensure that water does not make
contact with the microphone port. Blow-off procedures and
ultrasonic cleaning must not be used.
SUPPORTING DOCUMENTATION
Evaluation Board User Guide
V
GND
DD
UG-303, EVAL-ADMP441Z-FLEX: Bottom-Port I2S Output
MEMS Microphone Evaluation Board
UG-362, EVAL-ADMP441Z SDP Daughter Board for the
ADMP441 I2S MEMS Microphone
CAPACITOR
Circuit Note
CN-0208, High Performance Digital MEMS Microphone's Simple
TO V
DD
Interface to SigmaDSP Audio Processor with I2S Output
CN-0266, High Performance Digital MEMS Microphone
TO GND
Standard Digital Audio Interface to Blackfin DSP
Figure 14. Recommended Power Supply Bypass Capacitor Layout
Application Notes
HANDLING INSTRUCTIONS
Pick-and-Place Equipment
AN-1003 Application Note, Recommendations for Mounting and
Connecting Analog Devices, Inc., Bottom-Ported MEMS
Microphones
The MEMS microphone can be handled using standard pick-
and-place and chip shooting equipment. Care should be taken
to avoid damage to the MEMS microphone structure as follows:
AN-1068 Application Note, Reflow Soldering of the MEMS
Microphone
•
Use a standard pickup tool to handle the microphone.
Because the microphone hole is on the bottom of the
package, the pickup tool can make contact with any part
of the lid surface.
Do not pick up the microphone with a vacuum tool that
makes contact with the bottom side of the microphone.
Do not pull air out of or blow air into the microphone port.
Do not use excessive force to place the microphone on
the PCB.
AN-1112 Application Note, Microphone Specifications and
Terms Explained
AN-1124 Application Note, Recommendations for Sealing
Analog Devices, Inc., Bottom-Port MEMS Microphones from
Dust and Liquid Ingress
•
•
AN-1140 Application Note, Microphone Array Beamfoaming
For additional information, visit www.analog.com/mic.
Rev. B | Page 11 of 16
ADMP441
Data Sheet
LAYOUT AND DESIGN RECOMMENDATIONS
1.05
(6×)
0.25 DIA.
(THRU HOLE)
2.66 (4×)
0.96 1.33 (2×)
1.56
3.16
0.40 × 0.60
(8×)
DIMENSIONS SHOWN IN MILLIMETERS
Figure 15. Recommended Printed Circuit Board Land Pattern
(Dimensions shown in millimeters)
1.05
(6×)
0.20
1.05
2.66 (4×)
3.76
1.33 (2×)
1.6
1.07
0.350 × 0.550
(8×)
4.72
DIMENSIONS SHOWN IN MILLIMETERS
Figure 16. Recommended Printed Circuit Board Solder Paste Mask Pattern
(Dimensions shown in millimeters)
Rev. B | Page 12 of 16
Data Sheet
ADMP441
OUTLINE DIMENSIONS
4.82
4.72
4.62
0.30
REFERENCE
CORNER
1.07
1.56 DIA.
0.96 DIA.
0.275
4.10 REF
PIN 1
1.05 BSC
0.40 × 0.60
(PINS 1-8)
1
4
6
3.86
3.76
3.66
0.250 DIA.
0.225
2.66 BSC
5
3.14
REF
1.33 BSC
9
TOP VIEW
BOTTOM VIEW
1.05
0.98
0.88
0.73 REF
0.24 REF
SIDE VIEW
Figure 17. 9-Terminal Chip Array Small Outline No Lead Cavity [LGA_CAV]
4.72 mm × 3.76 mm × 1 mm Body
(CE-9-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option2
CE-9-1
Ordering Quantity
ADMP441ACEZ-RL
ADMP441ACEZ-RL7
EVAL-ADMP441Z
EVAL-ADMP441Z-FLEX
9-Terminal LGA_CAV, 13”Tape and Reel
9-Terminal LGA_CAV, 7”Tape and Reel
Evaluation Board
4,500
1,000
CE-9-1
Flex Evaluation Board
1 Z = RoHS Compliant Part.
2 This package option is halide-free.
Rev. B | Page 13 of 16
ADMP441
NOTES
Data Sheet
Rev. B | Page 14 of 16
Data Sheet
NOTES
ADMP441
Rev. B | Page 15 of 16
ADMP441
NOTES
Data Sheet
©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09568-0-10/12(B)
Rev. B | Page 16 of 16
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