ADMV1014 [ADI]
24 GHz to 44 GHz, Wideband, Microwave Downconverter;
| 型号： | ADMV1014 |
| 厂家： | 
ADI |
| 描述： | 24 GHz to 44 GHz, Wideband, Microwave Downconverter |
| 文件： | 总42页 (文件大小：2207K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
24 GHz to 44 GHz,
Wideband, Microwave Downconverter
ADMV1014
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Wideband RF input frequency range: 24 GHz to 44 GHz
2 downconversion modes
Direct conversion from RF to baseband I/Q
Image rejecting downconversion to complex IF
LO input frequency range: 5.4 GHz to 10.25 GHz
LO quadrupler for up to 41 GHz
Matched 50 Ω, single-ended RF input, and complex IF outputs
Option between matched 100 Ω balanced or 50 Ω single-
ended LO inputs
ADMV1014
SEN
I_P
VCC_QUAD
BG_RBIAS
RST
×4
I_N
100 Ω balanced baseband I/Q output impedance with
adjustable output common-mode voltage level
Image rejection optimization
Square law power detector for setting mixer input power
Variable attenuator for receiver power control
Programmable via a 4-wire SPI interface
32-terminal, 5 mm × 5 mm LGA package
IF_I
VCC_BG
VCC_LNA_1P5
GND
90°
0°
GND
IF_Q
Q_N
RF_IN
GND
Q_P
DET
APPLICATIONS
Point to point microwave radios
Radar, electronic warfare systems
Instrumentation, automatic test equipment (ATE)
Figure 1.
GENERAL DESCRIPTION
The ADMV1014 is a silicon germanium (SiGe), wideband,
microwave downconverter optimized for point to point microwave
radio designs operating in the 24 GHz to 44 GHz frequency range.
provide two single-ended complex IF outputs anywhere between
800 MHz and 6000 MHz. When used as an image rejecting
downconverter, the unwanted image term is typically
suppressed to better than 30 dBc below the wanted sideband.
The ADMV1014 offers a flexible local oscillator (LO) system,
including a frequency quadruple option allowing up to a 41 GHz
range of LO input frequencies to cover a radio frequency (RF)
input range as wide as 24 GHz to 44 GHz. A square law power
detector is provided to allow monitoring of the power levels at
the mixer inputs. The detector output provides closed-loop
control of the RF input variable attenuator through an external
op amp error integrator circuit option.
The downconverter offers two modes of frequency translation.
The device is capable of direct quadrature demodulation to
baseband inphase (I)/quadrature (Q) output signals, as well as
image rejection downconversion to a complex intermediate
frequency (IF) output carrier frequency. The baseband outputs
can be dc-coupled, or, more typically, the I/Q outputs are
ac-coupled with a sufficiently low high-pass corner frequency
to ensure adequate demodulation accuracy. The serial port
interface (SPI) allows fine adjustment of the quadrature phase
to allow the user to optimize I/Q demodulation performance.
Alternatively, the baseband I/Q outputs can be disabled, and the
I/Q signals can be passed through an on-chip active balun to
The ADMV1014 downconverter comes in a compact, thermally
enhanced, 5 mm × 5 mm LGA package. The ADMV1014 operates
over the −40°C to +85°C case temperature range.
Rev. A
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ADMV1014
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Image Rejection Downconversion........................................... 29
Detector ....................................................................................... 29
LO Input Path ............................................................................. 29
Power-Down ............................................................................... 29
Serial Port Interface (SPI) ......................................................... 30
Applications Information.............................................................. 31
Error Vector Magnitude (EVM) Performance ....................... 31
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Serial Port Register Timing......................................................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 9
I/Q Mode ....................................................................................... 9
IF Mode........................................................................................ 17
Output Detector Performance.................................................. 24
Return Loss and Isolations........................................................ 25
M × N Spurious Performance................................................... 27
Theory of Operation ...................................................................... 28
Start-Up Sequence...................................................................... 28
Baseband Quadrature Demodulation (I/Q Mode)................ 28
Baseband Quadrature Demodulation to Very Low
Frequencies ................................................................................. 32
Performance at Different Quad Filter Settings....................... 32
VVA Temperature Compensation............................................ 33
Performance Between Differential vs. Single-Ended LO Input
....................................................................................................... 33
Performance across RF Frequency at Fixed IF and Baseband
Frequencies ................................................................................. 34
Recommended Land Pattern.................................................... 35
Evaluation Board Information ................................................. 35
Register Summary .......................................................................... 36
Register Details ............................................................................... 37
Outline Dimensions....................................................................... 42
Ordering Guide .......................................................................... 42
REVISION HISTORY
4/2019—Rev. 0 to Rev. A
Changes to Return Loss and Isolations Section, Figure 95, and
Figure 97 .......................................................................................... 25
Changes to Figure 99 and Figure 101 .......................................... 26
Changes to Start-Up Sequence Section and Baseband
Quadrature Demodulation (I/Q Mode) Section ....................... 28
Changes to Image Rejection Downconversion Section
and LO Input Path Section............................................................ 29
Change to Serial Port Interface (SPI) Section............................. 30
Changes to Figure 111 ................................................................... 32
Changes to Table 18 and Table 19 ................................................ 41
Changes to Figure 1.......................................................................... 1
Changes to Table 3 and Thermal Resistance Section................... 6
Changes to Figure 3 and Table 5..................................................... 7
Changes to Figure 14...................................................................... 10
Changes to Figure 19 Caption....................................................... 11
Changes to Figure 27...................................................................... 12
Changes to Figure 51 Caption and Figure 52 Caption .............. 17
Changes to Figure 63 Caption and Figure 64 Caption .............. 19
Changes to Figure 69 Caption and Figure 70 Caption .............. 20
Changes to Figure 75...................................................................... 21
Changes to Figure 79...................................................................... 22
10/2018—Revision 0: Initial Version
Rev. A | Page 2 of 42
Data Sheet
ADMV1014
SPECIFICATIONS
RF amplitude = −30 dBm, measurements performed with a 0 mV dc bias. VCC_MIXER = VCC_QUAD = VCC_BG = VCC_LNA =
VCC_VGA = VCC_IF_BB = 3.3 V, DVDD = VCC_VVA = 1.8 V, Register 0x0B set to 0x727C, Register 0x03, Bits[12:13] set to 11, and
ambient temperature (TA) = 25°C, unless otherwise noted.
Measurements are in IF mode, performed with a 90° hybrid, Register 0x03, Bit 11 = 0, and Register 0x03, Bit 8 = 1, unless otherwise noted.
Measurements in I/Q mode are measured as a composite of the I and Q channel performance, common-mode voltage (VCM) = 1.15 V,
Register 0x03, Bit 11 = 1, and Register 0x03, Bit 8 = 0, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
FREQUENCY RANGES
RF Input
24
44
GHz
LO Input
LO Quadrupler
IF Output
Baseband (BB) I/Q Output
LO AMPLITUDE RANGE
I/Q DEMODULATOR PERFORMANCE
Conversion Gain
5.4
21.6
0.8
DC
−6
10.25 GHz
41
GHz
GHz
GHz
dBm
6.0
6.0
+6
0
At maximum gain
24 GHz to 42 GHz
42 GHz to 44 GHz
Voltage Variable Attenuator (VVA) Control Range
Single Sideband (SSB) Noise Figure
24 GHz to 42 GHz
42 GHz to 44 GHz
Input Third-Order Intercept (IP3)
24 GHz to 42 GHz
12.5
12.5
17
17
19
dB
dB
dB
At maximum gain
At maximum gain
5.5
6
8
8.5
dB
dB
0
−1
45
dBm
dBm
dBm
42 GHz to 44 GHz
Input Second-Order Intercept (IP2)
Input 1 dB Compression Point (P1dB)
24 GHz to 42 GHz
42 GHz to 44 GHz
Amplitude Balance
24 GHz to 44 GHz, at maximum gain
At maximum gain
−14
−15
−10
−11
0.5
1
2
4
dBm
dBm
dB
Degrees
Degrees
Degrees
Phase Balance
DC < baseband frequency (fBB) < 2 GHz
2 GHz < fBB < 4 GHz
4 GHz < fBB < 6 GHz
Image Rejection
Uncalibrated
Calibrated
24 GHz to 44 GHz, at maximum gain
45
52
dBc
dBc
IF DOWNCONVERTER PERFORMANCE
Conversion Gain
24 GHz to 42 GHz
42 GHz to 44 GHz
VVA Control Range
SSB Noise Figure
24 GHz to 42 GHz
42 GHz to 44 GHz
Input IP3
At maximum gain
12.5
11.5
17
16
19
dB
dB
dB
At maximum gain
At maximum gain
5.5
6
8
8.5
dB
dB
24 GHz to 42 GHz
42 GHz to 44 GHz
0
0.5
dBm
dBm
Rev. A | Page 3 of 42
ADMV1014
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
Input P1dB
At maximum gain
24 GHz to 42 GHz
−14
−15
−9
dBm
dBm
dB
Degrees
Degrees
Degrees
42 GHz to 44 GHz
Amplitude Balance
Phase Balance
−10
−0.5
0.5
1
800 MHz < IF frequency (fIF) < 2 GHz
2 GHz < fIF < 4 GHz
4 GHz < fIF < 6 GHz
2.5
Image Rejection
Uncalibrated
Calibrated
30
35
dBc
dBc
RECEIVER (Rx) POWER DETECTOR PERFORMANCE
Input Level
1 dB dynamic range
Minimum
Maximum
1 dB Dynamic Range
Output Voltage
Maximum DC Output
RETURN LOSS
−35
−14
20
dBm
dBm
dB
3.3
V
RF Input
LO Input
IF Output
BB Output
BB I/Q Output Impedance
LEAKAGE
50 Ω single-ended
100 Ω differential
50 Ω single-ended
100 Ω differential
−13
−10
−12
−15
100
dB
dB
dB
dB
Ω
At maximum gain
Fundamental LO to RF
4 × LO to RF
Fundamental LO to IF
Fundamental LO to I/Q
LOGIC INPUTS
−70
−70
−60
−60
dBm
dBm
dBm
dBm
Input Voltage Range
High, VINH
Low, VINL
DVDD − 0.4
0
1.8
0.4
V
V
Input Current, IINH/IINL
Input Capacitance, CIN
LOGIC OUTPUTS
Output Voltage Range
High, VOH
Low, VOL
Output High Current, IOH
POWER INTERFACE
100
3
μA
pF
DVDD − 0.4
0
1.8
0.4
500
V
V
μA
VCC_IF_BB, VCC_VGA, VCC_LNA_3P3, VCC_MIXER,
VCC_BG, VCC_QUAD
3.15
3.3
3.45
V
3.3 V Supply Current
DVDD, VCC_VVA
1.8 V Supply Current
VCC_LNA_1P5
1.5 V Supply Current
Total Power Consumption
Power-Down
437
1.8
4.2
1.5
33
mA
V
mA
V
mA
W
mW
1.7
1.9
1.43
1.57
1.5
96
125
Rev. A | Page 4 of 42
Data Sheet
ADMV1014
SERIAL PORT REGISTER TIMING
Table 2.
Parameter
tSDI, SETUP
tSDI, HOLD
tSCLK, HIGH
tSCLK, LOW
tSCLK,
Min
Typ
Max
Unit
ns
ns
%
%
䡟escription
Data to clock setup time
Data to clock hold time
Clock high duration
Clock low duration
Clock to SEN setup time
10
10
40 to 60
40 to 60
30
ns
_SETUP
SEN
tSCLK, DOT
tSCLK, DOV
tSCLK,
Clock to data out transition time
Clock to data out valid time
Clock to SEN inactive
10
10
ns
ns
ns
20
80
_INACTIVE
SEN
tSEN
Inactive SEN (between two operations)
ns
_INACTIVE
Timing Diagram
tSCLK, HIGH
tSCLK, LOW
SCLK
tSCLK, SEN_SETUP
tSEN_INACTIVE
SEN
tSCLK, DOT
tSCLK, SEN_INACTIVE
tSCLK, DOV
SDO
tSDI, HOLD
tSDI, SETUP
SDI
Figure 2. Serial Port Register Timing Diagram
Rev. A | Page 5 of 42
ADMV1014
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
TJ = (P × ѰJT) + TTOP
where:
TOP is package top temperature (°C). TTOP is measured at the
top center of the package.
ѰJT is the junction to top thermal characterization number.
P is the total power dissipation in the chip (W).
(1)
Parameter
Rating
T
Supply Voltage
VCC_IF_BB, VCC_VGA, VCC_LNA_3P3,
VCC_MIXER, VCC_BG, VCC_QUAD, DVDD
4.3 V
VCC_VVA, VCC_LNA_1P5
RF Input Power
LO Input Power
Maximum Junction Temperature
Maximum Power Dissipation1
Lifetime at Maximum Junction Temperature (TJ) 1 ×106 hours
2.3 V
0 dBm
9 dBm
125°C
2.17 W
TJ = (P × ѰJB) + TBOARD
(2)
where:
T
BOARD is the board temperature measured on the midpoint of
the longest side of the package no more than 1 mm from the
edge of the package body (°C).
Operating Case Temperature Range
Storage Temperature Range
Lead Temperature (Soldering 60 sec)
Moisture Sensitivity Level (MSL) Rating2
Electrostatic Discharge (ESD) Sensitivity
Human Body Model (HBM)
−40°C to +85°C
−55°C to +125°C
260°C
ѰJB is the junction to board thermal characterization number.
P is the total power dissipation in the chip (W).
As stated in JEDEC51-12, only use Equation 1 and Equation 2
when no heat sink or heat spreader is present. When a heat sink
or heat spreader is added, use θJC_TOP to estimate or calculate the
junction temperature.
MSL3
3000 V
750 V
Field Induced Charged Device Model
(FICDM)
Table 4. Thermal Resistance
1 The maximum power dissipation is a theoretical number calculated by
Package
(TJ − 85°C)/θJC_TOP
.
2
3
4
5
6
Type1
θJA
33.6
θJC_TOP
18.4
θJB
13.3
ΨJT
ΨJB
12.6
Unit
2 Based on IPC/JEDEC J-STD-20 MSL classifications.
CC-32-6
4.9
°C/W
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
1 The thermal resistance values specified in Table 4 are simulated based on
JEDEC specifications, unless specified otherwise, and must be used in
compliance with JESD51-12.
2 θJA is the junction to ambient thermal resistance in a natural convection,
JEDEC environment.
3 θJC_TOP is the junction to case (top) JEDEC thermal resistance.
4 θJB is the junction to board JEDEC thermal resistance.
5 ΨJT is the junction to top JEDEC thermal characterization parameter.
6 ΨJB is the junction to board JEDEC thermal characterization parameter
THERMAL RESISTANCE
ESD CAUTION
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC is
the junction to case thermal resistance.
Only use θJA and θJC to compare the thermal performance of
different packages when all test conditions listed are similar to
JEDEC specifications. Otherwise, use ѰJT and ѰJB to calculate
the device junction temperature using the following equations:
Rev. A | Page 6 of 42
Data Sheet
ADMV1014
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADMV1014
TOP VIEW
(Not to Scale)
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24
23
22
21
SEN
I_P
VCC_QUAD
BG_RBIAS
RST
I_N
IF_I
VCC_BG
GND
IF_Q
Q_N
Q_P
20 VCC_LNA_1P5
19 GND
18 RF_IN
GND
17
9
10 11 12 13 14 15 16
NOTES
1. EXPOSED PAD. SOLDER THE EXPOSED PAD
TO A LOW IMPEDANCE GROUND PLANE.
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
SPI Serial Enable. SEN is a high impedance pin with a logic of 1.8 V.
1
SEN
2, 3
Negative (I_N) and Positive (I_P) Differential BB I Outputs. These pins are dc-coupled.
I_P, I_N
4, 6
IF_I, IF_Q
IF I and IF Q Single-Ended Complex Quadrature Outputs. These pins are dc-coupled to GND, and
each pin is matched to 50 Ω.
5, 13, 17, 19, 25, 28
7, 8
GND
Ground.
Positive (Q_P) and Negative (Q_N) Differential Baseband Q Outputs. These pins are dc-coupled.
Q_N, Q_P
9
SDO
SPI Serial Data Output.
10
VCC_IF_BB
3.3 V Power Supply for BB and IF Section. Place a 100 pF, 0.01 μF, and a 10 μF capacitor close to this
pin.
11
12
14
VDET
VCC_VGA
VCTRL
Square Law Detector Output Voltage.
3.3 V Power Supply for RF Amplifier. Place a 100 pF, 0.01 μF, and a 10 μF capacitor close to this pin.
RF VVA Control Voltage. The voltage on this pin ranges from 1.8 V (minimum gain) to 0 V (maximum
gain). Refer to the ADMV1014-EVALZ user guide for the external component requirements.
15
VCC_VVA
1.8 V Power Supply for VVA Control Circuit. Place a 100 pF, 0.01 μF, and a 10 μF capacitor close to
this pin.
16
18
VCC_LNA_3P3 3.3 V Power Supply for LNA. Place a 100 pF, 0.01 μF, and a 10 μF capacitor close to this pin.
RF_IN
RF Input. This pin is dc-coupled internally with a choke to GND, and matched to 50 Ω, single-
ended. A dc input above 0 V requires external ac coupling.
20
21
VCC_LNA_1P5 1.5 V Power Supply for Low Noise Amplifier (LNA). Place a 100 pF, 0.01 μF, and a 10 μF capacitor
close to this pin.
VCC_BG
3.3 V Power Supply for Band Gap Circuit. Place a 100 pF, 0.01 μF, and a 10 μF capacitor close to this
pin.
22
23
RST
BG_RBIAS
SPI Reset. Connect this pin to logic high for normal operation.
Bang Gap Circuit External High Precision Resistor. Place a 1.1 kΩ, high precision resistor shunt to
ground close to this pin.
24
VCC_QUAD
3.3 V Power Supply for Quadruple. Place a 100 pF, 0.01 μF, and a 10 μF capacitor close to this pin.
Rev. A | Page 7 of 42
ADMV1014
Data Sheet
Pin No.
Mnemonic
Description
26, 27
LO_N, LO_P
Negative (LO_N) and Positive (LO_P) Differential Local Oscillator Input. These pins are dc-coupled
internally with a choke to GND and matched to 100 Ω differential or 50 Ω single-ended. A dc input
above 0 V requires external ac coupling. When using the LO input as single-ended, terminate the
unused LO port with a 50 Ω impedance to ground.
29
30
31
32
VCC_MIXER
DVDD
SCLK
3.3 V Power Supply for the Mixer. Place a 100 pF, 0.01 μF, and a 10 μF capacitor close to this pin.
1.8 V SPI Digital Supply. Place a 100 pF, 0.01 μF, and a 10 μF capacitor close to this pin.
SPI Clock Digital Input. SCLK is a high impedance pin.
SDI
SPI Serial Data Input. SDI is a high impedance pin.
EPAD
Exposed Pad. Solder the exposed pad to a low impedance ground plane.
Rev. A | Page 8 of 42
Data Sheet
ADMV1014
TYPICAL PERFORMANCE CHARACTERISTICS
I/Q MODE
RF amplitude = −30 dBm, measurements performed with a 0 mV dc bias. VCC_MIXER = VCC_QUAD = VCC_BG = VCC_LNA =
VCC_VGA = VCC_IF_BB = 3.3 V, DVDD = VCC_VVA = 1.8 V, and TA = 25°C, unless otherwise noted. Register 0x0B is set to 0x727C,
Register 0x03, Bits[13:12] are set to 11, VCM = 1.15 V, Register 0x03, Bit 11 = 1, Register 0x03, Bit 8 = 0, and measurements are a composite
of the I and Q channels. VATT is the attenuation voltage at the VCTRL pin. VATT = 0 V, unless otherwise specified.
25
25
20
15
+85°C AT 39GHz
+25°C AT 39GHz
–40°C AT 39GHz
+85°C AT 28GHz
+25°C AT 28GHz
–40°C AT 28GHz
20
15
10
5
10
5
0
–5
+85°C AT 1.8V
+25°C AT 1.8V
–40°C AT 1.8V
+85°C AT 0.8V
+25°C AT 0.8V
–40°C AT 0.8V
+85°C AT 0V
+25°C AT 0V
–40°C AT 0V
–10
–15
–20
–25
–30
0
–5
23
25
27
29
31
33
35
37
39
41
43
45
0
0.2
0.4
0.6
0.8
1.0
(V)
1.2
1.4
1.6
1.8
RF FREQUENCY (GHz)
V
ATT
Figure 4. Conversion Gain vs. RF Frequency at Three Different Gain Settings
for Various Temperatures, fBB = 100 MHz (Upper Sideband)
Figure 7. Conversion Gain vs. VATT for Various RF Frequencies (fRF),
fBB = 100 MHz at fRF = 28 GHz and 39 GHz
25
20
15
10
25
20
15
10
5
3.5V UPPER SIDEBAND
3.3V UPPER SIDEBAND
3.1V UPPER SIDEBAND
39GHz UPPER SIDEBAND
28GHz UPPER SIDEBAND
0
–5
5
0
–10
23
25
27
29
31
33
35
37
39
41
43
45
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
BASEBAND FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 5. Conversion Gain vs. RF Frequency for Various Supply Voltages,
fBB = 100 MHz
Figure 8. Conversion Gain vs. Baseband Frequency at fRF = 28 GHz and
39 GHz (Upper Sideband)
25
20
15
10
5
25
20
15
10
39GHz LOWER SIDEBAND
28GHz LOWER SIDEBAND
0
–5
+6dBm UPPER SIDEBAND
0dBm UPPER SIDEBAND
–6dBm UPPER SIDEBAND
5
0
–10
23
25
27
29
31
33
35
37
39
41
43
45
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
BASEBAND FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 6. Conversion Gain vs. RF Frequency for Various LO Inputs, fBB = 100 MHz
Rev. A | Page 9 of 42
Figure 9. Conversion Gain vs. Baseband Frequency at fRF = 28 GHz and
39 GHz (Lower Sideband)
ADMV1014
Data Sheet
10
8
10.0
7.5
5.0
2.5
0
+85°C UPPER SIDEBAND
+25°C UPPER SIDEBAND
–40°C UPPER SIDEBAND
39GHz UPPER SIDEBAND
28GHz UPPER SIDEBAND
6
4
2
0
–2
–4
–6
–8
–10
–2.5
–5.0
23
25
27
29
31
33
35
37
39
41
43
45
0
0.2
0.4
0.6
0.8
1.0
(V)
1.2
1.4
1.6
1.8
RF FREQUENCY (GHz)
V
ATT
Figure 13. Input IP3 vs. VATT for Various RF Frequencies (fRF),
RF Amplitude = −30 dBm per Tone at 20 MHz Spacing, fBB = 100 MHz (Upper
Sideband) at fRF = 28 GHz and 39 GHz
Figure 10. Input IP3 vs. RF Frequency at Maximum Gain for Various
Temperatures, RF Amplitude = −30 dBm per Tone at 20 MHz Spacing,
fBB = 100 MHz (Upper Sideband)
10.0
10
8
6
3.5V UPPER SIDEBAND
3.3V UPPER SIDEBAND
3.1V UPPER SIDEBAND
7.5
5.0
39GHz UPPER SIDEBAND
28GHz UPPER SIDEBAND
39GHz LOWER SIDEBAND
28GHz LOWER SIDEBAND
4
2.5
2
0
0
–2
–4
–6
–8
–10
–2.5
–5.0
–7.5
–10.0
23
25
27
29
31
33
35
37
39
41
43
45
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
BASEBAND FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 11. Input IP3 vs. RF Frequency at Maximum Gain for Various Supply
Voltages, RF Amplitude = −30 dBm per Tone at 20 MHz Spacing,
fBB = 100 MHz (Upper Sideband)
Figure 14. Input IP3 vs. Baseband Frequency at Maximum Gain, RF
Amplitude = −30 dBm per Tone at 20 MHz Spacing at fRF = 28 GHz and
39 GHz, Upper Sideband and Lower Sideband
10
5
8
6
4
+6dBm UPPER SIDEBAND
0dBm UPPER SIDEBAND
–6dBm UPPER SIDEBAND
39GHz UPPER SIDEBAND
28GHz UPPER SIDEBAND
3
4
2
1
2
0
0
–2
–4
–6
–8
–10
–1
–2
–3
–4
–5
23
25
27
29
31
33
35
37
39
41
43
45
–30 –29 –28 –27 –26 –25 –24 –23 –22 –21 –20
RF FREQUENCY (GHz)
INPUT POWER (dBm)
Figure 12. Input IP3 vs. RF Frequency at Maximum Gain for Various LO
Inputs, RF Amplitude = −30 dBm per Tone at 20 MHz Spacing, fBB = 100 MHz
(Upper Sideband)
Figure 15. Input IP3 vs. Input Power for Various RF Frequencies (fRF) at 20 MHz
Spacing, fBB = 100 MHz, fRF = 28 GHz and 39 GHz
Rev. A | Page 10 of 42
Data Sheet
ADMV1014
12
25
20
15
10
5
+85°C AT 39GHz
+25°C AT 39GHz
–40°C AT 39GHz
+85°C AT 28GHz
+25°C AT 28GHz
–40°C AT 28GHz
+85°C UPPER SIDEBAND
+25°C UPPER SIDEBAND
–40°C UPPER SIDEBAND
10
8
6
4
2
0
23
0
25
27
29
31
33
35
37
39
41
43
45
0
0.2
0.4
0.6
0.8
1.0
(V)
1.2
1.4
1.6
1.8
RF FREQUENCY (GHz)
V
ATT
Figure 16. Noise Figure vs. RF Frequency at Maximum Gain for Various
Temperatures, fBB = 100 MHz
Figure 19. Noise Figure vs. VATT for Various RF Frequencies and Temperatures,
fBB = 100 MHz at fRF = 28 GHz and 39 GHz
12
9
8
7
6
5
4
3.5V UPPER SIDEBAND
3.3V UPPER SIDEBAND
10
3.1V UPPER SIDEBAND
8
6
4
2
0
3
39GHz UPPER SIDEBAND
28GHz UPPER SIDEBAND
2
1
0
23
25
27
29
31
33
35
37
39
41
43
45
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
BASEBAND FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 17. Noise Figure vs. RF Frequency for Various Supply Voltages,
BB = 100 MHz
Figure 20. Noise Figure vs. Baseband Frequency at fRF = 28 GHz and 39 GHz
(Upper Sideband)
f
12
10
8
9
8
7
6
5
4
+6dBm UPPER SIDEBAND
0dBm UPPER SIDEBAND
–6dBm UPPER SIDEBAND
6
4
3
39GHz LOWER SIDEBAND
28GHz LOWER SIDEBAND
2
2
1
0
0
23
25
27
29
31
33
35
37
39
41
43
45
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
BASEBAND FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 18. Noise Figure vs. RF Frequency for Various LO Inputs, fBB = 100 MHz
Figure 21. Noise Figure vs. Baseband Frequency at fRF = 28 GHz and 39 GHz
(Lower Sideband)
Rev. A | Page 11 of 42
ADMV1014
Data Sheet
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
+85°C UPPER SIDEBAND
+25°C UPPER SIDEBAND
–40°C UPPER SIDEBAND
+6dBm UPPER SIDEBAND
0dBm UPPER SIDEBAND
–6dBm UPPER SIDEBAND
23
25
27
29
31
33
35
37
39
41
43
45
23
25
27
29
31
33
35
37
39
41
43
45
RF INPUT FREQUENCY (GHz)
RF INPUT FREQUENCY (GHz)
Figure 22. Image Rejection vs. RF Input Frequency at Maximum Gain for
Various Temperatures, fBB = 100 MHz, Uncalibrated
Figure 25. Image Rejection vs. RF Input Frequency for Various LO Inputs,
fBB = 100 MHz
80
80
+85°C UPPER SIDEBAND
70
70
60
50
40
30
20
10
0
39GHz UPPER SIDEBAND
28GHz UPPER SIDEBAND
+25°C UPPER SIDEBAND
–40°C UPPER SIDEBAND
60
50
40
30
20
10
0
23
25
27
29
31
33
35
37
39
41
43
45
0
0.2
0.4
0.6
0.8
1.0
(V)
1.2
1.4
1.6
1.8
RF INPUT FREQUENCY (GHz)
V
ATT
Figure 23. Image Rejection vs. RF Input Frequency at Maximum Gain for
Various Temperatures, fBB = 100 MHz, Calibrated
Figure 26. Image Rejection vs. VATT for Various RF Frequencies (fRF),
fBB = 100 MHz at fRF = 28 GHz and 39 GHz
80
70
60
50
40
80
70
60
50
40
30
20
10
0
39GHz UPPER SIDEBAND
28GHz UPPER SIDEBAND
39GHz LOWER SIDEBAND
28GHz LOWER SIDEBAND
30
3.5V UPPER SIDEBAND
20
10
0
3.3V UPPER SIDEBAND
3.1V UPPER SIDEBAND
23
25
27
29
31
33
35
37
39
41
43
45
0
1
2
3
4
5
6
7
RF INPUT FREQUENCY (GHz)
BASEBAND FREQUENCY (GHz)
Figure 24. Image Rejection vs. RF Input Frequency for Various Supply
Voltages, fBB = 100 MHz
Figure 27. Image Rejection vs. Baseband Frequency at fRF = 28 GHz and
39 GHz (Upper Sideband and Lower Sideband)
Rev. A | Page 12 of 42
Data Sheet
ADMV1014
60
50
40
30
60
50
40
30
20
10
0
+85°C UPPER SIDEBAND
20
10
0
+25°C UPPER SIDEBAND
–40°C UPPER SIDEBAND
39GHz UPPER SIDEBAND
28GHz UPPER SIDEBAND
23
25
27
29
31
33
35
37
39
41
43
45
0
0.2
0.4
0.6
0.8
1.0
(V)
1.2
1.4
1.6
1.8
RF FREQUENCY (GHz)
V
ATT
Figure 28. Input IP2 vs. RF Frequency at Maximum Gain for Various
Temperatures, RF Amplitude = −30 dBm per Tone at 20 MHz Spacing,
fBB = 100 MHz (Upper Sideband)
Figure 31. Input IP2 vs. VATT for Various RF Frequencies (fRF), RF Amplitude = −30
dBm per Tone at 20 MHz Spacing, fBB = 100 MHz (Upper Sideband) at
fRF = 28 GHz and 39 GHz
60
50
40
30
55
50
45
40
35
30
25
20
3.5V UPPER SIDEBAND
3.3V UPPER SIDEBAND
3.1V UPPER SIDEBAND
20
10
0
39GHz UPPER SIDEBAND
28GHz UPPER SIDEBAND
15
10
5
0
23
25
27
29
31
33
35
37
39
41
43
45
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
BASEBAND FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 32. Input IP2 vs. Baseband Frequency at Maximum Gain, RF
Amplitude = −30 dBm per Tone at 20 MHz Spacing at fRF = 28 GHz and
39 GHz, Upper Sideband
Figure 29. Input IP2 vs. RF Frequency (fRF) at Maximum Gain for Various
Supply Voltages, RF Amplitude = −30 dBm per Tone at 20 MHz Spacing,
fBB = 100 MHz (Upper Sideband)
55
50
45
40
35
30
25
60
50
40
30
20
20
39GHz LOWER SIDEBAND
28GHz LOWER SIDEBAND
15
10
5
+6dBm UPPER SIDEBAND
0dBm UPPER SIDEBAND
–6dBm UPPER SIDEBAND
10
0
0
23
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
BASEBAND FREQUENCY (GHz)
25
27
29
31
33
35
37
39
41
43
45
RF FREQUENCY (GHz)
Figure 33. Input IP2 vs. Baseband Frequency for Various RF Frequencies (fRF
at 20 MHz Spacing, fBB = 100 MHz, fRF = 28 GHz and 39 GHz
)
Figure 30. Input IP2 vs. RF Frequency at Maximum Gain for Various LO
Inputs, RF Amplitude = −30 dBm per Tone at 20 MHz Spacing, fBB = 100 MHz
(Upper Sideband)
Rev. A | Page 13 of 42
ADMV1014
Data Sheet
0
–2
0
–2
+85°C UPPER SIDEBAND
+25°C UPPER SIDEBAND
–40°C UPPER SIDEBAND
–4
–4
–6
–8
–6
–10
–12
–14
–16
–18
–20
–8
+85°C AT 39GHz
+25°C AT 39GHz
–40°C AT 39GHz
+85°C AT 28GHz
+25°C AT 28GHz
–40°C AT 28GHz
–10
–12
–14
23
25
27
29
31
33
35
37
39
41
43
45
0
0.2
0.4
0.6
0.8
1.0
(V)
1.2
1.4
1.6
1.8
RF FREQUENCY (GHz)
V
ATT
Figure 34. Input P1dB vs. RF Frequency at Maximum Gain for Various
Temperatures, fBB = 100 MHz
Figure 37. Input P1dB vs. VATT for Various RF Frequencies (fRF),
fBB = 100 MHz at fRF = 28 GHz and 39 GHz
0
0
–2
–2
–4
3.5V UPPER SIDEBAND
3.3V UPPER SIDEBAND
3.1V UPPER SIDEBAND
–4
–6
–6
–8
–8
–10
–12
–14
–16
–18
–20
–10
–12
39GHz UPPER SIDEBAND
–14
28GHz UPPER SIDEBAND
–16
–18
–20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
BASEBAND FREQUENCY (GHz)
23
25
27
29
31
33
35
37
39
41
43
45
RF FREQUENCY (GHz)
Figure 35. Input P1dB vs. RF Frequency for Various Supply Voltages,
fBB = 100 MHz
Figure 38. Input P1dB vs. Baseband Output Frequency at
f
RF = 28 GHz and 39 GHz (Upper Sideband)
0
0
–2
–2
–4
+6dBm UPPER SIDEBAND
0dBm UPPER SIDEBAND
–6dBm UPPER SIDEBAND
–4
–6
–6
–8
–8
–10
–12
–14
–16
–18
–20
–10
–12
–14
–16
–18
–20
39GHz LOWER SIDEBAND
28GHz LOWER SIDEBAND
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
BASEBAND FREQUENCY (GHz)
23
25
27
29
31
33
35
37
39
41
43
45
RF FREQUENCY (GHz)
Figure 36. Input P1dB vs. RF Frequency for Various LO Inputs, fBB = 100 MHz
Figure 39. Input P1dB vs. Baseband Output Frequency at
fRF = 28 GHz and 39 GHz (Lower Sideband)
Rev. A | Page 14 of 42
Data Sheet
ADMV1014
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.2
–0.4
–0.6
–0.8
–1.0
BB I_N +85°C
BB I_N +25°C
BB I_N –40°C
BB Q_N +85°C
BB Q_N +25°C
BB Q_N –40°C
BB Q_P +85°C
BB Q_P +25°C
BB Q_P –40°C
BB I_N +85°C
BB I_N +25°C
BB I_N –40°C
BB Q_N +85°C
BB Q_N +25°C
BB Q_N –40°C
BB Q_P +85°C
BB Q_P +25°C
BB Q_P –40°C
–0.8
–1.0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
BASEBAND OUTPUT FREQUENCY (GHz)
BASEBAND OUTPUT FREQUENCY (GHz)
Figure 40. Magnitude Error vs. Baseband Output Frequency, Referenced to
I_P Output, fRF = 28 GHz, for Various Temperatures, at Maximum Gain
Figure 42. Magnitude Error vs. Baseband Output Frequency, Referenced to
I_P Output, fRF = 39 GHz, for Various Temperatures, at Maximum Gain
8
6
8
6
4
4
2
2
0
0
–2
–4
–2
–4
BB I_N +85°C
BB I_N +25°C
BB I_N –40°C
BB Q_N +85°C
BB Q_N +25°C
BB Q_N –40°C
BB Q_P +85°C
BB Q_P +25°C
BB Q_P –40°C
BB I_N +85°C
BB I_N +25°C
BB I_N –40°C
BB Q_N +85°C
BB Q_N +25°C
BB Q_N –40°C
BB Q_P +85°C
BB Q_P +25°C
BB Q_P –40°C
–6
–8
–6
–8
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
BASEBAND OUTPUT FREQUENCY (GHz)
BASEBAND OUTPUT FREQUENCY (GHz)
Figure 41. Phase Error vs. Baseband Output Frequency, Referenced to I_P
Output, fRF = 28 GHz, for Various Temperatures, at Maximum Gain
Figure 43. Phase Error vs. Baseband Output Frequency, Referenced to I_P
Output, fRF = 39 GHz, for Various Temperatures, at Maximum Gain
Rev. A | Page 15 of 42
ADMV1014
Data Sheet
25
20
15
10
5
12
10
8
6
4
0
1
2
3
0
1
2
3
2
0
23
0
23
25
27
29
31
33
35
37
39
41
43
45
25
27
29
31
33
35
37
39
41
43
45
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 44. Conversion Gain vs. RF Frequency at Four Different
BB_AMP_GAIN_CTRL (Register 0x0A, Bits[2:1]) Settings, fBB = 100 MHz
(Upper Sideband)
Figure 46. Noise Figure vs. RF Frequency Four Different BB_AMP_GAIN_CTRL
(Register 0x0A, Bits[2:1]) Settings, fBB = 100 MHz (Upper Sideband)
5
4
3
2
1
0
–1
0
–2
1
2
3
–3
–4
–5
23
25
27
29
31
33
35
37
39
41
43
45
RF FREQUENCY (GHz)
Figure 45. Input IP3 vs. RF Frequency at Four Different BB_AMP_GAIN_CTRL
(Register A, Bits[2:1]) Settings, fBB = 100 MHz (Upper Sideband)
Rev. A | Page 16 of 42
Data Sheet
ADMV1014
IF MODE
RF amplitude = −30 dBm, measurements performed with a 0 mV dc bias. VCC_MIXER = VCC_QUAD = VCC_BG = VCC_LNA =
VCC_VGA = VCC_IF_BB = 3.3 V, DVDD = VCC_VVA = 1.8 V, TA = 25°C unless otherwise specified. Register 0x0B set to 0x727C,
Register 0x03, Bits[12:13] set to 11, measurements performed with a 90° hybrid, Register 0x03, Bit 11 = 0, and Register 0x03, Bit 8 = 1.
25
25
20
15
10
5
39GHz UPPER SIDEBAND
28GHz UPPER SIDEBAND
39GHz LOWER SIDEBAND
28GHz LOWER SIDEBAND
20
15
10
5
0
–5
–10
–15
–20
–25
–30
+85°C UPPER SIDEBAND
+25°C UPPER SIDEBAND
–40°C UPPER SIDEBAND
+85°C LOWER SIDEBAND
+25°C LOWER SIDEBAND
–40°C LOWER SIDEBAND
0
23
25
27
29
31
33
35
37
39
41
43
45
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
RF FREQUENCY (GHz)
IF FREQUENCY
Figure 47. Conversion Gain vs. RF Frequency at Maximum Gain for Various
Temperatures, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
Figure 50. Conversion Gain vs. IF Frequency (fIF) at Maximum Gain,
fRF = 28 GHz and 39 GHz (Upper Sideband and Lower Sideband)
25
20
15
10
5
25
+85°C AT 28GHz
+25°C AT 28GHz
20
–40°C AT 28GHz
+85°C AT 39GHz
+25°C AT 39GHz
15
–40°C AT 39GHz
10
0
5
0
–5
–10
3.5V UPPER SIDEBAND
–15
–5
3.3V UPPER SIDEBAND
3.1V UPPER SIDEBAND
–20
3.5V LOWER SIDEBAND
–10
–15
3.3V LOWER SIDEBAND
3.1V LOWER SIDEBAND
–25
–30
23
25
27
29
31
33
35
37
39
41
43
45
0
0.2
0.4
0.6
0.8
1.0
(V)
1.2
1.4
1.6
1.8
RF FREQUENCY (GHz)
V
ATT
Figure 48. Conversion Gain vs. RF Frequency at Maximum Gain for Various
Supply Voltages, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
Figure 51. Conversion Gain vs. VATT at Various Temperatures, fIF = 3.5 GHz,
fRF = 28 GHz and 39 GHz (Upper Sideband)
25
20
15
10
5
25
+85°C AT 28GHz
+25°C AT 28GHz
20
–40°C AT 28GHz
+85°C AT 39GHz
+25°C AT 39GHz
15
–40°C AT 39GHz
10
0
5
0
–5
–10
+6dBm UPPER SIDEBAND
0dBm UPPER SIDEBAND
–6dBm UPPER SIDEBAND
+6dBm LOWER SIDEBAND
0dBm LOWER SIDEBAND
–6dBm LOWER SIDEBAND
–15
–20
–25
–30
–5
–10
–15
23
25
27
29
31
33
35
37
39
41
43
45
0
0.2
0.4
0.6
0.8
1.0
(V)
1.2
1.4
1.6
1.8
RF FREQUENCY (GHz)
V
ATT
Figure 49. Conversion Gain vs. RF Frequency at Maximum Gain for Various
LO Inputs, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
Figure 52. Conversion Gain vs. VATT at Various Temperatures, fIF = 3.5 GHz ,
RF = 28 GHz and 39 GHz (Lower Sideband)
f
Rev. A | Page 17 of 42
ADMV1014
Data Sheet
12
10
8
+85°C UPPER SIDEBAND
10
8
+25°C UPPER SIDEBAND
–40°C UPPER SIDEBAND
+85°C LOWER SIDEBAND
+25°C LOWER SIDEBAND
–40°C LOWER SIDEBAND
6
6
4
4
2
0
2
–2
–4
–6
–8
–10
–12
39GHz UPPER SIDEBAND
0
28GHz UPPER SIDEBAND
39GHz LOWER SIDEBAND
28GHz LOWER SIDEBAND
–2
–4
–6
23
25
27
29
31
33
35
37
39
41
43
45
0
0.2
0.4
0.6
0.8
1.0
(V)
1.2
1.4
1.6
1.8
RF FREQUENCY (GHz)
V
ATT
Figure 53. Input IP3 vs. RF Frequency at Maximum Gain for Various
Temperatures, RF Amplitude = −30 dBm per Tone at 20 MHz Spacing,
fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
Figure 56. Input IP3 vs. VATT for Various RF Frequencies (fRF), RF Amplitude =
−30 dBm per Tone at 20 MHz Spacing, fIF = 3.5 GHz at fRF = 28 GHz and
39 GHz (Upper Sideband and Lower Sideband)
12
10
8
10
39GHz UPPER SIDEBAND
8
28GHz UPPER SIDEBAND
39GHz LOWER SIDEBAND
28GHz LOWER SIDEBAND
6
4
6
4
2
2
0
0
–2
–2
–4
–6
–8
–10
–4
3.5V UPPER SIDEBAND
–6
–8
3.3V UPPER SIDEBAND
3.1V UPPER SIDEBAND
3.5V LOWER SIDEBAND
3.3V LOWER SIDEBAND
3.1V LOWER SIDEBAND
–10
–12
23
25
27
29
31
33
35
37
39
41
43
45
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
RF FREQUENCY (GHz)
IF FREQUENCY (GHz)
Figure 57. Input IP3 vs. IF Frequency at Maximum Gain, RF Amplitude =
−30 dBm per Tone at 20 MHz Spacing at fRF = 28 GHz and 39 GHz
(Upper Sideband and Lower Sideband)
Figure 54. Input IP3 vs. RF Frequency at Maximum Gain for Various Supply
Voltages, RF Amplitude = −30 dBm per Tone at 20 MHz Spacing, fIF = 3.5 GHz
(Upper Sideband and Lower Sideband)
5
12
10
8
39GHz UPPER SIDEBAND
4
28GHz UPPER SIDEBAND
39GHz LOWER SIDEBAND
28GHz LOWER SIDEBAND
3
2
6
4
1
2
0
0
–2
–1
–2
–3
–4
–5
–4
+6dBm UPPER SIDEBAND
–6
–8
0dBm UPPER SIDEBAND
–6dBm UPPER SIDEBAND
+6dBm LOWER SIDEBAND
0dBm LOWER SIDEBAND
–6dBm LOWER SIDEBAND
–10
–12
–30 –29 –28 –27 –26 –25 –24 –23 –22 –21 –20
23
25
27
29
31
33
35
37
39
41
43
45
INPUT POWER (dBm)
RF FREQUENCY (GHz)
Figure 58. Input IP3 vs. Input Power for Various RF Frequencies (fRF), at
20 MHz Spacing, fIF = 3.5 GHz, fRF = 28 GHz and 39 GHz
(Upper Sideband and Lower Sideband)
Figure 55. Input IP3 vs. RF Frequency at Maximum gain for Various LO Inputs,
RF Amplitude = −30 dBm per Tone at 20 MHz Spacing, fIF = 3.5 GHz
(Upper Sideband and Lower Sideband)
Rev. A | Page 18 of 42
Data Sheet
ADMV1014
12
9
8
7
6
5
4
3
2
1
0
+85°C UPPER SIDEBAND
+25°C UPPER SIDEBAND
–40°C UPPER SIDEBAND
+85°C LOWER SIDEBAND
+25°C LOWER SIDEBAND
–40°C LOWER SIDEBAND
10
8
6
39GHz UPPER SIDEBAND
28GHz UPPER SIDEBAND
39GHz LOWER SIDEBAND
28GHz LOWER SIDEBAND
4
2
0
23
25
27
29
31
33
35
37
39
41
43
45
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
RF FREQUENCY (GHz)
IF FREQUENCY (GHz)
Figure 59. Noise Figure vs. RF Frequency at Maximum Gain for Various
Temperatures, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
Figure 62. Noise Figure vs. IF Frequency at Maximum Gain, fRF = 28 GHz and
39 GHz (Upper Sideband and Lower Sideband)
12
10
8
22
+85°C AT 28GHz
20
+25°C AT 28GHz
–40°C AT 28GHz
18
+85°C AT 39GHz
+25°C AT 39GHz
16
14
12
10
8
–40°C AT 39GHz
6
4
3.5V UPPER SIDEBAND
3.3V UPPER SIDEBAND
3.1V UPPER SIDEBAND
3.5V LOWER SIDEBAND
3.3V LOWER SIDEBAND
3.1V LOWER SIDEBAND
6
4
2
2
0
23
0
25
27
29
31
33
35
37
39
41
43
45
0
0.2
0.4
0.6
0.8
1.0
(V)
1.2
1.4
1.6
1.8
RF FREQUENCY (GHz)
V
ATT
Figure 63. Noise Figure vs. VATT at Various Temperatures, fIF = 3.5 GHz,
fRF = 28 GHz and 39 GHz (Upper Sideband)
Figure 60. Noise Figure vs. RF Frequency at Maximum Gain for Various
Supply Voltages, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
22
+85°C AT 28GHz
12
10
8
20
+25°C AT 28GHz
–40°C AT 28GHz
18
+85°C AT 39GHz
+25°C AT 39GHz
16
14
12
10
8
–40°C AT 39GHz
6
6
4
+6dBm UPPER SIDEBAND
0dBm UPPER SIDEBAND
–6dBm UPPER SIDEBAND
+6dBm LOWER SIDEBAND
0dBm LOWER SIDEBAND
–6dBm LOWER SIDEBAND
4
2
2
0
0
0.2
0.4
0.6
0.8
V
1.0
(V)
1.2
1.4
1.6
1.8
0
23
25
27
29
31
33
35
37
39
41
43
45
ATT
RF FREQUENCY (GHz)
Figure 64. Noise Figure vs. VATT at Various Temperatures, fIF = 3.5 GHz,
RF = 28 GHz and 39 GHz (Lower Sideband)
Figure 61. Noise Figure vs. RF Frequency at Maximum Gain for Various LO
Inputs, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
f
Rev. A | Page 19 of 42
ADMV1014
Data Sheet
0
1
–1
+85°C UPPER SIDEBAND
+25°C UPPER SIDEBAND
–40°C UPPER SIDEBAND
+85°C LOWER SIDEBAND
+25°C LOWER SIDEBAND
–40°C LOWER SIDEBAND
–2
–4
39GHz UPPER SIDEBAND
28GHz UPPER SIDEBAND
39GHz LOWER SIDEBAND
28GHz LOWER SIDEBAND
–3
–6
–5
–8
–10
–12
–14
–16
–18
–20
–7
–9
–11
–13
–15
23
25
27
29
31
33
35
37
39
41
43
45
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
RF FREQUENCY (GHz)
IF FREQUENCY (GHz)
Figure 65. Input P1dB vs. RF Frequency at Maximum Gain for Various
Temperatures, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
Figure 68. Input P1dB vs. IF Frequency at Maximum Gain,
fRF = 28 GHz and 39 GHz (Upper Sideband and Lower Sideband)
0
–2
2
0
–4
–2
–4
–6
–8
–6
–8
–10
–12
–10
–14
3.5V UPPER SIDEBAND
+85°C AT 28GHz
3.3V UPPER SIDEBAND
+25°C AT 28GHz
–12
–16
–18
–20
3.1V UPPER SIDEBAND
3.5V LOWER SIDEBAND
3.3V LOWER SIDEBAND
3.1V LOWER SIDEBAND
–40°C AT 28GHz
+85°C AT 39GHz
–14
–16
+25°C AT 39GHz
–40°C AT 39GHz
23
25
27
29
31
33
35
37
39
41
43
45
0
0.2
0.4
0.6
0.8
1.0
(V)
1.2
1.4
1.6
1.8
RF FREQUENCY (GHz)
V
ATT
Figure 69. Input P1dB vs. VATT at Various Temperatures, fIF = 3.5 GHz,
fRF = 28 GHz and 39 GHz (Upper Sideband)
Figure 66. Input P1dB vs. RF Frequency at Maximum Gain for Various Supply
Voltages, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
2
0
0
–2
–2
–4
–6
–8
–4
–6
–8
–10
–12
–10
+85°C AT 28GHz
–14
+6dBm UPPER SIDEBAND
+25°C AT 28GHz
–12
0dBm UPPER SIDEBAND
–40°C AT 28GHz
+85°C AT 39GHz
+25°C AT 39GHz
–40°C AT 39GHz
–16
–18
–20
–6dBm UPPER SIDEBAND
+6dBm LOWER SIDEBAND
0dBm LOWER SIDEBAND
–6dBm LOWER SIDEBAND
–14
–16
0
0.2
0.4
0.6
0.8
1.0
(V)
1.2
1.4
1.6
1.8
24
26
28
30
32
34
36
38
40
42
44
V
ATT
RF FREQUENCY (GHz)
Figure 70. Input P1dB vs. VATT at Various Temperatures, fIF = 3.5 GHz,
RF = 28 GHz and 39 GHz (Lower Sideband)
Figure 67. Input P1dB vs. RF Frequency at Maximum Gain for Various LO
Inputs, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
f
Rev. A | Page 20 of 42
Data Sheet
ADMV1014
60
60
50
40
30
20
10
0
+85°C UPPER SIDEBAND
+6dBm UPPER SIDEBAND
0dBm UPPER SIDEBAND
–6dBm UPPER SIDEBAND
+6dBm LOWER SIDEBAND
0dBm LOWER SIDEBAND
–6dBm LOWER SIDEBAND
+25°C UPPER SIDEBAND
–40°C UPPER SIDEBAND
+85°C LOWER SIDEBAND
+25°C LOWER SIDEBAND
–40°C LOWER SIDEBAND
50
40
30
20
10
0
23
25
27
29
31
33
35
37
39
41
43
45
23
25
27
29
31
33
35
37
39
41
43
45
RF INPUT FREQUENCY (GHz)
RF INPUT FREQUENCY (GHz)
Figure 74. Image Rejection vs. RF Input Frequency at Maximum Gain for
Various LO Inputs, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
Figure 71. Image Rejection vs. RF Input Frequency at Maximum Gain for Various
Temperatures, fIF = 3.5 GHz (Upper Sideband and Lower Sideband), Uncalibrated
60
60
+85°C UPPER SIDEBAND
39GHz UPPER SIDEBAND
+25°C UPPER SIDEBAND
50
50
28GHz UPPER SIDEBAND
–40°C UPPER SIDEBAND
39GHz LOWER SIDEBAND
28GHz LOWER SIDEBAND
+85°C LOWER SIDEBAND
+25°C LOWER SIDEBAND
–40°C LOWER SIDEBAND
40
30
20
10
0
40
30
20
10
0
0
23
25
27
29
31
33
35
37
39
41
43
45
1
2
3
4
5
6
7
IF INPUT FREQUENCY (GHz)
RF INPUT FREQUENCY (GHz)
Figure 72. Image Rejection vs. RF Input Frequency at Maximum Gain for Various
Temperatures, fIF = 3.5 GHz (Upper Sideband and Lower Sideband), Calibrated
Figure 75. Image Rejection vs. IF Input Frequency at Maximum Gain,
f
RF = 28 GHz and 39 GHz (Upper Sideband and Lower Sideband)
60
60
3.5V UPPER SIDEBAND
3.3V UPPER SIDEBAND
39GHz UPPER SIDEBAND
50
50
3.1V UPPER SIDEBAND
3.5V LOWER SIDEBAND
3.3V LOWER SIDEBAND
28GHz UPPER SIDEBAND
39GHz LOWER SIDEBAND
28GHz LOWER SIDEBAND
3.1V LOWER SIDEBAND
40
40
30
20
10
0
30
20
10
0
23
25
27
29
31
33
35
37
39
41
43
45
0
0.2
0.4
0.6
0.8
1.0
(V)
1.2
1.4
1.6
1.8
RF INPUT FREQUENCY (GHz)
V
ATT
Figure 73. Image Rejection vs. RF Input Frequency at Maximum Gain for Various
Supply Voltages, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
Figure 76. Image Rejection vs. VATT at Various RF Frequencies (fRF),
fIF = 3.5 GHz, fRF = 28 GHz and 39 GHz (Upper Sideband and Lower Sideband)
Rev. A | Page 21 of 42
ADMV1014
Data Sheet
20
18
16
14
12
10
8
20
18
16
14
12
10
8
0
1
2
3
4
5
6
7
8
12
13
14
15
6
6
9
10
11
0
4
2
0
4
1
3
2
7
15
0
23
23
25
27
29
31
33
35
37
39
41
43
45
25
27
29
31
33
35
37
39
41
43
45
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 80. Conversion Gain vs. RF Frequency at Different IF_AMP_
FINE_GAIN_x Settings, fIF = 3.5 GHz (Upper Sideband); Register 0x08, Bits[7:4]
and Bits[3:0] Are the Same
Figure 77. Conversion Gain vs. RF Frequency at Different
IF_AMP_COARSE_GAIN_x Settings, fIF = 3.5 GHz (Upper Sideband); Settings for
Register 0x08, Bits[11:8] and Register 0x09, Bits[15:12] Are the Same
5
4
5
4
3
3
2
2
1
1
0
0
–1
–1
0
0
1
2
3
4
5
6
7
8
12
13
14
15
–2
1
–2
–3
–4
–5
9
3
10
11
–3
7
15
–4
–5
23
25
27
29
31
33
35
37
39
41
43
45
23
25
27
29
31
33
35
37
39
41
43
45
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 78. Input IP3 vs. RF Frequency at Different IF_AMP_COARSE_GAIN_x
Settings, fIF = 3.5 GHz (Upper Sideband); Settings for Register 0x08, Bits[11:8]
and Register 0x09, Bits[15:12] Are the Same
Figure 81. Input IP3 vs. RF Frequency at Different IF_AMP_FINE_GAIN_x
Settings, fIF = 3.5 GHz (Upper Sideband); Settings for Register 0x08, Bits[7:4]
and Bits[3:0] Are the Same
10
9
10
9
8
8
7
7
6
6
5
5
4
4
3
0
1
2
3
4
5
6
7
8
12
13
14
15
3
2
1
0
0
9
2
1
0
1
10
11
3
7
15
23
25
27
29
31
33
35
37
39
41
43
45
23
25
27
29
31
33
35
37
39
41
43
45
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 79. Noise Figure vs. RF Frequency at Different
IF_AMP_COARSE_GAIN_x Settings, fIF = 3.5 GHz (Upper Sideband); Settings for
Register 0x08, Bits[11:8] and Register 0x09, Bits[15:12] Are the Same
Figure 82. Noise Figure vs. RF Frequency at Different IF_AMP_FINE_GAIN_x
Settings, fIF = 3.5 GHz (Upper Sideband); Settings for Register 0x08, Bits[7:4]
and Bits[3:0] Are the Same
Rev. A | Page 22 of 42
Data Sheet
ADMV1014
1.0
0.8
1.0
0.8
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
IF OUTPUT FREQUENCY (GHz)
IF OUTPUT FREQUENCY (GHz)
Figure 83. I/Q Magnitude Error vs. IF Output Frequency, Referenced to IF_I
Output, fRF = 28 GHz, for Various Temperatures, at Maximum Gain
Figure 85. I/Q Magnitude Error vs. IF Output Frequency, Referenced to IF_I
Output, fRF = 39 GHz, for Various Temperatures, at Maximum Gain
5
4
5
4
3
3
2
2
1
1
0
0
–1
–1
–2
–3
–4
–5
–2
–3
–4
–5
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
IF OUTPUT FREQUENCY (GHz)
IF OUTPUT FREQUENCY (GHz)
Figure 84. I/Q Phase Error vs. IF Output Frequency, Referenced to IF_I Output,
RF = 28 GHz, for Various Temperatures, at Maximum Gain
Figure 86. I/Q Phase Error vs. IF Output Frequency, Referenced to IF_I Output,
RF = 39 GHz, for Various Temperatures, at Maximum Gain
f
f
Rev. A | Page 23 of 42
ADMV1014
Data Sheet
OUTPUT DETECTOR PERFORMANCE
RF amplitude = −30 dBm, measurements performed with a 0 mV dc bias. VCC_MIXER = VCC_QUAD = VCC_BG = VCC_LNA =
VCC_VGA = VCC_IF_BB = 3.3 V, DVDD = VCC_VVA = 1.8 V, Register 0x0B is set to 0x727C, Register 0x03, Bit 6 = 0, Register 0x03,
Bits[13:12] set to 11, and TA = 25°C, unless otherwise noted.
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3.0
2.5
2.0
1.5
1.0
0.5
–22
–27
–32
+85°C = 64
+85°C = 8
+85°C = 0
+25°C = 64
+25°C = 8
+25°C = 0
–40°C = 64
–40°C = 8
–40°C = 0
–40
–35
–30
–25
–20
–15
–10
23
25
27
29
31
33
35
37
39
41
43
45
RF INPUT POWER (dBm)
RF INPUT FREQUENCY (GHz)
Figure 87. VDET vs. RF Input Power, fRF = 28 GHz for Various Temperatures
and DET_PROG Settings
Figure 89. VDET vs. RF Input Frequency at Various Input Power Levels,
DET_PROG = 8
3.5
3.0
2.5
2.0
1.5
1.0
5
4
3
2
1
0
+85°C = 64
+85°C = 8
+85°C = 0
+25°C = 64
+25°C = 8
+25°C = 0
–40°C = 64
–40°C = 8
–40°C = 0
–1
–2
–3
–4
–5
+85°C = 64
+85°C = 8
+85°C = 0
+25°C = 64
+25°C = 8
+25°C = 0
–40°C = 64
–40°C = 8
–40°C = 0
0.5
0
–40
–35
–30
–25
–20
–15
–10
–40
–35
–30
–25
–20
–15
–10
RF INPUT POWER (dBm)
RF INPUT POWER (dBm)
Figure 88. VDET vs. RF Input Power, fRF = 39 GHz for Various Temperatures
and DET_PROG Settings
Figure 90. VDET Linearity Error vs. RF Input Power, fRF = 28 GHz for Various
Temperatures and DET_PROG Settings
5
4
3
2
1
0
–1
–2
–3
–4
–5
+85°C = 64
+85°C = 8
+85°C = 0
+25°C = 64
+25°C = 8
+25°C = 0
–40°C = 64
–40°C = 8
–40°C = 0
–40
–35
–30
–25
–20
–15
–10
RF INPUT POWER (dBm)
Figure 91. VDET Linearity Error vs. RF Input Power, fRF = 39 GHz for Various
Temperatures and DET_PROG Settings
Rev. A | Page 24 of 42
Data Sheet
ADMV1014
RETURN LOSS AND ISOLATIONS
RF amplitude = −30 dBm, measurements performed with a 0 mV dc bias. VCC_MIXER = VCC_QUAD = VCC_BG = VCC_LNA =
VCC_VGA = VCC_IF_BB = 3.3 V, DVDD = VCC_VVA = 1.8 V, Register 0x0B is set to 0x727C, Register 0x03, Bits[13:12] are set to 11,
and TA = 25°C, unless otherwise noted.
Measurements in IF mode performed with a 90° hybrid, Register 0x03, Bit 11 = 0, Register 0x03, Bit 8 = 1, unless otherwise noted.
Measurements in I/Q mode are measured as a composite of the I and Q channel performed, VCM = 1.15 V, Register 0x03, Bit 11 = 1, and
Register 0x03, Bit 8 = 0, unless otherwise noted.
0
0
I
Q
–5
–5
–10
–15
–20
–25
–30
–35
–10
–15
–20
–25
–30
–35
23
25
27
29
31
33
35
37
39
41
43
45
0
1
2
3
4
5
6
7
RF FREQUENCY (GHz)
I/Q FREQUENCY (GHz)
Figure 92. RF Input Return Loss vs. RF Frequency
Figure 95. I/Q Differential Return Loss vs. I/Q Frequency (Taken Without
Hybrids or Baluns)
0
–5
0
–5
–10
–15
–20
–25
–30
–35
–10
–15
–20
LO
LO
LO
N
P
DIFF
IF_I
IF_Q
–25
–30
–35
4
5
6
7
8
9
10
11
12
0
1
2
3
4
5
6
7
LO FREQUENCY (GHz)
IF FREQUENCY (GHz)
Figure 93. LO Return Loss vs. LO Frequency
Figure 96. IF Return Loss vs. IF Frequency (Taken Without Hybrid)
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
–50
LOx1 = 1.8
LOx1 = +85°C
LOx1 = +25°C
LOx1 = –40°C
LOx4 = +85°C
LOx4 = +25°C
LOx4 = –40°C
LOx1 = 0.9
–55
LOx1 = 0
LOx4 = 1.8
–60
LOx4 = 0.9
LOx4 = 0
–65
–70
–75
–80
–85
–90
–95
–100
4
5
6
7
8
9
10
11
12
4
5
6
7
8
9
10
11
12
LO INPUT FREQUENCY (GHz)
LO INPUT FREQUENCY (GHz)
Figure 94. LO to RF Leakage vs. LO Input Frequency for Various Temperatures
at Different Gain Settings
Figure 97. LO to IF Leakage vs. LO Input Frequency at Different VCTRL Settings
Rev. A | Page 25 of 42
ADMV1014
Data Sheet
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
I = +85°C
I = +25°C
I = –40°C
Q = +85°C
Q = +25°C
Q = –40°C
I = 0
I = 1
I = 3
I = 7
I = 15
Q = 0
Q = 1
Q = 3
Q = 7
Q = 15
4
5
6
7
8
9
10
11
12
4
5
6
7
8
9
10
11
12
LO INPUT FREQUENCY (GHz)
LO INPUT FREQUENCY (GHz)
Figure 100. LO to IF Leakage, vs. LO Input Frequency at Different IF Amplifier
Gain Settings (Taken Without Hybrid)
Figure 98. LO to IF Leakage vs. LO Input Frequency at Various Temperatures
–40
–45
–50
–55
–60
–65
–70
–75
–40
–45
–50
–55
–60
–65
–70
–75
I_P = +85°C
I_P = +25°C
I_P = –40°C
I_N = +85°C
I_N = +25°C
I_N = –40°C
Q_P = +85°C
Q_P = +25°C
Q_P = –40°C
Q_N = +85°C
Q_N = +25°C
Q_N = –40°C
I_P = 0
I_P = 3
I_N = 0
I_N = 3
Q_P = 0
Q_P = 3
Q_N = 0
Q_N = 3
–80
–85
–90
–80
–85
–90
4
5
6
7
8
9
10
11
12
4
6
8
10
12
LO INPUT FREQUENCY (GHz)
LO INPUT FREQUENCY (GHz)
Figure 101. Fundamental LO to I/Q Leakage vs. LO Input Frequency at
Different Baseband Amplifier Gain Settings
Figure 99. LO to I/Q Leakage vs. LO Input Frequency at Various Temperatures
(Taken Without Hybrid)
Rev. A | Page 26 of 42
Data Sheet
ADMV1014
M × N SPURIOUS PERFORMANCE
IF Mode
Mixer spurious products are measured in dBc from the IF
output power level. Spurious values are measured using the
following equation:
Measurements are made on the IF_I port. Data is taken without
any 90° hybrid.
IF frequency (fIF) = 3.5 GHz, LO= 6.125 GHz at 0 dBm, and
|(M × RF)+ (N × LO)|
f
RF = 28 GHz at −30 dBm.
N/A means not applicable. Blank cells in the spurious
performance tables indicate that the frequency is above 50 GHz
and is not measured.
N × LO
4
0
1
2
3
5
6
7
8
䤁
81 93 85 93 93 99 96
94 89 63
Ĥ
−2
−1
0
The LO frequencies are referred from the frequencies applied
to the LO_x pin of the ADMV1014. RF amplitude = −30 dBm,
measurements performed with a 0 mV dc bias. VCC_MIXER =
VCC_QUAD = VCC_BG = VCC_LNA = VCC_VGA = VCC_
IF_BB = 3.3 V, DVDD = VCC_VVA = 1.8 V, Register 0x0B is set
to 0x727C, Register 0x03, Bits[13:12] are set to 11, and TA =
25°C, unless otherwise noted.
66
0
44 46 92 78
M × RF
N/A 45 43 65 54 71 64 80 58
66 84 84 81
+1
fIF = 3.5 GHz, LO= 8.875 GHz at 0 dBm, and fRF = 39 GHz at
−30 dBm.
N × LO
0
1
2
3
4
5
6
7
8
Measurements in IF mode performed with Register 0x03, Bit 11 = 0
and Register 0x03, Bit 8 = 1, unless otherwise noted.
84 92 91 93 59
39 91 92 89
−2
−1
0
62
93 81 71
0
M × RF
The measurements in I/Q mode are as follows: VCM = 1.15 V,
Register 0x03, Bit 11 = 1, and Register 0x03, Bit 8 = 0, unless
otherwise noted.
N/A 47 68 75 50 75
62 89
+1
fIF = 3.5 GHz, LO= 7.875 GHz at 0 dBm, and fRF = 28 GHz at
−30 dBm.
I/Q Mode
Measurements are made on the I_P port. Data is taken without
any hybrids or baluns.
N × LO
0
1
2
3
4
5
6
7
8
BB frequency (fBB) =100 MHz, LO= 6.975 GHz at 0 dBm, and
90 86 83 95 94 83 89 58
93 70 41 65 90 89 83
−2
−1
0
f
RF = 28 GHz at −30 dBm.
70
0
M × RF
N × LO
N/A 47 62 66 49 74 86
70 90 88
0
1
2
3
4
5
6
7
8
+1
85 87 87 82
90 54 46
86
45
103 96
59
−2
−1
0
fIF = 3.5 GHz, LO= 10.5 GHz at 0 dBm, and fRF =39 GHz at
−30 dBm
61
0
52
78
106 82
81
M × RF
N/A 43 55 65
61 91 80 82
48
76
N × LO
+1
0
1
2
3
4
5
6
7
8
fBB = 100 MHz, LO= 9.725 GHz at 0 dBm, and fRF = 39 GHz at
−30 dBm.
85 87 94 94 90 58
91 81 35 87 84 84 82
−2
−1
0
61
0
M × RF
N × LO
N/A 39 51 62 53
61 89
0
1
2
3
4
5
6
7
8
+1
85 88 87 92 87 60
92 56 47 51 61 85 84
−2
−1
0
63
0
M × RF
N/A 42 48 67 51 85
42 48
+1
Rev. A | Page 27 of 42
ADMV1014
Data Sheet
THEORY OF OPERATION
The ADMV1014 is a wideband microwave downconverter
optimized for microwave radio designs operating in the 24 GHz
to 44 GHz frequency range. See Figure 1 for a functional block
diagram of the device. The ADMV1014 digital settings are
controlled via the SPI. The ADMV1014 has two modes of
operation:
The baseband I/Q ports are designed to operate from dc to
6.0 GHz at each I and Q channel.
The BB output VCM can be changed from 1.05 V to 1.85 V. To
change the VCM, set BB_SWITCH_HIGH_LOW_COMMMON
(Register 0x0A, Bit 0) to be the opposite of Register 0x0A, Bit 6.
Also, set the MIXER_VGATE bit field (Register 0x07, Bits[15:9])
and the BB_AMP_REF_GEN bit field (Register 0x0A, Bits[6:3])
based on Table 6.
Baseband quadrature demodulation (I/Q mode)
Image reject I/Q downconversion (IF mode)
Table 6 provides the correct setting for these bit fields vs. the
required common-mode voltage.
START-UP SEQUENCE
The ADMV1014 SPI settings require its default settings to be
changed during startup for optimum performance. To use the
SPI, toggle the RST pin to logic low and then logic high to
perform a hard reset before starting up the device.
The VCM can be further adjusted on each I or Q channel by
15 mV by setting the BB_AMP_OFFSET_I bit field
(Register 0x09, Bits[4:0]) and the BB_AMP_OFFSET_Q bit field
(Register 0x09, Bits[9:5]) for each VCM setting shown in Table 6.
Set Register 0x0B to 0x727C after every power-up or reset. Set
Register 0x03, Bits[13:12] to 11 after every power-up or reset.
The most significant bit (MSB) for each bit field is the sign bit.
When the MSB is 1, the values of the four lower bits are
positive. When the MSB is 0, the values of the four lower bits
are negative. These bits also offer input IP2 and common-mode
rejection optimization.
BASEBAND QUADRATURE DEMODULATION (I/Q
MODE)
In I/Q mode, the output impedance of the baseband I/Q ports is
100 Ω differential. These outputs are designed to be loaded to a
dc-coupled, differential, 100 Ω load. I_P and I_N are the
differential baseband I outputs. Q_P and Q_N are the
differential baseband Q outputs.
The BB I/Q section of the ADMV1014 also features a baseband
amplifier with a digital attenuator that is controlled by setting
the BB_AMP_GAIN_CTRL bit field (Register 0x0A, Bits[2:1]).
Figure 44, Figure 45, and Figure 46 show the performance of the
baseband digital attenuator.
To set the ADMV1014 in I/Q mode, set BB_AMP_PD
(Register 0x03, Bit 8) to 0 and set IF_AMP_PD (Register 0x03,
Bit 11) to 1.
The Baseband Quadrature Demodulation to Very Low
Frequencies section shows the baseband performance to very
low demodulation frequencies.
Table 6. Common-Mode Voltage Settings
MIXER_VGATE
(Register 0x07, Bits[15:9])
BB_AMP_REF_GEN
(Register 0x0A, Bits[6:3])
BB_SWITCH_HIGH_LOW_COMMON_MODE
(Register 0x0A, Bit 0)
VCM (V)
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1101010
1101011
1101100
1101110
1101111
1110000
1110001
1110010
1110101
1110110
1110111
1111000
1111010
1111011
0101100
0101101
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Rev. A | Page 28 of 42
Data Sheet
ADMV1014
path can switch from differential to single-ended operation by
setting the QUAD_SE_MODE bits (Register 0x04, Bits[9:6]).
See the Performance Between Differential vs. Single-Ended LO
Input section for more information.
IMAGE REJECTION DOWNCONVERSION
The ADMV1014 features the ability to downconvert to a real IF
output anywhere from 800 MHz to 6000 MHz, while suppressing
the unwanted image sideband by typically better than 30 dBc.
The IF outputs are quadrature to each other, 50 Ω single-ended,
and are internally ac coupled. IF_I and IF_Q are the quadrature IF
outputs. An external 90° hybrid is required to select the appropriate
sideband.
Figure 102 shows a block diagram of the LO path.
To configure the ADMV1014 in IF mode, set BB_AMP_PD
(Register 0x03, Bit 8) to 1 and set IF_AMP_PD (Register 0x03,
Bit 11) to 0
LO_N
LO_P
4 × LO_N
4 × LO_P
×4
AMP
Each IF output features an amplifier with a digital attenuator.
The digital attenuator can be adjusted using fine or coarse steps.
The coarse steps for the IF_I can be adjusted using the IF_AMP_
COARSE_GAIN_I bit field (Register 0x08, Bits[11:8]). The coarse
steps for the IF_Q can be adjusted using the IF_AMP_COARSE_
GAIN_Q bit field (Register 0x09, Bits[15:12]). Each course gain
bit field has five settings. The fine steps for IF_I can be adjusted
using the IF_AMP_FINE_GAIN_I bit field (Register 0x08,
Bits[3:0]). The fine steps for the IF_Q can be adjusted using the
IF_AMP_FINE_GAIN_Q bit field (Register 0x08, Bits[7:4]).
Figure 77 to Figure 82 show the performance of these four bit
fields.
Figure 102. LO Path Block Diagram
Enable the quadrupler by setting the QUAD_IBIAS_PD bit
(Register 0x03, Bit 7) to 0 and the QUAD_BG_PD bit
(Register 0x03, Bit 9) to 0. To power down the quadrupler, set
both of these bits to 1.
An unwanted image can be downconverted from the
quadrature error in generating the quadrature LO signals.
Deviation from ideal quadrature (that is, total image rejection
and no image tone is downconverted) on these signals limits the
amount of achievable image rejection.
DETECTOR
The ADMV1014 offers about 25° of quadrature phase
adjustment in the LO path quadrature signals. Make these
adjustments through the LOAMP_PH_ADJ_I_FINE bits
(Register 0x05, Bits[15:9]) and the LOAMP_PH_ADJ_Q_FINE
(Register 0x05, Bits[8:2]) bits. These bits reject the unwanted
sideband signal. In IF mode amplitude adjustments can be made
to the complex outputs via IF_AMP_FINE_GAIN_Q
(Register 0x08, Bits[7:4]) and IF_AMP_FINE_GAIN_I
(Register 0x08, Bits[3:0]) to further reduce the unwanted
sideband.
The ADMV1014 features a square law detector that produces a
voltage linearly, according to the square of the RF voltage
output from the low noise amplifier. The detector can be
enabled by setting the DET_EN bit (Register 0x03, Bit 6) to 0. The
detector can be turned off by setting this bit to 1. The detector
linear range can be adjusted by setting the DET_PROG bit field
(Register 0x07, Bits[6:0]). These ranges are specified based on
the input power into the detector coming from the output of the
low noise amplifier. Each DET_PROG setting offers an
approximate 20 dB of 1 dB dynamic range based on a two-
point linear regression from an ideal line for one temperature at
each DET_PROG setting. See Figure 89 to Figure 91 for more
performance information of the detector.
POWER-DOWN
The SPI of the ADMV1014 allows the user to power down
device circuits and reduce power consumption. There are two
power-down modes: band gap power-down mode (BG_PD)
and individual power-down circuits mode. The BG_PD bit
(Register 0x03, Bit 5) and the QUAD_BG_PD bit (Register 0x03,
Bit 9) power down the band gap circuit. The QUAD_IBIAS_PD
bit (Register 0x03, Bit 7) and the IBIAS_PD bit (Register 0x03,
Bit 14) power down the specific circuits.
LO INPUT PATH
The LO input path operates from 5.4 GHz to 10.25 GHz with an
LO amplitude range of −6 dBm to +6 dBm. The LO has an
internal quadrupler (×4) and a programmable band-pass filter.
The LO band-pass filter is programmable using QUAD_FILTERS
(Register 0x04 Bits[3:0]). See the Performance at Different
Quad Filter Settings section for more information on the
QUAD_FILTERS settings.
Table 7 shows the circuits that are controlled by their related
power-down bit, the typical power savings, and the latency
requirement to power the circuits back up.
The LO path can operate either differentially or single-ended
(SE). LOIP and LOIN are the inputs to the LO path. The LO
Rev. A | Page 29 of 42
ADMV1014
Data Sheet
Table 7. Power-Down Power and Latency Requirements
Typical Power
Savings (mW)
Power-Up
Latency (μs)
Power-Down
Latency (μs)
Bit Name
Circuit
IBIAS_PD
QUAD_IBIAS_PD
BG_PD and QUAD_BG_PD
IBIAS_PD, IF_AMP_PD, QUAD_BG_PD,
BB_AMP_PD, QUAD_IBIAS_PD, BG_PD
Receiver bias current (IBIAS
LO path
Band gap
Entire chip
)
1172
238
1423
1435
5
4
4.5
5
<1
<1
<1
<1
SEN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SCLK
SDI
R/W A5
A4
A3
A2
A1
A0
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
P
Figure 103. Write Serial Port Timing Diagram
SEN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SCLK
SDI
R/W A5
A4
A3
A2
A1
A0
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
P
SDO
Figure 104. Read Serial Port Timing Diagram
Sideband. The ADMV1014 input logic level for the write cycle
supports an 1.8 V interface.
SERIAL PORT INTERFACE (SPI)
The SPI of the ADMV1014 allows the user to configure the device
for specific functions or operations via a 4-pin SPI port. This
interface provides users with added flexibility and customization.
The SPI consists of four control lines: SCLK, SDIN, SDO, and
For a read cycle, up to 16 bits of serial read data are shifted out,
MSB first. After the 16 bits of data shift out, the parity bit shifts
out. The output logic level for a read cycle is 1.8 V.
The parity bit always follows the direction of the data. If parity
is not used, the transmitting end transmits zero instead of parity.
The parity is odd, which means that the total number of ones
transmitted during a command, including the read/write bit,
the address bit, the data bit, and the parity bit, must be odd.
SEN
.
The ADMV1014 protocol consists of a write/read bit followed
by six register address bits, 16 data bits, and a parity bit. Both
the address and data fields are organized most significant bit
(MSB) first and end with the least significant bit. For a write, set
the first bit to 0. For a read, set the first bit to 1.
Figure 103 and Figure 104 show the SPI write and read
protocol, respectively.
The write cycle sampling must be performed on the rising edge.
The 16 bits of the serial write data are shifted in, MSB to Lower
Rev. A | Page 30 of 42
Data Sheet
ADMV1014
APPLICATIONS INFORMATION
ERROR VECTOR MAGNITUDE (EVM)
PERFORMANCE
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
Figure 105 shows the EVM vs. input power performance of the
ADMV1014 in IF mode at maximum gain, upper sideband,
25°C and 0 dBm LO input power. The EVM measurement was
performed using four 100 MHz, 5G-NR, 256QAM waveforms.
The EVM shown is the average of the four channels. The EVM
of the test equipment was not de-embedded.
Figure 106 shows the constellation diagram and EVM statistics
of each of the four channels at −30 dBm input power.
–45
–40
–35
–30
(dBm)
–25
–20
–15
P
IN
Figure 105. EVM vs. Input Power at 28 GHz, VCTRL = 0 V, TA = 25°C,
LO = 0 dBm, Upper Sideband (Low-Side LO), IF = 3.5 GHz
Figure 106. Constellation Diagram and EVM Statistics per Channel
Rev. A | Page 31 of 42
ADMV1014
Data Sheet
50
45
40
35
30
25
20
15
10
5
BASEBAND QUADRATURE DEMODULATION TO
VERY LOW FREQUENCIES
Figure 107 to Figure 111 show the I/Q mode performance at
low baseband frequencies. The measurements were performed
at 28 GHz, −25 dBm input power, VCM = 1.15 V, Register 0x03,
Bit 11 = 1, Register 0x03, Bit 8 = 0, 6 dBm LO input power, and
TA = 25°C.
350
300
250
200
IMAGE REJECT
0
1
10
100
1k
10k
100k
1M
10M
100M
BASEBAND FREQUENCY (Hz)
Figure 110. Image Rejection vs. Baseband Frequency
Q DIFFERENTIAL
I DIFFERENTIAL
150
350
100
50
0
300
250
200
150
100
50
1
10
100
1k
10k
100k
1M
10M
100M
BASEBAND FREQUENCY (Hz)
Q DIFFERENTIAL
I DIFFERENTIAL
Figure 107. I and Q Differential Peak-to-Peak Voltage vs. Baseband Frequency
20
18
16
14
12
10
0
1
10
100
1k
10k
100k
1M
10M
100M
BASEBAND FREQUENCY (Hz)
Figure 111. DC Offset Error vs. Baseband Frequency
8
Q GAIN
I GAIN
PERFORMANCE AT DIFFERENT QUAD FILTER
SETTINGS
7
6
5
0
Figure 112 shows the conversion gain vs. RF frequency in IF
mode at 25°C and LO input power = 6 dBm, for different
QUAD_FILTERS settings. Figure 113 shows the LO to IF_I and
1
10
100
1k
10k
100k
1M
10M
100M
LO to IF_Q leakage vs. LO frequency at different quad filter
BASEBAND FREQUENCY (Hz)
settings.
Figure 108. Conversion Gain vs. Baseband Frequency
25
20
15
10
5
5
4
3
2
1
0
AMPLITUDE IMBALANCE
PHASE IMBALANCE
0
–5
–10
QUAD_FILTERS = 0
QUAD_FILTERS = 5
QUAD_FILTERS = 10
QUAD_FILTERS = 15
–15
–20
–25
–30
23
25
27
29
31
33
35
37
39
41
43
45
1
10
100
1k
10k
100k
1M
10M
100M
RF FREQUENCY (GHz)
BASEBAND FREQUENCY (Hz)
Figure 112. Conversion Gain vs. RF Frequency for Four Different
QUAD_FILTERS Settings, fIF = 3.5 GHz (Upper Sideband)
Figure 109. Amplitude Imbalance and Phase Imbalance vs. Baseband Frequency
Rev. A | Page 32 of 42
Data Sheet
ADMV1014
–40
PERFORMANCE BETWEEN DIFFERENTIAL vs.
SINGLE-ENDED LO INPUT
IF I: QUAD_FILTERS = 0
IF I: QUAD_FILTERS = 5
IF I: QUAD_FILTERS = 10
IF I: QUAD_FILTERS = 15
–45
–50
–55
–60
–65
–70
–75
–80
Figure 115 to Figure 117 show the conversion gain, input IP3
and image rejection performance for operating the ADMV1014
LO input as differential vs. SE. The measurements were
performed with 0 dBm LO input power, IF mode, with an IF
frequency of 3.5 GHz, upper sideband, and TA = 25°C.
25
IF Q: QUAD_FILTERS = 0
IF Q: QUAD_FILTERS = 5
IF Q: QUAD_FILTERS = 10
IF Q: QUAD_FILTERS = 15
20
15
10
4
5
6
7
8
9
10
11
12
LO FREQUENCY (GHz)
Figure 113. LO To IF Leakage vs. RF Frequency for Four Different
QUAD_FILTERS Settings, fIF = 3.5 GHz (Upper Sideband)
LO DIFF
VVA TEMPERATURE COMPENSATION
LO SE P SIDE
5
0
LO SE N SIDE
Figure 114 shows the conversion gain vs. RF frequency at two
different Register 0x0B settings and three different temperatures
for IF mode. The recommended value suggested in the Start-Up
Sequence section provides the highest conversion gain. If the
priority is to decrease the conversion gain variation across
temperature, Register 0x0B can be set to 0x726C. However, at
this value, the conversion gain is lower at each temperature.
25
23
25
27
29
31
33
35
37
39
41
43
45
RF FREQUENCY (GHz)
Figure 115. Conversion Gain vs. RF Frequency for Three Different LO Mode
Settings, fIF = 3.5 GHz (Upper Sideband)
10
8
6
20
15
10
5
4
2
0
–2
–4
LO DIFF
+85°C AT REG 0x0B = 0x727C
+25°C AT REG 0x0B = 0x727C
LO SE P SIDE
0
–6
–8
LO SE N SIDE
–40°C AT REG 0x0B = 0x727C
+85°C AT REG 0x0B = 0x726C
+25°C AT REG 0x0B = 0x726C
–40°C AT REG 0x0B = 0x726C
–5
–10
23
25
27
29
31
33
35
37
39
41
43
45
–10
23
RF FREQUENCY (GHz)
25
27
29
31
33
35
37
39
41
43
45
RF FREQUENCY (GHz)
Figure 116. Input IP3 vs. RF Frequency for Three Different LO Mode Settings,
RF Amplitude = −30 dBm per Tone at 20 MHz Spacing, fIF = 3.5 GHz
(Upper Sideband)
Figure 114. Conversion Gain vs. RF Frequency at Maximum Gain for Various
Register 0x0B Settings and Various Temperatures
Rev. A | Page 33 of 42
ADMV1014
Data Sheet
40
35
30
25
20
15
10
30
20
10
0
–10
–20
–30
–40
–50
–60
–70
0.8GHz LOWER SIDEBAND
1.0GHz LOWER SIDEBAND
2.0GHz LOWER SIDEBAND
3.0GHz LOWER SIDEBAND
4.0GHz LOWER SIDEBAND
5.0GHz LOWER SIDEBAND
6.0GHz LOWER SIDEBAND
LO DIFF
LO SE P SIDE
LO SE N SIDE
5
0
24
26
28
30
32
34
36
38
40
42
44
23
25
27
29
31
33
35
37
39
41
43
45
RF INPUT FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 117. Image Rejection vs. RF Input Frequency for Three Different LO
Mode Settings, RF Amplitude = −30 dBm per Tone at 20 MHz Spacing,
Figure 119. Conversion Gain vs. RF Frequency at Multiple IF Frequency
Settings (Lower Sideband)
f
IF = 3.5 GHz (Upper Sideband)
25
20
15
10
5
PERFORMANCE ACROSS RF FREQUENCY AT FIXED
IF AND BASEBAND FREQUENCIES
The ADMV1014 quadrupler operates from 21.6 GHz to
41 GHz. When using high-side LO injection, the conversion
gain starts rolling off gradually after the quadrupler frequency
reaches 41 GHz. When using low-side LO, the conversion gain
starts rolling off when the quadrupler frequency is 21.6 GHz.
0
–5
–10
–15
–20
–25
–30
0.8GHz UPPER SIDEBAND
1.0GHz UPPER SIDEBAND
2.0GHz UPPER SIDEBAND
3.0GHz UPPER SIDEBAND
4.0GHz UPPER SIDEBAND
5.0GHz UPPER SIDEBAND
6.0GHz UPPER SIDEBAND
Figure 118 and Figure 119 show the conversion gain vs. RF
frequency in IF mode for fixed IF frequencies (TA = 25°C, LO =
6 dBm) for upper sideband and lower sideband, respectively.
Figure 120 and Figure 121 show the conversion gain vs. RF
23
25
27
29
31
33
35
37
39
41
43
45
frequency in IQ mode for fixed BB frequencies (TA = 25°C, LO =
RF FREQUENCY (GHz)
6 dBm) for upper sideband and lower sideband, respectively.
Figure 120. Conversion Gain vs. RF Frequency at Multiple I/Q Frequency
Settings (Upper Sideband)
25
20
15
10
5
30
20
10
0
0
–5
–10
–20
0.8GHz UPPER SIDEBAND
–10
–15
–20
–25
–30
1.0GHz UPPER SIDEBAND
2.0GHz UPPER SIDEBAND
3.0GHz UPPER SIDEBAND
4.0GHz UPPER SIDEBAND
5.0GHz UPPER SIDEBAND
6.0GHz UPPER SIDEBAND
–30
–40
–50
–60
0.8GHz LOWER SIDEBAND
1.0GHz LOWER SIDEBAND
2.0GHz LOWER SIDEBAND
3.0GHz LOWER SIDEBAND
4.0GHz LOWER SIDEBAND
5.0GHz LOWER SIDEBAND
6.0GHz LOWER SIDEBAND
23
25
27
29
31
33
35
37
39
41
43
45
RF FREQUENCY (GHz)
23
25
27
29
31
33
35
37
39
41
43
45
Figure 118. Conversion Gain vs. RF Frequency for Multiple IF Frequency
Settings (Upper Sideband)
RF FREQUENCY (GHz)
Figure 121. Conversion Gain vs. RF Frequency at Multiple IQ Frequency
Settings (Lower Sideband)
Rev. A | Page 34 of 42
Data Sheet
ADMV1014
RECOMMENDED LAND PATTERN
EVALUATION BOARD INFORMATION
Solder the exposed pad on the underside of the ADMV1014 to a
low thermal and electrical impedance ground plane. This pad is
typically soldered to an exposed opening in the solder mask on
the evaluation board. Connect these ground vias to all other
ground layers on the evaluation board to maximize heat
dissipation from the device package.
For more information about the ADMV1014 evaluation board,
refer to the ADMV1014-EVALZ user guide.
Figure 122. Evaluation Board Layout for the LGA package
Rev. A | Page 35 of 42
ADMV1014
Data Sheet
REGISTER SUMMARY
Table 8. Register Summary
Bit 15
Bit 14
Bit 6
Bit 13
Bit 5
Bit 12
Bit 4
Bit 11
Bit 3
Bit 10
Bit 2
Bit 9
Bit 1
Bit 8
Bit 0
Reg.
Name
Bits
Bit 7
Reset
R/W
0x00
SPI_CONTROL
[15:8]
PARITY_EN
SPI_SOFT_
RESET
RESERVED
CHIP_ID[7:4]
0x0093
R/W
[7:0]
CHIP_ID[3:0]
REVISION
RESERVED
0x01
0x02
ALARM
[15:8]
PARITY_
ERROR
TOO_FEW_ TOO_MANY_ ADDRESS
0x0000
0xFFFF
R
ERRORS
TOO_
ERRORS
_RANGE_
ERROR
[7:0]
RESERVED
ALARM_MASKS [15:8]
PARITY_
TOO_MANY_ ADDRESS
RESERVED
R/W
ERROR_MASK FEW_
ERRORS_
ERRORS_
MASK
_RANGE_
ERROR_
MASK
MASK
[7:0]
RESERVED
0x03
ENABLE
QUAD
[15:8]
[7:0]
RESERVED
IBIAS_PD
P1DB_COMPENSATION IF_AMP_
PD
RESERVED QUAD_
BG_PD
BB_AMP_
PD
0x0157
R/W
QUAD_IBIAS_ DET_EN
PD
BG_PD
RESERVED
0x04
0x05
[15:8]
[7:0]
RESERVED
QUAD_SE_MODE[3:2]
QUAD_FILTERS
0x5700
0x4101
R/W
R/W
QUAD_SE_MODE[1:0]
RESERVED
LO_AMP_
PHASE_
ADJUST1
[15:8]
LOAMP_PH_ADJ_I_FINE
LOAMP_
PH_ADJ_
Q_FINE[6]
[7:0]
LOAMP_PH_ADJ_Q_FINE[5:0]
MIXER_VGATE
RESERVED
0x07
0x08
0x09
MIXER
[15:8]
[7:0]
RESERVED 0xD808
R/W
R/W
R/W
RESERVED
DET_PROG
IF_AMP
[15:8]
[7:0]
RESERVED
IF_AMP_COARSE_GAIN_I
IF_AMP_FINE_GAIN_I
0x0000
IF_AMP_FINE_GAIN_Q
IF_AMP_BB_
AMP
[15:8]
IF_AMP_COARSE_GAIN_Q
RESERVED
BB_AMP_OFFSET_I
BB_AMP_GAIN_CTRL
BB_AMP_OFFSET_Q[4:3] 0x0000
[7:0]
BB_AMP_OFFSET_Q[2:0]
0x0A BB_AMP__AGC [15:8]
[7:0]
RESERVED
BB_AMP_REF_GEN
0x2390
R/W
RESERVED
BB_
SWITCH_
HIGH_
LOW_
COMMON_
MODE
0x0B
VVA_TEMP_
COMP
[15:8]
[7:0]
VVA_TEMPERATURE_COMPENSATION[15:8]
VVA_TEMPERATURE_COMPENSATION[7:0]
0x4A5C
R/W
Rev. A | Page 36 of 42
Data Sheet
ADMV1014
REGISTER DETAILS
Address: 0x00, Reset: 0x0093, Name: SPI_CONTROL
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
1
[15] PARITY_EN (R/W)
[3:0] REVISION (R)
Enable the Parity for Write Execution
Revision ID
[14] SPI_SOFT_RESET (R/W)
[11:4] CHIP_ID (R)
SPI Soft Reset
Chip ID
[13:12] RESERVED
Table 9. Bit Descriptions for SPI_CONTROL
Bits
Bit Name
Settings
Description
Reset
Access
15
14
[13:12]
[11:4]
[3:0]
PARITY_EN
SPI_SOFT_RESET
RESERVED
CHIP_ID
Enable the Parity for Write Execution
SPI Soft Reset
Reserved
0x0
0x0
0x0
0x9
0x3
R/W
R/W
R
Chip ID
Revision ID
R
R
REVISION
Address: 0x01, Reset: 0x0000, Name: ALARM
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
[15] PARITY_ERROR (R)
[11:0] RESERVED
Parity Error
[12] ADDRESS_RANGE_ERROR (R)
[14] TOO_FEW_ERRORS (R)
Address Range Error
Too Few Errors
[13] TOO_MANY_ERRORS (R)
Too_Many_Errors
Table 10. Bit Descriptions for ALARM
Bits
Bit Name
Settings Description
Reset
Access
15
PARITY_ERROR
Parity Error
0x0
0x0
0x0
0x0
0x0
R
R
R
R
R
14
13
12
TOO_FEW_ERRORS
TOO_MANY_ERRORS
ADDRESS_RANGE_ERROR
Too Few Errors
Too Many Errors
Address Range Error
Reserved
[11:0] RESERVED
Address: 0x02, Reset: 0xFFFF, Name: ALARM_MASKS
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
[15] PARITY_ERROR_MASK (R/W)
[11:0] RESERVED
Parity Error Mask
[12] ADDRESS_RANGE_ERROR_MASK (R/W)
[14] TOO_FEW_ERRORS_MASK (R/W)
Address Range Error Mask
Too Few Errors Mask
[13] TOO_MANY_ERRORS_MASK (R/W)
Too Many Errors Mask
Table 11. Bit Descriptions for ALARM_MASKS
Bits
15
14
13
Bit Name
Settings Description
Reset
0x1
0x1
0x1
0x1
Access
R/W
R/W
R/W
R/W
R
PARITY_ERROR_MASK
TOO_FEW_ERRORS_MASK
TOO_MANY_ERRORS_MASK
ADDRESS_RANGE_ERROR_MASK
Parity Error Mask
Too Few Errors Mask
Too Many Errors Mask
Address Range Error Mask
Reserved
12
[11:0] RESERVED
0xFFF
Rev. A | Page 37 of 42
ADMV1014
Data Sheet
Address: 0x03, Reset: 0x0157, Name: ENABLE
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
1
[15] RESERVED
[4:0] RESERVED
[14] IBIAS_PD (R/W)
[5] BG_PD (R/W)
Power Down the RX Ibias
Power Down the RX BG
[13:12] P1DB_COMPENSATION (R/W)
[6] DET_EN (R/W)
Turn on bits to optimize P1dB
Digital RX Detector Enable
[11] IF_AMP_PD (R/W)
Power Down the IF Amp
[7] QUAD_IBIAS_PD (R/W)
Power Down the Quadrupler Bias
Current.
[10] RESERVED
[8] BB_AMP_PD (R/W)
Power Down the Base-Band Amp
[9] QUAD_BG_PD (R/W)
Power Down the Quadrupler BandGap
Table 12. Bit Descriptions for ENABLE
Bits
15
Bit Name
RESERVED
IBIAS_PD
Settings Description
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x1
0x0
0x1
0x0
0x1
Access
R
Reserved
14
Power Down the Rx IBIAS
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R
[13:12] P1DB_COMPENSATION
Turn on bits to optimize P1dB
Power Down the IF Amp
Reserved
Power Down the Quadrupler Band Gap
Power Down the Baseband Amp
Power Down the Quadrupler Bias Current
Digital Rx Detector Enable
Power Down the Rx BG
11
10
9
8
7
IF_AMP_PD
RESERVED
QUAD_BG_PD
BB_AMP_PD
QUAD_IBIAS_PD
DET_EN
6
5
[4:0]
BG_PD
RESERVED
Reserved
Address: 0x04, Reset: 0x5700, Name: QUAD
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
1
0
1
0
1
1
1
0
0
0
0
0
0
0
0
[15:10] RESERVED
[3:0] QUAD_FILTERS (R/W)
LO Filters BW Selection
[9:6] QUAD_SE_MODE (R/W)
Switch Differential/SE Modes
0110: SE_Mode_N_Side.
1001: SE_Mode_P_Side.
1100: Differential Mode.
0000: LO Frequency BW: 8.625 to 10.25GHz.
0101: LO Frequency BW: 6.6 to 9.2GHz.
1010: LO Frequency BW: 5.4 to 8GHz.
1111: LO Frequency BW: 5.4 to 7GHz.
[5:4] RESERVED
Table 13. Bit Descriptions for QUAD
Bits Bit Name Settings
[15:10] RESERVED
Description
Reserved
Reset
0x15
0xC
Access
R
R/W
[9:6]
QUAD_SE_MODE
Switch Differential/SE Modes
0110 SE Mode N Side
1001 SE Mode P Side
1100 Differential Mode
Reserved.
[5:4]
[3:0]
RESERVED
QUAD_FILTERS
0x0
0x0
R
R/W
LO Filters BW Selection
0000 LO Frequency BW: 8.625 GHz to 10.25 GHz
0101 LO Frequency BW: 6.6 GHz to 9.2 GHz
1010 LO Frequency BW: 5.4 GHz to 8 GHz
1111 LO Frequency BW: 5.4 GHz to 7 GHz
Rev. A | Page 38 of 42
Data Sheet
ADMV1014
Address: 0x05, Reset: 0x4101, Name: LO_AMP_PHASE_ADJUST1
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
[15:9] LOAMP_PH_ADJ_I_FINE (R/W)
Mixer Image Rejection Calibration
0x00:Maximum Phase, 0x7F: Minimum
Phase
[1:0] RESERVED
[8:2] LOAMP_PH_ADJ_Q_FINE (R/W)
Mixer Image Rejection Calibration
0x00:Maximum Phase, 0x7F: Minimum
Phase
Table 14. Bit Descriptions for LO_AMP_PHASE_ADJUST1
Bits Bit Name Settings Description
[15:9] LOAMP_PH_ADJ_I_FINE
Reset
0x20
Access
R/W
Mixer Image Rejection Calibration 0x00: Maximum Phase, 0x7F:
Minimum Phase
[8:2]
[1:0]
LOAMP_PH_ADJ_Q_FINE
RESERVED
Mixer Image Rejection Calibration 0x0: Maximum Phase, 0x7F:
Minimum Phase
Reserved.
0x40
0x1
R/W
R
Address: 0x07, Reset: 0xD808, Name: MIXER
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
1
1
0
1
1
0
0
0
0
0
0
0
1
0
0
0
[15:9] MIXER_VGATE (R/W)
[6:0] DET_PROG (R/W)
Control BB Common Mode Voltage
(Please see the application section
for more Information)
Digital RX Detector Program
0: From -12 to +4dBm.
1: From -13 to +3dBm.
10: From -14 to +2dBm.
[8:7] RESERVED
100: From -15 to +1dBm.
1000: From -15.5 to +0.5dBm.
10000: From -16.25 to -0.25dBm.
100000: From -17 to -1dBm.
1000000: From -18 to -2dBm.
Table 15. Bit Descriptions for MIXER
Bits Bit Name Settings Description
[15:9] MIXER_VGATE
Reset
0x6C
Access
R/W
Control BB Common Mode Voltage. See the Applications Information section for
more information)
[8:7]
[6:0]
RESERVED
DET_PROG
Reserved.
0x0
0x8
R
R/W
Digital Rx Detector Program.
From −12 dBm to +4 dBm.
From −13 dBm to +3 dBm.
0
1
10 From −14 dBm to +2 dBm.
100 From −15 dBm to +1 dBm.
1000 From −15.5 dBm to +0.5 dBm.
10000 From −16.25 dBm to −0.25 dBm.
100000 From −17 dBm to −1 dBm.
1000000 From −18 dBm to −2 dBm.
Rev. A | Page 39 of 42
ADMV1014
Data Sheet
Address: 0x08, Reset: 0x0000, Name: IF_AMP
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
[15:12] RESERVED
[3:0] IF_AMP_FINE_GAIN_I (R/W)
IF Amp I, 10 Fine Steps from 0x0 to
0xA (Total attenuation ~1dB). Refer
to Figure 80 to Figure 82.
[11:8] IF_AMP_COARSE_GAIN_I (R/W)
Digital IF Amp 1dB Step Gain_I
0: Refer to Figure 77 to Figure 79.
1: Refer to Figure 77 to Figure 79.
11: Refer to Figure 77 to Figure 79.
111: Refer to Figure 77 to Figure 79.
1111: Refer to Figure 77 to Figure 79.
[7:4] IF_AMP_FINE_GAIN_Q (R/W)
IF Amp Q, 10 Fine Steps from 0x0
to 0xA (Total attenuation ~1dB). Refer
to Figure 80 to Figure 82.
Table 16. Bit Descriptions for IF_AMP
Bits
Bit Name
Settings Description
Reset Access
[15:12] RESERVED
Reserved.
Digital IF Amp Step Gain I.
0x0
0x0
R
R/W
[11:8]
IF_AMP_COARSE_GAIN_I
0
1
Refer to Figure 77 to Figure 79.
Refer to Figure 77 to Figure 79.
11 Refer to Figure 77 to Figure 79.
111 Refer to Figure 77 to Figure 79.
1111 Refer to Figure 77 to Figure 79.
[7:4]
[3:0]
IF_AMP_FINE_GAIN_Q
IF_AMP_FINE_GAIN_I
IF Amp Q, 10 Fine Steps from 0x0 to 0xA. Refer to Figure 80 to Figure 82.
IF Amp I, 10 Fine Steps from 0x0 to 0xA. Refer to Figure 80 to Figure 82.
0x0
0x0
R/W
R/W
Address: 0x9, Reset: 0x0000, Name: IF_AMP__BB_AMP
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
[15:12] IF_AMP_COARSE_GAIN_Q (R/W)
Digital IF Amp 1dB Step Gain_Q
[4:0] BB_AMP_OFFSET_I (R/W)
BB Amp I. Bit 4: Use as Sign Bit, b’1
is for positive values and b’0 is for
negative values; Bits [3:0] Minimum
Offset, 0xF: Maximum Offset.
0: Refer to Figure 77 to Figure 79.
1: Refer to Figure 77 to Figure 79.
11: Refer to Figure 77 to Figure 79.
111: Refer to Figure 77 to Figure 79.
1111: Refer to Figure 77 to Figure 79.
[9:5] BB_AMP_OFFSET_Q (R/W)
BB Amp Q. Bit 9: Use as Sign Bit,
b’1is for positive values and b’0 is
for negative values; Bit [8:5] Minimum
Offset, 0xF: Maximum Offset.
[11:10] RESERVED
Table 17. Bit Descriptions for IF_AMP__BB_AMP
Bits Bit Name Settings Description
[15:12] IF_AMP_COARSE_GAIN_Q
Reset Access
Digital IF Amp 1 dB Step Gain Q
Refer to Figure 77 to Figure 79
Refer to Figure 77 to Figure 79
0x0
R/W
0
1
11 Refer to Figure 77 to Figure 79
111 Refer to Figure 77 to Figure 79
1111 Refer to Figure 77 to Figure 79
Reserved.
[11:10] RESERVED
0x0
0x0
R
R/W
[9:5]
BB_AMP_OFFSET_Q
BB Amp Q (Bit 9: Use as Sign Bit, 1 is for positive values and 0 is for
negative values; Bits[8:5]: Minimum Offset, 0xF: Maximum Offset)
[4:0]
BB_AMP_OFFSET_I
BB Amp I (Bit 4: Use as Sign Bit, 1 is for positive values and 0 is for
negative values; Bits[3:0]: Minimum Offset, 0xF: Maximum Offset)
0x0
R/W
Rev. A | Page 40 of 42
Data Sheet
ADMV1014
Address: 0x0A, Reset: 0x2390, Name: BB_AMP_AGC
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
1
0
0
0
1
1
1
0
0
1
0
0
0
0
[15:7] RESERVED
[6:3] BB_AMP_REF_GEN (R/W)
Control BB Common Mode Voltage
See the Baseband Quadrature Demodulation
(I/Q Mode) section for more information.
[0] BB_SWITCH_HIGH_LOW_COMMON_MODE (R/W)
Setting between High and Low Output
Common Mode Voltage; Should Be
Set to Opposite from RegA<bit6>
[2:1] BB_AMP_GAIN_CTRL (R/W)
See Figure 44 to Figure 46.
Table 18. Bit Descriptions for BB_AMP_AGC
Bits
Bit Name
Settings Description
Reset Access
[15:7] RESERVED
Reserved.
0x4
0x2
R
R/W
[6:3]
BB_AMP_REF_GEN
Control BB Common-Mode Voltage. See the
Baseband Quadrature Demodulation (I/Q Mode)
section for more information.
[2:1]
0
BB_AMP_GAIN_CTRL
BB_SWITCH_HIGH_LOW_COMMON_MODE
See Figure 44 to Figure 46.
0x0
0x0
R/W
R/W
Setting between High and Low Output Common-
Mode Voltage. This bit must be set to opposite from
Register 0x0A, Bit 6. See the Baseband Quadrature
Demodulation (I/Q Mode) section for more
information.
Address: 0x0B, Reset: 0x4A5C, Name: VVA_TEMP_COMP
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
1
0
0
1
0
1
0
0
1
0
1
1
1
0
0
[15:0] VVA_TEMPPERATURE_COMPENSATION (R/W)
VVA Temperature Compensation
Table 19. Bit Descriptions for VVA_TEMP_COMP
Bits
Bit Name
Settings Description
Reset
Access
[15:0] VVA_TEMPERATURE_COMPENSATION
VVA Temperature Compensation. Set to 0x727C. See the
Start-Up Sequence section and the VVA Temperature
Compensation section for more information. Disable
PARITY_EN when updating the VVA temperature
compensation.
0x4A5C R/W
Rev. A | Page 41 of 42
ADMV1014
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00
4.90
0.32
0.27
0.22
0.81 BSC
SQ
0.40
0.35
0.30
PIN 1
CORNER AREA
PIN 1
INDICATOR
32
25
24
1
3.50 REF
SQ
3.57 BSC
SQ
0.50
BSC
17
8
16
9
0.75
BSC
BOTTOM VIEW
3.77 BSC
TOP VIEW
SIDE VIEW
0.165
BSC
0.52
0.45
0.38
0.275
REF
0.75 MAX
0.67 NOM
FOR PROPER CONNECTION OF
THE EXPOSED PADS, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.25
0.22
0.19
SEATING
PLANE
SECTION OF THIS DATA SHEET.
Figure 123. 32-Terminal Land Grid Array [LGA]
(CC-32-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
CC-32-6
CC-32-6
ADMV1014ACCZ
ADMV1014ACCZ-R7
ADMV1014-EVALZ
−40°C to +85°C
−40°C to +85°C
32-Terminal Land Grid Array Package [LGA]
32-Terminal Land Grid Array Package [LGA]
Evaluation Board
1 Z = RoHS-Compliant Part.
©2018–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D17172-0-4/19(A)
Rev. A | Page 42 of 42
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