ADN2812ACP-RL7 [ADI]
Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp; 连续速率12.3 Mb / s至2.7 Gb / s的时钟和数据恢复IC，集成限幅放大器
| 型号： | ADN2812ACP-RL7 |
| 厂家： | 
ADI |
| 描述： | Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| 文件： | 总28页 (文件大小：272K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and
Data Recovery IC with Integrated Limiting Amp
ADN2812
FEATURES
PRODUCT DESCRIPTION
Serial data input: 12.3 Mb/s to 2.7 Gb/s
Exceeds SONET requirements for jitter transfer/
generation/tolerance
Quantizer sensitivity: 6 mV typical
Adjustable slice level: 100 mV
Patented clock recovery architecture
Loss of signal (LOS) detect range: 3 mV to 15 mV
Independent slice level adjust and LOS detector
No reference clock required
The ADN2812 provides the receiver functions of quantization,
signal level detect, and clock and data recovery for continuous
data rates from 12.3 Mb/s to 2.7 Gb/s. The ADN2812 automati-
cally locks to all data rates without the need for an external
reference clock or programming. All SONET jitter requirements
are met, including jitter transfer, jitter generation, and jitter
tolerance. All specifications are quoted for −40°C to +85°C
ambient temperature, unless otherwise noted.
This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, low power fiber
optic receiver.
Loss of lock indicator
I2C™ interface to access optional features
Single-supply operation: 3.3 V
Low power: 750 mW typical
The receiver front end loss of signal (LOS) detector circuit
indicates when the input signal level has fallen below a user-
adjustable threshold. The LOS detect circuit has hysteresis to
prevent chatter at the output.
5 mm × 5 mm 32-lead LFCSP
APPLICATIONS
SONET OC-1/3/12/48 and all associated FEC rates
Fibre Channel, 2× Fibre Channel , GbE, HDTV, etc.
WDM transponders
The ADN2812 is available in a compact 5 mm × 5 mm 32-lead
chip scale package.
Regenerators/repeaters
Test equipment
Broadband cross-connects and routers
FUNCTIONAL BLOCK DIAGRAM
REFCLKP/N
(OPTIONAL)
LOL
CF1
CF2 VCC
VEE
2
LOOP
FILTER
FREQUENCY
DETECT
SLICEP/N
PIN
PHASE
SHIFTER
PHASE
DETECT
LOOP
FILTER
QUANTIZER
VCO
NIN
VREF
LOS
DETECT
DATA
RE-TIMING
2
2
THRADJ
LOS
DATAOUTP/N
CLKOUTP/N
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
ADN2812
TABLE OF CONTENTS
Specifications..................................................................................... 3
Jitter Specifications....................................................................... 4
Output and Timing Specifications............................................. 5
Absolute Maximum Ratings............................................................ 6
Thermal Characteristics .............................................................. 6
ESD Caution.................................................................................. 6
Timing Characteristics..................................................................... 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
I2C Interface Timing and Internal Register Description........... 10
Terminology .................................................................................... 12
Jitter Specifications......................................................................... 13
Jitter Generation ......................................................................... 13
Jitter Transfer............................................................................... 13
Jitter Tolerance............................................................................ 13
Theory of Operation ...................................................................... 14
Functional Description.................................................................. 16
Frequency Acquisition............................................................... 16
Limiting Amplifier ..................................................................... 16
Slice Adjust.................................................................................. 16
Loss of Signal (LOS) Detector .................................................. 16
Lock Detector Operation .......................................................... 16
Harmonic Detector .................................................................... 17
Squelch Mode ............................................................................. 17
I2C Interface ............................................................................... 18
Reference Clock (Optional)...................................................... 18
Applications Information.............................................................. 21
PCB Design Guidelines ............................................................. 21
DC-Coupled Application .......................................................... 23
Coarse Data Rate Readback Look-Up Table............................... 24
Outline Dimensions....................................................................... 26
Ordering Guide .......................................................................... 26
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 28
ADN2812
SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 µF, SLICEP = SLICEN = VEE, Input Data Pattern: PRBS 223 − 1,
unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
QUANTIZER—DC CHARACTERISTICS
Input Voltage Range
Peak-to-Peak Differential Input
@ PIN or NIN, dc-coupled
PIN – NIN
DC-coupled (see Figure 28, Figure 29,
and Figure 30)
223 − 1 PRBS, ac-coupled,1 BER = 1 x 10–10 10
1.8
2.8
2.0
2.8
V
V
Input Common Mode Level
2.3
2.5
V
Differential Input Sensitivity
Input Overdrive
Input Offset
6
3
500
290
mV p-p
mV p-p
µV
(see Figure 12)
5
Input RMS Noise
BER = 1 x 10–10
µV rms
QUANTIZER—AC CHARACTERISTICS
Data Rate
S11
Input Resistance
Input Capacitance
12.3
2700
Mb/s
dB
Ω
@ 2.5 GHz
Differential
−15
100
0.65
pF
QUANTIZER—SLICE ADJUSTMENT
Gain
SLICEP – SLICEN = 0.5 V
SLICEP – SLICEN
DC level @ SLICEP or SLICEN
0.08
–0.95
VEE
0.1
1
0.12
+0.95
0.95
V/V
V
V
Differential Control Voltage Input
Control Voltage Range
Slice Threshold Offset
LOSS OF SIGNAL DETECT (LOS)
Loss of Signal Detect Range (see Figure 5)
mV
RThresh = 0 Ω
RThresh = 100 kΩ
OC-48
12
2.0
15
3.0
17
4.0
mV
mV
Hysteresis (Electrical)
RThresh = 0 Ω
RThresh = 100 kΩ
OC-1
5.6
3.7
6
6
7.2
8.4
dB
dB
RThresh = 0 Ω
RThresh = 10 kΩ
DC-coupled2
DC-coupled2
5.6
2.0
6
4
500
400
7.2
6.7
dB
dB
ns
ns
LOS Assert Time
LOS De-Assert Time
LOSS OF LOCK DETECT (LOL)
VCO Frequency Error for LOL Assert
VCO Frequency Error for LOL De-Assert
LOL Response Time
With respect to nominal
With respect to nominal
12.3 Mb/s
1000
250
4
ppm
ppm
ms
OC-12
OC-48
1.0
1.0
µs
µs
ACQUISITION TIME
Lock to Data Mode
OC-48
OC-12
OC-3
OC-1
12.3 Mb/s
1.3
2.0
3.4
9.8
40.0
10.0
ms
ms
ms
ms
ms
ms
Optional Lock to REFCLK Mode
1 PIN and NIN should be differentially driven and ac-coupled for optimum sensitivity.
2 When ac-coupled, the LOS assert and de-assert time is dominated by the RC time constant of the ac coupling capacitor and the 50 Ω input termination of the
ADN2812 input stage.
Rev. 0 | Page 3 of 28
ADN2812
Parameter
Conditions
Min
Typ
Max
Unit
DATA RATE READBACK ACCURACY
Coarse Readback
(See Table 13)
10
%
Fine Readback
In addition to REFCLK accuracy
Data rate < 20 Mb/s
Data rate > 20 Mb/s
200
100
3.6
ppm
ppm
V
POWER SUPPLY VOLTAGE
3.0
3.3
POWER SUPPLY CURRENT
219
–40
235
259
+85
mA
°C
OPERATING TEMPERATURE RANGE
JITTER SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 uF, SLICEP = SLICEN = VEE, Input Data Pattern: PRBS 223 − 1,
unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
PHASE-LOCKED LOOP CHARACTERISTICS
Jitter Transfer BW
OC-48
OC-12
490
71
670
108
kHz
kHz
OC-3
23
35
kHz
Jitter Peaking
OC-48
OC-12
OC-3
0
0
0
0.03
0.03
0.03
0.002
0.037
0.002
0.019
0.002
0.011
dB
dB
dB
UI rms
UI p-p
UI rms
UI p-p
UI rms
UI p-p
Jitter Generation
OC-48, 12 kHz to 20 MHz
0.001
0.02
0.001
0.01
0.001
0.01
OC-12, 12 kHz to 5 MHz
OC-3, 12 kHz to 1.3 MHz
Jitter Tolerance
OC-48, 223 − 1 PRBS
600 Hz
70
19
3.8
0.75
0.4
92
45
5
1
0.6
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
6 kHz
100 kHz
1 MHz
20 MHz
OC-12, 223 − 1 PRBS
30 Hz3
100
44
2.5
1.0
UI p-p
UI p-p
UI p-p
UI p-p
300 Hz1
25 kHz
250 kHz1
OC-3, 223 − 1 PRBS
30 Hz1
50
24
3.5
1.0
UI p-p
UI p-p
UI p-p
UI p-p
300 Hz1
6500 Hz
65 kHz
3 Jitter tolerance of the ADN2812 at these jitter frequencies is better than what the test equipment is able to measure.
Rev. 0 | Page 4 of 28
ADN2812
OUTPUT AND TIMING SPECIFICATIONS
Table 3.
Parameter
Conditions
Min
Typ
Max
Unit
CML OUPUT CHARACTERISTICS
(CLKOUTP/N, DATAOUTP/N)
Single-Ended Output Swing
Differential Output Swing
Output High Voltage
Output Low Voltage
CML Ouputs Timing
Rise Time
VSE (see Figure 3)
VDIFF (see Figure 3)
VOH
VOL
300
600
350
700
600
1200
VCC
mV
mV
V
VCC − 0.6
VCC − 0.35 VCC − 0.3
V
20% to 80%
80% to 20%
TS (see Figure 2), OC-48
TH (see Figure 2), OC-48
95
95
200
200
112
123
250
250
ps
ps
ps
ps
Fall Time
Setup Time
Hold Time
150
150
I2C INTERFACE DC CHARACTERISTICS
Input High Voltage
LVCMOS
VIH
0.7 VCC
V
Input Low Voltage
Input Current
VIL
0.3 VCC
+10.0
0.4
V
µA
V
VIN = 0.1 VCC or VIN = 0.9 VCC −10.0
VOL, IOL = 3.0 mA
Output Low Voltage
I2C INTERFACE TIMING
SCK Clock Frequency
SCK Pulse Width High
SCK Pulse Width Low
Start Condition Hold Time
Start Condition Setup Time
Data Setup Time
(See Figure 11)
400
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHIGH
tLOW
tHD;STA
tSU;STA
tSU;DAT
tHD;DAT
TR/TF
tSU;STO
600
1300
600
600
100
300
20 + 0.1 Cb4
600
1300
Data Hold Time
SCK/SDA Rise/Fall Time
Stop Condition Setup Time
Bus Free Time between a Stop and a Start
REFCLK CHARACTERISTICS
Input Voltage Range
300
tBUF
Optional lock to REFCLK mode
@ REFCLKP or REFCLKN
VIL
0
V
VIH
VCC
100
V
Minimum Differential Input Drive
Reference Frequency
Required Accuracy
mV p-p
MHz
ppm
12.3
2.0
200
100
LVTTL DC INPUT CHARACTERISTICS
Input High Voltage
VIH
V
Input Low Voltage
Input High Current
Input Low Current
VIL
0.8
5
V
µA
µA
IIH, VIN = 2.4 V
IIL, VIN = 0.4 V
−5
LVTTL DC OUTPUT CHARACTERISTICS
Output High Voltage
Output Low Voltage
VOH, IOH = −2.0 mA
VOL, IOL = 2.0 mA
2.4
V
V
0.4
4 Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall-times are allowed (see Table 6).
Rev. 0 | Page 5 of 28
ADN2812
ABSOLUTE MAXIMUM RATINGS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 µF,
SLICEP = SLICEN = VEE, unless otherwise noted.
Stress above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Table 4.
Parameter
Rating
Supply Voltage (VCC)
4.2 V
Minimum Input Voltage (All Inputs)
Maximum Input Voltage (All Inputs)
Maximum Junction Temperature
Storage Temperature
VEE − 0.4 V
VCC + 0.4 V
125°C
−65°C to +150°C
300°C
THERMAL CHARACTERISTICS
Thermal Resistance
Lead Temperature (Soldering 10 s)
32-LFCSP, 4-layer board with exposed paddle soldered to VEE
θJA = 28°C/W.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 6 of 28
ADN2812
TIMING CHARACTERISTICS
CLKOUTP
T
H
T
S
DATAOUTP/N
Figure 2. Output Timing
OUTP
V
V
SE
CML
OUTN
OUTP–OUTN
V
SE
V
DIFF
0V
Figure 3. Single-Ended vs. Differential Output Specifications
Rev. 0 | Page 7 of 28
ADN2812
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
TEST1 1
VCC 2
VREF 3
NIN 4
24 VCC
23 VEE
22 LOS
21 SDA
20 SCK
19 SADDR5
18 VCC
17 VEE
PIN 1
INDICATOR
ADN2812*
PIN 5
TOP VIEW
(Not to Scale)
SLICEP
SLICEN
6
7
VEE 8
* THERE IS AN EXPOSED PAD ON THE BOTTOM OF
THE PACKAGE THAT MUST BE CONNECTED TO GND.
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
TEST1
VCC
Type1
Description
1
Connect to VCC.
2
P
Power for Limamp, LOS.
3
VREF
AO
AI
AI
AI
AI
P
Internal VREF Voltage. Decouple to GND with a 0.1 µF capacitor.
Differential Data Input. CML.
Differential Data Input. CML.
Differential Slice Level Adjust Input.
Differential Slice Level Adjust Input.
GND for Limamp, LOS.
4
NIN
5
PIN
6
SLICEP
SLICEN
VEE
7
8
9
THRADJ
REFCLKP
REFCLKN
VCC
AI
DI
DI
P
LOS Threshold Setting Resistor.
Differential REFCLK Input. 12.3 MHz to 200 MHz.
Differential REFCLK Input. 12.3 MHz to 200 MHz.
VCO Power.
10
11
12
13
VEE
P
VCO GND.
14
CF2
AO
AO
DO
P
Frequency Loop Capacitor.
15
CF1
Frequency Loop Capacitor.
16
LOL
Loss of Lock Indicator. LVTTL active high.
FLL Detector GND.
17
VEE
18
VCC
P
FLL Detector Power.
19
SADDR5
SCK
DI
DI
DI
DO
P
Slave Address Bit 5.
20
I2C Clock Input.
21
SDA
I2C Data Input.
22
LOS
Loss of Signal Detect Output. Active high. LVTTL.
Output Buffer, I2C GND.
Output Buffer, I2C Power.
23
VEE
24
VCC
P
25
CLKOUTN
CLKOUTP
SQUELCH
DATAOUTN
DATAOUTP
VEE
DO
DO
DI
DO
DO
P
Differential Recovered Clock Output. CML.
Differential Recovered Clock Output. CML.
Disable Clock and Data Outputs. Active high. LVTLL.
Differential Recovered Data Output. CML.
Differential Recovered Data Output. CML.
Phase Detector, Phase Shifter GND.
Phase Detector, Phase Shifter Power.
Connect to VCC.
26
27
28
29
30
31
VCC
P
32
TEST2
Pad
Exposed Pad
P
Connect to GND
1Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output.
Rev. 0 | Page 8 of 28
ADN2812
TYPICAL PERFORMANCE CHARACTERISTICS
16
1000
100
10
ADN2812 TOLERANCE
SONET REQUIREMENT MASK
SONET OBJECTIVE MASK
EQUIPMENT LIMIT
14
12
10
8
6
1
4
2
0.1
1
10
100
1k
10k
100k
1
10
100
1k
10k
100k
1M
10M
100M
R
(Ω)
JITTER FREQUENCY (Hz)
TH
Figure 5. LOS Comparator Trip Point Programming
Figure 6. Typical Measured Jitter Tolerance OC-48
Rev. 0 | Page 9 of 28
ADN2812
I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION
R/W
SLAVE ADDRESS [6...0]
A5
CTRL.
X
1
0
0
0
0
0
MSB = 1 SET BY
PIN 19
0 = WR
1 = RD
Figure 7. Slave Address Configuration
S
SLAVE ADDR, LSB = 0 (WR) A(S) SUB ADDR A(S) DATA A(S)
DATA A(S)
P
Figure 8. I2C Write Data Transfer
S
SLAVE ADDR, LSB = 0 (WR) A(S) SUB ADDR A(S)
S
SLAVE ADDR, LSB = 1 (RD) A(S) DATA A(M)
DATA A(M) P
S = START BIT
P = STOP BIT
A(M) = LACK OF ACKNOWLEDGE BY MASTER
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
Figure 9. I2C Read Data Transfer
START BIT
STOP BIT
SLAVE ADDRESS
SUB ADDRESS
DATA
SDA
SCK
A6
A5
A7
A0
D7
D0
S
P
WR
ACK
ACK
ACK
SLADDR[4...0]
SUB ADDR[6...1]
DATA[6...1]
Figure 10. I2C Data Transfer Timing
tF
tSU;DAT
tHD;STA
tBUF
tR
SDA
SCK
tSU;STO
tR
tF
tLOW
tHIGH
tHD;STA
tSU;STA
S
S
P
S
tHD;DAT
Figure 11. I2C Port Timing Diagram
Rev. 0 | Page 10 of 28
ADN2812
Table 6. Internal Register Map1
Reg Name
FREQ0
FREQ1
FREQ2
RATE
R/W
Address
D7
MSB
MSB
0
D6
D5
D4
D3
D2
D1
D0
LSB
R
0x0
R
0x1
LSB
R
0x2
MSB
LSB
R
0x3
COARSE_RD[8] MSB
Coarse datarate readback
COARSE_RD[1]
Datarate
measure
complete
LOS
status
Static
LOL
LOL
status
COARSE_
RD[0] LSB
MISC
R
0x4
x
x
x
Measure
datarate
Lock to
reference
CTRLA
CTRLB
CTRLC
W
W
W
0x8
0x9
FREF range
Datarate/DIV_FREF ratio
Config
LOL
Reset
MISC[4]
System
reset
Reset
MISC[2]
0
0
0
0
0
Squelch
mode
0x11
0
0
0
0
0
Config LOS
1 All writeable registers default to 0x00.
Table 7. Miscellaneous Register, MISC
Datarate Measurement
Complete
Coarse Rate
Readback LSB
LOS Status
D7 D6 D5
Static LOL
D4
LOL Status
D3
D2
D1
D0
x
x
0 = No loss of signal
1 = Loss of signal
0 = Waiting for next LOL
1 = Static LOL until reset
0 = Locked
1 = Acquiring
0 = Measuring datarate
1 = Measurement complete
x
COARSE_RD[0]
Table 8. Control Register, CTRLA1
FREF Range
Datarate/Div_FREF Ratio
D5 D4 D3 D2
Measure Datarate
D1
Lock to Reference
D0
D7 D6
0
0
1
1
0
1
0
1
12.3 MHz to 25 MHz
25 MHz to 50 MHz
50 MHz to 100 MHz
100 MHz to 200 MHz
0
0
0
0
0
0
0
0
1
0
1
0
1
2
4
2n
Set to 1 to measure datarate
0 = Lock to input data
1 = Lock to reference clock
n
1
0
0
0
256
1 Where DIV_FREF is the divided down reference referred to the 12.3 MHz to 25 MHz band (see the Reference Clock (Optional) section).
Table 9. Control Register, CTRLB
Config LOL
Reset MISC[4]
System Reset
D5
Reset MISC[2]
D3
D7
D6
D4
D2
D1
D0
0 = LOL pin normal operation Write a 1 followed by Write a 1 followed by Set
0 to reset MISC[4] 0 to reset ADN2812 to 0
Write a 1 followed by Set
Set
to 0
Set
to 0
0 to reset MISC[2]
to 0
1 = LOL pin is static LOL
Table 10. Control Register, CTRLC
Config LOS
D2
Squelch Mode
D1
D7
D6
D5
D4
D3
D0
Set to 0
Set to 0
Set to 0
Set to 0
Set to 0
Set to 0
0 = Active high LOS
1 = Active low LOS
0 = Squelch CLK and DATA
1 = Squelch CLK or DATA
Rev. 0 | Page 11 of 28
ADN2812
TERMINOLOGY
10mV p-p
Input Sensitivity and Input Overdrive
VREF
SCOPE
PROBE
Sensitivity and overdrive specifications for the quantizer involve
offset voltage, gain, and noise. The relationship between the
logic output of the quantizer and the analog voltage input is
shown in Figure 12. For sufficiently large positive input voltage,
the output is always Logic 1 and, similarly for negative inputs,
the output is always Logic 0. However, the transitions between
output Logic Levels 1 and 0 are not at precisely defined input
voltage levels, but occur over a range of input voltages. Within
this range of input voltages, the output might be either 1 or 0, or
it might even fail to attain a valid logic state. The width of this
zone is determined by the input voltage noise of the quantizer.
The center of the zone is the quantizer input offset voltage.
Input overdrive is the magnitude of signal required to guarantee
the correct logic level with 1 × 10−10 confidence level.
ADN2812
PIN
+
QUANTIZER
–
50Ω 50Ω
3kΩ
VREF
2.5V
Figure 13. Single-Ended Sensitivity Measurement
Driving the ADN2812 differentially (see Figure 14), sensitivity
seems to improve from observing the quantizer input with an
oscilloscope probe. This is an illusion caused by the use of a
single-ended probe. A 5 mV p-p signal appears to drive the
ADN2812 quantizer. However, the single-ended probe measures
only half the signal. The true quantizer input signal is twice this
value, because the other quantizer input is a complementary
signal to the signal being observed.
OUTPUT
NOISE
1
0
5mV p-p
SCOPE
VREF
PROBE
OFFSET
OVERDRIVE
INPUT (V p-p)
PIN
NIN
+
SENSITIVITY
× OVERDRIVE)
(2
QUANTIZER
Figure 12. Input Sensitivity and Input Overdrive
–
Single-Ended vs. Differential
50Ω 50Ω
VREF
5mV p-p
VREF
2.5V
AC coupling is typically used to drive the inputs to the
quantizer. The inputs are internally dc biased to a common-
mode potential of ~2.5 V. Driving the ADN2812 single-ended
and observing the quantizer input with an oscilloscope probe at
the point indicated in Figure 13 shows a binary signal with an
average value equal to the common-mode potential and
instantaneous values both above and below the average value. It
is convenient to measure the peak-to-peak amplitude of this
signal and call the minimum required value the quantizer
sensitivity. Referring to Figure 13, because both positive and
negative offsets need to be accommodated, the sensitivity is
twice the overdrive. The ADN2812 quantizer typically has
6 mV p-p sensitivity.
3kΩ
Figure 14. Differential Sensitivity Measurement
LOS Response Time
LOS response time is the delay between removal of the input
signal and indication of loss of signal (LOS) at the LOS output,
Pin 22. When the inputs are dc-coupled, the LOS assert time of
the AD2812 is 500 ns typically and the de-assert time is 400 ns
typically,. In practice, the time constant produced by the ac
coupling at the quantizer input and the 50 Ω on-chip input
termination determines the LOS response time.
Rev. 0 | Page 12 of 28
ADN2812
JITTER SPECIFICATIONS
The ADN2812 CDR is designed to achieve the best bit-error-
rate (BER) performance and exceeds the jitter transfer, genera-
tion, and tolerance specifications proposed for SONET/SDH
equipment defined in the Telcordia Technologies specification.
0.1
SLOPE = –20dB/DECADE
Jitter is the dynamic displacement of digital signal edges from
their long-term average positions, measured in unit intervals
(UI), where 1 UI = 1 bit period. Jitter on the input data can
cause dynamic phase errors on the recovered clock sampling
edge. Jitter on the recovered clock causes jitter on the
retimed data.
ACCEPTABLE
RANGE
fC
JITTER FREQUENCY (kHz)
The following sections briefly summarize the specifications of
jitter generation, transfer, and tolerance in accordance with the
Telcordia document (GR-253-CORE, Issue 3, September 2000)
for the optical interface at the equipment level and the
Figure 15. Jitter Transfer Curve
JITTER TOLERANCE
ADN2812 performance with respect to those specifications.
The jitter tolerance is defined as the peak-to-peak amplitude of
the sinusoidal jitter applied on the input signal, which causes a
1 dB power penalty. This is a stress test intended to ensure that
no additional penalty is incurred under the operating
conditions (see Figure 16).
JITTER GENERATION
The jitter generation specification limits the amount of jitter
that can be generated by the device with no jitter and wander
applied at the input. For OC-48 devices, the band-pass filter
has a 12 kHz high-pass cutoff frequency with a roll-off of
20 dB/decade, and a low-pass cutoff frequency of at least
20 MHz. The jitter generated must be less than 0.01 UI rms, and
must be less than 0.1 UI p-p.
15.00
SLOPE = –20dB/DECADE
JITTER TRANSFER
1.50
0.15
The jitter transfer function is the ratio of the jitter on the output
signal to the jitter applied on the input signal versus the
frequency. This parameter measures the limited amount of the
jitter on an input signal that can be transferred to the output
signal (see Figure 15).
f0
f1
f2
f3
f4
JITTER FREQUENCY (kHz)
Figure 16. SONET Jitter Tolerance Mask
Rev. 0 | Page 13 of 28
ADN2812
THEORY OF OPERATION
The ADN2812 is a delay- and phase-locked loop circuit for
clock recovery and data retiming from an NRZ encoded data
stream. The phase of the input data signal is tracked by two
separate feedback loops, which share a common control voltage.
A high speed delay-locked loop path uses a voltage controlled
phase shifter to track the high frequency components of input
jitter. A separate phase control loop, comprised of the VCO,
tracks the low frequency components of input jitter. The initial
frequency of the VCO is set by yet a third loop, which compares
the VCO frequency with the input data frequency and sets the
coarse tuning voltage. The jitter tracking phase-locked loop
controls the VCO by the fine-tuning control.
psh
e(s)
X(s)
INPUT
DATA
d/sc
o/s
1/n
Z(s)
RECOVERED
CLOCK
d = PHASE DETECTOR GAIN
o = VCO GAIN
c = LOOP INTEGRATOR
psh = PHASE SHIFTER GAIN
n = DIVIDE RATIO
JITTER TRANSFER FUNCTION
Z(s)
X(s)
1
=
cn
do
n psh
2
s
+ s
+ 1
o
TRACKING ERROR TRANSFER FUNCTION
2
e(s)
X(s)
s
=
d psh do
2
s
+ s +
c
cn
The delay- and phase-loops together track the phase of the
input data signal. For example, when the clock lags input data,
the phase detector drives the VCO to higher frequency, and also
increases the delay through the phase shifter; both these actions
serve to reduce the phase error between the clock and data. The
faster clock picks up phase, while the delayed data loses phase.
Because the loop filter is an integrator, the static phase error is
driven to zero.
Figure 17. ADN2812 PLL/DLL Architecture
JITTER PEAKING
IN ORDINARY PLL
Another view of the circuit is that the phase shifter implements
the zero required for frequency compensation of a second-
order phase-locked loop, and this zero is placed in the feedback
path and, thus, does not appear in the closed-loop transfer
function. Jitter peaking in a conventional second-order phase-
locked loop is caused by the presence of this zero in the closed-
loop transfer function. Because this circuit has no zero in the
closed-loop transfer, jitter peaking is minimized.
ADN2812
Z(s)
X(s)
o
d psh
c
n psh
FREQUENCY (kHz)
Figure 18. ADN2812 Jitter Response vs. Conventional PLL
The delay- and phase-loops together simultaneously provide
wide-band jitter accommodation and narrow-band jitter
filtering. The linearized block diagram in Figure 17 shows that
the jitter transfer function, Z(s)/X(s), is a second-order low-pass
providing excellent filtering. Note that the jitter transfer has no
zero, unlike an ordinary second-order phase-locked loop. This
means that the main PLL loop has virtually zero jitter peaking
(see Figure 18). This makes this circuit ideal for signal regen-
erator applications, where jitter peaking in a cascade of
The delay- and phase-loops contribute to overall jitter accom-
modation. At low frequencies of input jitter on the data signal,
the integrator in the loop filter provides high gain to track large
jitter amplitudes with small phase error. In this case, the VCO is
frequency modulated and jitter is tracked as in an ordinary
phase-locked loop. The amount of low frequency jitter that can
be tracked is a function of the VCO tuning range. A wider
tuning range gives larger accommodation of low frequency
jitter. The internal loop control voltage remains small for small
phase errors, so the phase shifter remains close to the center of
its range and thus contributes little to the low frequency jitter
accommodation.
regenerators can contribute to hazardous jitter accumulation.
The error transfer, e(s)/X(s), has the same high-pass form as an
ordinary phase-locked loop. This transfer function is free to be
optimized to give excellent wide-band jitter accommodation,
because the jitter transfer function, Z(s)/X(s), provides the
narrow-band jitter filtering.
Rev. 0 | Page 14 of 28
ADN2812
cannot be tolerated. In this region, the gain of the integrator
At medium jitter frequencies, the gain and tuning range of the
VCO are not large enough to track input jitter. In this case, the
VCO control voltage becomes large and saturates, and the VCO
frequency dwells at one extreme of its tuning range or the other.
The size of the VCO tuning range, therefore, has only a small
effect on the jitter accommodation. The delay-locked loop
control voltage is now larger, and so the phase shifter takes on
the burden of tracking the input jitter. The phase shifter range,
in UI, can be seen as a broad plateau on the jitter tolerance
curve. The phase shifter has a minimum range of 2 UI at all
data rates.
determines the jitter accommodation. Because the gain of the
loop integrator declines linearly with frequency, jitter accom-
modation is lower with higher jitter frequency. At the highest
frequencies, the loop gain is very small, and little tuning of the
phase shifter can be expected. In this case, jitter accommodation
is determined by the eye opening of the input data, the static
phase error, and the residual loop jitter generation. The jitter
accommodation is roughly 0.5 UI in this region. The corner
frequency between the declining slope and the flat region is
the closed loop bandwidth of the delay-locked loop, which is
roughly 3 MHz at OC-48.
The gain of the loop integrator is small for high jitter
frequencies, so that larger phase differences are needed to make
the loop control voltage big enough to tune the range of the
phase shifter. Large phase errors at high jitter frequencies
Rev. 0 | Page 15 of 28
ADN2812
FUNCTIONAL DESCRIPTION
FREQUENCY ACQUISITION
ADN2812 drops below the programmed LOS threshold, the
output of the LOS detector, LOS Pin 22, is asserted to a Logic 1.
The LOS detector’s response time is ~500 ns by design, but is
dominated by the RC time constant in ac-coupled applications.
The LOS pin defaults to active high. However, by setting Bit
CTRLC[2] to 1, the LOS pin is configured as active low.
The ADN2812 acquires frequency from the data over a range of
data frequencies from 12.3 Mb/s to 2.7 Gb/s. The lock detector
circuit compares the frequency of the VCO and the frequency
of the incoming data. When these frequencies differ by more
than 1000 ppm, LOL is asserted. This initiates a frequency
acquisition cycle. The VCO frequency is reset to the bottom of
its range, which is 12.3 MHz. The frequency detector then
compares this VCO frequency and the incoming data frequency
and increments the VCO frequency, if necessary. Initially, the
VCO frequency is incremented in large steps to aid fast acquisi-
tion. As the VCO frequency approaches the data frequency, the
step size is reduced until the VCO frequency is within 250 ppm
of the data frequency, at which point LOL is de-asserted.
There is typically 6 dB of electrical hysteresis designed into the
LOS detector to prevent chatter on the LOS pin. This means
that, if the input level drops below the programmed LOS
threshold causing the LOS pin to assert, the LOS pin is not de-
asserted until the input level has increased to 6 dB (2×) above
the LOS threshold (see Figure 19).
LOS OUTPUT
Once LOL is de-asserted, the frequency-locked loop is turned
off. The PLL/DLL pulls in the VCO frequency the rest of the
way until the VCO frequency equals the data frequency.
INPUT LEVEL
The frequency loop requires a single external capacitor between
CF1 and CF2, Pins 14 and 15. A 0.47 µF 20ꢀ, X7R ceramic
chip capacitor with < 10 nA leakage current is recommended.
Leakage current of the capacitor can be calculated by dividing
the maximum voltage across the 0.47 µF capacitor, ~3 V, by the
insulation resistance of the capacitor. The insulation resistance
of the 0.47 uF capacitor should be greater than 300 MΩ.
HYSTERESIS
LOS THRESHOLD
t
Figure 19. LOS Detector Hysteresis
LIMITING AMPLIFIER
The LOS detector and the SLICE level adjust can be used
simultaneously on the ADN2812. This means that any offset
added to the input signal by the SLICE adjust pins does not
affect the LOS detector’s measurement of the absolute input
level.
The limiting amplifier has differential inputs (PIN/NIN), which
are internally terminated with 50 Ω to an on-chip voltage
reference (VREF = 2.5 V typically). The inputs are typically
ac-coupled externally, although dc coupling is possible as long
as the input common mode voltage remains above 2.5 V (see
Figure 28, Figure 29, and Figure 30 in the Applications
Information section). Input offset is factory trimmed to achieve
better than 6 mV typical sensitivity with minimal drift. The
limiting amplifier can be driven differentially or single-ended.
LOCK DETECTOR OPERATION
The lock detector on the ADN2812 has three modes of
operation: normal mode, REFCLK mode, and static LOL mode.
Normal Mode
SLICE ADJUST
In normal mode, the ADN2812 is a continuous rate CDR that
locks onto any data rate from 12.3 Mb/s to 2.7 Gb/s without the
use of a reference clock as an acquisition aid. In this mode, the
lock detector monitors the frequency difference between the
VCO and the input data frequency, and de-asserts the loss of
lock signal, which appears on LOL Pin 16, when the VCO is
within 250 ppm of the data frequency. This enables the D/PLL,
which pulls the VCO frequency in the remaining amount and
also acquires phase lock. Once locked, if the input frequency
error exceeds 1000 ppm (0.1ꢀ), the loss of lock signal is re-
asserted and control returns to the frequency loop, which
begins a new frequency acquisition starting at the lowest point
in the VCO operating range, 12.3 MHz. The LOL pin remains
asserted until the VCO locks onto a valid input data stream to
The quantizer slicing level can be offset by 100 mV to mitigate
the effect of amplified spontaneous emission (ASE) noise or
duty cycle distortion by applying a differential voltage input of
up to 0.95 V to SLICEP/N inputs. If no adjustment of the slice
level is needed, SLICEP/N should be tied to VEE. The gain of
the slice adjustment is ~0.1 V/V.
LOSS OF SIGNAL (LOS) DETECTOR
The receiver front end LOS detector circuit detects when the
input signal level has fallen below a user-adjustable threshold.
The threshold is set with a single external resistor from Pin 9,
THRADJ, to VEE. The LOS comparator trip point-versus-
resistor value is illustrated in Figure 5. If the input level to the
Rev. 0 | Page 16 of 28
ADN2812
within 250 ppm frequency error. This hysteresis is shown in
Figure 20.
HARMONIC DETECTOR
The ADN2812 provides a harmonic detector, which detects
whether or not the input data has changed to a lower harmonic
of the data rate that the VCO is currently locked onto. For
example, if the input data instantaneously changes from OC-48,
2.488 Gb/s, to an OC-12, 622.080 Mb/s bit stream, this could be
perceived as a valid OC-48 bit stream, because the OC-12 data
pattern is exactly 4× slower than the OC-48 pattern. So, if the
change in data rate is instantaneous, a 101 pattern at OC-12
would be perceived by the ADN2812 as a 111100001111 pattern
at OC-48. If the change to a lower harmonic is instantaneous, a
typical CDR could remain locked at the higher data rate.
LOL
1
–1000
–250
0
250
1000
f
ERROR
VCO
(ppm)
Figure 20. Transfer Function of LOL
LOL Detector Operation Using a Reference Clock
In this mode, a reference clock is used as an acquisition aid to
lock the ADN2812 VCO. Lock to reference mode is enabled by
setting CTRLA[0] to 1. The user also needs to write to the
CTRLA[7:6] and CTRLA[5:2] bits in order to set the reference
frequency range and the divide ratio of the data rate with
respect to the reference frequency. For more details, see the
Reference Clock (Optional) section. In this mode, the lock
detector monitors the difference in frequency between the
divided down VCO and the divided down reference clock. The
loss of lock signal, which appears on the LOL Pin 16, is de-
asserted when the VCO is within 250 ppm of the desired
frequency. This enables the D/PLL, which pulls the VCO
frequency in the remaining amount with respect to the input
data and also acquires phase lock. Once locked, if the input
frequency error exceeds 1000 ppm (0.1ꢀ), the loss of lock signal
is re-asserted and control returns to the frequency loop, which
re-acquires with respect to the reference clock. The LOL pin
remains asserted until the VCO frequency is within 250 ppm of
the desired frequency. This hysteresis is shown in Figure 20.
The ADN2812 implements a harmonic detector that automati-
cally identifies whether or not the input data has switched to a
lower harmonic of the data rate that the VCO is currently
locked onto. When a harmonic is identified, the LOL pin is
asserted and a new frequency acquisition is initiated. The
ADN2812 automatically locks onto the new data rate, and the
LOL pin is de-asserted.
However, the harmonic detector does not detect higher
harmonics of the data rate. If the input data rate switches to a
higher harmonic of the data rate the VCO is currently locked
onto, the VCO loses lock, the LOL pin is asserted, and a new
frequency acquisition is initiated. The ADN2812 automatically
locks onto the new data rate.
The time to detect lock to harmonic is
16,384 × (Td/ρ)
where:
1/Td is the new data rate. For example, if the data rate is
switched from OC-48 to OC-12, then Td = 1/622 MHz.
Static LOL Mode
The ADN2812 implements a static LOL feature, which indicates
if a loss of lock condition has ever occurred and remains
asserted, even if the ADN2812 regains lock, until the static LOL
bit is manually reset. The I2C register bit, MISC[4], is the static
LOL bit. If there is ever an occurrence of a loss of lock
condition, this bit is internally asserted to logic high. The
MISC[4] bit remains high even after the ADN2812 has re-
acquired lock to a new data rate. This bit can be reset by writing
a 1 followed by 0 to I2C Register Bit CTRLB[6]. Once reset, the
MISC[4] bit remains de-asserted until another loss of lock
condition occurs.
ρ is the data transition density. Most coding schemes seek to
ensure that ρ = 0.5, for example, PRBS, 8B/10B.
When the ADN2812 is placed in lock to reference mode, the
harmonic detector is disabled.
SQUELCH MODE
Two squelch modes are available with the ADN2812. Squelch
DATAOUT AND CLKOUT mode is selected when CTRLC[1] =
0 (default mode). In this mode, when the squelch input, Pin 27,
is driven to a TTL high state, both the clock and data outputs
are set to the zero state to suppress downstream processing. If
the squelch function is not required, Pin 27 should be tied to
VEE.
Writing a 1 to I2C Register Bit CTRLB[7] causes the LOL pin,
Pin 16, to become a static LOL indicator. In this mode, the LOL
pin mirrors the contents of the MISC[4] bit and has the
functionality described in the previous paragraph. The
CTRLB[7] bit defaults to 0. In this mode, the LOL pin operates
in the normal operating mode, that is, it is asserted only when
the ADN2812 is in acquisition mode and de-asserts when the
ADN2812 has re-acquired lock.
Squelch DATAOUT OR CLKOUT mode is selected when
CTRLC[1] is 1. In this mode, when the squelch input is driven
to a high state, the DATAOUT pins are squelched. When the
squelch input is driven to a low state, the CLKOUT pins are
squelched. This is especially useful in repeater applications,
where the recovered clock may not be needed.
Rev. 0 | Page 17 of 28
ADN2812
I2C INTERFACE
reading back in autoincrement mode, then the highest subad-
dress register contents continue to be output until the master
device issues a no-acknowledge. This indicates the end of a read.
In a no-acknowledge condition, the SDATA line is not pulled
low on the ninth pulse. See Figure 8 and Figure 9 for sample
read and write data transfers and Figure 10 for a more detailed
timing diagram.
The ADN2812 supports a 2-wire, I2C compatible, serial bus
driving multiple peripherals. Two inputs, serial data (SDA) and
serial clock (SCK), carry information between any devices
connected to the bus. Each slave device is recognized by a
unique address. The ADN2812 has two possible 7-bit slave
addresses for both read and write operations. The MSB of the
7-bit slave address is factory programmed to 1. B5 of the slave
address is set by Pin 19, SADDR5. Slave address bits [4:0] are
defaulted to all 0s. The slave address consists of the 7 MSBs of
an 8-bit word. The LSB of the word sets either a read or write
operation (see Figure 7). Logic 1 corresponds to a read
operation, while Logic 0 corresponds to a write operation.
REFERENCE CLOCK (OPTIONAL)
A reference clock is not required to perform clock and data
recovery with the ADN2812. However, support for an optional
reference clock is provided. The reference clock can be driven
differentially or single-ended. If the reference clock is not being
used, then REFCLKP should be tied to VCC, and REFCLKN
can be left floating or tied to VEE (the inputs are internally
terminated to VCC/2). See Figure 21 through Figure 23 for
sample configurations.
To control the device on the bus, the following protocol must be
followed. First, the master initiates a data transfer by establish-
ing a start condition, defined by a high to low transition on SDA
while SCK remains high. This indicates that an address/data
stream follows. All peripherals respond to the start condition
and shift the next eight bits (the 7-bit address and the R/W bit).
The bits are transferred from MSB to LSB. The peripheral that
recognizes the transmitted address responds by pulling the data
line low during the ninth clock pulse. This is known as an
acknowledge bit. All other devices withdraw from the bus at this
point and maintain an idle condition. The idle condition is
where the device monitors the SDA and SCK lines waiting for
the start condition and correct transmitted address. The R/W
bit determines the direction of the data. Logic 0 on the LSB of
the first byte means that the master writes information to the
peripheral. Logic 1 on the LSB of the first byte means that the
master reads information from the peripheral.
The REFCLK input buffer accepts any differential signal with a
peak-to-peak differential amplitude of greater than 100 mV (for
example, LVPECL or LVDS) or a standard single-ended low
voltage TTL input, providing maximum system flexibility. Phase
noise and duty cycle of the reference clock are not critical and
100 ppm accuracy is sufficient.
ADN2812
REFCLKP
10
BUFFER
11
REFCLKN
100kΩ 100kΩ
VCC/2
The ADN2812 acts as a standard slave device on the bus. The
data on the SDA pin is 8 bits long supporting the 7-bit addresses
plus the R/W bit. The ADN2812 has 8 subaddresses to enable
the user-accessible internal registers (see Table 1 through
Table 7). It, therefore, interprets the first byte as the device
address and the second byte as the starting subaddress.
Autoincrement mode is supported, allowing data to be read
from or written to the starting subaddress and each subsequent
address without manually addressing the subsequent
Figure 21. Differential REFCLK Configuration
VCC
ADN2812
REFCLKP
CLK
OSC
OUT
BUFFER
REFCLKN
100kΩ 100kΩ
VCC/2
subaddress. A data transfer is always terminated by a stop
condition. The user can also access any unique subaddress
register on a one-by-one basis without updating all registers.
Figure 22. Single-Ended REFCLK Configuration
VCC
ADN2812
Stop and start conditions can be detected at any stage of the
data transfer. If these conditions are asserted out of sequence
with normal read and write operations, then they cause an
immediate jump to the idle condition. During a given SCK high
period, the user should issue one start condition, one stop
condition, or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADN2812 does not issue an acknowledge and returns to the idle
condition. If the user exceeds the highest subaddress while
10
REFCLKP
BUFFER
11
NC
REFCLKN
100kΩ 100kΩ
VCC/2
Figure 23. No REFCLK Configuration
Rev. 0 | Page 18 of 28
ADN2812
The two uses of the reference clock are mutually exclusive. The
reference clock can be used either as an acquisition aid for the
ADN2812 to lock onto data, or to measure the frequency of the
incoming data to within 0.01ꢀ. (There is the capability to
measure the data rate to approximately 10% without the use of
a reference clock.) The modes are mutually exclusive, because,
in the first use, the user knows exactly what the data rate is and
wants to force the part to lock onto only that data rate; in the
second use, the user does not know what the data rate is and
wants to measure it.
In this mode, if the ADN2812 loses lock for any reason, it
relocks onto the reference clock and continues to output a stable
clock.
While the ADN2812 is operating in lock to reference mode, if
the user ever changes the reference frequency, the FREF range
(CTRLA[7:6]), or the FREF ratio (CTRLA[5:2]), this must be
followed by writing a 0 to 1 transition into the CTRLA[0] bit to
initiate a new lock to reference command.
Using the Reference Clock to Measure Data Frequency
The user can also provide a reference clock to measure the
recovered data frequency. In this case, the user provides a
reference clock, and the ADN2812 compares the frequency of
the incoming data to the incoming reference clock and returns a
ratio of the two frequencies to 0.01ꢀ (100 ppm). The accuracy
error of the reference clock is added to the accuracy of the
ADN2812 data rate measurement. For example, if a 100-ppm
accuracy reference clock is used, the total accuracy of the
measurement is within 200 ppm.
Lock to reference mode is enabled by writing a 1 to I2C Register
Bit CTRLA[0]. Fine data rate readback mode is enabled by
writing a 1 to I2C Register Bit CTRLA[1]. Writing a 1 to both of
these bits at the same time causes an indeterminate state and is
not supported.
Using the Reference Clock to Lock onto Data
In this mode, the ADN2812 locks onto a frequency derived
from the reference clock according to the following equation:
Data Rate/2CTRLA[5:2] = REFCLK/2CTRLA[7:6]
The reference clock can range from 12.3 MHz and 200 MHz.
The ADN2812 expects a reference clock between 12.3 MHz and
25 MHz by default. If it is between 25 MHz and 50 MHz,
50 MHz and 100 MHz, or 100 MHz and 200 MHz, the user
needs to configure the ADN2812 to use the correct reference
frequency range by setting two bits of the CTRLA register,
CTRLA[7:6]. Using the reference clock to determine the
frequency of the incoming data does not affect the manner in
which the part locks onto data. In this mode, the reference clock
is used only to determine the frequency of the data. For this
reason, the user does not need to know the data rate to use the
reference clock in this manner.
The user must know exactly what the data rate is, and provide a
reference clock that is a function of this rate. The ADN2812 can
still be used as a continuous rate device in this configuration,
provided that the user has the ability to provide a reference
clock that has a variable frequency (see Application Note
AN-632).
The reference clock can be anywhere between 12.3 MHz and
200 MHz. By default, the ADN2812 expects a reference clock of
between 12.3 MHz and 25 MHz. If it is between 25 MHz and
50 MHz, 50 MHz and 100 MHz, or 100 MHz and 200 MHz, the
user needs to configure the ADN2812 to use the correct
reference frequency range by setting two bits of the CTRLA
register, CTRLA[7:6].
Prior to reading back the data rate using the reference clock, the
CTRLA[7:6] bits must be set to the appropriate frequency range
with respect to the reference clock being used. A fine data rate
readback is then executed as follows:
Table 11. CTRLA Settings
CTRLA[7:6]
Range (MHz)
12.3 to 25
25 to 50
50 to 100
100 to 200
CTRLA[5:2]
0000
0001
n
1000
Ratio
1
2
2n
Step 1: Write a 1 to CTRLA[1]. This enables the fine data rate
measurement capability of the ADN2812. This bit is level
sensitive and does not need to be reset to perform subsequent
frequency measurements.
00
01
10
11
256
Step 2: Reset MISC[2] by writing a 1 followed by a 0 to
CTRLB[3]. This initiates a new data rate measurement.
The user can specify a fixed integer multiple of the reference
clock to lock onto using CTRLA[5:2], where CTRLA should be
set to the data rate/DIV_FREF, where DIV_FREF represents the
divided-down reference referred to the 12.3 MHz to 25 MHz
band. For example, if the reference clock frequency was
38.88 MHz and the input data rate was 622.08 Mb/s, then
CTRLA[7:6] would be set to [01] to give a divided-down
reference clock of 19.44 MHz. CTRLA[5:2] would be set to
[0101], that is, 5, because
Step 3: Read back MISC[2]. If it is 0, then the measurement is
not complete. If it is 1, then the measurement is complete and
the data rate can be read back on FREQ[22:0]. The time for a
data rate measurement is typically 80 ms.
Step 4: Read back the data rate from registers FREQ2[6:0],
FREQ1[7:0], and FREQ0[7:0].
622.08 Mb/s/19.44 MHz = 25
Rev. 0 | Page 19 of 28
ADN2812
Additional Features Available via the I2C Interface
Coarse Data Rate Readback
Use the following equation to determine the data rate:
fDATARATE
where:
=
(
FREQ
[22..0
]
× fREFCLK
/2(14+SEL _ RATE)
)
The data rate can be read back over the I2C interface to
approximately +10ꢀ without the need of an external reference
clock. A 9-bit register, COARSE_RD[8:0], can be read back
when LOL is de-asserted. The 8 MSBs of this register are the
contents of the RATE[7:0] register. The LSB of the
COARSE_RD register is Bit MISC[0].
FREQ[22:0] is the reading from FREQ2[6:0] (MSByte),
FREQ1[7:0], and FREQ0[7:0] (LSByte).
Table 12.
D22 D21...D17 D16 D15 D14...D9 D8 D7 D6...D1 D0
Table 13 provides coarse data rate readback to within 10ꢀ.
FREQ2[6:0]
FREQ1[7:0]
FREQ0[7:0]
LOS Configuration
f
f
DATARATE is the data rate (Mb/s).
The LOS detector output, LOS Pin 22, can be configured to be
either active high or active low. If CTRLC[2] is set to Logic 0
(default), the LOS pin is active high when a loss of signal
condition is detected. Writing a 1 to CTRLC[2] configures the
LOS pin to be active low when a loss of signal condition is
detected.
REFCLK is the REFCLK frequency (MHz).
SEL_RATE is the setting from CTRLA[7:6].
For example, if the reference clock frequency is 32 MHz,
SEL_RATE = 1, since the CTRLA[7:6] setting would be [01],
because the reference frequency would fall into the 25 MHz to
50 MHz range. Assume for this example that the input data rate
is 2.488 Gb/s (OC-48). After following Steps 1 through 4, the
value that is read back on FREQ[22:0] = 0x26E010, which is
equal to 2.5477 × 106. Plugging this value into the equation
yields
System Reset
A frequency acquisition can be initiated by writing a 1 followed
by a 0 to the I2C Register Bit CTRLB[5]. This initiates a new
frequency acquisition while keeping the ADN2812 in the
operating mode that it was previously programmed to in
registers CTRL[A], CTRL[B], and CTRL[C].
(
2.5477e6 × 32e6
)
/
2(14+1)
= 2.488Gb/s
If subsequent frequency measurements are required, CTRLA[1]
should remain set to 1. It does not need to be reset. The
measurement process is reset by writing a 1 followed by a 0 to
CTRLB[3]. This initiates a new data rate measurement. Follow
Steps 2 through 4 to read back the new data rate.
Note: A data rate readback is valid only if LOL is low. If LOL is
high, the data rate readback is invalid.
Rev. 0 | Page 20 of 28
ADN2812
APPLICATIONS INFORMATION
PCB DESIGN GUIDELINES
Proper RF PCB design techniques must be used for optimal
performance.
If connections to the supply and ground are made through vias,
the use of multiple vias in parallel helps to reduce series
inductance, especially on Pin 24, which supplies power to the
high speed CLKOUTP/CLKOUTN and DATAOUTP/
DATAOUTN output buffers. Refer to the schematic in Figure 24
for recommended connections.
Power Supply Connections and Ground Planes
Use of one low impedance ground plane is recommended. The
VEE pins should be soldered directly to the ground plane to
reduce series inductance. If the ground plane is an internal
plane and connections to the ground plane are made through
vias, multiple vias can be used in parallel to reduce the series
inductance, especially on Pin 23, which is the ground return for
the output buffers. The exposed pad should be connected to the
GND plane using plugged vias so that solder does not leak
through the vias during reflow.
By using adjacent power supply and GND planes, excellent high
frequency decoupling can be realized by using close spacing
between the planes. This capacitance is given by
Cplane = 0.88εr A/d
where:
pF)
Use of a 10 µF electrolytic capacitor between VCC and VEE is
recommended at the location where the 3.3 V supply enters the
PCB. When using 0.1 µF and 1 nF ceramic chip capacitors, they
should be placed between the IC power supply VCC and VEE,
as close as possible to the ADN2812 VCC pins.
εr is the dielectric constant of the PCB material.
A is the area of the overlap of power and GND planes (cm2).
d is the separation between planes (mm).
For FR-4, εr = 4.4 mm and 0.25 mm spacing, C ~15 pF/cm2.
VCC
50Ω
100Ω
× 4
TRANSMISSION LINES
DATAOUTP
DATAOUTN
CLKOUTP
CLKOUTN
VCC
+
0.1µF
1nF
10µF
32 31 30 29 28 27 26 25
24
VCC
TEST1
VCC
1
2
3
4
5
6
7
8
1nF
0.1µF
VCC
VREF
NIN
VEE
23
22
21
20
19
18
17
LOS
0.1µF
1nF
µC
EXPOSED PAD
TIED OFF TO
VEE PLANE
WITH VIAS
SDA
2
VCC
I C
0.1µF
PIN
SCK
CONTROLLER
SLICEP
SLICEN
VEE
SADDR5
VCC
50Ω
50Ω
C
C
IN
VEE
TIA
VCC
9
10 11 12 13 14 15 16
IN
1nF
0.1µF
µC
R
TH
0.47µF
±
20% >300MΩ
INSULATION RESISTANCE
NC
VCC
NC = NO CONNECT
0.1µF
1nF
Figure 24. Typical ADN2812 Applications Circuit
Rev. 0 | Page 21 of 28
ADN2812
Transmission Lines
circuit board should be at least as large as this exposed pad. The
user must connect the exposed pad to VEE using plugged vias
so that solder does not leak through the vias during reflow. This
ensures a solid connection from the exposed pad to VEE.
Use of 50 Ω transmission lines is required for all high frequency
input and output signals to minimize reflections: PIN, NIN,
CLKOUTP, CLKOUTN, DATAOUTP, DATAOUTN (also
REFCLKP, REFCLKN, if a high frequency reference clock is
used, such as 155 MHz). It is also necessary for the PIN/NIN
input traces to be matched in length, and the CLKOUTP/N and
DATAOUTP/N output traces to be matched in length to avoid
skew between the differential traces. All high speed CML
outputs, CLKOUTP/N and DATAOUTP/N, also require 100 Ω
back termination chip resistors connected between the output
pin and VCC. These resistors should be placed as close as
possible to the output pins. These 100 Ω resistors are in parallel
with on-chip 100 Ω termination resistors to create a 50 Ω back
termination (see Figure 25).
Choosing AC Coupling Capacitors
AC coupling capacitors at the input (PIN, NIN) and output
(DATAOUTP, DATAOUTN) of the ADN2812 must be chosen
such that the device works properly over the full range of data
rates used in the application. When choosing the capacitors, the
time constant formed with the two 50 Ω resistors in the signal
path must be considered. When a large number of consecutive
identical digits (CIDs) are applied, the capacitor voltage can
droop due to baseline wander (see Figure 27), causing pattern-
dependent jitter (PDJ).
The user must determine how much droop is tolerable and
choose an ac coupling capacitor based on that amount of droop.
The amount of PDJ can then be approximated based on the
capacitor selection. The actual capacitor value selection may
require some trade-offs between droop and PDJ.
The high speed inputs, PIN and NIN, are internally terminated
with 50 Ω to an internal reference voltage (see Figure 26).
A 0.1 µF is recommended between VREF, Pin 3, and GND to
provide an ac ground for the inputs.
As with any high speed mixed-signal design, take care to keep
all high speed digital traces away from sensitive analog nodes.
Example: Assuming that 2ꢀ droop can be tolerated, then the
maximum differential droop is 4ꢀ. Normalizing to Vpp:
V
TERM
VCC
VCC
Droop = ∆ V = 0.04 V = 0.5 Vpp (1 − e–t/τ) ; therefore, τ = 12t
50Ω
50Ω
100Ω 100Ω
100Ω 100Ω
where:
0.1µF
0.1µF
τ is the RC time constant (C is the ac coupling capacitor, R =
100 Ω seen by C).
50Ω
t is the total discharge time, which is equal to nΤ.
n is the number of CIDs.
50Ω
ADN2812
V
TERM
T is the bit period.
Figure 25. Typical ADN2812 Applications Circuit
The capacitor value can then be calculated by combining the
equations for τ and t:
VCC
ADN2812
C
50Ω
50Ω
IN
C =12nT/R
PIN
NIN
Once the capacitor value is selected, the PDJ can be
approximated as
TIA
C
IN
50Ω 50Ω
3kΩ
VREF
−nT/RC
)
PDJ pspp = 0.5tr
where:
1−e(
/ 0.6
2.5V
0.1µF
Figure 26. ADN2812 AC-Coupled Input Configuration
PDJpspp is the amount of pattern-dependent jitter allowed;
< 0.01 UI p-p typical.
Soldering Guidelines for Chip Scale Package
The lands on the 32 LFCSP are rectangular. The printed circuit
board pad for these should be 0.1 mm longer than the package
land length and 0.05 mm wider than the package land width.
The land should be centered on the pad. This ensures that the
solder joint size is maximized. The bottom of the chip scale
package has a central exposed pad. The pad on the printed
tr is the rise time, which is equal to 0.22/BW,
where BW ~ 0.7 (bit rate).
Note that this expression for tr is accurate only for the inputs.
The output rise time for the ADN2812 is ~100 ps regardless of
data rate.
Rev. 0 | Page 22 of 28
ADN2812
VCC
ADN2812
C
C
IN
V1
V2
PIN
C
C
OUT
+
DATAOUTP
DATAOUTN
50Ω
CDR
TIA
LIMAMP
V
REF
IN
V1b
V2b
50Ω
NIN
–
OUT
1
2
3
4
V1
V1b
V2
VREF
V2b
VTH
V
DIFF
V
= V2–V2b
DIFF
VTH = ADN2812 QUANTIZER THRESHOLD
NOTES:
1. DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS ZERO.
2. WHEN THE OUTPUT OF THE TIA GOES TO CID, V1 AND V1b ARE DRIVEN TO DIFFERENT DC LEVELS. V2 AND V2b DISCHARGE TO THE
VREF LEVEL, WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS.
3. WHEN THE BURST OF DATA STARTS AGAIN, THE DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS IS APPLIED TO
THE INPUT LEVELS CAUSING A DC SHIFT IN THE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCH THAT ONE OF THE STATES,
EITHER HIGH OR LOW DEPENDING ON THE LEVELS OF V1 AND V1b WHEN THE TIA WENT TO CID, IS CANCELED OUT. THE QUANTIZER
DOES NOT RECOGNIZE THIS AS A VALID STATE.
4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2812. THE
QUANTIZER CAN RECOGNIZE BOTH HIGH AND LOW STATES AT THIS POINT.
Figure 27. Example of Baseline Wander
DC-COUPLED APPLICATION
The inputs to the ADN2812 can also be dc-coupled. This might
be necessary in burst mode applications, where there are long
periods of CIDs, and baseline wander cannot be tolerated. If the
inputs to the ADN2812 are dc-coupled, care must be taken not
to violate the input range and common-mode level require-
ments of the ADN2812 (see Figure 28 through Figure 30). If dc
coupling is required, and the output levels of the TIA do not
adhere to the levels shown in Figure 29, then level shifting
and/or an attenuator must be between the TIA outputs and the
ADN2812 inputs.
PIN
NIN
V
= PIN – NIN = 2
×
V
= 10mV AT SENSITIVITY
SE
PP
V
= 5mV MIN
SE
V
= 2.3V MIN
CM
(DC-COUPLED)
Figure 29. Minimum Allowed DC-Coupled Input Levels
VCC
V
= PIN – NIN = 2
×
V
= 2.0V MAX
SE
PP
PIN
ADN2812
50Ω
50Ω
PIN
V
= 1.0V MAX
= 2.3V
SE
TIA
V
NIN
CM
(DC-COUPLED)
50Ω
50Ω
3kΩ
2.5V
NIN
0.1µF
VREF
Figure 28. DC-Coupled Application
Figure 30. Maximum Allowed DC-Coupled Input Levels
Rev. 0 | Page 23 of 28
ADN2812
COARSE DATA RATE READBACK LOOK-UP TABLE
Code is the 9-bit value read back from COARSE_RD[8:0].
Table 13. Look-Up Table
Code
FMID
Code
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
FMID
Code
FMID
Code
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
FMID
0
1
2
3
4
5
6
7
5.1934e+06
5.1930e+06
5.2930e+06
5.3989e+06
5.5124e+06
5.6325e+06
5.7612e+06
5.8995e+06
6.0473e+06
6.2097e+06
6.3819e+06
6.5675e+06
6.7688e+06
6.9874e+06
7.2262e+06
7.4863e+06
7.4139e+06
7.4135e+06
7.5606e+06
7.7173e+06
7.8852e+06
8.0633e+06
8.2548e+06
8.4586e+06
8.6784e+06
8.9180e+06
9.1736e+06
9.4481e+06
9.7464e+06
1.0068e+07
1.0417e+07
1.0791e+07
1.0387e+07
1.0386e+07
1.0586e+07
1.0798e+07
1.1025e+07
1.1265e+07
1.1522e+07
1.1799e+07
1.2095e+07
1.2419e+07
1.2764e+07
1.3135e+07
1.3538e+07
1.3975e+07
1.4452e+07
1.4973e+07
1.4828e+07
1.4827e+07
1.5121e+07
1.5435e+07
1.5770e+07
1.6127e+07
1.6510e+07
1.6917e+07
1.7357e+07
1.7836e+07
1.8347e+07
1.8896e+07
1.9493e+07
2.0136e+07
2.0833e+07
2.1582e+07
2.0774e+07
2.0772e+07
2.1172e+07
2.1596e+07
2.2049e+07
2.2530e+07
2.3045e+07
2.3598e+07
2.4189e+07
2.4839e+07
2.5527e+07
2.6270e+07
2.7075e+07
2.7950e+07
2.8905e+07
2.9945e+07
2.9655e+07
2.9654e+07
3.0242e+07
3.0869e+07
3.1541e+07
3.2253e+07
3.3019e+07
3.3834e+07
3.4714e+07
3.5672e+07
3.6694e+07
3.7792e+07
3.8985e+07
4.0273e+07
4.1666e+07
4.3164e+07
96
97
98
99
4.1547e+07
4.1544e+07
4.2344e+07
4.3191e+07
4.4099e+07
4.5060e+07
4.6090e+07
4.7196e+07
4.8378e+07
4.9678e+07
5.1055e+07
5.2540e+07
5.4150e+07
5.5899e+07
5.7810e+07
5.9890e+07
5.9311e+07
5.9308e+07
6.0485e+07
6.1739e+07
6.3081e+07
6.4506e+07
6.6038e+07
6.7669e+07
6.9427e+07
7.1344e+07
7.3388e+07
7.5585e+07
7.7971e+07
8.0546e+07
8.3333e+07
8.6328e+07
8.3095e+07
8.3087e+07
8.4689e+07
8.6383e+07
8.8198e+07
9.0120e+07
9.2179e+07
9.4392e+07
9.6757e+07
9.9356e+07
1.0211e+08
1.0508e+08
1.0830e+08
1.1180e+08
1.1562e+08
1.1978e+08
1.1862e+08
1.1862e+08
1.2097e+08
1.2348e+08
1.2616e+08
1.2901e+08
1.3208e+08
1.3534e+08
1.3885e+08
1.4269e+08
1.4678e+08
1.5117e+08
1.5594e+08
1.6109e+08
1.6667e+08
1.7266e+08
1.6619e+08
1.6617e+08
1.6938e+08
1.7277e+08
1.7640e+08
1.8024e+08
1.8436e+08
1.8878e+08
1.9351e+08
1.9871e+08
2.0422e+08
2.1016e+08
2.1660e+08
2.2360e+08
2.3124e+08
2.3956e+08
2.3724e+08
2.3723e+08
2.4194e+08
2.4695e+08
2.5233e+08
2.5802e+08
2.6415e+08
2.7067e+08
2.7771e+08
2.8538e+08
2.9355e+08
3.0234e+08
3.1188e+08
3.2218e+08
3.3333e+08
3.4531e+08
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
Rev. 0 | Page 24 of 28
ADN2812
Code
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
FMID
Code
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
FMID
Code
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
FMID
Code
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
FMID
3.3238e+08
3.3235e+08
3.3876e+08
3.4553e+08
3.5279e+08
3.6048e+08
3.6872e+08
3.7757e+08
3.8703e+08
3.9742e+08
4.0844e+08
4.2032e+08
4.3320e+08
4.4719e+08
4.6248e+08
4.7912e+08
4.7449e+08
4.7447e+08
4.8388e+08
4.9391e+08
5.0465e+08
5.1605e+08
5.2831e+08
5.4135e+08
5.5542e+08
5.7075e+08
5.8711e+08
6.0468e+08
6.2377e+08
6.4437e+08
6.6666e+08
6.9062e+08
6.6476e+08
6.6470e+08
6.7751e+08
6.9106e+08
7.0558e+08
7.2096e+08
7.3743e+08
7.5514e+08
7.7405e+08
7.9485e+08
8.1688e+08
8.4064e+08
8.6640e+08
8.9438e+08
9.2496e+08
9.5825e+08
9.4898e+08
9.4893e+08
9.6776e+08
9.8782e+08
1.0093e+09
1.0321e+09
1.0566e+09
1.0827e+09
1.1108e+09
1.1415e+09
1.1742e+09
1.2094e+09
1.2475e+09
1.2887e+09
1.3333e+09
1.3812e+09
1.3295e+09
1.3294e+09
1.3550e+09
1.3821e+09
1.4112e+09
1.4419e+09
1.4749e+09
1.5103e+09
1.5481e+09
1.5897e+09
1.6338e+09
1.6813e+09
1.7328e+09
1.7888e+09
1.8499e+09
1.9165e+09
1.8980e+09
1.8979e+09
1.9355e+09
1.9756e+09
2.0186e+09
2.0642e+09
2.1132e+09
2.1654e+09
2.2217e+09
2.2830e+09
2.3484e+09
2.4187e+09
2.4951e+09
2.5775e+09
2.6666e+09
2.7625e+09
Rev. 0 | Page 25 of 28
ADN2812
OUTLINE DIMENSIONS
5.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
25
24
32
1
PIN 1
INDICATOR
0.50
BSC
3.25
3.10 SQ
2.95
4.75
BSC SQ
TOP
BOTTOM
VIEW
VIEW
0.50
0.40
0.30
17
16
8
9
0.25 MIN
3.50 REF
0.80 MAX
12° MAX
0.65 TYP
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 31. 32-Lead Frame Chip Scale Package [LFCSP]
(CP-32)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADN2812ACP
ADN2812ACP-RL
ADN2812ACP-RL7
Temperature Range
−40°C to 85°C
−40°C to 85°C
Package Description
Package Option
32-LFCSP
32-LFCSP, tape-reel, 2500 pcs
32-LFCSP, tape-reel, 1500 pcs
CP-32
CP-32
CP-32
−40°C to 85°C
Rev. 0 | Page 26 of 28
ADN2812
NOTES
Rev. 0 | Page 27 of 28
ADN2812
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C
Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04228–0–3/04(0)
Rev. 0 | Page 28 of 28
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Continuous Rate 10 Mb/s to 675 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp
ADI
ADN2814ACPZ-500RL7
Continuous Rate 10 Mb/s to 675 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp
ADI
ADN2814ACPZ-RL7
Continuous Rate 10 Mb/s to 675 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp
ADI
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