ADN4680EBCPZ [ADI]
250 Mbps, Half-Duplex, Quad M-LVDS Transceivers;
| 型号： | ADN4680EBCPZ |
| 厂家： | 
ADI |
| 描述： | 250 Mbps, Half-Duplex, Quad M-LVDS Transceivers |
| 文件： | 总21页 (文件大小：2141K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
ADN4680E
250 Mbps, Half-Duplex, Quad M-LVDS Transceivers
FEATURES
FUNCTIONAL BLOCK DIAGRAM
► Four M-LVDS transceivers (driver and receiver pairs)
► Switching rate: 250 Mbps (125 MHz)
► Independent pin select for each receiver, two modes:
► Type 1: input hysteresis of 15 mV typical
► Type 2: differential input threshold voltage offset by 100 mV to
support open-circuit, short-circuit, and bus idle fail-safe
► Compatible with the TIA/EIA-899 standard for M-LVDS
► Glitch free power-up/power-down on the M-LVDS bus
► Controlled transition times on the driver output
► Common-mode range: −1 V to +3.4 V, allowing communication
with ±2 V of ground noise
► Driver outputs high-Z when disabled or powered off
► Independent enable pins for each driver and receiver
► Enhanced ESD protection on bus pins
► ≥±15 kV HBM, air discharge
► ≥±8 kV HBM, contact discharge
► ≥±10 kV IEC 61000-4-2, air discharge
► ≥±8 kV IEC 61000-4-2, contact discharge
Figure 1.
► Enhanced ±8 kV HBM ESD protection for all pins, contact dis-
charge
GENERAL DESCRIPTION
► Operating temperature range: −40°C to +105°C
► Available in 48-lead, 7 mm x 7 mm LFCSP
The ADN4680E comprises four multipoint, low voltage differential
signaling (M-LVDS) transceivers (driver and receiver pairs) that
can operate at up to 125 MHz, or 250 Mbps nonreturn to zero
(NRZ). The driver and receiver of each transceiver are connected in
half-duplex configuration, which allows each transceiver to be con-
figured via independent enable pins for either sending or receiving
data. Electrostatic discharge (ESD) protection of up to ±15 kV is im-
plemented on the bus pins. The transceivers are optimized for low
dynamic power consumption for use in high density applications.
The ADN4680E is designed to the TIA/EIA-899 standard for use in
M-LVDS networks and complement TIA/EIA-644 LVDS devices with
additional multipoint capabilities.
APPLICATIONS
► Backplane and cable multipoint data transmission
► Multipoint clock distribution
► Low power, high speed alternative to shorter RS-485 links
► Networking and wireless base station infrastructure
► Grid infrastructure and relay protection systems
► Differential extension of SPI networks
The receivers detect the bus state with a differential input of as little
as ±50 mV over a common-mode voltage range of −1 V to
+3.4 V. Each receiver can be independently pin selectable as a
Type 1 or Type 2 receiver. Type 1 receivers have 15 mV of hystere-
sis so that slow changing signals or loss of input does not lead
to output oscillations. Type 2 receivers exhibit an offset threshold,
guaranteeing the output state when the inputs are open (open
circuit fail-safe), the bus is idle (bus idle or terminated fail-safe), or
when the inputs are hard short circuited.
The device is available in a compact 48-lead, 7 mm × 7 mm LFCSP
and operates over a temperature range of −40°C to +105°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to
change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
DOCUMENT FEEDBACK
TECHNICAL SUPPORT
Data Sheet
ADN4680E
TABLE OF CONTENTS
Features................................................................ 1
Applications........................................................... 1
Functional Block Diagram......................................1
General Description...............................................1
Specifications........................................................ 3
Receiver Input Threshold Test Voltages.............4
Timing Specifications......................................... 5
Absolute Maximum Ratings...................................7
Thermal Resistance........................................... 7
Electrostatic Discharge (ESD) Ratings...............7
ESD Caution.......................................................7
Pin Configurations and Function Descriptions.......8
Typical Performance Characteristics.....................9
Test Circuits and Switching Characteristics.........13
Driver Voltage and Current Measurements......13
Driver Timing Measurements........................... 14
Receiver Timing Measurements.......................15
Theory of Operation.............................................16
Three-State Bus Connection............................16
Truth Tables......................................................16
Glitch Free Powering Up and Powering
Down.............................................................. 17
Fault Conditions............................................... 17
Receiver Input Thresholds and Fail-Safe.........17
Sixty-Four Transceivers on a Network............. 17
Applications Information...................................... 18
PCB Layout...................................................... 19
M-LVDS Design Considerations.......................19
Extending the SPI over M-LVDS...................... 19
Outline Dimensions............................................. 21
Ordering Guide.................................................21
Evaluation Boards............................................ 21
REVISION HISTORY
9/2021—Revision 0: Initial Version
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Data Sheet
ADN4680E
SPECIFICATIONS
VCC = 3.0 V to 3.6 V, load resistance (RL) = 50 Ω, and TA = −40°C to +105°C, unless otherwise noted. All typical values are given for VCC
3.3 V and TA = 25°C.
=
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
POWER SUPPLY
Supply Current
ICC
125 MHz clock on DI1 to DI4 or A1 to A4
and B1 to B4, ENP high, and other pins
open, unless stated otherwise
Only Driver Enabled
65
8
75
mA
mA
mA
DE1 to DE4, RE1 to RE4 = VCC, RL = 50 Ω
DE1 to DE4 = 0 V, RE1 to RE4 = VCC
Both Driver and Receiver Disabled
Both Driver and Receiver Enabled
10
115
140
DE1 to DE4 = VCC, RE1 to RE4 = 0 V, RL
50 Ω, load capacitance (CL) = 15 pF
=
Only Receiver Enabled
60
75
mA
mA
DE1 to DE4, RE1 to RE4 = 0 V, CL = 15 pF
ENP low
Power-Down Supply Current
ICCPD
4.5
DRIVER
Differential Outputs
Differential Output Voltage Magnitude
∆|VOD| for Complementary Output States
Common-Mode Output Voltage (Steady State)
ΔVOS(SS) for Complementary Output States
Peak-to-Peak VOS
|VOD
|
450
−50
0.7
550
0
650
+50
1.1
mV
mV
V
See Figure 24
∆|VOD
|
See Figure 24
VOS(SS)
ΔVOS(SS)
VOS(PP)
0.9
0
See Figure 25 and Figure 28
See Figure 25 and Figure 28
See Figure 25 and Figure 28
See Figure 26
−50
+50
mV
mV
V
100
Maximum Steady-State Open-Circuit Output Voltage
VA(O) and
VB(O)
0
2.4
Voltage Overshoot1
Low to High
VPH
VPL
1.2 VSS
24
V
See Figure 29 and Figure 30
See Figure 29 and Figure 30
See Figure 27
High to Low
−0.2 VSS
V
Output Current, Short-Circuit
Logic Inputs (DIx, DEx, and ENP)
Input High Voltage
Input Low Voltage
Input Current
|IOS
|
mA
VIH
VIL
II
2
VCC
0.8
10
V
GND
0
V
μA
Input voltage (VI) = GND to VCC
VI = 0.4 sin(30 × 106πt) V + 0.5 V2
Input Capacitance
RECEIVER
CIN
5
Differential Inputs
Differential Input Threshold Voltage
Type 1 Receiver
See Table 2 and Figure 39
FSx = GND
VTH
VTH
−50
50
+50
150
mV
mV
Type 2 Receiver
FSx = VCC
Input Hysteresis
Type 1 Receiver
VHYS
VHYS
15
0
mV
mV
V
FSx = GND
FSx = VCC
Type 2 Receiver
Differential Input Voltage Magnitude
Logic Output ROx
Short-Circuit Current
Output Voltage
|VID
|
0.05
–65
2.4
VCC
+65
IOS
mA
REx= GND, ROx = VCC or GND
High
VOH
VOL
IOZ
V
Output high current (IOH) = –8 mA
Output low current (IOL) = 8 mA
Output voltage (VO) = 0 V or 3.6 V
Low
0.4
V
High Impedance Output Current
Logic Input (REx) and FSx)
Input Voltage
−10
+15
μA
High
VIH
2
VCC
V
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Data Sheet
ADN4680E
SPECIFICATIONS
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
Low
VIL
II
GND
−10
0.8
0
V
Input Current
μA
VI = GND to VCC
BUS INPUT AND OUTPUT
Input Current
Ax (Receiver or Transceiver with Driver Disabled)
IA
0
16
µA
Bx voltage (VB) = 1.2 V and Ax voltage (VA)
= 3.8 V
−10
−16
0
+10
0
µA
µA
µA
µA
µA
µA
VB = 1.2 V and VA = 0 V or 2.4 V
VB = 1.2 V and VA = −1.4 V
VA = 1.2 V and VB = 3.8 V
VA = 1.2 V and VB = 0 V or 2.4 V
VA = 1.2 V and VB = −1.4 V
VA = VB and 1.4 V ≤ VA ≤ 3.8 V
0 V ≤ VCC ≤ 1.5 V
Bx (Receiver or Transceiver with Driver Disabled)
IB
16
+10
0
−10
−16
−4
Differential (Receiver or Transceiver with Driver Disabled)
IAB
+4
Power-Off Input Current
Ax
IA(OFF)
0
16
+10
0
µA
µA
µA
µA
µA
µA
µA
pF
VB = 1.2 V and VA = 3.8 V
VB = 1.2 V and VA = 0 V or 2.4 V
VB = 1.2 V and VA = −1.4 V
VA = 1.2 V and VB = 3.8 V
VA = 1.2 V and VB = 0 V or 2.4 V
VA = 1.2 V and VB = −1.4 V
VA = VB and 1.4 ≤ VA ≤ 3.8 V
−10
−16
0
Bx
IB(OFF)
16
+10
0
−10
−16
−4
Differential
IAB(OFF)
+4
Input Capacitance (Transceiver with Driver Disabled)
CA or CB
13
VA or VB = 0.4 sin(30e6πt) V + 0.5 V, 2
other input = 1.2 V, DEx = 0 V
Differential Input Capacitance (Transceiver with Driver
Disabled)
CAB
6.5
pF
Ax – Bx voltage (VAB) =
0.4 sin(30× 106πt) V,2 DEx = 0 V
Input Capacitance Balance (CA/CB) (Transceiver with Driver
Disabled)
CA/B
1 ± 0.01
DEx = 0 V
1
These specifications are guaranteed by design and characterization
HP4194A impedance analyzer (or equivalent).
2
RECEIVER INPUT THRESHOLD TEST VOLTAGES
REx = 0 V.
Table 2. Test Voltages for Type 1 Receiver (FSx = GND)
Applied Voltages (V)
VB
Input Voltage (V)
VA
Differential, VID
Common-Mode, VIC
ROx (V)
+2.4
0
0
+2.4
+1.2
High
Low
High
Low
High
Low
+2.4
+3.35
+3.4
−1.4
−1.35
−2.4
+1.2
+3.4
+3.35
−1.35
−1.4
+0.05
−0.05
+0.05
−0.05
+3.375
+3.375
−1.375
−1.375
Table 3. Test Voltages for Type 2 Receiver (FSx = VCC
)
Applied Voltages (V)
Input Voltage (V)
VA
VB
Differential, VID
Common-Mode VIC
ROx (V)
+2.4
0
0
+2.4
−2.4
+0.15
+1.2
High
Low
High
+2.4
+3.25
+1.2
+3.4
+3.325
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Data Sheet
ADN4680E
SPECIFICATIONS
Table 3. Test Voltages for Type 2 Receiver (FSx = VCC
)
Applied Voltages (V)
Input Voltage (V)
Common-Mode VIC
VA
VB
Differential, VID
ROx (V)
+3.4
+3.35
−1.4
−1.4
+0.05
+0.15
+0.05
+3.375
−1.325
−1.375
Low
High
Low
−1.25
−1.35
TIMING SPECIFICATIONS
VCC = 3.0 V to 3.6 V and TA = –40°C to +105°C, unless otherwise noted. All typical specifications are given for VCC = 3.3 V and TA = 25°C.
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
DRIVER
Maximum Data Rate1
250
100
1.5
1
Mbps
Mbps
ns
TA = −40°C to +85°C
TA = −40°C to +105°C
Propagation Delay1
Differential Output Rise and Fall Time1
tPLH, tPHL
tR, tF
1.9
1.3
2.4
See Figure 29 and Figure 30
1.6
ns
See Figure 29 and Figure 30
Output Skew (Channel to Channel)1, 2
tSK(O)
100
135
350
ps
See Figure 29 and Figure 30
1
Pulse Skew |tPHL – tPLH
|
tSK
0
ps
See Figure 29 and Figure 30
Part to Part Skew1, 3
tSK(PP)
tJIT(PER)
tJIT(CYC)
tJIT(RJ)
tJIT(DJ)
ps
See Figure 29 and Figure 30
Period Jitter, RMS (1 Standard Deviation)
Cycle to Cycle Jitter, RMS
Random Jitter, RMS
Deterministic Jitter6
Disable Time1
3
ps
125 MHz clock input4, 5 (see Figure 33)
125 MHz clock input4, 5 (see Figure 33)
250 Mbps 215 − 1 PRBS input4 (see Figure 33)
250 Mbps 215 − 1 PRBS input 4(see Figure 33)
5
ps
2
ps
110
ps
From High Level
tPHZ
tPLZ
7
7
ns
ns
See Figure 31 and Figure 32
See Figure 31 and Figure 32
From Low Level
Enable Time1
To High Level
tPZH
tPZL
6
6
ns
ns
See Figure 31 and Figure 32
See Figure 31 and Figure 32
To Low Level
RECEIVER
Maximum Data Rate1
250
100
3
Mbps
Mbps
ns
TA = −40°C to +85°C
TA = −40°C to +105°C
Propagation Delay1
Rise and Fall Time1
Output Skew (Channel to Channel)1, 2
tPLH, tPHL
tR, tF
tSK(O)
tSK
4
5
CL = 15 pF (see Figure 34 and Figure 35)
CL = 15 pF (see Figure 34 and Figure 35)
CL = 15 pF (see Figure 34 and Figure 35)
CL = 15 pF (see Figure 34 and Figure 35)
FSx = GND
0.65
2.3
300
ns
ps
1
Pulse Skew |tPHL – tPLH
|
Type 1 Receiver
100
300
350
500
820
ps
ps
ps
ps
ps
Type 2 Receiver
Part to Part Skew1, 3
FSx = VCC
tSK(PP)
CL = 15 pF (see Figure 34 and Figure 35)
125 MHz clock input4, 5 (see Figure 38)
125 MHz clock input4, 5 (see Figure 38)
250 Mbps 215 − 1 PRBS input4 (see Figure 38)
FSx = GND, |VID| = 400 mV, VIC = 1 V
FSx = VCC, |VID| = 400 mV, VIC = 1 V
250 Mbps 215 − 1 PRBS input4 (see Figure 38)
FSx = GND, |VID| = 400 mV, VIC = 1 V
FSx = VCC, |VID| = 400 mV, VIC = 1 V
Period Jitter, RMS (1 Standard Deviation)
Cycle to Cycle Jitter, RMS
Deterministic Jitter6
Type 1 Receiver
tJIT(PER)
tJIT(CYC)
tJIT(DJ)
4
7
150
150
ps
ps
Type 2 Receiver
Random Jitter, RMS
Type 1 Receiver
tJIT(RJ)
3
3
Type 2 Receiver
Disable Time1
From High Level
tPHZ
10
ns
See Figure 36 and Figure 37
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Data Sheet
ADN4680E
SPECIFICATIONS
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
From Low Level
Enable Time1
To High Level
To Low Level
tPLZ
10
ns
See Figure 36 and Figure 37
tPZH
tPZL
15
15
ns
ns
See Figure 36 and Figure 37
See Figure 36 and Figure 37
1
Timing parameters are guaranteed by design and characterization. Values do not include stimulus jitter.
2
3
tSK(O) is defined as the difference in propagation delay between the fastest and slowest channel on the same device.
tSK(PP) is defined as the difference between the propagation delays of two devices between any specified terminals. This specification applies to devices at the same VCC
and temperature and with identical packages and test circuits.
4
5
6
tR = tF = 0.5 ns (10% to 90%)
50 ± 1% duty cycle, measured over 30,000 samples.
Deterministic jitter includes jitter due to pulse skew (tSK).
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Data Sheet
ADN4680E
ABSOLUTE MAXIMUM RATINGS
TA = TMIN to TMAX, unless otherwise noted.
ELECTROSTATIC DISCHARGE (ESD) RATINGS
Table 5.
The following ESD information is provided for handling of ESD-sen-
sitive devices in an ESD protected area only.
Parameter
Rating
VCC
−0.5 V to +4 V
−0.5 V to +4 V
−0.5 V to +4.5 V
−1.8 V to +4 V
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
Digital Inputs (RE1 to RE4, FS1 to FS4, and ENP)
Digital Inputs (DE1 to DE4 and DI1 to DI4)
Field induced charged device model (FICDM) per ANSI/ESDA/JE-
DEC JS-002.
Receiver Inputs and Driver Outputs (A1 to A4 and B1
to B4)
International Electrotechnical Commission (IEC) electromagnetic
compatibility: Part 4-2 (IEC) per IEC 61000-4-2
Receiver Output (RO1 to RO4)
Operating Temperature Range
Storage Temperature Range
−0.3 V to +4 V
−40°C to +105°C
−65°C to +150°C
ESD Ratings for ADN4680E
Table 7. ADN4680E, 48-Lead LFCSP
Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operat-
ing conditions for extended periods may affect product reliability.
ESD Model
Withstand Threshold (V)
Class
HBM
≥±8,000 (contact discharge)
≥±15,000 (air discharge)
≥±1,250
3B1
3B2
C51
Level 42
Level 32
FICDM
IEC
≥±8,000 (contact discharge)
≥±10,000 (air discharge)
THERMAL RESISTANCE
1
This class is for all pins.
Thermal performance is directly linked to PCB design and operation
environment. Close attention to PCB thermal design is required.
2
This class is for the A1 to A4 and B1 to B4 pins only.
θJA is the natural convection, junction to ambient thermal resistance
measured in a one cubic foot sealed enclosure.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Charged devi-
ces and circuit boards can discharge without detection. Although
this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
Table 6. Thermal Resistance
Package Type
θJA
Unit
CP-48-51
30.2
°C/W
1
Thermal impedance simulated values are based on JEDEC 2S2P thermal test
board with no bias. See JEDEC JESD-51.
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Data Sheet
ADN4680E
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 5, 8, 12
DE1 to DE4
Driver Output Enable. A logic high on the DE1 to DE4 pins enables the corresponding driver differential outputs. A logic low on the
DE1 to DE4 pins places the corresponding driver differential outputs in a high impedance state. If left floating, the DE1 to DE4 pins are
internally pulled to logic low.
2, 11, 15, 16, 24,
37, 45, 46
VCC
Power Supply (3.3 V ± 0.3 V). All VCC pins must be connected externally to the supply. Decouple the VCC pins to GND with 0.1 μF
capacitors.
3, 9, 13, 47
A2, A3, A4, A1
B2, B3, B4, B1
GND
Noninverting Receiver Input A and Noninverting Driver Output A for Each Transceiver.
Inverting Receiver Input B and Inverting Driver Output B for Each Transceiver.
Ground. All GND pins must be externally connected to ground.
4, 10, 14, 48
6, 7, 18, 23, 27,
31, 34, 38, 43
17, 44
NIC
Not Internally Connected. The NIC pins are not internally connected.
19, 21, 40, 42
RE3 , RE4,
RE1, RE2
Receiver Output Enable. A logic low on the RE1 to RE4 pins enables the corresponding receiver output. A logic high on the RE1 to
RE4 pins places the corresponding receiver output in a high impedance state. If left floating, the RE1 to RE4 pins are internally pulled
to logic high.
20, 22, 39, 41
25, 28, 32, 35
FS3, FS4, FS1, Receiver Fail-Safe Enable. A logic high on the FS1 to FS4 pins enables Type 2 receiver functionality for the corresponding receiver
FS2
inputs (offset threshold). A logic low on the FS1 to FS4 pins enables Type 1 receiver functionality (symmetrical thresholds). If left
floating, the FS1 to FS4 pins are internally pulled to logic high.
DI4, DI3, DI2,
DI1
Driver Inputs. When enabled (the corresponding DE1 to DE4 pins are logic high, and ENP is logic high):
A logic low on the DI1 to DI4 pins forces the corresponding noninverting driver output low and inverting output high, whereas a logic
high on the DI1 to DI4 pins forces the noninverting output high and inverting output low. If left floating, the DI1 to DI4 pins are internally
pulled to logic low.
26, 29, 33, 36
RO4, RO3,
RO2, RO1
Receiver Outputs. When the receiver is enabled (the corresponding RE1 to RE4 pins are logic low, and ENP is logic high),
the following results:
In Type 1 receiver mode (the corresponding FS1 to FS4 pins are logic low),
if Ax − Bx ≥ +50 mV, the output is logic high, and if Ax − Bx ≤ −50 mV, the output is logic low.
In Type 2 receiver mode (the corresponding FS1 to FS4 pins are logic high),
if Ax − Bx ≥ +150 mV, the output is logic high, and if Ax − Bx ≤ +50 mV, the output is logic low.
The receiver outputs are undefined outside of these conditions.
30
ENP
Global Device Power Enable Pin. The device is active when logic high is applied to the ENP pin. Power-down mode when logic low
is applied (overrides all other enable pins for the global device low power shutdown). If left floating, the ENP pin is internally pulled to
logic low.
EPAD
Exposed Pad. The exposed pad must be connected to ground for proper operation.
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Data Sheet
ADN4680E
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 3. ICC vs. Data Rate (Receiver VID = 400 mV and VIC = 1 V)
Figure 6. Receiver Output Low Voltage vs. Output Current
Figure 4. ICC vs. Ambient Temperature (Receiver VID = 400 mV and VIC = 1 V)
Figure 7. Receiver Output High Voltage vs. Output Current
Figure 5. Receiver ICC vs. Receiver CL (Receiver VID = 400 mV and VIC = 1 V)
Figure 8. Driver Differential Output Voltage vs. RL
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Data Sheet
ADN4680E
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 9. Driver Propagation Delay vs. Ambient Temperature
Figure 12. Transmitter Periodic Jitter, RMS vs. Ambient Temperature
Figure 10. Receiver Propagation Delay vs. Ambient Temperature
(VID = 400 mV and VIC = 1.1 V)
Figure 13. Transmitter Cycle to Cycle Jitter, RMS vs. Ambient Temperature
Figure 14. Transmitter Random Jitter, RMS vs. Ambient Temperature
Figure 11. Driver Transition Time vs. Ambient Temperature
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Data Sheet
ADN4680E
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 15. Transmitter Deterministic Jitter vs. Ambient Temperature
(RL = 50 Ω)
Figure 18. Receiver Periodic Jitter, RMS vs. Ambient Temperature
(VID = 400 mV and VIC = 1.1 V)
Figure 19. Receiver Cycle to Cycle Jitter, RMS vs. Ambient Temperature
(VID = 400 mV and VIC = 1.1 V)
Figure 16. Transmitter Deterministic Jitter vs. Data Rate (RL = 50 Ω)
Figure 17. Driver Output Eye Pattern (VCC= 3.3 V, TA= 25℃,
Data Rate = 250 Mbps, PRBS15 Input, and RL = 50 Ω)
Figure 20. Receiver Random Jitter, RMS vs. Ambient Temperature
(VID = 400 mV and VIC = 1.1 V)
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Data Sheet
ADN4680E
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 21. Receiver Deterministic Jitter vs. Ambient Temperature
(VID = 400 mV and VIC = 1.1 V)
Figure 23. Receiver Output Eye Pattern (VCC= 3.3 V, TA= 25℃,
Data Rate = 200 Mbps, PRBS15 Input, and CL = 15 pF)
Figure 22. Receiver Deterministic Jitter vs. Data Rate
(VID = 400 mV and VIC = 1.1 V)
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Data Sheet
ADN4680E
TEST CIRCUITS AND SWITCHING CHARACTERISTICS
DRIVER VOLTAGE AND CURRENT MEASUREMENTS
Figure 24. Driver Differential Output Voltage Measurement over Common-
Mode Range (VTEST Is the Test Voltage)
Figure 27. Driver Short Circuit
Figure 25. Driver Common-Mode Output Voltage Measurement
Figure 28. Driver Common-Mode Output Voltage (Steady State)
Figure 26. Maximum Steady-State Output Voltage Measurement
(S1 Is Switch 1)
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Data Sheet
ADN4680E
TEST CIRCUITS AND SWITCHING CHARACTERISTICS
DRIVER TIMING MEASUREMENTS
Figure 31. Driver Enable and Disable Time Circuit
Figure 29. Driver Timing Measurement Circuit
Figure 32. Driver Enable and Disable Times
Figure 30. Driver Propagation, Rise and Fall Times and Voltage Overshoot
Figure 33. Driver Period, Cycle to Cycle, Random and Deterministic Jitter Characteristics
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Data Sheet
ADN4680E
TEST CIRCUITS AND SWITCHING CHARACTERISTICS
RECEIVER TIMING MEASUREMENTS
Figure 36. Receiver Enable and Disable Time Circuit
Figure 34. Receiver Timing Measurement Circuit
Figure 37. Receiver Enable and Disable Times
Figure 35. Receiver Propagation and Rise and Fall Times
Figure 38. Receiver Period, Cycle to Cycle, Deterministic and Random Jitter Characteristics
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Data Sheet
ADN4680E
THEORY OF OPERATION
The ADN4680E comprises four transceivers for transmitting and
receiving M-LVDS at high data rates of up to 250 Mbps NRZ. Each
device has a differential line driver and a differential line receiver,
allowing each device to send and receive data. The drivers and
receivers are connected in half-duplex configuration, allowing a
transceiver to transmit or to receive but not simultaneously.
Figure 40 shows a typical half-duplex bus topology for M-LVDS.
an REx pin high puts the corresponding receiver output into a
high impedance state. The M-LVDS driver outputs remain in a high
impedance state while the transceiver is not powered.
Truth tables for driver and receiver output states under various
conditions are shown in Table 10 and Table 11.
TRUTH TABLES
Table 9. Truth Table Abbreviation Definitions
M-LVDS expands on the established LVDS method by allowing
bidirectional communication between more than two nodes. Up to
32 nodes can connect to a standard M-LVDS bus. The ADN4680E
is optimized for low dynamic power consumption in applications that
utilize multiple high speed M-LVDS lanes.
Abbreviation
Description
H
L
High level
Low level
X
I
Don’t care
Indeterminate
High impedance (off)
Disconnected/no input
THREE-STATE BUS CONNECTION
Z
The outputs of the device can be placed in a high impedance
state by disabling the driver or the receiver. Placing the driver in
a high impedance state allows several driver outputs to connect
to a single M-LVDS bus. Note that, on each bus line, only one
driver can be enabled at a time, but many receivers can be enabled
simultaneously.
NC
Table 10. Each Driver (See Table 9 for the Abbreviation Definitions)
Inputs
DEx
Outputs
Bx
VCC
ENP
DIx
Ax
On
On
On
On
On
Off
H
H
H
L
H
L
L
Z
Z
Z
L
Each driver can be enabled or disabled using the driver enable
pins (DE1 to DE4). The DEx pins enable the driver outputs when
driven logic high. When driven logic low, the DEx pins put the driver
outputs into a high impedance state. Similarly, active low receiver
enable pins (RE1 to RE4) control each receiver. Driving an REx
pin low enables the corresponding receiver output, whereas driving
H
H
H
H
Z
Z
Z
H
H
NC
X
X
L or NC
L or NC
X
X
X
X
X
Table 11. Each Receiver (see Table 9 for the Abbreviation Definitions)
Inputs
VCC
ENP
REx
FSx
Ax − Bx
Receiver Mode
ROx
On
On
On
On
On
On
On
On
On
On
On
On
Off
H
L
L
≥+50 mV
≤−50 mV
Type 1
Type 1
Type 1
Type 1
Type 1
Type 2
Type 2
Type 2
Type 2
Type 2
X
H
H
L
L
L
I
H
L
L
−50 mV < A − B < +50 mV
H
L
L
NC
I
H
L
L
Short circuit
I
H
L
H or NC
H or NC
H or NC
H or NC
H or NC
X
≥+150 mV
H
L
I
H
L
≤+50 mV
H
L
50 mV < A − B < 150 mV
H
L
NC
L
L
Z
Z
I
H
L
Short circuit
X
H or NC
X
X
X
L or NC
X
X
X
X
X
X
X
analog.com
Rev. 0 | 16 of 21
Data Sheet
ADN4680E
THEORY OF OPERATION
input threshold is offset by 100 mV to ensure that a logic low
is present on the receiver output during the bus idle or receiver
open-circuit conditions.
GLITCH FREE POWERING UP AND POWERING
DOWN
To minimize disruption to the bus when adding or removing nodes
from the network, the M‑LVDS outputs of the device are kept glitch
free when the device is powering up or powering down. This feature
allows insertion of a device onto a live M-LVDS bus because the
bus outputs are not switched on before the device is fully powered.
In addition, all outputs are placed in a high impedance state when
the device is powered off.
The different receiver thresholds for the two receiver types are
illustrated in Figure 39. See Table 11 for the receiver output states
under various conditions.
FAULT CONDITIONS
The ADN4680E contains short-circuit current protection that pro-
tects the device under fault conditions in case of short circuits on
the bus. This protection limits the transmitter output current in a
fault condition to 24 mA for short-circuit faults between
−1 V and +3.4 V. Any network fault must be cleared to avoid data
transmission errors and to ensure reliable operation of the data
network and of any devices that are connected to the network.
Figure 39. Input Threshold Voltages (VIA Is the Voltage Input on Pin Ax, and
VIB Is the Voltage Input on Pin Bx.)
RECEIVER INPUT THRESHOLDS AND FAIL-
SAFE
SIXTY-FOUR TRANSCEIVERS ON A NETWORK
Two receiver types are pin-selectable using the FSx pins for each
receiver. Protection against short circuits is integrated into each
receiver.
The TIA/EIA-899 standard specifies a maximum of 32 M-
LVDS transceivers connected to the same differential pair. The
ADN4680E receiver exceeds these requirements by a factor of two,
with a reduced input current allowing more devices to be connected
to the network without excessively loading a transmitter. Up to 64
transceivers from the ADN4680E can be connected to a single
network. The ac loading effects of any M-LVDS transceivers on
the network must also be considered. See the M-LVDS Design
Considerations section for more details.
Type 1 receivers (configured with FSx low) incorporate 15 mV of
hysteresis to ensure that slow changing signals or a loss of input
does not result in the oscillation of the receiver output. Type 1
receiver thresholds are ±50 mV. Therefore, the state of the receiver
output is indeterminate if the differential between Ax and Bx is
approximately 0 V. This state occurs if the bus is idle (approximately
0 V on both Ax and Bx), with no drivers enabled on the attached
nodes.
Type 2 receivers (configured with FSx high or open) have an
open-circuit, short-circuit, and bus idle (terminated) fail-safe. The
analog.com
Rev. 0 | 17 of 21
Data Sheet
ADN4680E
APPLICATIONS INFORMATION
M-LVDS extends the low power, high speed, differential signaling
of LVDS to multipoint systems where multiple nodes are connected
over short distances in a bus topology network.
The communication line is typically terminated at both ends by
resistors (RT), the value of which is chosen to match the character-
istic impedance of the medium (typically 100 Ω). For half-duplex
multipoint applications such as the one shown in Figure 40, only
one driver can be enabled at any time.
With M-LVDS, a transmitting node drives a differential signal across
a transmission medium such as a twisted pair cable. The transmit-
ted differential signal allows other receiving nodes that are connect-
ed along the bus to detect a differential voltage that can then be
converted back into a single-ended logic signal by the receiver.
Figure 40. Typical Half-Duplex M-LVDS Network
analog.com
Rev. 0 | 18 of 21
Data Sheet
ADN4680E
APPLICATIONS INFORMATION
where:
PCB LAYOUT
ZEFF is the effective characteristic impedance.
Z0 is the characteristic impedance of the M-LVDS signals.
L0 is the inductance per unit length of the M-LVDS signals.
C0 is the differential capacitance per unit length of the M-LVDS
signals.
CL is the differential capacitance of the load (the transceiver
module).
The ADN4680E must be adequately decoupled with 0.1 μF capaci-
tors between the VCC and GND pins.
The RO1 to RO4 pins of the ADN4680E output a 3.3 V single-
ended signal with fast switching edges of approximately 1 ns. Keep
these traces short and routed over a continuous reference plane to
minimize radiated emissions. Edge coupling to the reference plane
helps minimize fringing electric fields.
D is the distance between the loads.
EXTENDING THE SPI OVER M-LVDS
The RO1 to RO4 trace capacitance affects the switching supply
current drawn from the VCC supply. In applications where the low
power consumption is desired, minimize the RO1 to RO4 trace
length and capacitance (see Figure 5).
The ADN4680E can extend the reach and reliability of a serial
peripheral interface (SPI). At a high clock rate and transmission
distance, the single-ended signals used in the SPI suffer from
poor electromagnetic compatibility (EMC). Differential extenders are
commonly used to allow the reliable transmission of the SPI over
longer distances. The ADN4680E has several features that make it
well suited for this:
For optimum thermal performance, the exposed pad of the LFCSP
must be connected to GND and connected to a solid reference
plane through an array of 16 vias with diameter of 0.3 mm, or
similar.
► A data rate of up to 125 MHz supports the highest SPI clock
rates with minimal added skew and jitter.
► A quad channel transceiver that allows a single device to extend
the CLK, MOSI, MISO, and SS signals of the SPI.
► A half-duplex configuration allows for configurable channel direc-
tionality.
► The low propagation delay of the transceiver minimizes the
impact on transmission distance at higher SPI clock frequencies.
M-LVDS DESIGN CONSIDERATIONS
In a backplane or cabled M-LVDS network, the signal integrity is
dependent on good design practices. Follow these guidelines to
minimize adverse effects on noise margin caused by reflections:
► Route the M-LVDS signals as an impedance controlled differen-
tial pair, as either an edge-coupled microstrip or an embedded
edge-coupled stripline. The stripline is the preferred method.
► A differential characteristic impedance of between 100 Ω and
130 Ω is recommended. In heavily loaded M-LVDS networks, a
larger characteristic impedance gives the best noise margin.
► Maintain a uniform impedance across the M-LVDS network
where possible. Avoid unnecessary discontinuities, such as vias
or large test points, along the M-LVDS signals.
► Place M-LVDS transceiver modules at uniform distances across
the transmission line where possible.
► Place termination resistors within 2.5 cm of the end of the cable
or backplane.
► The robust EMC protection on the M-LVDS input and output pins
is suitable for operation in harsh environments.
► The M-LVDS common-mode range allows communication in the
presence of up to ±2 V of ground offset.
In Figure 41, the CLK, MOSI, and MISO signals of the SPI are
extended over several meters between a processor and a remote
device. The same schematic can function as either a master or
a remote interface, selectable via a single logic pin (M/#R). The
fourth transceiver of the ADN4680E is not shown and can be used
to extend the other SPI signals, such as the chip select line or an
interrupt from the remote device to the microcontroller unit (MCU).
► Keep any stub lengths off the main cable or backplane to less
than 2.5 cm.
► Minimize connector capacitance where possible.
► Note that Type 2 receivers include fail-safe functionality but have
reduced noise margin when receiving data. Configure receivers
as Type 1 where receiver fail-safe functionality is not required.
► In heavily loaded M-LVDS networks with multiple devices, match
the termination resistors to the effective impedance (ZEFF) of the
network. The effective impedance of the network is determined
by the capacitance of the network, the capacitance of each
transceiver module, and the distance between them as follows:
L
0
1
ZEFF
=
= Z0
C
L
D
C
L
(1)
C
+
1 +
0
C D
0
analog.com
Rev. 0 | 19 of 21
Data Sheet
ADN4680E
APPLICATIONS INFORMATION
Figure 41. SPI over M-LVDS with ADN4680E
A requirement of the SPI is that the round-trip time delay between
the master and the peripheral is less than half the SPI clock
period. This requirement places a restriction on the allowed latency,
which in turn, limits the maximum cable distance between the
master and the peripheral. Devices placed within the signal path,
such as transceivers, digital isolators, and level translators, add fur-
ther propagation delay, which reduces the maximum cable length.
The ADN4680E features 10× lower propagation delay than similar
RS-485-based solutions, allowing a 10 MHz SPI to operate over
several meters of Category 5e (Cat 5e) cabling.
Figure 42. Maximum Cable Length vs. SPI Clock Frequency
analog.com
Rev. 0 | 20 of 21
Data Sheet
ADN4680E
OUTLINE DIMENSIONS
Figure 43. 48-Lead Frame Chip Scale Package [LFCSP]
7 mm × 7 mm Body and 0.75 mm Package Height
(CP-48-5)
Dimensions Shown in Millimeters
Updated: September 09, 2021
ORDERING GUIDE
Package
Option
Model1
Temperature Range
Package Description
Packing Quantity
ADN4680EBCPZ
–40°C to +105°C
–40°C to +105°C
48-Lead LFCSP (7 mm × 7 mm with EPAD)
48-Lead LFCSP (7 mm × 7 mm with EPAD)
Tray, 0
CP-48-5
CP-48-5
ADN4680EBCPZ-RL
Reel, 2500
1
Z = RoHS Compliant Part.
EVALUATION BOARDS
Model
Description
EVAL-ADN4680EEBZ1
ADN4680E Evaluation Board
1
Z = RoHS Compliant Part.
©2021 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887-2356, U.S.A.
Rev. 0 | 21 of 21
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