ADN4697E [ADI]
3.3 V, 200 Mbps, Half- and Full-Duplex; 3.3 V ， 200 Mbps的半双工和全双工
| 型号： | ADN4697E |
| 厂家： | 
ADI |
| 描述： | 3.3 V, 200 Mbps, Half- and Full-Duplex |
| 文件： | 总20页 (文件大小：351K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 V, 200 Mbps, Half- and Full-Duplex,
High Speed M-LVDS Transceivers
Data Sheet
ADN4691E/ADN4693E/ADN4696E/ADN4697E
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
V
CC
Multipoint LVDS transceivers (low voltage differential
signaling driver and receiver pairs)
Switching rate: 200 Mbps (100 MHz)
Supported bus loads: 30 Ω to 55 Ω
Choice of 2 receiver types
Type 1 (ADN4691E/ADN4693E): hysteresis of 25 mV
Type 2 (ADN4696E/ADN4697E): threshold offset of 100 mV
for open-circuit and bus-idle fail-safe
Conforms to TIA/EIA-899 standard for M-LVDS
Glitch-free power-up/power-down on M-LVDS bus
Controlled transition times on driver output
Common-mode range: −1 V to +3.4 V, allowing
communication with 2 V of ground noise
Driver outputs high-Z when disabled or powered off
Enhanced ESD protection on bus pins
ADN4691E/
ADN4696E
RO
RE
DE
DI
R
A
B
D
GND
Figure 1.
V
CC
ADN4693E/
ADN4697E
A
B
RO
RE
DE
DI
R
15 kV HBM (human body model), air discharge
8 kV HBM (human body model), contact discharge
10 kV IEC 61000-4-2, air discharge
Z
Y
D
8 kV IEC 61000-4-2, contact discharge
Operating temperature range: −40°C to +85°C
Available in 8-lead (ADN4691E/ADN4696E) and 14-lead
(ADN4693E/ADN4697E) SOIC packages
GND
Figure 2.
APPLICATIONS
Backplane and cable multipoint data transmission
Multipoint clock distribution
Low power, high speed alternative to shorter RS-485 links
Networking and wireless base station infrastructure
GENERAL DESCRIPTION
The ADN4691E/ADN4693E/ADN4696E/ADN4697E are
multipoint, low voltage differential signaling (M-LVDS)
transceivers (driver and receiver pairs) that can operate at up to
200 Mbps (100 MHz). The receivers detect the bus state with a
differential input of as little as 50 mV over a common-mode
voltage range of −1 V to +3.4 V. ESD protection of up to 15 kV
is implemented on the bus pins. The parts adhere to the
TIA/EIA-899 standard for M-LVDS and complement TIA/EIA-
644 LVDS devices with additional multipoint capabilities.
The parts are available as half-duplex in an 8-lead SOIC package
(the ADN4691E/ADN4696E) or as full-duplex in a 14-lead
SOIC package (the ADN4693E/ADN4697E). A selection table
for the ADN469xE parts is shown in Table 1.
Table 1. ADN469xE Selection Table
Part No.
Receiver
Data Rate
100 Mbps
200 Mbps
100 Mbps
200 Mbps
100 Mbps
100 Mbps
200 Mbps
200 Mbps
SOIC
Duplex
Half
Half
Full
Full
Half
Full
ADN4690E Type 1
ADN4691E Type 1
ADN4692E Type 1
ADN4693E Type 1
ADN4694E Type 2
ADN4695E Type 2
ADN4696E Type 2
ADN4697E Type 2
8-lead
8-lead
14-lead
14-lead
8-lead
14-lead
8-lead
14-lead
The ADN4691E/ADN4693E are Type 1 receivers with 25 mV of
hysteresis, so that slow-changing signals or loss of input does
not lead to output oscillations. The ADN4696E/ADN4697E are
Type 2 receivers exhibiting an offset threshold, guaranteeing the
output state when the bus is idle (bus-idle fail-safe) or the inputs are
open (open-circuit fail-safe).
Half
Full
Rev. A
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Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
ADN4691E/ADN4693E/ADN4696E/ADN4697E
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Driver Voltage and Current Measurements............................ 11
Driver Timing Measurements .................................................. 12
Receiver Timing Measurements............................................... 13
Theory of Operation ...................................................................... 14
Half-Duplex/Full-Duplex Operation....................................... 14
Three-State Bus Connection..................................................... 14
Truth Tables................................................................................. 14
Glitch-Free Power-Up/Power-Down....................................... 15
Fault Conditions......................................................................... 15
Receiver Input Thresholds/Fail-Safe........................................ 15
Applications Information.............................................................. 16
Outline Dimensions....................................................................... 17
Ordering Guide .......................................................................... 17
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description......................................................................... 1
Revision History........................................................................... 2
Specifications..................................................................................... 3
Receiver Input Threshold Test Voltages .................................... 4
Timing Specifications .................................................................. 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Test Circuits and Switching Characteristics................................ 11
REVISION HISTORY
3/12—Rev. 0 to Rev. A
Changes to Table 8.............................................................................7
Changes to Figure 33.......................................................................13
Added Table 12 ................................................................................14
Changes to Receiver Input Thresholds/Fail-Safe Section
and Figure 36....................................................................................15
Changes to Ordering Guide...........................................................17
Added ADN4691E and ADN4693E................................. Universal
Changes to Features Section, General Description Section,
and Table 1..........................................................................................1
Added Type 1 Receiver Parameters, Table 2 ..................................3
Added Table 3, Renumbered Sequentially .....................................4
Added Type 1 Receiver Parameters, Table 5 ..................................5
Added Table 7.....................................................................................6
12/11—Revision 0: Initial Version
Rev. A | Page 2 of 20
Data Sheet
ADN4691E/ADN4693E/ADN4696E/ADN4697E
SPECIFICATIONS
VCC = 3.0 V to 3.6 V; RL = 50 Ω; TA = TMIN to TMAX, unless otherwise noted. 1
Table 2.
Parameter
Symbol
Min
Typ
Max
Unit Test Conditions/Comments
DRIVER
Differential Outputs
Differential Output Voltage Magnitude
∆|VOD| for Complementary Output States
Common-Mode Output Voltage (Steady State)
ΔVOC(SS) for Complementary Output States
Peak-to-Peak VOC
|VOD
∆|VOD
VOC(SS)
ΔVOC(SS)
VOC(PP)
|
480
−50
0.8
650
+50
1.2
+50
150
2.4
mV
mV
V
mV
mV
V
See Figure 19
See Figure 19
See Figure 20, Figure 23
See Figure 20, Figure 23
See Figure 20, Figure 23
See Figure 21
|
−50
Maximum Steady-State Open-Circuit Output
Voltage
VA(O), VB(O)
VY(O), or VZ(O)
,
0
Voltage Overshoot
Low to High
High to Low
VPH
VPL
1.2VSS
V
V
See Figure 24, Figure 27
See Figure 24, Figure 27
−0.2VSS
Output Current
Short Circuit
High Impedance State, Driver Only
|IOS
IOZ
|
24
+10
mA
μA
See Figure 22
–1.4 V ≤ (VY or VZ) ≤ 3.8 V,
other output = 1.2 V
–1.4 V ≤ (VY or VZ) ≤ 3.8 V,
other output = 1.2 V, 0 V ≤ VCC ≤ 1.5 V
VI = 0.4 sin(30e6πt) V + 0.5 V,2
other output = 1.2 V, DE = 0 V
VAB = 0.4 sin(30e6πt) V,2 DE = 0 V
−15
−10
Power Off
IO(OFF)
+10
μA
pF
pF
Output Capacitance
CY or CZ
3
Differential Output Capacitance
Output Capacitance Balance (CY/CZ)
Logic Inputs (DI, DE)
CYZ
CY/Z
2.5
1.01
0.99
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
VIH
VIL
IIH
2
GND
0
0
VCC
0.8
10
V
V
μA
μA
VIH = 2 V
VIL = 0.8 V
IIL
10
RECEIVER
Differential Inputs
Differential Input Threshold Voltage
Type 1 Receiver (ADN4691E, ADN4693E)
Type 2 Receiver (ADN4696E, ADN4697E)
Input Hysteresis
VTH
VTH
−50
50
+50
150
mV
mV
See Table 3, Figure 36
See Table 4, Figure 36
Type 1 Receiver (ADN4691E, ADN4693E)
Type 2 Receiver (ADN4696E, ADN4697E)
Differential Input Voltage Magnitude
Input Capacitance
VHYS
VHYS
|VID|
CA or CB
25
0
mV
mV
V
0.05
VCC
3
pF
VI = 0.4 sin(30e6πt) V + 0.5 V,2
other input = 1.2 V
Differential Input Capacitance
Input Capacitance Balance (CA/CB)
Logic Output RO
Output High Voltage
Output Low Voltage
CAB
CA/B
2.5
1.01
pF
VAB = 0.4 sin(30e6πt) V2
0.99
2.4
VOH
VOL
IOZ
V
V
μA
IOH = –8 mA
IOL = 8 mA
VO = 0 V or 3.6 V
0.4
+15
High Impedance Output Current
Logic Input RE
−10
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
VIH
VIL
IIH
2
VCC
0.8
0
V
V
μA
μA
GND
−10
−10
VIH = 2 V
VIL = 0.8 V
IIL
0
Rev. A | Page 3 of 20
ADN4691E/ADN4693E/ADN4696E/ADN4697E
Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit Test Conditions/Comments
BUS INPUT/OUTPUT
Input Current
A (Receiver or Transceiver with Driver Disabled) IA
0
32
+20
0
32
+20
0
μA
μA
μA
μA
μA
μA
μA
VB = 1.2 V, VA = 3.8 V
−20
−32
0
−20
−32
−4
VB = 1.2 V, VA = 0 V or 2.4 V
VB = 1.2 V, VA = −1.4 V
VA = 1.2 V, VB = 3.8 V
VA = 1.2 V, VB = 0 V or 2.4 V
VA = 1.2 V, VB = −1.4 V
VA = VB, 1.4 V ≤ VA ≤ 3.8 V
B (Receiver or Transceiver with Driver Disabled)
IB
Differential (Receiver or Transceiver with Driver
Disabled)
IAB
+4
Power-Off Input Current
A (Receiver or Transceiver)
0 V ≤ VCC ≤ 1.5 V
IA(OFF)
0
32
+20
0
32
+20
0
μA
μA
μA
μA
μA
μA
μA
pF
VB = 1.2 V, VA = 3.8 V
VB = 1.2 V, VA = 0 V or 2.4 V
VB = 1.2 V, VA = −1.4 V
VA = 1.2 V, VB = 3.8 V
VA = 1.2 V, VB = 0 V or 2.4 V
VA = 1.2 V, VB = −1.4 V
VA = VB, 1.4 ≤ VA ≤ 3.8 V
VI = 0.4 sin(30e6πt) V + 0.5 V,2
other input = 1.2 V, DE = 0 V
VAB = 0.4 sin(30e6πt) V,2 DE = 0 V
−20
−32
0
−20
−32
−4
B (Receiver or Transceiver)
IB(OFF)
Differential (Receiver or Transceiver)
Input Capacitance (Transceiver with Driver Disabled) CA or CB
IAB(OFF)
+4
5
Differential Input Capacitance (Transceiver with
Driver Disabled)
CAB
3
pF
Input Capacitance Balance (CA/CB) (Transceiver
with Driver Disabled)
CA/B
0.99
1.01
DE = 0 V
POWER SUPPLY
Supply Current
ICC
Only Driver Enabled
13
1
22
4
mA
mA
mA
mA
DE, RE = VCC, RL = 50 Ω
Both Driver and Receiver Disabled
Both Driver and Receiver Enabled
Only Receiver Enabled
DE = 0 V, RE= VCC, RL = no load
DE = VCC, RE = 0 V, RL = 50 Ω
DE, RE = 0 V, RL = 50 Ω
16
4
24
13
1 All typical values are given for VCC = 3.3 V and TA = 25°C.
2 HP4194A impedance analyzer (or equivalent).
RECEIVER INPUT THRESHOLD TEST VOLTAGES
RE
= 0 V, H = high, L = low
Table 3. Test Voltages for Type 1 Receiver
Applied Voltages
Input Voltage, Differential
Input Voltage, Common Mode
Receiver Output
VA (V)
2.4
0
VB (V)
0
2.4
3.75
3.8
−1.4
−1.35
VID (V)
2.4
−2.4
0.05
−0.05
0.05
−0.05
VIC (V)
1.2
1.2
3.775
3.775
−1.375
−1.375
RO (V)
H
L
H
L
H
L
3.8
3.75
−1.35
−1.4
Rev. A | Page 4 of 20
Data Sheet
ADN4691E/ADN4693E/ADN4696E/ADN4697E
Table 4. Test Voltages for Type 2 Receiver
Applied Voltages
Input Voltage, Differential
Input Voltage, Common Mode Receiver Output
VA (V)
+2.4
0
+3.8
+3.8
−1.25
−1.35
VB (V)
0
VID (V)
+2.4
−2.4
+0.15
+0.05
+0.15
+0.05
VIC (V)
+1.2
+1.2
+3.725
+3.775
−1.325
−1.375
RO (V)
H
L
H
L
H
L
+2.4
+3.65
+3.75
−1.4
−1.4
TIMING SPECIFICATIONS
VCC = 3.0 V to 3.6 V; TA = TMIN to TMAX, unless otherwise noted.1
Table 5.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
DRIVER
Maximum Data Rate
Propagation Delay
Differential Output Rise/Fall Time
200
1
1
Mbps
ns
ns
ps
ns
ps
ps
ns
ns
tPLH, tPHL
tR, tF
tSK
tSK(PP)
tJ(PER)
tJ(PP)
tPHZ
tPLZ
tPZH
tPZL
1.5
0
2.4
1.6
100
1
3
130
7
7
7
7
See Figure 24, Figure 27
See Figure 24, Figure 27
See Figure 24, Figure 27
See Figure 24, Figure 27
100 MHz clock input4 (see Figure 26)
200 Mbps 215 − 1 PRBS input6 (see Figure 29)
See Figure 25, Figure 28
See Figure 25, Figure 28
See Figure 25, Figure 28
Pulse Skew |tPHL – tPLH
|
Part-to-Part Skew2
Period Jitter, RMS (1 Standard Deviation)3
Peak-to-Peak Jitter3, 5
Disable Time from High Level
Disable Time from Low Level
Enable Time to High Level
Enable Time to Low Level
2
30
ns
ns
See Figure 25, Figure 28
RECEIVER
Propagation Delay
Rise/Fall Time
Pulse Skew |tRPHL – tRPLH
tRPLH, tRPHL
tR, tF
tSK
2
1
4
6
2.3
ns
ns
CL = 15 pF (see Figure 30, Figure 33)
CL = 15 pF (see Figure 30, Figure 33)
CL = 15 pF (see Figure 30, Figure 33)
|
Type 1 Receiver (ADN4691E,
ADN4693E)
Type 2 Receiver (ADN4696E,
ADN4697E)
Part-to-Part Skew2
Period Jitter, RMS (1 Standard Deviation)3
Peak-to-Peak Jitter3, 5
100
300
300
500
ps
ps
tSK(PP)
tJ(PER)
tJ(PP)
1
7
ns
ps
CL = 15 pF (see Figure 30, Figure 33)
100 MHz clock input7 (see Figure 32)
200 Mbps 215 − 1 PRBS input8 (see Figure 35)
4
Type 1 Receiver (ADN4691E,
ADN4693E)
Type 2 Receiver (ADN4696E,
ADN4697E)
tJ(PP)
300
450
700
800
ps
ps
Disable Time from High Level
Disable Time from Low Level
Enable Time to High Level
Enable Time to Low Level
tRPHZ
tRPLZ
tRPZH
tRPZL
10
10
15
15
ns
ns
ns
ns
See Figure 31, Figure 34
See Figure 31, Figure 34
See Figure 31, Figure 34
See Figure 31, Figure 34
1 All typical values are given for VCC = 3.3 V and TA = 25°C.
2 tSK(PP) is defined as the difference between the propagation delays of two devices between any specified terminals. This specification applies to devices at the same VCC
and temperature, and with identical packages and test circuits.
3 Jitter parameters are guaranteed by design and characterization. Values do not include stimulus jitter.
4 tR = tF = 0.5 ns (10% to 90%), measured over 30,000 samples.
5 Peak-to-peak jitter specifications include jitter due to pulse skew (tSK).
6 tR = tF = 0.5 ns (10% to 90%), measured over 100,000 samples.
7 |VID| = 400 mV (ADN4696E, ADN4697E), Vic = 1.1 V, tR = tF = 0.5 ns (10% to 90%), measured over 30,000 samples.
8 |VID| = 400 mV (ADN4696E, ADN4697E), Vic = 1.1 V, tR = tF = 0.5 ns (10% to 90%), measured over 100,000 samples.
Rev. A | Page 5 of 20
ADN4691E/ADN4693E/ADN4696E/ADN4697E
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = TMIN to TMAX, unless otherwise noted.
THERMAL RESISTANCE
Table 6.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
Rating
VCC
−0.5 V to +4 V
−0.5 V to +4 V
Digital Input Voltage (DE, RE, DI)
Receiver Input (A, B) Voltage
Half-Duplex (ADN4691E, ADN4696E)
Full-Duplex (ADN4693E, ADN4697E)
Receiver Output Voltage (RO)
Driver Output (A, B, Y, Z) Voltage
ESD Rating (A, B, Y, Z Pins)
HBM (Human Body Model)
Air Discharge
Table 7. Thermal Resistance
Package Type
8-Lead SOIC
14-Lead SOIC
θJA
121
86
Unit
°C/W
°C/W
−1.8 V to +4 V
−4 V to +6 V
−0.3 V to +4 V
−1.8 V to +4 V
ESD CAUTION
15 kV
8 kV
Contact Discharge
IEC 61000-4-2, Air Discharge
IEC 61000-4-2, Contact Discharge
ESD Rating (Other Pins, HBM)
ESD Rating (All Pins)
10 kV
8 kV
4 kV
FICDM
1.25 kV
Machine Model
400 V
Operating Temperature Range
Storage Temperature Range
−40°C to +85°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. A | Page 6 of 20
Data Sheet
ADN4691E/ADN4693E/ADN4696E/ADN4697E
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NC
RO
1
2
3
4
5
6
7
14
13
12
11
10
9
V
V
CC
CC
ADN4693E/
ADN4697E
TOP VIEW
RE
A
DE
B
(Not to Scale)
RO
RE
DE
DI
1
2
3
4
8
7
6
5
V
CC
DI
Z
ADN4691E/
ADN4696E
TOP VIEW
(Not to Scale)
B
GND
GND
Y
8
NC
A
GND
NC = NO CONNECT
Figure 3. ADN4691E/ADN4696E Pin Configuration
Figure 4. ADN4693E/ADN4697E Pin Configuration
Table 8. Pin Function Descriptions
ADN4691E/ ADN4693E/
ADN4696E
Pin No.
ADN4697E
Pin No.
Mnemonic Description
1
2
RO
Receiver Output. Type 1 receiver (ADN4691E/ADN4693E), when enabled:
If A − B ≥ 50 mV, then RO = logic high. If A − B ≤ −50 mV, then RO = logic low.
Type 2 receiver (ADN4696E/ADN4697E), when enabled:
If A − B ≥ 150 mV, then RO = logic high. If A − B ≤ 50 mV, then RO = logic low.
Receiver output is undefined outside these conditions.
2
3
4
3
4
5
RE
DE
DI
Receiver Output Enable. A logic low on this pin enables the receiver output, RO.
A logic high on this pin places RO in a high impedance state.
Driver Output Enable. A logic high on this pin enables the driver differential outputs.
A logic low on this pin places the driver differential outputs in a high impedance state.
Driver Input. Half-duplex (ADN4691E/ADN4696E), when enabled:
A logic low on DI forces A low and B high, whereas a logic high on DI forces A high and B low.
Full-duplex (ADN4693E/ADN4697E), when enabled:
A logic low on DI forces Y low and Z high, whereas a logic high on DI forces Y high and Z low.
Ground.
Noninverting Driver Output Y.
Inverting Driver Output Z.
Noninverting Receiver Input A and Noninverting Driver Output A.
Noninverting Receiver Input A.
Inverting Receiver Input B and Inverting Driver Output B.
Inverting Receiver Input B.
5
6, 7
9
10
N/A
12
N/A
11
GND
Y
Z
A
A
B
B
VCC
NC
N/A
N/A
6
N/A
7
N/A
8
N/A
13, 14
1, 8
Power Supply (3.3 V 0.3 V).
No Connect. Do not connect to these pins.
Rev. A | Page 7 of 20
ADN4691E/ADN4693E/ADN4696E/ADN4697E
TYPICAL PERFORMANCE CHARACTERISTICS
Data Sheet
20
18
0
–5
V
V
V
= 3.0V
= 3.3V
= 3.6V
CC
CC
CC
–10
–15
–20
–25
–30
–35
–40
–45
–50
16
DRIVER
14
12
10
8
6
RECEIVER (V = 250mV, V = 1V)
4
2
0
ID
IC
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
(V)
4.0
0
20
40
60
80
100
120
RECEIVER HIGH LEVEL OUTPUT VOLTAGE, V
OH
FREQUENCY (MHz)
Figure 8. Receiver Output Current vs. Output Voltage (Output High)
(TA = 25°C)
Figure 5. Power Supply Current (ICC) vs. Frequency
(VCC = 3.3 V, TA = 25°C; Receiver VID = 250 mV, VIC = 1 V)
20
18
16
14
12
10
8
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
DRIVER
RECEIVER (V = 250mV, V = 1V)
ID
IC
6
4
2
0
–50
–30
–10
10
30
50
70
90
0
2
4
6
8
10
12
14
TEMPERATURE (°C)
OUTPUT CURRENT, I (mA)
O
Figure 9. Driver Differential Output Voltage vs. Output Current
(VCC = 3.3 V, TA = 25°C)
Figure 6. Power Supply Current vs. Temperature (Data Rate = 200 Mbps,
CC = 3.3 V; Receiver VID = 250 mV, VIC = 1 V)
V
2.4
40
35
30
25
20
15
10
5
tPHL
tPLH
V
V
V
= 3V
= 3.3V
= 3.6V
CC
CC
CC
2.2
2.0
1.8
1.6
1.4
1.2
0
1.0
–40
–20
0
20
40
60
80
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
TEMPERATURE, T (°C)
RECEIVER LOW LEVEL OUTPUT VOLTAGE, V (V)
A
OL
Figure 10. Driver Propagation Delay vs. Temperature
(Data Rate = 2 Mbps, VCC = 3.3 V)
Figure 7. Receiver Output Current vs. Output Voltage (Output Low)
(TA = 25°C)
Rev. A | Page 8 of 20
Data Sheet
ADN4691E/ADN4693E/ADN4696E/ADN4697E
120
100
80
60
40
20
0
6.0
tRPLH
tRPHL
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
–50
–30
–10
10
30
50
70
90
120
90
–50
–30
–10
10
30
50
70
90
TEMPERATURE, T (°C)
TEMPERATURE, T (°C)
A
A
Figure 11. Receiver Propagation Delay vs. Temperature
(Data Rate = 2 Mbps, VCC = 3.3 V, VID = 400 mV, VIC = 1.1 V)
Figure 14. Driver Jitter (Peak-to-Peak) vs. Temperature
(Data Rate = 200 Mbps, VCC = 3.3 V, PRBS 215 − 1 Input)
3.0
7
6
5
4
3
2
1
0
2.5
2.0
1.5
1.0
0.5
0
0
20
40
60
80
100
20
30
40
50
60
70
80
90
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 12. Driver Jitter (Period) vs. Frequency
(VCC = 3.3 V, TA = 25°C, Clock Input)
Figure 15. Receiver Jitter (Period) vs. Frequency
(VCC = 3.3 V, TA = 25°C, VID = 400 mV)
800
700
600
500
400
300
200
100
0
120
100
80
60
40
20
0
0
20
40
60
80
100 120 140 160 180 200
–50
–30
–10
10
30
50
70
DATA RATE (Mbps)
TEMPERATURE (°C)
Figure 16. Receiver Jitter (Peak-to-Peak) vs. Temperature
Figure 13. Driver Jitter (Peak-to-Peak) vs. Data Rate
(VCC = 3.3 V, TA = 25°C, PRBS 215 − 1 Input)
(Data Rate = 200 Mbps, VCC = 3.3 V, VID = 400 mV, VIC = 1.1 V,
PRBS 215 − 1 Input)
Rev. A | Page 9 of 20
ADN4691E/ADN4693E/ADN4696E/ADN4697E
Data Sheet
1ns/DIV
2.5ns/DIV
Figure 17. ADN4696E Driver Output Eye Pattern
Figure 18. ADN4696E Receiver Output Eye Pattern
(Data Rate = 200 Mbps, PRBS 215 − 1 Input, CL = 15 pF)
(Data Rate = 200 Mbps, PRBS 215 − 1 Input, RL = 50 Ω)
Rev. A | Page 10 of 20
Data Sheet
ADN4691E/ADN4693E/ADN4696E/ADN4697E
TEST CIRCUITS AND SWITCHING CHARACTERISTICS
DRIVER VOLTAGE AND CURRENT MEASUREMENTS
A/Y
3.32kΩ
I
OS
V
CC
49.9Ω
V
DI
OD
+
A/Y
B/Z
3.32kΩ
B/Z
DI
–1V TO +3.4V
V
TEST
S1
S2
–1V OR +3.4V
–
V
TEST
NOTES
1. 1% TOLERANCE FOR ALL RESISTORS
Figure 19. Driver Voltage Measurement over Common-Mode Range
Figure 22. Driver Short Circuit
A/Y
B/Z
≈ 1.3V
≈ 0.7V
C1
1pF
R1
24.9Ω
A/Y
B/Z
DI
R2
24.9Ω
C3
2.5pF
V
OC
∆V
OC(SS)
V
C2
V
OC
OC(PP)
1pF
NOTES
1. C1, C2, AND C3 ARE 20% AND INCLUDE PROBE/STRAY
CAPACITANCE LESS THAN 2cm FROM DUT.
2. R1 AND R2 ARE 1%, METAL FILM, SURFACE MOUNT,
LESS THAN 2cm FROM DUT.
NOTES
1. INPUT PULSE GENERATOR: 500kHz; 50% ± 5% DUTY CYCLE; t , t ≤ 1ns.
R
F
2. V
MEASURED ON TEST EQUIPMENT WITH –3dB BANDWIDTH ≥ 1GHz.
OC(PP)
Figure 20. Driver Common-Mode Output Voltage Measurement
Figure 23. Driver Common-Mode Output Voltage (Steady State)
V
CC
A/Y
S1
S2
R1
1.62kΩ
±1%
V
, V
OR V
Z(O)
,
DE B/Z
A(O) B(O)
V
Y(O)
Figure 21. Maximum Steady-State Output Voltage Measurement
Rev. A | Page 11 of 20
ADN4691E/ADN4693E/ADN4696E/ADN4697E
Data Sheet
DRIVER TIMING MEASUREMENTS
V
CC
DI
0V
C1
1pF
A/Y
B/Z
0.5V
0.5V
tPHL
CC
CC
R1
50Ω
C3
0.5pF
DI
OUT
tPLH
V
SS
C2
1pF
90% V
90% V
SS
SS
V
PH
OUT
0V
0V
10% V
NOTES
1. C1, C2, AND C3 ARE 20% AND INCLUDE PROBE/STRAY
CAPACITANCE LESS THAN 2cm FROM DUT.
2. R1 IS 1%, METAL FILM, SURFACE MOUNT,
LESS THAN 2cm FROM DUT.
10% V
SS
SS
0% V
SS
V
PL
tR
tF
Figure 24. Driver Timing Measurement
NOTES
1. INPUT PULSE GENERATOR: 500kHz; 50% ± 5% DUTY CYCLE; tR
, tF ≤ 1ns.
V
CC
2. MEASURED ON TEST EQUIPMENT WITH –3dB BANDWIDTH ≥ 1GHz.
Figure 27. Driver Propagation, Rise/Fall Times and Voltage Overshoot
C1
1pF
A/Y
B/Z
R1
24.9Ω
C4
0.5pF
DI
OUT
S1
V
CC
R2
24.9Ω
C3
2.5pF
DE
DE
0.5V
tPZL
0.5V
tPLZ
CC
CC
C2
1pF
0V
0V
NOTES
1. C1, C2, C3, AND C4 ARE 20% AND INCLUDE PROBE/STRAY
CAPACITANCE LESS THAN 2cm FROM DUT.
2. R1 AND R2 ARE 1%, METAL FILM, SURFACE MOUNT,
LESS THAN 2cm FROM DUT.
OUT
–0.1V
0.1V
–0.1V
0.1V
(DI = 0V)
~ –0.6V
~ 0.6V
tPZH
tPHZ
Figure 25. Driver Enable/Disable Time
OUT
(DI = V
)
V
CC
CC
0V
INPUT
(CLOCK)
V
/2
V
/2
CC
CC
NOTES
1. INPUT PULSE GENERATOR: 500kHz; 50% ± 5% DUTY CYCLE; tR, tF ≤ 1ns.
2. MEASURED ON TEST EQUIPMENT WITH –3dB BANDWIDTH ≥ 1GHz.
0V
1/f0
Figure 28. Driver Enable/Disable Times
V
CC
OUTPUT
V
– V
OR
– V
A
B
0V
0V
INPUT
(PRBS)
0.5V
0.5V
CC
CC
V
Y
Z
(IDEAL)
0V
1/f0
V
– V
B
A
OR
OUTPUT
V
– V
Y
Z
V
– V
A
B
0V
0V
OUTPUT
0V
0V
OR
– V
V
Y
Z
V
– V
A
B
(ACTUAL )
OR
V
– V
tJ(PP)
tc(n)
Y
Z
tJ(PER) = |tc(n) – 1/f0|
NOTES
NOTES
1. INPUT PULSE GENERATOR: AGILENT 8304A STIMULUS SYSTEM;
200Mbps; 2 – 1PRBS.
1. INPUT PULSE GENERATOR: AGILENT 8304A STIMULUS SYSTEM;
100MHz; 50% ± 1% DUTY CYCLE.
15
2. MEASURED USING TEK TDS6604 WITH TDSJIT3 SOFTWARE.
2. MEASURED USING TEK TDS6604 WITH TDSJIT3 SOFTWARE.
Figure 29. Driver Peak-to-Peak Jitter Characteristics
Figure 26. Driver Period Jitter Characteristics
Rev. A | Page 12 of 20
Data Sheet
ADN4691E/ADN4693E/ADN4696E/ADN4697E
RECEIVER TIMING MEASUREMENTS
A
RO
V
ID
RE
B
V
A
B
C
15pF
L
V
OUT
V
NOTES
1. C IS 20%, CERAMIC, SURFACE MOUNT, AND INCLUDES
L
PROBE/STRAY CAPACITANCE < 2cm FROM DUT.
Figure 30. Receiver Timing Measurement
0V
0V
V
ID
1.4V
A
R
L
499Ω
tRPHL
90%
tRPLH
RO
1.0V
B
RE
V
OH
90%
1.2V
C
15pF
L
V
V
TEST
OUT
RE INPUT
V
0.5V
0.5V
OUT
CC
CC
10%
10%
V
OL
tF
tR
NOTES
1. C IS 20% AND INCLUDES PROBE/STRAY
CAPACITANCE < 2cm FROM DUT.
NOTES
1. INPUT PULSE GENERATOR: 50MHz; 50% ± 5% DUTY CYCLE; t , t ≤ 1ns.
2. MEASURED ON TEST EQUIPMENT WITH –3dB BANDWIDTH ≥ 1GHz.
L
R
F
2. R IS 1% METAL FILM, SURFACE MOUNT, <2cm FROM DUT.
L
Figure 33. Receiver Propagation and Rise/Fall Times
Figure 31. Receiver Enable/Disable Time
V
CC
INPUT
RE INPUT
0.5V
0.5V
(V – V
)
CC
CC
A
B
0V
V
0V
tRPZL
1/f0
tRPLZ
V
CC
OUT
(V
TEST
= V )
CC
0.5V
0.5V
CC
CC
(A = 1V)
V
OH
V
V
+ 0.5V
– 0.5V
OL
V
V
OL
OUTPUT
(IDEAL)
0.5V
0.5V
CC
CC
tRPZH
tRPHZ
OH
V
V
OL
OUT
OH
(V
TEST
(A = 1.4V)
= 0V)
1/f0
0V
V
OH
NOTES
1. INPUT PULSE GENERATOR: 500kHz; 50% ± 5% DUTY CYCLE; tR
,
tF ≤ 1ns.
OUTPUT
(ACTUAL)
0.5V
0.5V
CC
CC
Figure 34. Receiver Enable/Disable Times
V
OL
tc(n)
V
A
tJ(PER) = |tc(n) – 1f0|
INPUT
(PRBS)
NOTES
1. INPUT PULSE GENERATOR: AGILENT 8304A STIMULUS SYSTEM;
100MHz; 50% ± 1% DUTY CYCLE.
V
B
2. MEASURED USING TEK TDS6604 WITH TDSJIT3 SOFTWARE.
V
OH
Figure 32. Receiver Period Jitter Characteristics
OUTPUT
0.5V
0.5V
CC
CC
V
OL
tJ(PP)
NOTES
1. INPUT PULSE GENERATOR: AGILENT 8304A STIMULUS SYSTEM;
15
200Mbps; 2 – 1PRBS.
2. MEASURED USING TEK TDS6604 WITH TDSJIT3 SOFTWARE.
Figure 35. Receiver Peak-to-Peak Jitter Characteristics
Rev. A | Page 13 of 20
ADN4691E/ADN4693E/ADN4696E/ADN4697E
Data Sheet
THEORY OF OPERATION
The ADN4691E/ADN4693E/ADN4696E/ADN4697E are
transceivers for transmitting and receiving multipoint, low
voltage differential signaling (M-LVDS) at high speed (data
rates up to 200 Mbps). Each device has a differential line driver
and a differential line receiver, allowing each device to send and
receive data.
Driver, Half Duplex (ADN4691E/ADN4696E)
Table 10. Transmitting (See Table 9 for Abbreviations)
Inputs
Outputs
Power
Yes
Yes
Yes
Yes
DE
H
H
H
L
DI
H
L
NC
X
X
A
H
L
B
L
H
H
Z
Z
Z
Multipoint LVDS expands on the established LVDS low voltage
differential signaling method by allowing bidirectional commu-
nication between more than two nodes. Up to 32 nodes can be
connected on an M-LVDS bus.
L
Z
Z
Z
Yes
≤1.5 V
NC
X
X
HALF-DUPLEX/FULL-DUPLEX OPERATION
Driver, Full Duplex (ADN4693E/ADN4697E)
Half-duplex operation allows a transceiver to transmit or
receive, but not both at the same time. However, with full-
duplex operation, a transceiver can transmit and receive
simultaneously. The ADN4691E/ADN4696E are half-duplex
devices in which the driver and the receiver share differential
bus terminals. The ADN4693E/ADN4697E are full-duplex
devices that have dedicated driver output and receiver input
pins. Figure 37 and Figure 38 show typical half- and full-duplex
bus topologies, respectively, for M-LVDS.
Table 11. Transmitting (See Table 9 for Abbreviations)
Inputs
Outputs
Power
Yes
Yes
DE
H
H
DI
H
L
Y
H
L
Z
L
H
H
Z
Z
Z
Yes
Yes
Yes
≤1.5 V
H
L
NC
X
NC
X
X
L
Z
Z
Z
THREE-STATE BUS CONNECTION
X
The outputs of the device can be placed in a high impedance
state by disabling the driver or receiver. This allows several
driver outputs to be connected to a single M-LVDS bus. Note
that, on each bus line, only one driver can be enabled at a time,
but many receivers can be enabled at the same time.
Type 1 Receiver (ADN4691E/ADN4693E)
Table 12. Receiving (see Table 9 for Abbreviations)
Inputs
Output
RO
A − B
RE
Power
Yes
The driver can be enabled or disabled using the driver enable
pin (DE). DE enables the driver outputs when taken high; when
taken low, DE puts the driver outputs into a high impedance state.
≥50 mV
L
H
L
I
Yes
≤−50 mV
L
Yes
−50 mV < A − B < 50 mV
L
RE
Similarly, an active low receiver enable pin ( ) controls the
Yes
Yes
Yes
No
NC
X
X
L
I
RE
receiver. Taking
low enables the receiver, whereas taking it
H
NC
X
Z
Z
Z
high puts the receiver outputs into a high impedance state.
X
Truth tables for driver and receiver output states under various
conditions are shown in Table 10, Table 11, Table 12 and
Table 13.
Type 2 Receiver (ADN4696E/ADN4697E)
TRUTH TABLES
Table 13. Receiving (See Table 9 for Abbreviations)
Inputs
Output
Table 9. Truth Table Abbreviations
RE
Power
Yes
Yes
A − B
RO
H
L
Abbreviation
Description
≥150 mV
≤50 mV
L
L
H
L
High level
Low level
Yes
Yes
Yes
Yes
50 mV < A − B < 150 mV
NC
X
X
X
L
L
H
NC
X
I
L
Z
Z
Z
X
I
Z
Don’t care
Indeterminate
High impedance (off)
Disconnected
NC
No
Rev. A | Page 14 of 20
Data Sheet
ADN4691E/ADN4693E/ADN4696E/ADN4697E
Type 2 receivers (ADN4696E/ADN4697E) have an open circuit
and bus-idle fail-safe. The input threshold is offset by 100 mV so
that a logic low is present on the receiver output when the bus is
idle or when the receiver inputs are open.
GLITCH-FREE POWER-UP/POWER-DOWN
To minimize disruption to the bus when adding nodes, the
M-LVDS outputs of the device are kept glitch-free when the
device is powering up or down. This feature allows insertion of
devices onto a live M-LVDS bus because the bus outputs are not
switched on before the device is fully powered. In addition, all
outputs are placed in a high impedance state when the device is
powered off.
The different receiver thresholds for the two receiver types are
illustrated in Figure 36. See Table 12 and Table 13 for receiver
output states under various conditions.
TYPE 1 RECEIVER
TYPE 2 RECEIVER
OUTPUT
OUTPUT
FAULT CONDITIONS
The ADN4691E/ADN4693E/ADN4696E/ADN4697E contain
short-circuit current protection that protects the part under
fault conditions in the case of short circuits on the bus. This
protection limits the current in a fault condition to 24 mA at
the transmitter outputs for short-circuit faults between −1 V
and +3.4 V. Any network fault must be cleared to avoid data
transmission errors and to ensure reliable operation of the data
network and any devices that are connected to the network.
0.25
0.15
LOGIC 1
LOGIC 1
UNDEFINED
0.05
0
UNDEFINED
LOGIC 0
–0.05
LOGIC 0
–0.15
RECEIVER INPUT THRESHOLDS/FAIL-SAFE
Two receiver types are available, both of which incorporate
protection against short circuits.
Figure 36. Input Threshold Voltages
The Type 1 receivers of the ADN4691E/ADN4693E incorporate
25 mV of hysteresis. This ensures that slow-changing signals or
a loss of input does not result in oscillation of the receiver output.
Type 1 receiver thresholds are 50 mV; therefore, the state of the
receiver output is indeterminate if the differential between A and
B is about 0 V. This state occurs if the bus is idle (approximately 0 V
on both A and B), with no drivers enabled on the attached nodes.
Rev. A | Page 15 of 20
ADN4691E/ADN4693E/ADN4696E/ADN4697E
Data Sheet
APPLICATIONS INFORMATION
M-LVDS extends the low power, high speed, differential
signaling of LVDS (low voltage differential signaling) to
multipoint systems where multiple nodes are connected over
short distances in a bus topology network.
The communication line is typically terminated at both ends
by resistors (RT), the value of which is chosen to match the
characteristic impedance of the medium (typically 100 ꢀ).
For half-duplex multipoint applications such as the one shown
in Figure 37, only one driver can be enabled at any time. Full-
duplex nodes allow a master-slave topology as shown in Figure 38.
In this configuration, a master node can concurrently send and
receive data to/from slave nodes. At any time, only one slave
node can have its driver enabled to concurrently transmit data
back to the master node.
With M-LVDS, a transmitting node drives a differential signal
across a transmission medium such as a twisted pair cable. The
transmitted differential signal allows other receiving nodes that
are connected along the bus to detect a differential voltage that
can then be converted back into a single-ended logic signal by
the receiver.
R
R
T
T
A
B
A
B
A
B
A
B
ADN4696E
ADN4696E
ADN4696E
ADN4696E
R
R
R
R
D
D
D
D
RO RE DE DI
RO RE DE DI
RO RE DE DI
RO RE DE DI
NOTES
1. MAXIMUM NUMBER OF NODES: 32.
2. R IS EQUAL TO THE CHARACTERISTIC IMPEDANCE OF THE CABLE USED.
T
Figure 37. ADN4696E Typical Half-Duplex M-LVDS Network (Type 2 Receivers with Threshold Offset for Bus-Idle Fail-Safe)
R
R
R
R
T
T
T
T
A
B
R
Z
Y
A
B
R
Z
Y
A
B
R
Z
Y
A B Z Y
MASTER
SLAVE
SLAVE
SLAVE
ADN4697E
ADN4697E
ADN4697E
ADN4697E
R
D
D
D
D
RO RE DE DI
RO RE DE DI
RO RE DE DI
RO RE DE DI
NOTES
1. MAXIMUM NUMBER OF NODES: 32.
2. R IS EQUAL TO THE CHARACTERISTIC IMPEDANCE OF THE CABLE USED.
T
Figure 38. ADN4697E Typical Full-Duplex M-LVDS Master-Slave Network (Type 2 Receivers with Threshold Offset for Bus-Idle Fail-Safe)
Rev. A | Page 16 of 20
Data Sheet
ADN4691E/ADN4693E/ADN4696E/ADN4697E
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 39. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
8.75 (0.3445)
8.55 (0.3366)
8
7
14
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
0.50 (0.0197)
0.25 (0.0098)
45°
BSC
1.75 (0.0689)
1.35 (0.0531)
0.25 (0.0098)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 40. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
ADN4691EBRZ
ADN4691EBRZ-RL7
ADN4693EBRZ
ADN4693EBRZ-RL7
ADN4696EBRZ
ADN4696EBRZ-RL7
ADN4697EBRZ
ADN4697EBRZ-RL7
EVAL-ADN469xEHDEBZ
EVAL-ADN469xEFDEBZ
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Lead Standard Small Outline Package (SOIC_N)
8-Lead Standard Small Outline Package (SOIC_N)
14-Lead Standard Small Outline Package (SOIC_N)
14-Lead Standard Small Outline Package (SOIC_N)
8-Lead Standard Small Outline Package (SOIC_N)
8-Lead Standard Small Outline Package (SOIC_N)
14-Lead Standard Small Outline Package (SOIC_N)
14-Lead Standard Small Outline Package (SOIC_N)
Evaluation Board for Half-Duplex (ADN4691E/ADN4696E)
Evaluation Board for Full-Duplex (ADN4693E/ADN4697E)
R-8
R-8
R-14
R-14
R-8
R-8
R-14
R-14
1 Z = RoHS Compliant Part.
Rev. A | Page 17 of 20
ADN4691E/ADN4693E/ADN4696E/ADN4697E
NOTES
Data Sheet
Rev. A | Page 18 of 20
Data Sheet
NOTES
ADN4691E/ADN4693E/ADN4696E/ADN4697E
Rev. A | Page 19 of 20
ADN4691E/ADN4693E/ADN4696E/ADN4697E
NOTES
Data Sheet
©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10355-0-3/12(A)
Rev. A | Page 20 of 20
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