ADP1147 [ADI]
High Efficiency Step-Down Switching Regulator Controllers; 高效率降压型开关稳压控制器
| 型号： | ADP1147 |
| 厂家： | 
ADI |
| 描述： | High Efficiency Step-Down Switching Regulator Controllers |
| 文件： | 总12页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Efficiency Step-Down
Switching Regulator Controllers
a
ADP1147-3.3/ADP1147-5
FEATURES
FUNCTIO NAL BLO CK D IAGRAM
Greater Than 95% Efficiency
Current Mode Sw itching Architecture Provides
Superior Load and Line Transient Response
Wide Input Voltage Range 3.5 V* to 16 V
User Defined Current Lim it
Short Circuit Protection
Shutdow n Pin
Low Dropout Voltage
Low Standby Current 160 A typ
Low Cost
Available in 8-Lead PDIP or 8-Lead SOIC
V
P-DRIVE GROUND
SENSE(+)
SENSE(–)
IN
V
ADP1147
2
R
B
S
Q
1
SLEEP
Q
R
S
10mV to 150mV
5pF
C
V
OS
V
V
TH1
TH2
S
13k⍀
G
T
100k⍀
1.25V
APPLICATIONS
Portable Com puters
Modem s
V
OFF-TIME
CONTROL
REFERENCE
IN
SENSE(–)
Cellular Telephones
Portable Equipm ent
GPS System s
C
I
SHUTDOWN
T
TH
A very low dropout voltage with excellent output regulation can
be obtained by minimizing the dc resistance of the Inductor, the
RSENSE resistor, and the RDS(ON) of the P-MOSFET . T he power
savings mode conserves power by reducing switching losses at
lower output currents. When the output load current falls below
the minimum required for the continuous mode the ADP1147
will automatically switch to the power savings mode. It will remain
in this mode until the inductor requires additional current or the
sleep mode is entered. In sleep mode with no load the standby
power consumption of the device is reduced to 2.0 mW typical
at VIN = 10 V.
Handheld Instrum ents
GENERAL D ESCRIP TIO N
T he ADP1147 is part of a family of High Efficiency Step-Down
Switching Regulators. T hese regulators offer superior load and
line transient response, a user defined current limit and an
automatic power savings mode. T he automatic power savings
mode is used to maintain efficiency at lower output currents.
T he ADP1147 incorporates a constant off-time, current mode
switching architecture to drive an external P-channel MOSFET
at frequencies up to 250 kHz. Constant off-time switching gen-
erates a constant ripple current in the external inductor. T his
results in a wider input voltage operating range of 3.5 V* to
16 V, and a less complex circuit design.
For designs requiring even greater efficiencies refer to the
ADP1148 data sheet.
*3.5 volt operation is for the ADP1147-3.3.
100
V
= 6 VOLTS
IN
L
*
R
SENSE**
0.05⍀
95
90
85
80
75
70
65
60
P-CHANNEL
IRF7204
50H
V
(5.2V TO 12V)
+
IN
V
OUT
+
5V/2A
C
D1
30BQ040
IN
1F
V
= 10 VOLTS
+
IN
C
100F
OUT
390F
V
IN
0V = NORMAL
1.5V = SHUTDOWN
P-DRIVE
ADP1147
SHUTDOWN
C
C
R
C
3300pF
1k⍀
I
TH
SENSE(+)
SENSE(–)
1000pF
C
T
C
T
GND
470pF
*COILTRONICS CTX 50–2MP
**KRL SL-1-C1-0R050J
1
10
100
LOAD CURRENT – mA
1k
10k
SHUTDOWN
Figure 1. High Efficiency Step-Down Converter
(Typical Application)
Figure 2. ADP1147-5 Typical Efficiency, Figure 1 Circuit
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 781/ 329-4700
Fax: 781/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1998
ADP1147-3.3/ADP1147-5–SPECIFICATIONS
1
(0؇C ≤ T ≤ +70؇C , V = 10 V, VSHUTDOWN = 0 V unless otherwise noted)
ELECTRICAL CHARACTERISTICS
A
IN
AD P 1147
Typ Max
P aram eter
Conditions
VS
Min
Units
REGULAT ED OUT PUT VOLT AGE
ADP1147-3-3
ADP1147-5
VIN = 9 V
ILOAD = 700 mA
ILOAD = 700 mA
VOUT
3.23 3.33 3.43
4.90 5.05 5.20
V
V
OUT PUT VOLT AGE LINE REGULAT ION
TA = +25°C
VIN = 7 V to 12 V,
ILOAD = 50 mA
∆VOUT
∆VOUT
IQ
–40
0
+40
mV
OUT PUT VOLT AGE LOAD REGULAT ION
ADP1147-3.3
ADP1147-5
5 mA < ILOAD < 2 A
5 mA < ILOAD < 2 A
TA = +25°C, ILOAD = 0 A
40
60
50
65
100
mV
mV
mV p-p
Sleep Mode Output Ripple
INPUT DC SUPPLY CURRENT2
Normal Mode
TA = +25°C
4 V < VIN < 16 V
1.6
160 250
160 250
2.3
mA
µA
µA
µA
Sleep Mode (ADP1147-3.3)
Sleep Mode (ADP1147-5)
Shutdown
4 V < VIN < 16 V
4 V < VIN < 16 V
VSHUTDOWN = 2.1 V, 4 V < VIN < 16 V
10
22
CURRENT SENSE THRESHOLD VOLTAGE
ADP1147-3.3
+
VSENSE(–) = VOUT 100 mV (Forced
TA = +25°C
)
)
10
mV
mV
VSENSE(–) = VOUT– 100 mV (Forced
)
V5–V4
120
150 170
+
ADP1147-5
VSENSE(–) = VOUT 100 mV (Forced
TA = +25°C
10
mV
mV
VSENSE(–) = VOUT– 100 mV (Forced
)
120
0.6
150 170
SHUTDOWN PIN THRESHOLD
TA = +25°C
V6
I6
0.8
1.2
2
5
V
SHUTDOWN PIN INPUT CURRENT
0 V < VSHUTDOWN < 8 V, VIN = 16 V
µA
TA = +25°C
CT PIN DISCHARGE CURRENT
TA = +25°C, VOUT in Regulation,
VSENSE(–) = VOUT, VOUT = 0 V
50
4
70
2
90
10
µA
µA
I2
OFF-TIME
CT = 390 pF, ILOAD = 700 mA
tOFF
5
6
µs
DRIVER OUTPUT TRANSITION TIMES
TA = +25°C
CL = 3000 pF (Pin 8) VIN = 6 V
tr, tf
100 200
ns
NOTES
1All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
2Dynamic supply current is higher due to the gate charge being delivered at the switching frequency.
Specifications subject to change without notice.
ABSO LUTE MAXIMUM RATINGS
O RD ERING GUID E
Input Supply Voltage (Pin 1) . . . . . . . . . . . . . . 16 V to –0.3 V
Continuous Output Current (Pin 8) . . . . . . . . . . . . . . 50 mA
Sense Voltages (Pins 4, 5) . . . . . . . . . . . . . . . . 10 V to –0.3 V
Operating Ambient T emperature Range . . . . . 0°C to +70°C
Extended Commercial T emperature Range . . –40°C to +85°C
Junction T emperature* . . . . . . . . . . . . . . . . . . . . . . . +150°C
Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C
Lead T emperature (Soldering, 10 sec) . . . . . . . . . . . +300°C
O utput
Voltage
P ackage
D escription
P ackage
O ption
Model
ADP1147AN-3.3
ADP1147AR-3.3
ADP1147AN-5
ADP1147AR-5
3.3 V
3.3 V
5 V
Plastic DIP
SOIC
Plastic DIP
SOIC
N-8
SO-8
N-8
5 V
SO-8
*T J is calculated from the ambient temperature, T A, and power dissipation, PD
,
according to the following formulas: ADP1147AN-3.3, ADP1147AN-5: T J = T A
+
(PD × 110°C/W). ADP1147AR-3.3, ADP1147AR-5: T J = TA+(PD × 150°C/W).
–2–
REV. 0
ADP1147-3.3/ADP1147-5
1
(–40؇C ≤ T A ≤ +85؇C , V = 10 V, unless otherwise noted)
ELECTRICAL CHARACTERISTICS
IN
AD P 1147
Typ Max
P aram eter
Conditions
VS
Min
Units
REGULAT ED OUT PUT VOLT AGE
ADP1147-3.3
ADP1147-5
VIN = 9 V
ILOAD = 700 mA
ILOAD = 700 mA
VOUT
3.17 3.33 3.4
4.85 5.05 5.2
V
V
INPUT DC SUPPLY CURRENT
Normal Mode
Sleep Mode (ADP1147-3.3)
Sleep Mode (ADP1147-5)
Shutdown
4 V < VIN < 16 V
4 V < VIN < 16 V
5 V < VIN < 16 V
VSHUTDOWN = 2.1 V, 4 V < VIN < 16 V
IQ
1.6
160 280
160 280
2.6
mA
µA
µA
µA
10
28
CURRENT SENSE THRESHOLD VOLTAGE
ADP1147-3.3
+
VSENSE(–) = VOUT 100 mV (Forced)
V5–V4
TA = +25°C
25
mV
mV
VSENSE(–) = VOUT– 100 mV (Forced
)
)
120
120
150 175
+
ADP1147-5
VSENSE(–) = VOUT 100 mV (Forced
TA = +25°C
25
mV
mV
VSENSE(–) = VOUT– 100 mV (Forced
)
150 175
SHUTDOWN PIN THRESHOLD
V6
0.55 0.8
3.8
2
6
V
OFF-TIME
CT = 390 pF, ILOAD = 700 mA
tOFF
5
µs
NOTES
1All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
Specifications subject to change without notice.
P IN FUNCTIO N D ESCRIP TIO NS
P in
No.
Mnem onic
Function
1
2
VIN
CT
Input Voltage.
External Capacitor Connection. This capacitor sets the operating frequency of the device. The frequency is
also dependent on the input voltage level.
3
4
ITH
Error Amplifier Decoupling Pin. Pin 3 voltage level causes the comparator current threshold to increase.
SENSE(–)
This connects to internal resistive divider, which senses the output voltage. Pin 4 is also the (–) input for the
current comparator.
5
6
7
8
SENSE(+)
SHUTDOWN
GND
This provides the + input to the current comparator. The offset between Pins 4 and 5 together with RSENSE
establish the current trip threshold.
When this pin is pulled high, it keeps the MOSFET turned off. When the pin is pulled to ground, the
ADP1147 functions normally. This pin cannot be left floating.
Independent ground lines must be connected separately to (a) the negative pin of COUT and (b) the cathode
of the Schottky diode and the negative terminal of CIN
.
P-DRIVE
Provides high current drive for the MOSFET. Voltage swing is from V to ground at this pin.
IN
P IN CO NFIGURATIO NS
8-Lead P lastic D IP (N-8)
8-Lead SO IC (SO -8)
P-DRIVE
GND
V
1
2
3
4
8
7
6
5
V
I
P-DRIVE
GND
IN
1
2
3
4
8
7
6
5
IN
ADP1147
TOP VIEW
(Not to Scale)
C
T
ADP1147
C
T
TOP VIEW
I
(Not to Scale)
SHUTDOWN
SENSE+
TH
SHUTDOWN
SENSE+
TH
SENSE–
T
SENSE–
= 125؇C, = 110؇C/W
T
= 125؇C, = 150؇C/W
JA
JMAX
JA
JMAX
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP1147 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
–Performance Characteristics
ADP1147-3.3/ADP1147-5
1000
800
1000
200
L = 50H
V
= V
= +5V
SENSE
OUT
R
= 0.02⍀
SENSE
800
600
L = 25H
= 0.02⍀
150
100
R
SENSE
600
400
200
0
V
= +12V
IN
400
200
0
L = 50H
= 0.05⍀
R
50
0
V
= +10V
SENSE
IN
V
= +7V
IN
0
100
200
300
0
1
2
3
4
5
0
1
2
3
4
5
(V – V
) VOLTAGE – Volts
FREQUENCY – kHz
MAXIMUM OUTPUT CURRENT – Amps
IN
OUT
Figure 3. Selecting RSENSE vs.
Maxim um Output Current
Figure 4. Operating Frequency vs.
Tim ing Capacitor
Figure 5. Selecting Minim um Output
Capacitor vs. (VIN – VOUT) and Inductor
5.11
100
100
95
FIGURE 1 CIRCUIT
FIGURE 1 CIRCUIT
5.10
2
I R
GATE CHARGE
95
1 AMP
5.09
ADP1147 I
Q
100mA
5.08
90
0.1 AMP
85
5.07
90
SCHOTTKY
DIODE
300mA
5.06
80
75
70
5.05
85
80
5.04
1 AMP
5.03
4
8
12
16
5
8
11
14
17
20
10m
30m
0.1
0.3
– Amps
1
3
INPUT VOLTAGE – V
INPUT VOLTAGE – Volts
I
OUT
Figure 6. Typical Efficiency Losses
Figure 7. Efficiency vs. Input Voltage
Figure 8. ADP1147-5 Output Voltage
vs. Input Voltage
5.11
1.6
1.4
40
35
FIGURE 1 CIRCUIT
5.10
V
= +2V
SHUTDOWN
ACTIVE MODE
1.2
5.09
5.08
30
25
20
15
10
5
1.0
0.8
0.6
0.4
V
= 6 VOLTS
IN
5.07
5.06
5.05
5.04
V
= 12 VOLTS
IN
SLEEP MODE
0.2
5.03
5.02
0
0
0
400
800
1200
1600
2000
4
6
8
10
12
14
16 18 20
4
6
8
10 12 14
16 18
20
LOAD CURRENT – mA
INPUT VOLTAGE – Volts
INPUT VOLTAGE – Volts
Figure 9. Load Regulation
Figure 10. DC Supply Current
Figure 11. Supply Current in
Shutdown
–4–
REV. 0
ADP1147-3.3/ADP1147-5
1.8
1.6
1.4
80
70
60
50
30
25
20
0°C
+25°C
1.2
1.0
0.8
0.6
Q
+ Q = 100nC
P
N
+5V
40
15
10
5
+70°C
30
20
0.4
0.2
0
+3.3V
10
Q
+ Q = 50nC
P
N
0
0
20
50 80 110 140 170 200 230 260
OPERATING FREQUENCY – kHz
1
2
4
6
8
) – Volts
10
12
0.3 0.5
1
1.5
2
2.5
3
3.3 3.5
4
4.5
5
(V – V
OUTPUT VOLTAGE – Volts
IN
OUT
Figure 12. Operating Frequency vs.
Figure 13. Gate Charge Supply
Current
Figure 14. Off-Tim e vs. VOUT
(VIN–VOUT
)
155
150
145
140
135
95
3.35
100mA
MAXIMUM THRESHOLD
3.34
3.33
3.32
90
1 AMP
300mA
85
3.31
3.30
0.1 AMP
80
1 AMP
3.29
3.28
3.27
75
70
130
0
5
8
11
14
17
20
25
70
85
100
4
8
12
16
INPUT VOLTAGE – Volts
TEMPERATURE – ؇C
INPUT VOLTAGE – Volts
Figure 15. Current Sense Threshold
Voltage
Figure 16. Efficiency vs. Input
Voltage at VO = 3.3 V; Figure 1
Circuit with ADP1147-3.3
Figure 17. Output Voltage vs. Input
Voltage (VO = 3.3 V); Figure 1 Circuit
with ADP1147-3.3
3.36
3.34
3.32
3.30
V
= 6 VOLTS
IN
3.28
3.26
3.24
3.22
3.20
3.18
V
= 12 VOLTS
IN
0
400
800
1200
1600
2000
LOAD CURRENT – mA
Figure 18. Load Regulation (VO = 3.3 V);
Figure 1 Circuit with ADP1147-3.3
REV. 0
–5–
ADP1147-3.3/ADP1147-5
V
3.3V
0V
IN
4V–14V
(a) Continuous Mode Operation
C
IRF7204
IN
100F
25V
1F
D1
30BQ040
3.3V
0V
L*
50H
ADP1147-3.3
IN
V
P-DRIVE
C
(b) Power Saving Mode
Figure 19. CT Waveform s
T
620pF
C
I
GND
T
3300pF
SHUTDOWN
1nF
TH
SHUTDOWN
C
R
OUT
C
R
L
P-CHANNEL
SENSE
220F
6.3V
X2
1k⍀
SENSE(–) SENSE(+)
V
OUT
V
C
R
IN
D1
IN
SENSE**
C
OUT
50m⍀
1F
V
OUT
3.3V/2A
GROUND
PLANE
*COILTRONICS
CTX50-4
**KRL SL-1-C1-0R050J
ADP1147-3.3
C
T
V
P-DRIVE
IN
Figure 22. 3.3 V/2 A Regulator
390pF
C
I
GROUND
SHUTDOWN
SENSE(+)
T
3300pF
100
95
90
85
80
75
70
65
60
SHUTDOWN
TH
SENSE(–)
1k⍀
V
= 6 VOLTS
IN
1000pF
V
= 10 VOLTS
IN
Figure 20. Circuit Diagram Indicating the Recom m ended
Ground Plane Schem e for PCB Layout
V
IN
6V TO 14V
D1
1N4148
1
10
100
LOAD CURRENT – mA
1K
10K
Q1
2N3906
R7
220⍀
C8
1F
Figure 23. Efficiency vs. Load Current at VO = 3.3 V;
Figure 22 Circuit
R5
20k⍀
+
Q2
2N2222
R6
470⍀
C2-C4
220F/16V
OS-CON
Q4
D3
1N4148
IRF7403
D2
30BQ040
C1
1F
+
U1
ADP1147-5
L1
50H
Q3
VN2222LL
V
P-DRV
8
7
6
5
1
2
IN
C
I
GND
SHD
T
C5
3
4
TH
470pF
R1
1k⍀
C6
SNS+
SNS–
R3
100⍀
C9–C11
220F
؋
10V OS-CON
3.3nF
+
R2
0.02⍀
C7
2.2nF
R4
100⍀
V
5V/3A
OUT
Figure 21. 5 V/3 A Regulator Using N-Channel Device
–6–
REV. 0
ADP1147-3.3/ADP1147-5
AP P LICATIO NS
D eter m ining the O utput Cur r ent and the Value for R SENSE
T he value selected for RSENSE is determined by the required
output current. T he current comparator C has a threshold volt-
age range of 10 mV/RSENSE to 150 mV/RSENSE maximum. T his
threshold sets the peak current in the external inductor and
yields a maximum output current of:
T he ADP1147 family of regulators incorporate a current mode,
constant off-time architecture to switch an external P-channel
MOSFET . T he external MOSFET can be switched at frequen-
cies up to 250 kHz. T he switching frequency of the device is
determined by the value selected for capacitor CT .
A regulated output voltage is maintained by the feedback volt-
age at the SENSE(–) pin. T he SENSE(–) pin is connected to an
internal voltage divider. T he voltage from this internal divider is
fed to comparator V, and gain block G. It is then compared to
an internal 1.25 volt reference.
IRIPPLE
p p
−
IMAX = IPEAK
–
2
T he resistance values for RSENSE can range from 20 mΩ to
200 mΩ. A graph for selecting RSENSE vs. the maximum out-
put current is shown in Figure 3.
T he ADP1147 is capable of maintaining high levels of efficiency
by automatically switching between the power saving and con-
tinuous modes. T he internal R-S flip-flop # 2 controls the device
in the power saving mode, and gain block G assumes control
when the device is in the continuous mode of operation.
T he value of RSENSE can be determined by using the following
equation:
RSENSE (in mΩ) = 100/IMAX
T his equation allows for a design margin due to component
variations.
During the P-MOSFET on time, the voltage developed across
RSENSE is monitored by the SENSE(–) and SENSE(+) pins of
the device. When this voltage reaches the threshold level of
comparator C the output trips, switching the P drive to VIN, and
turns the external P-MOSFET off. At this point capacitor CT
begins to discharge at a rate that is determined by the off-time
controller. T he CT discharge current is proportional to the
voltage measured at the SENSE(–) pin. When the voltage on
cap CT decays to the threshold voltage (VT H 1), comparator T
switches and sets R-S flip-flop # 1. T his forces the P-drive out-
put low, and turns on the P-MOSFET . T he sequence is then
repeated. As the load current is increased, the output voltage
starts to drop. T his causes the gain circuit to raise the threshold
of the current comparator, and the load current is now tracked.
T he following equations are used to approximate the trip point
for the power savings mode and the peak short circuit current.
IPOWER SAVINGS ~ 5 mV/RSENSE + VO tOFF/2L
ISC(PK) = 150 mV/RSENSE
T he ADP1147 automatically increases the tOFF time when a
short circuit condition is encountered. T his allows sufficient
time for the inductor to decay between switching cycles. Due to
the resulting inductor ripple current the average short circuit
current ISC(AVG) is reduced to approximately IMAX
.
D eter m ining the O per ating Fr equency and Selecting Values
for CT and L
T he ADP1147 incorporates a constant off-time architecture to
switch an external P-MOSFET . T he off-time (tOFF) is deter-
mined by the value of the external timing cap CT . When the
P-MOSFET is turned on the voltage across CT is charged to
approximately 3.3 volts. During the switch off-time the voltage
on CT is discharged by a current that is proportional to the
voltage level of VOUT . T he voltage across CT is representative of
the current in the inductor, which decays at a rate that is pro-
portional to VOUT . Due to this relationship the value of the
inductor must track the value selected for CT .
When load currents are low, comparator B sets the R-S flip-flop
# 2 and asserts the power savings mode of operation. Compara-
tor B monitors the voltage developed across RSENSE. As the load
current decreases to 50% of the designed inductor ripple cur-
rent, the voltage reverses polarity. T his reversal causes compara-
tor B to trip, setting the Q-bar output of R-S flip-flop # 2 to a
logic zero, and interrupts the cycle by cycle operation of the
output. The output storage capacitors are then slowly discharged
by the load. When the output cap voltage decays to the VOS level
of comparator V, it resets flip-flop # 2, and the normal cycle by
cycle mode of operation resumes. If load currents are extremely
small, the time it takes for flip-flop # 2 to reset increases. During
the extended wait for reset period, capacitor CT will discharge
below the value of VT H2 causing comparator S to trip. T his
forces the internal sleep bar low and the device enters the sleep
mode. A significant amount of the IC is disabled during the
sleep mode, reducing the ground current from 1.6 mA to
160 µA, typical. In sleep mode the P-MOSFET is turned off
until additional inductor current is required. T he sleep mode is
terminated when flip-flop # 2 is reset.
T he following equation is used to determine the desired con-
tinuous mode operating frequency:
VOUT +VD
1−
VIN +VD
CT =
1. 3 × 104 × f
VD = the voltage drop across the Schottky diode.
T he graph in Figure 4 can be used to help determine the capaci-
tance value of CT vs. the operating frequency and input voltage.
T he P-MOSFET gate charge losses increase with the operating
frequency and results in lower efficiency (see the Efficiency
section).
Due to the constant off-time architecture, the input voltage has
an effect on the device switching frequency. T o limit the effects
of this variation in frequency the discharge current is increased
as the device approaches the dropout voltage of VIN +1.5 V. In
the dropout mode the P-MOSFET is constantly turned on.
REV. 0
–7–
ADP1147-3.3/ADP1147-5
T he formula used to calculate the continuous operating fre-
quency is:
Using a ferrite cores in a design can produce very low core
losses, allowing the designer to focus on minimizing copper loss
and core saturation problems. Ferrite cores exhibit a condition
known as “Hard Saturation,” which results in an abrupt collapse
of the inductance when the peak design current is exceeded.
T his causes the inductor ripple current to rise sharply, the out-
put ripple voltage to increase and the power savings mode of
operation to be erroneously activated. T o prevent this from
occurring the core should never be allowed to saturate.
VOUT +VD
1−
VIN +VD
f =
tOFF
VREG
tOFF =1. 3 × 104 ×CT ×
VOUT
VREG is the value of the desired output voltage. VOUT is the ac-
Molypermalloy (from Magnetics, Inc.) is a very good, low loss
core material for a toroids, but is more expensive than a ferrite
core. A reasonable compromise between price and performance,
from the same manufacturer is Kool Mu. T oroidal cores are
extremely desirable where efficient use of available space and
several layers of wire are required. T hey are available in various
surface mount configurations from Coiltronics Inc. and other
companies.
tual measured value of the output voltage. When in regulation
VREG/VOUT is equal to 1. The switching frequency of the ADP1147
decreases as the input voltage decreases. T he ADP1147 will
reduce the tOFF time by increasing the discharge current in ca-
pacitor CT if the input to output voltage differential falls below
1.5 volts. T his is to eliminate the possible occurrence of audible
switching prior to dropout.
Now that the operating frequency has been determined and the
value selected for CT , the required inductance for inductor L
can be computed. T he inductor L should be chosen so it will
generate no more than 25 mV/RSENSE of peak-to-peak inductor
ripple current.
P ower MO SFET Selection and Consider ations
T he ADP1147 requires the use of an external P-channel
MOSFET . T he major parameters to be considered when select-
ing the power MOSFET are the threshold voltage VGS(T H) and
the on resistance of the device RDS(ON)
.
T he following equation is used to determine the required value
for inductor L:
T he minimum input voltage determines if the design requires a
logic level or a standard threshold MOSFET . In applications
where the input voltage is > 8 volts, a standard threshold
MOSFET with a VGS(T H) of < 4 volts can be used. In designs
where VIN is < 8 volts, a logic level MOSFET with a VGS(T H) of
< 2.5 volts is recommended. Note: If a logic level MOSFET
is selected, the supply voltage to the ADP1147 must not
exceed the absolute maximum for the VGS of the MOSFET
(e.g., < ±8 volts for IRF7304).
25 mV (VOUT +VD ) ×tOFF
=
or
RSENSE
LMIN
(VOUT +VD ) ×tOFF × RSENSE
25 mV
LMIN
=
T he RDS(ON) requirement for the selected power MOSFET is
determined by the maximum output current (IMAX). An as-
sumption is made that when the ADP1147 is operating in the
continuous mode, either the Schottky Diode or the MOSFET
are always conducting the average load current. T he following
formulas are used to determine the duty cycle of each of the
components.
Substituting for tOFF above gives the minimum required induc-
tor value of:
LMIN = 5.1 × 105× RSENSE × CT × VREG
T he ESR requirements for the output storage capacitor can be
relaxed by increasing the inductor value, but efficiency due to
copper losses will be reduced. Conversely, the use of too low an
inductance may allow the inductor current to become discon-
tinuous, causing the device to enter the power savings mode
prematurely. As a result of this the power savings threshold is
lowered and the efficiency at lower current levels is severely
reduced.
VOUT +VD
P
−
Channel MOSFET Duty Cycle =
VIN +VD
VIN –VD
Schottky Diode Duty Cycle =
VIN +VD
Inductor Cor e Consider ations
Once the Duty Cycle is known, the RDS(ON) requirement for the
Power MOSFET can be determined by:
Now that the minimum inductance value for L has been deter-
mined, the inductor core selection can be made. High efficiency
converters generally cannot afford the core losses found in low
cost powdered iron cores. T his forces the use of a more expen-
sive ferrite, molypermalloy, or Kool Mu® cores. T he typical
efficiency in Figure 1 reflects the use of a molypermalloy core.
T he cost of the inductor can be cut in half by Using a Kool Mu
core type CT X 50-4 by Coiltronics, but the efficiency will be
approximately 1%–2% less. T he actual core losses are not de-
pendent on the size of the core, but on the amount of induc-
tance. An increase in inductance will yield a decrease in the
amount of core loss. Although this appears to be desirable, more
inductance requires more turns of wire with added resistance
and greater copper losses.
(VIN +VD ) × PP
RDS
=
(ON )
2 ×(1+δP )
(VOUT +VD ) × IMAX
where PP is the max allowable power dissipation and where δP is
the temperature dependency of RDS(ON) for the MOSFET . Effi-
ciency and thermal requirements will determine the value of PP,
(refer to Efficiency section). MOSFET S usually specify the 1+ δ
as a normalized RDS(ON ) vs. temperature trace, and δ can be
approximated to 0.007/°C for most low voltage MOSFET s.
O utput D iode Consider ations
When selecting the output diode careful consideration should be
given to peak current and average power dissipation so the
maximum specifications for the diode are not exceeded.
Kool Mu is a registered trademark of Magnetics, Inc.
–8–
REV. 0
ADP1147-3.3/ADP1147-5
T he Schottky diode is in conduction during the MOSFET off-
time. A short circuit of VOUT = 0 is the most demanding situa-
tion on for the diode. During this time it must be capable of
delivering ISC(PK) for duty cycles approaching 100%. T he equa-
tion below is used to calculate the average current conducted by
the diode under normal load conditions.
Chemicon, Nichicon and Sprague are three manufacturers of
high grade capacitors. Sprague offers a capacitor that uses an
OS-CON semiconductor dielectric. T his style capacitor pro-
vides the lowest amount of ESR for its size, but at a higher cost.
Most capacitors that meet the ESR requirements for IP-P ripple
will usually meet or exceed the rms current requirements. The
specifications for the selected capacitor should be consulted.
VIN –VOUT
Surface mount applications may require the use of multiple
capacitors in parallel to meet the ESR or rms current require-
ments. If dry tantalum capacitors are used it is critical that they
be surge tested and recommended by the manufacturer for use
in switching power supplies such as T ype 593D from Sprague.
AVX offers the T PS series of capacitors with various heights
from 2 mm to 4 mm. T he manufacturer should be consulted
for the latest information, specifications and recommendations
concerning specific capacitors. When operating with low supply
voltages, a minimum output capacitance will be required to
prevent the device from operating in a low frequency mode (see
Figure 5). T he output ripple also increases at low frequencies if
COUT is too small.
ID1
=
× ILOAD
VIN +VD
T o guard against increased power dissipation due to undesired
ringing, it is extremely important to adhere to the following:
1. Use proper grounding techniques.
2. Keep all track lengths as short as possible, especially connec-
tions made to the diode (refer to PCB Layout Considerations
section).
T he allowable forward voltage drop of the diode is determined
by the maximum short circuit current and power dissipation.
T he equation below is used to calculate VF:
VF = PD/ISC(PK)
Tr ansient Response
where PD is the maximum allowable power dissipation and is
determined by the system efficiency and thermal requirements
(refer to Efficiency Section).
T he response of the regulator loop can be verified by monitoring
the transient load response. Several cycles may be required for a
switching regulator circuit to respond to a step change in the dc
load current (resistive load). When a step in the load current
takes place a change in VOUT occurs. T he amount of the change
in VOUT is equal to the delta of ILOAD × ESR of COUT . T he delta
of ILOAD charges or discharges the output voltage on capacitor
CIN Consider ations
During the continuous mode of operation the current drawn
from the source is a square wave with a duty cycle equal to
VOUT /VIN. T o reduce or prevent large voltage transients an input
capacitor with a low ESR value and capable of handling the
maximum rms current should be selected. T he formula below
is used to determine the required maximum rms capacitor
current:
COUT . T his continues until the regulator loop responds to the
change in load and is able to restore VOUT to its original value.
VOUT should be monitored during the step change in load for
overshoot, undershoot or ringing, which may indicate a stability
problem. T he circuit shown in Figure 1 contains external com-
ponents that should provide sufficient compensation for most
applications. T he most demanding form of a transient that can
be placed on a switching regulator is the hot switching in of
loads that contain bypass or other sources of capacitance greater
than 1 µF. When a discharged capacitor is placed on the load it
is effectively placed in parallel with the output cap COUT , and
results in a rapid drop in the output voltage VOUT . Switching
regulators are not capable of supplying enough instantaneous
current to prevent this from occurring. T herefore, the inrush
current to the load capacitors should be held below the current
limit of the design.
CIN IRMS = [VOUT (VIN–VOUT)]0.5 × IMAX/VIN
T he maximum for this formula is reached when VIN = 2 VOUT
,
where IRMS = IOUT /2. It is best to use this worst case scenario for
design margin. Manufacturers of capacitors typically base the
current ratings of their caps on a 2000-hour life. T his requires a
prudent designer to use capacitors that are derated or rated at a
higher temperature. T he use of multiple capacitors in parallel
may also be used to meet design requirements. T he capacitor
manufacturer should be consulted for questions regarding spe-
cific capacitor selection.
In addition, for high frequency decoupling a 0.1 µF to 1.0 µF
ceramic capacitor should be placed and connected as close to
the VIN pin as possible.
Efficiency
Efficiency is one of the most important reasons for choosing a
switching regulator. T he percentile efficiency of a regulator can
be determined by dividing the output power of the device by the
input power and then multiplying the results by 100. Efficiency
losses can occur at any point in a circuit and it is important to
analyze the individual losses to determine changes that would
yield the most improvement. T he efficiency of a circuit can be
expressed as:
C O UT Consider ations
T he minimum required ESR value is the primary consideration
when selecting COUT . For proper circuit operation the ESR
value of COUT must be less than two times the value selected for
RSENSE (see equation below):
COUT Minimum Required ESR < 2 RSENSE
When selecting a capacitor for COUT , the minimum required
ESR is the primary concern. Proper circuit operation mandates
that the ESR value of COUT must be less than two times the
% efficiency = 100% – (% L1 + % L2 + % L3 . . . etc.)
L1, L2, L3, etc., are the individual losses as a percentage of the
input power. In high efficiency circuits small errors result when
expressing losses as a percentage of the output power.
value of RSENSE
.
A capacitor with an ESR value equal to RSENSE will provide the
best overall efficiency. If the ESR value of COUT increases to
two times RSENSE a 1% decrease in efficiency results. United
REV. 0
–9–
ADP1147-3.3/ADP1147-5
ILOAD × % duty cycle × VDROP = Diode Loss
Losses are encountered in all elements of the circuit, but the
four major sources for the circuit shown in Figure 1 are:
Figure 6 indicates the distribution of losses versus load cur-
rent in a typical ADP1147 switching regulator circuit. With
medium current loads the gate charge current is responsible
for a substantial amount of efficiency loss. At lower loads the
gate charge losses become large in comparison to the load,
and result in unacceptable efficiency levels. When low load
currents are encountered the ADP1147 employs a power
savings mode to reduce the effects of the gate loss. In the
power savings mode of operation the dc supply current is the
major source of loss and becomes a greater percentage as the
output current decreases.
1. T he ADP1147 dc bias current.
2. T he MOSFET gate charge current.
3. T he I2 × R losses.
4. T he voltage drop of the Schottky diode.
1. T he ADP1147’s dc bias current is the amount of current that
flows into VIN of the device minus the gate charge current.
With VIN = 10 volts, the dc supply current to the device is
typically 160 µA for a no load condition, and increases pro-
portionally with load to a constant of 1.6 mA in the continu-
ous mode of operation. Losses due to dc bias currents increase
as the input voltage VIN is increased. At VIN = 10 volts the dc
bias losses are usually less than 1% with a load current
greater than 30 mA. When very low load currents are
encountered the dc bias current becomes the primary point
of loss.
Losses at higher loads are primarily due to I2R and the
Schottky diode. All other variables such as capacitor ESR
dissipation, MOSFET switching, and inductor core losses
typically contribute less than 2% additional loss.
Cir cuit D esign Exam ple
In using the design example below assumptions are as follows:
2. T he MOSFET gate charge current is due to the switching of
the power MOSFET ’s gate capacitance. As the MOSFET ’s
gate is switched from a low to a high and back to a low again,
charge impulses dQ travel from VIN to ground. T he current
out of VIN is equal to dQ/dt and is usually much greater than
the dc supply current. When the device is operating in the
continuous mode the I gate charge is = f (QP). T ypically a
P-channel power MOSFET with an RDS on of 135 mΩ will
have a gate charge of 40 nC. With a 100 kH z, switching
frequency in the continuous mode, the I gate charge would
VIN = 5 Volts
VOUT = 3.3 Volts
VDIODE drop (VD) = 0.4 Volts
IMAX OUT = 1 Amp
Max switching frequency (f) = 100 kHz.
T he values for RSENSE, CT and L can be calculated based on the
above assumptions.
RSENSE = 100 mV/1 Amp = 100 mΩ.
tOFF time = (1/100 kHz) × [1 – (3.7/5.4)] = 3.15 µs.
4
equate to 4 mA or about a 2%–3% loss with a V of 10 volts.
CT = 3.15 µs /(1.3 × 10 ) = 242 pF.
IN
L = 5.1 × 10 5 × 0.1 Ω × 242 pF × 3.3 V = 41 µH.
If we further assume:
It should be noted that gate charge losses increase with
switching frequency or input voltage. A design requiring the
highest efficiency can be obtained by using more moderate
switching frequencies.
1. T he data is specified at +25°C.
2. MOSFET max power dissipation (PP) is limited to 250 mW.
3. MOSFET thermal resistance is 50°C/W.
3. I2 × R loss is a result of the combined dc circuit resistance
and the output load current. T he primary contributors to
circuit dc resistance are the MOSFET , the Inductor and
4. T he normalized RDS(ON) vs. temperature approximation (δP)
is 0.007/°C.
R
SENSE. In the continuous mode of operation the average
output current is switched between the MOSFET and the
Schottky diode and a continuous current flows through the
inductor and RSENSE. T herefore the RDS(ON) of the MOSFET
is multiplied by the on portion of the duty cycle. T he result is
then combined with the resistance of the Inductor and
T his results in 250 mW × 50°C per watt = 12.5°C of MOSFET
heat rise. If the ambient temperature TA is 50°C, a junction
temperature of 12.5°C +50°C, T A = 62.5°C. δP = 0.007 ×
(62.5°C –25°C) = 0.2625
We can now determine the required RDS(ON) for the MOSFET :
R
SENSE. T he following equations and example show how to
approximate the I2 × R losses of a circuit.
RDS(ON) = 5(0.25)/3.3 (1)2 (1.2625) = 300 mΩ
RDS(ON) × (Duty Cycle) + RINDUCTOR + RSENSE = R
T he above requirements can be met with the use of a P-channel
IRF7204 or an Si9430.
2
ILOAD × R = PLOSS
When VOUT is short circuited the power dissipation of the
Schottky diode is at worst case and the dissipation can rise
greatly. T he following equation can be used to determine the
power dissipation:
VOUT × ILOAD = POUT
PLOSS/POUT × 100 = % I2 × RLOSS
.
With the duty cycle = 0.5, RINDUCTOR = 0.15, RSENSE = 0.05
and ILOAD = 0.5 A. T he result would be a 3% I2R loss. T he
effects of I2R losses causes the efficiency to fall off at higher
output currents.
PD = ISC(AVG) × VDIODE Drop
A 100 mΩ RSENSE resistor will yield an ISC(AVG) of 1 A. With a
forward diode drop of 0.4 volts a 400 milliwatt diode power
dissipation results.
4. At high current loads the Schottky diode can be a substantial
point of power loss. T he diode efficiency is further reduced
by the use of high input voltages. T o calculate the diode loss,
the load current should be multiplied by the duty cycle of the
diode times the forward voltage drop of the diode.
T he rms current rating needed for CIN will be at least 0.5 A over
the temperature range.
–10–
REV. 0
ADP1147-3.3/ADP1147-5
T o obtain optimum efficiency the required ESR value of COUT
P r inted Wir e Boar d Layout Consider ations
is 100 mΩ or less.
T he PWB layout is extremely critical for proper circuit opera-
tion and the items listed below should be carefully considered
(see Figure 20)
T he circuit should also be evaluated with the minimum input
voltage. T his is done to assure that the power dissipation and
junction temperature of the P-channel MOSFET are not ex-
ceeded. At lower input voltages the operating frequency of the
ADP1147 decreases. T his causes the P-channel MOSFET to
remain in conduction for longer periods of time, resulting in
more power dissipation in the MOSFET .
1. T he signal and power grounds should be separate from each
other. T hey should be tied together only at ground Pin 7 of
the ADP1147. T he power ground should be tied to the an-
ode of the Schottky diode, and the (–) side of the CIN capaci-
tor. T he connections should be made with traces that are as
wide and as short as possible. T he signal ground should be
connected to the (–) side of capacitor COUT using the same
type of runs as above.
T he effects of VIN(MIN) can be evaluated if we assume the
following:
VIN(MIN) = 4.5 V
VOUT = 3.3 V
VD = 0.4 V
2. T he sense(–) run to Pin 4 of the ADP1147 should be con-
nected directly to the junction point of RSENSE and the + side
of COUT
.
fMIN = (1/3.15 µs) × (1– (3.7/4.9)) = 78 kHz.
3. T he sense(–) and sense(+) traces should be routed together
with minimum track spacing and run lengths. T he 1000 pF
filter capacitor across Pins 4 and 5 of the ADP1147 should
be located as close to the device as possible.
3.3(0.125 Ω)(1 A)2 (1.2625 )
PD
=
= 116 mW
4.5
Tr oubleshooting H ints
4. In order to supply sufficient ac current the (+) side of capaci-
tor CIN should be connected with wide short traces and must
be located as close to the source of the P-MOSFET as possible.
Efficiency is the primary reason for choosing the ADP1147 for
use in an application, and it is critical to determine that all por-
tions of the circuit are functioning properly in all modes. After
the design is complete the voltage waveforms on the timing
capacitor, CT , at Pin 2 of the device, should be compared to the
waveforms in Figures 19a and 19b.
5. In order to supply high frequency peak currents the input
decoupling capacitors should range from 0.1 µF to 1.0 µF
and must be located as close to the VIN pin and the ground
Pin 7 as possible.
In the continuous mode of operation the dc voltage level of the
waveform on CT should never fall below the 2 V level and it
should have a 0.9 V peak-to-peak sawtooth on it (see Figure
19a).
6. T he shutdown Pin (6) is a high impedance input and it must
not be allowed to float. T he normal mode of operation of the
device requires that this pin be pulled low.
In the Power Savings Mode the sawtooth waveform on CT will
decay to ground for extended periods of time (see Figure 19b).
During the time that the capacitor voltage is at ground the
ADP1147 is in the power savings or sleep mode and the qui-
escent current is reduced to 160 µA typical.
T he ripple current in the inductor should also be monitored to
determine that it is approximately the same in both modes of
operation. With a higher output currents the voltage level on CT
should never decay to ground as this would indicate poor
grounding and or decoupling.
REV. 0
–11–
ADP1147-3.3/ADP1147-5
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
8-Lead P lastic D IP
(N-8)
0.430 (10.92)
0.348 (8.84)
8
5
0.280 (7.11)
0.240 (6.10)
1
4
0.325 (8.25)
0.300 (7.62)
0.060 (1.52)
0.015 (0.38)
PIN 1
0.195 (4.95)
0.115 (2.93)
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
SEATING
PLANE
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
0.008 (0.204)
8-Lead SO IC
(SO -8)
0.1968 (5.00)
0.1890 (4.80)
8
1
5
4
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.0688 (1.75)
0.0532 (1.35)
0.0196 (0.50)
0.0099 (0.25)
x 45°
0.0098 (0.25)
0.0040 (0.10)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
–12–
REV. 0
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IC SWITCHING CONTROLLER, 250 kHz SWITCHING FREQ-MAX, PDIP8, PLASTIC, DIP-8, Switching Regulator or Controller
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