ADP162_技术文档

Constant-Frequency, Current-Mode

Step-Up DC/DC Controller

ADP1621

Data Sheet

FEATURES

TYPICAL APPLICATION CIRCUIT

V_IN= 3.3V

92% efficiency (no sense resistor required)

L1

4.7µH

1.0% initial accuracy

IC supply voltage range: 2.9 V to 5.5 V

Power-input voltage as low as 1.0 V

Capable of high supply input voltage (>5.5 V)

with an external NPN or a resistor

V_OUT= 5V

1A

D1

C3

1µF

10V

C4

0.1µF

10V

IN

R1

35.7kΩ

1%

R_S

80Ω

C_OUT1C_OUT2C_OUT3

1µF

10V

10µF

150µF

6.3V

×2

CS

10V

ADP1621

V

_INUVLO and 35 mA shunt regulator

R2

11.5kΩ

1%

SDSN

COMP

FREQ

External slope compensation with 1 resistor

Programmable operating frequency

(100 kHz to 1.5 MHz) with 1 resistor

Lossless current sensing for switch-node voltage <30 V

Resistor current sensing for switch-node voltage >30 V

Synchronizable to external clock

M1

GATE

PGND

R_COMP

9.09kΩ

FB

C2

120pF

GND

C1

C_COMP

1.8nF

47µF

6.3V

R_FREQ

31.6kΩ

1%

Current-mode operation for excellent line and load transient

responses

10 µA shutdown current

AGND

f

_OSC= 600kHz

C1 = MURATA GRM31CR60J476M

C_OUT3= SANYO POSCAP 6TPE150M

L1 = TOKO FDV0630-4R7M

M1 = VISHAY Si7882DP

D1 = VISHAY SSA33L

Figure 1. High Efficiency Output Boost Converter in Lossless Mode,

3.3 V Input, 5 V Output (Bootstrapped)

Current limit and thermal overload protection

Soft start in 2048 clock cycles

Supported by ADIsimPower™ design tool

100

90

80

70

60

50

APPLICATIONS

APD bias

Portable electronic equipment

Isolated dc/dc converter

Step-up/step-down dc/dc converter

LED driver for laptop computer and navigation system

LCD backlighting

GENERAL DESCRIPTION

40

30

The ADP1621 is a fixed-frequency, pulse-width modulation

(PWM), current-mode, step-up converter controller. It drives an

external n-channel MOSFET to convert the input voltage to a

higher output voltage. The ADP1621 can also be used to drive

flyback, SEPIC, and forward converter topologies, either isolated

or nonisolated.

0.01

0.1

1

10

LOAD CURRENT (A)

Figure 2. Efficiency of Circuit Shown in Figure 1

The ADP1621 supply input voltage range is 2.9 V to 5.5 V, although

higher input voltages are possible with the use of a small-signal

NPN pass transistor or a single resistor. The voltage of the

power input can be as low as 1 V for fuel cell applications. The

switching frequency is set by an external resistor over a range of

100 kHz to 1.5 MHz and can be synchronized to an external

clock by using the SDSN pin. The shutdown quiescent current is

less than 10 µA. The ADP1621 has a thermal shutdown feature

that shuts down the gate driver when the junction temperature

reaches approximately 150°C. The internal soft start circuit limits

inrush current at startup. The ADP1621 is available in the 10-lead

MSOP lead-free package and is specified over the −40°C to +125°C

junction temperature range.

The ADP1621 eliminates the use of a current-sense power

resistor by measuring the voltage drop across the on resistance

of the n-channel MOSFET. This technique, allowed up to a

maximum voltage of 30 V at the switch node, maximizes

efficiency and reduces cost. For switch-node voltages higher than

30 V or for more accurate current limiting, the CS pin can be

connected to a current-sense resistor in the source of the MOSFET.

The slope compensation is implemented by an external resistor,

allowing a wide range of external components (inductors and

MOSFETs), and can be chosen for various switching frequencies

and input and output voltages.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

ADP1621

Data Sheet

TABLE OF CONTENTS

Duty Cycle................................................................................... 14

Setting the Output Voltage........................................................ 14

Inductor Current Ripple............................................................ 14

Inductor Selection...................................................................... 14

Input Capacitor Selection.......................................................... 15

Output Capacitor Selection....................................................... 15

Diode Selection........................................................................... 15

MOSFET Selection..................................................................... 16

Loop Compensation .................................................................. 16

Slope Compensation.................................................................. 17

Current Limit.............................................................................. 18

Light Load Operation ................................................................ 18

Recommended Component Manufacturers........................... 19

Layout Considerations................................................................... 20

Efficiency Considerations ............................................................. 21

Examples of Application Circuits................................................. 22

Standard Boost Converter—Design Example ........................ 22

Bootstrapped Boost Converter................................................. 23

SEPIC Converter Circuit........................................................... 27

Low Voltage Power-Input Circuit ............................................ 27

LED Driver Application Circuits ............................................. 28

Related Parts.................................................................................... 30

Outline Dimensions....................................................................... 31

Ordering Guide .......................................................................... 31

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Typical Application Circuit ............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution.................................................................................. 5

Simplified Block Diagram ............................................................... 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Theory of Operation ...................................................................... 12

Control Loop............................................................................... 12

Current-Sense Configurations.................................................. 12

Current Limit .............................................................................. 13

Undervoltage Lockout ............................................................... 13

Shutdown..................................................................................... 13

Soft Start ...................................................................................... 13

Internal Shunt Regulators.......................................................... 13

Setting the Oscillator Frequency and Synchronization

Frequency .................................................................................... 13

Application Information: Boost Converter................................. 14

ADIsimPower Design Tool ....................................................... 14

REVISION HISTORY

6/12—Rev. A to Rev. B

Change to Features Section ............................................................. 1

Added ADIsimPower Design Tool Section................................. 14

Change to Table 6 ........................................................................... 30

Updated Outline Dimensions....................................................... 31

Changes to Ordering Guide .......................................................... 31

12/06—Rev. 0 to Rev. A

Changes to Table 1............................................................................ 3

Changes to Table 2............................................................................ 5

Added Table 3.................................................................................... 5

Changes to Table 5.......................................................................... 19

Changes to Ordering Guide .......................................................... 31

7/06—Revision 0: Initial Version

Rev. B | Page 2 of 32

Data Sheet

ADP1621

SPECIFICATIONS

V_IN= 5 V, R_FREQ= 100 kΩ, f_OSC= 200 kHz, T_J= −40°C to 125°C, unless otherwise noted.

Table 1.

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

MAIN CONTROL LOOP

Internal Soft Start Time

PIN Supply Voltage¹

IN Supply Voltage¹

Shunt Regulation Voltage

t_SS

V_PIN

V_IN

2048

Cycles

V

Ω

mA

µA

2.9

5.4

5.2

V_SHUNT

5.7

V_SHUNT

I_IN= 3 mA, I_PIN= 3 mA, T_A= 25°C

I_IN= 3 mA, I_PIN= 3 mA

Current into IN = 8 mA to 12 mA

Current into PIN = 8 mA to 12 mA

V_IN= 2.9 V to 5.5 V, V_FB= 1.215 V

V_IN= 2.9 V to 5.5 V, SDSN = GND

5.6

13

7

1.8

1

6.0

Shunt Resistance

R_SHUNT

I_IN

IN Quiescent Current

IN Shutdown Current

PIN Supply Current

Static Mode, No Switching

Shutdown Mode

3

10

I_PIN

V_FB= 1.3 V, V_COMP< V_{C O M P, Z C T}, GATE = 0 V

SDSN = GND

V_UVLOrising

V_UVLOhysteresis

T_A= 25°C

1

2.5

−80

10

2.8

µA

V

mV

V

nA

%/V

Undervoltage Lockout Threshold at

IN Pin

V_UVLO

V_FB

2.2

FB Regulation Voltage

1.203 1.215

1.197 1.215

1.227

1.233

+75

FB Input Current

Line Regulation²

I_FB

V_FB= 1.215 V, T_A= 25°C

−75

+25

0.02

−0.1

300

1.0

2.0

9.5

70

∆V_FB/∆V_IN

2.9 V ≤ V_IN≤ 5 V, T_J= −40°C to +85°C

2.9 V ≤ V_IN≤ 5 V, T_J= −40°C to +125°C

V_COMP= 1.4 V to 1.5 V

0.06

0.072 %/V

Load Regulation³

∆V_FB/∆V_COMP

g_m

V_{C O M P, Z C T}

V_COMP,CLAMP

−1

%

µS

V

V/V

µA

Error Amplifier Transconductance

COMP Zero-Current Threshold

COMP Clamp High Voltage

0.85

1.9

7.5

55

1.15

2.1

2.2

11.5

85

T_J= −40°C to +85°C

T_J= −40°C to +125°C

Current-Sense Amplifier Gain

Peak Slope-Compensation Current at

CS Pin⁴

n

I_SC,PK

V_CS= 0 V to 100 mV maximum

across R_S(GATE high)

CS Pin Leakage Current

Shutdown Time

Thermal Shutdown Threshold⁵

Thermal Shutdown Hysteresis⁵

OSCILLATOR

Oscillator Frequency Range⁶

Oscillator Frequency

Oscillator Frequency Tempco

SDSN Input Level Threshold

SDSN Threshold Hysteresis

SDSN Internal Pull-Down Resistor

Synchronization Minimum Pulse Width

Synchronization Maximum Pulse Width

Synchronization Frequency

GATE Minimum On Time

I_CS,LEAK

t_SD

T_TMSD

V_CS= 30 V (GATE low)

SDSN pin from high to low or left floating

5

µA

µs

°C

50

150

−10

f_OSC

f_OSC,TC

V_SDSN,THRESH

100

255

1500

395

kHz

%/°C

V

kΩ

ns

kHz

ns

%

R_FREQ= 65 kΩ, T_A= 25°C

V_IN= V_PIN= 5 V

325

0.06

1.7

−0.19

100

1.5

1.9

R_SDSN

t_SYNC,MIN

t_SYNC,MAX

f_SYNC

t_ON,MIN

t_OFF,MIN

D_MAX

V_SDSN= 0 V to V_IN

45

0.8/f_SYNC

100

110

1800

215

230

97

V_FB= 1.215 V, V_COMP= 1.0 V

V_FB= 1.215 V, V_COMP= 2.0 V

f_SW= 200 kHz, R_FREQ= 100 kΩ

f_OSC= 200 kHz, R_FREQ= 100 kΩ, f_SYNC= f_SW

180

190

GATE Minimum Off Time

Maximum Duty Cycle^{6, 7}

93

1.1

Recommended Maximum

f_SYNC/f_OSC

1.2

1.4

Synchronized Frequency Ratio^{6, 8}

Rev. B | Page 3 of 32

ADP1621

Data Sheet

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

GATE DRIVER

GATE Rise Time⁹

GATE Fall Time⁹

t_R

t_F

C_GATE= 3.3 nF

17

13

ns

¹The maximum input voltage is the shunt regulation voltage, which is typically 5.5 V and can range from 5.3 V to 6.0 V over the specified temperature range.

²The ADP1621 is tested in a feedback servo loop, which servos V_FBto the internal reference voltage. The voltage change in FB is measured while V_INis changed from

2.9 V to 5 V. The line regulation is calculated by (∆V_FB/V_FB) × 100%/∆V_IN.

³The ADP1621 is tested in a feedback servo loop, which servos V_FBto the internal reference voltage, and V_COMPis forced from 1.4 V to 1.5 V. The V_COMPrange is

(1.0 V ≤ V_COMP≤ 2.0 V).

⁴The peak slope-compensation current at the CS pin is typically 70 µA, and effectively clamped at 116 mV. Thus, R_Sshould not exceed 1.6 kΩ (116 mV/70 µA).

⁵Guaranteed by design for thermal shutdown. When the thermal junction temperature of the ADP1621 reaches approximately 150°C, the ADP1621 goes into thermal

shutdown and the GATE voltage is pulled low. When the junction temperature drops below about 140°C, the soft start sequence is initiated and the ADP1621 resumes

normal operation.

⁶f_OSCis the natural oscillation frequency, f_SYNCis the synchronization frequency, and f_SWis the switching frequency. If synchronization is used, then f_SW= f_SYNC; otherwise, f_SW= f_OSC

.

⁷Guaranteed by design and bench characterization.

⁸To ensure proper synchronization operation, set the synchronization frequency, f_SYNC, to 1.2× of the free-running frequency, f_OSC. Although the switching frequency can

be synchronized to as high as 1.8 MHz, the peak slope-compensation current decreases at higher synchronization frequencies. It is recommended that the maximum

f_SYNCbe less than 1.4× of f_OSCand should not exceed 1.8 MHz. The slope-compensation resistor, R_S, should be chosen for the synchronization frequency (see the Slope

Compensation section in the Application Information: Boost Converter section).

⁹GATE rise and fall times are measured from 10% to 90% levels.

Rev. B | Page 4 of 32

Data Sheet

ADP1621

ABSOLUTE MAXIMUM RATINGS

Absolute maximum ratings apply individually only, not in

combination. Unless otherwise specified, all other voltages are

referenced to GND.

Table 2.

Parameter

Rating

IN to GND

FB, COMP, SDSN, FREQ, GATE to GND

CS to GND

−0.3 V to V_SHUNT

−0.3 V to (V_IN+ 0.3 V)

−5 V to +33 V

−0.3 V to V_SHUNT

25 mA

THERMAL RESISTANCE

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

PIN to PGND

Supply Current into IN

Supply Current into PIN

Storage Temperature Range

Table 3. Thermal Resistance

35 mA

−55°C to +150°C

Package Type

θ_JA

Unit

°C/W

Junction Operating Temperature Range¹−55°C to +150°C

10-lead MSOP on a 2-layer PCB

10-lead MSOP on a 4-layer PCB

200

172

Junction Storage Temperature Range

Lead Temperature (Soldering, 10 sec)

Package Power Dissipation¹

−55°C to +150°C

300°C

Junction-to-ambient thermal resistance of the package is based

on modeling and calculation using 2-layer and 4-layer boards,

and natural convection. The junction-to-ambient thermal

resistance is application- and board-layout dependent. In

applications where high maximum power dissipation exists,

attention to thermal dissipation issues in board design is

required.

(T_J,MAX− T_A)/θ_JA

¹In applications where high power dissipation and poor package thermal

resistance are present, the maximum ambient temperature may need to be

derated. Maximum ambient temperature (T^A,MAX) is dependent on the

maximum operating junction temperature (T^J,MAX= 150^oC), the maximum

power dissipation of the device in the application (P^D,MAX), and the junction-

to-ambient thermal resistance of the package in the application (θ^JA), is given

by the following equation: T^A,MAX= TJ,MAX - - (θJA x PD,MAX).

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

Rev. B | Page 5 of 32

ADP1621

Data Sheet

SIMPLIFIED BLOCK DIAGRAM

V

REF

1.215V

SOFT START

(2048 CYCLES)

ERROR

AMPLIFIER

g

m

FB

5.5V

COMP

V

OSC

1.4V

SET

OSC

S

R

GATE

FREQ

SLOPE

COMP

GATE

DRIVER

PWM

COMPARATOR

+

IN

UVLO

100kΩ

CS

SDSN

n

PGND

5.5V

GND

ADP1621

Figure 3. ADP1621 Simplified Block Diagram

Rev. B | Page 6 of 32

Data Sheet

ADP1621

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SDSN

GND

1

2

3

4

5

10 IN

9

8

7

6

CS

ADP1621

TOP VIEW

(Not to Scale)

COMP

FB

GATE

PGND

FREQ

Figure 4. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic Description

1

SDSN

Shutdown and Synchronization Input. Turn the ADP1621 on by driving SDSN high; turn it off by driving SDSN low.

If SDSN is left floating or when the SDSN is pulled low, the ADP1621 goes into shutdown after 50 µs. If synchronization is

needed, synchronize the switching frequency to an external clock by connecting the external clock to the SDSN

pin. An internal 100 kΩ pull-down resistor is connected from SDSN to GND.

2

3

GND

COMP

Ground.

Regulation Control Compensation Node. COMP is the output of the internal transconductance error amplifier.

Connect a series RC from COMP to GND to compensate the regulator. The nominal voltage range for this pin is

1.0 V to 2.0 V.

4

FB

Feedback Input. FB is the input to the internal transconductance error amplifier. Drive FB from the output voltage

through a resistive voltage divider. The ratio of the voltage divider sets the output voltage. The regulation voltage

at FB is nominally 1.215 V.

5

6

7

8

9

FREQ

PGND

GATE

Frequency Control Input. Connect a resistor from FREQ to GND to set the free-running switching frequency

between 100 kHz and 1.5 MHz. The nominal voltage of this pin is 1.4 V.

Power Ground Input. PGND is the ground return for the internal gate driver and the negative input of the internal

current-sense amplifier. Connect PGND to GND as close to the ADP1621 as possible.

Gate Driver Output. The maximum gate driver output is equal to the PIN voltage. GATE drives the gate of the

external n-channel power MOSFET. Connect GATE to the gate of the MOSFET.

Power Input. PIN powers the gate driver output. An internal 5.5 V shunt regulator is connected to this pin. Bypass

PIN to PGND with a 0.1 µF or greater capacitor.

Current-Sense Input. CS is the positive input of the current-sense amplifier. When GATE is turned on, the voltage at

the CS pin increases linearly from 0 V to a maximum of 116 mV, and the nominal peak slope-compensation output

current is 70 µA. When GATE is off, the CS function is disabled. For current sensing in lossless mode, connect CS to

the drain of the power MOSFET. The absolute maximum voltage at CS is 33 V. For higher accuracy current sensing

or higher switch-node voltages, connect CS to a current-sense power resistor in the source of the power MOSFET.

In both sensing methods, it is required to add a slope-compensation resistor, R_S, to the CS pin to achieve stability

in the inductor current for duty cycles greater than 50%. However, it is recommended to add R_Sfor all duty cycles

because load transients can momentarily cause the duty cycle to be greater than 50%, even when the steady-

state duty cycle is less than 50%.

CS

10

IN

Input Voltage. IN powers the ADP1621 internal circuitry. An internal 5.5 V shunt regulator is connected to this pin.

Bypass IN to GND with a 0.1 µF or greater capacitor.

Rev. B | Page 7 of 32

ADP1621

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

100

92

91

90

89

88

87

86

90

80

70

60

50

LOAD = 0.5A

LOAD = 1A

T

= 25°C

f_S^A_W= 220kHz

T

V

= 25°C

= 3.3V

= 5V

A

40

30

V

= 3.3V

= 5V

85

84

IN

OUT

0.01

0.1

1

10

100

300

500

700

900

1100

1300

1500

LOAD CURRENT (A)

SWITCHING FREQUENCY (kHz)

Figure 5. Efficiency vs. Load Current

Figure 8. Efficiency vs. Switching Frequency

100

10

T

V

= 25°C

A

V

RIPPLES @ 5V

= 3.3V

OUT

AC-COUPLED

IN

= 5V

I

IN

OUT

LOAD = 1A

1

0.1

1

I

0.01

0.001

0.0001

T

= 25°C

A

2

NO SWITCHING

0.00001

CH2 = GATE

A CH2 2.6V

0

1

2

3

4

5

6

7

CH1 20mV CH2 2V

M2µs

SUPPLY VOLTAGE (V)

Figure 6. Output Voltage Ripple of the Circuit Shown in Figure 1

Figure 9. Supply Current vs. Supply Voltage

1.21605

2.5

2.0

1.5

1.0

T

V

= 25°C

= 5V

A

T

= 25°C

A

IN

1.21600

1.21595

1.21590

1.21585

0.5

0

1.21580

1.21575

2.5

3.0

3.5

4.0

4.5

(V)

5.0

5.5

6.0

1.17

1.19

1.21

1.23

(V)

1.25

1.27

1.29

V

IN

FB

Figure 7. V_FBvs. V_IN

Figure 10. V_COMPvs. V_FB

Rev. B | Page 8 of 32

Data Sheet

ADP1621

45

40

35

30

25

20

15

10

35

30

25

20

15

10

5

T

V

= 25°C

= V

A

MOSFET Q = 25nC

G

= 5V

t_R^INOR t^P_F^INIS FROM

10% TO 90% OF

t_R

THE GATE VOLTAGE

t_F

MOSFET Q = 15nC

G

MOSFET Q = 7nC

G

5

0

200

400

600

800 1000 1200 1400 1600 1800

0

5

10

15

20

25

30

35

40

45

50

SWITCHING FREQUENCY (kHz)

GATE CAPACITANCE (nF)

Figure 11. PIN Supply Current vs. Switching Frequency

Figure 14. GATE Rise and Fall Times vs. C_GATE

2.60

2.55

2.50

1600

1500

1400

1300

1200

1100

1000

900

800

700

600

500

400

300

200

100

0

SDSN = 5V

2.45

2.40

–50

0

50

100

150

0

20

40

60

80

100 120 140 160 180 200

(kΩ)

TEMPERATURE (°C)

R

FREQ

Figure 12. V_UVLOThreshold vs. Temperature

Figure 15. Oscillator Frequency vs. Resistance

1.03

1.02

1.01

1.00

0.99

198

197

196

195

194

193

V

= 5V

IN

T = 25°C

A

R

= 100kΩ

FREQ

0.98

0.97

192

191

–50

0

50

100

150

2

3

4

5

TEMPERATURE (°C)

V

(V)

IN

Figure 13. Frequency vs. Temperature

Figure 16. Oscillator Frequency vs. V_IN

Rev. B | Page 9 of 32

ADP1621

Data Sheet

250

1.6

1.4

1.2

1.0

0.8

0.6

0.4

V

= 5V

IN

CS = 30V

V

= 5V

IN

SDSN = 0V

200

150

100

50

0.2

0

–40

10

60

110

160

–50

0

50

100

150

CS LEAKAGE (nA)

TEMPERATURE (°C)

Figure 17. Temperature vs. CS Leakage

Figure 20. Shutdown IN Current vs. Temperature

1.2165

1.2160

1.2155

1.2150

1.2145

1.2140

1.2135

1.2130

1.2125

1.2120

8

4

V

= 1.2113V AT 25°C

V

= 5V

FB

FB BIAS CURRENT IS MEASURED

IN

SDSN = 0V

BY FORCING A CONSTANT 1.2113V

OVER THE TEMPERATURE RANGE.

0

–4

–8

–12

–16

–50

0

50

100

150

–50

0

50

100

150

TEMPERATURE (°C)

Figure 18. FB Bias Current vs. Temperature

Figure 21. FB Voltage vs. Temperature

90

80

70

60

50

40

30

20

10

0

T

V

= 25°C

= 3.3V

A

IN

= 5V

OUT

LOAD = 0.1A

DCM OPERATION

4

CH4 = INDUCTOR CURRENT

f_OSC= 200kHz

f_OSC= 550kHz

2

1

CH2 = DRAIN VOLTAGE

CH1 = GATE

1.0

1.2

1.4

1.6

f_SYNCf_OSC

1.8

2.0

2.2

CH1 5V

CH2 5V

CH4 500mAΩ

M2µs

A CH1

2.9V

/

Figure 19. Slope-Compensation Current vs. f_SYNC/f_OSC

Figure 22. DCM Switching Waveform

Rev. B | Page 10 of 32

Data Sheet

ADP1621

T

= 25°C LOAD = 0.3A

A

V

= 3.3V CCM OPERATION

IN

V

= 5V

OUT

LOAD CURRENT

FROM 0.2A TO 1.2A

4

2

4

1

CH4 = INDUCTOR CURRENT

CH2 = DRAIN VOLTAGE

CH1 = GATE

OUTPUT, AC-COUPLED

T

V

= 25°C

= 3.3V

A

1

IN

V

= 5V

OUT

CH1 5V

CH2 5V

CH4 500mAΩ

M2µs

A CH1

2.9V

CH1 50mV

M200µs

A CH4

700V

CH4 1AΩ

Figure 23. CCM Switching Waveform

Figure 26. Load Transient Response of the Circuit Shown in Figure 1

T

= 25°C

A

T

V

= 25°C

= 5V

A

V

f

= 3.3V

= 5V

IN

OUT

NO LOAD AT V

CH1 = V

OUT

= 220kHz

SW

SOFT-START = 9.3ms

CH1 = V

, AC-COUPLED

OUT

1

CH2 = SDSN

2

1

3

CH2 = V FROM 3V TO 4V

IN

2

CH3 = GATE

A CH1

CH1 1V

CH3 5V

CH2 5V

M2ms

4.5V

CH1 50mV CH2 2V

M400µs

A CH2

3.8V

Figure 24. Soft Start Waveform

Figure 27. Line Transient Response of the Configuration Shown in Figure 1

with No Load

T

= 25°C

A

V

= 5V

OUT

LOAD AT V

= 1A

OUT

CH1 = V

, AC-COUPLED

OUT

1

CH2 = V FROM 3V TO 4V

IN

2

CH1 50mV CH2 2V

M400µs

A CH2

3.8V

Figure 25. Line Transient Response of the Configuration Shown in Figure 1

with a 1 A Load

Rev. B | Page 11 of 32

ADP1621

Data Sheet

THEORY OF OPERATION

The ADP1621 is a fixed-frequency, current-mode, step-up dc/dc

converter controller. It drives an external n-channel MOSFET

to step the input voltage up to a higher output voltage. It can be

used for SEPIC, flyback, boost, buck-boost, forward, and other

converter topologies. It operates at a fixed switching frequency that

is set by an external resistor over a range of 100 kHz to 1.5 MHz,

and it can be synchronized to an external clock by connecting

the SDSN pin to the clock.

CURRENT-SENSE CONFIGURATIONS

The ADP1621 can sense the current across the on resistance of

the MOSFET to minimize external component count and improve

efficiency by eliminating the power that would be lost in a current-

sense resistor. This lossless technique eliminates the need for an

expensive current-sense resistor. In the lossless mode configuration,

the voltage at the CS pin (or the switch-node voltage at the drain of

the MOSFET) must not exceed 30 V (see Figure 28). This technique

maximizes efficiency and reduces cost. In practice, when the

calculated V_SWapproaches 30 V, one should build the board and

measure the actual V_SWbefore committing to the lossless mode

design. Because of the parasitic inductance in the diode, output

capacitor, and PCB traces, V_SWtypically has narrow peaks that

exceed the theoretical maximum voltage at V_SW—the sum of

The input supply current to the ADP1621 is less than 3 mA

during normal operation and less than 10 µA during shutdown.

The ADP1621 can drive large external MOSFETs, allowing it to

support load currents in excess of 10 A.

CONTROL LOOP

The ADP1621 uses a current-mode architecture to regulate the

output voltage. The output voltage is monitored at FB through

a resistive voltage divider. The voltage at FB is compared to the

internal 1.215 V reference voltage by the internal transconductance

error amplifier to create an error current at COMP. A resistor-

capacitor compensation impedance connected from COMP to

GND converts the error current to an error voltage.

V

_OUTand the forward-voltage drop of Diode D1. If the measured

peak voltage exceeds 30 V, or if a more accurate current limit is

desired, then the CS pin can be connected to an external current-

sense resistor in the source of the MOSFET (Figure 29). The

maximum power output is limited by the selection of the

external components.

L

D1

V

OUT

IN

At the beginning of the switching cycle, the MOSFET is turned

on and the inductor current ramps up. The MOSFET current is

measured and converted to a voltage using R_CSor R_DSONand is

added to the stabilizing slope-compensation ramp. The resulting

voltage sum passes through the current-sense amplifier to generate

the current-sense voltage. When the current-sense voltage is

greater than the COMP error voltage, the MOSFET is turned off

and the inductor current ramps down until the internal clock

initiates the next switching cycle. The duty-cycle of the PWM

modulator is thus adjusted to provide the necessary load current

at the desired output voltage. Because the output voltage ultimately

controls the peak inductor current through the COMP error

voltage, this scheme is referred to as peak current-mode control.

IN

CS

V

SW

R

S

ADP1621

SDSN

C

O

GATE

PGND GND

Figure 28. CS Pin Connection for V_SW< 30 V, Lossless Mode

(No Current-Sense Resistor Needed)

V

L

D1

SW

V

OUT

IN

With light loads, the converter can also operate under discon-

tinuous conduction mode and pulse-skipping modulation to

maintain output-voltage regulation. These two forms of operation

are discussed in detail in the Light Load Operation section.

Note that the converter can also be designed to operate in

discontinuous conduction mode at full load if desired.

GATE

ADP1621

SDSN

C

O

CS

PGND GND

R

S

R

CS

Overall, the current-mode regulation system of the ADP1621

allows fast transient responses while maintaining a stable output

voltage. By selecting the proper resistor-capacitor network from

COMP to GND, the regulator response can be optimized for a

wide range of input voltages, output voltages, and load currents.

Figure 29. CS Pin Connection for V_SW> 30 V, Resistor Sense Mode

with a Current-Sense Resistor, R_CS

Rev. B | Page 12 of 32

Data Sheet

ADP1621

CURRENT LIMIT

SETTING THE OSCILLATOR FREQUENCY AND

SYNCHRONIZATION FREQUENCY

The current limit is achieved by the COMP voltage clamp, owing

to the current-mode operation of the ADP1621. A detailed

explanation of how the current limit is determined can be found

in the Current Limit section of the Application Information:

Boost Converter section.

The free-running oscillator frequency, f_OSC, is set by a resistor

from FREQ to GND. A 100 kΩ resistor sets the typical oscillator

frequency to 200 kHz, a 65 kΩ resistor sets it to 325 kHz, a 32 kΩ

resistor sets it to 600 kHz, and a 10 kΩ resistor sets it to 1.5 MHz.

Figure 30 shows a typical relationship between f_OSCand R_FREQ

.

UNDERVOLTAGE LOCKOUT

1600

1500

1400

1300

1200

1100

1000

900

800

700

600

500

400

300

200

100

0

An internal undervoltage lockout (UVLO) circuit at the IN pin

holds the GATE voltage low when the IN voltage is below the

UVLO voltage, which is typically 2.5 V.

SHUTDOWN

The ADP1621 goes into shutdown approximately 50 µs after the

SDSN pin is pulled low or left floating. There is an internal 100 kΩ

resistor connected between SDSN and GND.

When the junction temperature of the ADP1621 reaches about

150°C, the ADP1621 goes into thermal shutdown and the GATE

voltage is pulled low. When the junction temperature drops below

about 140°C, the ADP1621 resumes normal operation after the

soft start sequence.

0

20

40

60

80

100 120 140 160 180 200

(kΩ)

R

FREQ

SOFT START

Figure 30. f_OSCvs. R_FREQ

The ADP1621 has an internal soft start circuit that ramps

the FB regulation voltage from 0 V to 1.215 V in 64 steps over

2048 clock oscillator cycles. This soft start ramp allows the

output voltage to slowly rise to the steady-state output voltage,

preventing input inrush current at startup.

The switching frequency can be synchronized to an external clock

by driving the SDSN pin with that clock signal. The SDSN pin

serves the two functions of shutdown control and frequency

synchronization input. If the SDSN input detects a low-to-high

transition within 10 µs of a high-to-low transition, it resets the

oscillator to synchronize to the frequency of the signal at SDSN.

The ADP1621 only synchronizes to frequencies greater than the

free-running switching frequency. To ensure proper synchronization

operation, set the synchronization frequency, f_SYNC, to 1.2× the free-

running frequency, f_OSC. The switching frequency, f_SW, is equal to

INTERNAL SHUNT REGULATORS

The IN and PIN pins each have an internal shunt regulator that

allows the ADP1621 to operate over a wide input voltage range.

The shunt regulators limit the voltages at IN and PIN to about

5.5 V, allowing the use of logic-level MOSFETs independent of

the input and/or output voltage. The shunt regulator voltage can

reach 5.7 V at 10 mA. See Figure 9 for the I-V characteristics of

these shunt regulators.

f_SYNC. Although the switching frequency can be synchronized to as

high as 1.8 MHz, the peak slope-compensation current decreases at

higher f_SYNC. It is recommended that the maximum f_SYNCbe less than

1.4× of f_OSC. The slope-compensation resistor, R_S, should be chosen

for the synchronization frequency (see the Slope Compensation

section). For SDSN to detect a high input, the high state must

remain high for at least 100 ns.

The internal power is derived from the IN pin, whereas the

MOSFET gate driver (GATE) current comes from the power

input, PIN. By separating the two inputs, PIN can be driven

with an external small-signal NPN transistor to limit the power

loss in the PIN shunt regulator when the input voltage is higher

than 5.5 V. See Figure 37 for an example. The maximum currents

going into PIN and IN should not exceed 35 mA and 25 mA,

respectively.

Rev. B | Page 13 of 32

ADP1621

Data Sheet

APPLICATION INFORMATION: BOOST CONVERTER

In this section, an analysis of a boost converter is presented,

along with guidelines for component selection. A typical boost-

converter application circuit is shown in Figure 1.

SETTING THE OUTPUT VOLTAGE

The output voltage is set through a voltage divider from the

output voltage to the FB input. The feedback resistor ratio sets

the output voltage of the system. The regulation voltage at FB is

1.215 V. The output voltage is given by (see Figure 1)

ADIsimPower DESIGN TOOL

The ADP1621 is supported by ADIsimPower design tool set.

ADIsimPower is a collection of tools that produce complete

power designs optimized for a specific design goal. The tools

enable the user to generate a full schematic, bill of materials,

and calculate performance in minutes. ADIsimPower can

optimize designs for cost, area, efficiency, and parts count

while taking into consideration the operating conditions and

limitations of the IC and all real external components. For

more information about ADIsimPower design tools, refer to

www.analog.com/ADIsimPower. The tool set is available from

this website, and users can also request an unpopulated board

through the tool.

R1

R2











V_OUT=1.215 V× 1 +

(4)



The input bias current into FB is 25 nA typical, 70 nA

maximum. For a 0.1% degradation in regulation voltage and

with 70 nA bias current, R2 must be less than 18 kΩ, which

results in 68 µA of divider current. Choose the value of R1 to set

the output voltage. Using higher values for R2 results in reduced

output voltage accuracy due to the input bias current at the FB

pin, whereas lower values cause increased quiescent current

consumption.

INDUCTOR CURRENT RIPPLE

DUTY CYCLE

Choose a peak-to-peak inductor ripple current between 20%

and 40% of the average inductor current. A good starting point

for a design is to choose the peak-to-peak ripple current to be

30% of 1/(1 − D) times the maximum load current:

To determine the worst-case inductor current ripple, output voltage

ripple, and slope-compensation factor, it is first necessary to

determine the system duty cycle. The duty cycle in continuous

conduction mode (CCM) is calculated by the equation

V_OUT+V_D−V_IN

I_LOAD,MAX

1− D

D =

(1)

∆I_L= 0.3×

(5)

V_OUT+V_D

where ΔI_Lis the peak-to-peak inductor ripple current, and I_LOAD,MAX

is the maximum load current required by the application.

where V_OUTis the desired output voltage, V_INis the input

voltage, and V_Dis the forward-voltage drop of the diode. A

typical Schottky diode has a forward-voltage drop of 0.5 V.

INDUCTOR SELECTION

The GATE minimum on and off times determine the minimum

and maximum duty cycles, respectively. The minimum on and

off times are typically 180 ns and 190 ns, respectively. The

minimum and maximum duty cycles are given by

The inductor value choice is important because it dictates

the inductor current ripple and therefore the voltage ripple

at the output.

The average inductor current, I_L,AVE, is given by

t_ON,MIN

I_LOAD

1− D

D_MIN

=

= t_ON,MIN× f_SW

(2)

(3)

I_L,AVE

=

(6)

t_SW

t_OFF,MIN

and the peak-to-peak inductor ripple current is inversely

proportional to the inductor value:

D_MAX=1−

=1−(t_OFF,MIN× f_SW)

t_SW

V

_IN×D

where D_MINis the minimum duty cycle, D_MAXis the maximum duty

cycle, t_ON,MINis the minimum on time, t_{OFF, MIN}is the minimum off

time, t_SWis the switching period, and f_SWis the switching frequency.

∆I_L=

(7)

f

_SW×L

where f_SWis the switching frequency, and L is the inductor value.

Note that when the converter tries to operate at a duty cycle

lower than D_MIN, pulse-skipping modulation occurs to maintain

the output voltage regulation (see the Light Load Operation

section).

Assuming continuous conduction mode (CCM) operation, the

peak inductor current is given by

I_LOAD

V

_IN×D

∆I_L

I_L,PK

=

+

=

+

(8)

1− D

2

1− D 2× f_SW×L

Smaller inductor values are typically smaller in size and usually

less expensive, but increase the ripple current. Larger ripple current

also increases the power loss in the inductor core. Too large an

inductor value results in added expense and may impede load

transient responses because it reduces the effect of slope

compensation.

Rev. B | Page 14 of 32

Data Sheet

ADP1621

Assuming the ripple current is 30% of 1/(1 − D) times the max-

imum load current, a reasonable choice for the inductor value is

OUTPUT CAPACITOR SELECTION

The output capacitor maintains the output voltage and supplies

current to the load while the external MOSFET is on.

V

_IN×D×

(1− D)

(9)

L =

0.3× f_SW× I_LOAD,MAX

The value and characteristics of the output capacitor greatly

affect the output voltage ripple and stability of the converter.

The amount of peak-to-peak output voltage ripple, ΔV_OUT, can

be approximated by

From this starting point, modify the inductance to obtain the

right balance of size, cost, and output voltage ripple while

maintaining the inductor ripple current between 20% and 40%

of 1/(1 − D) times the maximum load current. Keep in mind

that the inductor saturation current must be greater than the

peak inductor current. Magnetically shielded inductors are

generally recommended, although they cost slightly more than

unshielded inductors.

I

1−

∆I_L

2









LOAD

∆V_OUT

≈

+

×

D











²

1

+ ESR²+

(

2π× f_SW× ESL

)

(12)

2



2

π× f_SW×C_OUT



Also, losses due to the inductor winding resistance reduce the

efficiency of the boost converter. This power loss is given by

where ΔI_Lis the peak-to-peak inductor ripple current, f_SWis the

switching frequency, C_OUTis the output capacitance, ESR is the

effective ESR of C_OUT, and ESL is the effective equivalent series







²



I

LOAD

P_L,W

=

×R_W

(10)



inductance of C_OUT

.

1− D

Because the output capacitor is typically greater than 40 µF, the

ESR dominates the output capacitance impedance and thus the

output voltage ripple. The use of low ESR, ceramic dielectric

capacitors is preferred, although aluminum electrolytic,

tantalum, OS-CON™ (from Sanyo), and aluminum polymer

capacitors can be used. At higher switching frequencies, the ESL

of the output capacitor may also be a factor in determining the

output voltage ripple. Multiple capacitors can be connected in

parallel to reduce the effective ESR and ESL. Keep in mind that

the capacitance of a given capacitor typically degrades with

increased temperature and bias voltage. Consult the capacitor

manufacturer’s data sheet when determining the actual

capacitance of a capacitor under certain conditions.

where P_L,Wis the power dissipation in the winding of the

inductor, and R_Wis the winding resistance.

INPUT CAPACITOR SELECTION

The bulk input capacitor provides a low impedance path for the

inductor ripple current. Capacitor C1 in Figure 1 represents a

bulk input capacitor. Choose a bulk input capacitor whose

impedance at the switching frequency is lower than the

impedance of the voltage source V_IN.

The preferred bulk input capacitor is a 10 µF to 100 µF ceramic

capacitor because it has low equivalent series resistance (ESR) and

low impedance. Aluminum electrolytic and aluminum polymer

capacitors can also be used as the bulk input capacitors. The bulk

input capacitor does not need to be placed very close to the IN

and PIN pins. Aluminum electrolytic capacitors are the cheapest

and generally have high ESR values, which increase dramatically at

temperatures less than 0°C. Some aluminum electrolytic capacitors

have ESR less than 20 mΩ, but their capacitances are generally

greater than 800 µF. Aluminum polymer capacitors are more

expensive than the aluminum electrolytic ones, but are generally

cheaper than the ceramic capacitors for the same amount of

capacitance. Polymer capacitors have relatively low ESR, with

some models having less than 10 mΩ.

Ensure that the output capacitor ripple current rating, I_COUT,RMS

is greater than

,

D

1− D

I_COUT,RMS= I_LOAD

×

(13)

DIODE SELECTION

The diode conducts the inductor current to the output capacitor

and load while the MOSFET is off. The average diode current is

the load current:

I_DIODE,AVE= I_LOAD

(14)

Regardless of the type of capacitor used, make sure the ripple

current rating of the bulk input capacitor, I_CIN,RMS, is greater than

The rms diode current in continuous conduction mode is given by

∆I_L

2

1

3

I_LOAD

1− D

I_CIN,RMS

=

×

(11)

I_DIODE,RMS

=

× 1− D

(15)

where ΔI_Lis the peak-to-peak inductor ripple current.

where D is the duty cycle.

The power dissipated in the diode is

P_DIODE= V_D× I_LOAD

In addition to the bulk input capacitor, a bypass input capacitor is

required. The function of the bypass capacitor is to locally filter the

input voltage to the ADP1621 and maintain the input voltage at a

steady value during switching transitions. The bypass capacitor is

typically a 0.1 µF or greater ceramic capacitor and should be placed

as close as possible to the IN and PIN pins of the ADP1621.

Capacitors C3 and C4 in Figure 1 represent the bypass capacitors.

(16)

where V_Dis the forward-voltage drop of the diode.

Rev. B | Page 15 of 32

ADP1621

Data Sheet

The total power dissipation determines the diode junction

temperature, which is given by

The MOSFET power dissipation due to conduction is thus







²

I

LOAD

P =

×D×R_DSON

×

(1+ K

)

(19)



C

T_J,DIODE= T_A+ P_DIODE×θ_JA

(17)

1− D



where T_J,DIODEis the junction temperature, T_Ais the ambient tem-

perature, and θ_JAis the junction-to-ambient thermal resistance

of the diode package. The diode junction temperature must not

exceed its maximum rating at the given power dissipation level.

where P_Cis the conduction power loss, and R_DSONis the MOSFET

on resistance. The variable K is a factor that models the increase

of R_DSONwith temperature:

K = 0.005/^C ×

(

T_J,MOSFET− 25^C

)

(20)

For high efficiency, Schottky diodes are recommended. The low

forward-voltage drop of a Schottky diode reduces the power losses

during the MOSFET off time, and the fast switching speed reduces

the switching losses during the MOSFET transitions. However,

for high voltage, high temperature applications where the reverse

leakage current of the Schottky diode can become significant

and degrade efficiency, use an ultrafast-recovery junction diode.

where T_J,MOSFETis the MOSFET junction temperature. Note that

multiple n-channel MOSFETs can be placed in parallel to reduce

the effective R_DSON

.

The power dissipation due to switching transition loss is

approximated by

I_LOAD

(

V_OUT+V_D

)

×

(

t_R+t_F× f_SW

)

Make sure that the diode is rated to handle the average output

load current. Many diode manufacturers derate the current

capability of the diode as a function of the duty cycle. Verify

that the diode is rated to handle the average output load current

with the minimum duty cycle. Also, ensure that the peak inductor

current is less than the maximum rated current of the diode.

1− D

P_SW

=

(21)

2

where P_SWis the switching power loss, t_Ris the MOSFET rise

time, and t_Fis the MOSFET fall time. The MOSFET rise and fall

times are functions of both the gate drive circuitry and the

MOSFET used in the application.

MOSFET SELECTION

The total power dissipation of the MOSFET is the sum of the

conduction and transition losses:

When turned on, the external n-channel MOSFET allows

energy to be stored in the magnetic field of the inductor. When

the MOSFET is turned off, this energy is delivered to the load to

boost the output voltage.

P_MOSFET= P_C+ P_SW

(22)

where P_MOSFETis the total MOSFET power dissipation. Ensure

that the maximum power dissipation is significantly less than

the maximum power rating of the MOSFET.

The choice of the external power MOSFET directly affects the

boost converter performance. Choose the MOSFET based on

the following: threshold voltage (V_T), on resistance (R_DSON),

maximum voltage and current ratings, and gate charge.

The total power dissipation also determines the MOSFET

junction temperature, which is given by

T_J,MOSFET= T_A+ P_MOSFET×θ_JA

(23)

The minimum operating voltage of the ADP1621 is 2.9 V.

Choose a MOSFET with a V_Tthat is at least 0.3 V less than the

minimum input supply voltage at PIN used in the application.

Ensure that the maximum V_GSrating of the MOSFET is at least

a few volts greater than the maximum voltage that is applied to

PIN. Ensure that the maximum V_DSrating of the MOSFET

exceeds the maximum V_OUTby at least 5 V to 10 V. Depending

on parasitics, the MOSFET may be exposed to voltage spikes that

exceed the sum of V_OUTand the forward-voltage drop of the diode.

where T_J,MOSFETis the junction temperature, T_Ais the ambient

temperature, and θ_JAis the junction-to-ambient thermal

resistance of the MOSFET package. The MOSFET junction

temperature must not exceed its maximum rating at the given

power dissipation level.

If lossless current sensing is not used, there will also be power

dissipation in the external current-sense resistor, R_CS. The power

dissipation, P_CS, in the external resistor due to conduction losses

is given by

Estimate the rms current in the MOSFET under continuous

conduction mode by







²

I

LOAD

I_LOAD

1− D

P_CS

=

×D×R_CS

(24)



I_MOSFET,RMS

=

× D

(18)

1− D



LOOP COMPENSATION

where D is the duty cycle. Derate the MOSFET current at least

20% to account for inductor ripple and changes in the forward-

voltage drop of the diode.

The ADP1621 uses external components to compensate the

regulator loop, allowing optimization of the loop dynamics for

a given application.

The step-up converter produces an undesirable right-half plane

(RHP) zero in the regulation feedback loop. This RHP zero

requires compensating the regulator such that the crossover

Rev. B | Page 16 of 32

Data Sheet

ADP1621

frequency occurs well below the frequency of the RHP zero. The

location of the RHP zero is determined by the following equation:

Once the compensation resistor, R_COMP, is known, set the zero

formed by the resistor and compensation capacitor, C_COMP, to

one-fourth of the crossover frequency, or

R_LOAD

2π×L

2

f_Z,RHP

=

(1− D

)

×

(25)

2

C_COMP

=

(31)

π× f_C× R_COMP

where f_Z,RHPis the RHP zero frequency, and R_LOADis the equivalent

load resistance or the output voltage divided by the load current.

Capacitor C2 is chosen to cancel the zero introduced by the output

capacitance ESR. Thus, C2 should be set to (see Figure 31)

To stabilize the regulator, ensure that the regulator crossover

frequency is less than or equal to one-fifth of the RHP zero

frequency and less than or equal to one-fifteenth of the switching

frequency. For an initial practical design, choose the crossover

frequency f_Cto be the lower of

ESR×C_OUT

C2 =

(32)

R_COMP

where ESR represents the ESR of C_OUT

.

For low ESR output capacitors, such as ceramic capacitors, C2

is small, generally in the range of 10 pF to 400 pF. Because of the

parasitic inductance, resistance, and capacitance of the PCB layout,

the R_COMP, C_COMP, and C2 values might need to be adjusted by

observing the load transient response of the ADP1621 to establish a

stable operating system and achieve optimal transient performance.

For most applications, R_COMPis in the range of 5 kΩ to 100 kΩ,

and C_COMPis in the range of 100 pF to 30 nF.

f_SW

(26)

f_C=

15

and

f

Z,RHP

f_C=

(27)

5

where f_Cis the crossover frequency, and f_SWis the switching

frequency.

COMP

3

REF

The regulator loop gain is

g

m

2

R

COMP

C2

V_FB

V_OUT

1

C

A_VL

=

×

(1− D

)

× g_m×| Z_COMP|×

×| Z_OUT|

(28)

COMP

n×R_CS

Figure 31. Compensation Components

where A_VLis the loop gain, V_FBis the feedback regulation

voltage (typically 1.215 V), V_OUTis the regulated output voltage,

D is the duty cycle, g_mis the error amplifier transconductance

gain (typically 300 µS), Z_COMPis the impedance of the RC network

from COMP to GND, n is the current-sense amplifier gain

(typically 9.5), R_CSis the current-sense resistance, and Z_OUTis

the impedance of the load and output capacitor. In the case of

lossless current sensing, as shown in Figure 28, R_CSis equal to the

on resistance, R_DSON, of the external power MOSFET. Otherwise,

SLOPE COMPENSATION

The ADP1621 includes a circuit that allows adjustable slope

compensation. Slope compensation is required by current-

mode regulators to stabilize the current-control loop when

operating in continuous conduction and the switching duty

cycle is greater than 50%.

Slope compensation is achieved by internally forcing a ramping

current source out of the CS current-sense pin. By placing a resistor

between the CS pin and the current sensing device (the drain of

the external MOSFET in the case of lossless current sensing or

the source of the MOSFET if a current-sense resistor is used), a

voltage is developed across the resistor that is proportional to

the slope-compensation current.

R_CSrepresents the external current-sense resistor, as shown in

Figure 29.

To determine the crossover frequency, it is important to note

that at that frequency the compensation impedance, Z_COMP, is

dominated by Resistor R_COMP, and the output impedance, Z_OUT

,

is dominated by the impedance of the output capacitor, C_OUT

When solving for the crossover frequency, the equation is

simplified to

.

To ensure stability of the current-mode control loop, use a

compensation voltage slope that is equal to or greater than one-

half of the current-sense representation of the inductor current

downslope. Therefore, it follows that

| A_VL| =

V_FB

V_OUT

1

×

(1− D

)

× g_m×R_COMP

×

=1

I_SC,PK

1−t_OFF,MIN

×

f_SW

V_OUT+V_D−V_IN

n×R_CS2π× f_C×C_OUT

2× R_S

×

>

R_CS

×

(33)

×

L

(29)

where R_Sis the slope-compensation resistor, I_SC,PKis the peak slope-

compensation current, f_SWis the switching frequency, R_CSis the

current-sense resistor, V_OUTis the regulated output voltage, V_Dis the

forward-voltage drop of the diode, V_INis the input voltage, t_OFF,MINis

the minimum off time, and L is the power-stage inductor. In the

case of lossless current sensing, R_CSis equal to the on resistance,

where f_Cis the crossover frequency, R_COMPis the compensation

resistor, and C_OUTis the output capacitance.

Solving for R_COMPgives

2

π× f_C×C_OUT×n×R_CS×V_OUT

R_COMP

=

(30)

V_FB×(1− D)× g_m

Rev. B | Page 17 of 32

ADP1621

Data Sheet

R_DSON, of the external power MOSFET. Otherwise, R_CS

represents the external current-sense resistor.

which vary from part to part and with temperature. If lossless

current sensing is used, consider that the on resistance of a

MOSFET typically increases with increasing junction temperature.

Solving for R_Sgives the slope-compensation criterion:

The peak inductor current limit also limits the maximum load

current at a given output voltage. The maximum load current,

assuming CCM operation, is given by

R_CS

×

(

V_OUT+ V_D−V_IN

)

×

(

1 − t_OFF,MIN× f_SW

)

(34)

R_S>

2 × I_SC,PK× f_SW× L

Keep in mind that the above inequality is a function of both

I_LOAD,MAX

=

(1− D

)×

ADP1621 parameters and off-chip components, the values of

which vary from part to part and with temperature. Select R_Sto

ensure current-loop stability for all possible variations.

V

_COMP,CLAMP−V_COMP,ZCT

I_SC,PK× R_S× D









−

n

1− t_OFF,MIN× f_SW

V_IN× D

2× f_SW× L





−

R_CS

After accounting for parameter variations, use values of R_Sthat

are as close to the calculated limit as possible because excessive

slope compensation reduces the benefits of current-mode control

and increases the “softness” of the current limit, as discussed in the

Current Limit section. Given a typical peak slope-compensation

current of 70 µA, R_Sshould not exceed 1.6 kΩ because the voltage

at the CS pin is typically clamped at 116 mV. It is also recom-

mended that R_Sbe greater than 20 Ω. If the calculated R_Sis greater

than 1.6 kΩ, the parameters in Equation 34, such as R_CS, f_SW, and L,

can be adjusted such that R_Sis less than 1.6 kΩ.









(36)

If the load current exceeds I_LOAD,MAX, the output voltage drops

below the desired voltage.

LIGHT LOAD OPERATION

Discontinuous Conduction Mode

With light loads, the average inductor current is small, and,

depending on the converter design, the instantaneous inductor

current may reach 0 during the time when the MOSFET is off.

This mode of operation is termed discontinuous conduction

mode. The condition for entering discontinuous conduction

mode in a boost converter is

In conclusion, the value of R_Sshould be 20 Ω ≤ R_S≤ 1.6 kΩ.

CURRENT LIMIT

The current limit in the ADP1621 limits the peak inductor

current and is achieved by the COMP voltage clamp. The peak

inductor current, I_L,PK, is given by

V

_IN×D×

2×L× f_SW

(

1− D

)

I_LOAD

<

(37)

V_COMP,CLAMP−V_COMP,ZCT

I_SC,PK× R_S× D

1−t_OFF,MIN× f_SW

−

When the instantaneous inductor current reaches 0 during the

cycle, the inductor ceases to be a current source, and ringing

can be observed in the waveforms of the MOSFET drain voltage

and the inductor current. The frequency of the ringing is the

resonant frequency of the inductor and the total capacitance

from the SW node to GND, which includes the capacitances of

the MOSFET and diode, and any parasitic capacitances from

the PCB. While adding a resistive element, such as a snubber, to

the system further dampens the resonance, it also decreases the

efficiency of the regulator.

n

(35)

I_L,PK

=

R_CS

where V_COMP,CLAMPis the COMP clamp voltage (typically 2.0 V),

_COMP,ZCTis the COMP zero-current threshold (typically 1.0 V),

n is the current-sense amplifier gain (typically 9.5), I_SC,PKis the

peak slope-compensation current (typically 70 µA), R_Sis the

slope-compensation resistor, D is the duty cycle, f_SWis the

switching frequency, t_OFF,MINis the minimum off time (typically

190 ns), and R_CSis the current-sense resistor. In the case of

V

lossless current sensing, R_CSis equal to the on resistance, R_DSON

of the external power MOSFET. Otherwise, R_CSrepresents the

external current-sense resistor.

,

Pulse-Skipping Modulation

The ADP1621 features circuitry that improves the converter

efficiency and minimizes power consumption with no load or

very light loads. When the COMP voltage drops below V_{C OMP,ZC T}

(typically 1.0 V), which can occur at sufficiently light loads, the

MOSFET is powered off until the FB voltage drops below 1.215 V.

Then, the error amplifier drives the COMP voltage higher, and

the converter resumes switching when the COMP voltage rises

above the V_COMP,ZCTvoltage. While the MOSFET is powered off,

the output capacitor supplies current to the load.

The current limit in the ADP1621 is a “soft” current limit.

When the inductor current reaches the I_L,PKlimit given in

Equation 35, the duty cycle decreases, and the output voltage

drops below the desired voltage. The I_L,PKlimit in Equation 35

then increases in response to the smaller duty cycle, D. The

larger the slope-compensation resistor, R_S, the larger the effect

on I_L,PKfor an incremental decrease in D. This behavior results

in a “soft” current limit for the ADP1621. Use values of R_Sthat are

as close as possible to the calculated limit derived from

With light loads, the COMP voltage hovers around 1.0 V, and

short periods of switching are followed by long periods of the

MOSFET being powered off. This pulse-skipping modulation

operation improves converter efficiency by reducing the number of

switching cycles and therefore reducing the gate drive current and

the switching transition power loss.

Equation 34. If high-precision current limiting is required,

consider inserting a fuse in series with the inductor.

Also, keep in mind that the current limit is a function of both

ADP1621 parameters and off-chip components, the values of

Rev. B | Page 18 of 32

Data Sheet

ADP1621

Given the minimum on time of the ADP1621, pulse-skipping

modulation is also a requirement to maintain output voltage

regulation with light loads. During the short switching periods

of pulse-skipping modulation, the MOSFET is turned on for the

minimum on time each cycle, storing just enough energy in the

inductor to charge the output capacitor. During the long period

when the MOSFET is off, no current flows through the inductor,

and the light load current is supplied by the output capacitor.

RECOMMENDED COMPONENT MANUFACTURERS

Table 5.

Vendor

Components

AVX Corporation

Central Semiconductor Corp.

Coilcraft, Inc.

Capacitors

Diodes

Inductors

Diodes, Inc.

Diodes

International Rectifier

Murata Manufacturing Co., Ltd.

ON Semiconductor

Rubycon Corporation

Sanyo

Diodes, MOSFETs

Capacitors, inductors

Diodes, MOSFETs

Capacitors

Sumida

Inductors

Taiyo Yuden, Inc.

Toko America, Inc.

United Chemi-Con, Inc.

Vishay Siliconix

Capacitors, inductors

Inductors

Capacitors

Diodes, MOSFETs, resistors, capacitors

Rev. B | Page 19 of 32

ADP1621

Data Sheet

LAYOUT CONSIDERATIONS

Layout is important for all switching regulators, but is par-

ticularly important for regulators with high switching frequencies.

To achieve high efficiency, good regulation, and stability, a well-

designed printed circuit board layout is required. A sample PCB

layout for the standard boost converter circuit shown in Figure 33

is given in Figure 32.

•

Avoid routing high impedance traces near any node con-

nected to the switch node (the MOSFET drain) or near

Inductor L1 to prevent radiated switching-noise injection.

Add an extra copper plane at the connection of the MOSFET

drain and the anode of the diode to help dissipate the heat

generated by losses in those components.

Follow these guidelines when designing printed circuit boards:

Avoid ground loops by having one central ground node on the

PCB. If this is impractical, place the power ground with high

current levels physically closer to the PCB ground terminal.

The analog, low current-level ground should be placed farther

from the PCB ground terminal.

•

Keep the low ESR bypass input capacitor of 0.1 µF or higher

close to IN/PIN and GND.

•

Keep the high current path from Bulk Input Capacitor C1

through Inductor L1 and MOSFET M1 to PGND as short

as possible.

•

Minimize the length of the PCB trace between the GATE

pin and the MOSFET gate. The parasitic inductance in this

PCB trace can give rise to excessive voltage ringing at the

MOSFET gate and drain, as well as the regulator output. It

is recommended to add 5 Ω of resistance for every inch of

PCB trace. This helps to reduce the overshoot and ringing at

the drain and the output. However, this added resistance

increases the rise and fall times of the MOSFET; thus, the

switching loss in the MOSFET is increased.

•

Keep the high current path from Bulk Input Capacitor C1

through Inductor L1, Diode D1, and Output Capacitor C_OUT

to PGND as short as possible. Place C_OUTas close to PGND

as possible to reduce ground bouncing.

•

Keep high current traces as short and wide as possible to

minimize parasitic series inductance, which causes spiking

and electromagnetic interference (EMI).

To minimize switching noise, the drain of the power MOSFET

should be placed very close to the inductor, and the source

of the MOSFET (or the bottom side of the sense resistor)

should be connected directly to the power GND plane. Use

wide copper traces on the drain and on the source of the

MOSFET to minimize parasitic inductance and resistance.

Parasitic inductance can lead to excessive ringing during

switching transitions, and parasitic resistance reduces the

converter efficiency. Make sure that the MOSFET selected

is capable of handling the total power loss (conduction plus

transition losses) in the application circuit.

•

Place the feedback resistors as close to FB as possible to

prevent high frequency switching-noise injection.

Place the top of the upper feedback resistor, R1, as close

as possible to the top of C_OUTfor optimum output voltage

sensing.

•

If a current-sense resistor is connected between the source

of the MOSFET and PGND, ensure that the capacitance from

CS to PGND is minimized.

Place the compensation components as close as possible

t o C OM P.

V

IN

C1

L1

GND

D1

C

OUT1

M1

C

OUT2

V

OUT

GATE

OUT3

GND

ADP1621

SDSN

R_FREQ

REMOTE OUTPUT

SENSING

VIAS TO GND PLANE

VIAS TO 2ND LAYER

Figure 32. PCB Layout of the Circuit Shown in Figure 33 (2-layer PCB)

Rev. B | Page 20 of 32

Data Sheet

ADP1621

EFFICIENCY CONSIDERATIONS

The efficiency, η, of a dc/dc converter is given by

•

The power dissipation in the winding resistance of the

power stage inductor.

P_OUT

P_IN

η =

×100%

(38)

I





²

LOAD

P_{L, W}

=

×R_W

(42)





1− D



where P_OUTis the output power, and P_INis the input power to the

converter. While switching regulators are ideally lossless converters

of power, the nonideal characteristics of regulator components

degrade the efficiency of the regulator.

The supply current to the ADP1621 IC, which includes the

quiescent current and the gate driver charging current. The

power dissipation due to gate charging loss is approximated by

The primary sources of power dissipation in the regulator include

P_G= V_PIN×Q_G× f_SW

(43)

•

The power dissipation in the external power MOSFET due

to conduction and switching losses.

where P_Gis the gate charging power loss, V_PINis the voltage at

the PIN pin, Q_Gis the MOSFET total gate charge, and f_SWis

the converter switching frequency. Therefore, the total power

dissipation in the IC itself is given by

P_MOSFET= P_C+ P_SW

(39)

I











LOAD

=

×D×R

×(1+ K) +







DSON



(

)

(44)

P_IC= P_G+ V_IN× I_Q

1− D







=

(

V_PIN×Q_G× f_SW

)

+

(

V_IN× I_Q

)

I_LOAD

1− D









(V_OUT+V_D)×

×(t_R+t_F)× f_SW

where P_ICis the total power dissipated in the IC, I_Qis the

quiescent current, and V_INis the voltage at the IN pin.

2









The secondary sources of power dissipation in the regulator include

•

The power dissipation in the external current-sense

resistor if lossless current sensing is not used.

•

The power dissipation in the ESR of the input and output

capacitors.

²

I







LOAD

P_CS

=

×D×R_CS

(40)

(41)

•

Inductor core losses due to hysteresis and eddy currents.



1− D



The power dissipation in the external diode.

P_DIODE=V_D×I_LOAD

Rev. B | Page 21 of 32

ADP1621

Data Sheet

EXAMPLES OF APPLICATION CIRCUITS

The next step is to choose a Schottky diode. The average

STANDARD BOOST CONVERTER—

DESIGN EXAMPLE

and rms diode currents are calculated to be 1.0 A and 1.3 A,

respectively, using Equations 14 and 15. A Vishay SSA33L

Schottky diode meets the current and thermal requirements

and is an excellent choice.

The example covered here is for the ADP1621 configured as a

standard boost converter, as shown in Figure 33, where lossless

current sensing is employed. The design parameters are V_IN

3.3 V, V_OUT= 5 V, and a maximum load current of 1 A.

=

The power MOSFET must be chosen based on threshold voltage

(V_T), on resistance (R_DSON), maximum voltage and current ratings,

and gate charge. The rms current through the MOSFET is given

by Equation 18 as 1.1 A. The Vishay Si7882DP is a 20 V n-channel

power MOSFET that meets the current and thermal requirements.

It comes in a PowerPAK® package and offers low R_DSONand gate

charge. At V_GS= 2.5 V, the on resistance, R_DSON, is 8 mΩ.

To begin this design, a switching frequency of 600 kHz is chosen

(by setting R_FREQto 32 kΩ, see Figure 30) so that a small inductor

and small output capacitors can be used. The duty cycle is cal-

culated from Equation 1 to be 0.4, given a forward-voltage drop of

0.5 V for the Schottky diode. The feedback resistors are calculated

to be R1 = 35.7 kΩ and R2 = 11.5 kΩ from Equation 4.

The loop-compensation components are chosen to be R_COMP

=

Assuming that the inductor ripple is 30% of 1/(1 − D) times

the maximum load current, the inductor size is calculated to be

about 4.4 µH, according to Equation 9. The small, magnetically

shielded 4.7 µH Toko FDV0630-4R7M inductor is selected.

Because ceramic capacitors have very low ESR (a few milliohms),

a 47 µF/6.3 V Murata GRM31CR60J476M ceramic capacitor is

chosen for the input capacitor. The output voltage ripple for a

given C_OUT, ESR, and ESL can be found by solving Equation 12.

By choosing an output voltage ripple equal to 1% of the output

voltage, Equation 12 yields that the minimum C_OUTrequired is

100 µF and the maximum ESR required is 25 mΩ. Other com-

binations of capacitance and ESR are possible by choosing a

much larger C_OUTand a larger ESR. In this case, a small 1 µF

ceramic capacitor and two 150 µF Sanyo POSCAP™ capacitors

are selected. The low ESR ceramic capacitor helps to suppress

the high frequency overshoot at the output. POSCAP has low

ESR and high capacitance in a relatively small package. Ceramic

capacitors can also be used. Generally, bigger ceramic capacitors

are more expensive.

9.1 kΩ and C_COMP= 1.7 nF from Equations 30 and 31, respectively.

A roll-off capacitor of C2 = 120 pF is also added. The slope-

compensation resistor is set to be R_S= 80 Ω from Equation 34.

Lastly, given the chosen components, the peak inductor current

as set by the current limit circuitry is given by Equation 35 as

I

_L,PK= 12 A. Thus, the maximum load current, assuming CCM

operation, is given by Equation 36 as I_LOAD,MAX= 8 A, which is

safely above the 1.0 A load current requirement for this design

example. Note that the current limit is a strong function of R_CS,

which can vary part to part and with temperature. In addition,

note that R_CScan be implemented with an external current-

sense resistor or with the R_DSONof a MOSFET. Variations in R_CS

and the other parameters in Equations 35 and 36 must be taken

into account if precise current limiting is necessary. Due to the

parasitic resistance of PCB traces, R_Smight need to be adjusted

on the actual circuit board to achieve the desired current limit.

Keep in mind that R_Smust be less than 1.6 kΩ. Using a MOSFET

with a different R_DSONor adjusting R_CScan also set the current

limit to the desired level.

V

= 3.3V

IN

L1

4.7µH

V

= 5V

OUT

1A

D1

C3

1µF

10V

C4

0.1µF

10V

IN

C

1µF

10V

C

10µF

10V

C

OUT3

R1

OUT1

OUT2

R

80Ω

S

35.7kΩ

150µF

6.3V

×2

1%

CS

ADP1621

R2

11.5kΩ

1%

SDSN

M1

GATE

PGND

COMP

FREQ

R

COMP

9.09kΩ

FB

GND

C2

120pF

C

R

C1

47µF

6.3V

COMP

1.8nF

FREQ

31.6kΩ

1%

AGND

f_OSC= 600kHz

C1 = MURATA GRM31CR60J476M

M1 = VISHAY Si7882DP

D1 = VISHAY SSA33L

C

= SANYO POSCAP 6TPE150M

OUT3

L1 = TOKO FDV0630-4R7M

Figure 33. Typical Boost Converter Application Circuit

Rev. B | Page 22 of 32

Data Sheet

ADP1621

voltage reaches 12 V, the quiescent current stops flowing

BOOTSTRAPPED BOOST CONVERTER

through D2 and is supplied by the output. Keep in mind that the

dynamic supply current to PIN increases as the switching fre-

quency increases because more gate drive is needed for a higher

switching frequency. Therefore, R3 needs to be set appropriately.

The PIN supply current can be approximated by

The inputs of the ADP1621 can be driven from the step-up

converter output voltage to improve efficiency for low input

voltages. For low input voltages, bootstrapped operation improves

efficiency with heavy loads by increasing the available gate drive

voltage, thus reducing the on resistance of the MOSFET. However,

because the internal circuitry is driven from IN, the ADP1621

quiescent current and gate drive current supplied from the input

increases due to the step-up ratio and the conversion efficiency loss.

I_PIN= f_SW×Q_G

(45)

where I_PINis the PIN supply current, f_SWis the switching frequency,

and Q_Gis the gate charge of a particular MOSFET.

The circuit shown in Figure 1 shows a bootstrapped boost con-

verter, where V_IN= 3.3 V and V_OUT= 5 V. To ensure that the circuit

starts, make sure that the input voltage minus the forward-voltage

drop of the diode is greater than the UVLO voltage and the gate

threshold voltage of the MOFSET. In this example, the MOSFET

has a gate threshold voltage of 2.5 V. The regulator shown in

Figure 1 is very similar to that shown in Figure 33, which is a

standard boost without bootstrapping. Because the same MOSFET

and inductor are used in both circuits and the input and output

conditions are the same, the compensation components remain

unchanged.

An alternative implementation to Figure 34 is shown in Figure 35,

where an NPN transistor is used to supply the necessary current

to the input PIN at various loads, but the gate drive voltage is

limited to approximately 4.8 V (one diode drop below the

voltage at IN). Signal Diodes D2 and D3 help to provide the

necessary quiescent current to start the ADP1621. Once the

ADP1621 starts, the current stops flowing through these two

diodes because the voltages at PIN and IN are approximately

4.8 V and 5.5 V, respectively. One advantage of this technique

is that Q1 provides enough current to the gate driver at any

switching frequency with a wide range of MOSFETs that have

different gate charge specifications.

Figure 34 shows a bootstrapped application circuit for output

voltages greater than 5.5 V. In this case, the output is 12 V.

Notice that a resistor, R3, of 700 Ω is placed between V_OUTand

the IN and PIN pins to limit the input currents because the IN

and PIN pins are regulated to 5.5 V. A diode, D2, is placed between

Notice that the output capacitor, C_OUT2in Figure 34 and Figure 35,

is a large aluminum electrolytic capacitor, both in physical size

and capacitance. Such capacitors are very cheap relative to

ceramic capacitors (such as Sanyo POSCAP) or aluminum

polymer capacitors. The ADP1621 can work with a wide range

of capacitor types.

V_INand the IN/PIN pins to supply the necessary quiescent current

to start the ADP1621. Once the ADP1621 starts and the output

Rev. B | Page 23 of 32

ADP1621

Data Sheet

V

= 3.3V

IN

L1

10µH

D2

R3

700Ω

V

= 12V

1A

OUT

D1

C3

1µF

10V

C4

0.1µF

10V

C

OUT2

OUT1

IN

R1

10µF

16V

×2

330µF

25V

×2

R

200Ω

S

88.7kΩ

1%

CS

ADP1621

R2

10kΩ

1%

SDSN

M1

GATE

PGND

COMP

FREQ

R

COMP

FB

51.5kΩ

GND

C2

220pF

C

R

C1

COMP

FREQ

47µF

6.3V

330pF

31.6kΩ

1%

AGND

M1 = IRF7470

f_OSC= 600kHz

C1 = MURATA GRM31CR60J476M

C

= RUBYCON 25ZL330M8x16 D1 = VISHAY SSC53L

OUT2

L1 = COILCRAFT MSS1260-103ML

D2 = SIGNAL DIODE

Figure 34. Bootstrapped Application Circuit for V_OUT> 5.5 V

V

= 3.3V

IN

L1

10µH

D3

D2

Q1

R3

1.5kΩ

V

= 12V

1A

OUT

D1

C3

1µF

10V

C4

0.1µF

10V

C

OUT2

OUT1

IN

R1

10µF

16V

×2

330µF

25V

×2

R

200Ω

S

88.7kΩ

1%

CS

ADP1621

R2

10kΩ

1%

SDSN

M1

GATE

PGND

COMP

FREQ

R

COMP

FB

51.5kΩ

GND

C2

220pF

C

R

C1

COMP

FREQ

47µF

6.3V

330pF

31.6kΩ

1%

AGND

M1 = IRF7470

f_OSC= 600kHz

C1 = MURATA GRM31CR60J476M

C

= RUBYCON 25ZL330M8x16 D1 = VISHAY SSC53L

OUT2

L1 = COILCRAFT MSS1260-103ML

Q1 = SIGNAL NPN TRANSISTOR

D2, D3 = SIGNAL DIODE

Figure 35. Bootstrapped Application Circuit for V_OUT> 5.5 V

Rev. B | Page 24 of 32

Data Sheet

ADP1621

Low Input and High Output Boost Converter

with a single resistor, as shown in Figure 38. When there is a

wide input voltage range, it is sometimes desirable to use the

pass NPN transistor, as shown in Figure 37. If the input voltage

range is narrow, a single resistor connecting to the IN and PIN

pins is sufficient, as shown in Figure 38. In Figure 37, Resistor R3

limits the current going into IN, and there is power loss in this

resistor. The voltages at IN and PIN are both clamped to about

5.5 V, which can rise to as high as 5.9 V when the shunt current

is 30 mA. Refer to Figure 9 for the I-V characteristics of the

shunt regulators. Ensure that Resistor R3 is physically large

enough to handle the power dissipation. For switch-node

voltages higher than 30 V, a current-sense resistor is needed and

the CS pin senses the voltage across the sense resistor.

Figure 36 shows a typical application boost converter circuit

that operates at a switching frequency of 200 kHz with V_IN= 5 V

and V_OUT= 30 V with a 1 A load. The duty cycle for this circuit

is about 83%. A higher switching frequency can be selected, but

the switching power loss in the MOSFET increases and a bigger

MOSFET is needed. For switch-node voltages greater than 30 V,

a sense resistor, R_CS, is needed because the absolute maximum

voltage at CS is 33 V.

High Input Voltage Boost Converter Circuit

Input voltages higher than 5.5 V are possible with the addition

of a resistor and an NPN transistor, as shown in Figure 37, or just

V

= 5V

IN

L1

7.8µH

V

= 30V

OUT

1A

D1

C3

1µF

10V

C4

0.1µF

10V

R1

IN

C

1µF

100V

C

OUT3

OUT1

OUT2

4.7µF

50V

115kΩ

330µF

50V

×2

1%

FB

R2

ADP1621

4.87kΩ

1%

SDSN

M1

GATE

CS

COMP

FREQ

R

909Ω

R

S

CS

3mΩ

R

COMP

PGND

1.6MΩ

GND

C2

120pF

C1

C

R

FREQ

100kΩ

1%

COMP

20pF

47µF

6.3V

×2

AGND

f_OSC= 200kHz

C1 = MURATA GRM31CR60J476M

M1 = VISHAY SUD50N06-07L

C

= MURATA GRM31CR72A10

= MURATA GRM55ER71H475K D1 = IRF 15TQ060

= RUBYCON 50ZL330M10x23 L1 = COILCRAFT DO501DH-782ML

OUT1

OUT2

OUT3

Figure 36. Low Input, High Output Boost Converter

V

= 8V TO 15V

IN

R3

700Ω

L1

8.2µH

Q1

C3

1µF

10V

V

= 30V

1A

C4

0.1µF

10V

OUT

D1

R1

IN

C

1µF

100V

C

OUT3

OUT1

OUT2

4.7µF

50V

115kΩ

330µF

50V

×2

1%

FB

R2

ADP1621

SDSN

4.87kΩ

1%

M1

GATE

CS

COMP

FREQ

R

S

CS

R

COMP

2MΩ

402Ω 3mΩ

PGND

GND

C2

120pF

C1

C

R

COMP

220pF

FREQ

34.8kΩ

22µF

16V

×2

AGND

f_OSC= 560kHz

C1 = MURATA GRM32ER61C226K

M1 = IRF7470

C

= MURATA GRM31CR72A105K Q1 = SIGNAL NPN TRANSISTOR

= MURATA GRM55ER71H475K D1 = MBRB7H50

OUT1

OUT2

OUT3

= RUBYCON 50ZL220M10x23

L1 = COILCRAFT MSS1260-822ML

Figure 37. High Input Voltage and High Output Voltage Converter

Rev. B | Page 25 of 32

ADP1621

Data Sheet

V

= 12V

IN

R3

649Ω

L1

15µH

V

= 40V

OUT

1A

D1

C3

1µF

10V

C4

0.1µF

10V

R1

IN

C

1µF

100V

C

OUT3

OUT1

OUT2

4.7µF

50V

324kΩ

220µF

63V

×2

1%

FB

R2

10.2kΩ

1%

ADP1621

SDSN

M1

GATE

CS

COMP

FREQ

R

S

CS

R

COMP

2MΩ

442Ω 0.01Ω

PGND

GND

C2

120pF

C1

C

R

COMP

18pF

FREQ

34.8Ω

22µF

16V

×2

AGND

f_OSC= 560kHz

C1 = MURATA GRM32ER61C226K

M1 = VISHAY Si7478DP

C

= MURATA GRM31CR72A105K

= MURATA GRM55ER71H475K D1 = MBRB7H50

= RUBYCON 63ZL220M10x23 L1 = COILCRAFT MSS1278-153ML

OUT1

OUT2

OUT3

Figure 38. High Input Voltage and High Output Voltage Converter

Rev. B | Page 26 of 32

Data Sheet

ADP1621

load current during this time. When the MOSFET turns off and

the diode turns on, the energy in L1 and L2 is released to charge

the output capacitor, C_OUT, and the coupling capacitor, C5, as

well as to supply current to the load.

SEPIC CONVERTER CIRCUIT

A single-ended primary inductance converter (SEPIC) topology

is shown in Figure 39. This topology is useful for an unregulated

input voltage, where the regulated output voltage falls within the

input voltage range.

LOW VOLTAGE POWER-INPUT CIRCUIT

The input and output are dc-isolated by a coupling capacitor,

C5. L1 and L2 are coupled inductors with a 1:1 turn ratio, which

saves space on the PCB. In steady state, the average voltage across

C5 is the input voltage. When the MOSFET turns on and the

diode turns off, the input voltage provides energy to L1, and C5

provides energy to L2. The output capacitor, C_OUT, supplies the

The ADP1621 can be configured to run from a low voltage

(as low as 1 V) power input. The power source generally needs

to have a high current capability, such as a fuel cell. Figure 40

illustrates such an application, where the voltage of the power

input is 1 V and the voltage of the chip supply to the IN and

PIN pins is provided by an auxiliary low power source.

V

= 3V TO 5.5V

IN

V

= 3.3V

L2

2.4µH

OUT

2A

D1

L1

C3

1µF

10V

C4

0.1µF

10V

2.4µH

IN

C

OUT2

OUT1

1µF

10V

R

S

150µF

6.3V

×3

80Ω

CS

C5

10µF

10V

ADP1621

SDSN

X5R

M1

GATE

PGND

R1

COMP

FREQ

17.4kΩ

1%

R

COMP

FB

26kΩ

GND

R2

10kΩ

1%

C2

33pF

C1

C

1.2nF

R

22µF

10V

×2

COMP

FREQ

65kΩ

AGND

f_OSC= 325kHz

C1 = MURATA GRM332ER61A226K

M1 = VISHAY Si7882DP

C

= SANYO POSCAP 6TPE150MI D1 = VISHAY SSC53L

OUT2

C5 = MURATA GRM21BR61A106K

L1, L2 = COUPLED INDUCTORS, 1:1 RATIO, BH ELECTRONICS BH510-1006

Figure 39. A SEPIC DC/DC Converter

V

= 1V

IN

L1

2.2µH

V

= 2.9V TO 5.5V

CC

V

= 5V

OUT

1A

D1

C3

1µF

10V

C4

0.1µF

10V

IN

C

OUT3

R1

OUT1

OUT2

R

249Ω

S

35.7kΩ

1µF

10V

10µF

6.3V

150µF

6.3V

×2

1%

CS

ADP1621

R2

11.5kΩ

1%

SDSN

M1

GATE

PGND

COMP

FREQ

R

COMP

9.4kΩ

FB

GND

C2

260pF

C1

C

R

FREQ

31.6kΩ

1%

COMP

56nF

100µF

X5R

6.3V

AGND

f_OSC= 600kHz

C1 = MURATA GRM32ER60J107ME20 M1 = VISHAY Si7882DP

C

= MURATA GRM21BR60J106K D1 = MBRD835L

= SANYO POSCAP 6TPE150MI L1 = TOKO FDV0630-2R2M

OUT2

OUT3

Figure 40. Low Voltage Power-Input Application Circuit

Rev. B | Page 27 of 32

ADP1621

Data Sheet

Another method for driving the LEDs is shown in Figure 42,

where the PWM signal is filtered by an RC low-pass filter and is

fed to the FB node. The effective FB voltage at the bottom of the

LED string is modulated in an analog manner by the PWM

duty cycle. Thus, the average current through the LEDs is

modulated accordingly. Unlike the case depicted in Figure 41, a

higher duty cycle produces a lower average LED current using

the filtered PWM scheme in Figure 42. The advantage of this

circuit is that the PWM frequency can be in the range between

90 Hz and 100 kHz, and the duty cycle can be between 5% and

95%. The disadvantage of this method is that the forward

current through the LEDs is directly modified to control the

brightness of the LEDs. Because the wavelength of the light

emitted from an LED is a weak function of its forward current,

perfect color purity across the entire dimming range cannot be

guaranteed.

LED DRIVER APPLICATION CIRCUITS

The ADP1621 can be used as an LED driver. Two LED application

circuits are shown in Figure 41 and Figure 42, where each circuit

is driving 20 white LEDs in series. Each white LED has a typical

current of 150 mA at a typical forward voltage of 4.0 V, with a

maximum voltage of 4.5 V over the temperature range of −40°C

to +125°C.

Two methods for dimming the brightness of the LEDs are

shown in Figure 41 and Figure 42. In Figure 41, a PWM signal

is fed to the SDSN pin to turn the ADP1621 controller on and

off. As a result, the LED current is turned on and off, and the

average LED current is dependent on the PWM duty cycle. The

advantage of this method is that no current flows through the

LEDs during the PWM off cycle. In addition, when the ADP1621 is

on, the forward current through the LEDs is constant, which

guarantees constant color emission across the entire dimming

range. Because the soft start period is fixed at 2048 oscillator

cycles, the PWM frequency range is limited.

If PCB space is a constraint, smaller inductors can be selected

for the circuits shown in Figure 41 and Figure 42. For example,

a 4.7 µH inductor can be used, and a 200 kHz switching fre-

quency can be selected. However, with this small inductor, the

system operates in DCM, which is slightly less efficient than

operating in CCM.

As shown in Figure 41, because the natural switching frequency

chosen is 400 kHz, the useful PWM frequency range is 90 Hz to

195 Hz. However, when driving fewer LEDs, the ADP1621 can

be set to run at a faster frequency, increasing the maximum PWM

frequency. The PWM duty cycle can be between 5% and 95%. A

higher PWM duty cycle produces a higher average LED current.

Rev. B | Page 28 of 32

Data Sheet

ADP1621

V

= 10V TO 16V

IN

R

800Ω

B

L1

33µH

D1

100V

C4

0.1µF

C3

0.1µF

V

OUT

IN

C

OUT

150mA

1µF

100V

×3

M1

GATE

100V

20

LEDS

ADP1621

SDSN

PWM

R

S

800Ω

CS

FB

COMP

FREQ

R

COMP

PGND

GND

101kΩ

R

R1

8Ω

1/4W

C2

18pF

CS

3mΩ

C

R

FREQ

50kΩ

1%

C1

2.2µF

25V

COMP

390nF

AGND

f_OSC= 400kHz

C1 = MURATA GRM31MR71E225K

= MURATA GRM31CR72A105K D1 = IRF 10MQ100

M1 = VISHAY Si4482DY

C

OUT

L1 = COILCRAFT MSS1038-333NL

Figure 41. 20-Series LED Driver with PWM at SDSN

V

= 10V TO 16V

IN

R

800Ω

B

L1

C4

0.1µF

33µH

D1

100V

C3

0.1µF

V

OUT

IN

C

OUT

1µF

150mA

100V

×3

M1

GATE

100V

R5

18kΩ

20

ADP1621

R

LEDS

S

800Ω

SDSN

PWM =

CS

FB

R2

R3

R4

0V TO 4V

10kΩ

22.9kΩ 10kΩ

COMP

FREQ

R

COMP

PGND

101kΩ

GND

R

3m

R1

C5

C1

2.2µF

25V

C2

10pF

CS

8Ω 0.1µF

C

R

FREQ

COMP

390nF

1/4W

6.3V

50kΩ

1%

AGND

f_OSC= 400kHz

C1 = MURATA GRM31MR71E225K

M1 = VISHAY Si4482DY

C

= MURATA GRM31CR72A105K D1 = IRF 10MQ100

OUT

L1 = COILCRAFT MSS1038-333NL

Figure 42. 20-Series LED Driver with Filtered PWM

Rev. B | Page 29 of 32

ADP1621

Data Sheet

RELATED PARTS

Table 6.

Part Number

Description

Comments

ADP1612

ADP1613

ADP1614

Current-mode PWM step-up controller 1.4 A, internal FET R_DSONis 130 m Ω nominal, V_IN= 1.8 V to 5.5 V, V_OUTMAXis 20 V

Current-mode PWM step-up controller 2.0 A, internal FET R_DSONis 130 m Ω nominal, V_IN= 2.5 V to 5.5 V, V_OUTMAXis 20 V

Current-mode PWM step-up controller 4.0 A, internal FET R_DSONis 50 m Ω nominal, V_IN= 2.5 V to 5.5 V, V_OUTMAXis 20 V

Rev. B | Page 30 of 32

Data Sheet

ADP1621

OUTLINE DIMENSIONS

3.10

3.00

2.90

10

1

6

5

5.15

4.90

4.65

3.10

3.00

2.90

PIN 1

IDENTIFIER

0.50 BSC

0.95

0.85

0.75

15° MAX

1.10 MAX

0.70

0.55

0.40

0.15

0.05

0.23

0.13

6°

0°

0.30

0.15

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-BA

Figure 43. 10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

ORDERING GUIDE

Package

Option

Ordering

Quantity

Model¹

Temperature Range

−40°C to +125°C

Package Description

Branding

ADP1621ARMZ-R7

ADP1621-EVAL

10-Lead Mini Small Outline Package [MSOP]

Evaluation Board

RM-10

1,000

1

L3M

¹Z = RoHS Compliant Part.

Rev. B | Page 31 of 32

ADP1621

NOTES

Data Sheet

registered trademarks are the property of their respective owners.

D06090-0-6/12(B)

Rev. B | Page 32 of 32


型号：	ADP162
厂家：	ADI
描述：	Constant-Frequency, Current-Mode Step-Up DC/DC Controller
文件：	总32页 (文件大小：598K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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