ADP171AUJZ-R7 [ADI]
300 mA, Low Quiescent Current, CMOS Linear Regulators; 300毫安，低静态电流， CMOS线性稳压器
| 型号： | ADP171AUJZ-R7 |
| 厂家： | 
ADI |
| 描述： | 300 mA, Low Quiescent Current, CMOS Linear Regulators |
| 文件： | 总20页 (文件大小：538K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
300 mA, Low Quiescent Current,
CMOS Linear Regulators
ADP170/ADP171
TYPICAL APPLICATION CIRCUITS
FEATURES
Maximum output current: 300 mA
Input voltage range: 1.6 V to 3.6 V
Low quiescent current
V
V
IN
OUT
1
2
3
VIN
5
VOUT
C1
C2
ADP170
GND
I
I
GND = 23 μA with 0 mA load
GND = 170 μA with 300 mA load
ON
EN
NC
4
Low shutdown current: <1 μA
OFF
Low dropout voltage: 66 mV at 300 mA load
Output voltage accuracy: 1ꢀ
Up to 31 fixed-output voltage options available from 0.8 V to
3.0 V
Figure 1. ADP170 with Fixed Output Voltage, 1.8 V
V
= 2.3V
IN
V
= 1.8V
Adjustable-output voltage range
0.8 V to 3.0 V (ADP171)
OUT
1
2
3
VIN
5
4
VOUT
ADJ
C
C
OUT
IN
1µF
ADP171
GND
1µF
Accuracy over line, load, and temperature: 3ꢀ
Stable with small 1 μF ceramic output capacitor
PSRR performance of 70 dB at 10 kHz and 73 dB at 1 kHz
Low noise: 30 μV rms at VOUT = 0.8 V
Current limit and thermal overload protection
Logic-controlled enable
R1
ON
EN
OFF
R2
Figure 2. ADP171 with Adjustable Output Voltage
Compact 5-lead TSOT package
APPLICATIONS
Mobile phones
Digital camera and audio devices
Portable and battery-powered equipment
DSP/FPGA/microprocessor supplies
Post dc-dc regulation
GENERAL DESCRIPTION
The ADP170/ADP171 are low voltage input, low quiescent
current, low-dropout (LDO) linear regulators that operate from
1.6 V to 3.6 V and provide up to 300 mA of output current. The
low 66 mV dropout voltage at 300 mA load improves efficiency
and allows operation over a wide input voltage range. The low
23 μA of quiescent current at a 0 mA load makes the ADP170/
ADP171 ideal for battery-operated portable equipment.
performance and occupy minimal board space. Compared with
commodity types of LDOs, the ADP170/ADP171 provide 20 dB
to 40 dB better power supply rejection ratio (PSRR) at 100 kHz,
making the ADP170/ADP171 an ideal power source for analog-
to-digital converter (ADC) mixed-signal processor systems and
allowing use of smaller size bypass capacitors. In addition, low
output noise performance without the need for an additional
bypass capacitor further reduces printed circuit board (PCB)
component count.
The ADP170 is capable of 31 fixed-output voltage options, ranging
from 0.8 V to 3.0 V. ADP171 is an adjustable version, which allows
output voltages that range from 0.8 V to 3.0 V via an external
divider. The ADP170/ADP171 are optimized for stable operation
with small 1 μF ceramic output capacitors. Ideal for powering
digital processors, the ADP170/ADP171 exhibit good transient
Short-circuit protection and thermal overload protection circuits
prevent damage in adverse conditions. The ADP170/ADP171
are available in tiny 5-lead TSOT for the smallest footprint
solution to meet a variety of portable power applications.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2009–2010 Analog Devices, Inc. All rights reserved.
ADP170/ADP171
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 11
Applications Information.............................................................. 12
Capacitor Selection .................................................................... 12
Undervoltage Lockout ............................................................... 13
Enable Feature ............................................................................ 13
Current Limit and Thermal Overload Protection ................. 14
Thermal Considerations............................................................ 14
Printed Circuit Board Layout Considerations ....................... 16
Outline Dimensions....................................................................... 17
Ordering Guide .......................................................................... 17
Applications....................................................................................... 1
Typical Application Circuits............................................................ 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Input and Output Capacitor, Recommended Specifications........4
Absolute Maximum Ratings............................................................ 5
Thermal Data................................................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
REVISION HISTORY
5/10—Rev. A to Rev. B
Changes to Figure 1 and Figure 2................................................... 1
Updated Outline Dimensions....................................................... 17
Changes to Ordering Guide .......................................................... 17
6/09—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Updated Outline Dimensions....................................................... 17
1/09—Revision 0: Initial Version
Rev. B | Page 2 of 20
ADP170/ADP171
SPECIFICATIONS
VIN = (VOUT + 0.4 V) or 1.6 V (whichever is greater), EN = VIN, IOUT = 10 mA, CIN = COUT = 1 μF, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Symbol
VIN
Conditions
Min
Typ
23
Max
Unit
V
INPUT VOLTAGE RANGE
OPERATING SUPPLY CURRENT1
TJ = −40°C to +125°C
1.6
3.6
IGND
IOUT = 0 μA
IOUT = 0 μA, TJ = −40°C to +125°C
IOUT = 1 mA
IOUT = 1 mA, TJ = −40°C to +125°C
IOUT = 150 mA
IOUT = 150 mA, TJ = −40°C to +125°C
IOUT = 300 mA
IOUT = 300 mA, TJ = −40°C to +125°C
EN = GND
EN = GND, VIN = 3.6 V, TJ = −40°C to +85°C
EN = GND, VIN = 3.6 V, TJ = 85°C to 125°C
IOUT = 10 mA
1 mA < IOUT < 300 mA, VIN = (VOUT + 0.5 V) to 3.6 V
1 mA < IOUT < 300 mA, VIN = (VOUT + 0.5 V) to 3.6 V,
TJ = −40°C to +125°C
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
%
60
50
100
210
260
130
170
0.1
SHUTDOWN CURRENT
IGND-SD
2
25
+1
+2
+3
FIXED-OUTPUT VOLTAGE ACCURACY
VOUT
−1
−2
−3
%
%
ADJUSTABLE-OUTPUT VOLTAGE
ACCURACY (ADP171)2
VADJ
IOUT = 10 mA
1 mA < IOUT < 300 mA, VIN = (VOUT + 0.5 V) to 3.6 V
1 mA < IOUT < 300 mA, VIN = (VOUT + 0.5 V) to 3.6 V,
TJ = −40°C to +125°C
0.495 0.5
0.490
0.485
0.505
0.510
0.515
V
V
V
ADJ INPUT BIAS CURRENT (ADP171)
LINE REGULATION
LOAD REGULATION3
ADJI-BIAS
1.6 V ≤ VIN ≤ 3.6 V, ADJ connected to VOUT
15
nA
∆VOUT/∆VIN VIN = (VOUT + 0.5 V) to 3.6 V, TJ = −40°C to +125°C
∆VOUT/∆IOUT IOUT = 1 mA to 300 mA
−0.25
+0.25 %/V
%/mA
0.001
IOUT = 1 mA to 300 mA, TJ = −40°C to +125°C
0.007 %/mA
mV
DROPOUT VOLTAGE4
VDROPOUT
IOUT = 10 mA, VOUT ≥ 1.8 V
2
IOUT = 10 mA, VOUT ≥ 1.8 V, TJ = −40°C to +125°C
IOUT = 150 mA, VOUT ≥ 1.8 V
IOUT = 150 mA, VOUT ≥ 1.8 V, TJ = −40°C to +125°C
IOUT = 300 mA, VOUT ≥ 1.8 V
IOUT = 300 mA, VOUT ≥ 1.8 V, TJ = −40°C to +125°C
VOUT = 1.8 V
7
mV
mV
mV
mV
mV
μs
33
66
70
135
800
START-UP TIME5
CURRENT-LIMIT THRESHOLD6
tSTART-UP
ILIMIT
120
450
400
1.2
mA
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
TSSD
TJ rising
150
15
°C
°C
TSSD-HYS
EN INPUT
Logic High Voltage
Logic Low Voltage
Leakage Current Voltage
VIH
VIL
VI-LEAKAGE
1.6 V ≤ VIN ≤ 3.6 V
V
1.6 V ≤ VIN ≤ 3.6 V
EN = VIN or GND
EN = VIN or GND, TJ = −40°C to +125°C
0.4
1
V
μA
μA
0.1
80
UNDERVOLTAGE LOCKOUT
Input Voltage Rising
Input Voltage Falling
Hysteresis
UVLO
UVLORISE
UVLOFALL
UVLOHYS
TJ = −40°C to +125°C
TJ = −40°C to +125°C
1.5
V
V
mV
0.7
Rev. B | Page 3 of 20
ADP170/ADP171
Parameter
Symbol
Conditions
Min
Typ
72
50
40
30
73
70
50
47
Max
Unit
μV rms
μV rms
μV rms
μV rms
dB
dB
dB
dB
OUTPUT NOISE
OUTNOISE
10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 3.0 V
10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 1.8 V
10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 1.2 V
10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 0.8 V
1 kHz, VIN = 3.6 V, IOUT = 10 mA, VOUT = 0.8 V
10 kHz, VIN = 3.6 V, IOUT = 10 mA, VOUT = 0.8 V
10 kHz, VIN = (VOUT + 1 V), IOUT = 10 mA to 300 mA
100 kHz, VIN = (VOUT + 1 V), IOUT = 10 mA to 300 mA
POWER SUPPLY REJECTION RATIO
PSRR
1 The current from the external resistor divider network in the case of adjustable voltage output (as with the ADP171) should be subtracted from the ground current measured.
2 Accuracy when VOUT is connected directly to ADJ. When the VOUT voltage is set by external feedback resistors, the absolute accuracy in adjust mode depends on the
tolerances of resistors used.
3 Based on an end-point calculation using 1 mA and 300 mA loads. See Figure 6 for typical load regulation performance for loads less than 1 mA.
4 Applies only for output voltages above 1.6 V. Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal
output voltage.
5 Start-up time is defined as the time between the rising edge of EN and VOUT being at 90% of its nominal value.
6 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
Table 2.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
MINIMUM INPUT AND OUTPUT
CAPACITANCE1
CMIN
TJ = −40°C to +125°C
0.45
μF
CAPACITOR ESR
RESR
TJ = −40°C to +125°C
0.001
1
Ω
1 The minimum input and output capacitance should be greater than 0.45 μF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with any LDO.
Rev. B | Page 4 of 20
ADP170/ADP171
ABSOLUTE MAXIMUM RATINGS
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending
on PCB material, layout, and environmental conditions. The
specified values of θJA are based on a 4-layer, 4 in. × 3 in. PCB.
Refer to JESD 51-7 for detailed information regarding board
construction.
Table 3.
Parameter
Rating
VIN to GND
VOUT to GND
−0.3 V to +3.6 V
−0.3 V to VIN
EN to GND
−0.3 V to +3.6 V
−65°C to +150°C
−40°C to +125°C
−40°C to +85°C
JEDEC J-STD-020
Storage Temperature Range
Operating Junction Temperature Range
Operating Ambient Temperature Range
Soldering Conditions
ΨJB is the junction-to-board thermal characterization parameter
with units of °C/W. The ΨJB of the package is based on modeling
and calculation using a 4-layer board. The Guidelines for Reporting
and Using Electronic Package Thermal Information: JESD51-12
states that thermal characterization parameters are not the same
as thermal resistances. ΨJB measures the component power flowing
through multiple thermal paths rather than a single path as in
thermal resistance, θJB. Therefore, ΨJB thermal paths include
convection from the top of the package as well as radiation from
the package—factors that make ΨJB more useful in real-world
applications. Maximum junction temperature (TJ) is calculated
from the board temperature (TB) and power dissipation (PD)
using the formula
Stresses above those listed under absolute maximum ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply only individually, not in
combination. The ADP170/ADP171 can be damaged when the
junction temperature limits are exceeded. Monitoring ambient
temperature does not guarantee that TJ is within the specified
temperature limits. In applications with high power dissipation
and poor thermal resistance, the maximum ambient temperature
may have to be derated.
TJ = TB + (PD × ΨJB)
Refer to JESD51-8 and JESD51-12 for more detailed information
about ΨJB.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
In applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits. The junction temperature (TJ) of
the device is dependent on the ambient temperature (TA), the
power dissipation of the device (PD), and the junction-to-
ambient thermal resistance of the package (θJA).
Table 4. Thermal Resistance
Package Type
θJA
ΨJB
Unit
5-Lead TSOT
170
43
°C/W
ESD CAUTION
Maximum junction temperature (TJ) is calculated from the
ambient temperature (TA) and power dissipation (PD) using the
following formula:
TJ = TA + (PD × θJA)
Junction-to-ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
Rev. B | Page 5 of 20
ADP170/ADP171
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
1
2
3
VIN
GND
EN
VIN
GND
EN
5
5
4
VOUT
VOUT
ADJ
ADP170
ADP171
TOP VIEW
TOP VIEW
(Not to Scale)
(Not to Scale)
4
NC
NC = NO CONNECT
Figure 4. ADP171 5-Lead TSOT
Figure 3. ADP170 5-Lead TSOT
Table 5. Pin Function Descriptions
Pin No.
ADP170 ADP171 Mnemonic Description
1
2
3
1
2
3
VIN
GND
EN
Regulator Input Supply. Bypass VIN to GND with a 1 μF or greater capacitor.
Ground.
Enable Input. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For
automatic startup, connect EN to VIN.
4
5
NC
ADJ
VOUT
No Connect. Not connected internally.
Adjust. A resistor divider from VOUT to ADJ sets the output voltage.
Regulated Output Voltage. Bypass VOUT to GND with a 1 μF or greater capacitor.
4
5
Rev. B | Page 6 of 20
ADP170/ADP171
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 3.6 V, VOUT = 1.8 V, IOUT = 10 mA, CIN = COUT = 1 μF, TA = 25°C, unless otherwise noted.
1.810
1.805
1.800
1.795
1.790
1.785
1.780
1.775
1.770
200
180
160
140
120
100
80
I
I
I
= 300mA
= 100mA
= 10mA
LOAD
LOAD
LOAD
I
I
I
I
I
I
= 100µA
= 1mA
= 10mA
= 100mA
= 200mA
= 300mA
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
60
I
I
= 1mA
LOAD
40
= 100µA
LOAD
20
I
= 10µA
–5
LOAD
0
–40
–5
25
85
125
–40
25
85
125
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Figure 5. Output Voltage vs. Junction Temperature
Figure 8. Ground Current vs. Junction Temperature
1.804
1.803
1.802
1.801
1.800
1.799
1.798
180
160
140
120
100
80
60
40
20
0
0.01
0.01
0.1
1
10
100
1k
0.1
1
10
100
1k
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 6. Output Voltage vs. Load Current
Figure 9. Ground Current vs. Load Current
1.805
1.804
1.803
1.802
1.801
1.800
1.799
1.798
180
160
140
120
100
80
I
I
= 300mA
= 100mA
LOAD
LOAD
I
= 10mA
LOAD
60
I
I
= 1mA
LOAD
LOAD
40
= 100µA
20
I
I
= 100µA
= 1mA
I
I
= 10mA
= 100mA
I
I
= 200mA
= 300mA
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
I
= 10µA
LOAD
0
2.1
2.3
2.5
2.7
2.9
(V)
3.1
3.3
3.5
2.1
2.3
2.5
2.7
2.9
(V)
3.1
3.3
3.5
V
V
IN
IN
Figure 7. Output Voltage vs. Input Voltage
Figure 10. Ground Current vs. Input Voltage
Rev. B | Page 7 of 20
ADP170/ADP171
400
350
300
250
200
150
100
50
5.0
V
V
V
V
V
V
V
V
= 2.1V
= 2.3V
= 2.7V
= 2.9V
= 3.2V
= 3.4V
= 3.5V
= 3.6V
IN
IN
IN
IN
IN
IN
IN
IN
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
I
I
I
I
I
= 1mA
LOAD
LOAD
LOAD
LOAD
LOAD
= 10mA
= 100mA
= 200mA
= 300mA
0
1.5
1.6
1.7
1.8
1.9
2.0
–50
–25
0
25
50
75
100
125
V
(V)
TEMPERATURE (°C)
IN
Figure 11. Shutdown Current vs. Temperature at Various Input Voltages
Figure 14. Ground Current vs. Input Voltage (In Dropout)
–30
70
300mA
200mA
100mA
10mA
1mA
T
= 25°C
A
60
50
40
30
20
10
0
–40
–50
–60
–70
–80
–90
10
100
1k
10k
100k
1M
10M
0.1
1
10
100
1k
FREQUENCY (Hz)
LOAD CURRENT (mA)
Figure 15. Power Supply Rejection Ratio vs. Frequency, VOUT = 0.8 V
Figure 12. Dropout Voltage vs. Load Current
1.85
1.80
1.75
1.70
1.65
1.60
1.55
1.50
–30
300mA
200mA
100mA
10mA
1mA
–40
–50
–60
–70
–80
–90
I
I
I
I
I
= 1mA
LOAD
LOAD
LOAD
LOAD
LOAD
= 10mA
= 100mA
= 200mA
= 300mA
1.55
1.60
1.65
1.70
1.75
(V)
1.80
1.85
1.90
10
100
1k
10k
100k
1M
10M
V
FREQUENCY (Hz)
IN
Figure 13. Output Voltage vs. Input Voltage (in Dropout)
Figure 16. Power Supply Rejection Ratio vs. Frequency, VOUT = 1.8 V
Rev. B | Page 8 of 20
ADP170/ADP171
–30
–40
–50
–60
–70
–80
–90
70
60
50
40
30
20
10
0
3V
1.8V
0.8V
300mA
200mA
100mA
10mA
1mA
10
100
1k
10k
100k
1M
10M
0.001
0.01
0.1
1
10
100
1000
FREQUENCY (Hz)
LOAD CURRENT (mA)
Figure 17. Power Supply Rejection Ratio vs. Frequency, VOUT = 3.0 V
Figure 20. RMS Noise vs. Load Current and Output Voltage
–30
3V, 1mA
I
1.8V, 1mA
0.8V, 1mA
LOAD
1mA TO 300mA LOAD STEP,
2.5A/µs
–40
–50
–60
–70
–80
–90
3V, 300mA
1.8V, 300mA
0.8V, 300mA
1
V
OUT
2
V
V
= 3.6V
= 1.8V
IN
OUT
B
10
100
1k
10k
100k
1M
10M
CH1 200mA Ω CH2 50.0mV
M40.00µs A CH1
124mA
W
T
160.680µs
FREQUENCY (Hz)
Figure 18. Power Supply Rejection Ratio vs. Frequency, Various Output
Voltages and Load Currents
Figure 21. Load Transient Response, CIN and COUT = 1 μF
10
I
LOAD
1mA TO 300mA LOAD STEP,
2.5A/µs
1
1
0.8V
1.8V
3.0V
V
OUT
2
0.1
V
= 3.6V
IN
V
V
= 3.6V
= 1.8V
IN
OUT
I
= 10mA
= 1µF
LOAD
C
OUT
0.01
10
B
CH1 200mA Ω CH2 50.0mV
M40.0µs A CH1 204mA
W
100
1k
10k
100k
T
159.800µs
FREQUENCY (Hz)
Figure 19. Output Noise Spectrum
Figure 22. Load Transient Response, CIN and COUT = 4.7 μF
Rev. B | Page 9 of 20
ADP170/ADP171
V
IN
V
IN
2.6V TO 3.6V INPUT VOLTAGE STEP,
2V/µs
2.6V TO 3.6V INPUT VOLTAGE STEP
2V/µs
1
2
1
2
V
V
OUT
OUT
V
C
= 1.8V
OUT
= C
V
C
= 1.8V
OUT
= C
= 1µF
IN
OUT
= 1µF
IN
OUT
B
CH1 1.00V
CH2 10.0mV
M10.0µs A CH1
39.3000%
2.94V
CH1 1.00V
CH2 10.0mV
M10.0µs A CH1 2.94V
W
T
T
39.3000µs
Figure 23. Line Transient Response, Load Current = 1 mA
Figure 24. Line Transient Response, Load Current = 300 mA
Rev. B | Page 10 of 20
ADP170/ADP171
THEORY OF OPERATION
The ADP170/ADP171 are low quiescent current, low-dropout
linear regulators that operate from 1.6 V to 3.6 V and can provide
up to 300 mA of output current. Drawing a low 170 μA of quies-
cent current (typical) at full load makes the ADP170/ADP171
ideal for battery-operated portable equipment. Shutdown current
consumption is typically 100 nA.
Internally, the ADP170/ADP171 consist of a reference, an error
amplifier, a feedback voltage divider, and a PMOS pass transistor.
Output current is delivered via the PMOS pass device, which is
controlled by the error amplifier. The error amplifier compares
the reference voltage with the feedback voltage from the output
and amplifies the difference. If the feedback voltage is lower than
the reference voltage, the gate of the PMOS device is pulled lower,
allowing more current to pass and increasing the output voltage.
If the feedback voltage is higher than the reference voltage, the
gate of the PMOS device is pulled higher, allowing less current
to pass and decreasing the output voltage.
Optimized for use with small 1 μF ceramic capacitors, the
ADP170/ADP171 provide excellent transient performance.
ADP170
VIN
VOUT
The adjustable ADP171 has an output voltage range of 0.8 V to
3.0 V. The output voltage is set by the ratio of two external resistors,
as shown in Figure 2. The device servos the output to maintain
the voltage at the ADJ pin at 0.5 V referenced to ground. The
current in R1 is then equal to 0.5 V/R2 and the current in R1 is
the current in R2 plus the ADJ pin bias current. The ADJ pin
bias current, 15 nA at 25°C, flows through R1 into the ADJ pin.
SHORT CIRCUIT,
UVLO AND
THERMAL
R1
R2
GND
PROTECT
EN
SHUTDOWN
0.5V REFERENCE
The output voltage can be calculated using the equation:
NOTES
V
OUT = 0.5 V(1 + R1/R2) + (ADJI-BIAS)(R1)
1. R1 AND R2 ARE INTERNAL RESISTORS, AVAILABLE ON
THE ADP170 ONLY.
The value of R1 should be less than 200 kΩ to minimize errors
in the output voltage caused by the ADJ pin bias current. For
example, when R1 and R2 each equal 200 kΩ, the output voltage
is 1.0 V. The output voltage error introduced by the ADJ pin
bias current is 3 mV or 0.3%, assuming a typical ADJ pin bias
current of 15 nA at 25°C.
Figure 25. ADP170 Internal Block Diagram
ADP171
VIN
GND
EN
VOUT
SHORT CIRCUIT,
UVLO AND
THERMAL
Note that in shutdown, the output is turned off and the divider
current is zero.
PROTECT
The ADP170/ADP171 use the EN pin to enable and disable the
VOUT pin under normal operating conditions. When EN is high,
VOUT turns on; when EN is low, VOUT turns off. For automatic
startup, EN can be tied to VIN.
ADJ
SHUTDOWN
0.5V REFERENCE
Figure 26. ADP171 Internal Block Diagram
Rev. B | Page 11 of 20
ADP170/ADP171
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
Input Bypass Capacitor
Connecting a 1 μF capacitor from VIN to GND reduces the
circuit sensitivity to the printed circuit board (PCB) layout,
especially when long input traces or high source impedance
are encountered. If greater than 1 μF of output capacitance is
required, the input capacitor should be increased to match it.
The ADP170/ADP171 are designed for operation with small,
space-saving ceramic capacitors but will function with most
commonly used capacitors as long as care is taken with regard
to the effective series resistance (ESR) value. The ESR of the
output capacitor affects the stability of the LDO control loop.
A minimum of 1 μF capacitance with an ESR of 1 ꢀ or less is
recommended to ensure stability of the ADP170/ADP171. The
transient response to changes in load current is also affected by
output capacitance. Using a larger value of output capacitance
improves the transient response of the ADP170/ADP171 to
large changes in load current. Figure 27 and Figure 28 show the
transient responses for output capacitance values of 1 μF and
4.7 μF, respectively.
Input and Output Capacitor Properties
Any good quality ceramic capacitor can be used with the
ADP170/ADP171, as long as it meets the minimum capacitance
and maximum ESR requirements. Ceramic capacitors are manu-
factured with a variety of dielectrics, each with different behavior
over temperature and applied voltage. Capacitors must have a
dielectric adequate to ensure the minimum capacitance over the
necessary temperature range and dc bias conditions. A X5R or X7R
dielectric with a voltage rating of 6.3 V or 10 V is recommended.
The Y5V and Z5U dielectrics are not recommended, due to their
poor temperature and dc bias characteristics.
I
LOAD
1mA TO 300mA LOAD STEP,
2.5A/µs
Figure 29 depicts the capacitance vs. bias voltage characteristics
of a 0402, 1 μF, 10 V X5R capacitor. The variance of a capacitor
is strongly influenced by the capacitor size and voltage rating. In
general, a capacitor in a larger package or higher voltage rating
will exhibit less capacitance variance over bias voltage. The
temperature variation of the X5R dielectric is about 15% over
the −40°C to +85°C temperature range and is not a function of
package or voltage rating.
1
2
V
OUT
V
C
= 1.8V
OUT
= C
= 1µF
IN
OUT
1.2
B
CH1 200mA Ω CH2 50.0mV
M200ns A CH1
500.000ns
112mA
W
1.0
0.8
0.6
0.4
0.2
0
T
Figure 27. Output Transient Response, COUT = 1 ꢀF
I
LOAD
1mA TO 300mA LOAD STEP,
2.5A/µs
1
2
0
2
4
6
8
10
V
OUT
BIAS VOLTAGE (V)
Figure 29. Capacitance vs. Bias Voltage Characteristics
V
C
= 1.8V
OUT
= C
= 4.7µF
IN
OUT
Use Equation 1 to determine the worst-case capacitance
accounting for capacitor variation over temperature,
component tolerance, and voltage.
B
CH1 200mA Ω CH2 50.0mV
M200ns A CH1
500.000ns
108mA
W
T
Figure 28. Output Transient Response, COUT = 4.7 ꢀF
CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL)
(1)
where:
CBIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
Rev. B | Page 12 of 20
ADP170/ADP171
In this example, the worst-case temperature coefficient
The EN pin active/inactive thresholds are derived from the VIN
voltage. Therefore, these thresholds vary with changing input
voltage. Figure 31 shows typical EN active/inactive thresholds
when the input voltage varies from 1.6 V to 3.6 V.
1.2
(TEMPCO) over −40°C to +85°C is assumed to be 15% for an
X5R dielectric. The tolerance of the capacitor (TOL) is assumed
to be 10%, and CBIAS is 0.94 ꢁF at 1.8 V, as shown in Figure 29.
Substituting these values in Equation 1 yields
1.1
CEFF = 0.94 ꢁF × (1 − 0.15) × (1 − 0.1) = 0.719 ꢁF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over temper-
ature and tolerance at the chosen output voltage.
1.0
EN ACTIVE
0.9
0.8
To guarantee the performance of the ADP170/ADP171, it is
imperative that the effects of dc bias, temperature, and toler-
ances on the behavior of the capacitors are evaluated for each
application.
EN INACTIVE
0.7
0.6
0.5
0.4
UNDERVOLTAGE LOCKOUT
The ADP170/ADP171 have an internal undervoltage lockout
circuit that disables all inputs and the output when the input
voltage is less than approximately 1.2 V. This ensures that the
ADP170/ADP171 inputs and the output behave in a predictable
manner during power-up.
V
(V)
IN
Figure 31. Typical EN Pin Thresholds vs. Input Voltage
The ADP170/ADP171 utilize an internal soft start to limit the
inrush current when the output is enabled. The start-up time
for the 1.8 V option is approximately 120 ꢁs from the time the
EN active threshold is crossed to when the output reaches 90%
of its final value. As shown in Figure 32, the start-up time is
dependent on the output voltage setting.
ENABLE FEATURE
The ADP170/ADP171 use the EN pin to enable and disable the
VOUT pin under normal operating conditions. As shown in
Figure 30, when a rising voltage on EN crosses the active
threshold, VOUT turns on. When a falling voltage on EN
crosses the inactive threshold, VOUT turns off.
3.5
EN
V
= 3.0V
OUT
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 1.8V
OUT
V
= 0.8V
OUT
1
2
B
CH1 1.00V
CH2 1.00V
M20.0µs A CH1 2.72V
79.8000µs
W
T
Figure 32. Typical Start-Up Time
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
V
EN
Figure 30. ADP170/ADP171 Typical EN Pin Operation
As shown in Figure 30, the EN pin has hysteresis built in. This
prevents on/off oscillations that can occur due to noise on the
EN pin as it passes through the threshold points.
Rev. B | Page 13 of 20
ADP170/ADP171
CURRENT LIMIT AND THERMAL OVERLOAD
PROTECTION
The junction temperature of the ADP170/ADP171 can be
calculated from the following equation:
The ADP170/ADP171 are protected against damage due to
excessive power dissipation by current and thermal overload
protection circuits. The ADP170/ADP171 are designed to limit
the current when the output load reaches 450 mA (typical).
When the output load exceeds 450 mA, the output voltage is
reduced to maintain a constant current limit.
TJ = TA + (PD × θJA)
(2)
(3)
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
PD = [(VIN − VOUT) × ILOAD] + (VIN × IGND
)
where:
Thermal overload protection is included, which limits the junction
temperature to a maximum of 150°C (typical). Under extreme
conditions (that is, high ambient temperature and power dissip-
ation), when the junction temperature starts to rise above 150°C,
the output is turned off, reducing the output current to 0. When
the junction temperature drops below 135°C, the output is turned
on again and output current is restored to its nominal value.
I
I
LOAD is the load current.
GND is the ground current.
V
IN and VOUT are input and output voltages, respectively.
Power dissipation due to ground current is quite small and can
be ignored. Therefore, the junction temperature equation
simplifies to the following:
Consider the case where a hard short from VOUT to GND occurs.
At first, the ADP170/ADP171 will limit the current so that only
450 mA is conducted into the short. If self-heating of the junction
is great enough to cause its temperature to rise above 150°C,
thermal shutdown will activate, turning off the output and
reducing the output current to 0. As the junction temperature
cools and drops below 135°C, the output turns on and conducts
450 mA into the short, again causing the junction temperature
to rise above 150°C. This thermal oscillation between 135°C
and 150°C causes a current oscillation between 450 mA and 0 mA,
which continues as long as the short remains at the output.
TJ = TA + {[(VIN − VOUT) × ILOAD] × θJA}
(4)
As shown in Equation 4, for a given ambient temperature, input
to output voltage differential, and continuous load current,
there exists a minimum copper size requirement for the PCB to
ensure that the junction temperature does not rise above 125°C.
Figure 33 to Figure 38 show junction temperature calculations
for different ambient temperatures, load currents, VIN to VOUT
differentials, and areas of PCB copper.
140
T
MAX
J
120
100
80
60
40
20
0
I
= 300mA
Current and thermal limit protections are intended to protect
the device against accidental overload conditions.
LOAD
I
= 150mA
LOAD
THERMAL CONSIDERATIONS
To guarantee reliable operation, the junction temperature of the
ADP170/ADP171 must not exceed 125°C. To ensure the junction
temperature stays below this maximum value, the user needs to
be aware of the parameters that contribute to junction temperature
changes. These parameters include ambient temperature, power
dissipation in the power device, and thermal resistances between
the junction and ambient air (θJA). The θJA number is dependent
on the package assembly compounds used and the amount of
copper to which the GND pin of the package is soldered on the
PCB. Table 6 shows typical θJA values of the 5-lead TSOT package
for various PCB copper sizes.
I
= 100mA
= 25mA
LOAD
I
LOAD
I
= 10mA
I
= 1mA
1.5
LOAD
2.0
LOAD
0.5
1.0
2.5
3.0
V
– V (V)
IN
OUT
Figure 33. 500 mm2 of PCB Copper, TA = 25°C
140
120
100
80
T
MAX
J
I
= 300mA
LOAD
Table 6. Typical θJA Values
Copper Size (mm2)
01
θJA (°C/W)
170
I
= 150mA
LOAD
50
152
146
134
131
60
100
300
500
I
= 100mA
LOAD
40
I
= 25mA
LOAD
20
1 Device soldered to minimum size pin traces.
I
= 10mA
LOAD
I
= 1mA
1.5
LOAD
0
0.5
1.0
2.0
– V (V)
2.5
3.0
V
OUT
IN
Figure 34. 100 mm2 of PCB Copper, TA = 25°C
Rev. B | Page 14 of 20
ADP170/ADP171
140
120
100
80
140
120
100
80
T
MAX
T
MAX
J
J
I
= 300mA
LOAD
I
= 150mA
LOAD
I
= 300mA
LOAD
I
= 100mA
LOAD
I
I
= 150mA
LOAD
I
= 25mA
LOAD
60
= 100mA
= 25mA
60
LOAD
I
40
LOAD
40
I
= 1mA
I
= 10mA
LOAD
LOAD
1.5
20
20
I
= 10mA
LOAD
2.0
I
= 1mA
1.5
LOAD
0
0.5
0
0.5
1.0
2.5
3.0
3.0
3.0
1.0
2.0
– V (V)
2.5
3.0
V
– V
(V)
V
OUT
IN
OUT
IN
Figure 35. 0 mm2 of PCB Copper, TA = 25°C
Figure 38. 0 mm2 of PCB Copper, TA = 50°C
140
120
100
80
In cases where board temperature is known, use the thermal
characterization parameter, ΨJB, to estimate the junction tem-
perature rise (see Figure 39). Maximum junction temperature
(TJ) is calculated from the board temperature (TB) and power
dissipation (PD) using the following formula:
T
MAX
J
I
= 300mA
LOAD
I
= 150mA
LOAD
I
= 100mA
LOAD
TJ = TB + (PD × ΨJB)
(5)
I
= 25mA
LOAD
60
The typical value of ΨJB is 42.8°C/W for the 5-lead TSOT package.
140
40
I
= 10mA
I
= 1mA
LOAD
LOAD
120
100
80
20
0
0.5
1.0
1.5
V
2.0
2.5
– V (V)
IN
OUT
Figure 36. 500 mm2 of PCB Copper, TA = 50°C
I
I
I
I
= 1mA
I
I
I
= 150mA
= 250mA
= 300mA
60
40
20
0
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
140
120
100
80
= 10mA
= 50mA
= 100mA
T
MAX
J
T
MAX
J
I
= 300mA
LOAD
I
= 150mA
LOAD
0.4
0.8
1.2
1.6
– V
2.0
2.4
2.8
I
= 100mA
LOAD
V
(V)
IN
OUT
I
= 25mA
LOAD
60
Figure 39. TSOT, TA = 85°C
40
I
= 1mA
I
= 10mA
LOAD
LOAD
20
0
0.5
1.0
1.5
2.0
– V (V)
2.5
V
OUT
IN
Figure 37. 100 mm2 of PCB Copper, TA = 50°C
Rev. B | Page 15 of 20
ADP170/ADP171
GND
GND
PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATIONS
ANALOG DEVICES
ADP171-x.x-EVALZ
Heat dissipation from the package can be improved by
increasing the amount of copper attached to the pins of the
ADP170/ADP171. However, as can be seen from Table 6, a
point of diminishing returns is eventually reached, beyond
which an increase in the copper size does not yield significant
heat dissipation benefits.
C1
C2
U1
Place the input capacitor as close as possible to the VIN and
GND pins. Place the output capacitor as close as possible to the
VOUT and GND pins. Use of 0402 or 0603 size capacitors and
resistors achieves the smallest possible footprint solution on
boards where area is limited.
J1
R 1
VIN
VOUT
R 2
GND
GND
ANALOG DEVICES
ADP170-x.x-EVALZ
EN
GND
GND
Figure 41. Example ADP171 PCB Layout
C1
C2
U1
J1
VIN
VOUT
EN
GND
GND
Figure 40. Example ADP170 PCB Layout
Rev. B | Page 16 of 20
ADP170/ADP171
OUTLINE DIMENSIONS
2.90 BSC
5
1
4
3
2.80 BSC
1.60 BSC
2
0.95 BSC
1.90
BSC
*
0.90 MAX
0.70 MIN
*
1.00 MAX
0.20
0.08
8°
4°
0°
0.10 MAX
0.50
0.30
0.60
0.45
0.30
SEATING
PLANE
*
COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH
THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
Figure 42. 5-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-5)
Dimensions show in millimeters
ORDERING GUIDE
Package
Option
Model1
Temperature Range
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Output Voltage (V)2 Package Description
Branding
L8E
L8F
L8G
L8H
ADP170AUJZ-1.2-R7
ADP170AUJZ-1.5-R7
ADP170AUJZ-1.8-R7
ADP170AUJZ-2.5-R7
ADP170AUJZ-2.8-R7
ADP171AUJZ-R7
ADP170-1.8-EVALZ
ADP170-BL1-EVZ
ADP171-EVALZ
1.2
1.5
1.8
2.5
2.8
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
UJ-5
UJ-5
UJ-5
UJ-5
UJ-5
UJ-5
L8P
L9A
0.8 to 3.0 (Adjustable) 5-Lead TSOT
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
ADP171-BL1-EVZ
1 Z = RoHS Compliant Part.
2 For additional voltage options, contact your local Analog Devices, Inc., sales or distribution representative.
Rev. B | Page 17 of 20
ADP170/ADP171
NOTES
Rev. B | Page 18 of 20
ADP170/ADP171
NOTES
Rev. B | Page 19 of 20
ADP170/ADP171
NOTES
©2009–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07716-0-5/10(B)
Rev. B | Page 20 of 20
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