ADP1873ARMZ-0.3-R7_技术文档

Synchronous Current-Mode with

Constant On-Time, PWM Buck Controller

Data Sheet

ADP1872/ADP1873

FEATURES

TYPICAL APPLICATIONS CIRCUIT

V

= 2.75V TO 20V

IN

Power input voltage as low as 2.75 V to 20 V

Bias supply voltage range: 2.75 V to 5.5 V

Minimum output voltage: 0.6 V

0.6 V reference voltage with 1.0% accuracy

Supports all N-channel MOSFET power stages

Available in 300 kHz, 600 KHz, and 1.0 MHz options

No current-sense resistor required

Power saving mode (PSM) for light loads (ADP1873 only)

Resistor-programmable current-sense gain

Thermal overload protection

VIN

C

ADP1872/

ADP1873

C

IN

C

C2

R

C

COMP/EN

BST

DRVH

SW

C

R

Q1

BST

TOP

L

V

+

FB

OUT

R

BOT

C

GND

VDD

OUT

Q2

C

VDD2

DRVL

V

= 2.75V

TO 5.5V

DD

PGND

R

LOAD

5A

RES

C

VDD

Short-circuit protection

Figure 1.

Precision enable input

Integrated bootstrap diode for high-side drive

140 µA shutdown supply current

Starts into a precharged load

100

95

90

85

80

75

70

65

60

55

50

45

V

= 5.5V, V = 5.5V (PSM)

IN

V

= 5.5V, V = 5.5V

IN

DD

Small, 10-lead MSOP package

V

= 5.5V, V = 13.0V (PSM)

IN

DD

APPLICATIONS

Telecom and networking systems

Mid to high end servers

Set-top boxes

V

= 5.5V, V = 16.5V (PSM)

IN

DD

T

= 25°C

A

V

= 1.8V

OUT

= 300kHz

DSP core power supplies

f

SW

WURTH INDUCTOR:

744325120, L = 1.2µH, DCR = 1.8mΩ

INFINEON FETs:

BSC042N03MS G (UPPER/LOWER)

100

1k

10k

100k

LOAD CURRENT (mA)

Figure 2. ADP1872 Efficiency vs. Load Current (V_OUT= 1.8 V, 300 kHz)

GENERAL DESCRIPTION

The ADP1872/ADP1873 are versatile current-mode, synchronous

step-down controllers that provide superior transient response,

optimal stability, and current limit protection by using a constant

on-time, pseudo-fixed frequency with a programmable current-

sense gain, current-control scheme. In addition, these devices offer

optimum performance at low duty cycles by using valley current-

mode control architecture. This allows the ADP1872/ADP1873

to drive all N-channel power stages to regulate output voltages

as low as 0.6 V.

Available in three frequency options (300 kHz, 600 kHz, and

1.0 MHz, plus the PSM option), the ADP1872/ADP1873 are

well suited for a wide range of applications. These ICs not only

operate from a 2.75 V to 5.5 V bias supply, but can also accept a

power input as high as 20 V.

In addition, an internally fixed, soft start period is included to limit

input in-rush current from the input supply during startup and

to provide reverse current protection during soft start for a pre-

charged output. The low-side current-sense, current-gain scheme

and integration of a boost diode, along with the PSM/forced pulse-

width modulation (PWM) option, reduce the external part count

and improve efficiency.

The ADP1873 is the power saving mode (PSM) version of the

device and is capable of pulse skipping to maintain output

regulation while achieving improved system efficiency at light

loads (see the Power Saving Mode (PSM) Version (ADP1873)

section for more information).

The ADP1872/ADP1873 operate over the −40°C to +125°C

junction temperature range and are available in a 10-lead MSOP.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

ADP1872/ADP1873

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Timer Operation ........................................................................ 21

Pseudo-Fixed Frequency........................................................... 22

Applications Information.............................................................. 23

Feedback Resistor Divider ........................................................ 23

Inductor Selection...................................................................... 23

Output Ripple Voltage (ΔV_RR) .................................................. 23

Output Capacitor Selection....................................................... 23

Compensation Network ............................................................ 24

Efficiency Consideration........................................................... 25

Input Capacitor Selection.......................................................... 26

Thermal Considerations............................................................ 27

Design Example.......................................................................... 27

External Component Recommendations.................................... 30

Layout Considerations................................................................... 32

IC Section (Left Side of Evaluation Board)............................. 37

Power Section ............................................................................. 37

Differential Sensing.................................................................... 37

Typical Application Circuits ......................................................... 38

Dual-Input, 300 kHz High Current Application Circuit ...... 38

Single-Input, 600 kHz Application Circuit............................. 38

Dual-Input, 300 kHz High Current Application Circuit ...... 39

Outline Dimensions....................................................................... 40

Ordering Guide .......................................................................... 40

Applications....................................................................................... 1

Typical Applications Circuit............................................................ 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

Thermal Resistance ...................................................................... 5

Boundary Condition.................................................................... 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 7

ADP1872/ADP1873 Block Digram.............................................. 17

Theory of Operation ...................................................................... 18

Startup.......................................................................................... 18

Soft Start ...................................................................................... 18

Precision Enable Circuitry ........................................................ 18

Undervoltage Lockout ............................................................... 18

Thermal Shutdown..................................................................... 18

Programming Resistor (RES) Detect Circuit.......................... 19

Valley Current-Limit Setting .................................................... 19

Hiccup Mode During Short Circuit......................................... 20

Synchronous Rectifier................................................................ 21

Power Saving Mode (PSM) Version (ADP1873).................... 21

REVISION HISTORY

7/12—Rev. A to Rev. B

Changes to Table 9.......................................................................... 31

Changes to Figure 82...................................................................... 32

Changes to Figure 83...................................................................... 33

Changes to Figure 84...................................................................... 34

Changes to Figure 85...................................................................... 35

Changes to Figure 86...................................................................... 36

Changes to Differential Sensing Section and Figure 88............ 37

Changes to Figure 89 and Figure 90............................................. 38

Changes to Figure 91...................................................................... 39

Updated Outline Dimensions....................................................... 40

Changed R_ON= 15 mΩ/100 kꢀ Valley Current Level Value from

7.5 to 3.87; Table 6 .......................................................................... 20

Changes to Ordering Guide .......................................................... 40

3/10—Rev. 0 to Rev. A

Changes to Figure 1.......................................................................... 1

Changes to Table 1............................................................................ 3

Changes to Table 2............................................................................ 5

Changes to Figure 59 Caption and Figure 60 Caption .............. 16

Changes to Figure 64...................................................................... 17

Changes to Timer Operation Section .......................................... 22

Changes to Table 7.......................................................................... 23

Changes to Inductor Section......................................................... 28

10/09—Revision 0: Initial Version

Rev. B | Page 2 of 40

Data Sheet

ADP1872/ADP1873

SPECIFICATIONS

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VDD = 5 V,

BST − SW = 5 V, VIN = 13 V. The specifications are valid for T_J= −40°C to +125°C, unless otherwise specified.

Table 1.

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

POWER SUPPLY CHARACTERISTICS

High Input Voltage Range

VIN

ADP1872ARMZ-0.3/ADP1873ARMZ-0.3 (300 kHz)

ADP1872ARMZ-0.6/ADP1873ARMZ-0.6 (600 kHz)

ADP1872ARMZ-1.0/ADP1873ARMZ-1.0 (1.0 MHz)

C_IN= 1 µF to PGND, C_IN= 0.22 µF to GND

2.75

3.0

12

20

V

Low Input Voltage Range

VDD

ADP1872ARMZ-0.3/ADP1873ARMZ-0.3 (300 kHz)

ADP1872ARMZ-0.6/ADP1873ARMZ-0.6 (600 kHz)

ADP1872ARMZ-1.0/ADP1873ARMZ-1.0 (1.0 MHz)

FB = 1.5 V, no switching

2.75

3.0

5

1.1

140

2.65

190

5.5

V

mA

µA

V

Quiescent Current

Shutdown Current

Undervoltage Lockout

UVLO Hysteresis

I_{Q_DD}+ I_{Q_BST}

I_{DD, SD}+ I_{BST, SD}COMP/EN < 285 mV

UVLO Rising VDD (See Figure 34 for temperature variation)

215

Falling VDD from operational state

mV

SOFT START

Soft Start Period

See Figure 57

3.0

ms

ERROR AMPLIFER

FB Regulation Voltage

V_FB

T_J= 25°C

600

mV

T_J= −40°C to +85°C

T_J= −40°C to +125°C

595.5 600

594.2 600

605.4 mV

606.5 mV

Transconductance

FB Input Leakage Current

CURRENT-SENSE AMPLIFIER GAIN

Programming Resistor (RES)

Value from DRVL to PGND

G_M

I_{FB, LEAK}

300

515

1

730

50

µs

nA

FB = 0.6 V, COMP/EN = released

RES = 47 kΩ 1%

2.7

3

3.3

V/V

RES = 22 kΩ 1%

RES = none

RES = 100 kΩ 1%

5.5

11

22

6

12

24

6.5

13

26

V/V

SWITCHING FREQUENCY

Typical values measured at 50% time points with

0 nF at DRVH and DRVL; maximum values are

guaranteed by bench evaluation¹

ADP1872ARMZ-0.3/

300

kHz

ADP1873ARMZ-0.3 (300 kHz)

On-Time

Minimum On-Time

Minimum Off-Time

VIN = 5 V, V_OUT= 2 V, T_J= 25°C

VIN = 20 V

84% duty cycle (maximum)

1120 1200 1280 ns

145

320

600

190

385

ns

kHz

ADP1872ARMZ-0.6/

ADP1873ARMZ-0.6 (600 kHz)

On-Time

Minimum On-Time

Minimum Off-Time

ADP1872ARMZ-1.0/

ADP1873ARMZ-1.0 (1.0 MHz)

On-Time

Minimum On-Time

Minimum Off-Time

VIN = 5 V, V_OUT= 2 V, T_J= 25°C

VIN = 20 V, V_OUT= 0.8 V

65% duty cycle (maximum)

500

285

520

82

320

1.0

580

110

385

ns

MHz

VIN = 5 V, V_OUT= 2 V, T_J= 25°C

VIN = 20 V

45% duty cycle (maximum)

312

60

320

340

85

385

ns

Rev. B | Page 3 of 40

ADP1872/ADP1873

Data Sheet

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

OUTPUT DRIVER CHARACTERISTICS

High-Side Driver

Output Source Resistance

Output Sink Resistance

Rise Time²

I_SOURCE= 1.5 A, 100 ns, positive pulse (0 V to 5 V)

I_SINK= 1.5 A, 100 ns, negative pulse (5 V to 0 V)

BST − SW = 4.4 V, C_IN= 4.3 nF (see Figure 59)

BST − SW = 4.4 V, C_IN= 4.3 nF (see Figure 60)

2

3.5

2

Ω

ns

0.8

25

11

t_{r, DRVH}

t_{f, DRVH}

Fall Time²

Low-Side Driver

Output Source Resistance

Output Sink Resistance

Rise Time²

I_SOURCE= 1.5 A, 100 ns, positive pulse (0 V to 5 V)

I_SINK= 1.5 A, 100 ns, negative pulse (5 V to 0 V)

VDD = 5.0 V, C_IN= 4.3 nF (see Figure 60)

VDD = 5.0 V, C_IN= 4.3 nF (see Figure 59)

1.7

0.75

18

3

2

Ω

ns

t_{r, DRVL}

t_{f, DRVL}

Fall Time²

16

Propagation Delays

DRVL Fall to DRVH Rise²

DRVH Fall to DRVL Rise²

SW Leakage Current

Integrated Rectifier

Channel Impedance

PRECISION ENABLE THRESHOLD

Logic High Level

t_{tpdh, DRVH}

t_{tpdh, DRVL}

I_{SW, LEAK}

BST − SW = 4.4 V (see Figure 59)

BST − SW = 4.4 V (see Figure 60)

BST = 25 V, SW = 20 V, VDD = 5.5 V

22

24

ns

µA

110

330

I_SINK= 10 mA

22

Ω

VIN = 2.9 V to 20 V, VDD = 2.75 V to 5.5 V

235

285

35

mV

Enable Hysteresis

COMP VOLTAGE

COMP Clamp Low Voltage

V_{COMP (LOW)}

From disable state, release COMP/EN pin to enable

device (2.75 V ≤ VDD ≤ 5.5 V)

0.47

V

COMP Clamp High Voltage

COMP Zero Current Threshold

THERMAL SHUTDOWN

V_{COMP (HIGH)}

V_{COMP_ZCT}

T_TMSD

(2.75 V ≤ VDD ≤ 5.5 V)

2.55

V

1.15

Thermal Shutdown Threshold

Thermal Shutdown Hysteresis

Hiccup Current Limit Timing

Rising temperature

155

15

6

°C

ms

¹The maximum specified values are with the closed loop measured at 10% to 90% time points (see Figure 59 and Figure 60), C_GATE= 4.3 nF and upper- and lower-side

MOSFETs being Infineon BSC042N03MS G.

²Not automatic test equipment (ATE) tested.

Rev. B | Page 4 of 40

Data Sheet

ADP1872/ADP1873

ABSOLUTE MAXIMUM RATINGS

Table 2.

Absolute maximum ratings apply individually only, not in

combination. Unless otherwise specified, all other voltages are

referenced to PGND.

Parameter

Rating

VDD to GND

VIN to PGND

FB, COMP/EN to GND

DRVL to PGND

SW to PGND

BST to SW

BST to PGND

DRVH to SW

PGND to GND

−0.3 V to +6 V

THERMAL RESISTANCE

−0.3 V to +28 V

−0.3 V to (VDD + 0.3 V)

−0.3 V to +28 V

−2 V pulse (20 ns)

−0.6 V to (VDD + 0.3 V)

−0.3 V to +28 V

−0.3 V to VDD

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type

θ_JA(10-Lead MSOP)

2-Layer Board

θ_JA

Unit

213.1

171.7

°C/W

0.3 V

4-Layer Board

Operating Junction Temperature

Range

−40°C to +125°C

BOUNDARY CONDITION

Storage Temperature Range

Soldering Conditions

Maximum Soldering Lead

Temperature (10 sec)

−65°C to +150°C

JEDEC J-STD-020

300°C

In determining the values given in Table 2 and Table 3, natural

convection was used to transfer heat to a 4-layer evaluation board.

ESD CAUTION

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. B | Page 5 of 40

ADP1872/ADP1873

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VIN

COMP/EN

FB

1

2

3

4

5

10 BST

9

8

7

6

SW

ADP1872

TOP VIEW

(Not to Scale)

DRVH

PGND

DRVL

GND

VDD

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1

2

3

4

VIN

COMP/EN

FB

High Input Voltage. Connect VIN to the drain of the upper-side MOSFET.

Output of the Internal Error Amplifier/IC Enable. When this pin functions as EN, applying 0 V to this pin disables the IC.

Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected.

Analog Ground Reference Pin of the IC. All sensitive analog components should be connected to this ground

plane (see the Layout Considerations Section).

GND

5

6

VDD

Bias Voltage Supply for the ADP1872/ADP1873 Controller (Includes the Output Gate Drivers). A bypass capacitor

of 1 µF directly from this pin to PGND and a 0.1 µF across VDD and GND are recommended.

Drive Output for the External Lower Side, N-Channel MOSFET. This pin also serves as the current-sense gain

setting pin (see Figure 68).

DRVL

7

8

9

PGND

DRVH

SW

Power GND. Ground for the lower side gate driver and lower side, N-channel MOSFET.

Drive Output for the External Upper Side, N-Channel MOSFET.

Switch Node Connection.

10

BST

Bootstrap for the Upper Side MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected

between VDD and BST. A capacitor from BST to SW is required. An external Schottky diode can also be

connected between VDD and BST for increased gate drive capability.

Rev. B | Page 6 of 40

Data Sheet

ADP1872/ADP1873

TYPICAL PERFORMANCE CHARACTERISTICS

100

95

90

85

80

75

70

65

60

55

50

45

40

35

30

25

20

15

V_DD= 5.5V, V_IN= 13V (PSM)

_DD= 5.5V, V_IN= 5.5V (PSM)

V_DD= 5.5V, V_IN= 13V (PSM)

V_DD= 5.5V, V_IN= 5.5V

V

_DD= 5.5V, V_IN= 5.5V

95

90

85

80

75

70

65

60

55

50

45

40

35

30

V

_DD= 5.5V,

_IN= 16.5V (PSM)

V_DD= 3.6V, V_IN= 5.5V

_DD= 5.5V, V_IN= 13V

_DD= 3.6V, V_IN= 13V

V_DD= 5.5V,

_IN= 5.5V

(PSM)

V

_DD= 5.5V,

_IN= 16.5V

V_DD= 3.6V, V_IN= 5.5V

V

_DD= 5.5V, V_IN= 13V

(PSM)

V

V_DD= 5.5V, V_IN= 16.5V

V

_DD= 5.5V, V_IN= 16.5V

_DD= 3.6V, V_IN= 16.5V

V

WURTH IND: 744355147, L = 0.47µH, DCR: 0.80mΩ

INFINEON FETs: BSC042N03MS G (UPPER/LOWER)

T

= 25°C

T

= 25°C

A

100

1k

10k

100k

100

1k

10k

100k

LOAD CURRENT (mA)

Figure 4. Efficiency—300 kHz, V_OUT= 0.8 V

Figure 7. Efficiency—600 kHz, V_OUT= 0.8 V

100

95

90

85

80

75

70

65

60

55

50

45

40

35

30

25

100

95

90

85

80

75

70

65

60

55

50

45

40

35

30

25

V_DD= 5.5V, V_IN= 5.5V (PSM)

V

_DD= 5.5V, V_IN= 5.5V

V_DD= 5.5V, V_IN= 5.5V

V_DD= 5.5V, = V_IN= 5.5(PSM)

V_DD= 5.5V, V_IN= 16.5V (PSM)

_DD= 5.5V, V_IN= 16.5V

V_DD= 5.5V, V_IN= 16.5V

V_DD= 5.5V, V_IN= 16.5V (PSM)

V

_DD= 5.5V, V_IN= 13V (PSM)

_DD= 3.6V, V_IN= 3.6V

_DD= 5.5V, V_IN= 13V

V_DD= 5.5V, V_IN= 13V (PSM)

V

V_DD= 3.6V, V_IN= 5.5V

V

V_DD= 5.5V, V_IN= 13V

V

_DD= 3.6V, V_IN= 5.5V

WURTH IND: 744325120, L = 1.2µH, DCR: 1.8mΩ

INFINEON FETS: BSC042N03MS G (UPPER/LOWER)

T = 25°C

A

INFINEON FETS: BSC042N03MS G (UPPER/LOWER)

= 25°C

T

A

100

1k

10k

100k

100

1k

10k

100k

LOAD CURRENT (mA)

Figure 5. Efficiency—300 kHz, V_OUT= 1.8 V

Figure 8. Efficiency—600 kHz, V_OUT= 1.8 V

100

95

90

85

80

75

70

65

60

55

50

45

40

35

30

100

95

90

85

80

75

70

65

60

55

50

45

40

35

30

V_DD= 5.5V,

_IN= 13V (PSM)

V_DD= 3.6V,V_IN= 13V

V_DD= 5.5V, V_IN= 16.5V (PSM)

V

V_DD= 5.5V, V_IN= 13V

V_DD= 5.5V,

_IN= 16V

(PSM)

V_DD= 5.5V, V_IN= 16.5V (PSM)

V

V_DD= 3.6V, V_IN= 16.5V

V_DD= 5.5V, V_IN= 16.5V

V

= 2.7V

V

= 3.6V

V

= 5.5V

DD

13V

IN

16.5V

IN

16.5V

IN

16.5V

IN

WURTH IND: 7443551200, L = 2µH, DCR: 2.6mΩ

INFINEON FETs: BSC042N03MS G (UPPER/LOWER)

= 25°C

WURTH IND: 7443551200, L = 2µH, DCR: 2.6mΩ

INFINEON FETs: BSC042N03MS G (UPPER/LOWER)

T = 25°C

A

T

A

100

1k

10k

100k

100

1k

10k

100k

LOAD CURRENT (mA)

Figure 6. Efficiency—300 kHz, V_OUT= 7 V

Figure 9. Efficiency—600 kHz, V_OUT= 5 V

Rev. B | Page 7 of 40

ADP1872/ADP1873

Data Sheet

100

0.8030

0.8025

0.8020

0.8015

0.8010

0.8005

0.8000

0.7995

0.7990

0.7985

0.7980

0.7975

0.7970

0.7965

0.7960

V_DD= 5.5V, V_IN= 13V (PSM)

95

V_DD= 5.5V, V_IN= 5.5V

V

_DD= 5.5V,

_IN= 5.5V (PSM)

90

85

80

75

70

65

60

55

50

45

40

35

30

25

20

V_DD= 5.5V,

V

_IN= 16.5V

(PSM)

V

_DD= 5.5V, V_IN= 16.5V

V_DD= 5.5V, V_IN= 13V

V

= 13V

V

= 16.5V

IN

+125°C

+25°C

–40°C

+125°C

+25°C

–40°C

V_DD= 3.6V, V_IN= 5.5V

V_DD= 3.6V, V_IN= 3.6V

V

= 5.5V

IN

WURTH IND: 744303012, L = 0.12µH, DCR: 0.33mΩ

INFINEON FETs: BSC042N03MS G (UPPER/LOWER)

+125°C

+25°C

–40°C

T

= 25°C

A

100

1k

10k

100k

0

2000

4000

6000

8000 10,000 12,000 14,000 16,000

LOAD CURRENT (mA)

Figure 10. Efficiency—1.0 MHz, V_OUT= 0.8 V

Figure 13. Output Voltage Accuracy—300 kHz, V_OUT= 0.8 V

100

95

90

85

80

75

70

65

60

55

50

45

40

35

30

25

20

1.821

V_DD= 5.5V, V_IN= 5V (PSM)

V_DD= 5.5V,

V

_IN= 16.5V (PSM)

1.816

1.811

1.806

1.801

1.796

1.791

1.786

V

_DD= 5.5V,

_IN= 5V

V_DD= 5.5V,

_IN= 13V

(PSM)

V_DD= 5.5V, V_IN= 16.5V

V

V_DD= 3.6V, V_IN= 13V

_DD= 3.6V, V_IN= 16.5V

V

V_DD= 5.5V, V_IN= 13V

V

= 5.5V

+125°C

+25°C

–40°C

V

= 13V

+125°C

+25°C

–40°C

V

= 16.5V

IN

+125°C

+25°C

–40°C

WURTH IND: 744303022, L = 0.22µH, DCR: 0.33mΩ

INFINEON FETs: BSC042N03MS G (UPPER/LOWER)

= 25°C

T

A

0

1500 3000 4500 6000 7500 9000 10,500 12,000 13,500 15,000

LOAD CURRENT (mA)

100

1k

10k

100k

LOAD CURRENT (mA)

Figure 11. Efficiency—1.0 MHz, V_OUT= 1.8 V

Figure 14. Output Voltage Accuracy—300 kHz, V_OUT= 1.8 V

100

95

90

85

80

75

70

65

60

55

50

45

40

35

30

25

20

7.000

6.995

6.990

6.985

6.980

6.975

6.970

6.965

6.960

6.955

V_DD= 5.5V, V_IN= 5V (PSM) V_DD= 5.5V, V_IN= 16.5V (PSM)

V

= 3.6V, V = 13V

IN

= 3.6V, V = 16.5V

IN

DD

V_DD= 5V,

_IN= 13V

V

_DD= 5V, V_IN= 16.5V

WURTH IND: 744325072, L = 0.72µH, DCR: 1.65mΩ

INFINEON FETs: BSC042N03MS G (UPPER/LOWER)

= 25°C

+125°C

+25°C

–40°C

V

= 5.5V, V = 13V

IN

= 5.5V, V = 16.5V

IN

DD

T

A

0

1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000

LOAD CURRENT (mA)

100

1k

LOAD CURRENT (mA)

10k

Figure 12. Efficiency—1.0 MHz, V_OUT= 4 V

Figure 15. Output Voltage Accuracy—300 kHz, V_OUT= 7 V

Rev. B | Page 8 of 40

Data Sheet

ADP1872/ADP1873

1.801

1.800

1.799

1.798

1.797

1.796

1.795

1.794

1.793

1.792

1.791

1.790

1.789

1.810

1.809

1.808

1.807

1.806

1.805

1.804

1.803

1.802

1.801

1.800

1.799

1.798

1.797

V

= 5.5V

+125°C

+25°C

–40°C

V

= 13V

+125°C

+25°C

–40°C

V

= 16.5V

IN

V

= 5.5V

V

= 13V

V

= 16.5V

IN

+125°C

+25°C

–40°C

+125°C

+25°C

–40°C

+125°C

+25°C

–40°C

+125°C

+25°C

–40°C

0

1500 3000 4500 6000 7500 9000 10,500 12,000 13,500 15,000

LOAD CURRENT (mA)

0

1500 3000 4500 6000 7500 9000 10,500 12,000 13,500 15,000

LOAD CURRENT (mA)

Figure 16. Output Voltage Accuracy—600 kHz, V_OUT= 1.8 V

Figure 19. Output Voltage Accuracy—1.0 MHz, V_OUT= 1.8 V

5.044

4.050

4.045

4.040

4.035

4.030

4.025

4.020

4.015

4.010

4.005

4.000

3.995

3.990

3.985

3.980

3.975

3.970

5.042

5.040

5.038

5.036

5.034

5.032

5.030

5.028

5.026

5.024

5.022

5.020

V

= 13V

+125°C

+25°C

–40°C

V

= 16.5V

+125°C

+25°C

–40°C

IN

+125°C

+25°C

–40°C

V

= 5.5V, V = 13V

IN

DD

= 5.5V, V = 16.5V

IN

0

1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000

LOAD CURRENT (mA)

0

800 1600 2400 3200 4000 4800 5600 6400 7200 8000

LOAD CURRENT (mA)

Figure 17. Output Voltage Accuracy—600 kHz, V_OUT= 5 V

Figure 20. Output Voltage Accuracy—1.0 MHz, V_OUT= 4 V

0.807

0.806

0.805

0.804

0.803

0.802

0.801

0.800

0.799

0.798

0.6030

V

= 5.5V

+125°C

+25°C

–40°C

IN

0.6025

0.6020

0.6015

0.6010

0.6005

0.6000

0.5995

0.5990

0.5985

0.5980

0.5975

V

= 13V

+125°C

+25°C

–40°C

V

= 16.5V

IN

V

= 2.7V, V = 2.7V, 3.6V

IN

= 3.6V, V = 3.6V TO 16.5V

IN

= 5.5V, V = 5.5V, 13V, 16.5V

IN

DD

+125°C

+25°C

–40°C

0

2000

4000

6000

8000 10,000 12,000 14,000 16,000

–40.0

–7.5

25.0

57.5

90.0

122.5

LOAD CURRENT (mA)

TEMPERATURE (°C)

Figure 18. Output Voltage Accuracy—1 MHz, V_OUT= 0.8 V

Figure 21. Feedback Voltage vs. Temperature

Rev. B | Page 9 of 40

ADP1872/ADP1873

Data Sheet

335

340

325

310

295

280

265

250

235

220

205

190

V

= 5.5V

= 3.6V

+125°C

+25°C

–40°C

NO LOAD

V

= 5.5V

= 13V

= 16.5V

+125°C

+25°C

–40°C

DD

IN

325

315

305

295

285

275

265

255

245

235

225

10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2

0

2000

4000

6000

8000 10,000 12,000 14,000 16,000

V

(V)

LOAD CURRENT (mA)

IN

Figure 25. Frequency vs. Load Current, 300 kHz, V_OUT= 0.8 V

Figure 22. Switching Frequency vs. High Input Voltage,

300 kHz, ±±0% of ±2 V

360

350

340

330

320

310

300

290

280

270

260

650

600

550

500

450

400

V

= 5.5V

= 13V

= 16.5V

+125°C

+25°C

–40°C

V

= 5.5V

= 3.6V

+125°C

+25°C

–40°C

NO LOAD

IN

DD

0

2000 4000 6000 8000 10,000 12,000 14,000 16,000 18,000 20,000

LOAD CURRENT (mA)

10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2

V

(V)

IN

Figure 26. Frequency vs. Load Current, 300 kHz, V_OUT= ±.8 V

Figure 23. Switching Frequency vs. High Input Voltage,

600 kHz, V_OUT= ±.8 V, ±±0% of ±2 V

358

354

350

346

342

338

334

330

326

322

318

314

310

306

302

298

294

290

1000

950

900

850

800

750

700

650

600

550

V

= 13V

= 16.5V

+125°C

+25°C

–40°C

V

= 5.5V

= 3.6V

+125°C

+25°C

–40°C

NO LOAD

IN

DD

0

800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800 9600

LOAD CURRENT (mA)

10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2

V

(V)

IN

Figure 24. Switching Frequency vs. High Input Voltage,

±.0 MHz, ± ±0% of ±2 V

Figure 27. Frequency vs. Load Current, 300 kHz, V_OUT= 7 V

Rev. B | Page 10 of 40

Data Sheet

ADP1872/ADP1873

700

1300

1125

1150

1075

1000

925

V

= 5.5V

= 13V

= 16.5V

+125°C

+25°C

–40°C

V

= 5.5V

= 13V

= 16.5V

+125°C

+25°C

–40°C

IN

670

640

V

610

580

550

520

490

460

430

400

370

340

310

280

250

220

190

850

775

700

625

550

475

400

0

2000

4000

6000

8000 10,000 12,000 14,000 16,000

0

2000

4000

6000

8000 10,000 12,000 14,000 16,000

LOAD CURRENT (mA)

Figure 28. Frequency vs. Load Current, 600 kHz, V_OUT= 0.8 V

Figure 31. Frequency vs. Load Current, V_OUT= 1.0 MHz, 0.8 V

815

795

775

755

735

715

695

675

655

635

615

595

575

555

535

515

495

V

= 5.5V

= 13V

= 16.5V

IN

1450

1375

1300

1225

1150

1075

1000

925

V

= 5.5V

= 13V

= 16.5V

IN

MIN-OFF TIME

ENCROACHMENT

850

775

700

+125°C

+25°C

–40°C

+125°C

+25°C

–40°C

625

550

0

2000 4000 6000 8000 10,000 12,000 14,000 16,000 18,000 20,000

LOAD CURRENT (mA)

0

2000 4000 6000 8000 10,000 12,000 14,000 16,000 18,000 20,000

LOAD CURRENT (mA)

Figure 32. Frequency vs. Load Current, 1.0 MHz, V_OUT= 1.8 V

Figure 29. Frequency vs. Load Current, 600 kHz, V_OUT= 1.8 V

1450

1400

1350

1300

1250

1200

1150

1100

1050

1000

V

= 13V

= 16.5V

+125°C

+25°C

–40°C

705

698

691

684

677

670

663

656

649

642

635

628

621

614

607

600

IN

V

= 13V

= 16.5V

+125°C

+25°C

–40°C

IN

0

800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800 9600

LOAD CURRENT (mA)

0

800 1600 2400 3200 4000 4800 5600 6400 7200 8000

LOAD CURRENT (mA)

Figure 30. Frequency vs. Load Current, 600 kHz, V_OUT=5 V

Figure 33. Frequency vs. Load Current, 1.0 MHz, V_OUT= 4 V

Rev. B | Page 11 of 40

ADP1872/ADP1873

Data Sheet

2.658

2.657

2.656

2.655

2.654

2.653

2.652

2.651

2.650

2.649

680

630

580

530

480

430

380

330

280

230

180

V

= 2.7V

= 3.6V

= 5.5V

DD

–40

–20

0

20

40

60

80

100

120

–40

–20

0

20

40

60

80

100

120

TEMPERATURE (°C)

Figure 34. UVLO vs. Temperature

Figure 37. Minimum Off-Time vs. Temperature

100

95

90

85

80

75

70

65

60

55

50

45

40

680

630

580

530

480

430

380

330

280

230

180

V

= 2.7V

= 3.6V

= 5.5V

+125°C

+25°C

–40°C

+125°C

+25°C

–40°C

DD

300

400

500

600

700

800

900

1000

2.7

3.1

3.5

3.9

4.3

(V)

4.7

5.1

5.5

FREQUENCY (kHz)

V

DD

Figure 35. Maximum Duty Cycle vs. Frequency

Figure 38. Minimum Off-Time vs. V_DD(Low Input Voltage)

84

82

80

78

76

74

72

70

68

66

64

62

60

58

56

54

52

50

48

46

44

42

40

800

720

640

560

480

400

320

240

160

80

V

= 3.6V

= 5.5V

+125°C

+25°C

–40°C

DD

V

= 2.7V

= 3.6V

= 5.5V

+125°C

+25°C

–40°C

DD

3.6 4.8 6.0 7.2 8.4 9.6 10.8 12.0 13.2 14.4 15.6

300

400

500

600

700

800

900

1000

V

(V)

IN

FREQUENCY (kHz)

Figure 36. Maximum Duty Cycle vs. High Voltage Input (V_IN)

Figure 39. Internal Rectifier Drop vs. Frequency

Rev. B | Page 12 of 40

Data Sheet

ADP1872/ADP1873

1280

V

= 5.5V

= 13V

= 16.5V

1MHz

300kHz

T

= 25°C

IN

A

1200

1120

1040

960

880

800

720

640

560

480

400

320

240

160

80

OUTPUT VOLTAGE

1

2

INDUCTOR CURRENT

SW NODE

3

4

LOW SIDE

B

CH1 50mV

CH3 10V

CH2 5A Ω M400ns

35.8%

A

CH2

3.90A

W

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

B

T

CH4 5V

W

V

(V)

DD

Figure 43. Power Saving Mode (PSM) Operational Waveform, 100 mA

Figure 40. Internal Boost Rectifier Drop vs. V_DD(Low Input Voltage)

over VIN Variation

720

300kHz

1MHz

+125°C

+25°C

–40°C

OUTPUT VOLTAGE

640

560

480

400

320

240

160

80

1

INDUCTOR CURRENT

2

SW NODE

3

LOW SIDE

4

B

CH1 50mV

CH3 10V

CH2 5A Ω M4.0µs

35.8%

A

CH2

3.90A

W

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

B

T

CH4 5V

W

V

(V)

DD

Figure 41. Internal Boost Rectifier Drop vs. V_DD

Figure 44. PSM Waveform at Light Load, 500 mA

80

72

64

56

48

40

32

24

16

8

OUTPUT VOLTAGE

300kHz

1MHz

+125°C

+25°C

–40°C

4

INDUCTOR CURRENT

1

3

SW NODE

CH1 5A

CH3 10V

Ω

M400ns

30.6%

A

CH3

2.20V

2.7

3.1

3.5

3.9

4.3

(V)

4.7

5.1

5.5

B

T

CH4 100mV

W

V

DD

Figure 42. Lower Side MOSFET Body Conduction Time vs. V_DD(Low Input Voltage)

Figure 45. CCM Operation at Heavy Load, 18 A

(See Figure 91 for Application Circuit)

Rev. B | Page 13 of 40

ADP1872/ADP1873

Data Sheet

OUTPUT VOLTAGE

2

4

OUTPUT VOLTAGE

20A STEP

LOW SIDE

20A STEP

1

3

1

2

SW NODE

LOW SIDE

A CH1 3.40A

4

3

B

CH1 10A

CH3 20V

Ω

CH2 200mV

CH4 5V

M2ms

CH1 10A

CH3 20V

Ω

CH2 5V

CH4 200mV

M2ms

15.6%

A CH1

6.20A

W

B

T

75.6%

T

W

Figure 46. Load Transient Step—PSM Enabled, 20 A

(See Figure 91 Application Circuit)

Figure 49. Load Transient Step—Forced PWM at Light Load, 20 A

(See Figure 91 Application Circuit)

OUTPUT VOLTAGE

4

2

20A POSITIVE STEP

SW NODE

1

2

3

LOW SIDE

1

3

SW NODE

LOW SIDE

4

B

CH1 10A Ω CH2 200mV

CH3 20V CH4 5V

M20µs

A CH1

3.40A

CH1 10A Ω CH2 5V

M20µs

43.8%

A CH1

6.20A

W

B

T

30.6%

CH3 20V

CH4 200mV

T

W

Figure 50. Positive Step During Heavy Load Transient Behavior—Forced PWM

at Light Load, 20 A, V_OUT= 1.8 V (See Figure 91 Application Circuit)

Figure 47. Positive Step During Heavy Load Transient Behavior—PSM Enabled,

20 A, V_OUT= 1.8 V (See Figure 91 Application Circuit)

OUTPUT VOLTAGE

2

OUTPUT VOLTAGE

20A NEGATIVE STEP

1

SW NODE

3

LOW

SIDE

LOW SIDE

4

B

CH1 10A Ω CH2 200mV

CH3 20V CH4 5V

M10µs

A CH1

5.60A

CH1 10A Ω CH2 200mV

CH3 20V CH4 5V

M20µs

A CH1

3.40A

W

T

23.8%

T

48.2%

Figure 48. Negative Step During Heavy Load Transient Behavior—PSM Enabled,

20 A (See Figure 91 Application Circuit)

Figure 51. Negative Step During Heavy Load Transient Behavior—Forced PWM

at Light Load, 20 A (See Figure 91 Application Circuit)

Rev. B | Page 14 of 40

Data Sheet

ADP1872/ADP1873

OUTPUT VOLTAGE

1

2

4

1

INDUCTOR CURRENT

LOW SIDE

SW NODE

2

4

SW NODE

3

B

W

CH1 2V

CH3 10V

CH2 5A

CH4 5V

Ω

M4ms

49.4%

A CH1

920mV

CH1 2V

CH3 10V

CH2 5A

CH4 5V

Ω

M4ms

41.6%

A CH1

720mV

W

T

Figure 52. Output Short-Circuit Behavior Leading to Hiccup Mode

Figure 55. Power-Down Waveform During Heavy Load

1

OUTPUT VOLTAGE

1

2

INDUCTOR CURRENT

2

SW NODE

3

4

LOW SIDE

4

B

W

CH1 5V

CH3 10V

CH2 10A

CH4 5V

Ω

M10µs

36.2%

A CH2

8.20A

CH1 50mV

CH2 5A

CH4 5V

Ω

M2µs

35.8%

A CH2

3.90A

W

B

T

CH3 10V

T

W

Figure 53. Magnified Waveform During Hiccup Mode

Figure 56. Output Voltage Ripple Waveform During PSM Operation

at Light Load, 2 A

OUTPUT VOLTAGE

1

OUTPUT VOLTAGE

1

INDUCTOR CURRENT

LOW SIDE

4

2

4

LOW SIDE

SW NODE

3

INDUCTOR CURRENT

2

SW NODE

B

3

B

CH1 2V

CH2 5A

CH4 5V

Ω

M2ms

32.8%

A CH1

720mV

CH1 1V

CH2 5A

Ω

M1ms

63.2%

A CH1

1.56V

W

B

T

CH3 10V

T

CH3 10V

CH4 2V

W

Figure 54. Start-Up Behavior at Heavy Load, 18 A, 300 kHz

(See Figure 91 Application Circuit)

Figure 57. Soft Start and RES Detect Waveform

Rev. B | Page 15 of 40

ADP1872/ADP1873

Data Sheet

V

= 5.5V

= 3.6V

= 2.7V

DD

T

= 25°C

A

LOW SIDE

570

550

530

510

490

470

450

430

4

HIGH SIDE

SW NODE

3

2

M

HS MINUS

SW

CH2 5V

CH4 2V

M40ns

29.0%

A

CH2

4.20V

–40

–20

0

20

40

60

80

100

120

CH3 5V

MATH 2V 40ns

T

TEMPERATURE (°C)

Figure 61. Transconductance (G_M) vs. Temperature

Figure 58. Output Drivers and SW Node Waveforms

680

630

580

530

480

430

380

330

T

= 25°C

+125°C

+25°C

–40°C

A

LOW SIDE

16ns (t _{, DRVL})

f

4

22ns (

t

)

pdh, DRVH

HIGH SIDE

25ns (

t

)

, DRVH

r

SW NODE

3

2

HS MINUS

SW

M

CH2 5V

CH4 2V

M40ns

29.0%

A

CH2

4.20V

2.7

3.0

3.3

3.6

3.9

4.2

(V)

4.5

4.8

5.1

5.4

CH3 5V

MATH 2V 40ns

T

V

DD

Figure 59. Upper Side Driver Rising and Lower Side Falling Edge Waveforms

(C_GATE= 4.3 nF (Upper/Lower Side MOSFET),

Figure 62. Transconductance (G_M) vs. V_DD

Q_TOTAL= 27 nC (V_GS= 4.4 V (Q1), V_GS= 5 V (Q3))

1.30

18ns (

t

)

, DRVL

LOW SIDE

r

1.25

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

0.80

0.75

0.70

+125°C

+25°C

–40°C

4

HIGH SIDE

24ns (

t

)

pdh, DRVL

HS MINUS

SW

11ns (t _{, DRVH}

f

)

SW NODE

3

2

M

T

= 25°C

A

CH2 5V

CH4 2V

M20ns

T 39.2%

A

CH2

4.20V

2.7

3.1

3.5

3.9

4.3

(V)

4.7

5.1

5.5

CH3 5V

MATH 2V 20ns

V

DD

Figure 63. Quiescent Current vs. V_DD(VIN = 13 V)

Figure 60. Upper Side Driver Falling and Lower Side Rising Edge Waveforms

(C_GATE= 4.3 nF (Upper/Lower Side MOSFET),

Q_TOTAL= 27 nC (V_GS= 4.4 V (Q1), V_GS= 5 V (Q3))

Rev. B | Page 16 of 40

Data Sheet

ADP1872/ADP1873

ADP1872/ADP1873 BLOCK DIGRAM

ADP1872/

ADP1873

PRECISION ENABLE

BLOCK

TO ENABLE

ALL BLOCKS

COMP/EN

VDD

t_ON

VIN

BIAS

BLOCK

FILTER

V

DD

BST

REF_ZERO

I

SS

DRVH

SW

PFM

SS

COMP

STATE

MACHINE

DRIVERS

C

SS

SS_REF

ERROR

AMP

DRVL

FB

PGND

0.6V

PWM

I

REV

COMP

V

REG

800kΩ

CS

AMP

LOWER

COMP

CLAMP

CS GAIN

PROGRAMMING

ADC

REF_ZERO

CS GAIN SET

GND

Figure 64. ADP1872/ADP1873 Block Diagram

Rev. B | Page 17 of 40

ADP1872/ADP1873

Data Sheet

THEORY OF OPERATION

ADP1872/ADP1873

The ADP1872/ADP1873 are versatile current-mode, synchronous

step-down controllers that provide superior transient response,

optimal stability, and current limit protection by using a constant

on-time, pseudo-fixed frequency with a programmable current-

sense gain, current-control scheme. In addition, these devices offer

optimum performance at low duty cycles by using valley current-

mode control architecture. This allows the ADP1872/

ADP1873 to drive all N-channel power stages to regulate output

voltages as low as 0.6 V.

FB

V

DD

SS

ERROR

AMPLIFIER

0.6V

COMP/EN

C

PRECISION

ENABLE

C

C2

R

C

TO ENABLE

ALL BLOCKS

STARTUP

The ADP1872/ADP1873 have an input low voltage pin (VDD) for

biasing and supplying power for the integrated MOSFET drivers. A

bypass capacitor should be located directly across the VDD (Pin 5)

and PGND (Pin 7) pins. Included in the power-up sequence is

the biasing of the current-sense amplifier, the current-sense gain

circuit (see the Programming Resistor (RES) Detect Circuit

section), the soft start circuit, and the error amplifier.

285mV

Figure 65. Release COMP/EN Pin to Enable the ADP1872/ADP1873

COMP/EN

>2.4V

2.4V

HICCUP MODE INITIALIZED

MAXIMUM CURRENT (UPPER CLAMP)

The current-sense blocks provide valley current information

(see the Programming Resistor (RES) Detect Circuit section)

and are a variable of the compensation equation for loop stability

(see the Compensation Network section). The valley current

information is extracted by forcing 0.4 V across the DRVL output

and the PGND pin, which generates a current depending on the

resistor across DRVL and PGND in a process performed by the

RES detect circuit. The current through the resistor is used to set

the current-sense amplifier gain. This process takes approximately

800 µs, after which the drive signal pulses appear at the DRVL

and DRVH pins synchronously and the output voltage begins to

rise in a controlled manner through the soft start sequence.

1.0V

ZERO CURRENT

USABLE RANGE ONLY AFTER SOFT START

PERIOD IF CONTUNUOUS CONDUCTION

MODE OF OPERATION IS SELECTED.

500mV

LOWER CLAMP

285mV

0V

PRECISION ENABLE THRESHOLD

35mV HYSTERESIS

Figure 66. COMP/EN Voltage Range

UNDERVOLTAGE LOCKOUT

The rise time of the output voltage is determined by the soft start

and error amplifier blocks (see the Soft Start section). At the

beginning of a soft start, the error amplifier charges the external

compensation capacitor, causing the COMP/EN pin to rise above the

enable threshold of 285 mV, thus enabling the ADP1872/ADP1873.

The undervoltage lockout (UVLO) feature prevents the part

from operating both the upper side and lower side MOSFETs

at extremely low or undefined input voltage (VDD) ranges.

Operation at an undefined bias voltage may result in the incorrect

propagation of signals to the high-side power switches. This, in

turn, results in invalid output behavior that can cause damage

to the output devices, ultimately destroying the device tied at

the output. The UVLO level has been set at 2.65 V (nominal).

SOFT START

The ADP1872/ADP1873 have digital soft start circuitry, which

involves a counter that initiates an incremental increase in current,

by 1 µA, via a current source on every cycle through a fixed internal

capacitor. The output tracks the ramping voltage by producing

PWM output pulses to the upper side MOSFET. The purpose is to

limit the in-rush current from the high voltage input supply (VIN)

to the output (V_OUT).

THERMAL SHUTDOWN

The thermal shutdown is a self-protection feature to prevent the IC

from damage due to a very high operating junction temperature.

If the junction temperature of the device exceeds 155°C, the

part enters the thermal shutdown state. In this state, the device

shuts off both the upper side and lower side MOSFETs and

disables the entire controller immediately, thus reducing the

power consumption of the IC. The part resumes operation after

the junction temperature of the part cools to less than 140°C.

PRECISION ENABLE CIRCUITRY

The ADP1872/ADP1873 employ precision enable circuitry. The

enable threshold is 285 mV typical with 35 mV of hysteresis.

The devices are enabled when the COMP/EN pin is released,

allowing the error amplifier output to rise above the enable

threshold (see Figure 65). Grounding this pin disables the

ADP1872/ADP1873, reducing the supply current of the devices

to approximately 140 µA. For more information, see Figure 66.

Rev. B | Page 18 of 40

Data Sheet

ADP1872/ADP1873

PROGRAMMING RESISTOR (RES) DETECT CIRCUIT

VALLEY CURRENT-LIMIT SETTING

Upon startup, one of the first blocks to become active is the RES

detect circuit. This block powers up before soft start begins. It

forces a 0.4 V reference value at the DRVL output (see Figure 67)

and is programmed to identify four possible resistor values: 47 kΩ,

22 kΩ, open, and 100 kΩ.

The architecture of the ADP1872/ADP1873 is based on valley

current-mode control. The current limit is determined by three

components: the R_ONof the lower side MOSFET, the error amplifier

output voltage swing (COMP), and the current-sense gain. The

COMP range is internally fixed at 1.4 V. The current-sense gain

is programmable via an external resistor at the DRVL pin (see

the Programming Resistor (RES) Detect Circuit section). The

The RES detect circuit digitizes the value of the resistor at the

DRVL pin (Pin 6). An internal ADC outputs a 2-bit digital code

that is used to program four separate gain configurations in the

current-sense amplifier (see Figure 68). Each configuration

corresponds to a current-sense gain (A_CS) of 3 V/V, 6 V/V, 12 V/V,

24 V/V, respectively (see Table 5 and Table 6). This variable is used

for the valley current-limit setting, which sets up the appropriate

current-sense gain for a given application and sets the compensation

necessary to achieve loop stability (see the Valley Current-Limit

Setting and Compensation Network sections).

R_ONof the lower side MOSFET can vary over temperature and

usually has a positive T_C(meaning that it increases with

temperature); therefore, it is recommended to program the

current-sense gain resistor based on the rated R_ONof the

MOSFET at 125°C.

Because the ADP1872/ADP1873 are based on valley current

control, the relationship between I_CLIMand I_LOADis

K_I

2











I_CLIM I_LOAD 1 



ADP1872

Q1

DRVH

where:

I_CLIMis the desired valley current limit.

SW

I_LOADis the current load.

Q2

DRVL

K_Iis the ratio between the inductor ripple current and the

desired average load current (see Figure 10). Establishing K_I

helps to determine the inductor value (see the Inductor

Selection section), but in most cases, K_I= 0.33.

R

RES

CS GAIN

PROGRAMMING

Figure 67. Programming Resistor Location

SW

PGND

CS

AMP

I

LOAD

RIPPLE CURRENT =

3

LOAD CURRENT

ADC

CS GAIN SET

DRVL

0.4V

VALLEY CURRENT LIMIT

Figure 69. Valley Current Limit to Average Current Relation

RES

When the desired valley current limit (I_CLIM) has been determined,

the current-sense gain can be calculated by

Figure 68. RES Detect Circuit for Current-Sense Gain Programming

1.4 V

I_CLIM



Table 5. Current-Sense Gain Programming

A

_CSR_ON

Resistor

A_CS(V/V)

where:

A_CSis the current-sense gain multiplier (see Table 5 and Table 6).

_ONis the channel impedance of the lower side MOSFET.

47 kΩ

22 kΩ

Open

100 kΩ

3

6

12

24

R

Although the ADP1872/ADP1873 have only four discrete current-

sense gain settings for a given R_ONvariable, Table 6 and Figure 70

outline several available options for the valley current setpoint

based on various R_ONvalues.

Rev. B | Page 19 of 40

ADP1872/ADP1873

Data Sheet

Table 6. Valley Current Limit Program¹

The valley current limit is programmed as outlined in Table 6

and Figure 70. The inductor chosen must be rated to handle the

peak current, which is equal to the valley current from Table 6

plus the peak-to-peak inductor ripple current (see the Inductor

Selection section). In addition, the peak current value must be

used to compute the worst-case power dissipation in the MOSFETs

(see Figure 71).

Valley Current Level

47 kΩ

22 kΩ

Open

100 kΩ

R_ON

(mΩ) A_CS= 3 V/V A_CS= 6 V/V A_CS= 12 V/V A_CS= 24 V/V

1.5

2

38.9

29.2

23.3

19.5

16.7

13

11.7

10.6

5.83

3.87

3.25

2.5

3

3.5

4.5

5

5.5

10

15

18

49A

39.0

33.4

26.0

23.4

21.25

11.7

7.75

6.5

MAXIMUM DC LOAD

CURRENT

39.5A

∆I = 65%

OF 37A

INDUCTOR

CURRENT

COMP

OUTPUT

37A

35A

23.3

15.5

13.0

∆I = 45%

OF 32.25A

32.25A

∆I = 33%

OF 30A

31.0

26.0

30A

2.4V

¹Refer to Figure 70 for more information and a graphical representation.

VALLEY CURRENT LIMIT

THRESHOLD (SET FOR 25A)

39

37

35

COMP

OUTPUT

SWING

RES = 47kΩ

= 3V/V

33

31

29

27

25

23

21

19

17

15

13

11

9

A

CS

0A

1V

Figure 71. Valley Current-Limit Threshold in Relation to Inductor Ripple Current

RES = 22kΩ

= 6V/V

A

RES = NO RES

= 12V/V

CS

A

CS

HICCUP MODE DURING SHORT CIRCUIT

A current-limit violation occurs when the current across the

source and drain of the lower side MOSFET exceeds the current-

limit setpoint. When 32 current-limit violations are detected,

the controller enters idle mode and turns off the MOSFETs for

6 ms, allowing the converter to cool down. Then, the controller

re-establishes soft start and begins to cause the output to ramp

up again (see Figure 72). While the output ramps up, COMP is

monitored to determine if the violation is still present. If it is still

present, the idle event occurs again, followed by the full-chip

power-down sequence. This cycle continues until the violation

no longer exists. If the violation disappears, the converter is

allowed to switch normally, maintaining regulation.

RES = 100kΩ

A

= 24V/V

7

5

3

CS

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

(mΩ)

R

ON

Figure 70. Valley Current-Limit Value vs. R_ONof the Lower Side MOSFET

for Each Programming Resistor (RES)

REPEATED CURRENT LIMIT

VIOLATION DETECTED

HS

A PREDETERMINED NUMBER SOFT START IS

OF PULSES IS COUNTED TO REINITIALIZED TO

ALLOW THE CONVERTER MONITOR IF THE

CLIM

TO COOL DOWN

VIOLATION

STILL EXISTS

ZERO

CURRENT

Figure 72. Idle Mode Entry Sequence Due to Current-Limit Violations

Rev. B | Page 20 of 40

Data Sheet

ADP1872/ADP1873

As soon as the forward current through the lower side MOSFET

decreases to a level where

SYNCHRONOUS RECTIFIER

The ADP1872/ADP1873 employ an internal lower side MOSFET

driver to drive the external upper side and lower side MOSFETs.

The synchronous rectifier not only improves overall conduction

efficiency but also ensures proper charging to the bootstrap

capacitor located at the upper side driver input. This is beneficial

during startup to provide sufficient drive signal to the external

upper side MOSFET and attain fast turn-on response, which is

essential for minimizing switching losses. The integrated upper

and lower side MOSFET drivers operate in complementary

fashion with built-in anticross conduction circuitry to prevent

unwanted shoot-through current that may potentially damage the

MOSFETs or reduce efficiency as a result of excessive power loss.

10 mV = I_Q2× R_ON(Q2)

the zero-cross comparator (or I_REVcomparator) emits a signal to

turn off the lower side MOSFET. From this point, the slope of the

inductor current ramping down becomes steeper (see Figure 75)

as the body diode of the lower side MOSFET begins to conduct

current and continues conducting current until the remaining

energy stored in the inductor has been depleted.

ANOTHER t_ONEDGE IS

TRIGGERED WHEN V

OUT

FALLS BELOW REGULATION

SW

t_ON

POWER SAVING MODE (PSM) VERSION (ADP1873)

The power saving mode version of the ADP1872 is the ADP1873.

The ADP1873 operates in the discontinuous conduction mode

(DCM) and pulse skips at light load to midload currents. It

outputs pulses as necessary to maintain output regulation. Unlike

the continuous conduction mode (CCM), DCM operation

prevents negative current, thus allowing improved system

efficiency at light loads. Current in the reverse direction through

this pathway, however, results in power dissipation and therefore

a decrease in efficiency.

HS AND LS

IN IDLE MODE

LS

ZERO-CROSS COMPARATOR

DETECTS 10mV OFFSET AND

TURNS OFF LS

I

LOAD

0A

10mV = R

× I

LOAD

ON

HS

t_ON

Figure 75. 10 mV Offset to Ensure Prevention of Negative Inductor Current

The system remains in idle mode until the output voltage drops

below regulation. A PWM pulse is then produced, turning on the

upper side MOSFET to maintain system regulation. The ADP1873

does not have an internal clock; therefore, it switches purely as a

hysteretic controller, as described in this section.

HS AND LS ARE OFF

OR IN IDLE MODE

LS

t_OFF

TIMER OPERATION

The ADP1872/ADP1873 employ a constant on-time architecture,

which provides a variety of benefits, including improved load

and line transient response when compared with a constant

(fixed) frequency current-mode control loop of comparable

loop design. The constant on-time timer, or t_ONtimer, senses

the high input voltage (VIN) and the output voltage (V_OUT) using

SW waveform information to produce an adjustable one-shot

PWM pulse that varies the on-time of the upper side MOSFET in

response to dynamic changes in input voltage, output voltage, and

load current conditions to maintain regulation. It then generates

an on-time (t_ON) pulse that is inversely proportional to V_IN.

AS THE INDUCTOR

CURRENT APPROACHES

ZERO CURRENT, THE STATE

I

LOAD

0A

MACHINE TURNS OFF THE

LOWER SIDE MOSFET.

Figure 73. Discontinuous Mode of Operation (DCM)

To minimize the chance of negative inductor current buildup,

an on-board, zero-cross comparator turns off all upper side

and lower side switching activities when the inductor current

approaches the zero current line, causing the system to enter

idle mode, where the upper side and lower side MOSFETs are

turned off. To ensure idle mode entry, a 10 mV offset, connected

in series at the SW node, is implemented (see Figure 74).

ZERO-CROSS

V_OUT

t_ON K 

VIN

where K is a constant that is trimmed using an RC timer product

for the 300 kHz, 600 kHz, and 1.0 MHz frequency options.

SW

COMPARATOR

I

Q2

10mV

Q2

LS

Figure 74. Zero-Cross Comparator with 10 mV of Offset

Rev. B | Page 21 of 40

ADP1872/ADP1873

Data Sheet

VDD

VIN

To illustrate this feature more clearly, this section describes

t_ON

one such load transient event—a positive load step—in detail.

During load transient events, the high-side driver output pulse

width stays relatively consistent from cycle to cycle; however,

the off-time (DRVL on-time) dynamically adjusts according to

the instantaneous changes in the external conditions mentioned.

C

I

SW

INFORMATION

When a positive load step occurs, the error amplifier (out of

phase of the output, V_OUT) produces new voltage information

at its output (COMP). In addition, the current-sense amplifier

senses new inductor current information during this positive

load transient event. The error amplifier’s output voltage

reaction is compared to the new inductor current information

that sets the start of the next switching cycle. Because current

information is produced from valley current sensing, it is sensed

at the down ramp of the inductor current, whereas the voltage

loop information is sensed through the counter action upswing

of the error amplifier’s output (COMP).

R (TRIMMED)

Figure 76. Constant On-Time Timer

The constant on-time (t_ON) is not strictly constant because it varies

with VIN and V_OUT. However, this variation occurs in such a

way as to keep the switching frequency virtually independent

of VIN and V_OUT

.

The t_ONtimer uses a feedforward technique, applied to the constant

on-time control loop, making it pseudo-fixed frequency to a first

order. Second-order effects, such as dc losses in the external power

MOSFETs (see the Efficiency Consideration section), cause some

variation in frequency vs. load current and line voltage. These

effects are shown in Figure 22 to Figure 33. The variations in

frequency are much reduced compared with the variations

generated when the feedforward technique is not used.

The result is a convergence of these two signals (see Figure 77),

which allows an instantaneous increase in switching frequency

during the positive load transient event. In summary, a positive

load step causes V_OUTto transient down, which causes COMP to

transient up and therefore shortens the off time. This resulting

increase in frequency during a positive load transient helps to

quickly bring V_OUTback up in value and within the regulation

window.

The feedforward technique establishes the following relationship:

f

_SW= 1/K

where f_SWis the controller switching frequency (300 kHz,

600 kHz, and 1.0 MHz).

Similarly, a negative load step causes the off time to lengthen in

response to V_OUTrising. This effectively increases the inductor

demagnetizing phase, helping to bring V_OUTto within regulation.

In this case, the switching frequency decreases, or experiences a

foldback, to help facilitate output voltage recovery.

The t_ONtimer senses VIN and V_OUTto minimize frequency variation

with VIN and V_OUTas previously explained. This provides a

pseudo-fixed frequency, see the Pseudo-Fixed Frequency section

for additional information. To allow headroom for VIN/V_OUT

sensing, the following two equations must be adhered to. For

typical applications where V_DDis 5 V, these equations are not

relevant; however, for lower V_DD, care may be required.

Because the ADP1872/ADP1873 has the ability to respond

rapidly to sudden changes in load demand, the recovery period

in which the output voltage settles back to its original steady

state operating point is much quicker than it would be for a

fixed-frequency equivalent. Therefore, using a pseudo-fixed

frequency, results in significantly better load transient

performance than using a fixed frequency.

V

_DD≥ VIN/8 + 1.5

V_DD≥ V_OUT/4

PSEUDO-FIXED FREQUENCY

The ADP1872/ADP1873 employ a constant on-time control

scheme. During steady state operation, the switching frequency

stays relatively constant, or pseudo-fixed. This is due to the one-

shot t_ONtimer that produces a high-side PWM pulse with a fixed

duration, given that external conditions such as input voltage,

output voltage, and load current are also at steady state. During

load transients, the frequency momentarily changes for the

duration of the transient event so that the output comes back

within regulation quicker than if the frequency were fixed or if

it were to remain unchanged. After the transient event is complete,

the frequency returns to a pseudo-fixed value to a first-order.

LOAD CURRENT

DEMAND

CS AMP

OUTPUT

ERROR AMP

OUTPUT

VALLEY

TRIP POINTS

PWM OUTPUT

f_SW

>f_SW

Figure 77. Load Transient Response Operation

Rev. B | Page 22 of 40

Data Sheet

ADP1872/ADP1873

APPLICATIONS INFORMATION

FEEDBACK RESISTOR DIVIDER

Table 7. Recommended Inductors

L

DCR

I_SAT

Dimensions

(mm)

The required resistor divider network can be determine for a

given V_OUTvalue because the internal band gap reference (V_REF

is fixed at 0.6 V. Selecting values for R_Tand R_Bdetermines the

minimum output load current of the converter. Therefore, for a

given value of R_B, the R_Tvalue can be determined by

(µH) (mΩ) (A)

Manufacturer

Würth Elektronic

Sumida

Model No.

744303012

744303022

744355147

744325072

744355090

744325120

7443552100

744318180

7443551200

CEP125U-0R8

)

0.12

0.22

0.47

0.72

0.9

1.2

1.0

1.4

2.0

0.33

0.8

1.65

1.6

1.8

3.3

3.2

2.6

55

30

50

35

28

25

20

24

22

27.5

10.2 × 7

14.2 × 12.8

10.5 × 10.2

13 × 12.8

10.5 × 10.2

14 × 12.8

13.2 × 12.8

(V_OUT−0.6 V)

R_T= R_B×

0.6 V

INDUCTOR SELECTION

The inductor value is inversely proportional to the inductor

ripple current. The peak-to-peak ripple current is given by

0.8

I_LOAD

3

OUTPUT RIPPLE VOLTAGE (ΔV_RR)

∆I_L= K _I× I_LOAD

≈

The output ripple voltage is the ac component of the dc output

voltage during steady state. For a ripple error of 1.0%, the output

capacitor value needed to achieve this tolerance can be determined

using the following equation. (Note that an accuracy of 1.0% is

only possible during steady state conditions, not during load

transients.)

where K_Iis typically 0.33.

The equation for the inductor value is given by

(VIN −V_OUT

∆I_L× f_SW

)

V_OUT

VIN

L =

×

ΔV_RR= (0.01) × V_OUT

where:

VIN is the high voltage input.

_OUTis the desired output voltage.

_SWis the controller switching frequency (300 kHz, 600 kHz,

OUTPUT CAPACITOR SELECTION

V

f

The primary objective of the output capacitor is to facilitate

the reduction of the output voltage ripple; however, the output

capacitor also assists in the output voltage recovery during load

transient events. For a given load current step, the output voltage

ripple generated during this step event is inversely proportional

to the value chosen for the output capacitor. The speed at which

the output voltage settles during this recovery period depends

on where the crossover frequency (loop bandwidth) is set. This

crossover frequency is determined by the output capacitor, the

equivalent series resistance (ESR) of the capacitor, and the

compensation network.

and 1.0 MHz).

When selecting the inductor, choose an inductor saturation rating

that is above the peak current level and then calculate the

inductor current ripple (see the Valley Current-Limit Setting

section and Figure 78).

52

50

ΔI = 50%

ΔI = 40%

48

46

44

42

40

38

36

34

32

30

28

26

24

22

20

18

16

14

12

10

8

To calculate the small signal voltage ripple (output ripple

voltage) at the steady state operating point, use the following

equation:

ΔI = 33%













1

C_OUT= ∆I_L×

8× f_SW

×

[

∆V_RIPPLE−(∆I_L× ESR)

]

where ESR is the equivalent series resistance of the output

capacitors.

6

8

10 12 14 16 18 20 22 24 26 28 30

VALLEY CURRENT LIMIT (A)

To calculate the output load step, use the following equation:

Figure 78. Peak Current vs. Valley Current Threshold for

33%, 40%, and 50% of Inductor Ripple Current

∆I_LOAD

C_OUT= 2 ×

f_SW×(∆V_DROOP− (∆I_LOAD× ESR))

where ΔV_DROOPis the amount that V_OUTis allowed to deviate for

a given positive load current step (ΔI_LOAD).

Rev. B | Page 23 of 40

ADP1872/ADP1873

Data Sheet

Ceramic capacitors are known to have low ESR. However, the

trade-off of using X5R technology is that up to 80% of its capaci-

tance may be lost due to derating because the voltage applied

across the capacitor is increased (see Figure 79). Although X7R

series capacitors can also be used, the available selection is

limited to only up to 22 µF.

Error Amplifier Output Impedance (Z_COMP

)

Assuming C_C2is significantly smaller than C_COMP, C_C2can be

omitted from the output impedance equation of the error amplifier.

The transfer function simplifies to

R

_COMP( f_CROSS+ f_ZERO)

Z_COMP

=

f_CROSS

20

10

and

X7R (50V)

0

1

12

–10

–20

–30

–40

f_CROSS

=

× f_SW

where f_ZERO, the zero frequency, is set to be 1/4^thof the crossover

frequency for the ADP1872.

–50

Error Amplifier Gain (G_M)

The error amplifier gain (transconductance) is

G_M= 500 µA/V

X5R (25V)

–60

–70

X5R (16V)

–80

10µF TDK 25V, X7R, 1210 C3225X7R1E106M

22µF MURATA 25V, X7R, 1210 GRM32ER71E226KE15L

47µF MURATA 16V, X5R, 1210 GRM32ER61C476KE15L

–90

Current-Sense Loop Gain (G_CS)

The current-sense loop gain is

1

–100

0

5

10

15

20

25

30

DC VOLTAGE (V

)

DC

Figure 79. Capacitance vs. DC Voltage Characteristics for Ceramic Capacitors

G_CS

=

(A/V)

A

_CS×R_ON

Electrolytic capacitors satisfy the bulk capacitance requirements

for most high current applications. Because the ESR of electrolytic

capacitors is much higher than that of ceramic capacitors, when

using electrolytic capacitors, several MLCCs should be mounted

in parallel to reduce the overall series resistance.

where:

_CS(V/V) is programmable for 3 V/V, 6 V/V, 12 V /V, and 24 V/V

A

(see the Programming Resistor (RES) Detect Circuit and Valley

Current-Limit Setting sections).

R_ONis the channel impedance of the lower side MOSFET.

COMPENSATION NETWORK

Crossover Frequency

Due to its current-mode architecture, the ADP1872/ADP1873

require Type II compensation. To determine the component

values needed for compensation (resistance and capacitance

values), it is necessary to examine the converter’s overall loop

gain (H) at the unity gain frequency (f_SW/10) when H = 1 V/V.

The crossover frequency is the frequency at which the overall

loop (system) gain is 0 dB (H = 1 V/V). It is recommended for

current-mode converters, such as the ADP1872, that the user

set the crossover frequency between 1/10^thand 1/15^thof the

switching frequency.

V_OUT

V_REF

H =1 V/V = G_M×G_CS

×

× Z_COMP× Z_FILT

1

12

f_CROSS

=

f_SW

Examining each variable at high frequency enables the unity

gain transfer function to be simplified to provide expressions

for the R_COMPand C_COMPcomponent values.

The relationship between C_COMPand f_ZERO(zero frequency) is

1

f_ZERO

=

2π× R_COMP×C_COMP

Output Filter Impedance (Z_FILT

)

The zero frequency is set to 1/4^thof the crossover frequency.

Combining all of the above parameters results in

Examining the filter’s transfer function at high frequencies

simplifies to

1

f_CROSS

_CROSS+ f_ZERO

2πf_CROSSC_OUTV_OUT

Z_FILTER

=

R_COMP

=

×

sC_OUT

at the crossover frequency (s = 2πf_CROSS).

f

G_MG_CS

V_REF

1

C_COMP

2× π× R_COMP× f_ZERO

Rev. B | Page 24 of 40

Data Sheet

ADP1872/ADP1873

800

720

640

560

480

400

320

240

160

80

EFFICIENCY CONSIDERATION

V

= 2.7V

= 3.6V

= 5.5V

DD

One of the important criteria to consider in constructing a dc-to-dc

converter is efficiency. By definition, efficiency is the ratio of the

output power to the input power. For high power applications at

load currents up to 20 A, the following are important MOSFET

parameters that aid in the selection process:



V_{GS (TH)}: the MOSFET support voltage applied between the

gate and the source.



R_{DS (ON)}: the MOSFET on resistance during channel

conduction.

+125°C

+25°C

–40°C



Q_G: the total gate charge

C_N1: the input capacitance of the upper side switch

C_N2: the input capacitance of the lower side switch

300

400

500

600

700

800

900

1000

FREQUENCY (kHz)

Figure 80. Internal Rectifier Voltage Drop vs. Switching Frequency

The following are the losses experienced through the external

component during normal switching operation:

MOSFET Switching Loss

The SW node transitions due to the switching activities of the

upper side and lower side MOSFETs. This causes removal and

replenishing of charge to and from the gate oxide layer of the

MOSFET, as well as to and from the parasitic capacitance

associated with the gate oxide edge overlap and the drain and

source terminals. The current that enters and exits these charge

paths presents additional loss during these transition times.

This can be approximately quantified by using the following

equation, which represents the time in which charge enters and

exits these capacitive regions.



Channel conduction loss (both the MOSFETs)

MOSFET driver loss

MOSFET switching loss

Body diode conduction loss (lower side MOSFET)

Inductor loss (copper and core loss)

Channel Conduction Loss

During normal operation, the bulk of the loss in efficiency is due

to the power dissipated through MOSFET channel conduction.

Power loss through the upper side MOSFET is directly proportional

to the duty cycle (D) for each switching period, and the power

loss through the lower side MOSFET is directly proportional to

1 − D for each switching period. The selection of MOSFETs is

governed by the amount of maximum dc load current that the

converter is expected to deliver. In particular, the selection of

the lower side MOSFET is dictated by the maximum load

current because a typical high current application employs duty

cycles of less than 50%. Therefore, the lower side MOSFET is in

the on state for most of the switching period.

t

_SW-TRANS= R_GATE× C_TOTAL

where:

_GATEis the gate input resistance of the MOSFET.

_TOTALis the C_GD+ C_GSof the external MOSFET used.

R

C

The ratio of this time constant to the period of one switching cycle

is the multiplying factor to be used in the following expression:

t_SW-TRANS

P_SW(LOSS)



I_LOADVIN 2

t_SW

I_L²_OAD

_{N1, N2 (CL)}= [D × R_{N1 (ON)}+ (1 − D) × R_{N2 (ON)}] ×

or

P

_{SW (LOSS)}= f_SW× R_GATE× C_TOTAL× I_LOAD× VIN × 2

MOSFET Driver Loss

Other dissipative elements are the MOSFET drivers. The

contributing factors are the dc current flowing through the

driver during operation and the Q_GATEparameter of the external

MOSFETs.

P

_DR(LOSS)



V

_DR



f_SW

C

V

_DR I_BIAS









V

_DD



f_SWC_lowerFET

V

_DD^u^ppI^er_B^F_I^E_A^T_S



where:

C

_upperFETis the input gate capacitance of the upper-side MOSFET.

_lowerFETis the input gate capacitance of the lower-side MOSFET.

V

_DRis the driver bias voltage (that is, the low input voltage (V_DD)

minus the rectifier drop (see Figure 80)).

_BIASis the dc current flowing into the upper- and lower-side drivers.

_DDis the bias voltage.

I

V

Rev. B | Page 25 of 40

ADP1872/ADP1873

Data Sheet

Body Diode Conduction Loss

INPUT CAPACITOR SELECTION

The ADP1872/ADP1873 employ anticross conduction circuitry

that prevents the upper side and lower side MOSFETs from

conducting current simultaneously. This overlap control is

beneficial, avoiding large current flow that may lead to

irreparable damage to the external components of the power

stage. However, this blanking period comes with the trade-off of

a diode conduction loss occurring immediately after the

MOSFETs change states and continuing well into idle mode.

The amount of loss through the body diode of the lower side

MOSFET during the antioverlap state is given by

The goal in selecting an input capacitor is to reduce or to minimize

input voltage ripple and to reduce the high frequency source

impedance, which is essential for achieving predictable loop

stability and transient performance.

The problem with using bulk capacitors, other than their physical

geometries, is their large equivalent series resistance (ESR) and

large equivalent series inductance (ESL). Aluminum electrolytic

capacitors have such high ESR that they cause undesired input

voltage ripple magnitudes and are generally not effective at high

switching frequencies.

t_BODY(LOSS)

If bulk capacitors are to be used, it is recommended to use multi-

layered ceramic capacitors (MLCC) in parallel due to their low

ESR values. This dramatically reduces the input voltage ripple

amplitude as long as the MLCCs are mounted directly across

the drain of the upper side MOSFET and the source terminal of

the lower side MOSFET (see the Layout Considerations section).

Improper placement and mounting of these MLCCs may cancel

their effectiveness due to stray inductance and an increase in

trace impedance.

P_BODY(LOSS)

 I_LOADV_F2

t_SW

where:

t

_{BODY (LOSS)}is the body conduction time (refer to Figure 81 for

dead time periods).

_SWis the period per switching cycle.

t

V_Fis the forward drop of the body diode during conduction.

(Refer to the selected external MOSFET data sheet for more

information about the V_Fparameter.)

80

V_OUT





VIN V_OUT



+125°C

+25°C

–40°C

1MHz

300kHz

I_{CIN ,RMS} I_LOAD,MAX



72

64

56

48

40

32

24

16

8

V_OUT

The maximum input voltage ripple and maximum input capacitor

rms current occur at the end of the duration of 1 − D while the

upper side MOSFET is in the off state. The input capacitor rms

current reaches its maximum at time D. When calculating the

maximum input voltage ripple, account for the ESR of the input

capacitor as follows:

V

_{MAX, RIPPLE}= V_RIPP+ (I_{LOAD, MAX}× ESR)

where:

V

_RIPPis usually 1% of the minimum voltage input.

2.7

3.4

4.1

(V)

4.8

5.5

I

_{LOAD, MAX}is the maximum load current.

V

DD

ESR is the equivalent series resistance rating of the input

capacitor used.

Figure 81. Body Diode Conduction Time vs. Low Voltage Input (V_DD

)

Inductor Loss

Inserting V_{MAX, RIPPLE}into the charge balance equation to calculate

the minimum input capacitor requirement gives

During normal conduction mode, further power loss is caused

by the conduction of current through the inductor windings,

which have dc resistance (DCR). Typically, larger sized inductors

have smaller DCR values.

I_{LOAD, MAX}

D(1 D)

C_IN,min





V_{MAX, RIPPLE}

f_SW

or

The inductor core loss is a result of the eddy currents generated

within the core material. These eddy currents are induced by the

changing flux, which is produced by the current flowing through

the windings. The amount of inductor core loss depends on the

core material, the flux swing, the frequency, and the core volume.

Ferrite inductors have the lowest core losses, whereas powdered iron

inductors have higher core losses. It is recommended to use shielded

ferrite core material type inductors with the ADP1872/ADP1873

for a high current, dc-to-dc switching application to achieve

minimal loss and negligible electromagnetic interference (EMI).

I_{LOAD, MAX}

4 f_SWV_{MAX, RIPPLE}

C_IN,min



where D = 50%.

2

P

_{DCR (LOSS)}= DCR ×

+ Core Loss

I_LOAD

Rev. B | Page 26 of 40

Data Sheet

ADP1872/ADP1873

For example, if the external MOSFET characteristics are θ_JA

(10-lead MSOP) = 171.2°C/W, f_SW= 300 kHz, I_BIAS= 2 mA,

THERMAL CONSIDERATIONS

The ADP1872/ADP1873 are used for dc-to-dc, step down, high

current applications that have an on-board controller and on-board

MOSFET drivers. Because applications may require up to 20 A of

load current delivery and be subjected to high ambient temperature

surroundings, the selection of external upper side and lower side

MOSFETs must be associated with careful thermal consideration

to not exceed the maximum allowable junction temperature

of 125°C. To avoid permanent or irreparable damage if the

junction temperature reaches or exceeds 155°C, the part enters

thermal shutdown, turning off both external MOSFETs, and

does not re-enable until the junction temperature cools to 140°C

(see the Thermal Shutdown section).

C_upperFET= 3.3 nF, C_lowerFET= 3.3 nF, V_DR= 5.12 V, and V_DD= 5 . 5 V,

then the power loss is

P

_{DR (LOSS)}= [V_DR× (f_SWC_upperFETV_DR+ I_BIAS)] + [V_DD×

(f_SWC_lowerFETV_DD+ I_BIAS)]

= [5.12 × (300 × 10³× 3.3 × 10⁻⁹× 5.12 + 0.002)] +

[5.5 × (300 × 10³×3.3 × 10⁻⁹× 5.5 + 0.002)]

= 77.13 mW

The rise in package temperature is

T_R= θ_JA× P_{DR (LOSS)}

= 171.2°C × 77.13 mW

= 13.2°C

The maximum junction temperature allowed for the ADP1872/

ADP1873 ICs is 125°C. This means that the sum of the ambient

temperature (T_A) and the rise in package temperature (T_R), which

is caused by the thermal impedance of the package and the internal

power dissipation, should not exceed 125°C, as dictated by

Assuming a maximum ambient temperature environment of 85°C,

the junction temperature is

T_J= T_R× T_A= 13.2°C + 85°C = 98.2°C

which is below the maximum junction temperature of 125°C.

DESIGN EXAMPLE

T_J= T_R× T_A

where:

The ADP1872/ADP1873 are easy to use, requiring only a few

design criteria. For example, the example outlined in this section

uses only four design criteria: V_OUT= 1.8 V, I_LOAD= 15 A (pulsing),

VIN = 12 V (typical), and f_SW= 300 kHz.

T_Jis the maximum junction temperature.

T_Ris the rise in package temperature due to the power

dissipated from within.

T_Ais the ambient temperature.

Input Capacitor

The rise in package temperature is directly proportional to its

thermal impedance characteristics. The following equation

represents this proportionality relationship:

The maximum input voltage ripple is usually 1% of the

minimum input voltage (11.8 V × 0.01 = 120 mV).

V_RIPP= 120 mV

T_R= θ_JA× P_{DR (LOSS)}

V_{MAX, RIPPLE}= V_RIPP− (I_{LOAD, MAX}× ESR)

where:

= 120 mV − (15 A × 0.001) = 45 mV

I_{LOAD, MAX}

4 f_SWV_{MAX, RIPPLE}4×300×10³×105 mV

θ

_JAis the thermal resistance of the package from the junction to

the outside surface of the die, where it meets the surrounding air.

_{DR (LOSS)}is the overall power dissipated by the IC.

15 A

C_{IN, min}

=

P

The bulk of the power dissipated is due to the gate capacitance

of the external MOSFETs. The power loss equation of the

MOSFET drivers (see the MOSFET Driver Loss section in the

Efficiency Consideration section) is

= 120 µF

Choose five 22 µF ceramic capacitors. The overall ESR of five

22 µF ceramic capacitors is less than 1 mΩ.

I_RMS= I_LOAD/2 = 7.5 A

P

_{DR (LOSS)}= [V_DR× (f_SWC_upperFET

(f_SWC_{lowerFET DD}+ I_BIAS)]

where:

V_DR+ I_BIAS)] + [V_DD×

P

_CIN= (I_RMS)²× ESR = (7.5A)²× 1 mΩ = 56.25 mW

V

Inductor

Determining inductor ripple current amplitude:

C_upperFETis the input gate capacitance of the upper side MOSFET.

C

_lowerFETis the input gate capacitance of the lower side MOSFET.

I_LOAD

3

∆I_L≈

= 5 A

I

_BIASis the dc current (2 mA) flowing into the upper side and

lower side drivers.

_DRis the driver bias voltage (that is, the low input voltage (V_DD

minus the rectifier drop (see Figure 80)).

_DDis the bias voltage

so calculating for the inductor value

V

)

(V_{IN, MAX}−V_OUT

∆I_L× f_SW

)

V_OUT

V_{IN, MAX}

L =

×

V

(13.2 V −1.8 V) 1.8 V

×

=

5 V ×300×10³13.2 V

= 1.03 µH

Rev. B | Page 27 of 40

ADP1872/ADP1873

Data Sheet

The inductor peak current is approximately

15 A + (5 A × 0.5) = 17.5 A

Choose five 270 µF polymer capacitors.

The rms current through the output capacitor is

(V_IN,MAX−V_OUT

L× f_SW

)

Therefore, an appropriate inductor selection is 1.0 µH with

DCR = 3.3 mΩ (7443552100) from Table 7 with peak current

handling of 20 A.

P_{DCR (LOSS)}= DCR× I_L²_OAD

= 0.003 × (15 A)²= 675 mW

Current Limit Programming

The valley current is approximately

15 A − (5 A × 0.5) = 12.5 A

V_OUT

V_IN,MAX

1

2

1

3

I_RMS

=

×

(13.2 V −1.8 V) 1.8 V

×

1

2

1

3

=

×

= 1.49 A

1μF×300×10³13.2 V

The power loss dissipated through the ESR of the output

capacitor is

P

_COUT= (I_RMS)²× ESR = (1.5 A)²× 1.4 mΩ = 3.15 mW

Feedback Resistor Network Setup

It is recommended to use R_B= 15 kΩ. Calculate R_Tas

(1.8 V − 0.6 V)

Assuming a lower side MOSFET R_ONof 4.5 mΩ, choosing 13 A

as the valley current limit from Table 6 and Figure 70 indicates

that a programming resistor (RES) of 100 kΩ corresponds to an

R_T=15 kΩ×

= 30 kΩ

0.6 V

Compensation Network

A

_CSof 24 V /V.

Choose a programmable resistor of R_RES= 100 kΩ for a current-

sense gain of 24 V /V.

To calculate R_COMP, C_COMP, and C_PAR, the transconductance

parameter and the current-sense gain variable are required. The

transconductance parameter (G_M) is 500 µA/V, and the current-

sense loop gain is

Output Capacitor

Assume a load step of 15 A occurs at the output and no more

than 5% is allowed for the output to deviate from the steady

state operating point. The ADP1872’s advantage is, because the

frequency is pseudo-fixed, the converter is able to respond

quickly because of the immediate, though temporary, increase

in switching frequency.

1

G_CS

=

= 8.33 A/V

A_CSR_ON24×0.005

where A_CSand R_ONare taken from setting up the current limit

(see the Programming Resistor (RES) Detect Circuit and Valley

Current-Limit Setting sections).

ΔV_DROOP= 0.05 × 1.8 V = 90 mV

The crossover frequency is 1/12^thof the switching frequency:

Assuming the overall ESR of the output capacitor ranges from

5 mΩ to 10 mΩ,

300 kHz/12 = 25 kHz

The zero frequency is 1/4^thof the crossover frequency:

25 kHz/4 = 6.25 kHz

∆I_LOAD

C_OUT= 2×

f

_SW×(∆V_DROOP

15A

)

= 2×

f_CROSS

_CROSS+ f_ZERO

2πf_CROSSC_OUTV_OUT

300×10³×(90 mV)

R_COMP

=

×

f

G_MG_CS

V_REF

= 1.11 mF

25×10³

2×3.141×25×10³×1.11×10⁻³1.8

=

×

Therefore, an appropriate inductor selection is five 270 µF

polymer capacitors with a combined ESR of 3.5 mΩ.

25×10³+ 6.25×10³

500×10⁻⁶×8.3

0.6

= 100 kΩ

Assuming an overshoot of 45 mV, determine if the output

capacitor that was calculated previously is adequate:

1

C_COMP

=

2πR_COMPf_ZERO

(L × I²

)

LOAD

C_OUT

=

1

(V_OUT− ∆V_OVSHT)²−

1×10⁻⁶×(15 A)²

(1.8 − 45 mV)²−(1.8)²

(

V_OUT

)

=

2

(

2×3.14×100×10³×6.25×10³

= 250 pF

=

= 1.4 mF

Rev. B | Page 28 of 40

Data Sheet

ADP1872/ADP1873

Loss Calculations

P_{SW (LOSS)}= f_SW× R_GATE× C_TOTAL× I_LOAD× VIN × 2

= 300 × 10³× 1.5 Ω × 3.3 × 10⁻⁹× 15 A × 12 × 2

= 534.6 mW

Duty cycle = 1.8/12 V = 0.15

R_{ON (N2)}= 5.4 mΩ

P_{DR (LOSS)}

V_DD

=

[

V_DR

×

(

f_SWC_upperFETV_DR

I_BIAS

+

I_BIAS

)

]

+

t_BODY(LOSS)= 20 ns (body conduction time)

[

×

(

f_SWC_lowerFETV_DD

+

)

]

V_F= 0.84 V (MOSFET forward voltage)

= (5.12 × (300 × 10³× 3.3 × 10⁻⁹× 5.12 + 0.002)) +

(5.5 × (300 × 10³×3.3 ×10⁻⁹×5.5 + 0.002))

= 77.13 mW

C_IN= 3.3 nF (MOSFET gate input capacitance)

Q

_{N1, N2}= 17 nC (total MOSFET gate charge)

P

_COUT= (I_RMS)²× ESR = (1.5 A)²× 1.4 mΩ = 3.15 mW

R_GATE= 1.5 Ω (MOSFET gate input resistance)

= 0.003 × (15 A)²= 675 mW

2

× I_L²_OAD

P_{DCR (LOSS)}= DCR× I_LOAD

P_{N1, N2(CL)}

=

[

D × R_N1(ON)

+

(

1− D

)

× R_N2(ON)

]

= (0.15 × 0.0054 + 0.85 × 0.0054) × (15 A)²

= 1.215 W

P

_CIN= (I_RMS)²× ESR = (7.5 A)²× 1 mΩ = 56.25 mW

P

_LOSS= P_{N1, N2}+ P_{BODY (LOSS)}+ P_SW+ P_DCR+ P_DR+ P_COUT+ P_CIN

t_BODY(LOSS)

= 1.215 W + 151.2 mW + 534.6 mW + 77.13 mW +

3.15 mW + 675 mW + 56.25 mW

= 2.62 W

P_BODY(LOSS)

=

× I_LOAD×V_F×2

t_SW

= 20 ns × 300 × 10³× 15 A × 0.84 × 2

= 151.2 mW

Rev. B | Page 29 of 40

ADP1872/ADP1873

Data Sheet

EXTERNAL COMPONENT RECOMMENDATIONS

The configurations listed in Table 8 are with f_CROSS= 1/12 × f_SW, f_ZERO= ¼ × f_CROSS, R_RES= 100 kΩ, R_BOT= 15 kΩ, R_ON= 5.4 mΩ (BSC042N03MS G),

V

_DD= 5 V, and a maximum load current of 14 A.

The ADP1873 models listed in Table 8 are the PSM versions of the device.

Table 8. External Component Values

Marking Code

V_OUTVIN

L¹

(µH) (kΩ) (pF)

R_C

C_COMPC_PAR

R_TOP

SAP Model

ADP1872

LDT

LDU

LDV

ADP1873

LDF

LDK

LDL

(V)

0.8

1.2

1.8

2.5

3.3

5

(V)

13

C_IN(µF)

5 × 22²

4 × 22²

5 × 22²

4 × 22²

C_OUT(µF)

5 × 560³

4 × 560³

4 × 270⁴

3 × 270⁴

2 × 330⁵

330⁵

22²+ (4 × 47⁶)

4 × 560³

4 × 270⁴

2 × 330⁵

2 × 150⁷

22²+ 4 × 47⁶

4 × 560³

4 × 270⁴

3 × 270⁴

3 × 180⁸

5 × 270⁴

3 × 330⁵

3 × 270⁴

2 × 270⁴

150⁷

4 × 270⁴

2 × 330⁵

3 × 270⁴

330⁵

4 × 47⁶

3 × 47⁶

4 × 270⁴

2 × 330⁵

3 × 180⁸

270⁴

3 × 330⁵

3 × 270⁴

270⁴

(pF) (kΩ)

ADP1872ARMZ-0.3-R7/

ADP1873ARMZ-0.3-R7

0.72

1.0

47

34

47

34

47

34

47

34

47

34

47

740

571

800

740

592

829

339

326

271

407

307

430

362

326

296

415

380

223

163

233

210

268

326

261

233

217

74

57

80

74

59

83

34

33

27

41

31

43

36

33

30

41

38

22

16

23

21

27

33

26

23

22

5.0

15.0

30.0

47.5

67.5

110.0

160.0

15.0

30.0

47.5

67.5

110.0

160.0

5.0

15.0

30.0

47.5

15.0

30.0

47.5

67.5

110.0

15.0

30.0

47.5

67.5

110.0

160.0

5.0

15.0

30.0

47.5

15.0

30.0

47.5

67.5

110.0

15.0

30.0

47.5

67.5

1.0

1.53

2.0

3.27

3.44

1.0

7

1.2

1.8

2.5

3.3

5

16.5 4 × 22²

16.5 3 × 22²

1.0

1.67

2.00

3.84

4.44

0.22

0.47

0.90

1.00

1.76

0.47

0.72

0.90

1.0

7

ADP1872ARMZ-0.6-R7/

ADP1873ARMZ-0.6-R7

0.8

1.2

1.8

2.5

1.2

1.8

2.5

3.3

5

1.2

1.8

2.5

3.3

5

5.5

13

5 × 22²

3 × 22²

5 × 10⁹

16.5 3 × 10⁹

16.5 4 × 10⁹

2.0

7

ADP1872ARMZ-1.0-R7/

ADP1873ARMZ-1.0-R7

0.8

1.2

1.8

2.5

1.2

1.8

2.5

3.3

5

1.2

1.8

2.5

3.3

5.5

13

5 × 22²

3 × 22²

3 × 10⁹

4 × 10⁹

5 × 10⁹

4 × 10⁹

0.22

0.47

0.72

1.0

270⁴

3 × 47⁶

4 × 270⁴

3 × 270⁴

3 × 180⁸

270⁴

16.5 3 × 10⁹

16.5 4 × 10⁹

0.47

0.72

Rev. B | Page 30 of 40

Data Sheet

ADP1872/ADP1873

Marking Code

ADP1872 ADP1873

V_OUTVIN

L¹

(µH) (kΩ) (pF)

R_C

C_COMPC_PAR

R_TOP

SAP Model

(V)

C_IN(µF)

C_OUT(µF)

3 × 47⁶

22²+ 47⁶

(pF) (kΩ)

LDV

LDL

5

7

16.5 3 × 10⁹

1.0

34

268

228

27

23

110.0

160.0

¹See the Inductor Selection section (See Table 9).

²22 µF Murata 25 V, X7R, 1210 GRM32ER71E226KE15L (3.2 mm × 2.5 mm × 2.5 mm).

³560 µF Panasonic (SP-series) 2 V, 7 mΩ, 3.7 A EEFUE0D561LR (4.3 mm × 7.3 mm × 4.2 mm).

⁴270 µF Panasonic (SP-series) 4 V, 7 mΩ, 3.7 A EEFUE0G271LR (4.3 mm × 7.3 mm × 4.2 mm).

⁵330 µF Panasonic (SP-series) 4 V, 12 mΩ, 3.3 A EEFUE0G331R (4.3 mm × 7.3 mm × 4.2 mm).

⁶47 µF Murata 16 V, X5R, 1210 GRM32ER61C476KE15L (3.2 mm × 2.5 mm × 2.5 mm).

⁷150 µF Panasonic (SP-series) 6.3 V, 10 mΩ, 3.5 A EEFUE0J151XR (4.3 mm × 7.3 mm × 4.2 mm).

⁸180 µF Panasonic (SP-series) 4 V, 10 mΩ, 3.5 A EEFUE0G181XR (4.3 mm × 7.3 mm × 4.2 mm).

⁹10 µF TDK 25 V, X7R, 1210 C3225X7R1E106M.

Table 9. Recommended Inductors

L (µH)

0.12

0.22

0.47

0.72

0.9

1.2

1.0

1.4

2.0

DCR (mΩ)

0.33

0.8

1.65

1.6

1.8

3.3

3.2

2.6

I_SAT(A)

55

30

50

35

28

25

20

24

Dimension (mm)

10.2 × 7

14.2 × 12.8

10.5 × 10.2

13 × 12.8

10.5 × 10.2

14 × 12.8

Manufacturer

Model Number

744303012

744303022

744355147

744325072

744355090

744325120

7443552100

744318180

7443551200

CEP125U-0R8

Würth Elektronik

Würth Elektronic

Sumida

22

27.5

13.2 × 12.8

0.8

Table 10. Recommended MOSFETs

R_ON

(mΩ)

I_D

(A)

V_DS

(V)

C_IN

(nF)

Q_TOTAL

(nC)

V_GS= 4.5 V

Package

Manufacturer

Model Number

Upper-Side MOSFET

(Q1/Q2)

5.4

47

30

3.2

20

PG-TDSON8

Infineon

BSC042N03MS G

10.2

6.0

9

53

19

14

47

30

1.6

10

35

25

20

PG-TDSON8

SO-8

Infineon

Vishay

International Rectifier

Infineon

BSC080N03MS G

Si4842DY

IRF7811

2.4

3.2

Lower-Side MOSFET

(Q3/Q4)

5.4

PG-TDSON8

BSC042N03MS G

10.2

6.0

82

19

30

1.6

10

35

PG-TDSON8

SO-8

Infineon

Vishay

BSC080N03MS G

Si4842DY

Rev. B | Page 31 of 40

ADP1872/ADP1873

Data Sheet

LAYOUT CONSIDERATIONS

Figure 82 shows the schematic of a typical ADP1872/ADP1873

used for a high power application. Blue traces denote high current

pathways. VIN, PGND, and V_OUTtraces should be wide and

possibly replicated, descending down into the multiple layers.

Vias should populate, mainly around the positive and negative

terminals of the input and output capacitors, alongside the source

of Q1/Q2, the drain of Q3/Q4, and the inductor.

The performance of a dc-to-dc converter depends highly on

how the voltage and current paths are configured on the printed

circuit board (PCB). Optimizing the placement of sensitive

analog and power components are essential to minimize output

ripple, maintain tight regulation specifications, and reduce

PWM jitter and electromagnetic interference.

LOW VOLTAGE INPUT

HIGH VOLTAGE INPUT

V

= 5.0V

VIN = 12V

DD

JP1

C3

C4

C5

C6

C7

C

571pF

ADP1872/

ADP1873

22µF

C12

100nF

C

R

F

C

1

2

3

10

9

Q1

Q3

Q2

Q4

VIN

BST

57pF

47kΩ

COMP/EN

FB

SW

1.0µH

V

= 1.8V, 15A

OUT

R1 30kΩ

V

8

DRVH

OUT

+

C20

270µF

C21

270µF

C22

270µF

C23

270µF

R6

2Ω

R2

15kΩ

4

5

7

6

GND

VDD

PGND

DRVL

C13

1.5nF

C2

0.1µF

C1

1µF

MURATA: (HIGH VOLTAGE INPUT CAPACITORS)

22µF, 25V, X7R, 1210 GRM32ER71E226KE15 L

PANASONIC: (OUTPUT CAPACITORS)

270µF (SP-SERIES) 4V, 7mΩ EEFUE0G271LR

R5

100kΩ

INFINEON MOSFETs:

BSC042N03MS G (LOWER-SIDE)

BSC080N03MS G (UPPER-SIDE)

WURTH INDUCTORS:

1µH, 3.3mΩ, 20A 7443552100

Figure 82. ADP1872/ADP1873 High Current Evaluation Board Schematic (Blue Traces Indicate High Current Paths)

Rev. B | Page 32 of 40

Data Sheet

ADP1872/ADP1873

SENSITIVE ANALOG

COMPONENTS

LOCATED FAR

FROM THE NOISY

POWER SECTION.

SW

SEPARATE ANALOG GROUND

PLANE FOR THE ANALOG

COMPONENTS (THAT IS,

COMPENSATION AND

FEEDBACK RESISTORS).

OUTPUT CAPACITORS

ARE MOUNTED ON THE

RIGHTMOST AREA OF

THE EVB, WRAPPING

BACK AROUND TO THE

MAIN POWER GROUND

PLANE, WHERE IT MEETS

WITH THE NEGATIVE

TERMINALS OF THE

BYPASS POWER CAPACITOR (C1)

FOR VREG BIAS DECOUPLING

AND HIGH FREQUENCY

CAPACITOR (C2) AS CLOSE AS

POSSIBLE TO THE IC.

INPUT CAPACITORS

ARE MOUNTED CLOSE

TO DRAIN OF Q1/Q2

AND SOURCE OF Q3/Q4.

Figure 83. Overall Layout of the ADP1872 High Current Evaluation Board

Rev. B | Page 33 of 40

ADP1872/ADP1873

Data Sheet

Figure 84. Layer 2 of Evaluation Board

Rev. B | Page 34 of 40

Data Sheet

ADP1872/ADP1873

TOP RESISTOR

FEEDBACK TAP

VOUT SENSE TAP LINE EXTENDING BACK

TO THE TOP RESISTOR IN THE FEEDBACK

DIVIDER NETWORK (SEE FIGURE 82). THIS

OVERLAPS WITH PGND SENSE TAP LINE

EXTENDING BACK TO THE ANALOG

PLANE (SEE FIGURE 86, LAYER 4 FOR

PGND TAP).

Figure 85. Layer 3 of Evaluation Board

Rev. B | Page 35 of 40

ADP1872/ADP1873

Data Sheet

BOTTOM RESISTOR

TAP TO THE ANALOG

GROUND PLANE

PGND SENSE TAP FROM

NEGATIVE TERMINALS OF

OUTPUT BULK CAPACITORS.

THIS TRACK PLACEMENT

SHOULD BE DIRECTLY

BELOW THE VOUT SENSE

LINE FROM FIGURE 84.

Figure 86. Layer 4 (Bottom Layer) of Evaluation Board

Rev. B | Page 36 of 40

Data Sheet

ADP1872/ADP1873

IC SECTION (LEFT SIDE OF EVALUATION BOARD)

A dedicated plane for the analog ground plane (GND) should

be separate from the main power ground plane (PGND). With

the shortest path possible, connect the analog ground plane to

the GND pin (Pin 4). This plane should only be on the top layer

of the evaluation board. To avoid crosstalk interference, there

should not be any other voltage or current pathway directly

below this plane on Layer 2, Layer 3, or Layer 4. Connect the

negative terminals of all sensitive analog components to the

analog ground plane. Examples of such sensitive analog com-

ponents include the resistor divider’s bottom resistor, the high

frequency bypass capacitor for biasing (0.1 µF), and the

compensation network.

SW

VOUT

Mount a 1 µF bypass capacitor directly across the VDD pin

(Pin 5) and the PGND pin (Pin 7). In addition, a 0.1 µF should

be tied across the VDD pin (Pin 5) and the GND pin (Pin 4).

VIN

PGND

Figure 87. Primary Current Pathways During the On State of the Upper-Side

MOSFET (Left Arrow) and the On State of the Lower-Side MOSFET (Right Arrow)

POWER SECTION

DIFFERENTIAL SENSING

As shown in Figure 83, an appropriate configuration to localize

large current transfer from the high voltage input (VIN) to the

output (VOUT) and then back to the power ground is to put the

VIN plane on the left, the output plane on the right, and the main

power ground plane in between the two. Current transfers from

the input capacitors to the output capacitors, through Q1/Q2,

during the on state (see Figure 87). The direction of this current

(yellow arrow) is maintained as Q1/Q2 turns off and Q3/Q4

turns on. When Q3/Q4 turns on, the current direction continues to

be maintained (red arrow) as it circles from the bulk capacitor’s

power ground terminal to the output capacitors, through the

Q3/Q4. Arranging the power planes in this manner minimizes

the area in which changes in flux occur if the current through

Q1/Q2 stops abruptly. Sudden changes in flux, usually at source

terminals of Q1/Q2 and drain terminals of Q3/Q4, cause large

dV/dts at the SW node.

Because the ADP1872/ADP1873 operate in valley current-

mode control, a differential voltage reading is taken across the

drain and source of the lower-side MOSFET. The drain of the

lower-side MOSFET should be connected as close as possible to

the SW pin (Pin 9) of the IC. Likewise, the source should be

connected as close as possible to the PGND pin (Pin 7) of the

IC. When possible, both of these track lines should be narrow

and away from any other active device or voltage/current paths.

SW

PGND

The SW node is near the top of the evaluation board. The SW

node should use the least amount of area possible and be away

from any sensitive analog circuitry and components because

this is where most sudden changes in flux density occur. When

possible, replicate this pad onto Layer 2 and Layer 3 for thermal

relief and eliminate any other voltage and current pathways directly

beneath the SW node plane. Populate the SW node plane with

vias, mainly around the exposed pad of the inductor terminal

and around the perimeter of the source of Q1/Q2 and the drain

of Q3/Q4. The output voltage power plane (VOUT) is at the right-

most end of the evaluation board. This plane should be replicated,

descending down to multiple layers with vias surrounding the

inductor terminal and the positive terminals of the output bulk

capacitors. Ensure that the negative terminals of the output

capacitors are placed close to the main power ground (PGND),

as previously mentioned. All of these points form a tight circle

(component geometry permitting) that minimizes the area of

flux change as the event switches between D and 1 − D.

LAYER 1: SENSE LINE FOR SW

(DRAIN OF LOWER MOSFET)

LAYER 1: SENSE LINE FOR PGND

(SOURCE OF LOWER MOSFET)

Figure 88. Drain/Source Tracking Tapping of the Lower-Side MOSFET for CS

Amp Differential Sensing (Yellow Sense Line on Layer 2)

Differential sensing should also be applied between the

outermost output capacitor to the feedback resistor divider (see

Figure 85 and Figure 86). Connect the positive terminal of the

output capacitor to the top resistor (R_T). Connect the negative

terminal of the output capacitor to the negative terminal of the

bottom resistor, which connects to the analog ground plane as

well. Both of these track lines, as previously mentioned, should

be narrow and away from any other active device or voltage/

current paths.

Rev. B | Page 37 of 40

ADP1872/ADP1873

Data Sheet

TYPICAL APPLICATION CIRCUITS

DUAL-INPUT, 300 kHz HIGH CURRENT APPLICATION CIRCUIT

LOW VOLTAGE INPUT

= 5.0V

HIGH VOLTAGE INPUT

VIN = 12V

V

DD

JP1

C3

C4

C5

C6

C7

C

571pF

ADP1872/

ADP1873

22µF

C12

100nF

C

R

F

C

1

2

3

10

9

Q1

Q3

Q2

Q4

VIN

BST

57pF

47kΩ

COMP/EN

FB

SW

1.0µH

V

= 1.8V, 15A

OUT

R1 30kΩ

V

8

DRVH

OUT

+

C20

270µF

C21

270µF

C22

270µF

C23

270µF

R6

2Ω

R2

15kΩ

4

5

7

6

GND

VDD

PGND

DRVL

C13

1.5nF

C2

0.1µF

C1

1µF

MURATA: (HIGH VOLTAGE INPUT CAPACITORS)

22µF, 25V, X7R, 1210 GRM32ER71E226KE15 L

PANASONIC: (OUTPUT CAPACITORS)

270µF (SP-SERIES) 4V, 7mΩ EEFUE0G271LR

R5

100kΩ

INFINEON MOSFETs:

BSC042N03MS G (LOWER-SIDE)

BSC080N03MS G (UPPER-SIDE)

WURTH INDUCTORS:

1µH, 3.3mΩ, 20A 7443552100

Figure 89. Application Circuit for 12 V Input, 1.8 V Output, 15 A, 300 kHz (Q2/Q4 No Connect).

SINGLE-INPUT, 600 kHz APPLICATION CIRCUIT

HIGH VOLTAGE INPUT

VIN = 5.5V

JP1

C3

C4

C5

C6

C7

C

271pF

ADP1872/

ADP1873

22µF

C12

100nF

C

27pF

R

F

C

1

2

3

10

9

Q1

Q3

Q2

Q4

VIN

BST

47kΩ

COMP/EN

FB

SW

0.47µH

V

= 2.5V, 15A

OUT

R1 47.5kΩ

V

8

DRVH

OUT

+

C20

180µF

C21

180µF

C22

180µF

R6

2Ω

R2

15kΩ

4

5

7

6

GND

VDD

PGND

DRVL

C13

1.5nF

C2

0.1µF

C1

1µF

MURATA: (HIGH VOLTAGE INPUT CAPACITORS)

22µF, 25V, X7R, 1210 GRM32ER71E226KE15 L

PANASONIC: (OUTPUT CAPACITORS)

180µF (SP-SERIES) 4V, 10mΩ EEFUE0G181XR

R5

100kΩ

INFINEON MOSFETs:

BSC042N03MS G (LOWER-SIDE)

BSC080N03MS G (UPPER-SIDE)

WURTH INDUCTORS:

0.47µH, 0.8mΩ, 50A 744355147

Figure 90. Application Circuit for 5.5 V Input, 2.5 V Output, 15 A, 600 kHz (Q2/Q4 No Connect)

Rev. B | Page 38 of 40

Data Sheet

ADP1872/ADP1873

DUAL-INPUT, 300 kHz HIGH CURRENT APPLICATION CIRCUIT

LOW VOLTAGE INPUT

= 5V

HIGH VOLTAGE INPUT

VIN = 13V

V

DD

JP1

C3

C4

C5

C6

C7

C

800pF

R

C

ADP1872/

ADP1873

22µF

C12

100nF

C

F

C

1

2

3

10

9

Q1

Q3

Q2

Q4

VIN

BST

80pF

33.5kΩ

COMP/EN

FB

SW

0.8µH

V

= 1.8V, 20A

OUT

R1 30kΩ

V

8

DRVH

OUT

+

C20

270µF

C21

270µF

C22

270µF

C23

270µF

R6

2Ω

R2

15kΩ

4

5

7

6

GND

VDD

PGND

DRVL

C13

1.5nF

C2

0.1µF

C1

1µF

MURATA: (HIGH VOLTAGE INPUT CAPACITORS)

22µF, 25V, X7R, 1210 GRM32ER71E226KE15 L

PANASONIC: (OUTPUT CAPACITORS)

270µF (SP-SERIES) 4V, 7mΩ EEFUE0G271LR

INFINEON MOSFETs:

BSC042N03MS G (LOWER-SIDE)

BSC080N03MS G (UPPER-SIDE)

WURTH INDUCTORS:

0.72µH, 1.65mΩ, 35A 744325072

Figure 91. Application Circuit for 13 V Input, 1.8 V Output, 20 A, 300 kHz (Q2/Q4 No Connect)

Rev. B | Page 39 of 40

ADP1872/ADP1873

Data Sheet

OUTLINE DIMENSIONS

3.10

3.00

2.90

10

1

6

5

5.15

4.90

4.65

3.10

3.00

2.90

PIN 1

IDENTIFIER

0.50 BSC

0.95

0.85

0.75

15° MAX

1.10 MAX

0.70

0.55

0.40

0.15

0.05

0.23

0.13

6°

0°

0.30

0.15

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-BA

Figure 92. 10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Package Option

Branding

LDT

LDU

ADP1872ARMZ-0.3-R7

ADP1872ARMZ-0.6-R7

ADP1872ARMZ-1.0-R7

ADP1872-0.3-EVALZ

ADP1872-0.6-EVALZ

ADP1872-1.0-EVALZ

ADP1873ARMZ-0.3-R7

ADP1873ARMZ-0.6-R7

ADP1873ARMZ-1.0-R7

ADP1873-0.3-EVALZ

ADP1873-0.6-EVALZ

ADP1873-1.0-EVALZ

−40°C to +125°C

10-Lead Mini Small Outline Package [MSOP]

Forced PWM, 300 kHz Evaluation Board

Forced PWM, 600 kHz Evaluation Board

Forced PWM, 1 MHz Evaluation Board

RM-10

LDV

−40°C to +125°C

10-Lead Mini Small Outline Package [MSOP]

Power Saving Mode, 300 kHz Evaluation Board

Power Saving Mode, 600 kHz Evaluation Board

Power Saving Mode, 1 MHz Evaluation Board

RM-10

LDF

LDK

LDL

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D08297-0-7/12(B)

Rev. B | Page 40 of 40


型号：	ADP1873ARMZ-0.3-R7
厂家：	ADI
描述：	Synchronous Current-Mode Buck Controller with Constant On-time, 0.6 V Reference Voltage, and Power Saving Mode 开关光电二极管输出元件
文件：	总40页 (文件大小：1708K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADP1873ARMZ-0.3-R7 [ADI]

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