ADP2165ACPZ-3.3-R7_技术文档

5.5 V, 5 A/6 A, High Efficiency, Step-Down

DC-to-DC Regulators with Output Tracking

Data Sheet

ADP2165/ADP2166

FEATURES

TYPICAL APPLICATION CIRCUIT

Continuous output current

ADP2165: 5 A

ADP2166: 6 A

Integrated MOSFET

ADP2165/

ADP2166

PVIN

AVIN

EN

BST

SW

V

PVIN

C

BST

L1

R

C

IN

V

OUT

C

OUT

PGOOD

SYNC

RT

High-side on resistance: 19 mΩ

Low-side on resistance: 15 mΩ

Reference voltage: 0.6 V 1% over temperature range

Input voltage range: 2.7 V to 5.5 V

Current mode architecture

TOP

R

RT

FB

COMP

TRK

C

VREG

C

R

CP

C

R

BOT

VREG

SS

C

GND PGND

C

SS

Switching frequency

Fixed frequency: 620 kHz or 1.2 MHz

Adjustable frequency: 250 kHz to 1.4 MHz

Synchronizes to external clock: 250 kHz to 1.4 MHz

Selectable synchronize phase shift: in phase or out of phase

External compensation

Figure 1.

The ADP2165/ADP2166 are designed to be extremely flexible

with the addition of a minimal amount of external components

to program soft start and control loop compensation.

Programmable soft start

The ADP2165/ADP2166 are supplied from an input voltage of

2.7 V to 5.5 V. Output voltage options include 3.3 V, 2.5 V, 1.8 V,

1.5 V, 1.2 V, or 1.0 V fixed outputs and adjustable options capable

of supporting an output voltage range from 0.6 V to 90% of the

input voltage. Protection features include undervoltage lockout

(UVLO), overvoltage protection (OVP), overcurrent protection

(OCP), and thermal shutdown (TSD) for robust performance.

Startup into a precharged output

Voltage tracking input

Power-good output and precision enable input

Accurate current limit

Available in 24-lead, 4 mm × 4 mm LFCSP package

Supported by ADIsimPower™ design tool

APPLICATIONS

The ADP2165/ADP2166 operate over the −40°C to +125°C

junction temperature range and are available in a 24-lead

LFCSP package.

Point of load regulation

Communications and networking

High end consumer

Industrial, instrumentation, and healthcare

100

V

= 3.3V

PVIN

GENERAL DESCRIPTION

95

90

85

80

75

70

65

60

55

50

The ADP2165/ADP2166 are high efficiency, current mode

control, step-down dc-to-dc regulators with an integrated 19 mΩ

high-side FET and a 15 mΩ synchronous rectified FET. The

ADP2165/ADP2166 combine a small size, 4 mm × 4 mm LFCSP

package with an accurate current limit, resulting in a smaller

inductor size and a high power density, point of load solution.

V

= 5V

PVIN

Key features include precision enable, power-good monitor,

and output voltage tracking to facilitate robust sequencing.

The switching frequency can be programmed from 250 kHz

to 1.4 MHz, or it can be fixed at 620 kHz or 1.2 MHz. The

synchronization function allows the switching frequency to

synchronize to an external clock, minimizing the

V

= 1.8V

OUT

f_SW= 600kHz

0

1

2

3

4

5 6

OUTPUT CURRENT (A)

Figure 2. Efficiency vs. Output Current

electromagnetic interference (EMI) of the system.

Rev. B

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

ADP2165/ADP2166

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Undervoltage Lockout ............................................................... 13

Thermal Shutdown .................................................................... 13

Applications Information .............................................................. 14

ADIsimPower Design Tool ....................................................... 14

Input Capacitor Selection.......................................................... 14

Output Voltage Setting .............................................................. 14

Voltage Conversion Limitations............................................... 14

Inductor Selection...................................................................... 15

Output Capacitor Selection....................................................... 15

Compensation Design ............................................................... 16

Design Example.............................................................................. 17

Output Voltage Setting .............................................................. 17

Frequency Setting....................................................................... 17

Inductor Selection...................................................................... 17

Output Capacitor Selection....................................................... 18

Compensation Components..................................................... 18

Soft Start Time Program ........................................................... 18

Input Capacitor Selection.......................................................... 18

Recommended External Components .................................... 19

Printed Circuit Board Layout Recommendations ..................... 20

Reference Designs .......................................................................... 21

Outline Dimensions....................................................................... 23

Ordering Guide .......................................................................... 23

Applications....................................................................................... 1

General Description......................................................................... 1

Typical Application Circuit ............................................................. 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications..................................................................................... 4

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Theory of Operation ...................................................................... 12

Control Scheme .......................................................................... 12

PWM Mode................................................................................. 12

Enable/Shutdown ....................................................................... 12

Internal Regulator (VREG)....................................................... 12

Bootstrap Circuitry .................................................................... 12

Oscillator and Synchronization................................................ 12

Soft Start ...................................................................................... 13

Tracking ....................................................................................... 13

Power-Good (PGOOD)............................................................. 13

Peak Current-Limit and Short-Circuit Protection................. 13

Overvoltage Protection.............................................................. 13

REVISION HISTORY

8/2017—Rev. A to Rev. B

Changed LFCSP_WQ to LFCSP ..........................................Throughout

Updated Outline Dimensions .................................................................23

Changes to Ordering Guide.....................................................................23

9/2016—Rev. 0 to Rev. A

Change to Compensation Components Section ........................ 18

Change to Table 8 ........................................................................... 19

8/2014—Revision 0: Initial Version

Rev. B | Page 2 of 23

Data Sheet

ADP2165/ADP2166

FUNCTIONAL BLOCK DIAGRAM

EN

EN_BUF

UVLO

PVIN

1.2V

A

CS

+

HICCUP

MODE

OCP

–

I

SLOPE RAMP

MAX

V

Σ

PVIN

BST

COMP

0.6V

NFET1

+

–

I

SS

+

CMP

–

DRIVER

SS

TRK

FB

AMP

SW

CLK

OVP

CONTROL

LOGIC

0.7V

V

–

+

PVIN

NFET2

DRIVER

0.66V

–

+

PGND

–

+

NEG CURRENT

CMP

+

–

0.54V

I

NEG

PGOOD

AVIN

VREG

GND

DEGLITCH

OSC

EN_BUF

3.3V

REGULATOR

CLK

SYNC

RT

SLOPE RAMP

Figure 3. ADP2165/ADP2166 Functional Block Diagram

Rev. B | Page 3 of 23

ADP2165/ADP2166

SPECIFICATIONS

Data Sheet

V_PVIN= V_AVIN= 5 V, T_J= −40°C to +125°C for minimum/maximum specifications, and T_A= 25°C for typical specifications, unless otherwise

noted.

Table 1.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

PVIN AND AVIN

V_PVINVoltage Range

V_AVINVoltage Range

Quiescent Current

Shutdown Current

V_AVINUndervoltage Lockout Threshold

V_PVIN

V_AVIN

I_Q

I_SHDN

UVLO

2.7

5.5

10

150

2.7

V

mA

µA

V

No switching, f_SW= 600 kHz

EN = 0 V

V_AVINrising

2

25

2.6

2.5

V_AVINfalling

2.35

V

FB

FB Regulation Voltage

Fixed Output Version

FB Bias Current

V_FB

V_OUT

I_FB

V_PVIN= 2.7 V to 5.5 V

0.594

−1

0.6

0.606

+1

0.1

V

%

µA

0.01

ERROR AMPLIFIER (EA)

Transconductance

EA Source Current

EA Sink Current

g_m

I_SOURCE

I_SINK

430

3.1

500

75

85

570

3.5

µS

µA

INTERNAL REGULATOR (VREG)

VREG Voltage

3.3

140

50

V

mV

mA

Dropout Voltage

Regulator Current Limit

SW

I_VREG= 10 mA

High-Side On Resistance¹

V_BST− V_SW= 5 V

V_BST− V_SW= 3.3 V

V_PVIN= 5 V

V_PVIN= 3.3 V

ADP2165

19

22

15

16

8

29

34

23

26

9.5

10.5

mΩ

A

Low-Side On Resistance¹

High-Side Peak Current Limit

6.5

7.5

ADP2166

9

A

Low-Side Negative Current Limit

SW Minimum Off Time²

SW Minimum On Time²

OSCILLATOR (RT)

2.4

100

A

ns

t_{OFF_MIN}

t_{ON_MIN}

Switching Frequency

f_SW

RT pin floating

RT pin connected to VREG

R_RT= 95.3 kΩ

525

1.08

500

250

620

1.2

590

715

1.32

680

kHz

MHz

kHz

Switching Frequency Range

SYNC

1400

Synchronization Range

SYNC Minimum Pulse Width

SYNC Minimum Off Time

SYNC Input High Voltage

SYNC Input Low Voltage

SOFT START (SS)

250

100

1.3

1400

kHz

ns

V

0.4

4.3

V

SS Pull-Up Current

I_SS

2.7

3.5

µA

TRK

TRK Input Voltage Range

TRK-to-FB Offset Voltage

TRK Input Bias Current

0

−9

600

+9

100

mV

nA

TRK = 300 mV to 500 mV

Rev. B | Page 4 of 23

Data Sheet

ADP2165/ADP2166

Parameter

Symbol

Test Conditions/Comments

Min

107

87

Typ

Max

Unit

PGOOD

Power-Good Range

FB rising threshold

FB rising hysteresis

FB falling threshold

FB falling hysteresis

From FB to PGOOD

V_PGOOD= 5 V

111

3

90.5

3

16

0.1

27

115

%

94.5

Power-Good Deglitch Time

PGOOD Leakage Current

PGOOD Output Low Voltage

EN

Clock cycles

µA

mV

1

45

I_PGOOD= 1 mA

EN Threshold

EN Hysteresis

EN Pull-Down Resistor

THERMAL

1.12

1.2

100

1

1.28

V

mV

MΩ

Thermal Shutdown Threshold

Thermal Shutdown Hysteresis

150

25

°C

¹Pin-to-pin measurement.

²Guaranteed by design.

Rev. B | Page 5 of 23

ADP2165/ADP2166

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 2.

THERMAL RESISTANCE

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board (4-layer, JEDEC standard board) for

surface-mount packages.

Parameter

Rating

PVIN, AVIN, EN, PGOOD, FB

SW

−0.3 V to +6 V

−1 V to +6 V

BST

SW + 6 V

Table 3. Thermal Resistance

Package Type

24-Lead LFCSP

SS, COMP, TRK, VREG, SYNC, RT

PGND to GND

Operating Junction Temperature Range

Storage Temperature Range

Soldering Conditions

−0.3 V to +6 V

−0.3 V to +0.3 V

−40°C to +125°C

−65°C to +150°C

JEDEC J-STD-020

θ_JA

Unit

38.3

°C/W

ESD CAUTION

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Rev. B | Page 6 of 23

Data Sheet

ADP2165/ADP2166

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

18

17

16

15

14

13

SYNC

RT

PVIN

SW

ADP2165/

ADP2166

SW

TRK

SS

TOP VIEW

SW

4

5

6

(Not to Scale)

COMP

FB

SW

PGND

NOTES

1. EXPOSED PAD. SOLDER THE EXPOSED

PAD TO AN EXTERNAL GROUND PLANE

UNDERNEATH THE IC FOR THERMAL

DISSIPATION.

Figure 4. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1

2

3

SYNC

Synchronization Input. Connect this pin to an external clock between 250 kHz and 1.4 MHz to synchronize the

switching frequency to the external clock. RT can be used to program the phase shift when synchronizing the

external clock.

Frequency Setting. Connect a resistor between the RT and GND pins to program the switching frequency between

250 kHz to 1.4 MHz. When the RT pin is floating, the frequency is set to 620 kHz, and when the RT pin is connected

to VREG, the frequency is set to 1.2 MHz.

RT

TRK

Tracking Input. This pin can be used for tracking and sequencing. If the tracking function is not used, connect TRK

to VREG.

4

5

6

7

8

9

SS

COMP

FB

GND

PGOOD

BST

Soft Start Control. Connect a capacitor from the SS pin to the GND pin to program the soft start time.

Error Amplifier Output. Connect a compensation network from the COMP pin to the GND pin.

Feedback Voltage Sense Input. Connect to a resistor divider from V_OUT

.

Analog Ground. Connect to the ground plane.

Power-Good Output (Open-Drain). A pull-up resistor of 100 kΩ is recommended.

Supply Rail for the High-Side MOSFET Gate Drive. Place a 0.1 µF capacitor between the SW pin and the BST pin.

Power Ground. Connect this pin to the ground plane and to the output return side of the output capacitor.

10, 11,

12, 13

PGND

14, 15,

16, 17

SW

Switching Node.

18, 19,

20, 21

PVIN

AVIN

EN

Power Input. Connect this pin to the input power source and connect a bypass capacitor between this pin and

ground.

Bias Voltage Input Pin. Connect a bypass capacitor between this pin and GND and a small (10 Ω) resistor between

this pin and PVIN.

Precision Enable Input Pin. An external resistor divider can be used to set the turn-on threshold. To enable the

device automatically, connect the EN pin to PVIN. This pin has a 1 MΩ pull-down resistor to GND.

Internal Bias Regulator Output. It supplies the regulated voltage to the internal circuitry. Bypass the VREG pin to

the GND pin with a high quality, low ESR 1 µF ceramic capacitor.

22

23

24

VREG

EPAD

Exposed Pad. Solder the exposed pad to an external ground plane underneath the IC for thermal dissipation.

Rev. B | Page 7 of 23

ADP2165/ADP2166

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

T_A= 25°C, V_PVIN= V_AVIN= 5 V, V_OUT= 1.2 V, L = 1 µH, C_IN= 47 µF, C_OUT= 100 µF, f_SW= 600 kHz, unless otherwise noted.

100

95

90

85

80

75

70

65

60

55

50

100

95

90

85

80

75

70

65

60

55

50

V

= 2.5V

V

= 3.3V

V

= 2.5V

OUT

V

= 1.8V

OUT

V

= 1.8V

V

OUT

V

= 1.5V

OUT

V

= 1.2V

V

= 1.2V

OUT

V = 1.0V

OUT

V

= 1.0V

OUT

INDUCTOR: WÜRTH ELEKTRONIK 744311100

0

1

2

3

4

5

6

0

1

2

3

4

5

6

OUTPUT CURRENT (A)

Figure 5. Efficiency (f_SW= 600 kHz, V_PVIN= 3.3 V) vs. Output Current

Figure 8. Efficiency (f_SW= 600 kHz, V_PVIN= 5 V) vs. Output Current

100

V

= 3.3V

V

= 2.5V

OUT

V

= 2.5V

OUT

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

V

= 1.8V

V

= 1.5V

OUT

V

= 1.5V

OUT

V

= 1.2V

OUT

V

= 1.2V

V

= 1.8V

OUT

V

= 1.0V

V

= 1.0V

OUT

INDUCTOR: WÜRTH ELEKTRONIK 744314047

0

1

2

3

4

5

6

0

1

2

3

4

5

6

OUTPUT CURRENT (A)

Figure 6. Efficiency (f_SW= 1.2 MHz, V_PVIN= 3.3 V) vs. Output Current

Figure 9. Efficiency (f_SW= 1.2 MHz, V_PVIN= 5 V) vs. Output Current

2.3

2.2

40

35

+125ºC

2.1

+125ºC

30

2.0

+25ºC

1.9

25

–40ºC

+25ºC

1.8

1.7

1.6

1.5

20

–40ºC

15

10

2.7

3.1

3.5

3.9

V

4.3

(V)

4.7

5.1

5.5

2.7

3.1

3.5

3.9

V

4.3

(V)

4.7

5.1

5.5

PVIN

Figure 7. Quiescent Current vs. V_PVIN(No Switching)

Figure 10. Shutdown Current vs. V_PVIN

Rev. B | Page 8 of 23

Data Sheet

ADP2165/ADP2166

40

35

30

25

20

15

10

30

25

20

15

10

5

+125ºC

+25ºC

–40ºC

0

2.7

3.1

3.5

3.9

V

4.3

(V)

4.7

5.1

5.5

2.7

3.1

3.5

3.9

V

4.3

(V)

4.7

5.1

5.5

PVIN

Figure 11. High-Side NFET Resistor vs. V_PVIN(Pin-to-Pin Measurements)

Figure 14. Low-Side NFET Resistor vs. V_PVIN(Pin-to-Pin Measurements)

605

604

603

602

601

600

599

598

597

596

595

610

600

+125ºC

590

+25ºC

580

570

–40ºC

560

550

540

530

–40

0

25

85

125

2.7

3.1

3.5

3.9

V

4.3

(V)

4.7

5.1

5.5

TEMPERATURE (°C)

PVIN

Figure 12. Feedback Voltage vs. Temperature, V_PVIN= 5 V

Figure 15. Switching Frequency vs. V_PVIN(R_RT= 95.3 kΩ)

1300

660

650

640

630

620

610

600

590

580

570

560

1275

1250

1225

1200

1175

1150

1125

1100

+125ºC

+25ºC

–40°C

+25ºC

–40ºC

2.7

3.1

3.5

3.9

4.3

(V)

4.7

5.1

5.5

2.7

3.1

3.5

3.9

V

4.3

(V)

4.7

5.1

5.5

V

PVIN

Figure 13. Switching Frequency vs. V_PVINat 1.2 MHz (RT = VREG)

Figure 16. Switching Frequency vs. V_PVINat 620 kHz (RT Floating)

Rev. B | Page 9 of 23

ADP2165/ADP2166

Data Sheet

9.0

8.8

8.6

8.4

8.2

8.0

7.8

7.6

7.4

7.2

7.0

10.0

9.8

9.6

9.4

9.2

9.0

8.8

8.6

8.4

8.2

8.0

+125ºC

+25ºC

+125ºC

+25ºC

–40ºC

2.7

3.1

3.5

3.9

4.3

(V)

4.7

5.1

5.5

2.7

3.1

3.5

3.9

4.3

(V)

4.7

5.1

5.5

V

PVIN

Figure 17. ADP2165 Peak Current Limit vs. V_PVIN

Figure 20. ADP2166 Peak Current Limit vs. V_PVIN

T

EN

2

V

OUT

1

3

V

OUT

PGOOD

1

PGOOD

3

4

I

L

I

L

4

B

CH1 500mV

CH3 5.00V

CH2 5.00V

M1.00ms

T 10.00%

W

A

CH2

3.80V

W

B

W

CH1 500mV

CH3 5.00V

CH2 5.0V

CH4 2.00A Ω

M1.00ms

10.00%

A

CH2

3.80V

W

B

CH4 5.00A Ω

W

B

W

T

W

Figure 18. Soft Start with Full Load (600 kHz, V_PVIN= 5 V)

Figure 21. Soft Start with Precharge (600 kHz, V_PVIN= 5 V)

T

V

(AC)

V

(AC)

OUT

1

I

OUT

4

B

CH1 50.0mV

M200µs

30.20%

A

CH4

2.80A

CH1 50.0mV

M200µs

20.60%

A

CH4

4.60A

W

B

CH4 2.00A Ω

T

CH4 5.00A Ω

T

W

Figure 22. Load Transient (1.2 MHz, 0.5 A to 5.5 A Load Step)

Figure 19. Load Transient (600 kHz, 1.5 A to 4.5 A Load Step)

Rev. B | Page 10 of 23

Data Sheet

ADP2165/ADP2166

T

1

V

(AC)

OUT

TRK

2

SW

FB

2

3

I

L

4

B

CH1 5.00mV

CH2 5.00V

CH4 5.00A Ω

M1.00µs

40.20%

A

CH2

4.00V

W

CH2 500mV

M2.00ms

20.20%

A

CH3

300mV

T

CH3 500mV

T

Figure 23. Steady Waveform

Figure 26. Tracing Function

T

V

OUT

V

OUT

2

1

4

2

1

4

SW

I

L

I

L

B

CH1 5.00V CH2 500mV

M10.0ms

20.40%

A

CH2

600mV

W

B

W

CH1 5.00V CH2 500mV

M10.0ms

80.40%

A

CH2

600mV

CH4 5.00A Ω

T

CH4 5.00A Ω

T

Figure 24. Output Short

Figure 27. Output Short Recovery

T

SYNC

3

SYNC

SW

2

CH2 2.00V

M400ns

20.40%

A

CH3

400mV

CH2 2.00V

M400ns

20.40%

A

CH3

400mV

CH3 5.00V

T

CH3 5.00V

T

Figure 25. Synchronized to 1 MHz in Phase

Figure 28. Synchronized to 1 MHz 180° Out of Phase

Rev. B | Page 11 of 23

ADP2165/ADP2166

Data Sheet

THEORY OF OPERATION

The ADP2165/ADP2166 are step-down, dc-to-dc regulators.

They use a current mode architecture with an integrated high-side

and low-side switch. They target high performance applications

that require high efficiency and design simplicity.

INTERNAL REGULATOR (VREG)

The internal regulator provides a stable supply for the internal

control circuits. It is recommended to place a 1 μF ceramic

capacitor between the VREG and GND pins. The internal

regulator also includes a current-limit circuit to protect the

circuit if the maximum external load is added.

The ADP2165/ADP2166 can operate with an input voltage from

2.7 V to 5.5 V and regulate the output voltage down to 0.6 V.

Additional features for flexible design include programmable

switching frequency, programmable soft start, external

compensation, and enable and power-good pins. The

ADP2165/ADP2166 are also available with preset output

voltage options of 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, and 1.0 V.

The AVIN pin provides the power supply for the internal regulator.

When device is enabled, the internal regulator is active.

BOOTSTRAP CIRCUITRY

The ADP2165/ADP2166 integrate the boot regulator to provide

the gate drive voltage for the high-side NFET. A capacitor between

the BST and SW pins is charged from the PVIN pin while the

low-side NFET is on.

CONTROL SCHEME

The ADP2165/ADP2166 use a fixed frequency, current mode

PWM control architecture for good line and load transient

performance. In fixed frequency PWM mode, adjust the duty

cycle of the integrated MOSFET to regulate the output voltage

that has a low output ripple voltage.

Placing an X7R or X5R 0.1 μF ceramic capacitor between the

BST and SW pins is recommended.

OSCILLATOR AND SYNCHRONIZATION

The switching frequency of the ADP2165/ADP2166 can be set

by connecting a resistor between the RT pin and the GND pin.

Use the following equation to set the switching frequency:

PWM MODE

At the start of each oscillator cycle, the high-side NFET (N-

channel MOSFET) switch turns on and transmits a positive

voltage across the inductor. Current in the inductor increases

until the current sense signal crosses the peak inductor current

level set by the voltage on the COMP pin. The high-side NFET

then turns off, and the low-side NFET synchronous rectifier

then turns on. This puts a negative voltage across the inductor,

causing the inductor current to decrease. The synchronous

rectifier stays on for the rest of the cycle.

R

_RT(kΩ) = 60,000/[f_SW(kHz) + 10] − 5

A 191 kΩ resistor sets the frequency to 300 kHz, and a 93.1 kΩ

resistor sets frequency to 600 kHz. Figure 29 shows the typical

relationship between R_RTand f_SW.

1600

1400

1200

1000

800

ENABLE/SHUTDOWN

The EN input pin has a precision analog threshold of 1.2 V

(typical) with 100 mV of hysteresis. When the enable voltage

exceeds 1.2 V, the regulator turns on, and when it falls below

1.1 V (typical), the regulator turns off. To force the devices to

automatically start when input power is applied, connect the EN

pin to the PVIN pin.

600

400

When the ADP2165/ADP2166 are shut down, the soft start

capacitor discharges. When the devices are reenabled, a new

soft start cycle begins.

200

20

40

60

80

100

(kΩ)

120

140

160

180

R

RT

If the EN pin is not externally connected, an internal pull-down

resistor (1 MΩ) prevents an accidental enable.

Figure 29. Frequency (f_SW) vs. RT Resistor

To synchronize the ADP2165/ADP2166, drive an external clock

at the SYNC pin. The frequency of the external clock can be in

the 250 kHz to 1.4 MHz range.

During the synchronization, the RT pin can be used to program

the phase shift. When the RT pin is connected to the VREG pin,

the rising edge of the SW pin is 180° out of phase with the external

clock. If the RT pin is floating, the rising edge of the SW pin is in

phase with the external clock.

Rev. B | Page 12 of 23

Data Sheet

ADP2165/ADP2166

SOFT START

PEAK CURRENT-LIMIT AND SHORT-CIRCUIT

PROTECTION

The SS pin is used to program the soft start time. By connecting

a capacitor between the SS and GND pins, the internal current

then charges this capacitor and establishes the soft start ramp-up.

The soft start time can be calculated by the following equation:

The ADP2165/ADP2166 have a peak current-limit protection

circuit to prevent current runaway. When the inductor peak

current reaches the current-limit value, the high-side NFET

turns off, and the low-side NFET turns on until the next cycle,

while the overcurrent counter increments. If the overcurrent

counter count exceeds 10, the device enters hiccup mode, and

the high-side NFET and low-side NFET both turn off. The

devices remain in this mode for seven times the soft start time

and then attempt to restart from the soft start. If the current-

limit fault clears, the devices resume normal operation.

Otherwise, they reenter hiccup mode after counting 10 current-

limit violations.

0.6V ×C_SS

t_SS

=

I_SS

where:

_SSis the soft start capacitance.

_SSis the soft start pull-up current (3.5 µA).

C

I

If the output voltage is precharged prior to startup, the

ADP2165/ADP2166 prevent reverse inductor current that

discharges the output capacitor until the soft start voltage

exceeds the voltage on the FB pin.

OVERVOLTAGE PROTECTION

When the channel is disabled or a current fault happens, the

soft start capacitor discharges.

The ADP2165/ADP2166 provide an overvoltage protection

feature that protects the system from an output short to a higher

voltage supply or from a strong unload transient. If the feedback

voltage increases to 0.7 V, the internal high-side NFET turns off

and the low-side NFET turns on until the current through the

low-side NFET reaches the negative current limit. Thereafter, both

the high-side and low-side NFET are held in the off state until

the voltage at FB decreases to 0.63 V, and the devices resume

normal operation.

TRACKING

The ADP2165/ADP2166 have a tracking input feature, TRK,

that allows the output voltage to track another voltage (master

voltage). It is especially useful in core and I/O voltage tracking for

field programmable gate arrays (FPGAs), digital signal processors

(DSPs), and application specific integrated circuits (ASICs).

The internal error amplifier includes three positive inputs: the

internal reference voltage, the soft start voltage, and the TRK

voltage. The error amplifier regulates the FB voltage to the

lowest of the three voltages. To track a master voltage, tie the

TRK pin to a resistor divider from the master voltage.

UNDERVOLTAGE LOCKOUT

Undervoltage lockout circuitry is integrated in the ADP2165/

ADP2166. If AVIN drops below 2.5 V, the devices turn off.

When the AVIN voltage rises above 2.6 V, the soft start period

initiates, and the devices are enabled.

If the TRK function is not used, connect the TRK pin to the VREG.

THERMAL SHUTDOWN

POWER-GOOD (PGOOD)

In the event that the junction temperatures of the ADP2165/

ADP2166 rise above 150°C, the thermal shutdown circuit turns

the regulator off. Extreme junction temperatures can be the result

of high current operation, poor circuit board design, and/or

high ambient temperature. A 25°C hysteresis is included so that

when thermal shutdown occurs, the ADP2165/ADP2166 do not

return to operation until the on-chip temperature drops below

125°C. When coming out of thermal shutdown, soft start initiates.

The PGOOD pin is an active high, open-drain output that requires

a pull-up resistor. A logic high on the PGOOD pin indicates

that the voltage on the FB pin (and, therefore, the output

voltage) is within 10% of the desired value. In addition, there is a

16-cycle waiting period after the FB pin is detected as being

within the 10% range. A logic low on the PGOOD pin indicates

that the voltage on the FB pin is not within 10% of the desired

value. Similarly, there is a 16-cycle delay to deassert PGOOD.

Rev. B | Page 13 of 23

ADP2165/ADP2166

Data Sheet

APPLICATIONS INFORMATION

ADIsimPOWER DESIGN TOOL

VOLTAGE CONVERSION LIMITATIONS

The ADP2165/ADP2166 are supported by the ADIsimPower

design tool set. ADIsimPower is a collection of tools that produce

complete power designs optimized to a specific design goal. The

tools allow the user to generate a full schematic, bill of materials,

and calculate performance in minutes. ADIsimPower can optimize

designs for cost, area, efficiency, and parts count while taking

into consideration the operating conditions and limitations of

the IC and all real external components. The ADIsimPower tool

can be found at www.analog.com/ADIsimPower, and the user

can request an unpopulated board through the tool.

The minimum output voltage for a given input voltage and

switching frequency is constrained by the minimum on time.

The minimum on time of the ADP2165/ADP2166 is typically

100 ns. The minimum output voltage at a given input voltage

and frequency can be calculated using the following equation:

V

_{OUT_MIN}= V_PVIN× t_{ON_MIN}× f_SW− (R_{DSON_HS}− R_{DSON_LS}) ×

_{OUT_MIN}× t_{ON_MIN}× f_SW− (R_{DSON_LS}+ R_L) × I_{OUT_MIN}

where:

_{OUT_MIN}is the minimum output voltage.

_{ON_MIN}is the minimum on time.

I

(1)

V

t

INPUT CAPACITOR SELECTION

I_{OUT_MIN}is the minimum output current.

f

R

_SWis the switching frequency.

_{DSON_HS}is the high-side MOSFET on resistance.

_{DSON_LS}is the low-side MOSFET on resistance.

The input capacitor reduces the input voltage ripple caused by

the switch current on the PVIN pin. Place the input capacitor as

close as possible to the PVIN pin. A ceramic capacitor in the 10 µF

to 47 µF range is recommended. The loop that is composed of

this input capacitor, the high-side NFET, and the low-side NFET

must be kept as small as possible.

R_Lis the series resistance of the output inductor.

The maximum output voltage for a given input voltage and

switching frequency is constrained by the minimum off time

and the maximum duty cycle. The minimum off time is typically

100 ns, and the maximum duty cycle of the ADP2165/ADP2166

is typically 90%.

The voltage rating of the input capacitor must be greater than the

maximum input voltage. The rms current rating of the input

capacitor must be larger than the value calculated by the

following equation:

The maximum output voltage, limited by the minimum off time

at a given input voltage and frequency, can be calculated using

the following equation:

I_C

= I_OUT× D ×(1− D)

IN_RMS

OUTPUT VOLTAGE SETTING

V

I

_{OUT_MAX}= V_PVIN× (1 − t_{OFF_MIN}× f_SW) − (R_{DSON_HS}− R_{DSON_LS}) ×

_{OUT_MAX}× (1 − t_{OFF_MIN}× f_SW) − (R_{DSON_LS}+ R_L) × I_{OUT_MAX}(2)

where:

_{OUT_MAX}is the maximum output voltage.

_{OFF_MIN}is the minimum off time.

The output voltage of the ADP2165/ADP2166 is set by an

external resistive divider. The resistor values are calculated

using the following equation:

V

t

I













R_TOP

R_BOT

V_OUT= 0.6 ×

1 +

_{OUT_MAX}is the maximum output current.

The maximum output voltage, limited by the maximum duty

cycle at a given input voltage, can be calculated using the

following equation:

To limit the output voltage accuracy degradation due to FB bias

current (0.1 µA maximum) to less than 0.5% (maximum), ensure

that R_BOT< 30 kΩ.

V_{OUT_MAX}= D_MAX× V_PVIN

(3)

Table 5 lists the recommended resistor divider for various output

voltages.

where D_MAXis the maximum duty cycle.

As Equation 1 to Equation 3 show, reducing the switching

frequency alleviates the minimum on time and minimum off

time limitation.

Table 5. Resistor Divider for Various Output Voltages

V_OUT(V)

R_TOP1% (kΩ)

R_BOT1% (kΩ)

1.0

10

15

1.2

10

1.5

15

10

1.8

20

10

2.5

3.3

47.5

10

15

2.21

Rev. B | Page 14 of 23

Data Sheet

ADP2165/ADP2166

Shielded ferrite core materials are recommended for low core

loss and low EMI. Table 6 lists some recommended inductors.

INDUCTOR SELECTION

The inductor value is determined by the operating frequency,

input voltage, output voltage, and inductor ripple current. Using

a small inductor leads to a faster transient response; however, it

degrades efficiency due to a larger inductor ripple current.

Conversely, using a large inductor value leads to a smaller ripple

current and better efficiency; however, it results in a slower

transient response.

Table 6. Recommended Inductors

L

(µH)

I_SAT

(A)

I_RMSDCR

Vendor

Part No.

(A)

21

18

(mΩ)

1.10

1.35

Würth

Elektronik

744311022

744314047

744314076

744311100

0.22

0.47

0.76

1.0

32

20

15

19

14

15.5 2.25

15

11

4.6

6.6

As a guideline, the inductor ripple current, ΔI_L, is typically set

to one-third of the maximum load current. The inductor value

is calculated using the following equation:

744311150

1.5

7443340220

2.2

12.5 16.5 4.4

7443340330

3.3

8.5

30

28

24.3 17

22.3 13

16.4 11

23.5 15

14

21

20

6.5

2.9

4.0

4.75

7.9

9.8

7.6

(V_PVIN−V_OUT)× D

L =

Coilcraft

XAL7020-271ME

XAL7020-331ME

XAL7020-471ME

XAL7020-681ME

XAL7020-102ME

XAL7030-152ME

XAL7030-222ME

0.27

0.33

0.47

0.68

1.0

∆I_L× f_SW

where:

V_PVINis the input voltage.

V

_OUTis the output voltage.

1.5

2.2

ΔI_Lis the inductor ripple current.

_SWis the switching frequency.

D is the duty cycle, D = V_OUT/V_PVIN

18

12.9 13.7

f

.

OUTPUT CAPACITOR SELECTION

The ADP2165/ADP2166 use adaptive slope compensation in

the current loop to prevent subharmonic oscillations when the

duty cycle is larger than 50%. The internal slope compensation

limits the minimum inductor value.

The output capacitor selection affects the output ripple voltage

load step transient and the loop stability of the regulator.

For example, during a load step transient where the load is

suddenly increased, the output capacitor supplies the load until

the control loop can ramp up the inductor current. The delay

caused by the control loop causes the output to undershoot. The

output capacitance that is required to satisfy the voltage droop

requirement can be calculated by using the following equation:

For a duty cycle that is larger than 50%, the minimum inductor

value is determined by using the following equation:

V_OUT×(1− D)

L (Minimum) =

4 × f_SW

The peak inductor current is calculated by using the following

equation:

K_UV× ∆I_STEP²× L

2 ×(V_PVIN−V_OUT)× ∆V_{OUT _UV}

C_{OUT_UV}

=

∆I_L

2

I_PEAK= I_OUT+

where:

_UVis a factor, with a typical setting of K_UV= 2.

K

The saturation current of the inductor must be larger than the peak

inductor current. For ferrite core inductors with a quick saturation

characteristic, the saturation current rating of the inductor must

be higher than the current limit threshold of the switch. This

prevents the inductor from reaching saturation.

ΔI_STEPis the load step.

ΔV_{OUT_UV}is the allowable undershoot on the output voltage.

Another example occurs when a load is suddenly removed from

the output, and the energy stored in the inductor rushes into

the output capacitor, causing the output to overshoot.

The rms current of the inductor is calculated from the following

equation:

The output capacitance that is required to meet the overshoot

requirement can be calculated using the following equation:

2

∆I_L

12

K_OV× ∆I_STEP²× L

2

I_RMS

=

I_OUT

+

C_{OUT_OV}

=

2

(V_OUT+ ∆V_{OUT _OV}) −V_OUT

where:

_OVis a factor, with a typical setting of K_OV= 2.

ΔV_{OUT_OV}is the allowable overshoot on the output voltage.

K

Rev. B | Page 15 of 23

ADP2165/ADP2166

Data Sheet

The ESR and the value of the capacitance determine the output

ripple. Use the following equation to select a capacitor that can

meet the output ripple requirements:

The compensation components, R_Cand C_C, contribute a zero,

and the optional C_CPand R_Ccontribute an optional pole.

The loop gain transfer equation is as follows:

∆I_L

C_{OUT_RIPPLE}

=

T_V(S) =

8× f_SW× ∆V_{OUT _ RIPPLE}

R_BOT

−g_m

×

∆V_{OUT _ RIPPLE}

R_BOT+ R_TOPC_C+ C_CP

R_ESR

where:

=

∆I_L

1 + R_C× C_C× s

R_C× C_C× C_CP

× G_VD(s)

s × (1 +

× s)

ΔV_{OUT_RIPPLE}is the allowable output ripple voltage.

C_C+ C_CP

R

_ESRis the equivalent series resistance of the output capacitor

The following design guideline shows how to select the R_C, C_C,

and C_CPcompensation components for the ceramic output

capacitor applications:

in ohms (Ω).

Select the largest output capacitance given by C_{OUT_UV}, C_{OUT_OV}

and C_{OUT_RIPPLE}to meet both the load transient and the output

ripple performance.

,

1. Determine the cross frequency, f_C. Generally, f_Cis between

f_SW/12 and f_SW/6.

The selected output capacitor voltage rating must be greater

than the output voltage. The rms current rating of the output

capacitor must be larger than the value calculated by

∆I_L

2. Calculate R_Cby using the following equation:

2× π×V_OUT×C_OUT× f_C

R_C=

0.6V × g_m× A_VI

I_C

=

OUT_RMS

12

3. Place the compensation zero at the domain pole, f_P; then

determine C_Cby using the following equation:

COMPENSATION DESIGN

For peak current mode control, the power stage can be simplified

as a voltage controlled current source supplying current to the

output capacitor and load resistor. It is composed of one domain

pole and a zero that is contributed by the output capacitor ESR.

The control to output transfer function is based on the following:

(R + R_ESR)×C_OUT

C_C=

R_C

4. C_CPis optional. It can be used to cancel the zero caused by

the ESR of the output capacitor.

s

1+

R

_ESR×C_OUT

V

_OUT(s)

2×π× f_Z

C_CP

=

G

_VD(S) =

= A_VI× R ×

s

R_C

V_COMP(s)

1+

2×π× f_P

The fixed output version IC must consider the feedforward

capacitance of feedback resistor (R_TOP) to calculate C_CP.

The total internal feedback resistance is 1 MΩ.

1

f_Z=

f_P=

2 × π × R_ESR×C_OUT

First, place the compensation pole at the minimum value

1

2 × π ×(R + R_ESR)×C_OUT

between the domain pole, f_P, and f_FB× f_FB

.

Z

P

where:

_VI= 10 A/V.

R is the load resistance.

_OUTis the output capacitance.

_ESRis the equivalent series resistance of the output capacitor.

1

A

f_FB

=

P

1

2π×C_F×(

+

)

R_TOP

R_BOT

C

R

1

f_FB

Z

2π×R_TOP×C_F

The ADP2165/ADP2166 use a transconductance amplifier for the

error amplifier, which compensates for the system loop. Figure 30

shows the simplified, peak current mode control, small signal circuit.

Then, determine C_CPby

C_C×min

(

f_P, f_FB× f_FB

)

P

Z

V

OUT

C_CP

=

R_C×C_C− C_C×min

(

f_P, f_FB× f_FB

)

P

Z

R

TOP

where C_F= 8.14 pF.

V

C

R

COMP

C

OUT

–

g_m

+

–

A

VI

+

R

BOT

R

C

CP

ESR

C

Figure 30. Simplified Peak Current Mode Control, Small Signal Circuit

Rev. B | Page 16 of 23

Data Sheet

ADP2165/ADP2166

DESIGN EXAMPLE

ADP2166

V

= 5V

PVIN

BST

SW

C

0.1µF

BST

L1

0.47µH

C

V

= 1.2V

AVIN

EN

IN

OUT

47µF

16V

C

100µF

6.3V

C

OUT2

100µF

6.3V

OUT1

R

10kΩ

TOP

PGOOD

SYNC

RT

FB

COMP

C

4.7pF

R

TRK

CP

C

R

BOT

36kΩ

10kΩ

680pF

VREG

SS

C

1µF

SS

22nF

VREG

GND PGND

Figure 31. Schematic for Design Example

This section describes the procedures for selecting the external

components based on the example specifications listed in Table 7.

See Figure 31 for the schematic of this design example.

This calculation results in L = 0.422 µH. Choose the standard

inductor value of 0.47 µH.

The peak-to-peak inductor ripple current can be calculated by

using the following equation:

Table 7. Step-Down DC-to-DC Regulator Requirements

(V_IN−V_OUT)× D

Parameter

Specification

V_PVIN= 5.0 V 10%

V_OUT= 1.2 V

ΔI_L=

Input Voltage

L × f_SW

Output Voltage

Output Current

Output Voltage Ripple

Load Transient

This calculation results in ∆I_L= 1.617 A.

I_OUT= 6 A

Use the following equation to calculate the peak inductor

current:

∆V_{OUT_RIPPLE}= 12 mV

5%, 1 A to 5 A, 2 A/µs

f_SW= 1.2 MHz

Switching Frequency

∆I_L

2

I

_PEAK= I_OUT+

OUTPUT VOLTAGE SETTING

This calculation results in I_PEAK= 6.809 A.

Choose a 10 kΩ resistor as the top feedback resistor (R_TOP

)

and calculate the bottom feedback resistor (R_BOT) by using the

following equation:

Use the following equation to calculate the rms current flowing

through the inductor:

2













0.6

V_OUT− 0.6

∆I_L

12

2

R_BOT= R_TOP×

I_RMS

=

I_OUT

+

This calculation results in I_RMS= 6.018 A.

To set the output voltage to 1.2 V, the resistor values are as

follows: R_TOP= 10 kΩ and R_BOT= 10 kΩ.

Based on the calculated current value, select an inductor with

a minimum rms current rating of 6.03 A and a minimum

saturation current rating of 6.9 A.

FREQUENCY SETTING

To use the fixed 1.2 MHz switching frequency, connect the RT

pin to the VREG pin.

However, to protect the inductor from reaching its saturation

point under the current-limit condition, use an inductor that is

rated for at least a 9 A saturation current for reliable operation.

INDUCTOR SELECTION

The peak-to-peak inductor ripple current, ∆I_L, is set to 30% of

the maximum output current. Use the following equation to

estimate the inductor value:

Based on the requirements described previously, select a 0.47 µH

inductor, such as the 744314047 from Würth, which has a 1.35 mΩ

DCR and a 20 A saturation current.

(V_PVIN−V_OUT)× D

L =

∆I_L× f_SW

where:

V

_PVIN= 5 V.

_OUT= 1.2 V.

D = 0.24.

∆I_L= 1.8 A.

f_SW= 1.2 MHz.

Rev. B | Page 17 of 23

ADP2165/ADP2166

Data Sheet

OUTPUT CAPACITOR SELECTION

COMPENSATION COMPONENTS

The output capacitor is required to meet both the output voltage

ripple and load transient response requirements.

For better load transient and stability performance, set the cross

frequency, f_C, to f_SW/10. In this case, f_SWis running at 1200 kHz;

therefore, the f_Cis set to 120 kHz.

To meet the output voltage ripple requirement, use the following

equation to calculate the ESR and capacitance value of the output

capacitor:

The 100 µF and 47 µF ceramic output capacitors have a derated

value of 62 µF and 32 µF.

∆I_L

2× π ×1.2 V ×94 μF×120kHz

C_{OUT_RIPPLE}

=

R_C=

C_C=

= 28.35 kΩ

8× f_S× ∆V_{OUT _ RIPPLE}

0.6 V ×500 μs ×10A/V

∆V_{OUT _ RIPPLE}

(0.2 Ω + 0.002 Ω)×94 μF

R_ESR

=

= 669.8 pF

∆I_L

28.35 kΩ

This calculation results in C_{OUT_RIPPLE}= 14 µF and R_ESR= 7.4 mΩ.

0.002 Ω × 94 μF

C_CP

=

= 6.63 pF

To meet the 5% overshoot and undershoot transient

requirements, use the following equations to calculate the

capacitance:

28.35 kΩ

Choose standard components as follows: R_C= 27 kΩ, C_C= 680 pF,

and C_CP= 4.7 pF.

K_OV× ∆I_STEP²× L

(V_OUT+ ∆V_{OUT _OV}) −V_OUT

C_{OUT_OV}

=

SOFT START TIME PROGRAM

2

The soft start feature allows the output voltage to ramp up in a

controlled manner, eliminating output voltage overshoot during

soft start and limiting the inrush current. Set the soft start time

to 4 ms.

K_UV× ∆I_STEP²× L

2 ×(V_PVIN−V_OUT)× ∆V_{OUT _UV}

C_{OUT_UV}

where:

_OV= K_UV= 2, the coefficients for estimation purposes.

t_{SS _ EXT}× I_{SS _UP}4 ms ×3.5μA

K

C_SS

=

= 23.3 nF

∆I_STEP= 4 A, the load transient step.

0.6

0.6V

∆V_{OUT_OV}= 5% × V_OUT, the overshoot voltage.

∆V_{OUT_UV}= 5% × V_OUT, the undershoot voltage.

Choose a standard component value as follows: C_SS= 22 nF.

INPUT CAPACITOR SELECTION

This calculation results in C_{OUT_OV}= 100 µF and C_{OUT_UV}= 33 µF.

A minimum 22 µF ceramic capacitor must be placed near the

PVIN pin. In this application, it is recommended that one 47 µF,

X5R, 16 V ceramic capacitor be used.

According to the calculation, the output capacitance must be

greater than 100 µF, and the ESR of the output capacitor must be

smaller than 7.4 mΩ. It is recommended that one 100 µF, X5R,

6.3 V ceramic capacitor and one 47 µF, X5R, 6.3 V ceramic

capacitor be used, such as the GRM32ER60J107ME20 and

GRM32ER60J476ME20 from Murata, with an ESR of 2 mΩ.

Rev. B | Page 18 of 23

Data Sheet

ADP2165/ADP2166

RECOMMENDED EXTERNAL COMPONENTS

Table 8. Recommended External Components for Typical Applications with 6 A Output Current

f_SW(kHz)

V_PVIN(V)

3.3

5

V_OUT(V)

L (µH)

C_OUT(µF)¹

680 + 330

680 + 47

680

470 + 100

470 + 47

680 + 330

680 + 470

680

R_TOP(kΩ)

R_BOT(kΩ)

R_C(kΩ) C_C(pF)

C_CP(pF)

134

111

89

85

61

668

64

89

85

267

12

279

232

11

9

300

1

1.5

2.2

1.5

2.2

10

15

20

47.5

10

15

20

15

10

15

10

15

2.21

15

10

15

10

15

2.21

15

10

15

10

15

2.21

52.9

44.7

53.4

50.1

65.7

52.9

72.3

53.4

44.3

47.4

32.1

45.5

54.6

29.4

28.0

39.0

66.9

54.6

62.2

28.0

39.0

25.7

31.2

37.4

35.4

28.0

39.0

82.9

37.4

35.4

28.0

19.6

51.4

3300

1600

1500

1300

1500

1300

680

1.2

1.5

1.8

2.5

1

1.2

1.5

1.8

2.5

3.3

1

1.2

1.5

1.8

2.5

1

1.2

1.5

1.8

2.5

3.3

1

1.2

1.5

1.8

2.5

1

1.2

1.5

1.8

2.5

3.3

2.2

3.3

2.2

470

330 + 47

3 × 100

330 + 47

2 × 100 + 47

2 × 100

470 + 100

330 + 47

330

47.5

10

5

600

3.3

5

0.6

10

15

20

47.5

10

15

20

0.82

0.6

0.82

1

1.5

1

6

64

232

186

9

6

5

2 × 100

100 + 47

100

47.5

10

5

1200

3.3

5

0.33

0.47

0.33

0.47

0.6

2 × 100

100 + 47

100

330

2 × 100

100 + 47

100

10

15

20

47.5

10

15

20

8

7

5

4

3

139

7

5

4

680

0.6

47.5

10

680

3

2

5

¹680 µF: 2.5 V, KEMET T520D687M2R5ATE010; 470 µF: 2.5 V, KEMET T520D477M2R5ATE006; 330 µF: 2.5 V, KEMET T520D337M2R5ATE006; 220 µF: 2.5 V, KEMET

T520D227M2R5ATE007; 330 µF: 4 V, KEMET T520D337M004ATE006; 100 µF: 6.3 V, X5R, Murata GRM32ER60J107ME20; 47 µF: 6.3 V, X5R, Murata GRM32ER60J476ME20.

V_OUTis higher than 1.5 V, and C_OUTmust use a 4 V tantalum capacitor.

Rev. B | Page 19 of 23

ADP2165/ADP2166

Data Sheet

PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS

Good circuit board layout is essential for obtaining the best

performance from the ADP2165/ADP2166. Poor printed

circuit board (PCB) layout degrades the output regulation as

well as the electromagnetic interface (EMI) and electromagnetic

compatibility (EMC) performance. Figure 32 shows a PCB layout

example. For optimum layout, use the following guidelines:

•

Connect the exposed pad of the ADP2165/ADP2166 to

a large copper plane to maximize its power dissipation

capability for better thermal dissipation.

Place the feedback resistor divider network as close as possible to

the FB pin to prevent noise pickup. Try to minimize the length of

the trace that connects the top of the feedback resistor divider

to the output while keeping the trace away from the high current

traces and the switching node to avoid noise pickup. To further

reduce noise pickup, place an analog ground plane on either side of

the FB trace and ensure that the trace is as short as possible to

reduce parasitic capacitance pickup.

•

Use separate analog ground and power ground planes.

Connect the ground reference of sensitive analog circuitry,

such as output voltage divider components, to analog

ground. In addition, connect the ground reference of

power components, such as input and output capacitors, to

power ground. Connect both ground planes to the exposed

pad of the ADP2165/ADP2166.

Place the input capacitor, inductor, and output capacitor as

close to the IC as possible and use short traces.

•

Ensure that the high current loop traces are as short and as

wide as possible. Make the high current path from the input

capacitor through the inductor, the output capacitor, and the

power ground plane back to the input capacitor as short as

possible. To accomplish this, ensure that the input and output

capacitors share a common power ground plane.

ANALOG GROUND PLANE

VIA

BOTTOM LAYER

TRACE

C

COPPER PLANE

VREG

R

TOP

POWER GROUND PLANE

VREG

EN

PULL-UP

SW

GND

PGOOD

BST

AVIN

PVIN

C

BST

PGND

POWER GROUND

PLANE

INPUT

BYPASS

CAPACITOR

INPUT

PVIN

BULK

CAPACITOR

OUTPUT

CAPACITOR

PVIN

SW

INDUCTOR

VOUT

Figure 32. Recommended PCB Layout

Rev. B | Page 20 of 23

Data Sheet

ADP2165/ADP2166

REFERENCE DESIGNS

See Figure 33 through Figure 36 for the detailed reference designs.

ADP2165/

ADP2166

V

= 5V

PVIN

AVIN

EN

BST

C

0.1µF

BST

L1

0.82µH

C

V

= 1.2V

OUT

IN

47µF

16V

SW

C

470µF

6.3V

OUT

R

10kΩ

TOP

PGOOD

RT

FB

SYNC

TRK

COMP

C

33pF

R

33kΩ

C

1.5nF

CP

C

R

10kΩ

BOT

VREG

SS

C

1µF

SS

22nF

VREG

GND PGND

Figure 33. 1.2 V, 5 A/6 A, 620 kHz by Floating the RT Pin Step-Down Regulator Application

ADP2165/

ADP2166

PVIN

AVIN

EN

V

= 5V

PVIN

BST

C

0.1µF

BST

L1

0.6µH

C

V

= 1.8V

OUT

IN

47µF

16V

SW

C

100µF

6.3V

OUT

R

20kΩ

TOP

PGOOD

SYNC

RT

1.2MHz

EXT CLOCK

FB

COMP

C

3.3pF

R

TRK

CP

C

R

BOT

27kΩ

10kΩ

680pF

VREG

SS

C

1µF

SS

22nF

VREG

GND PGND

Figure 34. 1.8 V, 5 A/6 A Step-Down Regulator Application, Synchronized to 1.2 MHz, 180° Out of Phase with the External Clock

ADP2165/

ADP2166

V

= 5V

PVIN

AVIN

EN

BST

C

0.1µF

BST

L1

0.82µH

C

V

= 3.3V

IN

OUT

47µF

16V

SW

C

100µF

6.3V

OUT

R

10kΩ

TOP

PGOOD

SYNC

TRK

R

10kΩ

TRKT

FB

V

MASTER

COMP

R

TRKB

C

1.8pF

R

RT

CP

C

2.21kΩ

R

BOT

51kΩ

2.21kΩ

680pF

VREG

SS

C

1µF

SS

22nF

VREG

GND PGND

Figure 35. 3.3 V, 5 A/6 A, 1.2 MHz Step-Down Regulator Application, Tracking Mode

Rev. B | Page 21 of 23

ADP2165/ADP2166

Data Sheet

ADP2165/

ADP2166

V

= 5V

PVIN

BST

C

0.1µF

BST

L1

0.47µH

C

47µF

16V

V

= 1.2V

AVIN

EN

IN

OUT

SW

C

OUT2

OUT1

100µF

6.3V

100µF

6.3V

PGOOD

SYNC

RT

FB

COMP

R

T

C

R

TRK

CP

C

43.5kΩ

4.7pF

36kΩ

VREG

SS

C

SS

22nF

VREG

GND PGND

680pF

1µF

Figure 36. Fixed Output 1.2 V, 5 A/6 A, 1.2 MHz Step-Down Regulator Application

Rev. B | Page 22 of 23

Data Sheet

ADP2165/ADP2166

OUTLINE DIMENSIONS

DETAIL A

(JEDEC 95)

4.10

4.00 SQ

3.90

0.30

0.25

0.18

PIN 1

INDICATOR

PIN 1

INDIC ATOR AREA OPTIONS

(SEE DETAIL A)

24

19

18

1

0.50

BSC

2.70

2.60 SQ

2.50

EXPOSED

PAD

13

12

6

7

0.50

0.40

0.30

0.20 MIN

TOP VIEW

BOTTOM VIEW

0.80

0.75

0.70

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8

Figure 37. 24-Lead Lead Frame Chip Scale Package [LFCSP]

4 mm × 4 mm Body and 0.75 mm Package Height

(CP-24-15)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Output Current (A)

Temperature Range

−40°C to +125°C

Output Voltage

Package Description

Package Option

CP-24-15

ADP2165ACPZ-R7

5

ADJ

24-Lead LFCSP

Evaluation Board

24-Lead LFCSP

Evaluation Board

ADP2165ACPZ-1.0-R7

ADP2165ACPZ-1.2-R7

ADP2165ACPZ-1.5-R7

ADP2165ACPZ-1.8-R7

ADP2165ACPZ-2.5-R7

ADP2165ACPZ-3.3-R7

ADP2165-EVALZ

1.0 V

1.2 V

1.5V

1.8 V

2.5 V

3.3 V

ADP2166ACPZ-R7

6

−40°C to +125°C

ADJ

CP-24-15

ADP2166ACPZ-1.0-R7

ADP2166ACPZ-1.2-R7

ADP2166ACPZ-1.5-R7

ADP2166ACPZ-1.8-R7

ADP2166ACPZ-2.5-R7

ADP2166ACPZ-3.3-R7

ADP2166-EVALZ

1.0 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D10956-0-8/17(B)

Rev. B | Page 23 of 23


型号：	ADP2165ACPZ-3.3-R7
厂家：	ADI
描述：	5.5 V, 5 A/6 A, High Efficiency, Step-Down DC-to-DC Regulators with Output Tracking
文件：	总23页 (文件大小：670K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADP2165ACPZ-3.3-R7 [ADI]

相关型号：

ADP2165ACPZ-R7

ADP2166

ADP2166-EVALZ

ADP2166ACPZ-1.0-R7

ADP2166ACPZ-1.2-R7

ADP2166ACPZ-1.5-R7

ADP2166ACPZ-1.8-R7

ADP2166ACPZ-2.5-R7

ADP2166ACPZ-3.3-R7

ADP2166ACPZ-R7

ADP220ACBZ-1118R7

ADP220ACBZ-1212R7