ADP2442ACPZ-R7 [ADI]
36 V,1 A, Synchronous, Step-Down, DC-to-DC Regulator with External Clock Synchronization;
| 型号： | ADP2442ACPZ-R7 |
| 厂家： | 
ADI |
| 描述： | 36 V,1 A, Synchronous, Step-Down, DC-to-DC Regulator with External Clock Synchronization 开关 输出元件 |
| 文件： | 总37页 (文件大小：1641K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
36 V,1 A, Synchronous, Step-Down, DC-to-DC
Regulator with External Clock Synchronization
Data Sheet
ADP2442
FEATURES
TYPICAL CIRCUIT CONFIGURATION
C2
Wide input voltage range from 4.5 V to 36 V
Low minimum on time of 50 ns typical
Maximum load current of 1 A
C1
V
OUT
C
BOOST
High efficiency of up to 94%
Adjustable output down to 0.6 V
1% output voltage accuracy
R
R
TOP
V
IN
FB
VIN
SW
ADP2442
BOTTOM
V
OUT
COMP
Adjustable switching frequency from 300 kHz to 1 MHz
External synchronization from 300 kHz to 1 MHz
Pulse skip mode or forced fixed frequency mode
Precision enable input pin (EN)
C
C
OUT
R
IN
COMP
PGND
EN
C
COMP
Open-drain power good
R
FREQ
Internal soft start
Overcurrent-limit protection
Shutdown current of less than 15 μA
UVLO and thermal shutdown
Figure 1.
The ADP2442 offers the flexibility of external clock
synchronization. The switching frequency can be synchronized to
an external clock, applied to the SYNC/MODE pin. The ADP2442
can also be configured to operate in the forced fixed frequency
mode for low EMI or power saving mode to reduce the switching
losses at light load.
12-lead, 3 mm × 3 mm LFCSP package
Supported by the ADIsimPower™ tool set
Reference similar product ADP2441 with programmable soft
start and tracking
APPLICATIONS
The ADP2442 uses hiccup mode to protect the IC from short
circuits or from overcurrent conditions on the output. The internal
soft start limits inrush current during startup for a wide variety of
load capacitances. Other key features include input undervoltage
lockout (UVLO), thermal shutdown (TSD), and precision enable
(EN), which can also be used as a logic level shutdown input.
Point of load applications
Distributed power systems
Industrial control supplies
Standard rail conversion to 24 V/12 V/5 V/3.3 V
GENERAL DESCRIPTION
The ADP2442 is a constant frequency, current mode control,
synchronous, step-down, dc-to-dc regulator that is capable of
driving loads of up to 1 A with excellent line and load regulation
characteristics. The ADP2442 operates with a wide input voltage
range from 4.5 V to 36 V, which makes it ideal for regulating
power from a wide variety of sources. In addition, the ADP2442
has very low minimum on time (50 ns) and is, therefore, suitable
for applications requiring a very high step-down ratio.
The ADP2442 is available in a 3 mm × 3 mm, 12-lead LFCSP
package and is rated for a junction temperature range from
−40°C to +125°C.
100
90
80
70
60
50
40
30
20
10
0
V
= 12V
OUT
V
= 5V
OUT
The output voltage can be adjusted from 0.6 V to 0.9 × VIN. High
efficiency is obtained with integrated low resistance N-channel
MOSFETs for both high-side and low-side devices.
V
= 3.3V
OUT
The switching frequency is adjustable from 300 kHz to 1 MHz with
an external resistor. The ADP2442 also has an accurate power-good
(PGOOD) open-drain output signal.
V
= 24V
IN
PWM = 300kHz
0.01
0.1
LOAD (A)
1
Figure 2. Efficiency vs. Load Current, VIN = 24 V
Rev. B
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Technical Support
www.analog.com
ADP2442* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
REFERENCE MATERIALS
Technical Articles
• MS-2727: Optimizing Multiple Output Power Converters
EVALUATION KITS
• ADL5567 & AD9625 Analog Signal Chain Evaluation and
ADF4355-2 Wideband Synthesizer with VCO
DESIGN RESOURCES
• ADP2442 Material Declaration
• PCN-PDN Information
• ADP2442 Evaluation Board
• Quality And Reliability
• Symbols and Footprints
DOCUMENTATION
Application Notes
• AN-1269: Designing an Inverting Power Supply Using the
ADP2441/ADP2442 Synchronous Step-Down DC-to-DC
Regulators
DISCUSSIONS
View all ADP2442 EngineerZone Discussions.
Data Sheet
SAMPLE AND BUY
• ADP2442: 36 V,1 A, Synchronous, Step-Down, DC-to-DC
Visit the product page to see pricing options.
Regulator with External Clock Synchronization Data Sheet
User Guides
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
• UG-456: Evaluation Board for the ADP2442 36 V, 1 A,
Synchronous, Step-Down DC-to-DC Regulator with
External Clock Synchronization
DOCUMENT FEEDBACK
TOOLS AND SIMULATIONS
Submit feedback for this data sheet.
• ADIsimPower™ Voltage Regulator Design Tool
• ADP244x Buck Regulator Design Tool
• ADP244x Inverting Buck-Boost Design Tool
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ADP2442
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Thermal Shutdown .................................................................... 18
Applications Information .............................................................. 19
ADIsimPower Design Tool ....................................................... 19
Selecting the Output Voltage .................................................... 19
Setting the Switching Frequency.............................................. 19
External Component Selection ................................................ 20
Boost Capacitor .......................................................................... 22
VCC Capacitor............................................................................ 22
Loop Compensation .................................................................. 22
Large Signal Analysis of the Loop Compensation................. 22
Design Example.............................................................................. 24
Configuration and Components Selection ............................. 24
System Configuration ................................................................ 25
Typical Application Circuits ......................................................... 26
Design Example.......................................................................... 26
Other Typical Circuit Configurations ..................................... 27
Power Dissipation and Thermal Considerations ....................... 31
Power Dissipation....................................................................... 31
Thermal Considerations............................................................ 31
Evaluation Board Thermal Performance ................................ 32
Circuit Board Layout Recommendations ................................... 33
Outline Dimensions....................................................................... 34
Ordering Guide .......................................................................... 34
Applications....................................................................................... 1
General Description ......................................................................... 1
Typical Circuit Configuration......................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Efficiency in Forced Fixed Frequency Mode............................ 7
Efficiency in Pulse Skip Mode .................................................... 8
Internal Block Diagram ................................................................. 15
Theory of Operation ...................................................................... 16
Control Architecure ................................................................... 16
Adjustable Frequency................................................................. 17
Power Good................................................................................. 17
Mode of Operation..................................................................... 17
External Synchronization.......................................................... 17
Soft Start ...................................................................................... 17
Undervoltage Lockout ............................................................... 17
Precision Enable/Shutdown ...................................................... 17
Current-Limit and Short-Circuit Protection.............................. 18
REVISION HISTORY
8/15—Rev. A to Rev. B
Changes to Figure 51...................................................................... 15
5/14—Rev. 0 to Rev. A
Change to Features Section ............................................................. 1
11/12—Revision 0: Initial Version
Rev. B | Page 2 of 36
Data Sheet
ADP2442
SPECIFICATIONS
VIN = 4.5 V to 36 V, TJ = −40°C to +125°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
POWER SUPPLY
Input Voltage Range
Supply Current
Shutdown Current
UVLO
VIN
IVIN
ISHDN
4.5
36
2
15
V
mA
μA
VEN = 1.5 V not switching
VEN = AGND
1.7
10
Threshold
Hysteresis
VUVLO
VIN falling
3.8
4
200
4.2
5.5
V
mV
INTERNAL REGULATOR
Regulator Output Voltage
OUTPUT
VCC
VIN = 5 V to 36 V
5
V
Output Voltage Range
Maximum Output Current
Feedback Regulation Voltage
VOUT
IOUT
VFB
0.6
1
0.594
0.591
0.9 × VIN
V
A
V
V
TJ = −40°C to +85°C
TJ = −40°C to +125°C
0.6
0.6
0.606
0.609
Line Regulation
Load Regulation
0.005
0.05
%/V
%/A
ERROR AMPLIFIER
Feedback Bias Current
Transconductance
Open-Loop Voltage Gain1
MOSFETS
IFB_BIAS
gm
AVOL
VFB = 0.6 V
ICOMP = 20 μA
50
250
65
200
300
nA
μA/V
dB
200
High-Side Switch On Resistance2
Low-Side Switch On Resistance2
Leakage Current
Minimum On Time3
Minimum Off Time4
CURRENT SENSE
RDS_H(ON)
RDS_L(ON)
ILKG
tON_MIN
tOFF_MIN
BST − SW = 5 V
VCC = 5 V
VEN = AGND
170
120
1
50
165
270
180
25
65
175
mΩ
mΩ
ꢀA
ns
All switching frequencies
ns
Current Sense Amplifier Gain
Hiccup Time
Number of Cumulative Current-Limit Cycles
to Enter Hiccup Mode
Peak Current Limit
FREQUENCY
GCS
1.6
1.4
2
6
8
2.4
A/V
ms
Events
fSW = 300 kHz to1 MHz
ICL
1.6
1.8
A
Switching Frequency Range
Frequency Set Accuracy
fSW
300
270
900
300
1000
330
1100
1000
kHz
kHz
kHz
kHz
FREQ pin = 308 kΩ
FREQ pin = 92.5 kΩ
300
1000
Frequency Synchronization Range
SOFT START
Soft Start Time
PRECISION ENABLE
Input Threshold
Hysteresis
Leakage Current
Thermal Shutdown
Rising
tSS
2
ms
VEN(RISING)
VEN(HYST)
IIEN_LEAK
1.15
1.20
100
0.1
1.25
1
V
mV
μA
VIN = VEN
TSD
TSD(HYST)
150
25
°C
°C
Hysteresis
Rev. B | Page 3 of 36
ADP2442
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
POWER GOOD
PGOOD High, FB Rising Threshold5
PGOOD Low, FB Rising Threshold5
PGOOD High, FB Falling Threshold5
PGOOD Low, FB Falling Threshold5
PGOOD
89
92
95
%
%
%
%
111
106
83
115
109
86
118
112
89
Delay
tPGOOD
50
1
0.5
μs
μA
kΩ
High Leakage Current
Pull-Down Resistor
SYNC/MODE
IPGOOD(SRC) VPGOOD = VCC
IPGOOD(SNK) FB = 0 V
10
0.7
SYNC/MODE Input
Logic High
2
V
Logic Low
0.8
V
Pulse Width
100
ns
1 Guaranteed by design.
2 Measured between VIN and SW pins and includes bond wires and pin resistance.
3 Based on bench characterization. Measured with VIN = 12 V, VOUT = 1.2 V, load = 1 A, fSW = 1 MHz, and the output in regulation. Measurement does not include dead time.
4 Based on bench characterization. Measured with VIN = 15 V, VOUT = 12 V, load = 1 A, fSW = 600 kHz, and the output in regulation. Measurement does not include dead time.
5 This threshold is expressed as a percentage of the nominal output voltage.
Rev. B | Page 4 of 36
Data Sheet
ADP2442
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages based on
a 4-layer standard JEDEC board.
Parameter
VIN to PGND
EN to AGND
SW to PGND
BST to PGND
VCC to AGND
BST to SW
Rating
−0.3 V to +40 V
−0.3 V to +40 V
−0.3 V to +40 V
−0.3 V to +45 V
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to +6 V
Table 3. Thermal Resistance
Package Type
θJA
θJC
Unit
12-Lead LFCSP
40
2.4
°C/W
FREQ, PGOOD, SYNC/MODE, COM P,
FB to AGND
PGND to AGND
ESD CAUTION
0.3 V
Operating Junction Temperature
Range
−40°C to +125°C
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
−65°C to +150°C
260°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. B | Page 5 of 36
ADP2442
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
FB 1
9 VIN
SW
ADP2442
TOP
VIEW
COMP
2
8
EN 3
7 PGND
NOTES
1. THE EXPOSED PAD SHOULD BE CONNECTED
TO THE SYSTEM AGND PLANE AND PGND PLANE.
Figure 3. Pin Configuration, Top View
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1
FB
Feedback. The FB regulation voltage is 0.6 V. Connect this pin to a resistor divider from the output of the dc-to-dc
regulator.
2
3
COMP
EN
Error Amplifier Compensation. Connect a resistor and a capacitor in series to ground.
Precision Enable. This features offers 5% accuracy when using a 1.25 V reference voltage. Pull this pin high to
enable the regulator and pull it low to disable the regulator. Do not leave this pin floating.
4
5
PGOOD
FREQ
Active High Power Good Output. This pin pulls low when the output is out of regulation.
Switching Frequency. A resistor to AGND sets the switching frequency (see the Setting the Switching Frequency
section). Do not leave this pin floating.
6
SYNC/MODE External Clock Synchronization/Mode Pin. This pin can be used for external frequency synchronization and for
setting forced fixed frequency mode or pulse skip mode. SYNC/MODE accepts an external clock signal, and when
pulled high to 5 V, it sets the mode as forced fixed frequency mode. When this pin is tied to AGND, pulse skip
mode enables. Do not leave the SYNC/MODE pin floating.
7
PGND
Power Ground. Connect a decoupling ceramic capacitor as close as possible between the VIN pin and PGND.
Connect this pin directly to the exposed pad.
8
SW
Switch. The midpoint for the drain of the low-side N-channel power MOSFET switch and the source for the high-
side N-channel power MOSFET switch.
9
VIN
Power Supply Input. Connect this pin to the input power source, and connect a bypass ceramic capacitor directly
from this pin to PGND, as close as possible to the IC. The operation voltage is 4.5 V to 36 V.
10
BST
Boost. Connect a 10 nF ceramic capacitor between the BST and SW pins as close to the IC as possible to form a
floating supply for the high-side N-channel power MOSFET driver. This capacitor is required to drive the gate of
the N-channel power MOSFET above the supply voltage.
11
12
VCC
Output of the Internal Low Dropout Regulator. This pin supplies power for the internal controller and driver
circuitry. Connect a 1 µF ceramic capacitor between VCC and AGND and a 1 µF ceramic capacitor between VCC
and PGND. The VCC output is active when the EN pin voltage is more than 0.7 V.
Analog Ground. This pin is the internal ground for the control functions. Connect this pin to the exposed pad.
Exposed Pad. Connect the exposed pad to the system AGND plane and PGND plane.
AGND
EP
Rev. B | Page 6 of 36
Data Sheet
ADP2442
TYPICAL PERFORMANCE CHARACTERISTICS
EFFICIENCY IN FORCED FIXED FREQUENCY MODE
100
100
90
80
70
60
50
40
30
20
10
0
90
80
V
= 12V
IN
V
= 12V
70
60
50
40
30
20
10
0
IN
V
= 24V
IN
V
= 24V
IN
V
= 3.3V
V
= 3.3V
OUT
OUT
fSW = 300kHz
fSW = 700kHz
0.01
0.1
LOAD (A)
1
0.01
0.1
1
LOAD (A)
Figure 4. Efficiency vs. Load Current, VOUT = 3.3 V, fSW = 300 kHz
Figure 7. Efficiency vs. Load Current, VOUT = 3.3 V, fSW = 700 kHz
100
100
90
90
80
70
60
50
40
30
20
10
0
V
= 12V
IN
V
= 12V
IN
80
70
60
50
40
30
20
10
0
V
= 24V
IN
V
= 36V
V
= 24V
IN
IN
V
= 36V
IN
V
= 5V
V
= 5V
OUT
OUT
fSW = 300kHz
fSW = 700kHz
0.01
0.1
LOAD (A)
1
0.01
0.1
LOAD (A)
1
Figure 5. Efficiency vs. Load Current, VOUT = 5 V, fSW = 300 kHz
Figure 8. Efficiency vs. Load Current, VOUT = 5 V, fSW = 700 kHz
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
V
= 24V
IN
V
= 24V
IN
V
= 36V
IN
V
= 36V
IN
V
= 12V
V
= 12V
OUT
OUT
fSW = 600kHz
fSW = 300kHz
0.01
0.1
1
0.01
0.1
LOAD (A)
1
LOAD (A)
Figure 9. Efficiency vs. Load Current, VOUT = 12 V, fSW = 600 kHz
Figure 6. Efficiency vs. Load Current, VOUT = 12 V, fSW = 300 kHz
Rev. B | Page 7 of 36
ADP2442
Data Sheet
EFFICIENCY IN PULSE SKIP MODE
100
100
90
80
70
60
50
40
30
20
10
0
V
= 5V
IN
V
= 5V
90
80
70
60
50
40
30
20
10
0
IN
V
= 12V
IN
V
= 12V
IN
V
= 24V
IN
V
= 24V
IN
V
= 3.3V
V
= 3.3V
OUT
OUT
fSW = 300kHz
COILCRAFT MSS1038
fSW = 700kHz
COILCRAFT MSS1038
0.01
0.1
LOAD (A)
1
1
1
0.01
0.1
LOAD (A)
1
Figure 10. Efficiency vs. Load Current,
OUT = 3.3 V, fSW = 300 kHz
Figure 13. Efficiency vs. Load Current,
OUT = 3.3 V, fSW = 700 kHz
V
V
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
V
= 12V
IN
V
= 12V
IN
V
= 24V
IN
V
= 24V
IN
V
= 36V
IN
V
= 36V
IN
V
= 5V
V
= 5V
OUT
OUT
fSW = 300kHz
COILCRAFT MSS1038
fSW = 700kHz
COILCRAFT MSS1038
0.01
0.1
LOAD (A)
0.01
0.1
LOAD (A)
1
Figure 11. Efficiency vs. Load Current,
Figure 14. Efficiency vs. Load Current,
OUT = 5 V, fSW = 700 kHz
V
OUT = 5 V, fSW = 300 kHz
V
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
V
= 24V
IN
V
= 24V
IN
V
= 36V
IN
V
= 36V
IN
V
= 12V
V
= 12V
OUT
OUT
fSW = 300kHz
COILCRAFT MSS1038
fSW = 600kHz
COILCRAFT MSS1038
0.01
0.1
0.01
0.1
1
LOAD (A)
LOAD (A)
Figure 12. Efficiency vs. Load Current,
Figure 15. Efficiency vs. Load Current,
VOUT = 12 V, fSW = 300 kHz
VOUT = 12 V, fSW = 600 kHz
Rev. B | Page 8 of 36
Data Sheet
ADP2442
0.3
400
350
300
250
200
150
100
50
V
V
V
= 12V
= 24V
= 36V
IN
IN
IN
fSW = 300kHz
0.2
0.1
fSW = 700kHz
0
–0.1
–0.2
–0.3
V
= 5V
OUT
fSW = 700kHz
SYNC = VCC, FORCED PWM MODE
V
= 3.3V
15
OUT
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.0
42
5
10
20
25
30
35
40
LOAD (A)
V
(V)
IN
Figure 16. Load Regulation for Different Supplies
Figure 19. Pulse Skip (PSKIP) Threshold Load Current, VOUT = 3.3 V
1.0
0.8
300
fSW = 300kHz
250
0.6
0.4
T
= +25°C
A
200
0.2
T
= –40°C
A
fSW = 700kHz
0
150
–0.2
–0.4
–0.6
–0.8
–1.0
100
50
T
= +125°C
A
V
V
= 24V
= 5V
IN
OUT
V
= 5V
fSW = 700kHz
SYNC = AGND PULSE SKIP MODE
OUT
0
0
0.2
0.4
0.6
0.8
10
15
20
25
(V)
30
35
40
LOAD (A)
V
IN
Figure 17. Load Regulation for Different Temperatures
Figure 20. Pulse Skip Threshold Load Current, VOUT = 5 V
0.30
0.25
0.20
0.15
0.10
0.05
0
300
250
200
150
100
50
fSW = 300kHz
LOAD = 1A
LOAD = 500mA
fSW = 600kHz
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
V
= 5V
OUT
fSW = 700kHz
V
= 12V
20
SYNC = VCC PWM MODE
OUT
0
7
12
17
22
27
32
37
15
25
30
35
40
V
(V)
V
(V)
IN
IN
Figure 18. Line Regulation, VOUT = 5 V for Different Loads
Figure 21. Pulse Skip Threshold Load Current, VOUT = 12 V
Rev. B | Page 9 of 36
ADP2442
Data Sheet
12
10
8
1.24
1.22
1.20
1.18
1.16
1.14
1.12
1.10
1.08
1.06
1.04
V
= 36V
IN
ENABLE RISING THRESHOLD
6
ENABLE FALLING THRESHOLD
4
V
= 4.5V
IN
2
0
–50
–50 –30 –10
10
30
50
70
90
110 130 150
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 22. Shutdown Current vs. Temperature
Figure 25. Enable Threshold vs. Temperature
130
120
110
100
90
4.5
4.4
4.3
4.2
4.1
4.0
UVLO, RISING V
IN
80
UVLO, FALLING V
IN
P
P
P
P
FALL, FB INCREASING
RISE, FB DECREASING
RISE, FB INCREASING
FALL, FB DECREASING
GOOD
GOOD
GOOD
GOOD
70
60
3.9
–50
–50 –30 –10
10
30
50
70
90
110 130 150
–25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 23. UVLO Threshold vs. Temperature
Figure 26. PGOOD Threshold vs. Temperature
1200
1000
800
600
400
200
0
2.25
2.05
1.85
1.65
1.45
1.25
1.05
0.85
0.65
0.45
0.25
0.05
fSW = 1MHz
fSW = 700kHz
V
= 4.5V
= 12V
= 24V
= 36V
IN
V
V
V
IN
IN
IN
fSW = 300kHz
0
5
10
15
20
(V)
25
30
35
40
–50 –30 –10
10
30
50
70
90
110 130 150
V
TEMPERATURE (°C)
IN
Figure 27. Switching Frequency vs. Supply
Figure 24. Supply Current vs. Temperature
Rev. B | Page 10 of 36
Data Sheet
ADP2442
1.80
1.78
1.76
1.74
1.72
1.70
1.68
1.66
1.64
1.62
1.60
1.58
1.56
1.54
1.52
1.50
200
175
150
125
100
75
MINIMUM OFF
V
V
= 36V
IN
= 4.5V
IN
MINIMUM ON
50
25
0
–50
0
50
TEMPERATURE (°C)
100
150
–50 –30 –10
10
30
50
70
90
110 130 150
TEMPERATURE (°C)
Figure 31. Current Limit vs. Temperature
Figure 28. Minimum On Time and Minimum Off Time vs. Temperature
260
240
220
200
180
160
140
120
100
180
160
140
120
100
80
60
40
20
0
–50 –30 –10
10
30
50
70
90
110 130 150
–50
–25
0
25
50
75
100
125
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 29. High-Side RDS(ON) vs. Temperature
Figure 32. Low-Side RDS(ON) vs. Temperature
1200
1100
1000
900
800
700
600
500
400
300
200
fSW = 1MHz
V
OUT
1
4
INDUCTOR CURRENT
fSW = 700kHz
V
V
f
= 24V
IN
= 5V
OUT
= 700kHz
NO LOAD
SW
SYNC/MODE = AGND
SW
fSW = 300kHz
2
B
CH1 20.0mV
CH2 10.0V
CH4 200mA Ω
M4.00µs
50.40%
A CH4 116mA
W
–50 –30 –10
10
30
50
70
90
110 130 150
T
TEMPERATURE (°C)
Figure 30. Switching Frequency vs. Temperature
Figure 33. Pulse Skip Mode, VIN = 24 V, VOUT = 5 V, fSW = 700 kHz, No Load,
SYNC/MODE = AGND
Rev. B | Page 11 of 36
ADP2442
Data Sheet
V
OUT
1
V
OUT
1
4
INDUCTOR CURRENT
4
V
V
f
= 24V
NO LOAD
IN
= 5V SYNC/MODE = VCC
OUT
INDUCTOR CURRENT
= 700kHz
SW
SW
SW
2
2
B
B
CH1 20.0mV
CH2 10.0V
CH4 500mA Ω
M1.00µs
A
CH4 –30mA
CH1 200mV
CH2 10.0V
CH4 1.00A Ω
M2.00ms A CH1 100mV
W
W
B
B
W
W
T
50.40%
T
50.40%
Figure 34. PWM Mode
VIN = 24 V, VOUT = 5 V, fSW = 700 kHz, Load = No Load, SYNC/MODE = VCC
Figure 37. Hiccup Mode, VIN = 24 V, VOUT = 5 V, fSW = 700 kHz,
Output Shorted to PGND
V
OUT
1
V
OUT
1
INDUCTOR CURRENT
V
V
f
= 24V
IN
= 5V
OUT
= 700kHz
SW
V
V
f
= 24V
OUT
= 700kHz
LOAD = 5Ω
IN
= 5V SYNC/MODE = CLOCK
SW
4
2
LOAD
4
SW
B
B
CH1 20.0mV
CH2 10.0V
CH4 500mA Ω
M1.00µs
W
A CH4 960mA
CH1 100mV
M200µs
A
CH4 430mA
W
W
B
B
CH4 500mA Ω
W
T
50.40%
T
28.80%
Figure 35. PWM Mode with External Clock, VIN = 24 V, VOUT = 5 V,
SW = 700 kHz, Load = 5 Ω, SYNC/MODE = Clock
Figure 38. Load Transient Response, VIN = 24 V, VOUT = 5 V, fSW = 700 kHz,
SYNC/MODE = Clock, Load Step = 500 mA
f
V
OUT
1
1
V
= 24V
V
= 5V fSW = 700kHz
V
IN
OUT
OUT
V
V
f
= 12V
IN
= 5V
OUT
= 300kHz
LOAD STEP = 500mA
SW
SW
LOAD
2
EXTERNAL CLOCK
4
3
B
B
CH1 20.0mV
CH2 10.0V M1.00µs
T 50.40%
A
CH2
9.80V
CH1 100mV
M200µs
A CH4 690mA
W
W
B
CH3 2.00V
CH4 500mA Ω
W
Figure 36. External Clock Synchronization,
VIN = 24 V, VOUT = 5 V, fSW = 700 kHz, SYNC/MODE = Clock
Figure 39. Load Transient Response,
VIN = 12 V, VOUT = 5 V, fSW = 300 kHz, Load Step = 500 mA
Rev. B | Page 12 of 36
Data Sheet
ADP2442
EN
V
OUT
3
1
V
OUT
V
V
f
= 24V
IN
V
V
f
= 24V
= 12V
= 300kHz
= 5V
IN
OUT
OUT
= 700kHz
PULL-UP 100kΩ
SW
SW
1
2
PGOOD
LOAD
4
B
B
B
CH1 200mV
M200µs
A
CH4 260mA
CH1 2.00V
CH3 5.00V
CH2 2.00V
M1.00ms
40.20%
A CH3 2.80V
W
W
W
B
CH4 500mA Ω
T
W
T
28.80%
Figure 40. Load Transient Response, VIN = 24 V, VOUT = 12 V, fSW = 300 kHz,
SYNC/MODE = Clock, Load Step = 500 mA
Figure 43. Power-Good Shutdown, VIN = 24 V, VOUT = 5 V, fSW = 700 kHz
V
OUT
V
IN
1
V
OUT
LOAD
V
V
f
= 24V
= 12V
= 600kHz
V
V
f
= 36V
= 5V
= 700kHz
IN
OUT
IN
3
1
OUT
SW
SW
LOAD STEP = 500mA
NO LOAD
4
SYNC/MODE = AGND
SW
2
B
B
CH1 200mV
M200µs
A CH4 600mA
CH2 10.0V
CH1 2.00V
CH3 10.0V
M2.00ms
7.80%
A CH3 6.00V
W
W
W
B
CH4 500mA Ω
T
Figure 44. Startup with VIN, Pulse Skip Mode, VIN = 36 V, VOUT = 5 V,
fSW = 700 kHz, No Load, SYNC/MODE = AGND
Figure 41. Load Transient Response,
VIN = 24 V, VOUT = 12 V, fSW = 600 kHz, Load Step = 500 mA
V
V
f
= 36V
LOAD = 5Ω
IN
EN
V
IN
= 5V SYNC/MODE = VCC
3
OUT
= 700kHz
SW
V
OUT
3
1
V
SW
OUT
1
2
V
V
f
= 24V
IN
PGOOD
= 5V
OUT
2
= 700kHz
PULL-UP 100kΩ
SW
B
B
B
CH2 10.0V
CH1 2.00V
CH3 10.0V
M2.00ms
7.80%
A CH3 6.00V
CH1 2.00V
CH3 5.00V
CH2 2.00V
M2.00ms
20.80%
A
CH3 2.80V
W
W
W
W
B
T
T
Figure 45. Startup with VIN, PWM Mode, VIN = 36 V, VOUT = 5 V, fSW = 700 kHz,
Load = 5 Ω, SYNC/MODE = VCC
Figure 42. Power-Good Startup,
VIN = 24 V, VOUT = 5 V, fSW = 700 kHz
Rev. B | Page 13 of 36
ADP2442
Data Sheet
V
V
f
= 36V
EN
V
IN
V
IN
= 5V
OUT
= 700kHz
LOAD = 5Ω
SW
OUT
3
1
SYNC/MODE = VCC
V
V
f
= 24V
IN
V
= 5V
OUT
OUT
= 700kHz
LOAD = 5Ω
SW
3
SYNC/MODE = 700kHz
SW
SS
1
2
2
B
B
B
CH1 2.00V
CH3 10.0V
CH2 20.0V
M400µs
41.80%
A
CH3 6.00V
CH1 2.00V
CH3 5.00V
CH2 10.0V
M1.00ms
50.00%
A CH3 2.00V
W
W
W
W
B
T
T
Figure 46. Shutdown with VIN, PWM Mode, VIN = 36 V, VOUT = 5 V,
fSW = 700 kHz, Load = 5 Ω, SYNC/MODE = VCC
Figure 49. Shutdown with Precision Enable, VIN = 24 V, VOUT = 5 V,
fSW = 700 kHz, Load = 5 Ω, SYNC/MODE = 700 kHz
110
200
160
120
80
EN
90
70
3
V
V
f
= 24V
= 5V
= 700kHz
IN
V
OUT
OUT
50
SW
NO LOAD
30
40
SYNC/MODE = 700kHz
1
10
0
–10
–30
–50
–70
–90
–40
–80
–120
–160
–200
SS
CROSSOVER = 58kHz: 1/12fSW
PHASE MARGIN = 55°
V
V
f
= 24V
IN
= 5V
OUT
2
= 700kHz
LOAD = 1A
SW
B
CH1 2.00V
CH3 5.00V
CH2 10.0V
M1.00ms
9.60%
A CH3 2.00V
W
W
1
10
FREQUENCY (kHz)
100
B
T
Figure 47. Startup with Precision Enable, VIN = 24 V, VOUT = 5 V, fSW = 700 kHz,
Load = No Load, SYNC/MODE = 700 kHz
Figure 50. Magnitude and Phase vs. Frequency
EN
3
V
V
f
= 24V
= 5V
= 700kHz
IN
V
OUT
OUT
SW
LOAD = 5Ω
SYNC/MODE = 700kHz
1
SS
2
B
B
CH1 2.00V
CH3 5.00V
CH2 10.0V
M1.00ms
9.80%
A CH3 2.40V
W
W
T
Figure 48. Startup with Precision Enable,
VIN = 24 V, VOUT = 5 V, fSW = 700 kHz, Load = 5 Ω, SYNC/MODE = 700 kHz
Rev. B | Page 14 of 36
Data Sheet
ADP2442
INTERNAL BLOCK DIAGRAM
AGND
VIN
VCC
INTERNAL LDO
BST
EN
UVLO
+
1.25V
BAND GAP
REFERENCE
SYNC
OSC
FREQ
ENABLE
CLOCK
COMP
POWER STAGE
I
SS
PULSE SKIP ENABLE
+
PULSE SKIP
ENABLE
NMOS
FB
–
+
STATE MACHINE GATE
CONTROL LOGIC
COMP
THRESHOLD
1V
SW
SS
+
VCC
+
–
PWM
V
= 0.6V
REF
NMOS
PWM
COMPARATOR
PGND
HICCUP
HICCUP
TIMER
–
+
SLOPE
COMPENSATION/
RAMP
GENERATOR
CURRENT SENSE
AMPLIFIER
PGOOD
CURRENT
115% OF
FEEDBACK
LIMIT
COMPARATOR
REFERENCE
CURRENT
V
FB
86% OF
FEEDBACK
Figure 51. Internal Block Diagram
Rev. B | Page 15 of 36
ADP2442
Data Sheet
THEORY OF OPERATION
V
IN
The ADP2442 is a fixed frequency, current mode control, step-
down, synchronous switching regulator that is capable of driving
1 A loads. The device operates with a wide input voltage range
from 4.5 V to 36 V, and its output is adjustable from 0.6 V to
0.9 V × VIN. The integrated high-side N-channel power MOSFET
and the low-side N-channel power MOSFET yield high efficiency
at medium to heavy loads. Pulse skip mode is available to improve
efficiency at light loads.
CLOCK
VC
S
R
Q
Q
V
OUT
COMP
PWM DRIVER
I
L
COMPARATOR
R
× I
L
SWL
REF
RAMP
EMULATION
BLOCK
V
RAMP
gM
V
FB
SENSE_
OUT
The ADP2442 includes programmable features, such as output
voltage, switching frequency, and power good. These features
are programmed externally via tiny resistors and capacitors. The
ADP2442 also includes protection features, such as UVLO with
hysteresis, output short-circuit protection, and thermal shutdown.
G
CS
Figure 52. Control Architecture Block Diagram
Pulse Skip Mode
The ADP2442 pulse skip mode is enabled by connecting the
SYNC/MODE pin to AGND. In this mode, the pulse skip circuitry
turns on during light loads, switching only as necessary to keep the
output voltage within regulation. This mode allows the regulator to
maintain high efficiency during operation with light loads by
reducing switching losses. The pulse skip circuitry includes a
comparator, which compares the COMP voltage to a fixed pulse
skip threshold.
CONTROL ARCHITECURE
The ADP2442 is based on an emulated peak current mode control
architecture. The ADP2442 can operate in both fixed frequency
and pulse skip modes.
Fixed Frequency Mode
A basic block diagram of the control architecture is shown in
Figure 52. The ADP2442 can be configured in fixed frequency
mode. The output voltage, VOUT, is sensed on the feedback pin, FB.
An error amplifier integrates the error between the feedback
voltage (VFB) and the reference voltage (VREF = 0.6 V) to generate
an error voltage at the COMP pin.
COMP
CONTROL
LOGIC
PULSE SKIP
THRESHOLD
ADP2442
DC
1V
A current sense amplifier senses the valley inductor current (IL)
during the off period when the low-side power MOSFET is on
and the high-side power MOSFET is off. An internal oscillator
initiates a pulse-width modulation (PWM) pulse to turn off the
low-side power MOSFET and turn on the high-side power
MOSFET at a fixed switching frequency.
Figure 53. Pulse Skip Comparator
With light loads, the output voltage discharges at a very slow rate
(load dependent). When the output voltage is within regulation,
the device enters sleep mode and draws a very small quiescent
current. As the output voltage drops below the regulation voltage,
the COMP voltage rises above the pulse skip threshold. The
device wakes up and begins switching until the output voltage
is within regulation.
When the high-side N-channel power MOSFET is enabled, the
valley inductor current information is added to an emulated
ramp signal and the PWM comparator compares this value to
the error voltage on the COMP pin. The output of the PWM
comparator modulates the duty cycle by adjusting the trailing
edge of the PWM pulse that turns off the high-side power
MOSFET and turns on the low-side power MOSFET.
As the load increases, the settling value of the COMP voltage
increases. At a particular load, COMP settles above the pulse
skip threshold, and the device enters the fixed frequency mode.
Therefore, the load current at which COMP exceeds the pulse
skip threshold is defined as the pulse skip current threshold; the
value varies with the duty cycle and the inductor ripple current.
Slope compensation is programmed internally into the emulated
ramp signal and is automatically selected, depending on the
input voltage, output voltage, and switching frequency. This
prevents subharmonic oscillations for near or greater than 50%
duty cycle operation. The one restriction of this feature is that
the inductor ripple current must be set between 0.2 A and 0.5 A
to provide sufficient current information to the loop.
The measured value of pulse skip threshold over VIN is shown in
Figure 19, Figure 20, and Figure 21.
Rev. B | Page 16 of 36
Data Sheet
ADP2442
ADJUSTABLE FREQUENCY
EXTERNAL SYNCHRONIZATION
The ADP2442 features a programmable oscillator frequency with
a resistor connected between the FREQ and AGND pins.
The external synchronization feature allows the switching
frequency of the device to be synchronized to an external clock.
The SYNC/MODE input accepts a logic level clock input ranging
from 300 kHz to 1 MHz (minimum pulse width = 100 ns) and has
high input impedance. For best practices, it is recommended
that the set frequency (set by the resistor at the FREQ pin) be
within 30% of the expected clock frequency to ensure stable,
reliable, and seamless operation with or without an external
SYNC/MODE clock. When the ADP2442 is synchronized to an
external clock, the regulator switching frequency changes to the
external clock frequency.
At power-up, the FREQ pin is forced to 1.2 V and current flows
from the FREQ pin to AGND; the current value is based on the
resistor value on the FREQ pin. Next, the same current replicates in
the oscillator to set the switching frequency. Note that the resistor
connected to the FREQ pin must be placed as close as possible
to the FREQ pin (see the Applications Information section for
more information).
POWER GOOD
The PGOOD pin is an open-drain output that indicates the
status of the output voltage. When the voltage of the FB pin
is between 92% and 109% of the internal reference voltage,
the PGOOD output pulls high, provided there is a pull-up resistor
connected to the pin. When the voltage of the FB pin is not
within this range, the PGOOD output pulls low to AGND. The
PGOOD threshold is shown in Figure 54.
SOFT START
The ADP2442 has an internal soft start feature that allows the
output voltage to ramp up in a controlled manner, limiting the
inrush current during startup. The ADP2442 internal soft start
time is 2 ms.
EN
Likewise, the PGOOD pin is pulled low to AGND when
V
V
f
= 24V
= 5V
= 700kHz
INTERNAL SS TIME
2.18ms
3
1
IN
The input voltage is below the internal UVLO threshold.
The EN pin is low.
A thermal shutdown event has occurred.
V
OUT
OUT
SW
LOAD = NO LOAD
SYNC/MODE = AGND
SS
V
FALLING
V
RISING
OUT
OUT
116
110
100
100
90
2
84
B
B
CH1 2.00V
CH3 5.00V
CH2 10.0V
M1.00ms
26.00%
A CH1 3.44V
W
W
T
Figure 55. Internal Soft Start
UNDERVOLTAGE
POWER
GOOD
POWER
GOOD
UNDERVOLTAGE
OVERVOLTAGE
UNDERVOLTAGE LOCKOUT
The undervoltage lockout (UVLO) function prevents the IC
from turning on when the input voltage is below the specified
operating range to avoid an undesired operating mode. If the
input voltage drops below the specified range, the UVLO function
shuts off the device. The rising input voltage threshold for the
UVLO function is 4.2 V with 200 mV hysteresis. The 200 mV of
hysteresis prevents the regulator from turning on and off repeatedly
when there is a slow voltage ramp on the VIN pin.
PGOOD
Figure 54. PGOOD Threshold
In a typical application, a pull-up resistor connected between the
PGOOD pin and an external supply is used to generate a logic
signal. This pull-up resistor must range in value from 30 kΩ to
100 kΩ, and the external supply must be less than 5.5 V.
MODE OF OPERATION
The SYNC/MODE pin is a multifunctional pin. The fixed
frequency mode is enabled when SYNC/MODE is connected to
VCC or a high logic. When SYNC/MODE connects to AGND,
pulse skip mode enables. The external clock can be applied for
synchronization.
PRECISION ENABLE/SHUTDOWN
The ADP2442 features a precision enable pin (EN) to enable or
shutdown the device. The 5% accuracy lends itself to using a
resistor divider from the VIN pin (or another external supply) to
program a desired UVLO threshold that is higher than the fixed
internal UVLO of 4.2 V. The hysteresis is 100 mV.
Table 5. SYNC/MODE Pin Mode of Operation
SYNC/MODE Pin
Mode of Operation
If a resistor divider is not used, apply a logic signal instead. A
logic high enables the device, and a logic low forces the device
into shutdown mode.
Low
High
Clock Signal
Pulse skip mode
Forced fixed frequency mode
Forced fixed frequency mode
Rev. B | Page 17 of 36
ADP2442
Data Sheet
If the output is overloaded and the peak inductor current exceeds
the preset current limit for more than eight consecutive clock
cycles, the hiccup mode current-limit condition occurs. The
output goes to sleep for 6 ms, during which time the output
discharges, the average power dissipation reduces, and the device
wakes up with a soft start period. If the current-limit condition
is triggered again, the output goes to sleep and wakes up after 6 ms.
Figure 37 shows the current-limit hiccup mode when the output is
shorted to ground.
V
VIN
BST
IN
V
OUT
SW
FB
ADP2442
R1
R2
EN
FREQ AGND COMP
THERMAL SHUTDOWN
Figure 56. Precision Enable Used as a Programmable UVLO
If the ADP2442 junction temperature rises above 150°C, the
thermal shutdown circuit turns off the switching regulator. Extreme
junction temperatures can be the result of high current operation,
poor circuit board design, or high ambient temperature. A 25°C
hysteresis is included so that when a thermal shutdown occurs,
the ADP2442 does not return to normal operation until the
junction temperature drops below 125°C. Soft start is active
upon each restart cycle.
CURRENT-LIMIT AND SHORT-CIRCUIT PROTECTION
The ADP2442 has a current-limit comparator that compares the
current sensed across the low-side power MOSFET to the
internally set reference current. If the sensed current exceeds the
reference current, the high-side power MOSFET does not turn
on in the next cycle and the low-side power MOSFET stays on until
the inductor current ramps down below the current-limit level.
Rev. B | Page 18 of 36
Data Sheet
ADP2442
APPLICATIONS INFORMATION
ADIsimPOWER DESIGN TOOL
Table 6. Output Voltage Selection
The ADP2442 is supported by the ADIsimPower design tool
set. ADIsimPower is a collection of tools that produce complete
power designs optimized to a specific design goal. These tools
allow the user to generate a full schematic, bill of materials, and
calculate performance in minutes. ADIsimPower can optimize
designs for cost, area, efficiency, and device count while taking
into consideration the operating conditions and limitations of
the IC and all real external components. Find the ADIsimPower
tool at www.analog.com/adisimpower and the user can request an
unpopulated board through the tool.
Voltage (V)
RTOP (kΩ)
RBOTTOM (kΩ)
12
5
3.3
1.2
190
73
45
10
10
10
10
10
SETTING THE SWITCHING FREQUENCY
The choice of the switching frequency depends on the required
dc-to-dc conversion ratio and is limited by the minimum and
maximum controllable duty cycle, as shown in Figure 58. This
limitation is due to the requirement of minimum on time and
minimum off time for current sensing and robust operation.
However, the choice is also influenced by whether there is a need
for small external components. For example, higher switching
frequencies are required for small, area limited power solutions.
100
SELECTING THE OUTPUT VOLTAGE
The output voltage is set using a resistor divider connected between
the output voltage and the FB pin (see Figure 57). The resistor
divider divides down the output voltage to the 0.6 V FB regulation
voltage. The output voltage can be set to as low as 0.6 V and as
high as 90% of the power input voltage.
90
D
MAX
V
OUT
80
70
60
50
40
30
20
10
0
ADP2442
R
TOP
FB
R
BOTTOM
PGOOD
FREQ
R
FREQ
EXTERNAL
SUPPLY
D
MIN
Figure 57. Voltage Divider
0
200
400
600
800
1000
1200
The ratio of the resistive voltage divider sets the output voltage, and
the absolute value of the resistors sets the divider string current.
When calculating the resistor values for lower divider string
currents, take into account the small 50 nA (0.1 μA maximum)
FB bias current. The FB bias current can be ignored for a higher
divider string current; however, using small feedback resistors
degrades efficiency at very light loads.
FREQUENCY (kHz)
Figure 58. Duty Cycle vs. Switching Frequency
Calculate the value of the frequency resistor by using the
following equation:
92,500
fSW
RFREQ
=
(3)
To limit degradation of the output voltage accuracy due to FB
bias current to less than 0.005% (0.5% maximum), ensure that
the divider string current is greater than 20 μA. To calculate the
desired resistor values, first determine the value of the bottom
resistor, RBOTTOM, as follows:
where RFREQ is in kΩ and fSW is in kHz.
Table 7 and Figure 59 provide examples of frequency resistor
values that are based on the switching frequency.
Table 7. Frequency Resistor Selection
VREF
ISTRING
RFREQ
Frequency
300 kHz
700 kHz
1 MHz
RBOTTOM
=
(1)
308 kΩ
132 kΩ
92.5 kΩ
where:
REF is the internal reference and equals 0.6 V.
STRING is the resistor divider string current.
Next, calculate the value of the top resistor, RTOP, as follows:
V
I
VOUT −VREF
(2)
RTOP = RBOTTOM
×
VREF
Rev. B | Page 19 of 36
ADP2442
Data Sheet
1200
1100
1000
900
800
700
600
500
400
300
Inductor Selection
The high switching frequency of the ADP2442 allows for minimal
output voltage ripple even when small inductors are used. Selecting
the size of the inductor involves considering the trade-off between
efficiency and transient response. A smaller inductor results in
larger inductor current ripple, which provides excellent transient
response; however, it degrades efficiency. Because of the high
switching frequency of the ADP2442, use shielded ferrite core
inductors for their low core losses and low EMI.
The inductor ripple current also affects the stability of the loop
because the ADP2442 uses the emulated peak current mode
architecture. In the traditional approach of slope compensation,
the user sets the inductor ripple current and then sets the slope
compensation using an external ramp resistor. In most cases, the
inductor ripple current is typically set to be 1/3 of the maximum
load current for optimal transient response and efficiency. The
ADP2442 has internal slope compensation, which assumes that
the inductor ripple current is set to 0.3 A (30% of the maximum
load of 1 A), eliminating the need for an external ramp resistor.
200
50
100
150
200
250
300
350
RESISTANCE (kΩ)
Figure 59. Frequency vs. Resistor
EXTERNAL COMPONENT SELECTION
Input Capacitor Selection
The input current to a buck regulator is pulsating in nature. The
current is zero when the high-side switch is off and is
For the ADP2442, choose an inductor such that the peak-to-peak
ripple current of the inductor is between 0.2 A and 0.5 A for
stable operation. Calculate the inductor value as follows:
approximately equal to the load current when the switch is on.
Because switching occurs at reasonably high frequencies (300 kHz
to 1 MHz), the input bypass capacitor usually supplies most of
the high frequency current (ripple current), allowing the input
power source to supply only the average (dc) current. The input
capacitor needs a sufficient ripple current rating to handle the
input ripple and needs an ESR that is low enough to mitigate the
input voltage ripple. In many cases, different types of capacitors
are placed in parallel to minimize the effective ESR and ESL.
VOUT ×(VIN −VOUT
VIN × fSW × L
)
∆IL
=
(6)
0.2 A ≤ ΔIL ≤ 0.5 A
2×VOUT ×(VIN −VOUT
VIN × fSW
)
5×VOUT ×(VIN −VOUT
VIN × fSW
)
≤ L ≤
The minimum input capacitance required for a particular load is
3.3×VOUT ×(VIN −VOUT
)
LIDEAL
=
(7)
I
OUT × D ×(1− D)
CIN _ MIN
=
(4)
V
IN × fSW
(VPP − IOUT × D × RESR ) fSW
where:
VIN is the input voltage.
OUT is the desired output voltage.
SW is the regulator switching frequency.
L is the inductor value.
ΔIL is the peak-to-peak inductor ripple current.
where:
VPP is the desired input ripple voltage.
ESR is the equivalent series resistance of the capacitor.
OUT is the maximum load current.
D is the duty cycle.
SW is the switching frequency.
For best practice, use a ceramic bypass capacitor because the
V
f
R
I
f
L
IDEAL is the ideal calculated inductor value.
For applications with a wide input (VIN) range, choose the
inductor based on the geometric mean (VIN (GEOMETRIC)) of the
input voltage extremes.
ESR associated with this type of capacitor is near zero, simplifying
the equation to
I
OUT ×D ×(1− D)
CIN _ MIN
=
(5)
VIN(GEOMETRIC) = VIN _ MAX ×VIN _ MIN
(8)
(9)
VPP × fSW
where:
In addition, use a ceramic capacitor with a voltage rating that is
1.5 times the input voltage with X5R and X7R dielectrics. Using
Y5V and Z5U dielectrics is not recommended because of their
poor temperature and dc bias characteristics. Table 10 shows a list
of recommended MLCC capacitors.
V
V
IN_MAX is the maximum input voltage.
IN_MIN is the minimum input voltage.
The inductor value is based on VIN (GEOMETRIC) as follows:
3.3×VOUT ×(VIN(GEOMETRIC) −VOUT
VIN(GEOMETRIC) × fSW
)
LIDEAL
=
For large step load transients, add more bulk capacitance by
using electrolytic or polymer capacitors. Ensure that the ripple
current rating of the bulk capacitor exceeds the minimum input
ripple current of a particular design.
Rev. B | Page 20 of 36
Data Sheet
ADP2442
Table 8. Inductor Values for Various VIN, VOUT, and fSW
Table 10. Recommended Output Capacitors
Combinations
Vendor
Inductor Values
Capacitor
10 μF/25 V
22 μF/25 V
47 μF/6.3 V GCM32ER70J476KE19L
4.7 μF/50 V GRM31CR71H475KA12L
Murata
Taiyo Yuden
fSW (kHz)
300
300
300
300
300
300
300
300
600
600
600
600
600
600
600
VIN (V)
12
12
24
24
24
36
36
36
12
12
24
24
24
36
36
12
24
24
36
VOUT (V)
3.3
5
3.3
5
12
3.3
5
12
3.3
5
3.3
5
12
3.3
5
Min (μH)
22
Max (μH)
27
GRM32DR71E106KA12L
GRM32ER71E226KE15L
TMK325B7106KN-TR
TMK325B7226MM-TR
JMK325B7476MM-TR
UMK325B7475MMT
27
27
33
33
39
56
27
47
68
33
For acceptable maximum output voltage ripple, determine the
minimum output capacitance, COUT (MIN), as follows:
39
68
12
47
82
15
1
(11)
VRIPPLE IL ESR
8 fSW COUT (MIN )
Therefore,
OUT(MIN)
15
15
18
27
18
18
22
33
IL
C
(12)
8 fSW (VRIPPLE IL ESR)
15
18
where:
22
6.8
10
27
10
12
ΔVRIPPLE is the allowable peak-to-peak output voltage ripple.
ΔIL is the inductor ripple current.
ESR is the equivalent series resistance of the capacitor.
1000
1000
1000
1000
5
5
12
5
18
22
fSW is the switching frequency of the regulator.
12
15
When there is a step load requirement, choose the output
capacitor value based on the value of the step load. Use the
following equation to determine the maximum acceptable
output voltage droop/overshoot caused by the step load:
To avoid inductor saturation and ensure proper operation, choose
the inductor value so that neither the saturation current nor the
maximum temperature rated current ratings are exceeded.
Inductor manufacturers specify both of these ratings in data
sheets, or the rating can be calculated as follows:
3
(13)
COUT ( MIN ) IOUT (STEP )
fSW VDROOP
I L
2
(10)
I L _ PEAK I LOAD
( MAX )
where:
ΔIOUT (STEP) is the load step.
SW is the switching frequency of the regulator.
where:
LOAD (MAX) is the maximum dc load current.
ΔIL is the peak-to-peak inductor ripple current.
L_PEAK is the peak inductor current.
f
I
ΔVDROOP is the maximum allowable output voltage droop/overshoot.
Select the larger of the output capacitances derived from
Equation 12 and Equation 13. When choosing the type of ceramic
capacitor for the output filter of the regulator, select a capacitor
with a nominal capacitance that is 20% to 30% larger than the
calculated value because the effective capacitance degrades with dc
voltage and temperature. Figure 60 shows the capacitance loss
resulting from the dc bias voltage for two capacitors (X7R MLCC
capacitors from Murata are shown in Figure 60).
I
Table 9. Recommended Inductors
Small Inductors
Value (μH) (<10 mm × 10 mm)
Large Inductors
(>10 mm × 10 mm)
10
18
33
15
XAL4040-103ME
LPS6235-183ML
LPS6235-33ML
XAL4040-153ME
MSS1260
MSS1260
MSS1260
MSS1260
Output Capacitor Selection
The output capacitor selection affects both the output voltage
ripple and the loop dynamics of the regulator. The ADP2442 is
designed to operate with small ceramic output capacitors that
have low ESR and ESL; therefore, the device easily meets tight
output voltage ripple specifications. For best performance, use
X5R or X7R dielectric capacitors with a voltage rating that is
1.5 times the output voltage and avoid using Y5V and Z5U
dielectric capacitors, which have poor temperature and dc bias
characteristics. Table 10 lists recommended capacitors from
Murata and Taiyo Yuden.
Rev. B | Page 21 of 36
ADP2442
Data Sheet
30.0
LOOP COMPENSATION
The ADP2442 uses a peak current mode control architecture for
excellent load and line transient response. This control architecture
has two loops: an inner current loop and an external voltage loop.
24.6
19.2
13.8
8.40
The inner current loop senses the current in the low-side switch
and controls the duty cycle to maintain the average inductor
current. To ensure stable operation when the duty cycle is above
50%, slope compensation is added to the inner current loop.
22µF/25V
10µF/25V
The external voltage loop senses the output voltage and adjusts
the duty cycle to regulate the output voltage to the desired value. A
transconductance amplifier with an external series RC network
connected to the COMP pin compensates for the external
voltage loop, as shown in Figure 61.
3.00
0
5
10
15
20
25
DC BIAS VOLTAGE (V)
Figure 60. Capacitance vs. DC Voltage
ADP2442
For example, to attain 20 μF of output capacitance with an output
voltage of 5 V while providing some margin for temperature
variation, use a 22 μF capacitor with a voltage rating of 25 V
and a 10 μF capacitor with a voltage rating of 25 V in parallel.
This configuration ensures that the output capacitance is sufficient
under all conditions and, therefore, that the device exhibits
stable behavior.
COMP
VFB
R
C
COMP
gm
0.6V
COMP
AGND
BOOST CAPACITOR
The boost pin (BST) is used to power up the internal driver for the
high-side power MOSFET. In the ADP2442, the high-side power
MOSFET is an N-channel device to achieve high efficiency in
mid and high duty cycle applications. To power up the high-side
driver, a capacitor is required between the BST and SW pins.
The size of this boost capacitor is critical because it affects the
light load functionality and efficiency of the device. Therefore,
choose a boost ceramic capacitor with a value between 10 nF
and 22 nF with a voltage rating of 50 V, placing the capacitor as
close as possible to the IC. It is recommended to use a boost
capacitor within this range because a capacitor beyond 22 nF
can cause the LDO to reach the current-limit threshold.
Figure 61. RC Compensation Network
LARGE SIGNAL ANALYSIS OF THE LOOP
COMPENSATION
The control loop can be broken down into the following three
sections:
•
•
•
VOUT to VCOMP
COMP to IL
V
IL to VOUT
V
IN
VCC CAPACITOR
INDUCTOR
CURRENT
SENSE
The ADP2442 has an internal regulator to power up the internal
controller and the low-side driver. The VCC pin is the output of
the internal regulator. The internal regulator provides the pulse
current when the low-side driver turns on. Therefore, it is
recommended to place a 1 µF ceramic capacitor between the
VCC and PGND pins as close as possible to the IC and place a
1 µF ceramic capacitor between the VCC and AGND pins.
PULSE-WIDTH
MODULATOR
I
L
V
OUT
C
OUT
R
LOAD
V
COMP
g
G
m
V
= 0.6V
REF
ADP2442
R
C
COMP
COMP
Figure 62. Large Signal Model
Rev. B | Page 22 of 36
Data Sheet
ADP2442
Correspondingly, there are three transfer functions:
At the crossover frequency, the gain of the open-loop transfer
function is unity.
V
V
COMP (s) VREF
OUT (s) VOUT
=
× gm × ZCOMP (s)
(14)
(15)
(16)
H(fCROSSOVER) = 1
(20)
This yields Equation 21 for the RC compensation network
impedance at the crossover frequency.
IL (s)
COMP (s)
= GCS
V
2×π × fCROSSOVER ×COUT VOUT
Z
COMP ( fCROSSOVER ) =
×
V
IL (s)
OUT (s)
gm ×GCS
VREF
= ZFILT (s)
(21)
(22)
Placing s = fCROSSOVER in Equation 17,
where:
COMP is the comparator voltage.
1+2×π × fCROSSOVER ×RCOMP ×CCOMP
2×π × fCROSSOVER ×CCOMP
V
Z
COMP ( fCROSSOVER) =
IL is the inductor current.
gm is the transconductance of the error amplifier and equals
250 µA /V.
GCS is the current sense gain and equals 2 A /V.
To ensure that there is sufficient phase margin at the crossover
frequency, place the compensator zero at 1/8 of the crossover
frequency, as shown in the following equation:
VOUT is the output voltage of the regulator.
fCROSSOVER
1
V
REF is the internal reference voltage and equals 0.6 V.
fZERO
=
≈
(23)
ZCOMP(s) is the impedance of the RC compensation network that
2×π ×RCOMP ×CCOMP
8
forms a pole at the origin and a zero, as expressed in Equation 17.
Solving Equation 21, Equation 22, and Equation 23 yields the
values for the resistor and capacitor in the RC compensation
network, as shown in Equation 24 and Equation 25.
1+ s×RCOMP ×CCOMP
ZCOMP (s) =
(17)
s×CCOMP
2× π× fCROSSOVER
C
OUT ×VOUT
VREF
Z
FILT(s) is the impedance of the output filter and is expressed as
RCOMP = 0.9×
×
(24)
(25)
g
m ×GCS
RLOAD
Z
FILT (s) =
(18)
1+ s×RLOAD ×COUT
1
CCOMP
=
2× π× fZERO × RCOMP
where s is the angular frequency, which can be written as s = 2πf.
Using these equations allows calculating the compensations for
the voltage loop.
Obtain the overall loop gain, H(s), by multiplying the three
transfer functions previously mentioned as follows:
VREF
VOUT
H(s) = gm ×GCS
×
× ZCOMP (s)× ZFILT (s)
(19)
When the switching frequency (fSW), output voltage (VOUT),
output inductor (L), and output capacitor (COUT) values are
selected, the unity crossover frequency can be set to 1/12 of the
switching frequency.
Rev. B | Page 23 of 36
ADP2442
Data Sheet
DESIGN EXAMPLE
Consider an application with the following specifications:
Inductor Selection
Select the inductor by using Equation 7.
•
•
•
•
•
•
VIN: 24 V 10%
OUT: 5 V 1%
Switching frequency: 700 kHz
Load: 800 mA typical
Maximum load current: 1 A
Overshoot ≤ 2% under all load transient conditions
V
3.3×VOUT ×(VIN −VOUT
VIN × fSW
)
LIDEAL
=
=
3.3×5 V×(24 −5) V
24 V×700 kHz
LIDEAL
=18.66μH ≈18.3μH
In Equation 7, VIN = 24 V, VOUT = 5 V, ILOAD (MAX) = 1 A, and fSW
700 kHz, which results in L = 18.66 µH. When L = 18 μH (the
closest standard value) in Equation 6, ΔIL = 0.314 A. Although
the maximum output current that is required is 1 A, the maximum
peak current is 1.6 A. Therefore, the inductor must be rated for
higher than 1.6 A current.
=
CONFIGURATION AND COMPONENTS SELECTION
Resistor Divider
The first step in selecting the external components is to
calculate the resistance of the resistor divider that sets the
output voltage.
Using Equation 1 and Equation 2,
Input Capacitor Selection
VREF
ISTRING 60 μA
0.6
The input filter consists of a small 0.1 µF ceramic capacitor
placed as close as possible to the IC.
RBOTTOM
=
=
=10 kΩ
The minimum input capacitance required for a particular load is
VOUT −VREF
RTOP = RBOTTOM
×
I
OUT ×D×(1− D)
VREF
CIN _ MIN
=
VPP × fSW
5 V −0.6 V
RTOP =10 kΩ×
= 73.3 kΩ
where:
VPP = 50 mV.
OUT = 1 A.
D = 0.23.
SW = 700 kHz.
Therefore,
0.6 V
Switching Frequency
I
Choosing the switching frequency involves consideration of the
trade-off between efficiency and component size. Low frequency
improves the efficiency by reducing the gate losses but requires
a large inductor. The choice of high frequency is limited by the
minimum and maximum duty cycle.
f
1 A ×0.22×(1− 0.22)
0.05 V ×700 kHz
CIN _ MIN
=
≈ 4.9 μF
Table 11. Duty Cycle
Choosing an input capacitor of 10 µF with a voltage rating of
50 V ensures sufficient capacitance over voltage and temperature.
VIN
Duty Cycle
DNOMINAL = 20.8%
DMIN = 19%
24 V (Nominal)
26 V (10% Above Nominal)
22 V (10% Less than Nominal)
Output Capacitor Selection
DMAX = 23%
Select the output capacitor by using Equation 12 and Equation 13
Based on the estimated duty cycle range, choose the switching
frequency according to the minimum and maximum duty cycle
limitations, as shown in Figure 58. For example, a 700 kHz,
frequency is well within the maximum and minimum duty
cycle limitations.
∆IL
COUT (MIN)
≅
8× fSW ×(∆VRIPPLE − ∆IL ×ESR)
Equation 12 is based on the output voltage ripple (ΔVRIPPLE),
which is 1% of the output voltage.
Using Equation 3,
92,500
3
COUT (MIN) ≅ ∆IOUT(STEP)
f
SW ×∆VDROOP
RFREQ
=
fSW
FREQ = 132 kΩ
Equation 13 calculates the capacitor selection based on the
transient load performance requirement of 2%. Perform these
calculations, then use the equation that yields the larger capacitor
size to select a capacitor.
R
Rev. B | Page 24 of 36
Data Sheet
ADP2442
In this example, the values listed in Table 12 are substituted for
the variables in Equation 12 and Equation 13.
Selecting the crossover frequency to be 1/12 of the switching
frequency and placing the zero frequency at 1/8 of the crossover
frequency ensures that there is adequate phase margin in
the system.
Table 12. Requirements
Parameter
Test Conditions/Comments
Value
Table 13. Calculated Parameter Value
Ripple Current
Voltage Ripple
Voltage Droop Due
to Load Transient
Fixed at 0.3 A for the ADP2442 0.3 A
Parameter
fCROSSOVER
fZERO
Test Conditions/Comments
Value
1% of VOUT
2% of VOUT
50 mV
100 mV
1/12 of fSW
1/8 of fCROSSOVER
58.3 kHz
7.3 kHz
0.6 V
ESR
fSW
5 mΩ
700 kHz
VREF
gm
Fixed reference
Transconductance of error
amplifier
Current sense gain
Output capacitor
Output voltage
250 μA/V
The calculation based on the output voltage ripple (see
Equation 12) dictates that the minimum output capacitance is
GCS
COUT
VOUT
2 A/V
22 μF
5 V
0.3 A
COUT(MIN )
1.1μF
8700 kHz (50 mV 0.3 A5 mΩ)
Based on the values listed in Table 13, calculate the compen-
sation value:
Whereas the calculation based on the transient load (see
Equation 13) dictates that the minimum output capacitance is
2 58.3 22 5
RCOMP 0.9
121 kΩ
250 2
0.6
3
COUT(MIN) 0.5
22F
The closest standard resistor value is 118 kꢁ. Therefore,
1
700kHz0.1V
To meet both requirements, use the value determined by the
latter equation. As shown in Figure 60, capacitance degrades
with dc bias; therefore, choose a capacitor that is 1.5 times the
calculated value.
CCOMP
185pF180pF
2 7.3118
SYSTEM CONFIGURATION
Configure the system as follows; though the steps are not
sequential, they all must be completed:
COUT = 1.5 × 22 ꢀF = 32 ꢀF
Compensation Selection
Connect a capacitor of 1 ꢀF between the VCC and PGND
pins and another capacitor of 1 ꢀF between the VCC and
AGND pins. For best performance, use ceramic X5R or
X7R capacitors with a 25 V voltage rating.
Connect a ceramic capacitor of 10 nF with a 50 V voltage
rating between the BST and SW pins.
Connect a resistor between the FREQ and AGND pins as
close as possible to the IC.
If using the power-good feature, connect a 50 kꢁ pull-up
resistor to a 5 V external supply.
Calculate the compensation component values for the feedback
loop using the following equations:
2 fCROSSOVER COUT VOUT
RCOMP 0.9
g
m GCS
VREF
1
CCOMP
2 fZERO RCOMP
For synchronization, connect an external clock with a
frequency of 700 kHz to the SYNC/MODE pin. Connect
the external clock to AGND to activate pulse skip mode or
connect it to VCC for forced fixed frequency mode.
See Figure 63 for a schematic of this design example and Table 14
for the calculated component values.
Rev. B | Page 25 of 36
ADP2442
Data Sheet
TYPICAL APPLICATION CIRCUITS
DESIGN EXAMPLE
C3
1µF/25V
V
24V
:
IN
C5
10nF/50V
C4
1µF/25V
C2
4.7µF/
50V
C1
4.7µF/
50V
FB
VIN
L1
V
:
OUT
R5
118kΩ
18.3µH
R3
10kΩ
ADP2442
5V, 1A
COMP
EN
SW
C10
185pF
C6
0.1µF
C7
C8
10µF/
25V
22µF/
25V
PGND
VCC
R2
74kΩ
VCC
R7
50kΩ
PGOOD
R9
132kΩ
CLOCK:
700k±30%
Figure 63. Typical Application Circuit, VIN = 24 V 10%, VOUT = 5 V, fSW = 700 kHz
Table 14. Calculated Component Values for Figure 63
Quantity
Reference
C1, C2
C3, C4
C5
C7
C8
L1
C6
C10
R9
R5
Value
4.7 µF
1 µF
10 nF
22 µF
Description
Part Number
2
2
2
1
1
1
1
1
1
1
1
2
1
Capacitor ceramic, X7R, 50 V
GRM31CR71H475KA12L
GRM188R71E105KA12D
ECJ-1VB1H103K
Capacitor ceramic, 1 µF, 25 V, X7R, 10%, 0603
Capacitor ceramic, 10 nF, 50 V, 10%, X7R, 603
Capacitor ceramic, 22 µF, 25 V, X7R, 1210
Capacitor ceramic, 10 µF, 25 V, X7R, 1210
Inductor
GRM32ER71E226K
10 µF
GRM32DR71E106KA12L
CoilCraft MSS1260T-183NLB
ECJ-2FB1H104K
Determined by user
Determined by user
Determined by user
Determined by user
Determined by user
Determined by user
18.3 µH
0.1 µF
185 pF
132 kΩ
118 kΩ
74 kΩ
10 kΩ
50 kΩ
Capacitor ceramic, 0.1 µF, 50 V, X7R, 0805
Capacitor ceramic, 50 V
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
R2
R3
R7
Rev. B | Page 26 of 36
Data Sheet
ADP2442
OTHER TYPICAL CIRCUIT CONFIGURATIONS
C3
1µF/25V
V
24V
:
IN
C5
10nF/50V
C4
1µF/25V
C2
4.7µF/
50V
C1
4.7µF/
50V
FB
COMP
VIN
L1
33.3µH
V
:
OUT
R5
121kΩ
R3
10kΩ
ADP2442
12V, 1A
SW
C10
220pF
C6
0.1µF
C7
22µF/
25V
EN
PGND
EXT
R2
191kΩ
VCC
R7
50kΩ
PGOOD
R9
154kΩ
CLOCK:
600k±30%
Figure 64. Typical Application Circuit, VIN = 24 V 10%, VOUT = 12 V, fSW = 600 kHz
Table 15. Calculated Component Values for Figure 64
Quantity
Reference
C1, C2
C3, C4
C5
C7
C8
L1
C6
C10
R9
R5
Value
4.7 µF
1 µF
10 nF
22 µF
N/A1
33.3 µH
0.1 µF
220 pF
154 kΩ
121 kΩ
191 kΩ
10 kΩ
50 kΩ
Description
Part Number
2
2
2
1
1
1
1
1
1
1
1
2
1
Capacitor ceramic, X7R, 50 V
Capacitor ceramic, 1 µF, 25 V, X7R, 10%, 0603
Capacitor ceramic, 10000 pF, 50 V, 10%, X7R, 0603
Capacitor ceramic, 22 µF, 25 V, X7R, 1210
N/A1
GRM31CR71H475KA12L
GRM188R71E105KA12D
ECJ-1VB1H103K
GRM32ER71E226K
N/A1
Inductor
CoilCraft MSS1038-333ML
ECJ-2FB1H104K
Capacitor ceramic, 0.1 µF, 50 V, X7R, 0805
Capacitor ceramic, 50 V
Determined by user
Determined by user
Determined by user
Determined by user
Determined by user
Determined by user
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
R2
R3
R7
1 N/A means not applicable.
Rev. B | Page 27 of 36
ADP2442
Data Sheet
C3
1µF/25V
V
12V
:
IN
C5
10nF/50V
C4
1µF/25V
C2
4.7µF/
50V
C1
4.7µF/
50V
FB
VIN
L1
V
:
OUT
R5
118kΩ
18.3µH
R3
10kΩ
ADP2442
5V, 1A
COMP
EN
SW
C10
270pF
C6
0.1µF
C7
C8
22µF/
25V
22µF/
25V
PGND
EXT
R2
74kΩ
VCC
R7
50kΩ
PGOOD
R9
185kΩ
CLOCK:
500k±30%
Figure 65. Typical Application Circuit, VIN = 12 V 10%, VOUT = 5 V, fSW = 500 kHz
Table 16. Calculated Component Values for Figure 65
Quantity
Reference
C1, C2
C3, C4
C5
C7
C8
L1
C6
C10
R9
R5
Value
4.7 µF
1 µF
10 nF
22 µF
Description
Part Number
2
2
2
1
1
1
1
1
1
1
1
1
1
Capacitor ceramic, X7R, 50 V
GRM31CR71H475KA12L
GRM188R71E105KA12D
ECJ-1VB1H103K
Capacitor ceramic, 1 µF, 25 V, X7R, 10%, 0603
Capacitor ceramic, 10 nF, 50 V, 10%, X7R, 0603
Capacitor ceramic, 22 µF, 25 V, X7R, 1210
Capacitor ceramic, 22 µF, 25 V, X7R, 1210
Inductor
GRM32ER71E226K
22 µF
Determined by user
CoilCraft MSS1038-183ML
ECJ-2FB1H104K
Determined by user
Determined by user
Determined by user
Determined by user
Determined by user
Determined by user
18.3 µH
0.1 µF
270 pF
185 kΩ
118 kΩ
74 kΩ
10 kΩ
50 kΩ
Capacitor ceramic, 0.1 µF, 50 V, X7R, 0805
Capacitor ceramic, 50 V
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
R2
R3
R7
Rev. B | Page 28 of 36
Data Sheet
ADP2442
C3
1µF/25V
V
36V
:
IN
C5
10nF/50V
C4
1µF/25V
C2
4.7µF/
50V
C1
4.7µF/
50V
FB
VIN
L1
V
:
OUT
R5
91kΩ
33.3µH
R3
10kΩ
3.3V, 1A
ADP2442
COMP
EN
SW
C10
560pF
C6
0.1µF
C7
C8
47µF/
6.3V
47µF/
6.3V
PGND
EXT
R2
45kΩ
VCC
R7
50kΩ
PGOOD
R9
300kΩ
CLOCK:
300k±30%
Figure 66. Typical Application Circuit, VIN = 36 V 10%, VOUT = 3.3 V, fSW = 300 kHz
Table 17. Calculated Component Values for Figure 66
Quantity
Reference
C1, C2
C3, C4
C5
C7
C8
L1
C6
C10
R9
R5
Value
4.7 µF
1 µF
Description
Part Number
2
2
2
1
1
1
1
1
1
1
1
1
1
Capacitor ceramic, X7R, 50 V
GRM31CR71H475KA12L
GRM188R71E105KA12D
ECJ-1VB1H103K
GRM32ER70J476KE20L
GRM32ER70J476KE20L
CoilCraft MSS1038T-333ML
ECJ-2FB1H104K
Determined by user
Determined by user
Determined by user
Determined by user
Determined by user
Determined by user
Capacitor ceramic, 1 µF, 25 V, X7R, 10%, 0603
Capacitor ceramic, 10 nF, 50 V, 10%, X7R, 0603
Capacitor ceramic, 47 µF, 6.3 V, X7R, 1210
Capacitor ceramic, 47 µF, 6.3 V, X7R, 1210
Inductor
10 nF
47 µF
47 µF
33.3 µH
0.1 µF
560 pF
300 kΩ
91 kΩ
45 kΩ
10 kΩ
50 kΩ
Capacitor ceramic, 0.1 µF, 50 V, X7R, 0805
Capacitor ceramic, 50 V
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
R2
R3
R7
Rev. B | Page 29 of 36
ADP2442
Data Sheet
C3
1µF/25V
V
24V
:
IN
C5
10nF/50V
C4
1µF/25V
C2
4.7µF/
50V
C1
4.7µF/
50V
FB
VIN
L1
V
:
OUT
R5
115kΩ
12.3µH
R3
10kΩ
ADP2442
3.3V, 1A
COMP
EN
SW
C10
190pF
C6
0.1µF
C7
C8
10µF/
16V
22µF/
16V
PGND
EXT
R2
45.3kΩ
VCC
R7
50kΩ
PGOOD
R9
132kΩ
CLOCK:
700k±30%
Figure 67. Typical Application Circuit, VIN = 24 V 10%, VOUT = 3.3 V, fSW = 700 kHz
Table 18. Calculated Component Values for Figure 67
Quantity
Reference
C1, C2
C3, C4
C5
C7
C8
L1
C6
C10
R9
R5
Value
4.7 µF
1 µF
10 nF
22 µF
Description
Part Number
2
2
2
1
1
1
1
1
1
1
1
1
1
Capacitor ceramic, X7R, 50 V
GRM31CR71H475KA12L
GRM188R71E105KA12D
ECJ-1VB1H103K
GRM32ER71C226KEA8L
GRM32DR71E106KA12L
CoilCraft MSS1038T-123ML
ECJ-2FB1H104K
Determined by user
Determined by user
Determined by user
Determined by user
Determined by user
Determined by user
Capacitor ceramic, 1 µF, 25 V, X7R, 10%, 0603
Capacitor ceramic, 10 nF, 50 V, 10%, X7R, 0603
Capacitor ceramic, 22 µF, 16 V, X7R, 1210
Capacitor ceramic, 10 µF, 25 V, X7R, 1210
Inductor
10 µF
12.3 µH
0.1 µF
190 pF
132 kΩ
115 kΩ
45.3 kΩ
10 kΩ
50 kΩ
Capacitor ceramic, 0.1 µF, 50 V, X7R, 0805
Capacitor ceramic, 50 V
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
R2
R3
R7
Rev. B | Page 30 of 36
Data Sheet
ADP2442
POWER DISSIPATION AND THERMAL CONSIDERATIONS
Transition Losses
POWER DISSIPATION
The efficiency of a dc-to-dc regulator is
POUT
Transition losses occur because the N-channel MOSFET power
switch cannot turn on or off instantaneously. During a switch
node transition, the power switch provides all of the inductor
current, and the source-to-drain voltage of the power switch is
half the input, resulting in power loss. Transition losses increase
as the load current and input voltage increase; these losses
occur twice for each switching cycle.
Efficiency =
×100%
(26)
PIN
where:
PIN is the input power.
OUT is the output power.
The power loss of a dc-to-dc regulator is
LOSS = PIN − POUT
There are four main sources of power loss in a dc-to-dc regulator
P
The transition losses can be calculated as follows:
VIN
2
P
(30)
PTRANS
=
× IOUT ×(tON + tOFF ) fSW
where tON and tOFF are the rise time and fall time of the switch
node and are each approximately 10 ns for a 24 V input.
•
•
•
•
Inductor losses
Power switch conduction losses
Switching losses
THERMAL CONSIDERATIONS
The power dissipated by the regulator increases the die junction
temperature, TJ, above the ambient temperature, TA, as follows:
Transition losses
Inductor Losses
TJ = TA + TR
(31)
Inductor conduction losses are caused by the flow of current
through the inductor DCR (internal resistance). The inductor
power loss (excluding core loss) is
where the temperature rise, TR, is proportional to the power
dissipation, PD, in the package.
The proportionality coefficient is defined as the thermal
resistance from the junction temperature of the die to the
ambient temperature, as follows:
PL = IOUT2 × DCRL
(27)
Power Switch Conduction Losses
Power switch conduction losses are caused by the output current,
OUT, flowing through the N-channel MOSFET power switches
that have internal resistance, RDS(ON). The amount of power loss
can be approximated as follows:
TR = θJA + PD
(32)
I
where θJA is the junction-to-ambient thermal resistance and
equals 40°C/W for the JEDEC board (see Table 3).
2
When designing an application for a particular ambient
temperature range, calculate the expected ADP2442 power
P
COND = [RDS(ON) − HIGH SIDE × D + RDS(ON) − LOW SIDE × (1 − D)] × IOUT (28)
Switching Losses
dissipation (PD) due to the conduction, switching, and transition
losses using Equation 28, Equation 29, and Equation 30, and
then estimate the temperature rise using Equation 31 and
Equation 32. Improved thermal performance can be achieved
by good board layout.
Switching losses are associated with the current drawn by the
driver to turn the power devices on and off at the switching
frequency. Each time a power device gate is turned on and off,
the driver transfers a charge (∆Q) from the input supply to the
gate and then from the gate to ground.
For example, on the ADP2442 evaluation board (ADP2442-
EVALZ), the measured θJA is <30°C/W. Thermal performance of
the ADP2442-EVALZ evaluation board is shown in Figure 68
and Figure 69.
The amount of switching loss can by calculated as follows:
P
SW = QG_TOTAL × VIN × fSW
(29)
where:
QG_TOTAL is the total gate charge of both the high-side and low-
side devices and is approximately 18 nC. fSW is the switching
frequency.
Rev. B | Page 31 of 36
ADP2442
Data Sheet
EVALUATION BOARD THERMAL PERFORMANCE
145
125
105
85
55
T
= 25°C
A
50
45
40
35
30
25
65
45
25
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
IC POWER DISSIPIATION (W)
IC POWER DISSIPIATION (W)
Figure 69. Maximum Ambient Temperature vs. Power Dissipation Based on
ADP2442-EVALZ
Figure 68. Junction Temperature vs. Power Dissipation Based on
ADP2442-EVALZ
Rev. B | Page 32 of 36
Data Sheet
ADP2442
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Good printed circuit board (PCB) layout is essential for obtaining
optimum performance. Poor PCB layout degrades the output
voltage ripple; the load, line, and feedback regulation; and the
EMI and electromagnetic compatibility performance. For
optimum layout, refer to the following guidelines:
The placement and routing of the compensation components
are critical for optimum performance of ADP2442. Place
the compensation components as close as possible to the
COMP pin. Use 0402 sized compensation components to
allow closer placement, which in turn reduces parasitic noise.
Surround the compensation components with AGND to
prevent noise pickup.
The FREQ pin is sensitive to noise; therefore, place the
frequency resistor as close as possible to the FREQ pin and
route it with minimal trace length.
Use separate analog and power ground planes. Connect the
ground reference of sensitive analog circuitry, such as the
output voltage divider component and the compensation
and frequency resistor, to analog ground. In addition, connect
the ground references of power components, such as input
and output capacitors, to power ground. Connect both
ground planes to the exposed pad of the ADP2442.
Place one end of the input capacitor as close as possible to
the VIN pin, and connect the other end to the closest
power ground plane.
Ground the small signal components to the analog ground
path.
C4
C3
C5
V
Place a high frequency filter capacitor between the VIN
and PGND pins, as close as possible to the PGND pin.
VCC is the internal regulator output. Place a 1 μF capacitor
between the VCC and AGND pins and another 1 μF
capacitor between the VCC and PGND pins. Place the
capacitors as close as possible to the pins.
Ensure that the high current loop traces are as short and
wide as possible. Make the high current path from CIN
through L, COUT, and the power ground plane back to CIN
as short as possible. To accomplish this, ensure that the
input and output capacitors share a common power
ground plane.
Make the high current path from the PGND pin through L
and COUT back to the power ground plane as short as possible.
To do this, ensure that the PGND pin is tied to the PGND
plane as close as possible to the input and output capacitors
(see Figure 70).
OUT
R2
V
IN
FB
VIN
SW
L1
V
OUT
R3
ADP2442
COMP
V
IN
C6
C7
R6
PGND
EN
R5
C10
R8
R9
NOTES
1. THICK LINE INDICATES HIGH CURRENT TRACE.
Figure 70. High Current Trace
C
BST
Connect the ADP2442 exposed pad to a large copper plane
to maximize its power dissipation capability.
VCC
AGND
FB
C
V
IN
Place the feedback resistor divider network as close as possible
to the FB pin to prevent noise pickup. Keep the length of the
trace connecting the top of the feedback resistor divider to
the output as short as possible and, to avoid noise pickup,
also keep it away from the high current traces and switch
node. Place an analog ground plane on either side of the FB
trace, further reducing noise pickup.
IN
COMP
V
OUT
FREQ
PGND
C
OUT
Figure 71. PCB Top Layer Placement
Rev. B | Page 33 of 36
ADP2442
Data Sheet
OUTLINE DIMENSIONS
3.10
3.00 SQ
2.90
0.30
0.23
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
10
12
0.50
BSC
1
3
9
7
EXPOSED
PAD
1.70
1.60 SQ
1.50
0.20 MIN
6
4
0.50
0.40
0.30
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-229-WEED-4.
Figure 72. 12-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Very Thin Quad
(CP-12-6)
Dimensions shown in millimeters
ORDERING GUIDE
Package
Model1
Output Voltage Temperature Range Package Description
Option
12-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-12-6
Evaluation Board (Preset to 5 V)
Branding
ADP2442ACPZ-R7 Adjustable
ADP2442-EVALZ
−40°C to +125°C
LK5
1 Z = RoHS Compliant Part.
Rev. B | Page 34 of 36
Data Sheet
NOTES
ADP2442
Rev. B | Page 35 of 36
ADP2442
NOTES
Data Sheet
©2012–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10667-0-8/15(B)
Rev. B | Page 36 of 36
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ADP2503ACPZ-3.5-R7
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