ADP3168JRUZ-REEL7 [ADI]
IC SWITCHING CONTROLLER, 4000 kHz SWITCHING FREQ-MAX, PDSO28, MO-153AE, TSSOP-28, Switching Regulator or Controller;
| 型号： | ADP3168JRUZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | IC SWITCHING CONTROLLER, 4000 kHz SWITCHING FREQ-MAX, PDSO28, MO-153AE, TSSOP-28, Switching Regulator or Controller 开关 光电二极管 |
| 文件： | 总24页 (文件大小：947K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
6-Bit, Programmable 2-, 3-, 4-Phase
Synchronous Buck Controller
ADP3168
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VCC
28
RAMPADJ RT
14 13
Selectable 2-, 3-, or 4-phase operation at up to
1 MHz per phase
ADP3168
10 mV worst-case differential sensing error over
temperature
Logic-level PWM outputs for interface to
external high power drivers
Active current balancing between all output phases
Built-in Power Good/crowbar blanking supports
On-the-fly VID code changes
6-bit digitally programmable 0.8375 V to 1.6 V output
Programmable short-circuit protection with
programmable latch-off delay
UVLO
SHUTDOWN
AND BIAS
11
EN
OSCILLATOR
SET EN
27
PWM1
RESET
19
GND
DAC
+150mV
RESET
26
PWM2
CURRENT-
BALANCING
CIRCUIT
2-, 3-, 4-PHASE
DRIVER LOGIC
CSREF
25
PWM3
RESET
DAC
–250mV
24
PWM4
RESET
APPLICATIONS
10
PWRGD
DELAY
CROWBAR
Desktop PC power supplies for:
Next generation Intel® processors
VRM modules
CURRENT
LIMIT
23
SW1
22
SW2
21
SW3
GENERAL DESCRIPTION
15
ILIMIT
20
SW4
EN
The ADP3168 is a highly efficient, multiphase, synchronous
buck switching regulator controller optimized for converting a
12 V main supply into the core supply voltage required by high
performance Intel processors. It uses an internal 6-bit DAC to
read a voltage identification (VID) code directly from the
processor, which is used to set the output voltage between
0.8375 V and 1.6 V, and uses a multimode PWM architecture to
drive the logic-level outputs at a programmable switching
frequency that can be optimized for VR size and efficiency. The
phase relationship of the output signals can be programmed to
provide 2-, 3-, or 4-phase operation, allowing for the construc-
tion of up to four complementary buck switching stages.
17
CSSUM
CURRENT-
LIMIT
CIRCUIT
16
CSREF
12
DELAY
18
CSCOMP
SOFT-
START
8
9
FB
COMP
PRECISION
VID
DAC
REFERENCE
The ADP3168 also includes programmable no-load offset and
slope functions to adjust the output voltage as a function of the
load current so that it is always optimally positioned for a
system transient. The ADP3168 also provides accurate and
reliable short-circuit protection, adjustable current limiting, and
a delayed Power Good output that accommodates on-the-fly
output voltage changes requested by the CPU.
7
1
2
3
4
5
6
FBRTN
VID4 VID3 VID2 VID1 VID0 VID5
Figure 1.
The device is specified over the commercial temperature range
of 0°C to 85°C and is available in a 28-lead TSSOP package.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
ADP3168
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics and Test Circuits............... 7
Theory of Operation ........................................................................ 9
Number of Phases......................................................................... 9
Master Clock Frequency.............................................................. 9
Output Voltage Differential Sensing.......................................... 9
Output Current Sensing .............................................................. 9
Active Impedance Control Mode............................................. 10
Current-Control Mode and Thermal Balance........................ 10
Voltage Control Mode................................................................ 10
Soft Start ...................................................................................... 10
Current-Limit, Short-Circuit, and Latch-Off Protection...... 11
Dynamic VID.............................................................................. 12
Power-Good Monitoring........................................................... 12
Output Crowbar ......................................................................... 12
Output Enable and UVLO ........................................................ 12
Application Information................................................................ 13
Setting the Clock Frequency..................................................... 13
Soft Start and Current Limit Latch-Off Delay Times............ 13
Inductor Selection...................................................................... 13
Designing an Inductor............................................................... 15
Selecting a Standard Inductor................................................... 15
Output Droop Resistance.......................................................... 15
Inductor DCR Temperature Correction ................................. 16
Output Offset.............................................................................. 16
COUT Selection ............................................................................. 17
Power MOSFETs......................................................................... 18
Ramp Resistor Selection............................................................ 19
COMP Pin Ramp ....................................................................... 19
Current-Limit Set Point............................................................. 19
Feedback Loop Compensation Design.................................... 19
CIN Selection and Input Current di/dt Reduction.................. 21
Tuning Procedure for the ADP3168........................................ 21
Layout and Component Placement.............................................. 23
General Recommendations....................................................... 23
Power Circuitry .......................................................................... 23
Signal Circuitry........................................................................... 23
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
11/04—Rev. A to Rev. B
Changes to Specifications................................................................ 3
Updated Outline Dimensions....................................................... 24
Changes to Ordering Guide .......................................................... 24
4/03—Data Sheet Changed from Rev. 0 to Rev. A.
Changes to Specifications................................................................ 2
Rev. B | Page 2 of 24
ADP3168
SPECIFICATIONS
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VCC = 12 V,
FBRTN = GND, TA = 0°C to 85°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
ERROR AMPLIFIER
Output Voltage Range
Accuracy
VCOMP
VFB
0.5
−10
3.5
+10
V
mV
Relative to nominal DAC output,
Referenced to FBRTN,
CSSUM = CSCOMP; see Figure 10
VCC = 10 V to 14 V
Line Regulation
Input Bias Current
FBRTN Current
Output Current
Gain Bandwidth Product
Slew Rate
∆VFB
IFB
IFBRTN
IO(ERR)
GBW(ERR)
0.05
15.5
90
500
20
%
µA
µA
µA
MHz
V/µs
14
17
120
FB forced to VOUT − 3%
COMP = FB
CCOMP = 10 pF
25
VID INPUTS
Input Low Voltage
Input High Voltage
Input Current, Input Voltage Low
Input Current, Input Voltage High
Pull-Up Resistance
Internal Pull-Up Voltage
VID Transition Delay Time1
No CPU Detection Turn-Off
Delay Time
VIL(VID)
VIH(VID)
IIL(VID)
IIH(VID)
RVID
0.4
V
V
0.8
VID(X) = 0 V
VID(X) = 1.25 V
−20
15
60
−30
25
115
µA
µA
kΩ
V
ns
ns
35
0.825
400
400
1.00
VID code change to FB change
VID code change to 11111 to
PWM going low
OSCILLATOR
Frequency Range1
Frequency Variation
fOSC
fPHASE
0.25
155
4
245
MHz
kHz
kHz
kHz
V
TA = 25°C, RT = 250 kΩ, 4-phase
TA = 25°C, RT = 115 kΩ, 4-phase
TA = 25°C, RT = 75 kΩ, 4-phase
RT = 100 kΩ to GND
200
400
600
2.0
Output Voltage
VRT
VRAMPADJ
IRAMPADJ
1.9
−50
0
2.1
+50
100
RAMPADJ Output Voltage
RAMPADJ Input Current Range
CURRENT SENSE AMPLIFIER
Offset Voltage
Input Bias Current
Gain Bandwidth Product
Slew Rate
Input Common-Mode Range
Positioning Accuracy
Output Voltage Range
Output Current
RAMPADJ − FB
mV
µA
VOS(CSA)
IBIAS(CSA)
GBW(CSA)
CSSUM − CSREF; see Figure 5
−1.5
−50
+1.5
+50
mV
nA
MHz
V/µs
V
mV
V
µA
10
10
CCSCOMP = 10 pF
CSSUM and CSREF
See Figure 6
0
−77
0.05
3
−83
3.3
∆VFB
−80
500
ICSCOMP
= 100 µA
ICSCOMP
CURRENT-BALANCE CIRCUIT
Common-Mode Range
Input Resistance
Input Current
Input Current Matching
VSW(X)CM
RSW(X)
ISW(X)
−600
20
4
+200
40
10
mV
kΩ
µA
%
SW(X) = 0 V
SW(X) = 0 V
SW(X) = 0 V
30
7
∆ISW(X)
−5
+5
1 Guaranteed by design, not tested in production.
Rev. B | Page 3 of 24
ADP3168
Parameter
Symbol
Conditions
Min
2.9
Typ
Max
Unit
CURRENT-LIMIT COMPARATOR
ILIMIT Output Voltage
Normal Mode
VILIMIT(NM)
VILIMIT(SD)
IILIMIT(NM)
VCL
EN > 1.7 V, RILIMIT = 250 kΩ
EN > 0.8 V, IILIMIT = −100 µA
EN > 1.7 V, RILIMIT = 250 kΩ
VCSREF − VCSCOMP, RILIMIT = 250 kΩ
VCL/IILIMIT
3
3.1
400
V
Shutdown Mode
mV
µA
mV
mV/µA
V
Output Current, Normal Mode
Current-Limit Threshold Voltage
Current-Limit Setting Ratio
DELAY Normal Mode Voltage
DELAY Overcurrent Threshold
Latch-Off Delay Time
12
105
125
10.4
3
1.8
600
145
VDELAY(NM)
VDELAY(OC)
tDELAY
2.9
1.7
3.1
1.9
V
µs
RDELAY = 250 kΩ, CDELAY = 4.7 nF
SOFT START
Output Current, Soft-Start Mode
Soft-Start Delay Time
IDELAY(SS)
tDELAY(SS)
During startup, DELAY < 2.8 V
RDELAY = 250 kΩ, CDELAY= 4.7 nF
VID code = 011111
15
20
350
25
µA
µs
ENABLE INPUT
Input Low Voltage
VIL(EN)
VIH(EN)
IIL(EN)
0.4
V
V
µA
µA
Input High Voltage
Input Current, Input Voltage Low
Input Current, Input Voltage High
POWER-GOOD COMPARATOR
Undervoltage Threshold
Overvoltage Threshold
Output Low Voltage
Power-Good Delay Time
VID Code Changing
VID Code Static
Crowbar Trip Point
Crowbar Reset Point
Crowbar Delay Time
VID Code Changing
VID Code Static
0.8
−1
EN = 0 V
EN = 1.25 V
+1
25
IIH(EN)
10
VPWRGD(UV)
VPWRGD(OV)
VOL(PWRGD)
Relative to nominal DAC output
Relative to nominal DAC output
IPWRGD(SINK) = 4 mA
−200
90
−250
150
225
−325
200
400
mV
mV
mV
100
250
200
150
550
µs
ns
mV
mV
VCROWBAR
tCROWBAR
Relative to nominal DAC output
Relative to FBRTN
Overvoltage to PWM going low
90
450
200
650
100
4.0
250
400
µs
ns
PWM OUTPUTS
Output Voltage Low
Output Voltage High
SUPPLY
VOL(PWM)
VOH(PWM)
IPWM(SINK) = 400 µA
IPWM(SOURCE) = 400 µA
160
5.0
500
mV
V
DC Supply Current
UVLO Threshold Voltage
UVLO Hysteresis
5
6.9
0.9
8
7.3
1.1
mA
V
V
VUVLO
VCC rising
6.5
0.7
Rev. B | Page 4 of 24
ADP3168
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VCC
FBRTN
VID0 to VID5, EN, DELAY, ILIMIT,
CSCOMP, RT, PWM1 to PWM4, COMP
SW1-SW4
All Other Inputs and Outputs
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Absolute maximum ratings apply individually
only, not in combination. Unless otherwise specified, all other
voltages are referenced to GND.
Rating
−0.3 V to +15 V
−0.3 V to +0.3 V
−0.3 V to +5.5 V
−5 V to +25 V
−0.3 V to VCC + 0.3 V
Operating Ambient Temperature
Range
0°C to 85°C
Operating Junction Temperature
Storage Temperature Range
125°C
−65°C to +150°C
Junction to Air Thermal Resistance (θJA) 100°C/W
Lead Temperature (Soldering, 10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
300°C
215°C
220°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 5 of 24
ADP3168
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
28
VID4
VCC
27
2
VID3
PWM1
PWM2
3
VID2
26
ADP3168
VID1
4
25 PWM3
24
5
VID0
PWM4
6
VID5
23 SW1
22 SW2
7
FBRTN
FB
TOP VIEW
8
21
20
SW3
SW4
(Not to Scale)
COMP
PWRGD
EN
9
10
11
12
19 GND
18 CSCOMP
17
16
15
DELAY
CSSUM
CSREF
ILIMIT
RT 13
14
RAMPADJ
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Function
1 to 6
VID4 to VID0, VID5 Voltage Identification DAC Inputs. These six pins are pulled up to an internal reference, providing a Logic 1
if left open. When in normal operation mode, the DAC output programs the FB regulation voltage from
0.8375 V to 1.6 V. Leaving VID4 through VID0 open results in the ADP3168 going into a no CPU mode,
shutting off its PWM outputs.
7
8
FBRTN
FB
Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.
Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor
between this pin and the output voltage sets the no -load offset point.
9
COMP
Error Amplifier Output and Compensation Point.
10
PWRGD
Power Good Output. Open-drain output that pulls to GND when the output voltage is outside the proper
operating range.
11
12
EN
DELAY
Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs.
Soft-Start Delay and Current Limit Latch-Off Delay Setting Input. An external resistor and capacitor
connected between this pin and GND set the soft-start ramp-up time and the overcurrent latch-off delay
time.
13
14
15
RT
Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the
oscillator frequency of the device.
PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal
PWM ramp.
Current Limit Set Point/Enable Output. An external resistor from this pin to GND sets the current limit
threshold of the converter. This pin is actively pulled low when the ADP3168 EN input is low or when VCC
is below its UVLO threshold to signal to the driver IC that the driver high-side and low-side outputs should
go low.
RAMPADJ
ILIMIT
16
CSREF
Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current-
sense amplifier and the Power Good and crowbar functions. This pin should be connected to the common
point of the output inductors.
17
18
19
CSSUM
CSCOMP
GND
Current-Sense Summing Node. External resistors from each switch node to this pin sum the average
inductor currents to measure the total output current.
Current Sense Compensation Point. A resistor and a capacitor from this pin to CSSUM determine the slope
of the load line and the positioning loop response time.
Ground. All internal biasing and the logic output signals of the device are referenced to this ground.
20 to 23 SW4 to SW1
Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused
phases should be left open.
24 to 27 PWM4 to PWM1
Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver, such as the
ADP3413 or ADP3418. Connecting the PWM3 and/or PWM4 outputs to GND causes that phase to turn off,
allowing the ADP3168 to operate as a 2-, 3 -, or 4 -phase controller.
28
VCC
Supply Voltage for the Device.
Rev. B | Page 6 of 24
ADP3168
TYPICAL PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS
5.3
5.2
5.1
5.0
4.9
4.8
4.7
4.6
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
T
= 25°C
A
4-PHASE OPERATION
SEE EQUATION 1 FOR FREQUENCIES NOT ON THIS GRAPH
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
50
100
150
200
250
300
MASTER CLOCK FREQUENCY (MHz)
R
VALUE (kΩ)
T
Figure 4. Supply Current vs. Master Clock Frequency
Figure 3. Master Clock Frequency vs. RT
ADP3168
ADP3168
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VID4
VCC
PWM1
PWM2
PWM3
PWM4
SW1
12V
+
28
18
12V
VCC
1µF
100nF
VID3
3
VID2
CSCOMP
6-BIT CODE
4
VID1
39kΩ
100nF
CSSUM
CSREF
5
VID0
17
16
19
6
VID5
1kΩ
7
FBRTN
FB
SW2
1.0V
CSCOMP – 1V
40
8
SW3
V
=
OS
GND
9
COMP
PWRGD
EN
SW4
1kΩ
10
11
12
13
14
GND
Figure 5. Test Circuit 1, Current Sense Amplifier VOS
1.25V
CSCOMP
CSSUM
CSREF
ILIMIT
ADP3168
20kΩ
100nF
DELAY
RT
28
8
12V
VCC
4.7nF
250kΩ
RAMPADJ
FB
250kΩ
10kΩ
9
COMP
Figure 7. Test Circuit 3, Closed-Loop Output Voltage Accuracy
200kΩ
CSCOMP
18
17
16
100nF
200kΩ
∆V
CSSUM
CSREF
1.0V
19 GND
∆V
= FB
= 80mV – FB
= 0mV
∆V
FB
∆V
Figure 6. Test Circuit, Positioning Voltage
Rev. B | Page 7 of 24
ADP3168
Table 4. Output Voltage vs. VID Code (X = Don’t Care)
VID4 VID3 VID2 VID1 VID0 VID5 VOUT(NOM)
VID4 VID3 VID2 VID1 VID0 VID5 VOUT(NOM)
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
1
1
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
X
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
No CPU
0.8375 V
0.850 V
0.8625 V
0.875 V
0.8875 V
0.900 V
0.9125 V
0.925 V
0.9375 V
0.950 V
0.9625 V
0.975 V
0.9875 V
1.000 V
1.0125 V
1.025 V
1.0375 V
1.050 V
1.0625 V
1.075 V
1.0875 V
1.100 V
1.1125 V
1.125 V
1.1375 V
1.150 V
1.1625 V
1.175 V
1.1875 V
1.200 V
1.2125 V
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.225 V
1.2375 V
1.250 V
1.2625 V
1.275 V
1.2875 V
1.300 V
1.3125 V
1.325 V
1.3375 V
1.350 V
1.3625 V
1.375 V
1.3875 V
1.400 V
1.4125 V
1.425 V
1.4375 V
1.450 V
1.4625 V
1.475 V
1.4875 V
1.500 V
1.5125 V
1.525 V
1.5375 V
1.550 V
1.5625 V
1.575 V
1.5875 V
1.600 V
Rev. B | Page 8 of 24
ADP3168
THEORY OF OPERATION
The ADP3168 combines a multimode, fixed frequency PWM
control with multiphase logic outputs for use in 2-, 3-, and
4-phase synchronous buck CPU core supply power converters.
The internal 6-bit VID DAC conforms to Intel’s VRD/VRM 10
specifications. Multiphase operation is important for producing
the high currents and low voltages demanded by today’s
microprocessors. Handling the high currents in a single-phase
converter would place high thermal demands on system
components such as inductors and MOSFETs.
The PWM outputs become logic-level devices once normal
operation starts. The detection is normal and is intended for
driving external gate drivers such as the ADP3418. Because
each phase is monitored independently, operation approaching
100% duty cycle is possible. Also, more than one output can be
on at any given time for overlapping phases.
MASTER CLOCK FREQUENCY
The clock frequency of the ADP3168 is set with an external
resistor connected from the RT pin to ground. The frequency
follows the graph in Figure 3. To determine the frequency per
phase, the clock is divided by the number of phases in use. If
PWM4 is grounded, divide the master clock by 3 for the
frequency of the remaining phases. If PWM3 and PWM4 are
grounded, divide by 2. If all phases are in use, divide by 4.
The multimode control of the ADP3168 ensures a stable, high
performance topology for
•
•
Balancing currents and thermals between phases
High speed response at the lowest possible switching
frequency and output decoupling
•
Minimizing thermal switching losses due to lower
frequency operation
OUTPUT VOLTAGE DIFFERENTIAL SENSING
The ADP3168 combines differential sensing with a high
accuracy VID DAC and reference and a low offset error amp-
lifier to maintain a worst-case specification of 10 mV differ-
ential sensing error with a VID input of 1.6000 V over its full
operating output voltage and temperature range. The output
voltage is sensed between the FB and FBRTN pins. FB should
be connected through a resistor to the regulation point, usually
the remote sense pin of the microprocessor. FBRTN should be
connected directly to the remote sense ground point. The
internal VID DAC and precision reference are referenced to
FBRTN, which has a minimal current of 90 µA to allow
accurate remote sensing. The internal error amplifier compares
the output of the DAC to the FB pin to regulate the output
voltage.
•
•
Tight load-line regulation and accuracy
High current output resulting from having up to a 4-phase
operation
Reduced output ripple due to multiphase cancellation
PC board layout noise immunity
Ease of use and design due to independent component
selection
Flexibility in operation for tailoring design to low cost or
high performance
•
•
•
•
NUMBER OF PHASES
The number of operational phases and their phase relationship
is determined by the internal circuitry that monitors the PWM
outputs. Normally, the ADP3168 operates as a 4-phase PWM
controller. Grounding the PWM4 pin programs 3-phase
operation; grounding the PWM3 and PWM4 pins programs
2-phase operation.
OUTPUT CURRENT SENSING
The ADP3168 provides a dedicated current sense amplifier
(CSA) to monitor the total output current for proper voltage
positioning vs. load current and for current limit detection.
Sensing the load current at the output gives the total average
current being delivered to the load, which is an inherently more
accurate method than peak current detection or sampling the
current across a sense element such as the low-side MOSFET.
This amplifier can be configured several ways, depending on
the objectives of the system:
When the ADP3168 is enabled, the controller outputs a voltage
on PWM3 and PWM4 of approximately 550 mV. An internal
comparator checks each pin’s voltage vs. a threshold of 400 mV.
If the pin is grounded, the voltage is below the threshold and
the phase is disabled. The output resistance of the PWM pin is
approximately 5 kΩ during this detection time. Any external
pull-down resistance connected to the PWM pin should be at
least 25 kΩ to ensure proper operation. The phase detection is
made during the first two clock cycles of the internal oscillator.
After this time, if the PWM output is not grounded, the 5 kΩ
resistance is removed and switches between 0 V and 5 V. If the
PWM output was grounded, it remains off.
•
•
•
Output inductor ESR sensing without thermistor for lowest
cost
Output inductor ESR sensing with thermistor for improved
accuracy with tracking of inductor temperature
Sense resistors for most accurate measurements
Rev. B | Page 9 of 24
ADP3168
The positive input of the CSA is connected to the CSREF pin,
which is connected to the output voltage. The inputs to the
amplifier are summed together through resistors from the
sensing element (such as the switch node side of the output
inductors) to the inverting input, CSSUM. The feedback resistor
between CSCOMP and CSSUM sets the gain of the amplifier,
and a filter capacitor is placed in parallel with this resistor.
The gain of the amplifier is programmable by adjusting the
feedback resistor to set the load line required by the micro-
processor. The current information is then given as the differ-
ence of CSREF − CSCOMP. This difference signal is used
internally to offset the VID DAC for voltage positioning and
as a differential input for the current-limit comparator.
Resistors RSW1 through RSW4 (see the typical applica-tion circuit
in Figure 11) can be used for adjusting thermal balance. It is
best to add these resistors during the initial design, so make
sure placeholders are provided in the layout.
To increase the current in any given phase, make RSW for that
phase larger. (Make RSW = 0 for the hottest phase and do not
change during balancing.) Increasing RSW to only 500 Ω makes
a substantial increase in phase current. Increase each RSW value
by small amounts to achieve balance, starting with the coolest
phase first.
VOLTAGE CONTROL MODE
A high gain bandwidth voltage mode error amplifier is used for
the voltage-mode control loop. The control input voltage to the
positive input is set via the VID 6-bit logic code, according to
the voltages listed in Table 4. This voltage is also offset by the
droop voltage for active positioning of the output voltage as a
function of current, commonly known as active voltage
To provide the best accuracy for the current sensing, the CSA
was designed to have a low offset input voltage. Also, the
sensing gain is determined by external resistors so that it can
be made extremely accurate.
ACTIVE IMPEDANCE CONTROL MODE
positioning. The output of the amplifier is the COMP pin,
which sets the termination voltage for the internal PWM ramps.
For controlling the dynamic output voltage droop as a function
of output current, a signal proportional to the total output
current at the CSCOMP pin can be scaled to be equal to the
droop impedance of the regulator times the output current.
This droop voltage is then used to set the input control voltage
to the system. The droop voltage is subtracted from the DAC
reference input voltage directly to tell the error amplifier where
the output voltage should be. This differs from previous
implementations and allows enhanced feed-forward response.
The negative input (FB) is tied to the output sense location with
a resistor, RB, and is used for sensing and controlling the output
voltage at this point. A current source from the FB pin flowing
through RB is used for setting the no-load offset voltage from
the VID voltage. The no-load voltage is negative with respect to
the VID DAC. The main loop compensation is incorporated
into the feedback network between FB and COMP.
SOFT START
CURRENT-CONTROL MODE AND THERMAL
BALANCE
The power-on ramp-up time of the output voltage is set with a
capacitor and a resistor in parallel from the DELAY pin to
ground. The RC time constant also determines the current-limit
latch-off time, as explained in the following section. In UVLO
or when EN is a logic low, the DELAY pin is held at ground.
After the UVLO threshold is reached and EN is a logic high, the
DELAY capacitor is charged up with an internal 20 µA current
source. The output voltage follows the ramping voltage on the
DELAY pin, limiting the inrush current. The soft-start time
depends on the values of VID DAC and CDLY, with a secondary
effect from RDLY. Refer to the Application Information section
The ADP3168 has individual inputs that are used for
monitoring the current in each phase. This information is
combined with an internal ramp to create a current-balancing
feedback system that has been optimized for initial current
balance accuracy and dynamic thermal balancing during
operation. This current-balance information is independent of
the average output current information used for positioning
described previously.
The magnitude of the internal ramp can be set to optimize
the transient response of the system. It also monitors the
supply voltage for feed-forward control for changes in the
supply. A resistor connected from the power input voltage to
the RAMPADJ pin determines the slope of the internal PWM
ramp. Detailed information about programming the ramp is
given in the Application Information section.
for detailed information on setting CDLY
.
When the PWRGD threshold is reached, the soft-start cycle is
stopped and the DELAY pin is pulled up to 3 V. This ensures
that the output voltage is at the VID voltage when the PWRGD
signals to the system that the output voltage is good. If EN is
taken low or VCC drops below UVLO, the DELAY capacitor is
reset to ground to be ready for another soft-start cycle. Figure 8
shows a typical start-up sequence for the ADP3168.
External resistors can be placed in series with individual phases,
for example, to create an intentional current imbalance so one
phase may have better cooling and can support higher currents.
Rev. B | Page 10 of 24
ADP3168
The latch-off function can be reset either by removing and
reapplying VCC to the ADP3168, or by pulling the EN pin low
for a short time. To disable the short-circuit latch-off function,
the external resistor to ground should be left open, and a high
value (>1 MΩ) resistor should be connected from DELAY to
VCC. This prevents the DELAY capacitor from discharging, so
the 1.8 V threshold is never reached. The resistor has an impact
on the soft-start time because the current through it adds to the
internal 20 µA current source.
Figure 8. Start-Up Waveforms, Circuit of Figure 12. Channel 1—PWRGD,
Channel 2—VOUT, Channel 3—High-Side MOSFET VGS
Channel 4—Low-Side MOSFET VGS
,
CURRENT-LIMIT, SHORT-CIRCUIT, AND
LATCH-OFF PROTECTION
The ADP3168 compares a programmable current-limit set
point to the voltage from the output of the current-sense
amplifier. The level of current limit is set with the resistor from
the ILIMIT pin to ground. During normal operation, the
voltage on ILIMIT is 3 V. The current through the external
resistor is internally scaled to give a current-limit threshold of
10.4 mV/µA. If the difference in voltage between CSREF and
CSCOMP rises above the current-limit threshold, the internal
current-limit amplifier controls the internal COMP voltage to
maintain the average output current at the limit.
Figure 9. Overcurrent Latch-Off Waveforms, Circuit of Figure 11. Channel 1—
PWRGD, Channel 2—VOUT, Channel 3—CSCOMP Pin of ADP3168,
Channel 4—High-Side MOSFET VGS
During startup, when the output voltage is below 200 mV, a
secondary current limit is active. This is necessary because the
voltage swing of CSCOMP cannot go below ground. This
secondary current limit controls the internal COMP voltage
to the PWM comparators to 2 V. This limits the voltage drop
across the low-side MOSFETs through the current-balance
circuitry.
After the limit is reached, the 3 V pull-up on the DELAY pin is
disconnected, and the external delay capacitor is discharged
through the external resistor. A comparator monitors the
DELAY voltage and shuts off the controller when the voltage
drops below 1.8 V. The current-limit latch-off delay time is
therefore set by the RC time constant discharging from 3 V to
1.8 V. The Application Information section discusses the
There is also an inherent per-phase current limit that protects
individual phases in the case where one or more phases stop
functioning because of a faulty component. This limit is based
on the maximum normal mode COMP voltage.
selection of CDLY and RDLY
.
Because the controller continues to cycle the phases during the
latch-off delay time, if the short is removed before the 1.8 V
threshold is reached, the controller returns to normal operation.
The recovery characteristic depends on the state of PWRGD. If
the output voltage is within the PWRGD window, the controller
resumes normal operation. However, if a short circuit has
caused the output voltage to drop below the PWRGD threshold,
a soft-start cycle is initiated.
Rev. B | Page 11 of 24
ADP3168
DYNAMIC VID
OUTPUT CROWBAR
The ADP3168 incorporates the ability to dynamically change
the VID input while the controller is running. This allows the
output voltage to change while the supply is running and
supplying current to the load. This is commonly referred to as
VID on-the-fly (OTF). A VID OTF can occur under either light
load or heavy load conditions. The processor signals the
controller by changing the VID inputs in multiple steps from
the start code to the finish code. This change can be either
positive or negative.
As part of the protection for the load and output components of
the supply, the PWM outputs are driven low (turning on the
low-side MOSFETs) when the output voltage exceeds the upper
Power-Good threshold. This crowbar action stops once the
output voltage has fallen below the release threshold of
approximately 450 mV.
Turning on the low-side MOSFETs pulls down the output as the
reverse current builds up in the inductors. If the output over-
voltage is due to a short of the high-side MOSFET, this action
current limits the input supply or blows its fuse, protecting the
microprocessor from destruction.
When a VID input changes state, the ADP3168 detects the
change and ignores the DAC inputs for a minimum of 400 ns.
This prevents a false code due to logic skew while the six VID
inputs are changing. Additionally, the first VID change initiates
the PWRGD and CROWBAR blanking functions for a mini-
mum of 250 µs to prevent a false PWRGD or CROWBAR event.
Each VID change resets the internal timer. Figure 10 shows VID
on-the-fly performance when the output voltage is stepping up
and the output current is switching between minimum and
maximum values, which is the worst-case situation.
OUTPUT ENABLE AND UVLO
The input supply (VCC) to the controller must be higher than
the UVLO threshold, and the EN pin must be higher than its
logic threshold for the ADP3168 to begin switching. If UVLO is
less than the threshold or the EN pin is a logic low, the
ADP3168 is disabled. This holds the PWM outputs at ground,
shorts the DELAY capacitor to ground, and holds the ILIMIT
pin at ground.
In the application circuit, the ILIMIT pin should be connected
OD
to the
pins of the ADP3418 drivers. Because ILIMIT is
grounded, this disables the drivers so that both DRVH and
DRVL are grounded. This feature is important to prevent
discharging of the output capacitors when the controller is shut
off. If the driver outputs were not disabled, a negative voltage
could be generated on the output due to the high current
discharge of the output capacitors through the inductors.
Figure 10. VID On-the-Fly Waveforms, Circuit of Figure 12.
VID Change = 5 mV, 5 µs per Step, 50 Steps, IOUT Change =5 A to 65 A
POWER-GOOD MONITORING
The Power-Good comparator monitors the output voltage via
the CSREF pin. The PWRGD pin is an open-drain output
whose high level (when connected to a pull-up resistor)
indicates that the output voltage is within the nominal limits
specified in Table 1 based on the VID voltage setting. PWRGD
goes low if the output voltage is outside of this specified range.
PWRGD is blanked during a VID OTF event for a period of
250 µs to prevent false signals during the time the output is
changing.
Rev. B | Page 12 of 24
ADP3168
APPLICATION INFORMATION
The closest standard value for CDLY is 39 nF. Once CDLY has been
chosen, RDLY can be calculated for the current-limit latch-off
time using
The design parameters for a typical Intel VRD 10 compliant
CPU application are as follows:
•
•
•
•
•
•
Input voltage (VIN) = 12 V
VID setting voltage (VVID) = 1.500 V
Duty cycle (D) = 0.125
Nominal output voltage at no load (VONL) = 1.480 V
Nominal output voltage at 65 A load (VOFL) = 1.3955 V
Static output voltage drop based on a 1.3 mΩ load line (RO)
from no load to full load
1.96 ×tDELAY
RDLY
=
(3)
CDLY
If the result for RDLY is less than 200 kΩ, a smaller soft-start time
should be considered by recalculating the equation for CDLY, or a
longer latch-off time should be used. In no case should RDLY be
less than 200 k . In this example, a delay time of 8 ms gives
RDLY = 402 kΩ. The closest standard 5% value is 390 kΩ.
•
•
•
•
•
(VD) = VONL − VOFL = 1.480 V − 1.3955 V = 84.5 mV
Maximum output current (IO) = 65 A
Maximum output current step (∆IO) = 60 A
Number of phases (n) = 3
INDUCTOR SELECTION
The choice of inductance for the inductor determines the
ripple current in the inductor. Less inductance leads to more
ripple current, which increases the output ripple voltage and
conduction losses in the MOSFETs but allows using smaller
inductors and, for a specified peak-to-peak transient deviation,
less total output capacitance. Conversely, a higher inductance
means lower ripple current and reduced conduction losses but
requires larger inductors and more output capacitance for the
same peak-to-peak transient deviation. In any multiphase con-
verter, a practical value for the peak-to-peak inductor ripple
current is less than 50% of the maximum dc current in the
same inductor. Equation 4 shows the relationship between
the inductance, oscillator frequency, and peak-to-peak ripple
current in the inductor.
Switching frequency per phase (fSW) = 267 kHz
SETTING THE CLOCK FREQUENCY
The ADP3168 uses a fixed-frequency control architecture. The
frequency is set by an external timing resistor (RT). The clock
frequency and the number of phases determine the switching
frequency per phase, which relates directly to switching losses
and the sizes of the inductors and input and output capacitors.
With n = 3 for three phases, a clock frequency of 800 kHz sets
the switching frequency, fSW, of each phase to 267 kHz, which
represents a practical trade-off between the switching losses and
the sizes of the output filter components. Figure 3 shows that to
achieve an 800 kHz oscillator frequency, the correct value for RT
is 249 kΩ. Alternatively, the value for RT can be calculated using
Equation 5 can be used to determine the minimum inductance
based on a given output ripple voltage.
1
RT =
(1)
1
VVID
×
1− D
)
(
n × fSW × 5.83 pF −
)
IR
=
(4)
1.5MΩ
fSW × L
where 5.83 pF and 1.5 MΩ are internal IC component values.
For good initial accuracy and frequency stability, a 1% resistor
is recommended.
VVID × RO ×
1−
n × D
L ≥
(5)
fSW ×VRIPPLE
Solving Equation 5 for a 10 mV p-p output ripple voltage yields:
1.5 V ×1.3 mΩ × 1− 0.375
SOFT START AND CURRENT LIMIT LATCH-OFF
DELAY TIMES
= 456 nH
L ≥
267 kHz ×10 mV
Because the soft-start and current limit latch-off delay functions
share the DELAY pin, these two parameters must be considered
together. The first step is to set CDLY for the soft-start ramp. This
ramp is generated with a 20 µA internal current source. The
value of RDLY has a second-order impact on the soft-start time
because it sinks part of the current source to ground. However,
as long as RDLY is kept greater than 200 kΩ, this effect is minor.
The value for CDLY can be approximated using
If the resulting ripple voltage is less than that designed for, the
inductor can be made smaller until the ripple value is met. This
allows optimal transient response and minimum output
decoupling.
The smallest possible inductor should be used to minimize the
number of output capacitors. Choosing a 600 nH inductor is a
good starting point and gives a calculated ripple current of
8.2 A. The inductor should not saturate at the peak current of
25.8 A and should be able to handle the sum of the power
dissipation caused by the average current of 22.7 A in the
winding and core loss.
⎛
⎜
⎝
⎞
⎟
⎟
⎠
VVID
2 × RDLY
tss
VVID
⎜
CDLY = 20 µA −
×
(2)
where tSS is the desired soft-start time. Assuming an RDLY of
390 kΩ and a desired a soft-start time of 3 ms, CDLY is 36 nF.
Rev. B | Page 13 of 24
ADP3168
increased measurement error. A good rule is to have the DCR
be about 1 to 1½ times the droop resistance (RO). Our example
uses an inductor with a DCR of 1.6 mΩ.
Another important factor in the inductor design is the DCR,
which is used for measuring the phase currents. A large DCR
causes excessive power losses, while too small a value leads to
L1
470µF/16V × 6
1.6µH
NICHICON PW SERIES
V
12V
IN
+
+
C9
4.7µF
C1
C6
V
RTN
IN
U2
C8
ADP3418 100nF
D1
1N4148WS
D2
Q1
IPD12N03L
1
2
3
4
8
7
6
5
BST
IN
DRVH
SW
820µF/2.5V × 8
1N4148WS
L2
FUJITSU RE SERIES
600nH/1.6mΩ
V
CC(CORE)
8mΩ ESR (EACH)
0.8375V–1.6V
OD
PGND
DRVL
+
+
C10
4.7nF
R1
65A AVG, 74A PK
VCC
C28
C21
C7
V
CC(CORE) RTN
2.2Ω
4.7µF
Q3
IPD06N03L
Q2
IPD06N03L
10µF × 23MLCC
AROUND
SOCKET
D3
C13
4.7µF
C12
U3
1N4148WS
ADP3418100nF
Q4
IPD12N03L
1
2
3
4
8
7
6
5
BST
DRVH
L3
IN
SW
600nH/1.6mΩ
OD
PGND
DRVL
C14
4.7nF
VCC
C11
R2
4.7µF
2.2Ω
Q6
IPD06N03L
Q5
IPD06N03L
D4
C17
4.7µF
U4
ADP3418
1N4148WS
C16
100nF
Q7
IPD12N03L
1
2
3
4
BST
DRVH
8
7
6
5
L4
IN
SW
PGND
DRVL
600nH/1.6mΩ
OD
C18
4.7nF
VCC
R3
C15
2.2Ω
4.7µF
R
TH
100kΩ, 5%
Q9
IPD06N03L
Q8
IPD06N03L
+
R4
10Ω
C19
1µF
C20
33µF
U1
ADP3168
R
R
383kΩ
1
2
VID4
VID3
VID2
VID1
VID0
VID5
FBRTN
FB
VCC 28
PWM1 27
PWM2 26
3
FROM CPU
4
25
PWM3
PWM4
SW1
5
24
23
22
21
20
19
18
17
16
15
1
R
SW1
6
1
R
SW2
7
SW2
C
1.5nF
B
1
R
SW3
8
SW3
C
FB
33pF
R
PH3
124kΩ
9
R
COMP
ꢀ
SW4
PH1
124kΩ
R
C
R
A
B
A
POWER
GOOD
1.33kΩ 390pF 16.9kΩ
R
10
11
12
13
14
PWRGD
EN
GND
PH2
124kΩ
R
R
C
CS1
CS2
CS2
1.5nF
35.7kΩ 73.2kΩ
ENABLE
CSCOMP
CSSUM
CSREF
ILIMIT
DELAY
RT
C
CS1
2.2nF
C
DLY
39nF
R
DLY
390kΩ
R
T
249kΩ
RAMPADJ
R
LIM
200kΩ
NOTE:
1
FOR A DESCRIPTION OF OPTIONAL R
RESISTORS, SEE THE THEORY OF OPERATION SECTION.
SW
Figure 11. 65 A Intel Pentium 4-CPU Supply Circuit, VRD 10 Design
Rev. B | Page 14 of 24
ADP3168
DESIGNING AN INDUCTOR
OUTPUT DROOP RESISTANCE
Once the inductance and DCR are known, the next step is to
either design an inductor or find a standard inductor that
comes as close as possible to meeting the overall design goals.
It is also important to have the inductance and DCR tolerance
specified to control the accuracy of the system. 15% inductance
and 8% DCR (at room temperature) are reasonable tolerances
that most manufacturers can meet.
The design requires that the regulator output voltage measured
at the CPU pins drops when the output current increases. The
specified voltage drop corresponds to a dc output resistance (RO).
The output current is measured by summing together the
voltage across each inductor and passing the signal through a
low-pass filter. This summer filter is the CS amplifier config-
ured with resistors RPH(X) (summers), and RCS and CCS (filter).
The output resistance of the regulator is set by the following
equations, where RL is the DCR of the output inductors:
The first decision in designing the inductor is to choose the
core material. There are several possibilities for providing low
core loss at high frequencies. Two examples are the powder
cores (e.g., Kool-Mµ® from Magnetics, Inc. or Micrometals)
and the gapped soft ferrite cores (e.g., 3F3 or 3F4 from Philips).
Low frequency powdered iron cores should be avoided due to
their high core loss, especially when the inductor value is
relatively low and the ripple current is high.
RCS
RPH
( )
x
RO
=
× RL
(6)
(7)
L
CCS
=
RL × RCS
One has the flexibility of choosing either RCS or RPH(X). It is best
to select RCS equal to 100 kΩ, and then solve for RPH(X) by
rearranging Equation 6.
The best choice for a core geometry is a closed-loop type such
as a pot core, PQ, U, or E core or toroid. A good compromise
between price and performance is a core with a toroidal shape.
RL
There are many useful references for quickly designing a power
inductor, such as the following:
RPH
RPH
(
x
)
=
× RCS
RO
1.6 mΩ
1.3 mΩ
•
Magnetic Designer Software
Intusoft (www.intusoft.com)
=
( )
×100 kΩ = 123 kΩ
x
•
Designing Magnetic Components for High-Frequency
DC-DC Converters, by William T. McLyman, Kg
Magnetics, Inc., ISBN 1883107008
Next, use Equation 6 to solve for CCS.
600 nH
CCS
=
= 3.75 nF
1.6 mΩ ×100 kΩ
It is best to have a dual location for CCS in the layout so standard
values can be used in parallel to get as close to the value desired.
For this example, choosing CCS to be 1.5 nF and 2.2 nF in
parallel is a good choice. For best accuracy, CCS should be a 5%
or 10% NPO capacitor. The closest standard 1% value for RPH(X)
is 124 kΩ.
SELECTING A STANDARD INDUCTOR
The companies listed below can provide design consultation
and deliver power inductors optimized for high power
applications upon request.
Power Inductor Manufacturers
•
•
•
•
Coilcraft
(847)639-6400
www.coilcraft.com
Coiltronics
(561)752-5000
www.coiltronics.com
Sumida Electric Company
(510) 668-0660
www.sumida.com
Vishay Intertechnology
(402) 563-6866
www.vishay.com
Rev. B | Page 15 of 24
ADP3168
INDUCTOR DCR TEMPERATURE CORRECTION
4. Compute the relative values for RCS1, RCS2, and RTH using:
With the inductor’s DCR being used as the sense element and
copper wire being the source of the DCR, one needs to com-
pensate for temperature changes of the inductor’s winding.
Fortunately, copper has a well-known temperature coefficient
(TC) of 0.39%/°C.
(
A − B
)
× γ1 × γ2 × − A ×
(
1− B
)
× γ2 + B ×
(1− A)× γ1
RCS2
=
A ×
(1− B
)
× γ1 − B × 1− A
(
)
× γ2 − A − B)
(
(
1− A
)
RCS1
=
(8)
1
A
−
1− RCS2 γ1 − RCS2
If RCS is designed to have an opposite and equal percentage
change in resistance to that of the wire, it cancels the temper-
ature variation of the inductor’s DCR. Due to the nonlinear
nature of NTC thermistors, resistors RCS1 and RCS2 are needed
(see Figure 12) to linearize the NTC and produce the desired
temperature tracking.
1
RTH
=
1
1
−
1− RCS2 RCS1
5. Calculate RTH = RTH × RCS, then select the closest value of
thermistor available. Also compute a scaling factor k based
on the ratio of the actual thermistor value used relative to
the computed one:
PLACE AS CLOSE AS POSSIBLE
TO NEAREST INDUCTOR
TO
SWITCH
NODES
TO
OR LOW-SIDE MOSFET
RTH
V
(
ACTUAL)
OUT
(9)
k =
R
SENSE
TH
RTH
(
CALCULATED )
6. Finally, calculate values for RCS1 and RCS2 using Equation 10:
R
R
R
PH3
PH1
PH2
ADP3168
RCS1 = RCS × k × γCS1
(10)
RCS2 = RCS
×
((1− k
)
+
(k × γCS 2 ))
R
R
CS2
CS1
CSCOMP
CSSUM
CSREF
18
17
16
C
CS
1.8nF
KEEP THIS PATH
For this example, RCS has been chosen to be 100 kΩ , so we start
with a thermistor value of 100 kΩ. Looking through available
0603 size thermistors, we find a Vishay NTHS0603N01N1003JR
NTC thermistor with A = 0.3602 and B = 0.09174. From these
we compute RCS1 = 0.3796, RCS2 = 0.7195, and RTH = 1.0751.
Solving for RTH yields 107.51 kΩ, so we choose 100 kΩ, making
k = 0.9302. Finally, we find RCS1 and RCS2 to be 35.3 kΩ and
73.9 kΩ. Choosing the closest 1% resistor values yields a choice
of 35.7 kΩ and 73.2 kΩ.
AS SHORT AS POSSIBLE
AND WELL AWAY FROM
SWITCH NODE LINES
Figure 12. Temperature Compensation Circuit Values
The following procedure and expressions yield values to use for
RCS1, RCS2, and RTH (the thermistor value at 25°C) for a given RCS
value.
OUTPUT OFFSET
1. Select an NTC based on type and value. Because there is no
value yet, start with a thermistor with a value close to RCS.
The NTC should also have an initial tolerance of better
than 5%.
2. Based on the type of NTC, find its relative resistance
value at two temperatures. The temperatures that work
well are 50°C and 90°C. We will call these resistance values
A (RTH(50°C)/RTH(25°C)) and B (RTH(90°C)/RTH(25°C)). Note that
the NTC’s relative value is always 1 at 25°C.
Intel’s specification requires that at no load the nominal output
voltage of the regulator be offset to a lower value than the
nominal voltage corresponding to the VID code. The offset is
set by a constant current source flowing out of the FB pin (IFB)
and flowing through RB. The value of RB can be found using
Equation 11:
VVID −VONL
RB =
IFB
3. Find the relative value of RCS required for each of these
temperatures. This is based on the percentage change
needed, which in this example is initially 0.39%/°C.
These are called r1 (1/(1 + TC × (T1 − 25))) and r2
(1/(1 + TC × (T2 − 25))), where TC = 0.0039, T1 = 50°C,
and T2 = 90°C.
(11)
1.5V −1.480 V
RB =
= 1.33 kΩ
15 µA
The closest standard 1% resistor value is 1.33 kΩ.
Rev. B | Page 16 of 24
ADP3168
COUT SELECTION
The required output decoupling for the regulator is typically
recommended by Intel for various processors and platforms.
One can also use some simple design guidelines to determine
what is required. These guidelines are based on having both
bulk and ceramic capacitors in the system.
For our example, 23 10 µF 1206 MLC capacitors (CZ = 230 µF)
were used. The VID on-the-fly step change is 250 mV in 150 µs
with a setting error of 2.5 mV. Solving for the bulk capacitance
yields
⎛
⎞
600 nH × 60 A
3 ×1.3 mΩ ×1.5 V
⎜
⎜
⎟
Cx
Cx
≤
)
− 230 µF = 5.92 mF
(
(
MIN
The first thing is to select the total amount of ceramic capaci-
tance. This is based on the number and type of capacitor to be
used. The best location for ceramics is inside the socket, with
12 to 18 of size 1206 being the physical limit. Others can be
placed along the outer edge of the socket as well.
⎟
⎠
⎝
600 nH × 250 mV
≤
)
×
MAX
2
)
3 × 4.62 ×
(1.3 mΩ
×1.5 V
2
⎛
⎜
⎞
⎛
⎞
⎟
150 µs ×1.5 V × 3 × 4.6 ×1.3 mΩ
250 mV × 600 nH
⎜
⎜
⎟
⎟
1+
−1 − 230 µF
⎜
⎜
⎝
⎟
Combined ceramic values of 200 µF to 300 µF are recom-
mended, usually made up of multiple 10 µF or 22 µF capacitors.
Select the number of ceramics and then find the total ceramic
capacitance (CZ).
⎟
⎠
⎝
⎠
= 23.9 mF
where k = 4.6
Using eight 820 µF A1-Polys with a typical ESR of 8 mΩ each
yields CX = 6.56 mF with an RX = 1.0 mΩ.
Next, there is an upper limit imposed on the total amount of
bulk capacitance (CX) when one considers the VID on-the-fly
voltage stepping of the output (voltage step VV in time tV with
error of VERR) and a lower limit based on meeting the critical
capacitance for load release for a given maximum load step ∆IO:
One last check should be made to ensure that the ESL of the
bulk capacitors (LX) is low enough to limit the initial high
frequency transient spike. This is tested using
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
L × Δ IO
Cx
Cx
≥
MIN )
−Cz
(12)
(
(
Lx ≤ Cz × R
n × RO ×VVID
(14)
2
)
Lx ≤ 230 µF ×
(
1.3 mΩ
= 389 pH
≤
)
MAX
In this example, LX is 375 pH for the eight A1-Polys capacitors,
which satisfies this limitation. If the LX of the chosen bulk
capacitor bank is too large, the number of capacitors must be
increased.
2
⎛
⎞
⎛
⎜
⎝
⎞
⎟
⎟
⎠
⎜
⎟
L
VV
VVID nKRO
⎜
×
×
1+ tv
×
−1 − Cz (13)
⎜
⎜
⎝
⎟
nK 2RO2 VVID
VV
L
⎟
⎠
One should note that for this multimode control technique, all
ceramic designs can be used as long as the conditions of
Equations 11, 12, and 13 are satisfied.
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
VERR
VV
where K = 1n
To meet the conditions of these expressions and transient re-
sponse, the ESR of the bulk capacitor bank (RX) should be less
than two times the droop resistance, RO. If the CX(MIN) is larger
than CX(MAX), the system does not meet the VID on-the-fly
specification and may require the use of a smaller inductor or
more phases (and may have to increase the switching frequency
to keep the output ripple the same).
Rev. B | Page 17 of 24
ADP3168
MOSFET input capacitance, the following expression provides
an approximate value for the switching loss per main MOSFET,
where nMF is the total number of main MOSFETs:
POWER MOSFETS
For this example, the N-channel power MOSFETs have been
selected for one high-side switch and two low-side switches per
phase. The main selection parameters for the power MOSFETs
are VGS(TH), QG, CISS, CRSS, and RDS(ON). The minimum gate drive
voltage (the supply voltage to the ADP3418) dictates whether
standard threshold or logic-level threshold MOSFETs must be
used. With VGATE ~10 V, logic-level threshold MOSFETs (VGS(TH)
<2.5 V) are recommended.
VCC × IO
nMF
nMF
n
P
= 2 × fSW
)
×
× RG ×
× CISS
(16)
S
(
MF
Here, RG is the total gate resistance (2 Ω for the ADP3418 and
about 1 Ω for typical high speed switching MOSFETs, making
RG = 3 Ω) and CISS is the input capacitance of the main
MOSFET. Note that adding more main MOSFETs (nMF) does
not really help the switching loss per MOSFET because the
additional gate capacitance slows switching. The best thing to
reduce switching loss is to use lower gate capacitance devices.
The maximum output current IO determines the RDS(ON) require-
ment for the low-side (synchronous) MOSFETs. The ADP3168,
balances currents between phases, thus the current in each low-
side MOSFET is the output current divided by the total number
of MOSFETs (nSF). With conduction losses being dominant, the
following expression shows the total power being dissipated in
each synchronous MOSFET in terms of the ripple current per
phase (IR) and average total output current (IO):
The conduction loss of the main MOSFET is given by the
following, where RDS(MF) is the ON resistance of the MOSFET:
2
2
⎡
⎢
⎤
⎥
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
IO
n × IR
nMF
1
P
= D ×
+
×
× RDS
(17)
C
(
MF
)
(
MF
)
nMF
12
⎢
⎣
⎥
⎦
2
2
⎡
⎢
⎤
⎥
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
IO
n IR
nSF
1
P
=
(1− D
)
×
+
×
× RDS
(15)
)
SF
(
SF
Typically, for main MOSFETs, the highest speed (low CISS
)
nSF
12
⎢
⎥
⎣
⎦
device is preferred, but these usually have higher ON resistance.
Select a device that meets the total power dissipation (about
1.5 W for a single D-PAK) when combining the switching and
conduction losses.
Knowing the maximum output current being designed for and
the maximum allowed power dissipation, one can find the
required RDS(ON) for the MOSFET. For D-PAK MOSFETs up to
an ambient temperature of 50°C, a safe limit for PSF is 1 W to
1.5 W at 120°C junction temperature. Thus, for this example
(65 A maximum), we find RDS(SF) (per MOSFET) < 8.7 mΩ.
This RDS(SF) is also at a junction temperature of about 120°C,
so we need to make sure we account for this when making
this selection. For this example, we selected two lower-side
MOSFETs at 7 mΩ each at room temperature, which gives
8.4 mΩ at high temperature.
For this example, an Infineon IPD12N03L was selected as the
main MOSFET (three total; nMF = 3), with a CISS = 1460 pF
(max) and RDS(MF) = 14 mΩ (max at TJ = 120°C), and an
Infineon IPD06N03L was selected as the synchronous
MOSFET (six total; nSF = 6), with CISS = 2370 pF (max) and
RDS(SF) = 8.4 mΩ (max at TJ = 120°C). The synchronous
MOSFET CISS is less than 3000 pF, satisfying that requirement.
Solving for the power dissipation per MOSFET at IO = 65 A and
IR = 8.2 A yields 863 mW for each synchronous MOSFET and
1.44 W for each main MOSFET. These numbers work well
considering there is usually more PCB area available for each
main MOSFET vs. each synchronous MOSFET.
Another important factor for the synchronous MOSFET is
the input capacitance and feedback capacitance. The ratio
of the feedback to input needs to be small (less than 10%
is recommended) to prevent accidental turn-on of the
synchronous MOSFETs when the switch node goes high.
One last thing to consider is the power dissipation in the driver
for each phase. This is best described in terms of the QG for the
MOSFETs and is given by the following, where QGMF is the total
gate charge for each main MOSFET and QGSF is the total gate
charge for each synchronous MOSFET:
Also, the time to switch the synchronous MOSFETs off should
not exceed the nonoverlap dead time of the MOSFET driver
(40 ns typical for the ADP3418). The output impedance of
the driver is about 2 Ω and the typical MOSFET input gate
resistances are about 1 Ω to 2 Ω, so a total gate capacitance of
less than 6000 pF should be adhered to. Because there are
two MOSFETs in parallel, the input capacitance for each
synchronous MOSFET should be limited to 3000 pF.
⎡
⎤
fSW
PDRV
=
×
(nMF × QGMF + nSF × QGSF
)
+ ICC ⎥ ×VCC (18)
⎢
⎣
2 × n
⎦
Also shown is the standby dissipation factor (ICC × VCC) for
the driver. For the ADP3418, the maximum dissipation should
be less than 400 mW. For our example, with ICC = 7 mA,
QGMF = 22.8 nC, and QGSF = 34.3 nC, we find 260 mW in each
driver, which is below the 400 mW dissipation limit. See the
ADP3418 data sheet for more details.
The high-side (main) MOSFET must be able to handle two
main power dissipation components: conduction and switching
losses. The switching loss relates to the amount of time it takes
for the main MOSFET to turn on and off, and to the current
and voltage that are being switched. Basing the switching speed
on the rise and fall time of the gate driver impedance and
Rev. B | Page 18 of 24
ADP3168
RAMP RESISTOR SELECTION
The ramp resistor (RR) is used for setting the size of the internal
PWM ramp. The value of this resistor is chosen to provide the
best combination of thermal balance, stability, and transient
response. This expression determines the optimum value:
For values of RLIM greater than 500 kΩ, the current limit may
be lower than expected, so some adjustment of RLIM may be
needed. Here, ILIM is the average current limit for the output of
the supply. For our example, choosing 120 A for ILIM, we find
RLIM to be 200 kΩ, for which we chose 200 kΩ as the nearest
1% value.
AR × L
RR =
3 × AD × RDS × CR
(19)
The per-phase current limit described earlier has its limit
determined by the following:
0.2 × 600 nH
3 × 5 × 4.2 mΩ × 5 pF
RR =
= 381kΩ
VCOMP
) −VR −VBIAS
IR
(
MAX
where AR is the internal ramp amplifier gain, AD is the current
balancing amplifier gain, RDS is the total low-side MOSFET ON
resistance, and CR is the internal ramp capacitor value. The
closest standard 1% resistor value is 383 kΩ.
IPHLIM
≅
+
(23)
AD × RDS
2
(
MAX
)
For the ADP3168, the maximum COMP voltage (VCOMP(MAX)) is
3.3 V, the COMP pin bias voltage (VBIAS) is 1.2 V, and the
current balancing amplifier gain (AD) is 5. Using VR of 0.63 V
and RDS(MAX) of 4.2 mΩ (low-side ON resistance at 150°C), we
find a per-phase limit of 66 A.
The internal ramp voltage magnitude can be calculated using
AR ×
(
1− D
RR × CR × fSW
0.2 × 1− 0.125
383 kΩ × 5 pF × 267 kHz
)
× VVID
VR =
VR =
(20)
(
)
×1.5V
This limit can be adjusted by changing the ramp voltage VR, but
make sure not to set the per-phase limit lower than the average
per-phase current (ILIM/n).
The size of the internal ramp can be made larger or smaller. If
it is made larger, stability and transient response improve, but
thermal balance degrades. Likewise, if the ramp is made
smaller, thermal balance improves at the sacrifice of transient
response and stability. The factor of three in the denominator of
Equation 19 sets a ramp size that gives an optimal balance for
good stability, transient response, and thermal balance.
There is also a per-phase initial duty cycle limit determined by
VCOMP
) −VBIAS
(
MAX
DMAX = D ×
(24)
VRT
For this example, the maximum duty cycle is found to be 0.42.
FEEDBACK LOOP COMPENSATION DESIGN
COMP PIN RAMP
Optimized compensation of the ADP3168 allows the best
possible response of the regulator’s output to a load change. The
basis for determining the optimum compensation is to make
the regulator and output decoupling appear as an output
impedance that is entirely resistive over the widest possible
frequency range, including dc, and equal to the droop resistance
(RO). With the resistive output impedance, the output voltage
droops in proportion with the load current at any load current
slew rate; this ensures the optimal positioning and allows the
minimization of the output decoupling.
There is a ramp signal on the COMP pin due to the droop
voltage and output voltage ramps. This ramp amplitude adds to
the internal ramp to produce the following overall ramp signal
at the PWM input.
VR
VRT
=
(21)
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
2 ×
(
1− n × D
)
1−
n × fSW × CX × RO
For this example, the overall ramp signal is found to be 0.63 V.
CURRENT-LIMIT SET POINT
With the multimode feedback structure of the ADP3168, the
feedback compensation must be set to make the converter’s
output impedance, working in parallel with the output
decoupling, meet this goal. There are several poles and zeros
created by the output inductor and decoupling capacitors
(output filter) that need to be compensated for.
To select the current-limit set point, first find the resistor value
for RLIM. The current limit threshold for the ADP3168 is set
with a 3 V source (VLIM) across RLIM with a gain of 10.4 mV/µA
(ALIM). RLIM can be found using the following:
ALIM ×VLIM
ILIM × RO
RLIM
=
(22)
A type-three compensator on the voltage feedback is adequate
for proper compensation of the output filter. The expressions
given in Equations 25 to 29 are intended to yield an optimal
starting point for the design; some adjustments may be
necessary to account for PCB and component parasitic effects
(see the Tuning Procedure for the ADP3168).
Rev. B | Page 19 of 24
ADP3168
The first step is to compute the time constants for all of the poles and zeros in the system:
RL × VRT
VDID
2 × L ×
(
1− n × D
)
× VRT
RE = n × RO × AD × RDS
+
+
n × CX × RO × VVID
1.6 mΩ × 0.63V 2 × 600 nH ×
1− 0.375
× 0.63 V
RE = 3 ×1.3 mΩ+ 5 × 4.2 mΩ+
+
37.9 mΩ
(25)
1.5 V
3 × 6.56 mF ×1.3 mΩ ×1.5 V
LX RO − R'
375 pH 1.3 mΩ− 0.6 mΩ
TA = CX
×
(
RO − R'
)
+
×
= 6.56 mF ×
(
1.3 mΩ− 0.6 mΩ
)
+
×
= 4.79 µs
(26)
(27)
RO
RX
1.3 mΩ
1.0 mΩ
TB =
TC =
(
RX + R'−RO
)
× CX
=
(
1.0 mΩ+ 0.6 mΩ−1.3 mΩ
)
× 6.56 mF = 1.97 µs
⎛
⎞
⎟
⎟
⎠
⎛
⎞
AD × RDS
2 × fSW
5 × 4.2 mΩ
2 × 267 kHz
⎜
⎜
⎟
⎟
VRT × L −
0.63 V × 600 nH =
⎜
⎜
⎝
⎝
⎠
=
= 6.2 µs
(28)
(29)
VVID × RE
1.5 V × 37.9 mΩ
2
CX × CZ × RO2
RO − R' + CZ × RO 6.56 mF ×
6.56 mF × 230 µF ×
1.3 mΩ− 0.6 mΩ
1.3 mΩ
)
TD
=
=
= 521 ns
CX
×
(
)
(
)
+ 230 µF ×1.3 mΩ
where, for the ADP3168, R' is the PCB resistance from the bulk capacitors to the ceramics and where RDS is the total low side MOSFET
ON resistance per phase. For this example, AD is 5, VRT equals 0.63 V, R' is approximately 0.6 mΩ (assuming a 4-layer motherboard), and
LX is 375 pH for the eight Al-Poly capacitors.
The compensation values can be solved using the following:
Figure 13 shows the typical transient response using the
compensation values.
n × RO × TA
CA
=
RE × RB
(30)
3 ×1.3 mΩ × 4.79 µs
37.9 mΩ ×1.33 kΩ
CA =
RA =
= 371 pF
TC
6.2 µs
=
= 16.7 kΩ
(31)
(32)
(33)
CA 371 pF
TB
1.97 µs
CB
=
=
= 1.48 nF
= 31.2 pF
RB 1.33 kΩ
TD
521 ns
CFB
=
=
RA 16.7 kΩ
Figure 13. Typical Transient Response for Design Example
Choosing the closest standard values for the components yields
CA = 390 pF, RA = 16.9 kΩ, CB = 1.5 nF, CFB = 33 pF
Rev. B | Page 20 of 24
ADP3168
CIN SELECTION AND INPUT CURRENT
DI/DT REDUCTION
TUNING PROCEDURE FOR THE ADP3168
1. Build circuit based on compensation values computed
from design spreadsheet.
2. Hook up dc load to circuit, turn on, and verify operation.
Also check for jitter at no-load and full-load.
DC Loadline Setting
In continuous inductor current mode, the source current of the
high-side MOSFET is approximately a square wave with a duty
ratio equal to n × VOUT/VIN and an amplitude of one-nth of the
maximum output current. To prevent large voltage transients, a
low ESR input capacitor sized for the maximum rms current
must be used. The maximum rms capacitor current is given by
3. Measure output voltage at no-load (VNL). Verify that it is
within tolerance.
1
4. Measure output voltage at full-load cold (VFLCOLD). Let
board set for ~10 minutes at full-load and measure output
(VFLHOT). If there is a change of more than a couple of
millivolts, adjust RCS1 and RCS2 using Equations 35 and 37.
5. Repeat Step 4 until cold and hot voltage measurements
remain the same.
ICRMS = D × IO
×
−1
N × D
(34)
1
ICRMS = 0.125 × 65 A ×
−1 =10.5A
3× 0.125
Note that the capacitor manufacturer’s ripple current ratings are
often based on only 2,000 hours of life. This makes it advisable
to further derate the capacitor or choose a capacitor rated at a
higher temperature than required. Several capacitors may be
placed in parallel to meet size or height requirements in the
design. In this example, the input capacitor bank is formed by
three 2,200 µF, 16 V Nichicon capacitors with a ripple current
rating of 3.5 A each.
6. Measure output voltage from no-load to full-load using 5 A
steps. Compute the loadline slope for each change and then
average to get overall loadline slope (ROMEAS).
7. If ROMEAS is off from RO by more than 0.05 mΩ, use the
following to adjust the RPH values:
ROMEAS
RPH
) = RPH ×
(OLD)
(36)
(
NEW
RO
To reduce the input current di/dt to a level below the
recommended maximum of 0.1 A/µs, an additional small
inductor (L > 1 µH @ 15 A) should be inserted between the
converter and the supply bus. That inductor also acts as a filter
between the converter and the primary power source.
8. Repeat Steps 6 and 7 to check loadline and repeat
adjustments if necessary.
9. Once complete with dc loadline adjustment, do not change
RPH, RCS1, RCS2, or RTH for rest of procedure.
10. Measure output ripple at no-load and full-load with scope
and make sure it is within specifications.
V
V
NL −VFLCOLD
NL −VFLHOT
RCS2
) = RSC2 ×
(OLD)
(35)
(
NEW
(37)
1
RCS 2
=
NEW )
(
RCS1 ) + RTH
(25°C )
1
(
OLD
−
RCS1 ) × RTH
+
(
RCS1 ) − RCS 2
)
×
(
RCS1 ) − RTH
)
RTH
(25°C
(
OLD
(
25°C
)
(
OLD
(
NEW
)
(
OLD
(
25°C
)
)
100
90
80
70
60
50
40
30
20
10
0
0
10
20
30
40
50
60
OUTPUT CURRENT (A)
Figure 14. Efficiency of the Circuit of Figure 11 vs. Output Current
Rev. B | Page 21 of 24
ADP3168
AC Loadline Setting
11. Remove dc load from circuit and hook up dynamic load.
12. Hook up scope to output voltage and set to dc coupling
with time scale at 100 µs/div.
V
DROOP
13. Set dynamic load for a transient step of about 40 A at 1
kHz with 50% duty cycle.
14. Measure output waveform (may have to use dc offset on
scope to see waveform). Try to use vertical scale of 100
mV/div or finer.
V
TRAN1
V
TRAN2
15. This waveform should look something like Figure 15. Use
the horizontal cursors to measure VACDRP and VDCDRP as
shown. Do not measure the undershoot or overshoot that
happens immediately after the step.
Figure 16. Transient Setting Waveform
20. If both overshoots are larger than desired, try making the
adjustments described below. (Note: If these adjustments
do not change the response, you are limited by the output
decoupling.) Check the output response each time you
make a change as well as the switching nodes (to make sure
the response is still stable).
V
ACDRP
a. Make ramp resistor larger by 25% (RRAMP).
V
DCDRP
b. For VTRAN1, increase CB or increase switching
frequency.
c. For VTRAN2, increase RA and decrease CA by 25%.
21. For load release (see Figure 17), if VTRANREL is larger than
Figure 15. AC Loadline Waveform
VTRAN1 (see Figure 16), there is not enough output
16. If the VACDRP and VDCDRP are different by more than a few
millivolts, use Equation 38 to adjust CCS. Parallel different
values to get the right one because there are limited
standard capacitor values available. (Make sure that there
are locations for two capacitors in the layout for this.)
VACDRP
capacitance. You will either need more capacitance or have
to make the inductor values smaller. (If you change
inductors, you will need to start the design over using the
spreadsheet and this tuning procedure.)
CCS
= CCS ×
(OLD)
(38)
(
NEW
)
VDCDRP
V
TRANREL
17. Repeat Steps 11 to 13, making adjustments if necessary.
Once complete, do not change CCS again in the procedure.
18. Set dynamic load step to maximum step size (do not use a
step size larger than needed) and verify that the output
waveform is square (which means VACDRP and VDCDRP are
equal).Make sure load step slew rate and turn-on are set for
a slew rate of ~150 A/µs to 250 A/µs (for example, a load
step of 50 A should take 200 ns to 300 ns) with no overshoot.
Some dynamic loads have an excessive turn-on overshoot if
a minimum current is not set properly. (This is an issue if
using a VTT tool.)
V
DROOP
Figure 17. Transient Setting Waveform
Because the ADP3168 turns off all of the phases (switches
inductors to ground), there is no ripple voltage present during
load release. Thus, you do not have to add headroom for ripple,
allowing your load release VTRANREL to be larger than VTRAN1 by
the amount of ripple and still meet specifications.
Initial Transient Setting
19. With dynamic load still set at maximum step size, expand
scope time scale to see 2 µs/div to 5 µs/div. The waveform
may have two overshoots and one minor undershoot (see
Figure 16). Here, VDROOP is the final desired value.
If VTRAN1 and VTRANREL are less than the desired final droop, this
implies that capacitors can be removed. When removing
capacitors, check the output ripple voltage as well to make sure
it is still within specifications.
Rev. B | Page 22 of 24
ADP3168
The output capacitors should be connected as close as possible
to the load (or connector) that receives the power (e.g., a
microprocessor core). If the load is distributed, the capacitors
should also be distributed and generally in proportion to where
the load tends to be more dynamic.
LAYOUT AND COMPONENT PLACEMENT
The following guidelines are recommended for optimal
performance of a switching regulator in a PC system. Key layout
issues are illustrated in Figure 18.
SWITCH NODE
PLANES
Avoid crossing signal lines over the switching power path loop,
as described next.
12V CONNECTOR
INPUT POWER PLANE
POWER CIRCUITRY
The switching power path should be routed on the PCB to
encompass the shortest possible length in order to minimize
radiated switching noise energy (i.e., EMI) and conduction
losses in the board. Failure to take proper precautions often
results in EMI problems for the entire PC system as well as
noise-related operational problems in the power converter
control circuitry. The switching power path is the loop formed
by the current path through the input capacitors and the power
MOSFETs including all interconnecting PCB traces and planes.
Using short and wide interconnection traces is critical in this
path because it minimizes the inductance in the switching loop,
which can cause high energy ringing, and it accommodates the
high current demand with minimal voltage loss.
THERMISTOR
KEEP-OUT
AREA
OUTPUT
POWER
PLANE
KEEP-OUT
AREA
KEEP-OUT
AREA
CPU
SOCKET
KEEP-OUT
AREA
Figure 18. Layout Recommendations
Whenever a power dissipating component (e.g., a power
MOSFET) is soldered to a PCB, the liberal use of vias, both
directly on the mounting pad and immediately surrounding it,
is recommended. Two important reasons for this are improved
current rating through the vias and improved thermal
performance from vias extended to the opposite side of the
PCB, where a plane can more readily transfer the heat to the air.
Make a mirror image of any pad being used to heat sink the
MOSFETs on the opposite side of the PCB to achieve the best
thermal dissipation to the air around the board. To further
improve thermal performance, use the largest possible pad area.
GENERAL RECOMMENDATIONS
For good results, a PCB with at least four layers is recom-
mended. This should allow the needed versatility for control
circuitry interconnections with optimal placement, power
planes for ground, input, and output power, and wide inter-
connection traces in the rest of the power delivery current
paths. Keep in mind that each square unit of 1 ounce copper
trace has a resistance of ~0.53 mΩ at room temperature.
Whenever high currents are routed between PCB layers, vias
should be used liberally to create several parallel current paths
so that the resistance and inductance introduced by the current
paths is minimized and the via current rating is not exceeded.
The output power path should also be routed to encompass a
short distance. The output power path is formed by the current
path through the inductor, the output capacitors, and the load.
If critical signal lines (including the output voltage sense lines
of the ADP3168) must cross through power circuitry, it is best
if a signal ground plane can be interposed between those signal
lines and the traces of the power circuitry. This creates a shield
to minimize noise injection into the signals at the expense of
making signal ground a bit noisier.
For best EMI containment, a solid power ground plane should
be used as one of the inner layers extending fully under all the
power components.
SIGNAL CIRCUITRY
The output voltage is sensed and regulated between the FB pin
and the FBRTN pin, which connects to the signal ground at the
load. To avoid differential mode noise pickup in the sensed
signal, the loop area should be small. Thus the FB and FBRTN
traces should be routed adjacent to each other on top of the
power ground plane back to the controller.
An analog ground plane should be used around and under the
ADP3168 as a reference for the components associated with the
controller. This plane should be tied to the nearest output de-
coupling capacitor ground and should not be tied to any other
power circuitry to prevent power currents from flowing in it.
The components around the ADP3168 should be located close
to the controller with short traces. The most important traces to
keep short and away from other traces are the FB and CSSUM
pins. See Figure 18 for details on layout for the CSSUM node.
Connect the feedback traces from the switch nodes as close as
possible to the inductor. The CSREF signal should be connected
to the output voltage at the nearest inductor to the controller.
Rev. B | Page 23 of 24
ADP3168
OUTLINE DIMENSIONS
9.80
9.70
9.60
28
15
4.50
4.40
4.30
6.40 BSC
1
14
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
8°
0°
0.75
0.60
0.45
0.30
0.19
0.20
0.09
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AE
Figure 19. 28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADP3168JRU-REEL7
ADP3168JRU-REEL
ADP3168JRUZ-REEL1
Temperature Range
Package Options
RU-28 (TSSOP-28)
RU-28 (TSSOP-28)
RU-28 (TSSOP-28)
Quantity per Reel
0°C to 85°C
0°C to 85°C
0°C to 85°C
1000
2500
2500
1 Z = Pb-free part.
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03258-0-12/04(B)
Rev. B | Page 24 of 24
相关型号：
ADP3170JRUZ-REEL
IC SWITCHING CONTROLLER, PDSO20, TSSOP-20, Switching Regulator or Controller
ONSEMI
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