ADP3189_技术文档

8-Bit Programmable 2- to 5-Phase

Synchronous Buck Controller

ADP3189

This device uses a multi-mode PWM architecture to drive the

logic-level outputs at a programmable switching frequency that

can be optimized for VR size and efficiency. The phase relation-

ship of the output signals can be programmed to provide 2-, 3-,

4-, or 5-phase operation, allowing for the construction of up to

five complementary buck switching stages.

FEATURES

Selectable 2-, 3-, 4-, or 5-phase operation at up

to 1 MHz per phase

±±7± ꢀV worst-case differential sensing error over

teꢀperature

Logic-level PWM outputs for interface to external

high-power drivers

The ADP3189 also includes programmable no-load offset and

slope functions to adjust the output voltage as a function of the

load current, so it is optimally positioned for a system transient.

The ADP3189 also provides accurate and reliable short-circuit

protection, adjustable current limiting, and a delayed power

good output that accommodates on-the-fly output voltage

changes requested by the CPU.

Active current balancing between all output phases

Built-in power good/crowbar blanking supports on-the-fly

VID code changes

Digitally prograꢀꢀable 075 V to 176 V output— supports

both VR107x and VR11 specifications

Prograꢀꢀable short-circuit protection with prograꢀꢀable

latch-off delay

ADP3189 is specified over the extended commercial tem-

perature range of 0°C to +85°C and is available in a

40-lead LFCSP package.

APPLICATIONS

Desktop PC power supplies for

Next generation Intel® processors

VRM ꢀodules

¹Protected by U.S. Patent Number 6,683,441; others pending.

GENERAL DESCRIPTION

The ADP3189¹is a highly efficient multi-phase synchronous

buck switching regulator controller optimized for converting a

12 V main supply into the core supply voltage required by high

performance Intel processors. It uses an internal 8-bit DAC to

read a voltage identification (VID) code directly from the

processor, which is used to set the output voltage between 0.5 V

and 1.6 V.

Rev7 0

Inforꢀation furnished by Analog Devices is believed to be accurate and reliable7 However, no

responsibility is assuꢀed by Analog Devices for its use, nor for any infringeꢀents of patents or other

rights of third parties that ꢀay result froꢀ its use7 Specifications subject to change without notice7 No

license is granted by iꢀplication or otherwise under any patent or patent rights of Analog Devices7

Tradeꢀarks and registeredtradeꢀarks arethe property of their respective owners7

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ADP3189

TABLE OF CONTENTS

Functional Block Diagram .............................................................. 3

Current Limit Latch-Off Delay Times..................................... 22

Inductor Selection...................................................................... 23

Designing an Inductor............................................................... 23

Selecting a Standard Inductor .............................................. 23

Current Sense Amplifier............................................................ 24

Inductor DCR Temperature Correction ................................. 24

Load Line Setting........................................................................ 25

Output Offset.............................................................................. 26

C_OUTSelection ............................................................................. 26

Power MOSFETs......................................................................... 27

Ramp Resistor Selection............................................................ 28

COMP Pin Ramp ....................................................................... 28

Current Limit SetPoint .............................................................. 29

Feedback Loop Compensation Design.................................... 29

C_INSelection and Input Current di/dt Reduction.................. 31

Thermal Monitor Design .......................................................... 31

Tuning the ADP3189 ................................................................. 32

DC Loadline Setting .............................................................. 32

AC Loadline Setting............................................................... 33

Initial Transient Setting......................................................... 33

Layout and Component Placement ......................................... 34

General Recommendations .................................................. 34

Power Circuitry Recommendations .................................... 34

Signal Circuitry Recommendations .................................... 34

Outline Dimensions....................................................................... 35

Ordering Guide .......................................................................... 35

Specifications..................................................................................... 4

Test Circuits....................................................................................... 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function DescriptionS ............................ 9

Typical Performance Characteristics ........................................... 11

Theory of Operation ...................................................................... 12

Start-Up Sequence...................................................................... 12

Phase Detection Sequence......................................................... 12

Master Clock Frequency............................................................ 13

Output Voltage Differential Sensing........................................ 13

Output Current Sensing ............................................................ 13

Active Impedance Control Mode............................................. 13

Current Control Mode and Thermal Balance ........................ 13

Voltage Control Mode................................................................ 14

Delay Timer................................................................................. 14

Soft Start ...................................................................................... 14

Current Limit, Short Circuit, and Latch-Off Protection....... 15

Dynamic VID.............................................................................. 15

Power Good Monitoring ........................................................... 15

Output Crowbar ......................................................................... 16

Output Enable and UVLO ........................................................ 16

Thermal Monitoring .................................................................. 16

Application Information................................................................ 22

Setting the Clock Frequency..................................................... 22

Soft Start Delay Time................................................................. 22

REVISION HISTORY

7/05—Revision 0: Initial Version

Rev. 0 | Page 2 of 36

ADP3189

FUNCTIONAL BLOCK DIAGRAM

VCC

RT RAMPADJ

12 13

31

ADP3189

UVLO

19

SHUTDOWN

AND BIAS

OSCILLATOR

OD

SET EN

RESET

30

29

CMP

PWM1

PWM2

18

GND

CMP

RESET

850mV

CURRENT

BALANCING

CIRCUIT

2-/3-/4-/5-PHASE

DRIVER LOGIC

1

EN

DAC + 150mV

CSREF

28

27

26

CMP

RESET

PWM3

PWM4

PWM5

CMP

DAC – 250mV

CMP

CROWBAR

2

PWRGD

DELAY

CURRENT

LIMIT

25

24

23

22

21

SW1

SW2

SW3

SW4

SW5

10

TTSENSE

VRHOT

THERMAL

THROTTLING

CONTROL

9

8

VRFAN

17

15

CSCOMP

CSREF

11

7

ILIMIT

CURRENT

LIMIT

CIRCUIT

DELAY

16

CSSUM

4

FB

5

3

COMP

+

–

14

LLSET

PRECISION

REFERENCE

BOOT

FBRTN

VOLTAGE

& SOFT-START

CONTROL

6

SS

VID

DAC

40

VIDSEL

32

33

34

35

36

37

38

39

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

Figure 1.

Rev. 0 | Page 3 of 36

ADP3189

SPECIFICATIONS

VCC = 12 V, FBRTN = GND, T_A= 0°C to 85°C, unless otherwise noted.¹

Table 1.

Paraꢀeter

Syꢀbol

Conditions

Min

Typ

Max

Unit

ERROR AMPLIFIER

Output Voltage Range²

Accuracy

V_COMP

V_FB

0.95

3.95

V

Relative to nominal DAC output, referenced to

FBRTN,

LLSET = CSREF, Figure 2,

VIDSEL = GND,

VIDSEL = 1.25 V,

−7.7

+7.7

mV

VID Range 1.00625 V to 1.60000 V

V_FB(BOOT)

In start-up

CSREF − LLSET = 80 mV

1.092 1.1

1.108

−82

+1

V

Load Line Positioning Accuracy

Differential Non-Linearity

Line Regulation

−78

−1

−80

mV

LSB

%

VCC = 10 V to 14 V

0.003

15

ΔV_FB

I_FB

I_FBRTN

I_COMP

GBW_(ERR)

Input Bias Current

FBRTN Current

Output Current

Gain Bandwidth Product

Slew Rate

13.5

16.5

200

μA

MHz

V/μs

125

500

20

FB forced to V_OUT− 3%

COMP = FB

25

LLSET Input Voltage Range

LLSET Input Bias Current

BOOT Voltage Hold Time

VID INPUTS

V_LLSET

I_LLSET

t_BOOT

Relative to CSREF

−250

−120

+250 mV

+120 nA

ms

C_DELAY= 10 nF

2

Input Low Voltage

V_IL(VID)

V_IH(VID)

VIDx, VIDSEL

0.4

V

μA

ns

Input High Voltage

Max V_IHfor VID on Fly²

Input Current

VID Transition Delay Time²

No CPU Detection Turn-Off Delay

Time²

0.8

1.26

I_IN(VID)

−1

VID code change to FB change

VID code change to PWM going low

200

OSCILLATOR

Frequency Range²

Frequency Variation

f_OSC

f_PHASE

0.25

180

5

220

MHz

kHz

V

T_A= 25°C, R_T= 243 kΩ, 5-phase

T_A= 25°C, R_T= 113 kΩ, 5-phase

T_A= 25°C, R_T= 51 kΩ, 5-phase

R_T= 243 kΩ to GND

200

400

800

1.7

Output Voltage

V_RT

V_RAMPADJ

I_RAMPADJ

1.6

−50

1

1.8

+50

50

RAMPADJ Output Voltage

RAMPADJ Input Current Range

CURRENT SENSE AMPLIFIER

Offset Voltage

Input Bias Current

Gain Bandwidth Product

Slew Rate

Input Common-Mode Range

Output Voltage Range

Output Current

RAMPADJ − FB

mV

μA

V_OS(CSA)

I_BIAS(CSSUM)

GBW_(CSA)CSSUM = CSCOMP

C_CSCOMP= 10 pF

CSSUM − CSREF, Figure 3

−1.0

−50

+1.0

+50

mV

nA

MHz

V/μs

V

μA

ms

10

CSSUM and CSREF

0

0.05

3

2.8

I_CSCOMP

t_OC(DELAY)

500

8

Current Limit Latch-Off Delay Time

C_DELAY= 10 nF

Rev. 0 | Page 4 of 36

ADP3189

Paraꢀeter

Syꢀbol

Conditions

Min

Typ

Max

Unit

CURRENT BALANCE AMPLIFIER

Common Mode Range

Input Resistance

Input Current

Input Current Matching

V_SW(X)CM

R_SW(X)

I_SW(X)

−600

35

2.5

+200 mV

SWx = 0 V

50

4.0

65

5.5

+5

kΩ

μA

%

−5

ΔI_SW(X)

CURRENT LIMIT COMPARATOR

Output Voltage

Output Current

V_ILIMIT

I_ILIMIT

R_ILIMIT= 143 kΩ

1.6

1.7

12

1.8

V

μA

Maximum Output Current²

Current Limit Threshold Voltage

Current Limit Setting Ratio

DELAY TIMER

60

105

μA

mV

mV/μA

V_CL

V_CSREF− V_CSCOMP, R_ILIMIT= 143 kΩ

V_CL/I_ILIMIT

120

10

135

Normal Mode Output Current

Output Current in Current Limit

Threshold Voltage

SOFT START

I_DELAY

I_DELAY(CL)

V_DELAY(TH)

12

3.0

1.6

15

3.75

1.7

18

4.5

1.8

μA

V

Output Current

I_SS

During start-up

12

15

18

μA

ENABLE INPUT

Threshold Voltage

Hysteresis

Input Current

V_TH(EN)

V_HYS(EN)

I_IN(EN)

800

80

−1

850

100

900

120

+1

mV

μA

Delay Time

t_DELAY(EN)

EN > 950 mV, C_DELAY= 10 nF

2

ms

OD OUTPUT

Output Low Voltage

V_OL(

100

5

500

mV

V

)

OD

Output High Voltage

V_OH(

4

)

OD

THERMAL THROTTLING CONTROL

TTSENSE Voltage Range

TTSENSE VRFAN Threshold Voltage

TTSENSE VRHOT Threshold Voltage

TTSENSE Hysteresis

Internally limited

0

1.08

780

5.3

1.14

840

V

mV

1.11

810

55

TTSENSE Input Current

VRFAN Output Low Voltage

VRHOT Output Low Voltage

POWER GOOD COMPARATOR

Undervoltage Threshold

Overvoltage Threshold

Output Low Voltage

−105 −120 −135 μA

V_OL(VRFAN)

V_OL(VRHOT)I_{VRHOT (SINK)}= −4 mA

I_{VRFAN (SINK)}= −4 mA

150

300

mV

V_PWRGD(UV)Relative to nominal DAC output

V_PWRGD(OV)Relative to nominal DAC output

V_OL(PWRGD)I_PWRGD(SINK)= −4 mA

−200 −250 −300 mV

100

150

200

300

mV

Power Good Delay Time

During Soft Start²

VID Code Changing

VID Code Static

Crowbar Trip Point

C_DELAY= 10 nF

2

ms

μs

ns

mV

100

400

200

150

375

V_CROWBAR

t_CROWBAR

Relative to nominal DAC output

Relative to FBRTN

Overvoltage to PWM going low

100

320

200

430

Crowbar Reset Point

Crowbar Delay Time

VID Code Changing

VID Code Static

100

400

μs

ns

PWM OUTPUTS

Output Low Voltage

Output High Voltage

V_OL(PWM)

V_OH(PWM)

I_PWM(SINK)= −400 μA

I_PWM(SOURCE)= 400 μA

160

5

500

mV

V

4.0

Rev. 0 | Page 5 of 36

ADP3189

Paraꢀeter

Syꢀbol

Conditions

Min

Typ

Max

Unit

SUPPLY

DC Supply Current

UVLO Threshold Voltage

UVLO Hysteresis

6

7.4

0.6

10

7.8

0.8

mA

V

V_UVLO

VCC rising

7

0.4

¹All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

²Guaranteed by design or bench characterization, not tested in production.

Rev. 0 | Page 6 of 36

ADP3189

TEST CIRCUITS

8-BIT CODE

12V

+

1μF

100nF

40

ADP3189

1

1.25V

EN

PWM1

PWM2

PWM3

PWM4

PWM5

SW1

SW2

SW3

SW4

SW5

PWRGD

FBRTN

FB

COMP

SS

DELAY

VRFAN

VRHOT

TTSENSE

VCC

31

5

12V

1kΩ

ADP3189

COMP

FB

10nF

10kΩ

4

LLSET

–

14

15

18

ΔV

CSREF

VID

DAC

250kΩ

+

20kΩ

1.25V

GND

100nF

Figure 2. Closed-Loop Output Voltage Accuracy

Figure 4. Positioning Voltage

ADP3189

VCC

31

17

12V

CSCOMP

CSSUM

CSREF

GND

39kΩ

100nF

16

15

18

1kΩ

1.25V

CSCOMP – 1.25V

40

V

=

OS

Figure 3. Current Sense Amplifier V_OS

Rev. 0 | Page 7 of 36

ADP3189

ABSOLUTE MAXIMUM RATINGS

Table 2.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or

any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability. Absolute maximum ratings apply individually

only, not in combination. Unless otherwise specified all other

voltages re referenced to GND.

Paraꢀeter

Rating

VCC

FBRTN

−0.3 V to +15 V

−0.3 V to +0.3 V

−0.3 V to VCC + 0.3 V

−5 V to +25 V

−10 V to +25 V

−0.3 V to +5.5 V

−65°C to +150°C

0°C to +85°C

125°C

PWM3 to PWM5, RAMPADJ

SW1 to SW5

<200 ns

All Other Inputs and Outputs

Storage Temperature

Operating Ambient Temperature Range

Operating Junction Temperature

Thermal Impedance (θ_JA)

Lead Temperature

Soldering (10 sec)

Infrared (15 sec)

100°C/W

300°C

260°C

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the

human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. 0 | Page 8 of 36

ADP3189

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

EN

PWGRD

FBRTN

FB

COMP

SS

DELAY

VRFAN

VRHOT

TTSENSE

1

2

3

4

5

6

7

8

9

10

PIN 1

INDICATOR

30 PWM1

29 PWM2

28 PWM3

27 PWM4

26 PWM5

25 SW1

24 SW2

23 SW3

22 SW4

21 SW5

ADP3189

TOP VIEW

(Not to Scale)

Figure 5. Pin Configuration

Table 3. Pin Function Descriptions

Pin No7 Mneꢀonic Description

1

EN

Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD

output low.

2

PWRGD

Power Good Output. Open-drain output that signals when the output voltage is outside of the proper

operating range.

3

4

FBRTN

FB

Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.

Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between

this pin and the output voltage sets the no-load offset point.

5

6

COMP

SS

Error Amplifier Output and Compensation Point.

Soft Start Delay Setting Input. An external capacitor connected between this pin and GND sets the soft start

ramp-up time.

7

DELAY

VRFAN

VRHOT

TTSENSE

ILIMIT

Delay Timer Setting Input. An external capacitor connected between this pin and GND sets the overcurrent

latch-off delay time, BOOT voltage hold time, EN delay time, and PWRGD delay time.

VR Fan Activation Output. Active high open drain output that signals when the temperature at the

monitoring point connected to TTSENSE exceeds the programmed VRFAN temperature threshold.

VR Hot Output. Active high open drain output that signals when the temperature at the monitoring point

connected to TTSENSE exceeds the programmed VRHOT temperature threshold.

VR Hot Thermal Throttling Sense Input. An NTC thermistor between this pin and GND is used to remotely

sense the temperature at the desired thermal monitoring point.

Current Limit Set Point. An external resistor from this pin to GND sets the current limit threshold of the

converter.

Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator

frequency of the device.

PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal

PWM ramp.

Output Load Line Programming Input. This pin can be directly connected to CSCOMP, or it can be connected

to the center point of a resistor divider between CSCOMP and CSREF. Connecting LLSET to CSREF disables

positioning.

8

9

10

11

12

13

14

RT

RAMPADJ

LLSET

15

CSREF

Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense

amplifier and the power good and crowbar functions. This pin should be connected to the common point of

the output inductors.

16

17

CSSUM

Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor

currents together to measure the total output current.

Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determines the gain of

the current sense amplifier and the positioning loop response time.

CSCOMP

18

19

GND

OD

Ground. All internal biasing and the logic output signals of the device are referenced to this ground.

Output Disable Logic Output. This pin is actively pulled low when the ADP3189 EN input is low or when

VCC is below its UVLO threshold to signal to the Driver IC that the driver high-side and low-side outputs

should go low.

20

NC

No Connect.

Rev. 0 | Page 9 of 36

ADP3189

Pin No7 Mneꢀonic

Description

21 to 25 SW5 to SW1

Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases

should be left open.

26 to 30 PWM5 to PMW1 Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the

ADP3120. Connecting the PWM3, PWM4, and/or PWM5 outputs to VCC will cause that phase to turn off,

allowing the ADP3189 to operate as a 2-, 3-, 4-, or 5-phase controller.

31

VCC

Supply Voltage for the Device.

32 to 39 VID7 to VID0

Voltage Identification DAC Inputs. These eight pins are pulled down to GND, providing a logic zero if

left open. When in normal operation mode, the DAC output programs the FB regulation voltage from

0.5 V to 1.6 V (see Table 4).

40

VIDSEL

VID DAC Selection Pin. The logic state of this pin determines whether the internal VID DAC decodes

VID0 to VID7 as extended VR10 or VR11 inputs.

Rev. 0 | Page 10 of 36

ADP3189

TYPICAL PERFORMANCE CHARACTERISTICS

5.0k

4.5k

4.0k

3.5k

3.0k

2.5k

2.0k

1.5k

1.0k

0.5k

0

5.0k

4.5k

4.0k

3.5k

3.0k

2.5k

2.0k

1.5k

1.0k

0.5k

0

5.8

6.0

6.2

6.4

6.6

0

200

500

800

1000

SUPPLY CURRENT (μA)

Rt (kΩ)

Figure 6. Master Clock Frequency vs. RT

Figure 7. Oscillator Frequency vs .Supply Current

Rev. 0 | Page 11 of 36

ADP3189

THEORY OF OPERATION

The ADP3189 combines a multimode, fixed frequency PWM

control with multiphase logic outputs for use in 2-, 3-, 4-, and

5-phase synchronous buck CPU core supply power converters.

The internal VID DAC is designed to interface with the Intel

8-bit VRD/VRM 11- and 7-bit VRD/VRM 10x-compatible

CPUs. Multiphase operation is important for producing the

high currents and low voltages demanded by today’s microproc-

essors. Handling the high currents in a single-phase converter

places high thermal demands on the components in the system,

such as the inductors and MOSFETs.

UVLO

12V

THRESHOLD

SUPPLY

0.85V

VTT I/O

(ADP3189 EN)

V

DELAY(TH)

(1.7V)

DELAY

V

BOOT

V

VID

(1.1V)

1.0V

SS

TD3

The multimode control of the ADP3189 ensures a stable,

high performance topology for the following:

V

BOOT

VID

(1.1V)

TD1

VCC_CORE

TD4

TD5

•

Balancing currents and thermals between phases

TD2

VR READY

(ADP3189 PWRGD)

High speed response at the lowest possible switching

frequency and output decoupling

50μs

CPU

VID INPUTS

VID INVALID

VID VALID

•

Minimizing thermal switching losses by using lower

frequency operation

Figure 8. System Start-Up Sequence

PHASE DETECTION SEQUENCE

•

Tight load line regulation and accuracy

During start-up, the number of operational phases and their

phase relationship is determined by the internal circuitry moni-

toring the PWM outputs. Normally, the ADP3189 operates as

a 5-phase PWM controller. Connecting the PWM5 pin to VCC

programs a 4-phase operation, and connecting the PWM5 pin

and PWM4 pin to VCC programs a 3-phase operation. For

2-phase operation, connect PWM5, PWM4, and PWM3

to VCC.

High current output from having up to 5-phase operation

Reduced output ripple due to multiphase cancellation

PC board layout noise immunity

Ease of use and design due to independent component

selection

•

Flexibility in operation for tailoring design to low cost or

high performance

Prior to soft start, while EN is low, the PWM3, PWM4, and

PWM5 pins sink approximately 100 μA. An internal compara-

tor checks each pin’s voltage vs. a threshold of 3.15 V. If the pin

is tied to VCC, it is above the threshold. Otherwise, an internal

current sink pulls the pin to GND, which is below the threshold.

PWM1 and PWM2 are low during the phase detection interval,

which occurs during the first five clock cycles of the internal

oscillator. After this time, if the remaining PWM outputs are

not pulled to VCC, the 100 μA current sink is removed, and

they function as normal PWM outputs. If they are pulled to

VCC, the 100 μA current source is removed, and the outputs

are put into a high-impedance state.

START-UP SEQUENCE

The ADP3189 follows the VR11 start-up sequence shown in

Figure 8. After both the EN and UVLO conditions are met,

the DELAY pin goes through one cycle (TD1). After this cycle,

the internal oscillator is enabled. The first five clock cycles are

blanked from the PWM outputs and used for phase detection

as explained in the Phase Detection Sequence section. Then, the

soft start ramp is enabled (TD2), and the output comes up to the

boot voltage of 1.1 V. The boot hold time is determined by the

DELAY pin as it goes through a second cycle (TD3). During

TD3, the processor VID pins settle to the required VID code.

When TD3 is over, the ADP3189 soft starts either up or down to

the final VID voltage (TD4). After TD4 has been completed and

the PWRGD masking time (equal to VID on the fly masking) is

finished, a third ramp on the DELAY pin sets the PWRGD

blanking (TD5).

The PWM outputs are logic-level devices intended for driving

external gate drivers such as the ADP3120. Since each phase is

monitored independently, operation approaching 100% duty

cycle is possible. Also, more than one output can be on at the

same time to allow overlapping phases.

Rev. 0 | Page 12 of 36

ADP3189

An additional resistor divider connected between CSREF and

MASTER CLOCK FREQUENCY

CSCOMP, with the mid point connected to LLSET, can be used

to set the load line required by the microprocessor. The current

information is then given as CSREF – LLSET. This difference

signal is used internally to offset the VID DAC for voltage

positioning. The difference between CSREF and CSCOMP

is then used as a differential input for the current-limit

comparator. This allows for the load line to be set independ-

ently of the current-limit threshold. In the event that the

current limit threshold and load line are not independent,

the resistor divider between CSREF and CSCOMP can be

removed and the CSCOMP pin can be directly connected

to LLSET. To disable voltage positioning entirely (that is,

no load line) connect LLSET to CSREF.

The clock frequency of the ADP3189 is set with an external

resistor connected from the RT pin to ground. The frequency

follows the graph in Figure 6. To determine the frequency per

phase, the clock is divided by the number of phases in use. If

all phases are in use, divide by 5. If PWM5 is tied to VCC, then

divide the master clock by 4 for the frequency of the remaining

phases. If PWM4 and PWM5 are tied to VCC, then divide by 3.

If PWM3, PWM4, and PWM5 are tied to VCC, then divide

by 2.

OUTPUT VOLTAGE DIFFERENTIAL SENSING

The ADP3189 combines differential sensing with a high

accuracy VID DAC and reference and a low offset error ampli-

fier. This maintains a worst-case specification of 7.7 mV

differential sensing error over its full operating output voltage

and temperature range. The output voltage is sensed between

the FB pin and FBRTN pin. FB should be connected through

a resistor to the regulation point, usually the remote sense pin

of the microprocessor. FBRTN should be connected directly

to the remote sense ground point. The internal VID DAC

and precision reference are referenced to FBRTN, which has

a minimal current of 125 μA to allow accurate remote sensing.

The internal error amplifier compares the output of the DAC

to the FB pin to regulate the output voltage.

To provide the best accuracy for sensing current, the CSA is

designed to have a low offset input voltage. Also, the sensing

gain is determined by external resistors, so that it can be made

extremely accurate.

ACTIVE IMPEDANCE CONTROL MODE

For controlling the dynamic output voltage droop as a function

of output current, a signal proportional to the total output current

at the LLSET pin can be scaled to be equal to the droop imped-

ance of the regulator times the output current. This droop voltage

is then used to set the input control voltage to the system. The

droop voltage is subtracted from the DAC reference input voltage

directly to tell the error amplifier where the output voltage should

be. This allows enhanced feed-forward response.

OUTPUT CURRENT SENSING

The ADP3189 provides a dedicated current-sense amplifier

(CSA) to monitor the total output current for proper voltage

positioning vs. load current and for current-limit detection.

Sensing the load current at the output gives the total average

current being delivered to the load, which is an inherently more

accurate method than peak current detection or sampling the

current across a sense element such as the low-side MOSFET.

This amplifier can be configured several ways, depending on

the objectives of the system, as follows:

CURRENT CONTROL MODE AND THERMAL

BALANCE

The ADP3189 has individual inputs (SW1 to SW5) for each

phase, which are used for monitoring the current of each phase.

This information is combined with an internal ramp to create

a current balancing feedback system that has been optimized

for initial current balance accuracy and dynamic thermal

balancing during operation. This current balance information

is independent of the average output current information used

for positioning as described in the Output Current Sensing

section.

•

Output inductor DCR sensing without a thermistor for

lowest cost.

Output inductor DCR sensing with a thermistor for

improved accuracy with tracking of inductor temperature.

The magnitude of the internal ramp can be set to optimize the

transient response of the system. It also monitors the supply volt-

age for feed-forward control for changes in the supply. A resistor

connected from the power input voltage to the RAMPADJ pin

determines the slope of the internal PWM ramp. External

resistors can be placed in series with individual phases to

create an intentional current imbalance if desired, such as

when one phase has better cooling and can support higher

currents. Resistors R_SW1through R_SW5(see the Typical

Application Circuit in Figure 11) can be used for adjusting

thermal balance. It is best to have the ability to add these

resistors during the initial design, so ensure that placeholders

are provided in the layout.

Sense resistors for highest accuracy measurements.

The positive input of the CSA is connected to the CSREF pin,

which is connected to the output voltage. The inputs to the

amplifier are summed together through resistors from the

sensing element, such as the switch node side of the output

inductors, to the inverting input, CSSUM. The feedback resistor

between CSCOMP and CSSUM sets the gain of the amplifier,

and a filter capacitor is placed in parallel with this resistor. The

gain of the amplifier is programmable by adjusting the feedback

resistor.

Rev. 0 | Page 13 of 36

ADP3189

To increase the current in any given phase, enlarge R_SWfor that

phase (make R_SW= 0 for the hottest phase and do not change

during balancing). Increasing R_SWto only 500 Ω makes a

substantial increase in phase current. Increase each R_SWvalue

by small amounts to achieve balance, starting with the coolest

phase first.

Once the SS voltage is within 100 mV of the boot voltage, the

boot voltage delay time (TD3) is started. The end of the boot

voltage delay time signals the beginning of the second soft start

time (TD4). The SS voltage now changes from the boot voltage

to the programmed VID DAC voltage (either higher or lower)

using the SS amplifier with the limited output current of 15 μA.

The voltage of the FB pin follows the ramping voltage of the SS

pin, limiting the inrush current during the transition from the

boot voltage to the final DAC voltage. The second soft start

time depends on the boot voltage, the programmed VID DAC

voltage, and C_SS.

VOLTAGE CONTROL MODE

A high gain-bandwidth voltage mode error amplifier is used for

the voltage-mode control loop. The control input voltage to the

positive input is set via the VID logic according to the voltages

listed in Table 4.

If either EN is taken low or VCC drops below UVLO, DELAY

and SS are reset to ground to be ready for another soft start

cycle. Figure 9 shows typical start-up waveforms for the

ADP3189.

This voltage is also offset by the droop voltage for active

positioning of the output voltage as a function of current,

commonly known as active voltage positioning. The output

of the amplifier is the COMP pin, which sets the termination

voltage for the internal PWM ramps.

The negative input (FB) is tied to the output sense location with

a resistor R_Band is used for sensing and controlling the output

voltage at this point. A current source from the FB pin flowing

through R_Bis used for setting the no-load offset voltage from

the VID voltage. The no-load voltage is negative with respect to

the VID DAC. The main loop compensation is incorporated

into the feedback network between FB and COMP.

1

3

2

4

DELAY TIMER

The delay times for the start-up timing sequence are set with

a capacitor from the DELAY pin to ground. In UVLO, or when

EN is logic low, the DELAY pin is held at ground. After the

UVLO and EN signals are asserted, the first delay time (TD1 in

Figure 8) is initiated. A 15 μA current flows out of the DELAY

pin to charge C_DLY. A comparator monitors the DELAY voltage

with a threshold of 1.7 V. The delay time is therefore set by the

15 μA charging a capacitor from 0 V to 1.7 V. This DELAY pin

is used for multiple delay timings (TD1, TD3, and TD5) during

the start-up sequence. Also, DELAY is used for timing the

current limit latch off, as explained in the Current Limit, Short

Circuit, and Latch-Off Protection section.

CH1 1.0V

CH3 1.0V

CH2 1.0V

CH4 10.0V

M2.00ms

T 22.0%

A CH1

500V

Figure 9. Typical Start-up Waveforms

Channel 1: CSREF, Channel 2: DELAY,

Channel 3: SS, Channel 4: Phase 1 Switch Node

SOFT START

The Soft Start times for the output voltage are set with a capacitor

from the SS pin to ground. After TD1 and the phase detection

cycle have been completed, the SS time (TD2 in Figure 8) starts.

The SS pin is disconnected from GND, and the capacitor is

charged up to the 1.1 V boot voltage by the SS amplifier, which

has a limited output current of 15 μA. The voltage at the FB pin

follows the ramping voltage on the SS pin, limiting the inrush

current during start-up. The soft start time depends on the

value of the boot voltage and C_SS.

Rev. 0 | Page 14 of 36

ADP3189

CURRENT LIMIT, SHORT CIRCUIT, AND LATCH-OFF

PROTECTION

1

The ADP3189 compares a programmable current-limit set

point to the voltage from the output of the current-sense

amplifier. The level of current limit is set with the resistor

from the ILIMIT pin to ground. During operation, the voltage

on ILIMIT is 1.7 V. The current through the external resistor is

internally scaled to give a current limit threshold of 10 mV/μA.

If the difference in voltage between CSREF and CSCOMP rises

above the current limit threshold, the internal current limit

amplifier controls the internal COMP voltage to maintain the

average output current at the limit.

3

2

4

CH1 1.0V

CH3 1.0V

CH2 1.0V

CH4 10.0V

M2.00ms

T 22.0%

A CH1

500V

If the limit is reached and TD5 has completed, a latch-off delay

time starts, and the controller shuts down if the fault is not

removed. The current limit delay time shares the DELAY pin

timing capacitor with the start-up sequence timing. However,

during current limit, the DELAY pin current is reduced to

3.75 μA. A comparator monitors the DELAY voltage and shuts

off the controller when the voltage reaches 1.7 V. Therefore,

the current limit latch-off delay time is set by the current of

3.75 μA, charging the delay capacitor from 0 V to 1.7 V. This

delay is four times longer than the delay time during the start-

up sequence.

Figure 10. Overcurrent Latch-Off Waveforms

Channel 1: CSREF, Channel 2: DELAY,

Channel 3: COMP, Channel 4: Phase 1 Switch Node

DYNAMIC VID

The ADP3189 has the ability to dynamically change the VID

inputs while the controller is running. This allows the output

voltage to change while the supply is running and supplying

current to the load. This is commonly referred to as VID on-

the-fly (OTF). A VID OTF can occur under light or heavy load

conditions. The processor signals the controller by changing the

VID inputs in multiple steps from the start code to the finish

code. This change can be positive or negative.

The current limit delay time starts only after the TD5 has

completed. If there is a current limit during start-up, the

ADP3189 goes through TD1 to TD5, and then starts the latch-

off time. Because the controller continues to cycle the phases

during the latch-off delay time, if the short is removed before

the 1.7 V threshold is reached, the controller returns to normal

operation, and the DELAY capacitor is reset to GND.

When a VID input changes state, the ADP3189 detects the

change and ignores the DAC inputs for a minimum of 200 ns.

This time prevents a false code due to logic skew while the eight

VID inputs are changing. Additionally, the first VID change

initiates the PWRGD and crowbar blanking functions for a

minimum of 100 μs to prevent a false PWRGD or crowbar

event. Each VID change resets the internal timer.

The latch-off function can be reset by either removing and

reapplying the supply voltage to the ADP3189, or by toggling

the EN pin low for a short time. To disable the short circuit

latch-off function, an external resistor should be placed in

parallel with C_DLY. This prevents the DELAY capacitor from

charging up to the 1.7 V threshold. The addition of this resistor

will cause a slight increase in the delay times.

POWER GOOD MONITORING

The power good comparator monitors the output voltage via

the CSREF pin. The PWRGD pin is an open-drain output whose

high level, when connected to a pull-up resistor, indicates that

the output voltage is within the nominal limits specified based

on the VID voltage setting. PWRGD goes low if the output

voltage is outside of this specified range, if the VID DAC inputs

are in no CPU mode, or whenever the EN pin is pulled low.

PWRGD is blanked during a VID OTF event for a period of

400 μs to prevent false signals during the time the output is

changing.

During start-up, when the output voltage is below 200 mV,

a secondary current limit is active. This is necessary because

the voltage swing of CSCOMP cannot go below ground. This

secondary current limit controls the internal COMP voltage

to the PWM comparators to 1.5 V. This limits the voltage drop

across the low-side MOSFETs through the current balance

circuitry. An inherent per-phase current limit protects

individual phases if one or more phases stop functioning

because of a faulty component. This limit is based on the

maximum normal mode COMP voltage. Typical overcurrent

latch-off waveforms are shown in Figure 10.

Rev. 0 | Page 15 of 36

ADP3189

The PWRGD circuitry also incorporates an initial turn-on

delay time (TD5), based on the DELAY timer. Prior to the

SS voltage reaching the programmed VID DAC voltage and the

PWRGD masking time finishing, the PWRGD pin is held low.

Once the SS pin is within 100 mV of the programmed DAC

voltage, the capacitor on the DELAY pin begins to charge up.

A comparator monitors the DELAY voltage and enables

PWRGD when the voltage reaches 1.7 V. The PWRGD delay

time is, therefore, set by a current of 15 μA, charging a capacitor

from 0 V to 1.7 V.

THERMAL MONITORING

The ADP3189 includes a thermal monitoring circuit to detect

when a point on the VR has exceeded two different user-defined

temperatures. The thermal monitoring circuit requires an NTC

thermistor to be placed between TTSENSE and GND. A fixed

current of 120 μA is sourced out of the TTSENSE pin and into

the thermistor. The current source is internally limited to 5 V.

An internal circuit compares the TTSENSE voltage to a 1.11 V

and a 0.81 V threshold, and outputs an open-drain signal at the

VRFAN and VRHOT outputs, respectively. Once the voltage on

the TTSENSE pin goes below its respective threshold, the open

drain outputs assert high to signal the system that an overtem-

perature event has occurred. Since the TTSENSE voltage changes

slowly with respect to time, 55 mV of hysteresis is built into these

comparators. The thermal monitoring circuitry does not depend

on EN and is active when UVLO is above its threshold. When

UVLO is below its threshold, VRFAN and VRHOT are

forced low.

OUTPUT CROWBAR

As part of the protection for the load and output components

of the supply, the PWM outputs are driven low, turning on the

low-side MOSFETs, when the output voltage exceeds the upper

crowbar threshold. This crowbar action stops once the output

voltage falls below the release threshold of approximately

375 mV.

Turning on the low-side MOSFETs pulls down the output as

the reverse current builds up in the inductors. If the output

overvoltage is due to a short in the high-side MOSFET, this

action current-limits the input supply or blows its fuse,

protecting the microprocessor from being destroyed.

OUTPUT ENABLE AND UVLO

For the ADP3189 to begin switching, the input supply (VCC)

to the controller must be higher than the UVLO threshold,

and the EN pin must be higher than its 0.85 V threshold. This

initiates a system start up sequence. If either UVLO or EN is

less than their respective thresholds, the ADP3189 is disabled.

This holds the PWM outputs at ground, shorts the DELAY

capacitor to ground, and forces PWRGD and

signals low.

OD

In the application circuit, the

pin should be connected to

OD

disables

the

inputs of the ADP3120 driver. Grounding

the drivers such that both DRVH and DRVL are grounded. This

feature is important in preventing the discharge of the output

capacitors when the controller is shut off. If the driver outputs

were not disabled, a negative voltage can be generated during

output due to the high current discharge of the output

capacitors through the inductors.

Rev. 0 | Page 16 of 36

ADP3189

Table 4.VR11 and VR10.x VID Codes for the ADP3189

VR11 DAC CODES: VIDSEL = HIGH

VR107x DAC CODES: VIDSEL = LOW

OUTPUT

OFF

VID± VID6 VID5 VID4 VID3 VID2 VID1 VID0 VID4 VID3 VID2 VID1 VID0 VID5 VID6

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

N/A

0

1

OFF

1.60000

1.59375

1.58750

1.58125

1.57500

1.56875

1.56250

1.55625

1.55000

1.54375

1.53750

1.53125

1.52500

1.51875

1.51250

1.50625

1.50000

1.49375

1.48750

1.48125

1.47500

1.46875

1.46250

1.45625

1.45000

1.44375

1.43750

1.43125

1.42500

1.41875

1.41250

1.40625

1.40000

1.39375

1.38750

1.38125

1.37500

1.36875

1.36250

1.35625

1.35000

1.34375

1.33750

1.33125

1.32500

1.31875

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Rev. 0 | Page 17 of 36

ADP3189

VR11 DAC CODES: VIDSEL = HIGH

VR107x DAC CODES: VIDSEL = LOW

OUTPUT

1.31250

1.30625

1.30000

1.29375

1.28750

1.28125

1.27500

1.26875

1.26250

1.25625

1.25000

1.24375

1.23750

1.23125

1.22500

1.21875

1.21250

1.20625

1.20000

1.19375

1.18750

1.18125

1.17500

1.16875

1.16250

1.15625

1.15000

1.14375

1.13750

1.13125

1.12500

1.11875

1.11250

1.10625

1.10000

1.09375

OFF

VID± VID6 VID5 VID4 VID3 VID2 VID1 VID0 VID4 VID3 VID2 VID1 VID0 VID5 VID6

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

N/A

0

OFF

1.08750

1.08125

1.07500

1.06875

1.06250

1.05625

1.05000

1.04375

1.03750

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Rev. 0 | Page 18 of 36

ADP3189

VR11 DAC CODES: VIDSEL = HIGH

VR107x DAC CODES: VIDSEL = LOW

OUTPUT

1.03125

1.02500

1.01875

1.01250

1.00625

1.00000

0.99375

0.98750

0.98125

0.97500

0.96875

0.96250

0.95625

0.95000

0.94375

0.93750

0.93125

0.92500

0.91875

0.91250

0.90625

0.90000

0.89375

0.88750

0.88125

0.87500

0.86875

0.86250

0.85625

0.85000

0.84375

0.83750

0.83125

0.82500

0.81875

0.81250

0.80625

0.80000

0.79375

0.78750

0.78125

0.77500

0.76875

0.76250

0.75625

0.75000

0.74375

0.73750

0.73125

VID± VID6 VID5 VID4 VID3 VID2 VID1 VID0 VID4 VID3 VID2 VID1 VID0 VID5 VID6

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

N/A

Rev. 0 | Page 19 of 36

ADP3189

VR11 DAC CODES: VIDSEL = HIGH

VR107x DAC CODES: VIDSEL = LOW

OUTPUT

0.72500

0.71875

0.71250

0.70625

0.70000

0.69375

0.68750

0.68125

0.67500

0.66875

0.66250

0.65625

0.65000

0.64375

0.63750

0.63125

0.62500

0.61875

0.61250

0.60625

0.60000

0.59375

0.58750

0.58125

0.57500

0.56875

0.56250

0.55625

0.55000

0.54375

0.53750

0.53125

0.52500

0.51875

0.51250

0.50625

0.50000

OFF

VID± VID6 VID5 VID4 VID3 VID2 VID1 VID0 VID4 VID3 VID2 VID1 VID0 VID5 VID6

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

N/A

1

0

1

OFF

1

Rev. 0 | Page 20 of 36

ADP3189

0 5 6 2 6 - 0 1 1

V C C

D 7 V I

N C

O D

D 6 V I

D 5 V I

D 4 V I

D 3 V I

D 2 V I

D 1 V I

D 0 V I

G N D

P

C S C O M

C S S U M

C S R E F

S L E L T

P A D J R A M

R T

D S V E I L

I L I M I T

* FOR A DESCRIPTION OF OPTIONAL R

SW

RESISTORS, SEE THE THEORY OF OPERATION SECTION

Figure 11.Typical 4-Phase Application Circuit

Rev. 0 | Page 21 of 36

ADP3189

APPLICATION INFORMATION

The design parameters for a typical Intel VRD 11 compliant

CPU application are as follows:

SOFT START DELAY TIME

The value of C_SSsets the soft start time. The ramp is generated

with a 15 μA internal current source. The value for C_SScan be

found using:

•

Input voltage (V_IN) = 12 V

VID setting voltage (V_VID) = 1.300 V

TD2

V_BOOT

(2)

C_SS=15μA×

Duty cycle (D) = 0.108

Nominal output voltage at no load (V_ONL) = 1.285 V

Nominal output voltage at 115 A load (V_OFL) = 1.170 V

Static output voltage drop based on a 1.0 mΩ load line (R_O)

where TD2 is the desired soft start time and V_BOOTis internally

set to 1.1 V. Assuming a desired TD2 time of 3 ms, C_SSis 41 nF.

The closest standard value for C_SSis 39 nF. Although C_SSalso

controls the time delay for TD4 (which is determined by the

final VID voltage), the minimum specification for TD4 is 0 ns.

This means that as long as the TD2 time requirement is met,

TD4 will be within the specification.

from no load to full load (V_D) = V_ONL− V_OFL

1.285 V − 1.170 V = 115 mV

=

•

Maximum output current (I_O) = 130 A

Maximum output current step (ΔI_O) = 100 A

Maximum output current slew-rate (S_R) = 200 A/μ sec

Number of phases (n) = 4

CURRENT LIMIT LATCH-OFF DELAY TIMES

The start-up and current limit delay times are determined by

the capacitor connected to the DELAY pin. The first step is to

set C_DLYfor the TD1, TD3, and TD5 delay times (see Figure 8).

The DELAY ramp (I_DELAY)is generated using a 15 μA internal

current source. The value for C_DLYcan be approximated using:

Switching frequency per phase (f_SW) = 330 kHz

SETTING THE CLOCK FREQUENCY

The ADP3189 uses a fixed-frequency control architecture.

The frequency is set by an external timing resistor (R_T).

The clock frequency and the number of phases determine

the switching frequency per phase, which relates directly

to switching losses and the sizes of the inductors, and of

the input and output capacitors. With n = 4 for four phases,

a clock frequency of 1.32 MHz sets the switching frequency

(f_SW) of each phase to 330 kHz, which represents a practical

trade-off between the switching losses and the sizes of the out-

put filter components. Equation 1 shows that to achieve a

1.32 MHz oscillator frequency, the correct value for R_Tis

181 kΩ. Alternatively, the value for R_Tcan be calculated using

TD(x)

V_DELAY(TH)

C_DLY= I_DELAY

×

(3)

where TD(x) is the desired delay time for TD1, TD3, and TD5.

The DELAY threshold voltage (V_DELAY(TH)) is given as 1.7 V. In

this example, 2 ms is chosen for all three delay times, which

meets Intel’s specification. Solving for C_DLYgives a value of

17.6 nF. The closest standard value for C_DLYis 18 nF.

When the ADP3189 goes into current limit, the internal current

source changes from 15 μA to 3.75 μA. This makes the latch-off

delay time 4 times longer than the start-up delay time. Longer

latch-off delay times can be achieved by placing a resistor in

1

(1)

R_T

=

− 13 kΩ

parallel with C_DLY

.

n × f_SW× 3.9 pF

where 3.9 pF and 13 kΩ are internal IC component values.

For good initial accuracy and frequency stability, a 1% resistor

is recommended.

Rev. 0 | Page 22 of 36

ADP3189

INDUCTOR SELECTION

DESIGNING AN INDUCTOR

The choice of inductance for the inductor determines the ripple

current in the inductor. Less inductance leads to more ripple

current, which increases the output ripple voltage and conduction

losses in the MOSFETs, but allows using smaller inductors and,

for a specified peak-to-peak transient deviation, less total output

capacitance. Conversely, a higher inductance means lower

ripple current and reduced conduction losses, but requires

larger inductors and more output capacitance for the same

peak-to-peak transient deviation.

Once the inductance and DCR are known, the next step is to

either design an inductor or to find a standard inductor that

comes as close as possible to meeting the overall design goals.

It is also important to have the inductance and DCR tolerance

specified to control the accuracy of the system. 15% inductance

and 7% DCR, at room temperature, are reasonable tolerances

most manufacturers can meet.

The first decision in designing the inductor is choosing the

core material. Several possibilities for providing low core loss

at high frequencies include the powder cores (for example,

Kool-Mμ® from Magnetics, Inc. or from Micrometals) and the

gapped soft ferrite cores (for example, 3F3 or 3F4 from Philips).

Low frequency powdered iron cores should be avoided due to

their high core loss, especially when the inductor value is

relatively low and the ripple current is high.

In any multiphase converter, a practical value for the

peak-to-peak inductor ripple current is less than 50% of

the maximum dc current in the same inductor. Equation 4

shows the relationship between the inductance, oscillator

frequency, and peak-to-peak ripple current in the inductor.

Equation 5 can be used to determine the minimum inductance

based on a given output ripple voltage.

The best choice for a core geometry is a closed-loop type such

as a potentiometer core; PQ, U, or E core; or toroid. A good

compromise between price and performance is a core with

a toroidal shape.

V_VID

×

(

1− D

f_SW× L

V_VID× R_O

)

(4)

(5)

I_R

=

×

(

1−

(n×D)

)

Many useful magnetics design references are available for

quickly designing a power inductor, such as

L ≥

f_SW×V_RIPPLE

•

Magnetic Designer Software

Intusoft (www.intusoft.com)

Solving Equation 5 for an 8 mV p-p output ripple voltage yields

1.3 V ×1.0 mꢀ × 1−0.432

(

)

L ≥

= 280 nH

•

Designing Magnetic Components for High-Frequency DC-

DCConverters, by William T. McLyman, Kg Magnetics,

Inc., ISBN 1883107008

330 kHz × 8 mV

If the resulting ripple voltage is less than that designed for,

the inductor can be made smaller until the ripple value is met.

This allows optimal transient response and minimum output

decoupling.

Selecting a Standard Inductor

The following power inductor manufacturers can provide design

consultation and deliver power inductors optimized for high

power applications upon request.

The smallest possible inductor should be used to minimize

the number of output capacitors. For this example, choosing a

320 nH inductor is a good starting point and gives a calculated

ripple current of 11 A. The inductor should not saturate at the

peak current of 35.5 A and should be able to handle the sum of

the power dissipation caused by the average current of 30 A in

the winding and core loss.

•

Coilcraft

www.coilcraft.com

Coiltronics

www.coiltronics.com

Sumida Electric Company

www.sumida.com

Another important factor in the inductor design is the DCR

(R_L), which is used for measuring the phase currents. A large

DCR can cause excessive power losses, while too small a value

can lead to increased measurement error. A good rule is to have

the DCR be about 1 to 1½ times the droop resistance (R_O). This

example uses an inductor with a DCR of 1.4 mΩ.

Vishay Intertechnology

www.vishay.com

Rev. 0 | Page 23 of 36

ADP3189

CURRENT SENSE AMPLIFIER

INDUCTOR DCR TEMPERATURE CORRECTION

Most designs require the regulator output voltage, measured at

the CPU pins, to drop when the output current increases. The

specified voltage drop corresponds to a dc output resistance (R_O),

also referred to as a load line. The ADP3189 has the flexibility of

adjusting R_O, independent of current limit or compensation

components, and it can also support CPUs that do not require

a load line.

With the inductor’s DCR is used as the sense element and

copper wire is the source of the DCR, the user needs to

compensate for temperature changes of the inductor’s winding.

Fortunately, copper has a well known temperature coefficient

(TC) of 0.39%/°C.

If R_CSis designed to have an opposite and equal percentage

change in resistance to that of the wire, it cancels the tempera-

ture variation of the inductor’s DCR. Due to the nonlinear

nature of NTC thermistors, resistors R_CS1and R_CS2are needed.

See Figure 12 to linearize the NTC and produce the desired

temperature tracking.

For designs requiring a load line, the impedance gain of the

CS amplifier (R_CSA) must be to be greater than or equal to the load

line. All designs, whether they have a load line or not, should

keep R_CSA≥ 1 mΩ.

PLACE AS CLOSE AS POSSIBLE

TO THE NEAREST INDUCTOR

The output current is measured by summing the voltage across

each inductor and passing the signal through a low-pass filter.

This summer filter is the CS amplifier configured with resistors

R

TM

R

PH3

PH1

PH2

R

_PH(X)(summers), and R_CSand C_CS(filter). The impedance gain

ADP3189

of the regulator is set by the following equations, where R_Lis the

DCR of the output inductors:

R

CS2

CS1

CSCOMP

18

17

16

R_CS

KEEP THIS PATH

AS SHORT AS

POSSIBLE AND

WELL AWAY FROM

SWITCH NODE LINES

C

CS2

R_CSA

=

× R_L

(6)

(7)

CS1

CSSUM

CSREF

R_PH

x

( )

L

C_CS

=

R_L× R_CS

The user has the flexibility of choosing either R_CSor R_PH(X)

.

Figure 12. Temperature Compensation Circuit Values

However, it is best to select R_CSequal to 100 kΩ, and then solve

for R_PH(X)by rearranging Equation 6. Here R_CSA= R_O= 1 mΩ

since this is equal to our design loadline.

The following procedure and expressions yield values to use

for R_CS1, R_CS2, and R_TH(the thermistor value at 25°C) for a given

R_CSvalue.

R_L

R_CSA

R_PH

=

× R_CS

(

x

)

1. Select an NTC based on type and value. Since the value

is unknown, use a thermistor with a value close to R_CS.

The NTC should also have an initial tolerance of better

than 5%.

1.4 mꢀ

1.0 mꢀ

R_PH

=

×100 kꢀ =140 kꢀ

(

x

)

2. Based on the type of NTC, find its relative resistance value

at two temperatures. The temperatures that work well are

50°C and 90°C. These resistance values are called

A (R_TH(50°C))/R_TH(25°C)) and B (R_TH(90°C))/R_TH(25°C)). The NTC’s

relative value is always 1 at 25°C.

Next, use Equation 7 to solve for C_CS.

320 nH

C_CS

=

= 2.28 nF

1.4 mꢀ ×100 kꢀ

It is best to have a dual location for C_CSin the layout so that

standard values can be used in parallel to get as close to the

value desired. For best accuracy, C_CSshould be a 5% or 10%

NPO capacitor. This example uses a 5% combination for C_CS

of two 1 nF capacitors in parallel. Recalculating R_CSand R_PH(X)

using this capacitor combination yields 114 kΩ and 160 kΩ.

The closest standard 1% value for R_PH(X)is 158 kΩ.

3. Find the relative value of R_CSrequired for each of these

temperatures. This is based on the percentage change

needed, which in this example is initially 0.39%/°C. These

are called r₁(1/(1 + TC × (T₁− 25))) and r₂(1/(1 + TC ×

(T₂− 25))), where TC = 0.0039 for copper. T₁= 50°C and

T₂= 90°C are chosen. From this, calculate that r₁= 0.9112

and r₂= 0.7978.

Rev. 0 | Page 24 of 36

ADP3189

1. Compute the relative values for R_CS1, R_CS2, and R_THusing

LOAD LINE SETTING

For load line values greater than 1 mΩ, R_CSAcan be set equal

to R_O, and the LLSET pin can be directly connected to the

CSCOMP pin. When the load line value needs to be less than

1 mΩ, two additional resistors are required. Figure 13 shows

the placement of these resistors.

(

A− B

)

× r₁× r₂− A×

(

1− B

(1− A

)

× r₂+ B ×

× r₂−

(

1− A

)

× r₁

r_CS2

=

(8)

(9)

A× 1− B × r₁− B ×

(

)

(

A− B

)

(

1− A

)

r_CS1

=

1

A

−

1− r_CS2r₁− r_CS2

1

r_TH

=

(10)

1

−

ADP3189

1− r_CS2r_CS1

CSCOMP

17

Calculate R_TH= r_TH× R_CS, then select the closest value of

thermistor available. Also, compute a scaling factor k based

on the ratio of the actual thermistor value used relative to

the computed one:

CSSUM

16

CSREF

15

R_TH

(

ACTUAL)

k =

(11)

R_TH

R

LL2

(

CALCULATED

)

LL1

OPTIONAL LOAD LINE

SELECT SWITCH

2. Calculate values for R_CS1and R_CS2using Equation 12 and

Equation 13:

LLSET

14

Q

LL

R_CS1= R_CS× k × r_CS1

R_CS2= R_CSk × r_CS2

))

(

1− k

) (

(12)

(13)

Figure 13. Load Line Setting Resistors

×

+

The two resistors R_LL1and R_LL2set up a divider between the

CSCOMP pin and CSREF pin. This resistor divider is input into

the LLSET pin to set the load line slope R_Oof the VR according

to the following equation:

In this example, R_CSwas calculated to be 114 kΩ. Look for an

available 100 kΩ thermistor, 0603 size. One such thermistor

is the Vishay NTHS0603N01N1003JR NTC thermistor with

A = 0.3602 and B = 0.09174. From these values, compute

R_LL2

r

_CS1= 0.3795, r_CS2= 0.7195, and r_TH= 1.075.

(14)

R_O=

× R_CSA

R_LL1+ R_LL2

Solving for R_THyields 122.55 kΩ, so 100 kΩ is chosen, making

k = 0.816. Next find R_CS1and R_CS2to be 35.3 kΩ and 87.9 kΩ.

Finally, choose the closest 1% resistor values, which yields a

choice of 35.7 kΩ and 88.7 kΩ.

For best results, start with a 1% resistor of 20.0 kΩ for R_LL2

Then, solve for the required value of R_LL1by rearranging

Equation 14 as follows:

.

R_LL2

R_O=

× R_CSA

R_LL1+ R_LL2

Another useful feature for some VR applications is the ability to

select different load lines. Figure 13 shows an optional MOSFET

switch that allows this. Here, design for R_CSA= R_O(MAX)(selected

with Q_LLon) and then use Equation 14 to set R_O= R_O(MIN)

(selected with Q_LLoff).

For this design, R_CSA= R_O= 1 mΩ, so connect LLSET directly to

CSCOMP, and the resistors R_LL1and R_LL2are not needed.

Rev. 0 | Page 25 of 36

ADP3189

A lower limit is based on meeting the capacitance for load

release for a given maximum load step ꢂI_Oand a maximum

allowable overshoot. The total amount of load release voltage

is given as ΔV_O= ΔI_O× R_O+ ΔV_rl, where ΔV_rlis the maximum

allowable overshoot voltage.

OUTPUT OFFSET

The Intel specification requires that at no load the nominal

output voltage of the regulator is offset to a value lower than

the nominal voltage corresponding to the VID code. The offset

is set by a constant current source flowing out of the FB pin (I_FB)

and flowing through R_B. The value of R_Bcan be found using

Equation 15:

⎛

⎜

⎞

⎟

⎜

⎟

L ×ꢂ I_O

ΔV_rl

C_x

≥

MIN )

− C_z

(17)

(18)

V_VID−V_ONL

(

⎛

⎞

⎟

⎠

R_B

=

⎜

n× R_O+

×V_VID

I_FB

⎜

⎝

⎟

⎠

⎜

ΔI_O

⎝

1.3 V−1.285 V

=1.00 kꢀ

(15)

≤

MAX )

(

15 ꢁA

2

⎛

⎞

⎟

⎛

⎞

⎟

⎠

V_V

V_VIDnKR_O

L

⎜

The closest standard 1% resistor value is 1.00 kΩ.

⎜

×

1+ t_v

×

− 1 −C_z

⎜

⎝

⎟

nK ²R_O²V_VID

V_V

L

⎜

⎟

⎠

⎝

C_OUTSELECTION

⎛

⎜

⎝

⎞

⎟

⎠

V_ERR

V_V

The required output decoupling for the regulator is typically

recommended by Intel for various processors and platforms.

Use some simple design guidelines to determine the require-

ments. These guidelines are based on having both bulk

capacitors and ceramic capacitors in the system.

where K = −1n

To meet the conditions of these expressions and transient

response, the ESR of the bulk capacitor bank (R_X) should be less

than two times the droop resistance (R_O). If the C_X(MIN)is larger

than C_X(MAX), the system cannot meet the VID on-the-fly speci-

fication and can require the use of a smaller inductor or more

phases (and may have to increase the switching frequency to

keep the output ripple the same).

First, select the total amount of ceramic capacitance. This is

based on the number and type of capacitor to be used. The best

location for ceramic capacitors is inside the socket, with 12 to

18 of size, 1206 being the physical limit. Other capacitors can be

placed along the outer edge of the socket as well.

This example uses eighteen 10 μF 1206 MLC capacitors

(C_Z= 180 F). The VID on-the-fly step change is 450 mV in

230 μs with a setting error of 2.5 mV. The maximum allowable

load release overshoot for this example is 50 mV, therefore

solving for the bulk capacitance yields

To aid in determining the minimum amount of ceramic

capacitance required, start with a worst-case load step occur-

ring right after a switching cycle has stopped. The ceramic

capacitance then delivers the charge to the load while the load

is ramping up and until the VR has responded with the next

switching cycle.

⎛

⎜

⎞

⎟

⎜

⎟

320 nH ×100 A

The following equation gives the designer a rough

approximation for determining the minimum ceramic

capacitance needed. Due to the complexity of the PCB

parasitics and bulk capacitors, the actual amount of ceramic

capacitance required may vary.

⎟

C_x

≤

MIN )

−180 ꢁF = 3.92 mF

(

⎛

⎜

⎝

⎞

⎟

⎠

⎟

50 mV

100 A

⎜

4 × 1.0 mꢀ+

×1.3 V

⎜

⎝

⎟

⎠

320 nH × 450 mV

C_x

≤

MAX

)

×

⎡

⎤

Δ I_O

2 S_R

1

⎛

⎜

⎞

⎠

(

4 × 5.2²×

(

1.0 mꢀ

)

×1.3 V

2

(16)

C_Z

≥

×

− D −

⎟

(

MIN

)

⎢

⎣

⎥

⎦

R_O

f_SW

n

⎝

2

⎛

⎜

⎞

⎟

⎛

⎞

⎟

⎠

230 ꢁs ×1.3V × 4 × 5.2 ×1.0 mꢀ

450 mV × 320 nH

The typical ceramic capacitors used are made up of multiple

10 μF or 22 μF capacitors. For this example, Equation 16 yields

180.8 μF, so eighteen 10 uF ceramics will suffice.

⎜

⎝

1+

−1 −180 ꢁF

⎜

⎟

⎜

⎝

⎟

⎠

Next, there is an upper limit imposed on the total amount of

bulk capacitance (C_X) when the user considers the VID on-the-

fly voltage stepping of the output (voltage step V_Vin time t_V

with error of V_ERR).

= 43.0 mF

where K = 5.2

Rev. 0 | Page 26 of 36

ADP3189

Another important factor for the synchronous MOSFET is the

input capacitance and feedback capacitance. The ratio of the

feedback to input needs to be small (less than 10% is recom-

mended) to prevent accidental turn-on of the synchronous

MOSFETs when the switch node goes high.

Using ten 560 μF Al-Poly capacitors with a typical ESR of 6 mΩ

each yields C_X= 5.6 mF with an R_X= 0.6 mΩ.

One last check should be made to ensure that the ESL of the

bulk capacitors (L_X) is low enough to limit the high frequency

ringing during a load change.

Also, the time to switch the synchronous MOSFETs off should

not exceed the nonoverlap dead time of the MOSFET driver

(40 ns typical for the ADP3120). The output impedance of the

driver is approximately 2 Ω, and the typical MOSFET input gate

resistances are about 1 Ω to 2 Ω, so a total gate capacitance of

less than 6000 pF should be adhered to. Since there are two

MOSFETs in parallel, the input capacitance for each synchronous

MOSFET should be limited to 3000 pF.

This is tested using

L_x≤ C_z× R_O²× Q ²

(19)

4

3

2

L_x≤180 ꢁF ×

(

1 mꢀ

)

×

= 240 pH

where Q²is limited to ⁴/₃to ensure a critically damped system.

In this example, L_Xis approximately 240 pH for the ten

A1-Polys capacitors, which satisfies this limitation. If the L_X

of the chosen bulk capacitor bank is too large, the number of

ceramic capacitors may need to be increased, or lower ESL bulks

used if there is excessive undershoot during a load transient.

The high-side (main) MOSFET has to be able to handle two

main power dissipation components: conduction and switching

losses. The switching loss is related to the amount of time it

takes for the main MOSFET to turn on and off, and to the

current and voltage that are being switched. Basing the switching

speed on the rise and fall time of the gate driver impedance and

MOSFET input capacitance, the following expression provides

an approximate value for the switching loss per main MOSFET,

where n_MFis the total number of main MOSFETs:

For this multimode control technique, all ceramic designs can

be used providing the conditions of Equation 16, Equation 17,

Equation 18, and Equation 19 are satisfied.

POWER MOSFETS

For this example, the N-channel power MOSFETs have been

selected for one high-side switch and two low-side switches per

phase. The main selection parameters for the power MOSFETs

are V_GS(TH), Q_G, C_ISS, C_RSS, and R_DS(ON). The minimum gate drive

voltage (the supply voltage to the ADP3120) dictates whether

standard threshold or logic-level threshold MOSFETs must be

used. With V_GATE~10 V, logic-level threshold MOSFETs

(V_GS(TH)< 2.5 V) are recommended.

V_CC× I_O

n_MF

n

P_S

= 2 × f_SW

MF

)

×

× R_G

×

× C_ISS

(21)

(

n_MF

where R_Gis the total gate resistance (2 Ω for the ADP3120 and

about 1 Ω for typical high speed switching MOSFETs, making

R_G= 3 Ω), and C_ISSis the input capacitance of the main MOSFET.

Adding more main MOSFETs (n_MF) does not help the switching

loss per MOSFET, since the additional gate capacitance slows

switching. Use lower gate capacitance devices to reduce

switching loss.

The maximum output current (I_O) determines the R_DS(ON)

requirement for the low-side (synchronous) MOSFETs. With

the ADP3189, currents are balanced between phases, thus the

current in each low-side MOSFET is the output current divided

by the total number of MOSFETs (n_SF). With conduction losses

being dominant, the following expression shows the total power

being dissipated in each synchronous MOSFET in terms of the

ripple current per phase (I_R) and average total output current (I_O):

The conduction loss of the main MOSFET is given by the

following, where R_DS(MF)is the on resistance of the MOSFET:

2

⎡

⎛

⎜

⎢

⎜

⎝

⎤

⎥

n × I

⎞

⎟

⎠

⎛

⎜

⎝

⎞

⎟

⎠

I_O

1

12

R

P_C

= D ×

+

×

× R_DS

MF

( )

(22)

(

MF

)

n_MF

⎢

⎣

⎥

⎦

Typically, for main MOSFETs, the highest speed (low C_ISS)

2

⎡

⎢

⎤

⎥

n I

⎛

⎜

⎝

⎞

⎟

⎠

⎛

⎜

⎝

⎞

⎟

⎠

I_O

n_SF

1

12

R

device is preferred, but these usually have higher on resistance.

Select a device that meets the total power dissipation (about

1.5 W for a single D-PAK) when combining the switching and

conduction losses.

P_SF

=

(1− D

)

×

+

×

×R_DS

(20)

(

SF )

n_SF

⎢

⎣

⎥

⎦

Knowing the maximum output current being designed for and

the maximum allowed power dissipation, the user can find the

required R_DS(ON)for the MOSFET. For D-PAK MOSFETs up to

an ambient temperature of 50°C, a safe limit for P_SFis 1 W to

1.5 W at 120°C junction temperature. Thus, for this example

(119 A maximum), R_DS(SF)(per MOSFET) < 7.5 mΩ. This R_DS(SF)

is also at a junction temperature of about 120°C, so be certain to

account for this when making this selection. This example uses

two lower-side MOSFETs at 4.8 mΩ, each at 120°C.

Rev. 0 | Page 27 of 36

ADP3189

For this example, an NTD40N03L was selected as the main

MOSFET (eight total; n_MF= 8), with C_ISS= 584 pF (max) and

The internal ramp voltage magnitude can be calculated by using

A_R×

(

1− D

)×V_VID

V_R=

R

_DS(MF)= 19 mΩ (max at T_J= 120°C), and an NTD110N02L was

selected as the synchronous MOSFET (eight total; n_SF= 8), with

_ISS= 2710 pF (max) and R_DS(SF)= 4.8 mΩ (max at T_J= 120°C).

R_R× C_R× f_SW

(25)

C

0.2 ×

1−0.108 ×1.3 V

( )

The synchronous MOSFET C_ISSis less than 3000 pF, satisfying

this requirement. Solving for the power dissipation per MOSFET

at IO = 119 A and IR = 11 A yields 958 mW for each synchronous

MOSFET and 872 mW for each main MOSFET. The guideline

is to limit the MOSFET power dissipation to 1 W. The values

calculated in Equation 21 and Equation 22 comply with this

guideline.

V_R=

= 394 mV

357 kꢀ × 5 pF × 330 kHz

The size of the internal ramp can be made larger or smaller.

If it is made larger, stability and noise rejection improves, but

transient degrades. Likewise, if the ramp is made smaller,

transient response improves at the sacrifice of noise rejection

and stability.

Finally, consider the power dissipation in the driver for each

phase. This is best expressed as Q_Gfor the MOSFETs and is

given by the following equation, where Q_GMFis the total gate

charge for each main MOSFET and Q_GSFis the total gate charge

for each synchronous MOSFET.

The factor of 3 in the denominator of Equation 24 sets a ramp

size that gives an optimal balance for good stability, transient

response, and thermal balance.

COMP PIN RAMP

⎡

⎢

⎤

f_SW

2 × n

A ramp signal on the COMP pin is due to the droop voltage and

output voltage ramps. This ramp amplitude adds to the internal

ramp to produce the following overall ramp signal at the PWM

input:

P_DRV

=

×

(

n_MF× Q_GMF+n_SF× Q_GSF

)

+ I_CC×V (23)

⎥

CC

⎢

⎣

⎥

⎦

Also shown is the driver’s standby dissipation factor (I_CC× V_CC).

For the ADP3120, the maximum dissipation should be less than

400 mW. In this example, with I_CC= 7 mA, Q_GMF= 5.8 nC, and

Q_GSF= 48 nC, one finds 297 mW in each driver, which is below

the 400 mW dissipation limit. See the ADP3120 data sheet for

more details.

V_R

V_RT

=

(26)

⎛

⎜

⎝

⎞

⎟

⎠

2×

(

1−n × D

)

1−

n × f_SW× C_X× R_O

In this example, the overall ramp signal is 0.46 V. However,

if the ramp size is smaller than 0.5 V, increase the ramp size

to be at least 0.5 V by decreasing the ramp resistor for noise

immunity. As there is only 0.46 V initially, a ramp resistor value

of 332 kΩ is chosen for this example, yielding an overall ramp

of 0.51 V.

RAMP RESISTOR SELECTION

The ramp resistor (R_R) is used for setting the size of the internal

PWM ramp. The value of this resistor is chosen to provide the

best combination of thermal balance, stability, and transient

response. The following expression is used for determining the

optimum value:

A_R× L

R_R

=

3 × A_D× R_DS× C_R

(24)

0.2 × 320 nH

R_R

=

= 356 kꢀ

3 × 5 × 2.4 mꢀ × 5 pF

where

A_Ris the internal ramp amplifier gain.

A_Dis the current balancing amplifier gain.

R_DSis the total low-side MOSFET on resistance.

C_Ris the internal ramp capacitor value.

Rev. 0 | Page 28 of 36

ADP3189

CURRENT LIMIT SETPOINT

FEEDBACK LOOP COMPENSATION DESIGN

To select the current limit setpoint, first find the resistor value

for R_LIM. The current limit threshold for the ADP3189 is set

with a 1.7 V source (V_LIM) across R_LIMwith a gain of 10 mV/μA

(A_LIM). R_LIMcan be found using

Optimized compensation of the ADP3189 allows the best

possible response of the regulator’s output to a load change.

The basis for determining the optimum compensation is to

make the regulator and output decoupling appear as an output

impedance that is entirely resistive over the widest possible

frequency range, including dc, and equal to the droop resis-

tance (R_O). With the resistive output impedance, the output

voltage droops in proportion to the load current at any load

current slew rate. This ensures the optimal positioning and

allows the minimization of the output decoupling.

A_LIM×V_LIM

R_LIM

=

(27)

I_LIM× R_CSA

For values of R_LIMgreater than 500 kΩ, the current limit may be

lower than expected, so some adjustment of R_LIMis needed. Here,

I_LIMis the peak average current limit for the supply output. In this

example, choosing a peak current limit of 170 A for I_LIM, results

in R_LIM= 100 kΩ, and 100 kΩ is chosen as the nearest 1% value.

With the multimode feedback structure of the ADP3189, the

feedback compensation must be set to make the converter’s

output impedance, working in parallel with the output decoup-

ling, to meet this goal. Several poles and zeros created by the

output inductor and decoupling capacitors (output filter) need

to be compensated for.

The per-phase initial duty cycle limit and peak current during a

load step are determined by

V_COMP

₎−V_BIAS

(

MAX

D_MAX= D ×

(28)

(29)

V_RT

A type-three compensator on the voltage feedback is adequate

for proper compensation of the output filter. Equation 31 to

Equation 35 are intended to yield an optimal starting point for

the design; some adjustments may be necessary to account for

PCB and component parasitic effects (see the Tuning the

ADP3189 section).

D_MAX

f_SW

(

V_IN−V_VID

)

I_PHMAX

≅

×

L

For the ADP3189, the maximum COMP voltage (V_COMP(MAX)) is

4.0 V and the COMP pin bias voltage (V_BIAS) is 1.1 V. In this

example, the maximum duty cycle is 0.61 and the peak current

is 62 A.

First, compute the time constants for all the poles and zeros in

the system, using Equation 31 to Equation 35 on the next page.

The limit of the peak per-phase current described earlier during

the secondary current limit is determined by

V_COMP

₎−V_BIAS

CLAMPED

(

(30)

I_PHLIM

≅

A_D× R_DS

(

MAX )

For the ADP3189, the current balancing amplifier gain (A_D) is 5,

and the clamped COMP pin voltage is 2 V. Using an R_DS(MAX)of

2.8 mΩ (low-side on resistance at 150°C) results in a per-phase

peak current limit of 64 A. This current level can be reached

only with an absolute short at the output, and the current limit

latch-off function shuts down the regulator before overheating

can occur.

Rev. 0 | Page 29 of 36

ADP3189

The first step is to compute the time constants for all of the poles and zeros in the system:

R_L×V_RT2× L ×

(

1−n × D ×V_RT

)

R_E= n × R_O+ A_D× R_DS

+

V_VID

n × C_X× R_O×V_VID

1.4 mꢀ × 0.51V 2 × 320 nH ×

(

1−0.432

)

× 0.51 V

(31)

R_E= 4 ×1 mꢀ +5 × 2.4 mꢀ +

+

= 22.9 mꢀ

1.3 V

4 × 5.6 mF ×1 mꢀ ×1.3 V

240 pH 1 mꢀ −0.5mꢀ

R_O− R'

L_X

R_O

T_A= C_X

×

(

R_O− R'

)

+

×

= 5.6 mF ×

(

1 mꢀ−0.5 mꢀ

)

+

×

= 3.00 ꢁs

(32)

(33)

R_X

0.6 mꢀ +0.5 mꢀ −1 mꢀ

1 mꢀ

× 5.6 mF = 560 ns

0.6 mꢀ

T_B=

(

R_X+ R'−R_O× C_X

)

=

(

)

⎛

⎞

⎟

⎠

⎛

⎞

⎟

⎠

A_D× R_DS

2 × f_SW

5 × 2.4 mꢀ

⎜

V_RT× L −

0.51 V × 320 nH−

⎜

2 × 330 kHz

⎝

T_C=

T_D=

=

= 5.17 ꢁs

(34)

(35)

V_VID× R_E

1.3 V × 22.9 mꢀ

5.6 mF×180 ꢁF×

+C_Z× R_O5.6 mF× 1mꢀ−0.5mꢀ

C_X×C × R²

(

1mꢀ

)

2

Z

O

=

= 338 ns

C_X×

(

R_O− R'

)

(

)

+180ꢁF×1mꢀ

where, for the ADP3189, R' is the PCB resistance from the bulk capacitors to the ceramics and where R_DSis the total low-side MOSFET

on resistance per phase. In this example, A_Dis 5, V_RTequals 0.51 V, R' is approximately 0.5 mΩ (assuming a 4-layer, 1 ounce mother-

board), and L_Xis 240 pH for the ten Al-Poly capacitors.

The compensation values can then be solved using

n × R_O×T_A

R_E× R_B

4×1 mꢀ × 3.00 ꢁs

22.9 mꢀ ×1.00 kꢀ

(36)

(37)

(38)

(39)

C_A

R_A

=

= 524 pF

5.17 ꢁs

C_A524 pF

T_C

=

= 9.87 kꢀ

= 560 pF

= 34.2 pF

T_B

560 ns

C_B

C_FB

=

R_B1.00 kꢀ

T_D

338ns

=

R_A9.87 kꢀ

These are the starting values prior to tuning the design to account for layout and other parasitic effects (see the Tuning the ADP3189

section). The final values selected after tuning are

C_A= 560 pF

R_A= 10.0 kΩ

C_B= 560 pF

C_FB= 27 pF

Rev. 0 | Page 30 of 36

ADP3189

Figure 14 and Figure 15 show the typical transient response

using these compensation values.

The capacitor manufacturer’s ripple current ratings are often

based on only 2,000 hours of life. This makes it advisable to

further derate the capacitor or to choose a capacitor rated at a

higher temperature than required. Several capacitors may be

placed in parallel to meet size or height requirements in the

design. In this example, the input capacitor bank is formed by

two 2,700 μF, 16 V aluminum electrolytic capacitors, and eight

4.7 μF ceramic capacitors.

To reduce the input current di/dt to a level below the recom-

mended maximum of 0.1 A/μs, an additional small inductor

(L > 370 nH at 18 A) should be inserted between the converter

and the supply bus. This inductor also acts as a filter between

the converter and the primary power source.

THERMAL MONITOR DESIGN

Figure 14. Typical Transient Response for Design Example

Load Step

A thermistor is used on the TTSENSE input of the ADP3189

for monitoring the temperature of the VR. A constant current

of 120 μA is sourced out of this pin and run through a thermis-

tor network such as that shown in Figure 16.

ADP3189

VRFAN

8

VRHOT

9

TTSENSE

10

OPTIONAL

TEMPERATURE

0.1

ADJUST

RESISTOR

PLACE THERMISTOR

NEAR CLOSEST PHASE

R

TTSENSE

Figure 16. VR Thermal Monitor Circuit

Figure 15. Typical Transient Response for Design Example Load Release

A voltage is generated from this current through the thermistor

and sensed inside the IC. When the voltage reaches 1.11 V, the

VRFAN output gets set. When the voltage reaches 0.81 V, the

VRHOT gets set. This corresponds to R_TTSENSEvalues of 9.25 kΩ

for VRFAN and 6.75 kΩ.

C_INSELECTION AND INPUT CURRENT

di/dt REDUCTION

In continuous inductor current mode, the source current of the

high-side MOSFET is approximately a square wave with a duty

ratio equal to n × V_OUT/V_INand an amplitude of one-nth the

maximum output current. To prevent large voltage transients,

a low ESR input capacitor, sized for the maximum rms current,

must be used. The maximum rms capacitor current is given by

These values correspond to a thermistor temperature of ~100°C

and ~110°C when using the same type of 100 kΩ NTC thermistor

used in the current sense amplifier.

An additional fixed resistor in parallel with the thermistor

provides tuning the trip point temperatures to match the hot-

test temperature in the VR, when the thermistor itself is directly

sensing a proportionately lower temperature. Setting this

resistor value is best accomplished with a variable resistor

during thermal validation, and then fixing this value for the

final design.

1

I_CRMS= D × I_O×

−1

N × D

(40)

1

I_CRMS= 0.108 ×119A ×

− 1 =14.7 A

4 × 0.108

Additionally, a 0.1 μF should be used for filtering noise.

Rev. 0 | Page 31 of 36

ADP3189

TUNING THE ADP3189

1. Build a circuit based on the compensation values

computed from the design spreadsheet.

6. Measure the output voltage from no load to full load using

5 A steps. Compute the loadline slope for each change, and

then average to get overall loadline slope (R_OMEAS).

2. Hook up the dc load to circuit, turn it on, and verify its

operation. Also, check for jitter at no load and full load.

7. If R_OMEASis off from R_Oby more than 0.05 mΩ, use the

following to adjust the R_PHvalues:

DC Loadline Setting

R_OMEAS

R_O

(42)

3. Measure the output voltage at no load (V_NL). Verify that it

is within tolerance.

R_PH

= R_PH

×

OLD)

(

NEW

)

(

8. Repeat Step 6 and Step 7 to check the loadline, and repeat

adjustments if necessary.

4. Measure the output voltage at full load cold (V_FLCOLD). Let

the board sit for ~10 minutes at full load, and then measure

the output (V_FLHOT). If there is a change of more than a few

millivolts, adjust R_CS1and R_CS2using Equation 41 and

Equation 43.

9. Once dc loadline adjustment is complete, do not change

R_PH, R_CS1, R_CS2, or R_THfor the remainder of the procedure.

10. Measure the output ripple at no load and full load with

a scope, and make sure it is within specifications.

V_NL−V_FLCOLD

V_NL−V_FLHOT

(41)

R_CS2

= R_CS2

×

OLD)

(

NEW

)

(

5. Repeat Step 4 until the cold and hot voltage measurements

remain the same.

1

R_CS1

=

NEW )

(43)

(

R_CS1

₎+ R_TH

1

(

OLD

(25°C

)

−

R_CS1

× R_TH

+

(

R_CS1

₎− R_CS2

)

×

(

R_CS1

₎− R_TH

)

R_TH

(

OLD

)

(

25°C

)

(

OLD

(

NEW

)

(

OLD

(

25°C

)

(25°C

)

Rev. 0 | Page 32 of 36

ADP3189

AC Loadline Setting

Initial Transient Setting

11. Remove the dc load from the circuit and hook up the

dynamic load.

18. With the dynamic load still set at the maximum step size,

expand the scope time scale to see 2 μs/div to 5 μs/div.

The waveform can have two overshoots and one minor

undershoot (see Figure 18). Here, V_DROOPis the final

desired value.

12. Hook up the scope to the output voltage and set it to dc

coupling with the time scale at 100 μs/div.

13. Set the dynamic load for a transient step of about 40 A at

1 kHz with 50% duty cycle.

14. Measure the output waveform (use dc offset on scope to

see the waveform). Try to use a vertical scale of

100 mV/div or finer. This waveform should look similar

to Figure 17.

V

DROOP

V

TRAN1

V

TRAN2

V

ACDRP

Figure 18. Transient Setting Waveform

V

DCDRP

19. If both overshoots are larger than desired, try making

the adjustments described later in this step. If these

adjustments do not change the response, you are limited

by the output decoupling. Check the output response

each time you make a change, and check the switching

nodes to make ensure that the response is still stable.

Figure 17. AC Loadline Waveform

•

Make the ramp resistor larger by 25% (R_RAMP).

15. Use the horizontal cursors to measure V_ACDRPand V_DCDRPas

shown. Do not measure the undershoot or overshoot that

happens immediately after this step.

For V_TRAN1, increase C_Bor increase the switching

frequency.

16. If V_ACDRPand V_DCDRPare different by more than a few

millivolts, use Equation 44 to adjust C_CS.You may need to

parallel different values to get the right one since there are

limited standard capacitor values available. (It is a good

idea to have locations for two capacitors in the layout for

this.)

•

For V_TRAN2, increase R_Aand decrease C_Aby 25%.

20. For load release (see Figure 19), if V_TRANRELis larger

than the allowed overshoot, there is not enough output

capacitance. Either more capacitance is needed, or the

inductor values need to be made smaller. (When changing

inductors, start the design again using a spreadsheet and

this tuning procedure.)

V_ACDRP

(44)

C_CS

= C_CS

×

OLD)

(

NEW

)

(

V_DCDRP

17. Repeat Step 11 to Step 13 and repeat the adjustments if

necessary. Once complete, do not change C_CSfor the

remainder of the procedure.

V

TRANREL

V

DROOP

Set the dynamic load step to maximum step size (do not

use a step size larger than needed) and verify that the

output waveform is square, which means that V_ACDRPand

V_DCDRPare equal.

Figure 19. Transient Setting Waveform

Rev. 0 | Page 33 of 36

ADP3189

Avoid crossing any signal lines over the switching power path

loop, described in the Power Circuitry Recommendations

section.

Since the ADP3189 turns off all of the phases (switches inductors

to ground), there is no ripple voltage present during load release.

Therefore, the user does not have to add headroom for ripple,

allowing load release VTRANREL to be larger than VTRAN1,

by the amount of ripple, and still meet specifications.

Power Circuitry Recommendations

The switching power path should be routed on the PCB to

encompass the shortest-possible length in order to minimize

radiated switching noise energy (that is, EMI) and conduction

losses in the board. Failure to take proper precautions often

results in EMI problems for the entire PC system and noise-

related operational problems in the power converter control

circuitry. The switching power path is the loop formed by

the current path through the input capacitors and the power

MOSFETs, including all interconnecting PCB traces and planes.

Using short and wide interconnection traces is especially critical

in this path for two reasons: it minimizes the inductance in the

switching loop, which can cause high energy ringing, and it

accommodates the high current demand with minimal

voltage loss.

If V_TRAN1and V_TRANRELare less than the desired final droop, this

implies that capacitors can be removed. When removing capaci-

tors, check the output ripple voltage as well to make sure it is

still within specifications.

LAYOUT AND COMPONENT PLACEMENT

The following guidelines are recommended for optimal

performance of a switching regulator in a PC system.

General Recommendations

For good results, a PCB with at least four layers is recommended.

This should allow the needed versatility for control circuitry

interconnections with optimal placement, power planes for

ground, input and output power, and wide interconnection

traces in the remainder of the power delivery current paths.

Keep in mind that each square unit of 1 ounce copper trace

has a resistance of ~0.53 mΩ at room temperature.

Whenever a power dissipating component, for example, a

power MOSFET, is soldered to a PCB, the liberal use of vias,

both directly on the mounting pad and immediately surrounding

it, is recommended. Two important reasons for this are improved

current rating through the vias and improved thermal perform-

ance from vias extended to the opposite side of the PCB, where

a plane can more readily transfer the heat to the air. Make a

mirror image of any pad being used to heatsink the MOSFETs

on the opposite side of the PCB to achieve the best thermal

dissipation to the air around the board. To further improve

thermal performance, use the largest possible pad area.

Whenever high currents must be routed between PCB layers,

vias should be used liberally to create several parallel current

paths, so the resistance and inductance introduced by these

current paths is minimized and the via current rating is not

exceeded.

If critical signal lines (including the output voltage sense lines

of the ADP3189) must cross through power circuitry, it is best

if a signal ground plane can be interposed between those signal

lines and the traces of the power circuitry. This serves as a

shield to minimize noise injection into the signals at the

expense of making signal ground a bit noisier.

The output power path should also be routed to encompass a

short distance. The output power path is formed by the current

path through the inductor, the output capacitors, and the load.

For best EMI containment, a solid power ground plane should

be used as one of the inner layers extending fully under all the

power components.

An analog ground plane should be used around and under the

ADP3189 as a reference for the components associated with the

controller. This plane should be tied to the nearest output

decoupling capacitor ground and should not be tied to any other

power circuitry to prevent power currents from flowing in it.

Signal Circuitry Recommendations

The output voltage is sensed and regulated between the FB pin

and the FBRTN pin, which connect to the signal ground at the

load. To avoid differential mode noise pickup in the sensed

signal, the loop area should be small. Thus, the FB trace and

FBRTN trace should be routed adjacent to each other on top

of the power ground plane back to the controller.

The components around the ADP3189 should be located close

to the controller with short traces. The most important traces

to keep short and away from other traces are the FB pin and

CSSUM pin. The output capacitors should be connected as

close as possible to the load (or connector), for example, a

microprocessor core, that receives the power. If the load is

distributed, the capacitors should also be distributed and

generally be in proportion to where the load tends to be

more dynamic.

The feedback traces from the switch nodes should be connected

as close as possible to the inductor. The CSREF signal should be

connected to the output voltage at the nearest inductor to the

controller.

Rev. 0 | Page 34 of 36

ADP3189

OUTLINE DIMENSIONS

6.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

31

40

1

30

PIN 1

INDICATOR

0.50

BSC

TOP

VIEW

4.25

4.10 SQ

3.95

5.75

BCS SQ

EXPOSED

PAD

(BOTTOM VIEW)

0.50

0.40

0.30

21

10

11

20

0.25 MIN

4.50

REF

12° MAX

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

1.00

0.85

0.80

0.30

0.23

0.18

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2

Figure 20. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

6 mm × 6 mm Body, Very Thin Quad

(CP-40)

Dimensions shown in millimeters

ORDERING GUIDE

Ordering

Quantity

Model

Teꢀperature Range

Package Description

Package Option

ADP3189JCPZ-RL¹

¹Z = Pb-free part.

0°C to 85°C

40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

CP-40

2500

Rev. 0 | Page 35 of 36

ADP3189

NOTES

©

registered tradeꢀarks are the property of their respective owners7

D05626–0–±/05(0)

Rev. 0 | Page 36 of 36


型号：	ADP3189
厂家：	ADI
描述：	8-Bit Programmable 2- to 5-Phase Synchronous Buck Controller 8位可编程2-5相同步降压控制器控制器
文件：	总36页 (文件大小：1415K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADP3189 [ADI]

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