ADP3333 [ADI]
High Accuracy Ultralow IQ, 300 mA, anyCAP Low Dropout Regulator; 高精度超低智商300毫安，公司的anyCAP低压差稳压器
| 型号： | ADP3333 |
| 厂家： | 
ADI |
| 描述： | High Accuracy Ultralow IQ, 300 mA, anyCAP Low Dropout Regulator |
| 文件： | 总8页 (文件大小：120K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Accuracy Ultralow IQ, 300 mA,
anyCAP® Low Dropout Regulator
a
ADP3333
FEATURES
FUNCTIO NAL BLO CK D IAGRAM
High Accuracy Over Line and Load: ꢀ0.8% @ 25ꢁC,
ꢀ1.8% Over Temperature
Q1
IN
OUT
Ultralow Dropout Voltage: 230 mV (Max) @ 300 mA
Requires Only CO = 1.0 ꢂF for Stability
anyCAP = Stable with Any Type of Capacitor
(Including MLCC)
Current and Thermal Limiting
Low Noise
THERMAL
PROTECTION
ADP3333
R1
R2
CC
g
DRIVER
m
SD
BANDGAP
REF
Low Shutdown Current: < 1 ꢂA
2.6 V to 12 V Supply Range
–40ꢁC to +85ꢁC Ambient Temperature Range
Ultrasmall 8-Lead MSOP Package
GND
APPLICATIONS
Cellular Phones
PCMCIA Cards
Personal Digital Assistants (PDAs)
DSP/ASIC Supplies
GENERAL D ESCRIP TIO N
ADP3333 is a member of the ADP333x family of precision low
dropout anyCAP voltage regulators. Pin-compatible with the
MAX8860, the ADP3333 operates with a wider input voltage
range of 2.6 V to 12 V and delivers a load current up to 300 mA.
ADP3333 stands out from other conventional LDOs with a
novel architecture and an enhanced process that enables it to
offer performance advantages over its competition. Its patented
design requires only a 1.0 µF output capacitor for stability. T his
device is insensitive to output capacitor Equivalent Series Resis-
tance (ESR), and is stable with any good quality capacitor,
including ceramic (MLCC) types for space-restricted applica-
tions. ADP3333 achieves exceptional accuracy of ±0.8% at
room temperature and ±1.8% over temperature, line and load
variations. T he dropout voltage of ADP3333 is only 140 mV
(typical) at 300 mA. T his device also includes a safety current
limit, thermal overload protection and a shutdown feature. In
shutdown mode, the ground current is reduced to less than
1 µA. T he ADP3333 has ultralow quiescent current, 70 µA (typ)
in light load situations.
ADP3333
NC
V
IN
IN
V
OUT
OUT
C
1ꢂF
IN
C
1ꢂF
OUT
GND
SD
OFF
NC = NO CONNECT
ON
Figure 1. Typical Application Circuit
anyCAP is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2001
1
(V = 6.0 V, C = COUT = 1.0 ꢂF, T = –40ꢁC to +125ꢁC, unless otherwise noted)
ADP3333–SPECIFICATIONS
IN
IN
J
P aram eter
Sym bol
Condition
Min
Typ
Max
Unit
OUT PUT
Voltage Accuracy2
VOUT
VIN = VOUT NOM 0.3 V to 12 V
IL = 0.1 mA to 300 mA
TJ = 25°C
0.8
0.8
%
VIN = VOUT NOM 0.3 V to 12 V
IL = 0.1 mA to 300 mA
VIN = VOUT NOM 0.3 V to 12 V
TJ = 25°C
IL = 0.1 mA to 300 mA
TJ = 25°C
VOUT = 98% of VOUT NOM
IL = 300 mA
IL = 200 mA
–1.8
+1.8
%
Line Regulation2
Load Regulation
Dropout Voltage
0.04
0.04
mV/V
mV/mA
VDROP
140
105
30
230
185
mV
mV
mV
IL = 0.1 mA
Peak Load Current
Output Noise
ILDPK
VNOISE
VIN = VOUT NOM + 1 V
f = 10 Hz–100 kHz, CL = 10 µF
IL = 300 mA
600
45
mA
µV rms
GROUND CURRENT
In Regulation
IGND
IL = 300 mA
2.0
2.0
1.5
1.4
200
70
5.5
4.3
3.3
mA
mA
mA
mA
µA
IL = 300 mA, TJ = 25°C
IL = 300 mA, TJ = 85°C
IL = 200 mA
IL = 10 mA
IL = 0.1 mA
275
100
190
µA
µA
In Dropout
IGND
VIN = VOUT NOM – 100 mV
IL = 0.1 mA,
70
VIN = VOUT NOM – 100 mV
IL = 0.1 mA, TJ = 0°C to 125°C
SD = 0 V, VIN = 12 V
70
160
1
µA
µA
In Shutdown
IGNDSD
0.01
SHUT DOWN
T hreshold Voltage
VTHSD
ISD
ON
OFF
2.0
V
V
µA
µA
µA
µA
0.4
7
4.5
1
SD Input Current
0 ≤ SD ≤ 12 V
0 ≤ SD ≤ 5 V
TJ = 25°C VIN = 12 V
TJ = 125°C VIN = 12 V
0.85
0.8
0.01
0.01
Output Current In Shutdown
IOSD
1
NOT ES
1Application stable with no load.
2VIN = 2.6 V for models with VOUT NOM ≤ 2.3 V.
Specifications subject to change without notice.
–2–
REV. 0
ADP3333
P IN FUNCTIO N D ESCRIP TIO NS
ABSO LUTE MAXIMUM RATINGS*
Input Supply Voltage . . . . . . . . . . . . . . . . . . . –0.3 V to +16 V
Shutdown Input Voltage . . . . . . . . . . . . . . . . –0.3 V to +16 V
Power Dissipation . . . . . . . . . . . . . . . . . . . Internally Limited
Operating Ambient T emperature Range . . . . –40°C to +85°C
Operating Junction T emperature Range . . . –40°C to +125°C
P in
Mnem onic Function
1
OUT
IN
Output of the Regulator. Bypass to ground
with a 1.0 µF or larger capacitor.
Input pin. Bypass to ground with a 1.0 µF
or larger capacitor.
2
(4-layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W
(2-layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C/W
JA
JA
3
GND
Ground Pin
No Connect
Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C
Lead T emperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*T his is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged.
4–6, 8 NC
SD
7
Active Low Shutdown Pin. Connect to
ground to disable the regulator output.
When shutdown is not used, his pin should
be connected to the input pin
O RD ERING GUID E
P IN CO NFIGURATIO N
O utput
Voltage
P ackage
O ption
Branding
Inform ation
Model
OUT
IN
1
2
3
4
8
7
6
5
ADP3333ARM-1.5
1.5 V
1.8 V
2.5 V
2.77 V
3 V
RM-8
(MSOP-8)
RM-8
(MSOP-8)
RM-8
(MSOP-8)
RM-8
(MSOP-8)
RM-8
(MSOP-8)
RM-8
(MSOP-8)
RM-8
(MSOP-8)
RM-8
LKA
LKB
LKC
LKD
LKE
LKF
LKG
LKH
NC
SD
NC
NC
ADP3333
TOP VIEW
ADP3333ARM-1.8
ADP3333ARM-2.5
ADP3333ARM-2.77
ADP3333ARM-3
ADP3333ARM-3.15
ADP3333ARM-3.3
ADP3333ARM-5
GND
(Not to Scale)
NC*
NC = NO CONNECT
*CAN BE CONNECTED
TO ANY OTHER PIN.
3.15 V
3.3 V
5 V
(MSOP-8)
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3333 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. T herefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
ADP3333–Typical Performance Characteristics
2.502
2.500
2.498
2.496
2.502
140
120
100
80
V
= 2.5V
V
= 6V
I
= 100ꢂA
OUT
V
= 2.5V
IN
L
OUT
0mA
V
= 2.5V
2.500
OUT
2.498
2.496
2.494
2.492
100mA
I
= 0
L
2.494
2.492
60
200mA
300mA
40
2.490
2.488
20
0
2.490
2.488
3
4
5
6
7
8
9
10 11 12
0
2
4
6
8
10
12
0
50
100
150
200
250
300
INPUT VOLTAGE – V
INPUT VOLTAGE – Volts
OUTPUT LOAD – mA
TPC 1. Line Regulation Output
Voltage vs. Supply Voltage
TPC 3. Ground Current vs. Supply
Voltage
TPC 2. Output Voltage vs. Load
Current
1.0
2.5
2.0
3.5
0
V
= 6V
0.9
0.8
V
= 6V
IN
IN
3.0
2.5
2.0
0.7
200mA
I
= 300mA
L
0.6
I
= 200mA
L
0.5
1.5
1.0
I
= 100mA
L
0.4
0.3
0.2
1.5
1.0
0.5
0
300mA
0.1
0.0
–0.1
–0.2
–0.3
–0.4
0.5
0
I
= 0mA
0
L
0
0
50
100
150
200
250
300
–50 –25
25
50
75
100 125
–50 –25
0
25
50
75
100 125
JUNCTION TEMPERATURE – ꢁC
OUTPUT LOAD – mA
JUNCTION TEMPERATURE – ꢁC
TPC 4. Ground Current vs.
Load Current
TPC 6. Ground Current vs.
Junction Temperature
TPC 5. Output Voltage Variation % vs.
Junction Temperature
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
C
= 1ꢂF
V
= 2.5V
OUT
OUT
3
2
1
0
4
2
0
3.0
2.5
2.0
1.5
1.0
0.5
0
SD = V
R
IN
= 8.3ꢃ
L
C
= 10ꢂF
OUT
V
= 2.5V
OUT
SD = V
R
IN
= 8.3ꢃ
L
0
50
100
150
200
250
300
200
400
TIME – ꢂs
600
800
1
2
3
4
OUTPUT LOAD – mA
TIME – Sec
TPC 7. Dropout Voltage vs.
Output Current
TPC 9. Power-Up Response
TPC 8. Power-Up/Power-Down
–4–
REV. 0
ADP3333
V
= 4V
= 2.5V
= 1ꢂF
V
= 2.5V
V
= 2.5V
IN
OUT
OUT
2.52
2.51
2.50
2.49
2.7
2.6
2.5
2.4
2.52
2.51
2.50
2.49
V
C
R
C
= 8.3ꢃ
= 1ꢂF
R
C
= 8.3ꢃ
= 10ꢂF
OUT
L
L
L
L
L
300
10
3.50
3.00
3.50
3.00
40
80
140
180
40
80
140
180
200
400
600
800
TIME – ꢂs
TIME – ꢂs
TIME – ꢂs
TPC 10. Line Transient Response
TPC 11. Line Transient Response
TPC 12. Load Transient Response
V
= 4V
IN
1ꢂF
3
2.7
2.6
2.5
2.4
V
C
= 2.5V
OUT
= 10ꢂF
L
2.5
0
2
1
0
10ꢂF
10ꢂF
3
1ꢂF
V
= 6V
IN
V
= 6V
= 2.5V
= 8.3ꢃ
2
1
0
IN
300
10
V
R
OUT
2
0
L
V
= 6V
400
IN
200
400
600
800
200
600
800
200
400
600
800
TIME – ꢂs
TIME – ꢂs
TIME – ꢂs
TPC 13. Load Transient Response
TPC 14. Short Circuit Current
TPC 15. Turn ON-Turn OFF
Response
100
10
120
–20
V
= 2.5V
OUT
I = 1mA
L
V
= 2.2V
OUT
C
= 10ꢂF
= 500mA
L
–30
–40
–50
–60
–70
–80
–90
I
100
80
L
C
= 10ꢂF
L
C
= 1ꢂF
= 500mA
L
I
L
C
= 1ꢂF
L
1
C
= 1ꢂF
= 50ꢂA
L
I
L
60
300mA
0.1
0.01
40
0mA
C
= 10ꢂF
= 50ꢂA
L
20
0
I
L
0.001
0
10
20
30
– ꢂF
40
50
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
10M
C
FREQUENCY – Hz
L
FREQUENCY – Hz
TPC 16. Power Supply Ripple
Rejection
TPC 17. RMS Noise vs. CL
(10 Hz–100 kHz)
TPC 18. Output Noise Density
–5–
REV. 0
ADP3333
designing with LDOs more difficult because of their unclear
specifications and extreme variations over temperature.
TH EO RY O F O P ERATIO N
T he new anyCAP LDO ADP3333 uses a single control loop for
regulation and reference functions see (Figure 2). T he output
voltage is sensed by a resistive voltage divider consisting of R1
and R2 which is varied to provide the available output voltage
option. Feedback is taken from this network by way of a series
diode (D1) and a second resistor divider (R3 and R4) to the
input of an amplifier.
With the ADP3333 anyCAP LDO, this is no longer true. It can be
used with virtually any good quality capacitor, with no constraint
on the minimum ESR. This innovative design allows the circuit to
be stable with just a small 1 µF capacitor on the output. Additional
advantages of the pole splitting scheme include superior line noise
rejection and very high regulator gain which leads to excellent line
and load regulation. An impressive ±1.8% accuracy is guaranteed
over line, load and temperature.
OUTPUT
R1
INPUT
Q1
ATTENUATION
/V
Additional features of the circuit include current limit and ther-
mal shutdown.
(V
)
BANDGAP OUT
COMPENSATION
CAPACITOR
C
LOAD
D1
R3
PTAT
OS
g
NONINVERTING
WIDEBAND
DRIVER
(a)
R2
FB
V
AP P LICATIO N INFO RMATIO N
m
PTAT
CURRENT
R
LOAD
Capacitor Selection
Output Ca pa citor
R4
ADP3333
T he stability and transient response of the LDO is a function of
the output capacitor. T he ADP3333 is stable with a wide range
of capacitor values, types and ESR (anyCAP). A capacitor as
low as 1.0 µF is all that is needed for stability; larger capacitors
can be used if high current surges on the output are anticipated.
T he ADP3333 is stable with extremely low ESR capacitors
(ESR » 0), such as Multilayer Ceramic Capacitors (MLCC) or
OSCON. Note that the effective capacitance of some capacitor
types fall below the minimum over temperature or with dc voltage.
Ensure that the capacitor provides at least 1.0 µF of capacitance
over temperature and dc bias.
GND
Figure 2. Functional Block Diagram
A very high gain error amplifier is used to control this loop. T he
amplifier is constructed in such a way that at equilibrium it pro-
duces a large, temperature-proportional input “offset voltage” that
is repeatable and very well controlled. T he temperature propor-
tional offset voltage is combined with the complementary diode
voltage to form a “virtual bandgap” voltage, implicit in the network,
although it never appears explicitly in the circuit. Ultimately, this
patented design makes it possible to control the loop with only one
amplifier. This technique also improves the noise characteristics
of the amplifier by providing more flexibility on the trade-off of
noise sources that leads to a low noise design.
Input Bypa ss Ca pa citor
An input bypass capacitor is not strictly required but it is recom-
mended in any application involving long input wires or high
source impedance. Connecting a 1.0 µF capacitor from the input
to ground reduces the circuit's sensitivity to PC board layout and
input transients. If a larger output capacitor is necessary then a
larger value input capacitor is also recommended.
T he R1, R2 divider is chosen in the same ratio as the bandgap
voltage to the output voltage. Although the R1, R2 resistor divider
is loaded by the diode D1 and a second divider consisting of R3
and R4, the values can be chosen to produce a temperature stable
output. This unique arrangement specifically corrects for the load-
ing of the divider so that the error resulting from base current
loading in conventional circuits is avoided.
O utput Cur r ent Lim it
T he ADP3333 is short circuit protected by limiting the pass
transistor’s base drive current. T he maximum output current is
limited to about 1 A. See T PC 14.
Ther m al O ver load P r otection
T he patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. T he use of this special
noninverting driver enables the frequency compensation to include
the load capacitor in a pole splitting arrangement to achieve
reduced sensitivity to the value, type and ESR of the load
capacitance.
The ADP3333 is protected against damage due to excessive power
dissipation by its thermal overload protection circuit. T hermal
protection limits the die temperature to a maximum of 165°C.
Under extreme conditions (i.e., high ambient temperature and
power dissipation) where the die temperature starts to rise above
165°C, the output current will be reduced until the die tempera-
ture has dropped to a safe level.
Most LDOs place very strict requirements on the range of ESR
values for the output capacitor because they are difficult to stabilize
due to the uncertainty of load capacitance and resistance. Moreover,
the ESR value, required to keep conventional LDOs stable, changes
depending on load and temperature. These ESR limitations make
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, the device's power dissipation should be externally
limited so that the junction temperature will not exceed 125°C.
–6–
REV. 0
ADP3333
Calculating Junction Tem per atur e
P r inted Cir cuit Boar d Layout Consider ations
Device power dissipation is calculated as follows:
Use the following general guidelines when designing printed
circuit boards:
1. Keep the output capacitor as close to the output and ground
pins as possible.
2. Keep the input capacitor as close to the input and ground
pins as possible.
3. PC board traces with larger cross sectional areas will remove
more heat from the ADP3333. For optimum heat transfer,
specify thick copper and use wide traces.
PD = V −VOUT
I
+ V
I
GND
(
)
(
)
IN
LOAD
IN
Where ILOAD and IGND are load current and ground current, VIN
and VOUT are the input and output voltages respectively.
Assuming the worst-case operating conditions are ILOAD
300 mA, IGND = 2.6 mA, VIN = 4.0 V and VOUT = 3.0 V, the
device power dissipation is:
=
4. Connect the NC pins (Pins 5, 6, and 8) to ground for better
thermal performance.
5. T he thermal resistance can be decreased by approximately
10% by adding a few square centimeters of copper area to
the lands connected to the pins of the LDO.
PD = 4.0 V − 3.0 V 300 mA + 4.2 V 2.0 mA = 308 mW
(
)
(
)
T he package used on the ADP3333 has a thermal resistance of
158°C/W for 4-layer boards. T he junction temperature rise
above ambient will be approximately equal to:
6. Use additional copper layers or planes to reduce the thermal
resistance. Again, connecting the other layers to the ground and
NC pins of the ADP3333 is best, but not necessary. When
connecting the ground pad to other layers use multiple vias.
TJA = 0.308 W × 158°C /W = 48.7°C
So, to limit the junction temperature to 125°C, the maximum
allowable ambient temperature is:
TA( MAX ) = 125°C − 48.7°C = 76.3°C
Shutdown Mode
Applying a high signal to the shutdown pin, or connecting it to
the input pin, will turn the output ON. Pulling the shutdown
pin to 0.3 V or below, or connecting it to ground, will turn the
output OFF. In shutdown mode, the quiescent current is reduced
to less than 1 µA.
REV. 0
–7–
ADP3333
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
8-Lead Mini/m icro SO IC P ackage [Mini_SO ]
(RM-8)
0.122 (3.10)
0.114 (2.90)
8
5
4
0.122 (3.10)
0.114 (2.90)
0.199 (5.05)
0.187 (4.75)
1
PIN 1
0.0256 (0.65) BSC
0.120 (3.05)
0.112 (2.84)
0.120 (3.05)
0.112 (2.84)
0.043 (1.09)
0.037 (0.94)
0.006 (0.15)
0.002 (0.05)
33ꢁ
27ꢁ
0.018 (0.46)
0.008 (0.20)
0.028 (0.71)
0.016 (0.41)
0.011 (0.28)
0.003 (0.08)
SEATING
PLANE
REV. 0
–8–
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