ADP5074ACPZ-R7 [ADI]
2.4 A, DC-to-DC Inverting Regulator;
| 型号： | ADP5074ACPZ-R7 |
| 厂家： | 
ADI |
| 描述： | 2.4 A, DC-to-DC Inverting Regulator |
| 文件： | 总17页 (文件大小：520K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.4 A, DC-to-DC Inverting Regulator
ADP5074
Data Sheet
FEATURES
TYPICAL APPLICATION CIRCUIT
Wide input voltage range: 2.85 V to 15 V
Adjustable negative output to VIN − 39 V
Integrated 2.4 A main switch
1.2 MHz/2.4 MHz switching frequency with optional external
frequency synchronization from 1.0 MHz to 2.6 MHz
Resistor programmable soft start timer
Slew rate control for lower system noise
Precision enable control
C
VREF
AVIN
PVIN
VREF
V
IN
R
FB
C
IN
ADP5074
FB
R
FT
ON
D1
OFF
VREG
EN
V
SW
OUT
C
C
OUT
VREG
L1
Power-good output
SS
UVLO, OCP, OVP, and TSD protection
3 mm × 3 mm, 16-lead LFCSP
−40°C to +125°C junction temperature
Supported by the ADIsimPower tool set
PWRGD
C
PWRGD
COMP
SLEW
SYNC/FREQ
R
C
C
GND
APPLICATIONS
Figure 1.
Bipolar amplifiers, ADCs, digital-to-analog converters
(DACs), and multiplexers
High speed converters
Radio frequency (RF) power amplifier (PA) bias
Optical modules
GENERAL DESCRIPTION
The ADP5074 is a high performance dc-to-dc inverting regulator
used to generate negative supply rails.
Other key safety features in the ADP5074 include overcurrent
protection (OCP), overvoltage protection (OVP), thermal
shutdown (TSD), and input undervoltage lockout (UVLO).
The input voltage range of 2.85 V to 15 V supports a wide variety of
applications. The integrated main switch enables the generation of
an adjustable negative output voltage down to 39 V below the
input voltage.
The ADP5074 is available in a 16-lead LFCSP and is rated for a
−40°C to +125°C operating junction temperature range.
Table 1. Related Devices
The ADP5074 operates at a pin selected 1.2 MHz/2.4 MHz
switching frequency. The ADP5074 can synchronize with an
external oscillator from 1.0 MHz to 2.6 MHz to ease noise
filtering in sensitive applications. The regulator implements
programmable slew rate control circuitry for the MOSFET
driver stage to reduce electromagnetic interference (EMI).
Boost
Switch (A)
Inverter
Switch (A)
Device
Package
ADP5070 1.0
ADP5071 2.0
ADP5073 Not
applicable
ADP5074 Not
applicable
ADP5075 Not
applicable
0.6
1.2
1.2
2.4
0.8
20-lead LFCSP (4 mm ×
4 mm) and TSSOP
20-lead LFCSP (4 mm ×
4 mm) and TSSOP
16-lead LFCSP (3 mm ×
3 mm)
16-lead LFCSP (3 mm ×
3 mm)
The ADP5074 includes a fixed internal or resistor programmable
soft start timer to prevent inrush current at power-up. During
shutdown, the regulator completely disconnects the load from the
input supply to provide a true shutdown. A power good pin is
available to indicate the output is stable.
12-ball WLCSP
(1.61 mm × 2.18 mm)
Rev. A
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Technical Support
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ADP5074
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Internal Regulators..................................................................... 10
Precision Enabling...................................................................... 11
Soft Start ...................................................................................... 11
Slew Rate Control....................................................................... 11
Current-Limit Protection ............................................................ 11
Overvoltage Protection.............................................................. 11
Power Good ................................................................................ 11
Applications Information .............................................................. 12
ADIsimPower Design Tool ....................................................... 12
Component Selection ................................................................ 12
Common Applications .............................................................. 15
Layout Considerations............................................................... 16
Outline Dimensions....................................................................... 17
Ordering Guide .......................................................................... 17
Applications....................................................................................... 1
Typical Application Circuit ............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 10
PWM Mode................................................................................. 10
Skip Mode.................................................................................... 10
Undervoltage Lockout (UVLO) ............................................... 10
Oscillator and Synchronization................................................ 10
REVISION HISTORY
10/2017—Rev. 0 to Rev. A
Updated Outline Dimensions....................................................... 17
Changes to Ordering Guide .......................................................... 17
10/2015—Revision 0: Initial Version
Rev. A | Page 2 of 17
Data Sheet
ADP5074
SPECIFICATIONS
PVIN = AVIN = 2.85 V to 15 V, VOUT = −15 V, fSW = 1200 kHz, TJ = −40°C to +125°C for minimum/maximum specifications, and TA =
25°C for typical specifications, unless otherwise noted.
Table 2.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
INPUT SUPPLY VOLTAGE RANGE
QUIESCENT CURRENT
Operating Quiescent Current
PVIN, AVIN (Total)
VIN
2.85
15
V
PVIN, AVIN
IQ
1.8
5
4.0
10
mA
µA
No switching, EN = high, PVIN = AVIN =
5 V
No switching, EN = low, PVIN = AVIN =
5 V, −40°C ≤ TJ ≤ +85°C
Shutdown Current
ISHDN
UVLO
System UVLO Threshold
Rising
Falling
AVIN
VUVLO_RISING
VUVLO_FALLING
VHYS
2.8
2.55
0.25
2.85
V
V
V
2.5
Hysteresis
OSCILLATOR CIRCUIT
Switching Frequency
fSW
1.130
2.240
1.200
2.400
1.270
2.560
MHz
MHz
SYNC/FREQ = low
SYNC/FREQ = high (connect to VREG)
SYNC/FREQ Input
Input Clock Range
fSYNC
1.000
100
100
2.600
1.3
MHz
ns
ns
V
Input Clock Minimum On Pulse Width
Input Clock Minimum Off Pulse Width
Input Clock High Logic
Input Clock Low Logic
PRECISION ENABLING (EN)
High Level Threshold
Low Level Threshold
tSYNC_MIN_ON
tSYNC_MIN_OFF
VH (SYNC)
VL (SYNC)
0.4
V
VTH_H
VTH_L
VTH_S
REN
1.125
1.025
0.4
1.15
1.05
1.175
1.075
V
V
V
MΩ
Shutdown Mode
Internal circuitry disabled to achieve ISHDN
Pull-Down Resistance
INTERNAL REGULATOR
VREG Output Voltage
INVERTING REGULATOR
Reference Voltage
1.48
4.25
1.60
VREG
VREF
V
V
Accuracy
−0.5
−1.5
+0.5
+1.5
%
%
V
%
%
µA
V
V
V
Ω
V
TJ = 25°C
TJ = −40°C to +125°C
Feedback Voltage
Accuracy
VREF − VFB
0.8
−0.5
−1.5
+0.5
+1.5
0.1
TJ = 25°C
TJ = −40°C to +125°C
Feedback Bias Current
Overvoltage Protection Threshold
Power-Good Threshold
IFB
VOV
VPG (GOOD)
VPG (BAD)
RDS_PG (ON)
0.74
0.7
0.68
28
At the FB pin after soft start is complete
VREF − VFB ≥ VPG (GOOD)
VREF − VFB ≤ VPG (BAD)
Power-Good FET On Resistance
Power-Good FET Maximum Drain Source VDS_PG (MAX)
Voltage
5.5
Power-Good Supply Voltage
VPG (SUPPLY )
1.4
Voltage required on PVIN pin for power-
good FET to pull down
Load Regulation
∆(VREF − VFB)/
∆ILOAD
∆(VREF − VFB)/
∆VVIN
0.0006
0.02
%/A
%/V
ILOAD = 20 mA to 1500 mA (regulator
not in skip mode)
Line Regulation
V
VIN = 2.85 V to 14.5 V, ILOAD = 15 mA
(regulator not in skip mode)
Rev. A | Page 3 of 17
ADP5074
Data Sheet
Parameter
Symbol
gM
RDS (ON)
Min
Typ
300
200
Max
Unit
µA/V
mΩ
V
Test Conditions/Comments
Error Amplifier (EA) Transconductance
Power FET On Resistance
Power FET Maximum Drain Source Voltage VDS (MAX)
270
330
VIN = 5 V
39
Current-Limit Threshold
Minimum On Time
Minimum Off Time
SOFT START
ILIM
2.4
2.75
55
50
3.2
A
ns
ns
Soft Start Timer
tSS
4
32
8 × tSS
ms
ms
ms
SS = open
SS resistor = 50 kΩ to GND
Hiccup Time
THERMAL SHUTDOWN
Threshold
tHICCUP
TSHDN
THYS
150
15
°C
°C
Hysteresis
Rev. A | Page 4 of 17
Data Sheet
ADP5074
ABSOLUTE MAXIMUM RATINGS
Table 3.
THERMAL RESISTANCE
θJA and ΨJT are based on a 4-layer printed circuit board (PCB)
(two signals and two power planes) with thermal vias connecting
the exposed pad to a ground plane as recommended in the
Layout Considerations section. θJC is measured at the top of the
package and is independent of the PCB. The ΨJT value is more
appropriate for calculating junction to case temperature in the
application.
Parameter
PVIN, AVIN
SW
GND
VREG
Rating
−0.3 V to +18 V
PVIN − 40 V to PVIN + 0.3 V
−0.3 V to +0.3 V
−0.3 V to lower of AVIN + 0.3 V or +6V
EN, FB, SYNC/FREQ, PWRGD −0.3 V to +6 V
COMP, SLEW, SS, VREF
−0.3 V to VREG + 0.3 V
Operating Junction
Temperature Range
Storage Temperature
Range
−40°C to +125°C
−65°C to +150°C
JEDEC J-STD-020
Table 4. Thermal Resistance
Package Type
θJA
θJC
ΨJT
Unit
16-Lead LFCSP
75.01
55.79 0.95
°C/W
Soldering Conditions
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. A | Page 5 of 17
ADP5074
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SW
SLEW
1
2
3
4
12 PVIN
11 VREG
10 GND
ADP5074
TOP VIEW
(Not to Scale)
PWRGD
SYNC/FREQ
9
VREF
NOTES.
1. NIC = NO INTERNAL CONNECTION. FOR IMPROVED THERMAL
PERFORMANCE, CONNECT THESE PINS TO THE PCB GROUND PLANE.
2. EXPOSED PAD. CONNECT THE EXPOSED PAD TO GND.
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
SW
SLEW
Switching Node for the Inverting Regulator.
Driver Stage Slew Rate Control. The SLEW pin sets the slew rate for the FET driving the SW pin. For the fastest
slew rate (best efficiency), leave the SLEW pin open. For a normal slew rate, connect the SLEW pin to VREG. For
the slowest slew rate (best noise performance), connect the SLEW pin to GND.
3
4
PWRGD
Power-Good Output (Open-Drain). Pull this pin up to VREG with a resistor to provide a high output when power
is good.
SYNC/FREQ Frequency Setting and Synchronization Input. To set the switching frequency to 2.4 MHz, pull the SYNC/FREQ pin
high. To set the switching frequency to 1.2 MHz, pull the SYNC/FREQ pin low. To synchronize the switching
frequency, connect the SYNC/FREQ pin to an external clock.
5
6
7
8
SS
Soft Start Programming. Leave the SS pin open to obtain the fastest soft start time. To program a slower soft
start time, connect a resistor between the SS pin and GND.
Inverting Regulator Precision Enable. The EN pin is compared to an internal precision reference to enable the
inverting regulator output.
Error Amplifier Compensation for the Inverting Regulator. Connect the compensation network between this pin and
GND.
Feedback Input for the Inverting Regulator. Connect a resistor divider between the negative side of the
inverting regulator output capacitor and VREF to program the output voltage.
EN
COMP
FB
9
VREF
GND
VREG
PVIN
AVIN
Inverting Regulator Reference Output. Connect a 1.0 μF ceramic filter capacitor between the VREF pin and GND.
Ground.
Internal Regulator Output. Connect a 1.0 μF ceramic filter capacitor between the VREG pin and GND.
Power Input for the Inverting Regulator.
10
11
12
13
System Power Supply for the ADP5074.
14, 15, 16 NIC
EPAD EPAD
No Internal Connection. For improved thermal performance, connect these pins to the PCB ground plane.
Exposed Pad. Connect the exposed pad to GND.
Rev. A | Page 6 of 17
Data Sheet
ADP5074
TYPICAL PERFORMANCE CHARACTERISTICS
Typical performance characteristics are generated using the standard bill of materials for each input/output combination listed in Table 9.
90
80
70
60
50
40
30
20
10
0
1600
1400
1200
1000
800
600
400
200
0
V
V
V
V
V
V
V
= 3.3V, L = 2.2µH
= 3.3V, L = 3.3µH
= 5V, L = 3.3µH
= 5V, L = 5.6µH
= 12V, L = 5.6µH
= 12V, L = 10µH
= 15V, L = 5.6µH
IN
IN
IN
IN
IN
IN
IN
V
V
= 12V, 1.2MHz
= 12V, 2.4MHz
IN
IN
–40
–35
–30
–25
–20
(V)
–15
–10
–5
0
0.001
0.01
0.1
(A)
1
10
I
V
OUT
OUT
Figure 3. Maximum Output Current, fSW = 1.2 MHz, TA = 25°C, Based on
Target of 70% ILIM (MIN)
Figure 6. Efficiency vs. Current Load (IOUT), VIN = 12 V, VOUT = −5 V, TA = 25°C
1200
90
80
70
60
50
40
30
V
V
V
V
V
V
V
= 3.3V, L = 1µH
= 3.3V, L = 2.2µH
= 5V, L = 2.2µH
= 5V, L = 3.3µH
= 12V, L = 2.2µH
= 12V, L = 5.6µH
= 15V, L = 3.3µH
IN
IN
IN
IN
IN
IN
IN
1000
800
600
400
200
0
V
V
V
V
= 12V, 1.2MHz
= 12V, 2.4MHz
= 5V, 1.2MHz
= 5V, 2.4MHz
IN
IN
IN
IN
20
10
0
–35
–30
–25
–20
V
–15
(V)
–10
–5
0
0.001
0.01
0.1
1
OUT
I
(A)
OUT
Figure 4. Maximum Output Current, fSW = 2.4 MHz, TA = 25°C, Based on
Target of 70% ILIM (MIN)
Figure 7. Efficiency vs. Current Load (IOUT), VIN = 5 V and 12 V, VOUT = −15 V,
A = 25°C
T
80
70
60
50
40
30
20
90
80
70
60
50
40
30
20
10
0
V
V
= 12V, 1.2MHz
= 12V, 2.4MHz
IN
IN
V
V
= 5V, 1.2MHz
= 5V, 2.4MHz
10
0
IN
IN
0.001
0.01
0.1
(A)
1
10
0.001
0.01
0.1
1
I
OUT
I
(A)
OUT
Figure 5. Efficiency vs. Current Load (IOUT), VIN = 12 V, VOUT = −2.5 V, TA = 25°C
Figure 8. Efficiency vs. Current Load (IOUT), VIN = 5 V, VOUT = −30 V, TA = 25°C
Rev. A | Page 7 of 17
ADP5074
Data Sheet
2.54
2.49
2.44
2.39
2.34
2.29
2.24
90
80
70
60
50
40
30
20
10
T
T
T
= +125°C
= +25°C
= –40°C
A
A
A
T
T
T
= +125°C
= +25°C
= –40°C
A
A
A
0
0
2
4
6
8
10
12
14
16
0.001
0.01
0.1
(A)
1
10
I
V
(V)
OUT
IN
Figure 9. Efficiency vs. Current Load (IOUT) for Various Temperatures, VIN = 5 V,
OUT = −15 V, fSW = 1.2 MHz
Figure 12. Oscillator Frequency vs. Input Voltage (VIN) for Various
Temperatures, SYNC/FREQ Pin = High
V
0.50
1.27
T
T
T
= +125°C
= +25°C
= –40°C
A
A
A
1.25
1.23
1.21
1.19
1.17
1.15
1.13
0.30
0.10
–0.10
–0.30
–0.50
0
2
4
6
8
10
12
0
2
4
6
8
10
12
14
16
V
(V)
IN
V
(V)
IN
Figure 10. Line Regulation, VOUT = −5 V, fSW = 1.2 MHz, 15 mA Load, TA = 25°C
(Skip Mode Not Shown)
Figure 13. Oscillator Frequency vs. Input Voltage (VIN) for Various
Temperatures, SYNC/FREQ Pin = Low
0.50
18
16
14
12
10
8
1.2 MHz
2.4 MHz
0.30
0.10
–0.10
–0.30
–0.50
6
4
T
T
T
=
=
=
+80°C
+25°C
–40°C
A
A
A
2
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
0
2
4
6
8
10
12
14
16
LOAD (A)
V
(V)
IN
Figure 11. Load Regulation, VIN = 12 V, VOUT = −5 V, fSW = 1.2 MHz, TA = 25°C
(Skip Mode Not Shown)
Figure 14. Shutdown Quiescent Current (ISHDN) vs. Input Voltage (VIN) for
Various Temperatures, EN Pin Below Shutdown Threshold
Rev. A | Page 8 of 17
Data Sheet
ADP5074
2.3
T
T
T
=
=
=
+125°C
+25°C
–40°C
A
A
A
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
I
INDUCTOR
3
1
V
SW
2
V
OUT
0
2
4
6
8
10
12
14
16
2.50GS/s
CH1 5.00V
CH2 500mV
CH3 100mA
M 4.00µs
T 29.50%
CH1
7.00V
B
V
(V)
1M POINTS
IN
W
Figure 18. Skip Mode Operation Showing Inductor Current (IINDUCTOR), Switch
Node Voltage (VSW), and Output Ripple (VOUT), VIN = 12 V, VOUT = −5 V,
Figure 15. Operating Quiescent Current (IQ) vs. Input Voltage (VIN) for Various
Temperatures, EN Pin On
I
LOAD = 1 mA, fSW = 1.2 MHz, TA = 25°C
V
IN
I
INDUCTOR
3
1
2
V
OUT
2
1
V
V
SW
V
FB
4
OUT
B
2.50GS/s
CH1 5.00V
CH2 500mV
CH3 200mA
M 200ns
CH1
7.00V
250kS/s
10k POINTS
CH1
5.00V
CH1 1.00V
M 4.00ms
11.92ms
W
B
B
B
T 37.70%
1M POINTS
T
W
CH2 100mV
CH4 20.0mV
W
W
Figure 16. Line Transient Showing VIN, VOUT, and VFB, VIN = 4.5 V to 5.5 V Step,
Figure 19. Discontinuous Conduction Mode Operation Showing Inductor
Current (IINDUCTOR), Switch Node Voltage (VSW), and Output Ripple (VOUT),
VOUT = −5 V, RLOAD = 300 Ω, fSW = 1.2 MHz, TA = 25°C
VIN = 12 V, VOUT= −5 V, ILOAD = 100 mA, fSW = 1.2 MHz, TA = 25°C
I
INDUCTOR
I
LOAD
3
1
V
OUT
2
3
V
SW
V
FB
4
V
OUT
2
B
B
B
2.50MS/s
12.48ms 100k POINTS
CH2 50.0mV
CH3 10.0mA
CH4 5.00mV
M 4.00ms
CH3
40.0mA
W
W
W
B
B
2.50GS/s
–13.0020µs 1M POINTS
CH1 5.00V
CH2 500mV
CH3 200mA
M 200ns
CH1
7.70V
W
W
T
T
Figure 17. Load Transient Showing ILOAD, VOUT, and VFB, VIN = 12 V,
OUT = −5 V, ILOAD = 35 mA to 45 mA Step, fSW = 1.2 MHz, TA = 25°C
Figure 20. Continuous Conduction Mode Operation Showing Inductor
Current (IINDUCTOR), Switch Node Voltage (VSW), and Output Ripple (VOUT),
V
VIN = 12 V, VOUT = −5 V, ILOAD = 250 mA, fSW = 1.2 MHz, TA = 25°C
Rev. A | Page 9 of 17
ADP5074
Data Sheet
THEORY OF OPERATION
V
IN
C
IN
C
VREG
SYNC/
FREQ
AVIN
VREG
PVIN
CURRENT
SENSE
HIGH VOLTAGE
REGULATOR
INVERTER
PWM CONTROL
D1
HIGH VOLTAGE
BAND GAP
SW
EN
SLEW
L1
C
OUT
SLEW
PLL
R
FT
ERROR AMP
REF
OSCILLATOR
FB
R
CONTROL
THERMAL
FB
VREG
EN
VREF
REF_1.6V
VREG
4µA
R
PG
REF FB
(OPTIONAL)
SHUTDOWN
PWRGD
COMP
C
VREF
UVLO
POWER
GOOD
REF
REF_1.6V
REFERENCE
GENERATOR
START-UP
TIMERS
R
C
OVP
C
C
SS
GND
R
(OPTIONAL)
SS
Figure 21. Functional Block Diagram
PWM MODE
OSCILLATOR AND SYNCHRONIZATION
The inverting regulator in the ADP5074 operates at a fixed fre-
quency set by an internal oscillator. At the start of each oscillator
cycle, the MOSFET switch turns on, applying a positive voltage
across the inductor. The inductor current (IINDUCTOR) increases
until the current sense signal crosses the peak inductor current
threshold that turns off the MOSFET switch; this threshold is set
by the error amplifier output. During the MOSFET off time, the
inductor current declines through the external diode until the next
oscillator clock pulse starts a new cycle. The ADP5074 regulates the
output voltage by adjusting the peak inductor current threshold.
A phase-locked loop (PLL)-based oscillator generates the internal
clock and offers a choice of two internally generated frequency
options or external clock synchronization. The switching frequency
is configured using the SYNC/FREQ pin options shown in Table 6.
For external synchronization, connect the SYNC/FREQ pin to a
suitable clock source. The PLL locks to an input clock within
the range specified by fSYNC
.
Table 6. SYNC/FREQ Pin Options
SYNC/FREQ Pin
High
Switching Frequency
2.4 MHz
SKIP MODE
Low
1.2 MHz
During light load operation, the regulator can skip pulses to
maintain output voltage regulation. Skipping pulses increases
the device efficiency. The COMP voltage is monitored internally
and when it falls below a threshold (due to the output voltage
rising above the target during a switching cycle), the next switching
cycle is skipped. This voltage is monitored on a cycle-by-cycle
basis. During skip operation, the output ripple is increased and
the ripple frequency varies. The choice of inductor defines the
output current below which skip mode occurs.
External Clock
1× clock frequency
INTERNAL REGULATORS
The internal VREG regulator in the ADP5074 provides a stable
power supply for the internal circuitry. The VREG supply provides
a high signal for device configuration pins but must not be used
to supply external circuitry.
The VREF regulator provides a reference voltage for the inverting
regulator feedback network to ensure a positive feedback voltage
on the FB pin. A current-limit circuit is included for both internal
regulators to protect the circuit from accidental loading.
UNDERVOLTAGE LOCKOUT (UVLO)
The UVLO circuitry monitors the AVIN pin voltage level. If the
input voltage drops below the VUVLO_FALLING threshold, the
regulator turns off. After the AVIN pin voltage rises above the
V
UVLO_RISING threshold, the soft start period initiates, and the
regulator is enabled.
Rev. A | Page 10 of 17
Data Sheet
ADP5074
When the peak inductor current exceeds the current-limit
PRECISION ENABLING
threshold, the power MOSFET switch is turned off for the
remainder of that switch cycle. If the peak inductor current
continues to exceed the overcurrent limit, the regulator enters
hiccup mode. The regulator stops switching and then restarts
with a new soft start cycle after tHICCUP and repeats until the
overcurrent condition is removed.
The ADP5074 has an enable pin that features a precision enable
circuit with an accurate reference voltage. This reference allows the
ADP5074 to be sequenced easily from other supplies. It can also
be used as a programmable UVLO input by using a resistor divider.
The enable pin has an internal pull-down resistor that defaults
to off when the pin is floating. When the voltage at the enable pin is
greater than the VTH_H reference level, the regulator is enabled.
OVERVOLTAGE PROTECTION
An overvoltage protection mechanism is present on the FB pin
for the inverting regulator.
SOFT START
The regulator in the ADP5074 includes soft start circuitry that
ramps the output voltage in a controlled manner during startup,
thereby limiting the inrush current. The soft start time is internally
set to the fastest rate when the SS pin is open.
When the voltage on the FB pin drops below the VOV threshold,
the switching stops until the voltage rises above the threshold.
This functionality is enabled after the soft start period has elapsed.
POWER GOOD
Connecting a resistor between SS and ground allows the
adjustment of the soft start delay.
The ADP5074 provides an open-drain power-good output to
indicate when the output voltage reaches a target level.
SLEW RATE CONTROL
A pull-up voltage must be provided on the PWRGD pin through
an external resistor to provide a high output when the power is
good. The pull-up voltage is typically sourced from the VREG pin
although an external supply may be used with a maximum voltage
of VDS_PG (MAX). The power-good FET pulls down when the supply
on the PVIN pin rises above VPG (SUPPLY) and the FET remains on
until the enable is brought high and soft start has completed. Note
that if an external supply is used, the power-good output may be
The ADP5074 uses programmable output driver slew rate
control circuitry. This circuitry reduces the slew rate of the
switching node as shown in Figure 22, resulting in reduced
ringing and lower EMI. To program the slew rate, connect the
SLEW pin to the VREG pin for normal mode, to the GND pin
for slow mode, or leave it open for fast mode. This logic allows the
use of an open-drain output from a noise sensitive device to
switch the slew rate from fast to slow, for example, during
analog-to-digital converter (ADC) sampling.
high until PVIN reaches VDS_PG (MAX)
.
As soon as the device is enabled and soft start is complete, the
power-good function monitors the voltage on the FB pin. If the
voltage VREF − VFB is greater than the VPG (GOOD) threshold, the
power-good FET turns off, allowing the power-good output to
be pulled up to VREG or an external supply signaling a power-
good valid condition. If the voltage VREF − VFB is less than the
Note that slew rate control causes a trade-off between efficiency
and low EMI.
FASTEST
VPG (BAD) threshold, the power-good FET turns on, pulling the
output to GND, indicating the power output is not good.
SLOWEST
THERMAL SHUTDOWN
In the event that the ADP5074 junction temperature rises above
T
SHDN, the thermal shutdown circuit turns off the IC. Extreme
junction temperatures can be the result of prolonged high current
operation, poor circuit board design, and/or high ambient
temperature. Hysteresis is included so that when thermal shutdown
occurs, the ADP5074 does not return to operation until the on-
chip temperature drops below TSHDN − THYS. When resuming from
thermal shutdown, a soft start is performed.
Figure 22. Switching Node at Various Slew Rate Settings
CURRENT-LIMIT PROTECTION
The inverting regulator in the ADP5074 includes current-limit
protection circuitry to limit the amount of forward current
allowed through the MOSFET switch.
Rev. A | Page 11 of 17
ADP5074
Data Sheet
APPLICATIONS INFORMATION
Output Capacitor
ADIsimPOWER DESIGN TOOL
Higher output capacitor values reduce the output voltage ripple
and improve load transient response. When choosing this value,
it is also important to account for the loss of capacitance due to
the output voltage dc bias.
The ADP5074 is supported by the ADIsimPower™ design tool
set. ADIsimPower is a collection of tools that produce complete
power designs optimized to a specific design goal. These tools
allow the user to generate a full schematic, bill of materials, and
calculate performance in minutes. ADIsimPower can optimize
designs for cost, area, efficiency, and device count while taking
into consideration the operating conditions and limitations of
the IC and all real external components. The ADIsimPower tool
can be found at www.analog.com/adisimpower, and the user
can request an unpopulated board through the tool.
Ceramic capacitors are manufactured with a variety of dielectrics,
each with a different behavior over temperature and applied
voltage. Capacitors must have a dielectric adequate to ensure
the minimum capacitance over the necessary temperature range
and dc bias conditions. X5R or X7R dielectrics with a voltage rating
of 25 V or 50 V (depending on output) are recommended for
best performance. Y5V and Z5U dielectrics are not recommended
for use with any dc-to-dc converter because of their poor
temperature and dc bias characteristics.
COMPONENT SELECTION
Feedback Resistors
The ADP5074 provides an adjustable output voltage. An external
resistor divider sets the output voltage, where the divider output
must equal the feedback reference voltage, VFB. To limit the output
voltage accuracy degradation due to feedback bias current, ensure
that the current through the divider is at least 10 × IFB.
Calculate the worst case capacitance accounting for capacitor
variation over temperature, component tolerance, and voltage
using the following equation:
C
EFFECTIVE = CNOMINAL × (1 − TEMPCO) × (1 − DCBIASCO) ×
(1 − Tolerance)
where:
Set the negative output for the inverting regulator by
R
R
FT
VOUT = VFB
−
(
VREF −VFB
)
C
C
EFFECTIVE is the effective capacitance at the operating voltage.
NOMINAL is the nominal data sheet capacitance.
FB
where:
TEMPCO is the worst case capacitor temperature coefficient.
DCBIASCO is the dc bias derating at the output voltage.
Tolerance is the worst case component tolerance.
V
V
OUT is the negative output voltage.
FB is the FB reference voltage.
R
R
FT is the feedback resistor from VOUT to FB.
FB is the feedback resistor from FB to VREF.
To guarantee the performance of the device, it is imperative that
the effects of dc bias, temperature, and tolerances on the behavior
of the capacitors be evaluated for each application.
VREF is the VREF pin reference voltage.
Table 7 shows recommended values for common output
voltages using standard resistor values.
Capacitors with lower effective series resistance (ESR) and
effective series inductance (ESL) are preferred to minimize
output voltage ripple.
Table 7. Recommended Feedback Resistor Values
Desired Output
Voltage (V)
Actual Output
Voltage (V)
Note that the use of large output capacitors may require a slower
soft start to prevent current limit during startup. A 10 µF capacitor
is suggested as a good balance between performance and size.
RFT (MΩ)
0.332
0.475
0.523
0.715
1.15
1.62
1.15
2.8
2.32
RFB (kΩ)
102
100
102
115
158
133
71.5
162
118
113
113
102
107
115
−1.8
−3
−1.804
−3.000
Input Capacitor
−3.3
−4.2
−5
−3.302
−4.174
−5.023
−8.944
−12.067
−13.027
−14.929
−18.103
−20.014
−23.984
−30.004
−34.748
Higher value input capacitors help reduce the input voltage
ripple and improve transient response.
−9
To minimize supply noise, place the input capacitor as close as
possible to the AVIN and PVIN pins. A low ESR capacitor is
recommended.
−12
−13
−15
−18
−20
−24
−30
−35
For stability, the use of a good quality 10 µF ceramic capacitor
with low dc bias effects is recommended. If the power pins are
individually decoupled, it is recommended to use a minimum
of a 5.6 µF capacitor on the PVIN pin and a 3.3 µF capacitor on
the AVIN pin.
2.67
2.94
3.16
4.12
5.11
Rev. A | Page 12 of 17
Data Sheet
ADP5074
VREG Capacitor
For the inductor ripple current in continuous conduction mode
(CCM) operation, the input (VIN) and output (VOUT) voltages
determine the switch duty cycle (Duty) by the following equation:
A 1.0 µF ceramic capacitor (CVREG) is required between the
VREG pin and GND.
|VOUT | + VDIODE
VIN + |VOUT | + VDIODE
VREF Capacitor
Duty =
A 1.0 µF ceramic capacitor (CVREF) is required between the
VREF pin and GND.
where VDIODE is the forward voltage drop of the Schottky diode
Soft Start Resistor
(D1).
A resistor (RSS) can be connected between the SS pin and the GND
pin to increase the soft start time. The soft start time can be set
using this resistor between 4 ms (268 kΩ) and 32 ms (50 kΩ).
Leaving the SS pin open selects the fastest time of 4 ms. Figure 23
shows the behavior of this operation. Calculate the soft start time
(tSS) using the following formula:
Determine the dc current in the inductor in CCM (IL1) using
the following equation:
IOUT
(1− Duty)
IL1
=
Using the duty cycle (Duty) and switching frequency (fSW),
determine the on time (tON) using the following equation:
t
SS = 38.4 × 10−3 − 1.28 × 10−7 × RSS (Ω)
Duty
fSW
tON
=
where 50 kΩ ≤ RSS ≤ 268 kΩ.
SOFT START
TIMER
The inductor ripple current (∆IL1) in steady state is calculated by
VIN × tON
32ms
∆IL1
=
L1
Solve for the inductance value (L1) using the following equation:
VIN × tON
L1 =
4ms
SS PIN OPEN
R1
∆IL1
SOFT START
RESISTOR
R2
Assuming an inductor ripple current of 30% of the maximum
dc current in the inductor results in
Figure 23. Soft Start Behavior
VIN × tON × (1 − Duty)
Diodes
L1 =
0.3 × IOUT
A Schottky diode with low junction capacitance is recommended
for D1. At higher output voltages and especially at higher switching
frequencies, the junction capacitance is a significant contributor to
efficiency. Higher capacitance diodes also generate more switching
noise. As a guide, a diode with less than 40 pF junction capacitance
is preferred when the output voltage is in the range of −5 V to −37 V.
Ensure that the peak inductor current (the maximum input
current plus half the inductor ripple current) is below the rated
saturation current of the inductor. Likewise, ensure that the
maximum rated rms current of the inductor is greater than the
maximum dc input current to the regulator.
Inductor Selection
When operating the ADP5074 inverting regulator in CCM, for
stable current mode operation, ensure that the selected
inductance is equal to or greater than the minimum calculated
inductance, LMIN, for the application parameters in the following
equation:
The inductor stores energy during the on time of the power
switch, and transfers that energy to the output through the
output rectifier during the off time. To balance the trade-offs
between small inductor current ripple and efficiency, inductance
values in the range of 1 µH to 22 µH are recommended. In
general, lower inductance values have higher saturation current
and lower series resistance for a given physical size. However,
lower inductance results in a higher peak current that can lead
to reduced efficiency and greater input and/or output ripple and
noise. A peak-to-peak inductor ripple current close to 30% of
the maximum dc current in the inductor typically yields an
optimal compromise.
0.13
(µH)
L1 > LMIN = VIN
×
− 0.16
(1 − Duty)
Table 9 suggests a series of inductors to use with the ADP5074
inverting regulator.
For the smallest solution size, inductors with a saturation
current below ILIM may be used when the output current in the
application is such that the inductor current stays below the
saturated region.
Rev. A | Page 13 of 17
ADP5074
Data Sheet
Loop Compensation
Therefore, when solving for the crossover frequency, the equation
(by definition of the crossover frequency) is simplified to
The ADP5074 uses external components to compensate the
regulator loop, allowing the optimization of the loop dynamics
for a given application. It is recommended to use the ADIsimPower
tool to calculate compensation components.
VFB
VIN
AVL
=
×
×GM ×
|VOUT| (VIN + 2 ×|VOUT|)
1
RC ×GCS
×
=1
The inverting converter, produces a right half plane zero in the
regulation feedback loop. This feedback loop requires compensat-
ing the regulator such that the crossover frequency occurs well
below the frequency of the right half plane zero. The right half
plane zero frequency is determined by the following equation:
2π × fC ×COUT
where fC is the crossover frequency.
To solve for RC, use the following equation:
2π × fC × COUT ×|VOUT|×(VIN + (2 ×|VOUT|)
RC =
RLOAD(1 − Duty)2
2π × L1× Duty
VFB ×VIN × GM × GCS
fZ (RHP) =
where GCS = 12.5 A /V.
where:
Using typical values for VFB and GM results in
fZ (RHP) is the right half plane zero frequency.
2094 × fC ×COUT ×|VOUT|× (VIN + (2 ×|VOUT|)
RLOAD is the equivalent load resistance or the output voltage
RC =
VIN
divided by the load current.
For better accuracy, it is recommended to use the value of
output capacitance (COUT) that takes into account the capacitance
reduction from dc bias in the calculation for RC.
|VOUT| +VDIODE
VIN +|VOUT| + VDIODE
Duty =
where VDIODE is the forward voltage drop of the Schottky diode
(D1).
After the compensation resistor is known, set the zero formed
by CC and RC to one-fourth of the crossover frequency, or
To stabilize the regulator, ensure that the regulator crossover
frequency is less than or equal to one-tenth of the right half
plane zero frequency.
2
CC =
π × fC ×RC
where CC is the compensation capacitor.
The regulator loop gain is
ERROR
AMPLIFIER
FB
VFB
|VOUT
VIN
COMP
AVL
=
×
× GM ×
g
M
|
(VIN + 2 ×|VOUT|)
REF
R
C
C
ROUT||ZCOMP × GCS × ZOUT
B
C
C
where:
A
V
V
V
VL is the regulator loop gain.
FB is the feedback regulation voltage.
OUT is the regulated negative output voltage.
IN is the input voltage.
Figure 24. Compensation Components
The optional capacitor, CB, is chosen to cancel the zero
introduced by the ESR of the output capacitor. For low ESR
capacitors such as ceramic chip capacitors, CB can be omitted
from the design.
GM is the error amplifier transconductance gain.
R
Z
OUT is the output impedance of the error amplifier and is 33 MΩ.
COMP is the impedance of the series RC network from COMP
Solve for CB as follows:
to GND.
G
ESR × COUT
CS is the current sense transconductance gain (the inductor
CB =
current divided by the voltage at COMP), which is internally
set by the ADP5074 and is 12.5 A/V.
RC
For optimal transient performance, RC and CC may need to be
adjusted by observing the load transient response of the ADP5074.
For most applications, RC is within the range of 1 kΩ to 200 kΩ,
and CC is within the range of 1 nF to 68 nF.
ZOUT is the impedance of the load in parallel with the output
capacitor.
To determine the crossover frequency, it is important to note
that, at that frequency, the compensation impedance (ZCOMP) is
dominated by a resistor, RC, and the output impedance (ZOUT) is
dominated by the impedance of the output capacitor (COUT).
Rev. A | Page 14 of 17
Data Sheet
ADP5074
output. Table 8 shows the components common to all VIN and
COMMON APPLICATIONS
V
OUT conditions.
Table 8 and Table 9 list a number of common component
selections for typical VIN and VOUT conditions. These have been
bench tested and provide an off the shelf solution. To optimize
components for an application, it is recommended to use the
ADIsimPower tool set.
Table 8. Recommended Common Components Selections
Reference Value (µF) Part Number Manufacturer
CIN
CVREG
CVREF
10
1
1
TMK316B7106KL-TD
GRM188R71A105KA61D
GRM188R71A105KA61D
Taiyo Yuden
Murata
Murata
Figure 25 shows the schematic referenced by Table 8 and Table 9
with example component values for a +5 V input to a −15 V
C
VREF
1µF
AVIN
VREF
V
IN
+12V
R
PVIN
FB
158kΩ
C
10µF
IN
ADP5074
FB
R
FT
ON
1.15MΩ
OFF
PG
EN
V
OUT
–5V
C
VREG
1µF
SW
D1
C
OUT
10µF
VREG
DFLS240L
R
L1
SS
5.6µH
1MΩ
PWRGD
C
PWRGD
COMP
SLEW
SYNC/FREQ
R
820Ω
C
C
GND
180nF
Figure 25. Typical +12 V Input to −5 V Output, 1.2 MHz Application
Table 9. Recommended Inverting Regulator Components
VIN
(V) (V)
VOUT Freq.
(MHz)
−2.5 1.2
−2.5 2.4
−3.3 1.2
−3.3 2.4
L1
COUT
(µF)
D1, Diodes,
Inc., Part
RFT
(MΩ)
RFB
CC
RC
(µH) L1, Coilcraft® Part
COUT, Murata Part
(kΩ) (nF) (kΩ)
3.3
3.3
3.3
3.3
3.3
3.3
5
5
5
5
5
2.2
1
XAL4020-222ME_
XAL4020-102ME_
XAL4020-222ME_
XAL4020-122ME_
XAL4020-222ME_
XAL4020-152ME_
XAL4030-332ME_
XAL4020-222ME_
XAL4020-122ME_
XAL4020-222ME_
XAL5050-562ME_
XAL5050-562ME_
XAL4030-332ME_
XAL4020-152ME_
XAL5050-562ME_
XAL4020-222ME_
XAL4040-103ME_
XAL4030-472ME_
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
GRM32ER71H106KA12L
GRM32ER71H106KA12L
GRM32ER71H106KA12L
GRM32ER71H106KA12L
GRM32ER71H106KA12L
GRM32ER71H106KA12L
GRM32ER71H106KA12L
GRM32ER71H106KA12L
GRM32ER71H106KA12L
GRM32ER71H106KA12L
GRM32ER71H106KA12L
GRM32ER71H106KA12L
GRM32ER71H106KA12L
GRM32ER71H106KA12L
GRM32ER71H106KA12L
GRM32ER71H106KA12L
GRM32ER71H106KA12L
GRM32ER71H106KA12L
DFLS240L
DFLS240L
DFLS240L
DFLS240L
DFLS240L
DFLS240L
DFLS240L
DFLS240L
DFLS240
DFLS240
DFLS240
DFLS240
DFLS240L
DFLS240L
DFLS240L
DFLS240L
DFLS240
DFLS240
0.432
0.432
0.532
0.532
1.15
1.15
1.15
1.15
2.32
2.32
4.12
4.12
0.432
0.432
1.15
1.15
2.32
2.32
107
107
102
102
158
158
158
158
118
118
107
107
107
107
158
158
118
118
270
47
120
33
39
22
82
33
15
2.2
3.3
3.9
470
82
180
22
27
0.56
1.3
1
2.2
1.2
2.2
1.5
3.3
2.2
5.6
2.2
5.6
5.6
3.3
1.5
5.6
2.2
10
2
−5
−5
−5
−5
−15
−15
−30
−30
1.2
2.4
1.2
2.4
1.2
2.4
1.2
2.4
2.7
3.6
1.6
2.3
9.1
24
39
36
5
12
12
12
12
12
12
−2.5 1.2
−2.5 2.4
0.33
0.75
0.82
2.2
4.9
10
−5
−5
−15
−15
1.2
2.4
1.2
2.4
4.7
6.8
Rev. A | Page 15 of 17
ADP5074
Data Sheet
Avoid routing high impedance traces near any node con-
nected to the SW pin or near Inductor L1 to prevent radiated
switching noise injection.
Place the feedback resistors as close to the FB pin as possible
to prevent high frequency switching noise injection.
Route a trace to RFT directly from the COUT pad for
optimum output voltage sensing.
Place the compensation components as close as possible to
COMP. Do not share vias to the ground plane with the
feedback resistors to avoid coupling high frequency noise into
the sensitive COMP pin.
Place the CVREF and CVREG capacitors as close to the
VREG and VREF pins as possible. Ensure that short traces
are used between VREF and RFB.
LAYOUT CONSIDERATIONS
PCB layout is important for all switching regulators but is
particularly important for regulators with high switching
frequencies. To achieve high efficiency, good regulation, good
stability, and low noise, a well designed PCB layout is required.
Follow these guidelines when designing PCBs:
Keep the input bypass capacitor, CIN, close to the PVIN pin
and the AVIN pin. Route each of these pins individually to
the pad of this capacitor to minimize noise coupling
between the power inputs, rather than connecting the two
pins at the device. A separate capacitor can be used on the
AVIN pin for the best noise performance.
Keep the high current paths as short as possible. These
paths include the connections between CIN, L1, D1,
COUT, and GND and their connections to the ADP5074.
Keep high current traces as short and wide as possible to
minimize parasitic series inductance, which causes spiking
and EMI.
14mm
COUT
VOUT
GND
VIN
D1
CIN
L1
CVREG
CVREF
U1
GND
CC RC
RFT
RFB
Figure 26. Suggested Layout for 18 mm × 14 mm, +12 V Input to −5 V Output Application
(Dashed Line Is Connected on the Internal Layer of the PCB; Other Vias Connected to the Ground Plane;
SS, EN, PWRGD, SLEW, and SYNC/FREQ Connections Not Shown for Clarity and Are Typically Connected on an Internal Layer)
Rev. A | Page 16 of 17
Data Sheet
ADP5074
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
3.10
3.00 SQ
2.90
0.30
0.23
0.18
PIN 1
INDICATOR
PIN 1
13
16
TIONS
INDICATOR AREA OP
(SEE DETAIL A)
0.50
BSC
12
1
1.75
1.60 SQ
1.45
EXPOSED
PAD
9
4
8
5
0.50
0.40
0.30
0.20 MIN
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TOJEDEC STANDARDS MO-220-WEED-6.
Figure 27. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-22)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
Branding Code
ADP5074ACPZ-R7
ADP5074CP-EVALZ
−40°C to +125°C
16-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
CP-16-22
LR0
1 Z = RoHS Compliant Part.
©2015–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12818-0-10/17(A)
Rev. A | Page 17 of 17
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