ADP5138W-1-EVALZ [ADI]
Quad, 1 A, 5.5 V, Synchronous Step-Down Regulators with One RF LDO Regulator;型号: | ADP5138W-1-EVALZ |
厂家: | ADI |
描述: | Quad, 1 A, 5.5 V, Synchronous Step-Down Regulators with One RF LDO Regulator |
文件: | 总23页 (文件大小:571K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Quad, 1 A, 5.5 V, Synchronous Step-Down
Regulators with One RF LDO Regulator
Data Sheet
ADP5138
FEATURES
TYPICAL APPLICATION CIRCUIT
V
OUT1
PVINx voltage range: 3 V to 5.5 V
Continuous output current
Channel 1 to Channel 4 (buck): 1 A
Channel 5 (LDO): 250 mA
3.2 MHz fixed PWM switching frequency
Synchronization input function
Buck regulators run at 90° out of phase
Individual precision enable input
Power-on reset output
ADP5138
R
POR
L1
POR
= 3.3V
AVIN
POR
C
AVIN
V
OUT1
EN1
V
= 5V ± 10%
SW1
FB1
IN
PVIN1
C
OUT1
C
IN1
PGND1
L2
V
= 1.0V
OUT2
EN2
SW2
PVIN2
C
R
R
OUT2
TOP2
C
C
C
C
IN2
FB2
Integrated compensation
R
BOT2
L3
PGND2
Soft start and power-up sequencing reduce inrush current
Active output discharge switch function
Stable with low ESR output ceramic capacitors
OVLO, UVM, and UVLO
TSD protection
Qualified for automotive applications
V
= 1.25V
OUT3
EN3
SW3
PVIN3
C
OUT3
TOP3
IN3
IN4
IN5
FB3
R
BOT3
L4
PGND3
V
= 1.35V
OUT4
EN4
SW4
FB4
PVIN4
C
OUT4
APPLICATIONS
PGND4
Automotive
Industrial and instrumentation
DC to dc point of load applications
V
= 1.8V
OUT5
EN5
VOUT5
FB5
R
TOP5
PVIN5
C
OUT5
SYNC GND
R
BOT5
Figure 1.
GENERAL DESCRIPTION
The ADP5138 integrates four high performance synchronous
step-down regulators and one low noise radio frequency (RF)
low dropout (LDO) regulator. The device runs from PVINx
input voltages of 3 V to 5.5 V. The output voltage of each
channel is factory set or can be programmed down to 0.8 V
with a resistor. Each step-down regulator can provide up to 1 A
of continuous output current and the LDO can provide 250 mA
of output current.
The ADP5138 integrates internal compensation to simplify
the design. The internal soft start circuitry and power-up
sequencing help reduce the input inrush current.
The ADP5138 monitors the input voltage and provides input
overvoltage lockout (OVLO), undervoltage monitor (UVM),
and undervoltage lockout (UVLO) features. It also monitors the
undervoltage and overvoltage of the outputs. The power-on
reset (POR) signal is asserted when the input or output voltage
fault occurs.
The ADP5138 runs at the fixed PWM switching frequency,
3.2 MHz, or can be synchronized to the external clock from
2.8 MHz to 3.5 MHz, which is outside the amplitude
modulation (AM) band. The four buck regulators run at 90°
out of phase to reduce the input ripple current and the input
capacitor size, thereby helping to lower system electromagnetic
interference (EMI).
Additional protection includes overcurrent protection (OCP)
and thermal shutdown (TSD).
The ADP5138 operates over the −40°C to +125°C operating
temperature range (junction), and is available in a 28-lead
LFCSP package.
Rev. A
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Technical Support
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ADP5138
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Input Overvoltage Lockout (OVLO)....................................... 17
Input Undervoltage Monitor (UVM) ...................................... 17
Input Undervoltage Lockout (UVLO)..................................... 17
Output Voltage Power-Good.................................................... 17
Power-On Reset (POR) ............................................................. 18
Soft Start and Power-Up Sequence .......................................... 18
Current-Limit and Short-Circuit Protection.......................... 18
Active Output Discharge........................................................... 19
Thermal Shutdown .................................................................... 19
Applications Information .............................................................. 20
Input Capacitor Selection.......................................................... 20
Output Voltage Setting .............................................................. 20
Inductor Selection ...................................................................... 20
Output Capacitor Selection....................................................... 20
Application Circuit..................................................................... 21
Factory-Programmable Options .................................................. 22
Outline Dimensions....................................................................... 23
Ordering Guide .......................................................................... 23
Automotive Products................................................................. 23
Applications....................................................................................... 1
Typical Application Circuit ............................................................. 1
General Description......................................................................... 1
Table of Contents .............................................................................. 2
Revision History ........................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
Buck Regulator Specifications .................................................... 5
LDO Regulator Specifications .................................................... 6
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 17
Control Scheme .......................................................................... 17
Precision Enable and Shutdown............................................... 17
Oscillator and Phase Shift ......................................................... 17
Synchronization.......................................................................... 17
REVISION HISTORY
8/2018—Rev. 0 to Rev. A
Change to Figure 2 ........................................................................... 3
5/2018—Revision 0: Initial Version
Rev. A | Page 2 of 23
Data Sheet
ADP5138
FUNCTIONAL BLOCK DIAGRAM
CHANNEL 1: BUCK REGULATOR 1
PVIN1
A
1
CS
HIGH-SIDE
CURRENT SENSE
OCP
I
LIM
PVIN1
SLOPE RAMP
SOFT
DRIVER
START
V
CMP1
TSD
REF
EA1
FB1
DIVIDER
SW1
CONTROL
LOGIC AND
MOSFET
110% × V
REF
PVIN1
DRIVER
PGOOD1
WITH
ANTICROSS
PROTECTION
DRIVER
PGND1
95% × V
REF
UVLO
OVLO
1.2V
EN_DELAY
LOW-SIDE
CURRENT
SENSE
EN1_BUF
EN1
CLK1
PVIN2
FB2
EN2
CHANNEL 2: BUCK REGULATOR 2
CHANNEL 3: BUCK REGULATOR 3
SW2
PGND2
PVIN3
SW3
FB3
EN3
PGND3
PVIN4
SW4
FB4
EN4
CHANNEL 4: BUCK REGULATOR 4
CHANNEL 5: LDO
PGND4
PVIN5
EN5
VOUT5
FB5
V
REF
EN5_BUF
1.2V
EN_DELAY
EA5
110% × V
UVLO
OVLO
TSD
REF
LDO
CONTROL
PGOOD5
95% × V
REF
COMMON BLOCK
EN1_BUF
EN2_BUF
EN3_BUF
EN4_BUF
EN5_BUF
CLK1
SLOPE RAMP1
CLK2
EN_SYS
UVLO
SLOPE RAMP2
CLK3
OSC
SYNC
2.8V
SLOPE RAMP3
CLK4
AVIN
4.2V
5.8V
VIN_OK
UVM
SLOPE RAMP4
OVLO
POR
GND
TSD
POR DELAY
TIME AND
CONTROL LOGIC
TSD
THERMAL
PGOOD1
EN1_BUF
PGOOD2
EN2_BUF
EN3_BUF
VOUT_OK
PGOOD3
PGOOD4
PGOOD5
EN4_BUF
EN5_BUF
ADP5138
Figure 2.
Rev. A | Page 3 of 23
ADP5138
Data Sheet
SPECIFICATIONS
VAVIN = VPVIN1 = VPVIN2 = VPVIN3 = VPVIN4 = VPVIN5 = 5.0 V, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C
for typical specifications, unless otherwise noted. VOUTx is the output voltage on Channel x, where x is 1 to 5.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
POWER INPUT
PVINx Voltage Range
VPVINx
PVIN1, PVIN2, PVIN3, and PVIN4 pins
PVIN5 pin
AVIN pin
No switching
VEN1 = VEN2 = VEN3 = VEN4 = VEN5 = GND
3
1.7
3
5.5
5.5
5.5
7.5
20
V
V
V
mA
µA
AVIN Voltage Range
Quiescent Current
Shutdown Current
VAVIN
IQ
ISHDN
6
0.6
Input UVLO Threshold
AVIN UVLO Rising
AVIN UVLO Falling
2.9
2.8
3
V
V
2.7
Input Undervoltage Monitor Threshold
AVIN UVM Falling
AVIN UVM Hysteresis
Input OVLO Threshold
AVIN OVLO Rising
AVIN OVLO Hysteresis
ENABLE
Rising Threshold
4.05
4.2
80
4.35
100
V
mV
5.6
5.8
80
6
100
V
mV
ENx pins
POR pin
1.2
1.1
1
1.28
V
V
MΩ
Falling Threshold
1.02
Pull-Down Resistance
POWER-ON RESET (POR)
Output Undervoltage Threshold
Rising Threshold
Percentage of normal VOUTx
Percentage of normal VOUTx
93
91
95
93
97
95
%
%
Falling Threshold
Output Overvoltage Threshold
Rising Threshold
Falling Threshold
Percentage of normal VOUTx
Percentage of normal VOUTx
108
105.5
110
108
112
110
%
%
Deglitch Time
POR Rising
POR Falling
tPOR_DELAY_R
tPOR_DELAY_F
5
5.7
10
6.8
ms
µs
POR Leakage Current
POR Output Low Voltage
POR Effective Threshold Voltage on AVIN1
START-UP SEQUENCE DELAY TIME
THERMAL SHUTDOWN
Threshold1
POR voltage (VPOR) = 5 V
POR current (IPOR) = 3 mA
IPOR = 1 mA, VPOR ≤ 0.2 V
Delay time during startup
0.05
38
1
µA
mV
V
100
1.16
700
VAVIN_POR
tSS_D
500
600
µs
150
15
°C
°C
Hysteresis1
1 Guaranteed by design, but not production tested.
Rev. A | Page 4 of 23
Data Sheet
ADP5138
BUCK REGULATOR SPECIFICATIONS
VAVIN = VPVIN1 = VPVIN2 = VPVIN3 = VPVIN4 = 5.0 V, T J = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for
typical specifications, unless otherwise noted.
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min
Typ Max
Unit
FEEDBACK
FB1 to FB4 Regulation Voltage
Fixed Output Accuracy1
OUTPUT CHARACTERISTICS
Load Regulation2
VFB1 to VFB4
VOUT1 to VOUT4
Adjustable version
0.788 0.8
−2
0.812
+2
V
%
Pulse-width modulation (PWM) mode
Output current (IOUT) from 0 A to 1 A, VAVIN = VPVINx = 5 V
VAVIN = VPVINx = 4 V to 5.5 V, IOUT = 1 A
∆VOUT/∆IOUT
∆VOUT/∆VPVIN
0.3
0.1
%/A
%/V
Line Regulation2
SWITCH NODE
High-Side On Resistance3
Low-Side On Resistance3
SWx Leakage Current
CURRENT LIMIT
RDSON_H
RDSON_L
ISW_LK
VAVIN = VPVINx = 5 V, ISWx = 0.5 A
VAVIN = VPVINx = 5 V, ISWx = 0.5 A
VAVIN = VPVINx = 5 V, SWx = GND or SWx = VPVINx
130 200
120 200
0.1
mΩ
mΩ
µA
High-Side Peak Current Limit
Low-Side Sink Current Limit
PWM SWITCHING FREQUENCY
PHASE SHIFT
1.28
3
1.6
1
1.92
3.4
A
A
fSW
3.2
90
MHz
Degrees
Phase shift between channels
SYNC pin
SYNC
Synchronization Range
SYNC Minimum On Time
SYNC Minimum Off Time
SYNC Input Voltage
High
2.8
100
100
3.5
MHz
ns
ns
1.2
V
V
Ω
Low
0.4
OUTPUT DISCHARGE RESISTANCE
RDISCHARGE1 to
RDISCHARGE4
64
100
SOFT START TIME
tSS1 to tSS4
425
500 575
µs
1 VOUT1 to VOUT4 are the output voltages on Channel 1 to Channel 4.
2 Bench characterization result.
3 Pin to pin measurement.
Rev. A | Page 5 of 23
ADP5138
Data Sheet
LDO REGULATOR SPECIFICATIONS
VAVIN = 5.0 V, VPVIN5 = (output voltage of Channel 5 (VOUT5) + 0.5 V) or 3 V (whichever is greater), input capacitance of Channel 5 (CIN5) =
output capacitance of Channel 5 (COUT5) = 1 μF, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for
typical specifications, unless otherwise noted.
Table 3.
Parameter
Symbol
IQ_LDO5
IOUT5
Test Conditions/Comments
Min
Typ
Max
Unit
CURRENT
Operating Quiescent Current
IOUT5 = 0 µA, VOUT5 = 1.8 V
IOUT5 = 100 mA, VOUT5 = 1.8 V
VPVIN5 ≥ 3 V
1.7 V ≤ VPVIN5 < 3 V
VOUT5 drops 5% from nominal voltage
58
146
100
300
250
100
µA
µA
mA
mA
mA
Output Current
Current Limit
300
400
FEEDBACK
FB5 Regulation Voltage
Fixed Output Voltage Accuracy
VFB5
VOUT5
Adjustable version
IOUT5 = 10 mA, TJ = 25°C
1 mA < IOUT5 < 250 mA
0.788 0.8
−1
−2
0.812
+1
+2
V
%
%
REGULATION
Load Regulation
Line Regulation
DROPOUT VOLTAGE1
IOUT5 from 1 mA to 250 mA
IOUT5 = 10 mA
0.002 0.005 %/mA
−0.1
420
+0.1
%/V
mV
mV
Ω
VDROPOUT5
VOUT5 = 3.3 V, IOUT5 = 250 mA
VOUT5 = 1.8 V, IOUT5 = 100 mA
173
132
83
OUTPUT DISCHARGE RESISTANCE
SOFT START TIME
OUTPUT NOISE2
RDISCHARGE5
tSS5
120
720
VOUT5 = 1.8 V, IOUT5 = 250 mA
570
20
µs
OUTNOISE5 10 Hz to 100 kHz, VPVIN5 = 5 V, VOUT5 = 1.8 V, IOUT5
250 mA, adjustable output option
=
µV rms
POWER SUPPLY REJECTION RATIO2 PSRRLDO5
1 kHz, VPVIN5 = 5 V, VOUT5 = 1.8 V, IOUT5 = 250 mA,
adjustable output option
55
dB
1 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage.
2 Bench characterization result.
Rev. A | Page 6 of 23
Data Sheet
ADP5138
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment.
Parameter
Rating
PVIN1, PVIN2, PVIN3, PVIN4, PVIN5, AVIN,
VOUT5
SW1, SW2, SW3, SW4
FB1, FB2, FB3, FB4, FB5, EN1, EN2, EN3, EN4,
EN5, POR, SYNC
−0.3 V to +6 V
Careful attention to PCB thermal design is required.
−0.3 V to +6 V
−0.3 V to +6 V
Table 5. Thermal Resistance
Package Type
1
θJA
θJC
Unit
PGND1, PGND2, PGND3, PGND4 to GND
Operating Temperature Range (Junction)
Storage Temperature Range
Soldering Conditions
−0.3 V to +0.3 V
−40°C to +125°C
−65°C to +150°C
JEDEC J-STD-020
CP-28-5
32.6
1.4
°C/W
1 θJA is measured using natural convection on a JEDEC 4-layer board with the
exposed pad soldered to the PCB and with thermal vias.
Electrostatic Discharge (ESD)
Human Body Model
Charged Device Model
ESD CAUTION
2000 V
500 V
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A | Page 7 of 23
ADP5138
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
21 PVIN4
PVIN1 1
SW1 2
20 SW4
19 PGND4
PGND1 3
PGND2 4
SW2 5
ADP5138
18 PGND3
17 SW3
TOP VIEW
(Not to Scale)
PVIN2 6
FB2 7
16 PVIN3
15 FB3
NOTES
1. EXPOSED PAD. SOLDER THE EXPOSED
PAD TO AN EXTERNAL GROUND PLANE.
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
PVIN1
Power Input for Channel 1. Connect PVIN1 to the input power source, and connect a bypass capacitor between
this pin and PGND1.
2
3
4
5
6
SW1
Switch Node for Channel 1.
Power Ground for Channel 1.
Power Ground for Channel 2.
Switch Node for Channel 2.
Power Input for Channel 2. Connect PVIN2 to the input power source, and connect a bypass capacitor between
this pin and PGND2.
PGND1
PGND2
SW2
PVIN2
7
8
FB2
EN2
Feedback Voltage Sense Input for Channel 2. Connect this pin to a resistor divider from VOUT2 for the adjustable
version. For the fixed output version, connect this pin to VOUT2 directly.
Precision Enable Pin for Channel 2. Use an external resistor divider to set the turn-on threshold. To enable
Channel 2 automatically, connect the EN2 pin to PVIN2.
9
POR
Power-On Reset Output (Open Drain).
10
PVIN5
Power Input for Channel 5. Connect PVIN5 to the input power source, and connect a bypass capacitor between
this pin and ground.
11
FB5
Feedback Voltage Sense Input for Channel 5. Connect this pin to a resistor divider from VOUT5 for the adjustable
version. For the fixed output version, connect this pin to VOUT5 directly.
12
13
VOUT5
EN5
Output of Channel 5. Connect a bypass capacitor between this pin and ground.
Precision Enable Pin for Channel 5. Use an external resistor divider to set the turn-on threshold. To enable
Channel 5 automatically, connect the EN5 pin to PVIN5.
14
15
16
EN3
Precision Enable Pin for Channel 3. Use an external resistor divider to set the turn-on threshold. To enable
Channel 3 automatically, connect the EN3 pin to PVIN3.
Feedback Voltage Sense Input for Channel 3. Connect this pin to a resistor divider from VOUT3 for the adjustable
version. For the fixed output version, connect this pin to VOUT3 directly.
Power Input for Channel 3. Connect PVIN3 to the input power source, and connect a bypass capacitor between
this pin and PGND3.
FB3
PVIN3
17
18
19
20
21
SW3
Switch Node for Channel 3.
Power Ground for Channel 3.
Power Ground for Channel 4.
Switch Node for Channel 4.
Power Input for Channel 4. Connect PVIN4 to the input power source, and connect a bypass capacitor between
this pin and PGND4.
PGND3
PGND4
SW4
PVIN4
22
23
FB4
EN4
Feedback Voltage Sense Input for Channel 4. Connect this pin to a resistor divider from VOUT4 for the adjustable
version. For the fixed output version, connect this pin to VOUT4 directly.
Precision Enable Pin for Channel 4. Use an external resistor divider to set the turn-on threshold. To enable
Channel 4 automatically, connect the EN4 pin to PVIN4.
Rev. A | Page 8 of 23
Data Sheet
ADP5138
Pin No.
24
Mnemonic
Description
GND
Analog Ground. Connect this pin to the ground plane.
25
SYNC
Synchronization Input. Connect this pin to an external clock between 2.8 MHz and 3.5 MHz to synchronize the
switching frequency to the external clock. If synchronization function is not used, connect this pin to GND.
26
27
AVIN
EN1
Bias Voltage Input Pin. Connect AVIN to PVINx, and connect a bypass capacitor between AVIN and GND.
Precision Enable Pin for Channel 1. Use an external resistor divider to set the turn-on threshold. To enable
Channel 1 automatically, connect the EN1 pin to PVIN1.
28
FB1
EP
Feedback Voltage Sense Input for Channel 1. Connect this pin to a resistor divider from VOUT1 for the adjustable
version. For the fixed output version, connect this pin to VOUT1 directly.
Exposed Pad. Solder the exposed pad to an external ground plane.
Rev. A | Page 9 of 23
ADP5138
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VAVIN = VPVIN1 = VPVIN2 = VPVIN3 = VPVIN4 = VPVIN5 = 5.0 V, fSW = 3.2 MHz, unless otherwise noted. VOUTx is the output voltage on
a single channel.
100
90
80
70
60
50
40
30
20
10
0
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
V
V
V
= 3V
= 5V
= 5.5V
PVINx
PVINx
PVINx
V
V
V
V
= 3.3V
= 1.0V
= 1.25V
= 1.35V
OUT1
OUT2
OUT3
OUT4
–40
–20
0
20
40
60
80
100
120
0.3
0
0.1
0.2
0.4
0.5
0.6
0.7
0.8
0.9
1.0
TEMPERATURE (°C)
OUTPUT CURRENT (A)
Figure 4. Efficiency vs. Output Current at VPVINx = 5 V, fSW = 3.2 MHz
Figure 7. Quiescent Current vs. Temperature
3500
3.00
2.95
2.90
2.85
2.80
2.75
2.70
RISING
FALLING
V
V
V
= 3V
= 5V
= 5.5V
PVINx
PVINx
PVINx
3000
2500
2000
1500
1000
500
0
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 8. AVIN UVLO Threshold vs. Temperature
Figure 5. Shutdown Current vs. Temperature
5.88
5.84
5.80
5.76
5.72
5.68
5.64
4.36
4.32
4.28
4.24
4.20
4.16
4.12
RISING
FALLING
RISING
FALLING
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. AVIN OVLO Threshold vs. Temperature
Figure 6. AVIN UVM Threshold vs. Temperature
Rev. A | Page 10 of 23
Data Sheet
ADP5138
1.24
1.22
1.20
1.18
1.16
1.14
1.12
1.10
1.08
5.80
5.75
5.70
5.65
5.60
5.55
5.50
EN1 RISING
EN2 RISING
EN3 RISING
EN4 RISING
EN5 RISING
EN1 FALLING
EN2 FALLING
EN3 FALLING
EN4 FALLING
EN5 FALLING
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 10. Enable Threshold vs. Temperature
Figure 13. POR Rising Deglitch Time vs. Temperature
110.4
93.6
93.4
93.2
93.0
92.8
92.6
92.4
110.2
110.0
109.8
109.6
109.4
109.2
CH1: FIXED 3.3V
CH1: FIXED 3.3V
CH2: FIXED 1.0V
CH3: FIXED 1.25V
CH4: FIXED 1.35V
CH5: FIXED 1.8V
CH2: FIXED 1.0V
CH3: FIXED 1.25V
CH4: FIXED 1.35V
CH5: FIXED 1.8V
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Output Overvoltage Rising Threshold vs. Temperature
Figure 14. Output Undervoltage Falling Threshold vs. Temperature
804
803
802
801
800
799
803
802
801
800
FB5
799
798
798
797
796
FB1
FB2
FB3
FB4
797
796
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15. Feedback Voltage of LDO vs. Temperature
Figure 12. Feedback Voltage of Buck Regulators vs. Temperature
Rev. A | Page 11 of 23
ADP5138
Data Sheet
3.22
3.21
3.20
3.19
3.18
3.17
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
V
= 3.3V
OUT1
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. Channel 1 Fixed Output Voltage vs. Temperature
Figure 19. Switching Frequency vs. Temperature
1.40
1.35
1.30
1.25
1.20
1.90
1.85
1.80
1.75
1.70
V
= 1.8V
OUT5
V
V
V
= 1.0V
OUT2
OUT3
OUT4
1.15
1.10
1.05
1.00
0.95
0.90
= 1.25V
= 1.35V
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. Channel 2, Channel 3, and Channel 4
Fixed Output Voltage vs. Temperature
Figure 20. Channel 5 Fixed Output Voltage vs. Temperature
180
170
160
150
140
130
120
110
100
170
160
150
140
130
120
110
100
90
CH1
CH1
CH2
CH3
CH4
CH2
CH3
CH4
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 18. High-Side Metal-Oxide Semiconductor Field Effect Transistor
(MOSFET) On Resistor vs. Temperature
Figure 21. Low-Side MOSFET On Resistor vs. Temperature
Rev. A | Page 12 of 23
Data Sheet
ADP5138
600
595
580
570
560
550
508
506
504
502
500
498
496
494
492
490
CH1
CH2
CH3
CH4
CH5
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 22. Buck Regulators Soft Start Time vs. Temperature
Figure 25. LDO Soft Start Time vs. Temperature
1.70
430
420
410
400
390
380
370
CH1
CH2
CH3
CH4
1.65
1.60
1.55
1.50
1.45
1.40
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 23. Current-Limit Threshold of Buck Regulators vs. Temperature
Figure 26. Current Limit of LDO vs. Temperature
10
–20
I
= 250mA
OUT5
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
I
= 10mA
OUT5
1
0.1
0.01
0.001
0.0001
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 24. LDO Output Noise Density vs. Frequency at VPVIN5 = 5 V,
OUT5 = 250 mA, VOUT5 = 1.8 V, Adjustable Output Option
Figure 27. LDO PSRR vs. Frequency at VPVIN5 = 5 V, VOUT5 = 1.8 V,
Adjustable Output Option
I
Rev. A | Page 13 of 23
ADP5138
Data Sheet
30
25
20
15
10
5
T
SW1
1
2
SW2
SW3
3
4
SW4
0
10
CH1 5.00V
CH3 5.00V
CH2 5.00V
CH4 5.00V
200ns
50.60%
CH1
1.80V
100
1k
10k
100k
1M
T
FREQUENCY (Hz)
Figure 28. LDO Output Noise RMS Value vs. Frequency at VPVIN5 = 5 V,
Figure 31. Phase Shift
I
OUT5 = 250 mA, VOUT5 = 1.8 V, Adjustable Output Option
T
T
V
ENx
OUT3
1
V
OUT4
4
2
V
V
OUT1
2
3
OUT2
V
OUT5
3
1
V
OUT3
POR
4
B
B
B
CH1 5.00V
CH2 2.00V
CH4 1.00V
1.00ms
30.00%
CH1
2.70V
B
B
B
B
W
B
W
W
CH1 5.00V
CH3 1.00V
CH2 1.00V
CH4 1.00V
1.00ms
87.20%
CH1
2.70V
W
W
W
CH3 500mV
T
W
T
W
Figure 29. Startup with Full Load (ENx, VOUT1, VOUT2, and VOUT3
)
Figure 32. Startup with Full Load (VOUT3, VOUT4, VOUT5, and POR)
T
T
ENx
V
OUT3
V
1
OUT1
4
2
V
V
OUT4
V
OUT2
OUT3
2
3
OUT5
V
3
1
POR
4
B
B
B
B
B
B
B
B
CH1 5.00V
CH3 1.00V
CH2 2.00V
CH4 1.00V
2.00ms
30.00%
CH1
2.70V
CH1 5.00V
CH3 1.00V
CH2 1.00V
CH4 1.00V
2.00ms
30.00%
CH1
2.70V
W
W
W
W
W
W
W
W
T
T
Figure 30. Shutdown at No Load (ENx, VOUT1, VOUT2, and VOUT3
)
Figure 33. Shutdown at No Load (VOUT3, VOUT4, VOUT5, and POR)
Rev. A | Page 14 of 23
Data Sheet
ADP5138
T
T
V
OUT1
1
V
(AC)
OUT5
I
L1
1
SW1
4
2
I
OUT5
4
B
B
CH1 2.00V
CH2 2.00V
CH4 1.00A Ω
400ns
49.60%
CH2
2.72V
CH1 20.0mV
200µs
20.00%
CH4 60.0mA
W
W
B
B
T
CH4 100mA Ω
T
W
W
Figure 34. Overcurrent Protection (IL1 is Channel 1 Inductor Current)
Figure 37. Load Transient Response of Channel 5 (1.8 V), 0 A to 0.2 A
T
T
V
(AC)
V
(AC)
OUT1
OUT2
1
1
I
I
OUT1
OUT2
4
4
B
B
CH1 50.0mV
200µs
20.20%
CH4
650mA
CH1 50.0mV
200µs
20.00%
CH4 640mA
W
W
B
B
CH4 500mA Ω
T
CH4 500mA Ω
T
W
W
Figure 35. Load Transient Response of Channel 1 (3.3 V), 0.1 A to 0.9 A
Figure 38. Load Transient Response of Channel 2 (1.0 V), 0.1 A to 0.9 A
T
T
V
(AC)
V
(AC)
OUT3
OUT4
1
1
I
I
OUT3
OUT4
4
4
B
B
CH1 50.0mV
200µs
20.00%
CH4
640mA
CH1 50.0mV
200µs
20.00%
CH4 640mA
W
W
B
B
CH4 500mA Ω
T
CH4 500mA Ω
T
W
W
Figure 36. Load Transient Response of Channel 3 (1.25 V), 0.1 A to 0.9 A
Figure 39. Load Transient Response of Channel 4 (1.35 V), 0.1 A to 0.9 A
Rev. A | Page 15 of 23
ADP5138
Data Sheet
T
T
PVIN2
PVIN1
V
(AC)
OUT2
1
3
1
3
V
(AC)
OUT1
B
B
CH1 20.0mV
CH3 1.00V
2.00ms
20.00%
CH3
5.20V
CH1 10.0mV
CH3 1.00V
2.00ms
20.00%
CH3
5.20V
W
W
B
B
T
T
W
W
Figure 40. Line Transient Response of Channel 1 (3.3 V), PVIN1 from 4.5 V
to 5.5 V, 1 A Load Current
Figure 43. Line Transient Response of Channel 2 (1.0 V), PVIN2 from 4.5 V
to 5.5 V, 1 A Load Current
T
T
PVIN3
PVIN4
1
1
V
(AC)
V
(AC)
OUT3
OUT4
3
3
B
B
CH1 20.0mV
CH3 1.00V
2.00ms
T 20.00%
CH3
5.20V
CH1 10.0mV
CH3 1.00V
2.00ms
20.00%
CH3
5.22V
W
W
B
B
T
W
W
Figure 41. Line Transient Response of Channel 3 (1.25 V), PVIN3 from 4.5 V
to 5.5 V, 1 A Load Current
Figure 44. Line Transient Response of Channel 4 (1.35 V), PVIN4 from 4.5 V
to 5.5 V, 1 A Load Current
T
PVIN5
1
V
(AC)
OUT5
3
B
CH1 10.0mV
CH3 1.00V
2.00ms
20.00%
CH3
5.20V
W
B
T
W
Figure 42. Line Transient Response of Channel 5 (1.8 V), PVIN5 from 4.5 V
to 5.5 V, 250 mA Load Current
Rev. A | Page 16 of 23
Data Sheet
ADP5138
THEORY OF OPERATION
The ADP5138 is a power management IC that integrates four
buck regulators and one low noise LDO in a 28-lead LFCSP
package. The device can operate with a PVINx input voltage
from 3 V to 5.5 V and can regulate the output voltage down to
0.8 V or set by factory. It provides input UVLO, OVLO, and
UVM features. The ADP5138 also monitors the output voltage
and provides the POR output.
SYNCHRONIZATION
To synchronize the ADP5138, connect an external clock to the
SYNC pin. The external clock frequency can be in the 2.8 MHz
to 3.5 MHz range. During synchronization, Channel 1 runs in
phase with the external clock.
If the synchronization function is not used, connect the SYNC pin
to ground.
CONTROL SCHEME
INPUT OVERVOLTAGE LOCKOUT (OVLO)
The ADP5138 uses a fixed frequency, peak current mode,
PWM control architecture. At the start of each oscillator cycle,
the high-side field effect transistor (FET) turns on, placing a
positive voltage across the inductor. The inductor current
increases until the current sense signal crosses the peak
inductor current threshold that turns off the high-side FET and
turns on the low-side FET, which, in turn, places a negative
voltage across the inductor, causing the inductor current to reduce.
The low-side FET stays on for the remainder of the cycle.
The ADP5138 integrates an input overvoltage lockout circuit on
the input supply. When the input voltage, VAVIN, exceeds 5.8 V
(typical), an OVLO event is detected, all the regulators are
turned off, and the POR is pulled down to ground. When the
input voltage falls back to 5.72 V (typical) or less, the OVLO
releases and a soft start reinitializes.
INPUT UNDERVOLTAGE MONITOR (UVM)
The ADP5138 integrates an input undervoltage monitoring
circuit on the input supply. When the input voltage, VAVIN, drops
below 4.2 V (typical), the POR pin pulls down to ground while
the device still works until the input voltage drops down to the
input voltage UVLO threshold. When the input voltage exceeds
4.28 V (typical), the POR pin pulls high after a POR rising delay
time, tPOR_DELAY_R, if all other conditions are met.
PRECISION ENABLE AND SHUTDOWN
The ADP5138 has five independent enable pins (ENx) for each
channel. The ENx pins are precision analog inputs that enable
the regulator when the voltage on ENx exceeds 1.2 V (typical).
When the ENx voltage falls below 1.1 V (typical), the regulator
turns off. An internal pull-down resistor (1 MΩ) prevents the
regulator from being accidentally enabled if ENx is left floating.
INPUT UNDERVOLTAGE LOCKOUT (UVLO)
To force the ADP5138 to automatically start when the input
power is applied, connect ENx to PVINx.
The ADP5138 integrates an input undervoltage lockout circuit
on the input supply. When the input voltage, VAVIN, drops below
2.8 V (typical), an input UVLO event is detected, all the regulators
turn off, and the POR pin pulls down to ground. When the
input voltage recovers from the UVLO event and the input
voltage exceeds 2.9 V (typical), a soft start reinitializes.
OSCILLATOR AND PHASE SHIFT
The buck regulators in the ADP5138 run at a 3.2 MHz fixed
switching frequency. For Channel 2 to Channel 4, the phase
shift with respect to Channel 1 is set to 90°, which reduces the
input ripple current and the input capacitance, thereby helping
to lower system EMI.
OUTPUT VOLTAGE POWER-GOOD
Each of the five regulators integrates an output voltage power-
good monitoring circuit.
SW1
When the output voltage drops below the undervoltage falling
threshold (93% of the nominal output voltage), an output under-
voltage event is detected, and the power-good signal becomes
low. When the output voltage rises above the undervoltage
rising threshold (95% of the nominal output voltage), the
power-good signal becomes high.
SW2
SW3
When the output voltage exceeds the overvoltage rising
threshold (110% of the nominal output voltage), an output
overvoltage event is detected. During the output overvoltage,
the corresponding regulator stops switching, and the power-
good signal becomes low. When the output voltage drops below
the overvoltage falling threshold (108% of the nominal output
voltage), the corresponding regulator recovers to normal
operation, and the power-good signal becomes high.
SW4
90°
90°
90°
90°
Figure 45. Even Phase Shift Between Channel 1 and Channel 4
Rev. A | Page 17 of 23
ADP5138
Data Sheet
V
V
,
POWER-ON RESET (POR)
PVINx
AVIN
The ADP5138 integrates the POR circuit to monitor the input
voltage and output voltage of the regulators. The POR pin is an
active high, open-drain output that requires a resistor to pull
the pin up to a voltage.
ENx
V
OUT1
OUT2
OUT3
OUT4
V
V
V
V
The ENx pin voltage determines which output voltage is
monitored in the POR circuit. When the ENx pin voltage
exceeds 1.2 V (typical), the POR circuit monitors the
corresponding output voltage. When the ENx pin voltage is
lower than 1.1 V (typical), the POR circuit does not monitor
the corresponding output voltage.
95%
OUT5
POR
tSS1
The POR pin does not pull high until all of the following
conditions are met followed by a 5.7 ms (typical) delay:
tSS2
tSS3
tSS4
•
The input voltage is greater than the undervoltage lockout
threshold and undervoltage monitor threshold.
The input voltage is less than the input overvoltage
threshold.
tSS_D
tSS5
2 × tSS_D
3 × tSS_D
4 × tSS_D
•
tPOR_DELAY_R
•
•
No thermal shutdown.
All the power-good signals are high for these monitored
output voltages.
Figure 46. Power-Up Sequence with All Channels Enabled at Same Time
V
,
PVINx
V
AVIN
The POR pin is pulled down when any of these conditions are
not met with a 10 µs deglitch time.
EN2, EN3
EN1, EN4, EN5
If all the channels are disabled, the POR pin pulls down to
ground.
V
V
V
V
V
OUT1
OUT2
OUT3
OUT4
95%
The POR output is fully controlled when the voltage on AVIN is
higher than VAVIN_POR
.
95%
OUT5
SOFT START AND POWER-UP SEQUENCE
POR
tSS2
The ADP5138 has integrated soft start circuitry for each channel
to limit the output voltage rising time and to reduce the inrush
current during startup. The soft start time is fixed at 500 µs
(typical) for the buck regulators and 570 µs (typical) for the
LDO regulator.
tSS5
tSS4
tSS1
tSS3
tSS_D
3 × tSS_D
2 × tSS_D
4 × tSS_D
tPOR_DELAY_R
tPOR_DELAY_R
When the ADP5138 exits the input UVLO, input OVLO, or
thermal shutdown event, there is a fixed delay time on each
enable signal. This delay time prevents all the regulators from
powering up at the same time and reduces the input inrush
current. Table 7 shows the delay time for each channel.
Figure 47. Power-Up Sequence with Channels Enabled at Different Times
CURRENT-LIMIT AND SHORT-CIRCUIT
PROTECTION
The ADP5138 integrates a cycle by cycle, peak current-limit
protection circuit to prevent current runaway for each buck
regulator. The high-side FET peak current is limited to 1.6 A
(typical). When the peak inductor current reaches the current-
limit threshold, the high-side FET turns off, the low-side FET
turns on, and the output reference voltage decreases.
Table 7. Enable Delay Time for Each Channel
Channel
Delay Time
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
15 µs
tSS_D
2 × tSS_D
3 × tSS_D
4 × tSS_D
The low-side FET in the buck regulator can also sink current
from the load. If the low-side sink current limit is exceeded, both
the low-side and high-side FETs are turned off until the next
cycle starts.
Figure 46 shows the power-up sequence when the ENx pins are
pulled up at the same time. Channel 1 powers up first, followed
by Channel 2, Channel 3, Channel 4, and Channel 5.
Figure 47 shows the power-up sequence when the channels are
enabled at different times.
Rev. A | Page 18 of 23
Data Sheet
ADP5138
The LDO is designed to current limit when the output load
reaches the current-limit threshold. When the output load
exceeds the current-limit threshold, the output voltage is
reduced to maintain a constant current limit.
switch is 64 Ω for the buck regulators and 83 Ω for the LDO
regulator.
THERMAL SHUTDOWN
In the event that the ADP5138 junction temperature exceeds
150°C, the thermal shutdown circuit turns off the device. A 15°C
hysteresis is included so that the ADP5138 does not recover from
thermal shutdown until the on-chip temperature drops below
135°C. Upon recovery, a soft start and the power-up sequence
are initiated prior to normal operation.
ACTIVE OUTPUT DISCHARGE
Each of the five regulators in the ADP5138 integrates a discharge
switch from the switching node to ground. This switch is turned
on when its associated ENx pin is low, which helps to discharge
the output capacitor quickly. The typical value of the discharge
Rev. A | Page 19 of 23
ADP5138
Data Sheet
APPLICATIONS INFORMATION
Use the following equation to calculate the inductor value:
INPUT CAPACITOR SELECTION
(VIN − VOUT ) × D
The input capacitor reduces the input voltage ripple caused by
the switch current on PVINx. Place the input capacitor as close
as possible to the PVINx pin. A ceramic capacitor in the 10 μF
to 47 μF range is recommended. The loop composed of the input
capacitor, the high-side MOSFET, and the low-side MOSFET
must be kept as small as possible.
L =
∆IL × fSW
where:
V
IN is the input voltage.
VOUT is the output voltage.
D is the duty cycle (D = VOUT/VIN).
ΔIL is the inductor current ripple.
The voltage rating of the input capacitor must be greater than
the maximum input voltage. Ensure that the rms current rating
of the input capacitor is larger than the value calculated from
the following equation:
fSW is the switching frequency.
Use the following equation to calculate the peak inductor current:
∆IL
2
IPEAK = IOUT
+
ICIN _ RMS = IOUT
× D ×(1− D)
The saturation current of the inductor must be larger than the
peak inductor current. For ferrite core inductors with a quick
saturation characteristic, the saturation current rating of the
inductor must be higher than the current-limit threshold of the
switch to prevent the inductor from reaching saturation.
where:
I
OUT is the output current.
D is the duty cycle (D = VOUT/VIN).
OUTPUT VOLTAGE SETTING
The output voltage (VOUT) of the ADP5138 can be factory set or
programmed by an external resistor divider.
Use the following equation to calculate the rms current of the
inductor:
2
If the output voltage is factory set, connect the FBx pin to the
output voltage directly.
∆IL
12
2
IRMS
=
IOUT
+
If the output voltage is programmable, use the following
equation to set the output voltage:
Shielded ferrite core materials are recommended for low core
loss and low EMI.
RTOP
RBOT
OUTPUT CAPACITOR SELECTION
VOUT = 0.8× 1 +
The output capacitor selection affects both the output voltage
ripple and the loop dynamics of the regulator. The ADP5138
operates with small ceramic capacitors that have low equivalent
series resistance (ESR) and low equivalent series inductance
(ESL) and can, therefore, easily meet the output voltage ripple
specifications.
where:
R
R
TOP is the top resistor of the resistor divider.
BOT is the bottom resistor of the resistor divider.
Table 8. Resistor Divider Values for Various Output Voltages
VOUT (V)
RTOP 1% (kΩ)
RBOT 1% (kΩ)
When the regulator operates in continuous conduction mode, the
overall output voltage ripple is the sum of the voltage spike caused
by the output capacitor ESR plus the voltage ripple caused by the
charging and discharging of the output capacitor.
1.0
1.2
1.5
1.8
2.5
3.3
4.99
10
10
18.7
24.3
35.7
20
20
11.5
15
11.5
11.5
1
∆VRIPPLE = ∆IL ×
+ ESRC
OUT
8 × fSW ×COUT
INDUCTOR SELECTION
where:
ΔVRIPPLE is the output voltage ripple.
OUT is the output capacitance.
The inductor value is determined by the operating frequency,
input voltage, output voltage, and inductor ripple current. Using
a small inductor value leads to a faster transient response but
degrades efficiency due to a larger inductor ripple current. Using
a large inductor value leads to a smaller ripple current and
better efficiency but results in a slower transient response.
C
Capacitors with lower ESR are preferable to guarantee low
output voltage ripple, as shown in the following equation:
∆VRIPPLE
ESRC
≤
OUT
∆IL
As a guideline, an inductor with its value in the range from
0.68 µH to 2.2 µH is recommended for the best balance between
transient and efficiency performance. The inductor ripple
current, ΔIL, is typically set to one-third of the maximum load
current.
Ceramic capacitors are manufactured with a variety of dielectrics,
each with different behavior over temperature and applied voltage.
X5R or X7R dielectrics are recommended for best performance
due to the low ESR and small temperature coefficients.
Rev. A | Page 20 of 23
Data Sheet
ADP5138
APPLICATION CIRCUIT
V
ADP5138
OUT1
R
POR
100kΩ
POR
= 3.3V
AVIN
POR
C
L1
1µH
AVIN
1µF/16V
V
V
OUT1
EN1
PVIN1
V
= 5V ± 10%
SW1
FB1
IN
C
OUT1
C
10µF/6.3V
IN1
10µF/6.3V
PGND1
L2
1µH
= 1.0V
OUT2
SW2
EN2
R
TOP2
1.62kΩ
C
PVIN2
OUT2
FB2
C
10µF/6.3V
IN2
R
BOT2
10µF/6.3V
PGND2
6.49kΩ
L3
1µH
V
= 1.25V
OUT3
SW3
R
TOP3
5.36kΩ
EN3
PVIN3
C
OUT3
FB3
C
10µF/6.3V
IN3
R
BOT3
10µF/6.3V
PGND3
9.53kΩ
L4
1µH
V
= 1.35V
OUT4
SW4
FB4
EN4
PVIN4
C
OUT4
C
10µF/6.3V
IN4
10µF/6.3V
PGND4
V
= 1.8V
OUT5
VOUT5
FB5
EN5
PVIN5
R
TOP5
C
18.7kΩ
IN5
C
OUT5
1µF/16V
1µF/16V
R
15kΩ
BOT5
SYNC GND
Figure 48. Application Circuit
Rev. A | Page 21 of 23
ADP5138
Data Sheet
FACTORY-PROGRAMMABLE OPTIONS
The output of each buck regulator and the LDO can be preset to
one of the options listed in Table 9. There are 15 fixed options
and one adjustable option. To order a device with options other
than the default options listed in the Ordering Guide, contact a
local Analog Devices, Inc., sales or distribution representative.
Table 9. Output Voltage Fuse-Selectable Trim Options
Parameter
Output Voltage Trim Options (V)
Buck Regulator 1
Buck Regulator 2
Buck Regulator 3
Buck Regulator 4
LDO
Adjustable, 0.9, 0.95, 1.0, 1.05, 1.1, 1.15, 1.2, 1.25, 1.35, 1.5, 1.8, 2.5, 2.65, 3.0, 3.3
Adjustable, 0.9, 0.95, 1.0, 1.05, 1.1, 1.15, 1.2, 1.25, 1.35, 1.5, 1.8, 2.5, 2.65, 3.0, 3.3
Adjustable, 0.9, 0.95, 1.0, 1.05, 1.1, 1.15, 1.2, 1.25, 1.35, 1.5, 1.8, 2.5, 2.65, 3.0, 3.3
Adjustable, 0.9, 0.95, 1.0, 1.05, 1.1, 1.15, 1.2, 1.25, 1.35, 1.5, 1.8, 2.5, 2.65, 3.0, 3.3
Adjustable, 1.0, 1.05, 1.1, 1.15, 1.2, 1.25, 1.3, 1.5, 1.8, 2.5, 2.65, 2.8, 2.85, 3.0, 3.3
Rev. A | Page 22 of 23
Data Sheet
ADP5138
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
0.25
0.20
0.15
4.10
4.00 SQ
3.90
PIN 1
INDICATOR
PIN 1
22
28
IONS
INDICATOR AR EA OP T
(SEE DETAIL A)
1
21
0.40
BSC
2.70
2.60 SQ
2.50
EXPOSED
PAD
15
7
14
8
0.45
0.40
0.35
0.20 MIN
TOP VIEW
SIDE VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGE.
Figure 49. 28-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-28-5)
Dimensions shown in millimeters
ORDERING GUIDE
Output Voltage (V)4
Buck 1 Buck 2 Buck 3 Buck 4 LDO Temperature Range Package Description Package Option
Model1, 2, 3
ADP5138WACPZ-1-R7 3.3
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
1.35
ADJ
1.35
ADJ
ADJ
ADJ
−40°C to +125°C
−40°C to +125°C
28-Lead LFCSP
28-Lead LFCSP
Evaluation Board
CP-28-5
CP-28-5
ADP5138ACPZ-2-R7
ADP5138W-1-EVALZ
ADJ
3.3
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
3 To order a device with options other than the two default options listed in the ordering guide, contact a local Analog Devices sales or distribution representative.
4 ADJ means adjustable.
AUTOMOTIVE PRODUCTS
The ADP5138W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for this model.
©2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16669-0-8/18(A)
Rev. A | Page 23 of 23
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