ADP5360 [ADI]
Advanced Battery Management PMIC with Ultra Low Power Buck and Buck Boost;
| 型号： | ADP5360 |
| 厂家： | 
ADI |
| 描述： | Advanced Battery Management PMIC with Ultra Low Power Buck and Buck Boost 电池 集成电源管理电路 |
| 文件： | 总60页 (文件大小：1871K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Advanced Battery Management PMIC with
Ultra Low Power Buck and Buck Boost
ADP5360
Data Sheet
FEATURES
GENERAL DESCRIPTION
Linear battery charger
High accuracy and programmable charge terminal voltage
and charge current up to 320 mA
Compliant with JEITA charge temperature specification
Li-Ion and Li-Poly battery monitor and protection
Voltage-based fuel gauge with adaptive filter limitation
Independent battery protection of overcharge and
overdischarge
The ADP5360 combines one high performance linear charger
for a single lithium-ion (Li-Ion)/lithium-polymer (Li-Poly)
battery with a programmable, ultralow quiescent current fuel
gauge and battery protection circuit, one ultralow quiescent
buck, one buck boost switching regulator, and a supervisory
circuit that can monitor output voltage.
The ADP5360 charger operates at up to 6.8 V to prevent USB
bus spiking during disconnect or connect scenarios.
Temperature sensor with external NTC
Ultralow quiescent current buck converter
Quick output discharge option
Ultralow quiescent current buck boost converter
Quick output discharge option
The ADP5360 features an internal isolation field effect transistor
(FET) between the linear charger output and the battery node.
The full battery protection features are activated when the device is
in the battery overcharge and overdischarge fault conditions.
MR
Supervisory with manual reset ( ) and watchdog timer
The ADP5360 fuel gauge uses a voltage-based algorithm with
an adaptive filter limitation solution. The fuel gauge reports
real-time battery state of charge (SOC) for the rechargeable
Li-Ion battery with ultralow quiescent current.
Shipment mode extends battery life
Full I2C programmability with dedicated interrupt pin
APPLICATIONS
Rechargeable Li-Ion/Li-Poly battery-powered devices
Portable consumer devices
Portable medical devices
Wearable devices
The ADP5360 buck regulator operates at 1.0 MHz switching
frequency in forced pulse-width modulation (FPWM) mode.
In hysteresis mode, the regulator achieves excellent efficiency at
a low output power.
The ADP5360 buck boost regulator only operates in hysteresis
mode and outputs a voltage less than or greater than the battery
voltage.
The ADP5360 supervisory circuits monitor the regulator output
voltage and provide a power-on reset signal to the system. A
watchdog timer and an external pushbutton can reset the
microprocessor.
The I2C-compatible interface enables the programmability of all
battery charging parameters, the protection threshold, the buck
output voltage, and the status bit readback.
The ADP5360 operates over the −40°C to +85°C junction
temperature range and is available in a 32-ball, 2.56 mm ×
2.56 mm wafer level chip scale package (WLCSP).
Rev. 0
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rightsof third parties that may result fromits use. Specifications subject to change without notice. No
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Tel: 781.329.4700
Technical Support
©2019 Analog Devices, Inc. All rights reserved.
www.analog.com
ADP5360
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Battery Fuel Gauge ..................................................................... 25
Battery Protection ...................................................................... 28
Buck Regulator Operation ........................................................ 28
Buck Boost Regulator Operation ............................................. 30
Supervisory ................................................................................. 31
Shipment Mode .......................................................................... 32
Fault Recovery ............................................................................ 32
Thermal Management ............................................................... 32
I2C Interface .................................................................................... 33
I2C Addresses .............................................................................. 33
SDA and SCL Pins ...................................................................... 33
Interrupts..................................................................................... 33
Control Register Map..................................................................... 35
Fuel Gauge Register Bit Descriptions ...................................... 45
Switching Regulator Register Bit Descriptions ...................... 48
Supervisory Register Bit Descriptions..................................... 50
Status and Fault Register Bit Descriptions.............................. 50
Applications Information.............................................................. 54
Typical Application Circuits ..................................................... 54
External Components................................................................ 55
PCB Layout Guidelines.................................................................. 57
Factory-Programmable Options .............................................. 58
Outline Dimensions....................................................................... 60
Ordering Guide .......................................................................... 60
Applications....................................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
Battery Charger Specifications ................................................... 4
Battery Monitor Specifications ................................................... 6
Buck Regulator Specifications .................................................... 6
Buck Boost Regulator Specifications ......................................... 7
I2C-Compatible Interface Timing Specifications ..................... 8
Recommended Input and Output Capacitance and
Inductance..................................................................................... 8
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
Maximum Power Dissipation ..................................................... 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 12
Typical Waveforms ..................................................................... 16
Theory of Operation ...................................................................... 20
Battery Charger........................................................................... 20
Battery Isolation FET ................................................................. 22
Battery Detection........................................................................ 22
Battery Temperature................................................................... 23
REVISION HISTORY
11/2019—Revision 0: Initial Version
Rev. 0 | Page 2 of 60
Data Sheet
ADP5360
FUNCTIONAL BLOCK DIAGRAM
VDD
V
6.8V
BUS_OV
VIN1
VBUS
3.9V
V
BUS_OK
I
LIM_PWM
BUCK
CONTROL
LOGIC
SW1
I
LIM_HSY
PGND1
I
LIM
VSYS
EN1
CHARGE CONTROL
AND
TRICKLE
SOURCE
STP
BATTERY PROTECTION
FB1
I
BAT
VID SET
VID1
0.6V REF
AND
SOFT START
I
END
ISOB
DETECTION
SINK
STP
EN2
VIN2
STP
ENCHG
OSCILLATOR
SW2A
ICS
UNDER
PGND2
SW2B
BUCK BOOST
CONTROL
LOGIC
VOLTAGE
ILIM
OVER
VOLTAGE
BSNS
VOUT2
FUEL GAUGE
ADC
I
BAT
ALGORITHM
THR
SCL
VID SET
0.6V REF
AND
SOFT START
2
I C INTERFACE
SDA
INT
AND
LOGIC CONTROL
AND
DIGITAL CIRCUIT
ENSD
MR
PGOOD1
RESET
PGOOD2
AGNDx
NOTES
BAT
1. I
IS THE BATTERY SENSE CURRENT.
Figure 1.
Rev. 0 | Page 3 of 60
ADP5360
Data Sheet
SPECIFICATIONS
BATTERY CHARGER SPECIFICATIONS
TJ = −40°C to +85°C, voltage of the VBUS pin (VVBUS) = 5.0 V, voltage of the ISOB pin (VISOB) = 3.8 V, C1 = 2.2 μF, C2 = 1 μF, C3 = C4 =
10 μF (see Figure 60), and all registers are at default values, unless otherwise noted.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min Typ
Max Unit
GENERAL PARAMETERS
Undervoltage Lockout (UVLO)
VUVLO
Rising threshold, voltage of the ISOB pin,
2.1
2.15
V
V
VBUS = 0 V
Falling threshold, voltage of the ISOB pin,
VBUS = 0 V
LIM = 100 mA
1.8
1.88
95
V
V
I
ILIM
Input Current Limit
Operation Current
VBUS Consumption
100
2
mA
IQ_BUS
Charger, fuel gauge, buck, and buck boost
enabled, no charge current
1.5
mA
Battery Consumption
IQ_PRO
Enable battery protection only, VVBUS = 0 V
Fuel gauge, active mode, VVBUS = 0 V
Fuel gauge, sleep mode, VVBUS = 0 V
Enable buck and buck boost, VVBUS = 0 V
All disabled, VVBUS = 0 V
0.25
3.5
0.2
0.34
150
10
1.8
5
0.85
1
450
50
310
μA
μA
μA
μA
nA
nA
nA
IQ_FG_ACT
IQ_FG_SLEEP
IQ_REG
IQ_DISALL
IQ_SHIP
Shipment mode, TJ = 25°C
Shipment mode, TJ = −40°C to +85°C
CHARGING PARAMETERS
Fast Charge Constant Current
Mode
ICHG
ICHG = 100 mA
ICHG = 10 mA to 320 mA, TJ = 0°C to 85°C
94
−15
100
106
+15
mA
%
Accuracy1
Charge Current
Trickle1
Weak
ITRK_DEAD
ICHG_WEAK
VTRK_DEAD
ΔVTRK_DEAD
VWEAK
ITRK_DEAD = 5 mA, TJ = 0°C to 85°C
VTRK_DEAD = 2.5 V
4
5
6
mA
mA
V
mV
V
ITRK_DEAD + ICHG
Trickle to Weak Charge Threshold1
Hysteresis
Weak to Fast Charge Threshold1
Hysteresis
Battery Termination Voltage
Termination Voltage Accuracy1
2.41 2.5
100
2.88 3.0
100
2.57
3.08
VWEAK = 3.0 V
ΔVWEAK
VTRM
mV
VTRM = 4.2 V on the BSNS pin, TJ = 25°C
VTRM = 4.2 V, on the BSNS pin, TJ = 0°C to 85°C
IEND = 5 mA, TJ = 0°C to 85°C
4.18 4.200
−1
2
4.22
+1
8
V
%
mA
mV
Charge Complete Current1
Recharge Voltage Differential1
BATTERY ISOLATION FET
IEND
VRCH
5
120
ISOFET
RDSON_ISO
Resistance Between ISOB and VSYS
VVBUS = 0 V, current of the ISOB pin (IISOB) =
100 mA
145
220
mΩ
LOW DROPOUT (LDO) AND HIGH VOLTAGE
BLOCKING FET
Regulated System Voltage1
High Voltage Blocking FET On Resistance
Input Operating Voltage Range
Good Threshold
Rising
VSYS_REG
RDSON_HV
VTRM = 4.2 V, VSYSTEM = VTRM + 200 mV
IVBUS = 100 mA
VVBUS
4.4
550
V
mΩ
V
820
6.8
4.1
3.5
6.4
VVBUS_OK
VVBUS_OK_RISE
VVBUS_OK_FALL
VVBUS_OV
VVBUS_OV_RISE
VVBUS_OV_FALL
3.9
3.6
4.0
7.0
V
V
Falling
Overvoltage Threshold
Rising
6.8
6.6
V
V
Falling
Rev. 0 | Page 4 of 60
Data Sheet
ADP5360
Parameter
Symbol
Test Conditions/Comments
Min Typ
Max Unit
THERMAL PROTECTION
Thermal Shutdown Temperature2
TSD
TJ RISING
TJ FALLING
110
100
°C
°C
THERMISTOR CONTROL
Thermistor Current
Negative Temperature Coefficient (NTC)
Resistor (RNTC) = 10 kΩ
INTC_10k
57.5 60
11.5 12
62
μA
RNTC = 47 kΩ
RNTC = 100 kΩ
BATTERY DETECTION
Sink Current
Source Current
Battery Threshold
Low
INTC_47k
INTC_100k
12.5
6.35
μA
μA
5.65
6
ISINK
ISOURCE
4.1
2
6
2.5
7
3
mA
mA
VBATL
VBATH
1.92
2
2.06
3.48
V
V
High
3.27 3.4
Timer
tBATOK
VNOBAT
333
2
ms
V
Threshold After Charging Completed
TIMERS
Start Charging Delay Timer
Trickle Charge Timer1
tSTART
tTRK
300
60
ms
min
CHG_TMR_PERIOD = 60 minutes and
600 minutes
Fast Charge Timer1
Charge Complete Timer
Deglitch Timer
tCHG
tEND
tDG
CHG_TMR_PERIOD = 60 minutes and
600 minutes
600
7.5
31
min
min
ms
Voltage of the BSNS pin (VBSNS) = VTRM
EN_TEND = 1 bit, register set
,
Applies to VTRM, VRCH, IEND, VWEAK, VTRK_DEAD, and
VVBUS_OK
Safety Timer
Reset Timeout Period
tSAFE
tRP
tSH
36
40
44
min
ms
ms
200
200
12.5
MR
for Shipment Mode
Watchdog Timer1
I2C (SCL AND SDA)
Maximum Voltage on Digital Inputs
Input Voltage
tWD
sec
VDIN_MAX
5.5
0.4
0.4
V
Low Level
High Level
Low Level Output Voltage
VIL
VIH
VOL
Applies to SCL, SDA
Applies to SCL, SDA
Applies to SDA, SDA current sink (ISDA_SINK) =
2 mA
V
V
V
1.2
INT, RESET, PGOOD1, AND PGOOD2
Input and Output Leakage Current
Input and Output Low Voltage
ENCHG, EN1, EN2, STP, MR, ENSD
Input Voltage Threshold
High
IIO_LEAK
VIO_LOW
Input and output voltage (VIO) = 5 V
Input and output current (IIO) = 1 mA
10
90
150
200
nA
mV
VIH
1.2
V
Low
VIL
0.4
V
Input Leakage Current
IEN_LEAKAGE
150
nA
1 These values are programmable via I2C. Values are given with default register values.
2 Specification is not production tested but is supported by characterization data at initial product release.
Rev. 0 | Page 5 of 60
ADP5360
Data Sheet
BATTERY MONITOR SPECIFICATIONS
TJ = −40°C to +85°C, VISOB = 3.8 V, C1 = 2.2 μF, C2 = 1 μF, C3 = C4 = 10 μF, and all registers are at default values, unless otherwise noted.
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
BATTERY VOLTAGE SENSING
Analog-to-Digital Converter (ADC) Reading
Voltage
Range
0
4.8
V
Resolution
Accuracy
Based on 12-bit ADC
TJ = 25°C
1.17
mV
mV
%
−12.5
−1
+12.5
+1
Fuel Gauge UVLO Threshold
Rising
Falling
VBSNS
VUVLO_FG_RISE
VUVLO_FG_FALL
2.7
2.58
2.8
V
V
2.48
−1.5
BATTERY OVERDISCHARGE MONITORING
Undervoltage Threshold
Rising
VBPUV_FALL
+1.5
700
%
%
ms
Falling Hysteresis
VBPUV_FALL_HYS HYS_UV_DISCH = 2%
2
30
Undervoltage Deglitch Timer
Overdischarge Current
Threshold
Deglitch Timer
Hiccup Off Time
tBPUV_DIS
DGT_UV_DISCH = 30 ms
IBPOC_DIS
tBPOC_DIS
tDIS_HCP
OC_DISCH = 600 mA
DGT_OC_DISCH = 5 ms
480
600
5
200
mA
ms
ms
BATTERY OVERCHARGE MONITORING
Overvoltage Threshold
Rising
VVBUS = 5 V
VBPOV_RISE
−1.5
130
+1.5
170
%
%
sec
mA
ms
ms
Falling Hysteresis
VBPOV_RISE_HYS HYS_OV_CHG = 2%
2
Overvoltage Deglitch Timer
Overcurrent Threshold
Overcurrent Deglitch Timer
Hiccup Off Time
tBPOV_CHG
IBPOC
tBPOC_CHG
tCHG_HCP
DGT_OV_CHG = 0.5 sec
OC_CHG = 150 mA
DGT_OC_CHG = 10 ms
0.5
150
10
200
BUCK REGULATOR SPECIFICATIONS
TJ = −40°C to +85°C, voltage of the VIN1 pin (VVIN1) = voltage of the VSYS pin (VVSYS) = 3.8 V, buck output voltage (VOUT1) = 1.2 V, C5 =
C6 = 10 ꢀF, L1 = 4.7 ꢀH (see Figure 60), and all registers are at default values, unless otherwise noted.
Table 3.
Parameter
Symbol
Test Conditions/Comments
Min Typ
Max
Unit
UVLO THRESHOLD
Rising
Falling
VVIN1
VUVLO1_RISE
VUVLO1_FALL
2.3
2.15 2.2
2.35
V
V
OSCILLATOR CIRCUIT
Switching Frequency in Pulse Width
Modulation (PWM) Mode
Feedback Threshold of Frequency Fold
FB1 PIN
Output Voltage Option Range
PWM Mode
Fixed Voltage Identification (VID) Code
Voltage Accuracy
fSW1
0.85 1.0
1.25
1.15
MHz
V
VOSC_FOLD_RISE
VOUT1 = 2.5 V
VOUT1
Factory trim or I2C, six bits
0.6
−2
3.75
+2
V
VFB1_PWM_FIX
%
Rev. 0 | Page 6 of 60
Data Sheet
ADP5360
Parameter
Symbol
Test Conditions/Comments
Min Typ
Max
Unit
Hysteresis Mode
Fixed VID Code Voltage Threshold Accuracy
Hysteresis of Voltage Threshold
Feedback Bias Current
VFB1_HYS_FIX
VFB1_HYS (HYS)
IFB1
−2
1
+2
%
%
nA
VOUT1 = 0.6 V
50
SW1 PIN
Power FET On Resistance
High-Side
Low-Side
Current Limit in PWM Mode
Peak Current in Hysteresis Mode
Minimum On Time1
RDS (ON) H
RDS (ON) L
ILIM_PWM
ILIM_HYS
Pin to pin measurement
Pin to pin measurement
PWM mode
280
260
1000 1150
200
60
380
380
mΩ
mΩ
mA
mA
ns
850
160
Hysteresis mode, BUCK_ILIM = 200 mA
240
tMIN_ON
SOFT START
Default Soft Start Time
OUTPUT DISCHARGE SWITCH ON RESISTANCE
tSS1
BUCK_SS[1:0] = 1 ms
1
ms
Ω
RDIS1
255
1 Guaranteed by design.
BUCK BOOST REGULATOR SPECIFICATIONS
TJ = −40°C to +85°C, voltage of the VIN2 pin (VVIN2) = VVSYS = 3.8 V, voltage of the VOUT2 pin (VVOUT2) = 5 V, C 7 = C8 = 10 μF, L2 =
4.7 μH (see Figure 60), and all registers are at default values, unless otherwise noted.
Table 4.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
UVLO THRESHOLD
Rising
Falling
VVIN2
VUVLO2_RISING
VUVLO2_FALLING
2.3
2.16
2.36
V
V
2.11
1.8
−2
OUTPUT VOLTAGE RANGE
Output Voltage Accuracy
Hysteresis of Voltage Threshold Accuracy
SW2AAND SW2B PINS
SWA2 Pin FET Resistance
High-Side
Factory trim or I2C, six bits
5.5
+2
V
%
%
VVOUT2
VVOUT2_HYS
1
RDS(ON)1_2A-H
RDS(ON)1_2A-L
354
250
470
360
mΩ
mΩ
Low-Side
SW2B Pin FET Resistance
High-Side
Low-Side
Peak Current-Limit Threshold
SOFT START TIME
Soft Start Time
RDS(ON)1_2B-H
RDS(ON)1_2B-L
ITH(ILIM1_2)
290
230
200
400
330
240
mΩ
mΩ
mA
BUCKBST_ILIM = 200 mA
BUCKBST_SS[0:1] = 1 ms
160
1
tSS2
1
ms
ms
Ω
Programmable Soft Start Range
OUTPUT DISCHARGE SWITCH ON RESISTANCE
512
RDIS2
255
Rev. 0 | Page 7 of 60
ADP5360
Data Sheet
I2C-COMPATIBLE INTERFACE TIMING SPECIFICATIONS
TA = 25°C and VISOB = 3.8 V, unless otherwise noted.
Table 5.
Parameter
Symbol
Min
Typ
Max
Unit
I2C-COMPATIBLE INTERFACE
Capacitive Load, Each Bus Line
SCL Clock Frequency
SCL High Time
SCL Low Time
CS
fSCL
400
400
pF
kHz
µs
µs
ns
µs
µs
µs
µs
µs
ns
ns
ns
tHIGH
tLOW
tSUDAT
tHDDAT
tSUSTA
tHDSTA
tBUF
tSUSTO
tR
0.6
1.3
100
0
Data Setup Time
Data Hold Time1
0.9
Setup Time for Repeated Start
Hold Time for Start and Repeated Start
Bus Free Time Between a Stop Condition and a Start Condition
Setup Time for Stop Condition
Rise Time of SCL and SDA
Fall Time of SCL and SDA
Pulse Width of Suppressed Spike
0.6
0.6
1.3
0.6
20
20
0
300
300
50
tF
tSP
1 A master device must provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL. See Figure 2 for more information.
Timing Diagram
SDA
tF
tBUF
tF
tSP
tR
tLOW
tR
tSUDAT
tHDSTA
SCL
tHIGH
tSUSTA
tSUSTO
S
Sr
P
S
tHDDAT
S = START CONDITION
Sr = REPEATED START CONDITION
P = STOP CONDITION
Figure 2. I2C Timing Diagram
RECOMMENDED INPUT AND OUTPUT CAPACITANCE AND INDUCTANCE
Table 6.
Parameter
CAPACITANCE
VBUS Capacitance
VDD Pin Capacitance
Total Capacitance
VSYS Pin
Test Conditions/Comments
Effective capacitance
Min
Typ
Max
Unit
1.0
0.47
2.2
1.0
µF
μF
10
4.7
4.7
2.2
2.2
1
10
10
10
10
10
10
µF
µF
µF
µF
µF
µF
ISOB Pin
VIN1 Pin
VIN2 Pin
VOUT1 Node
VOUT2 Pin
1
INDUCTANCE
Buck
Buck Boost
2.2
2.2
4.7
4.7
6.8
6.8
µH
µH
Rev. 0 | Page 8 of 60
Data Sheet
ADP5360
ABSOLUTE MAXIMUM RATINGS
Table 7.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
VBUS to PGND1
PGND1, PGND2 to AGNDx
All Other Pins to AGNDx
Continuous Drain Current, Battery
Supplementary Mode from ISOB to VSYS,
TJ = 85°C
Rating
−0.5 V to +20 V
−0.3 V to +0.3 V
−0.3 V to +6 V
1.1 A
θ
JA is the natural convection, junction to ambient, thermal
resistance measured in a one cubic foot sealed enclosure. θJC is
the junction to case thermal resistance.
Temperature Range
Storage
Operating Junction
Soldering Conditions
Table 8. Thermal Resistance
Package Type
CB-32-2
−65°C to +150°C
−40°C to +85°C
JEDEC J-STD-020
θJA
50
θJC
0.35
Unit
°C/W
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADP5360 package
is limited by the associated rise in TJ on the die. At approximately
150°C, which is the glass transition temperature, the plastic
changes properties. Even temporarily exceeding this temperature
limit can change the stresses that the package exerts on the die,
permanently shifting the parametric performance of the ADP5360.
ESD CAUTION
Rev. 0 | Page 9 of 60
ADP5360
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
INT
PGND2
SW2B
VOUT2
SCL
SDA
A
B
C
D
E
F
SW2A
VIN2
AGND2
STP
ENSD
EN2
PGOOD1 THR
BSNS
ISOB
VSYS
PGOOD2
ILIM
FB1
VID1
EN1
SW1
RESET
ENCHG
MR
ICS
PGND1
VIN1
VDD
VBUS
AGND1
Figure 3. Ball Configuration (Top View)
Table 9. Ball Function Descriptions
Ball No.
Mnemonic Description
A1
A2
A3
A4
PGND2
SW2B
VOUT2
SCL
Power Ground for the Buck Boost Regulator.
Switching Node for the Buck Boost Regulator.
Buck Boost Regulator Output Pin.
I2C Serial Clock. This pin requires an external pull-up resistor.
I2C Serial Data. This pin requires an external pull-up resistor.
A5
SDA
A6
INT
Processor Interrupt (Active Low). This pin requires an external pull-up resistor. If this pin is not used, this pin can
be left floating.
B1
B2
B3
SW2A
AGND2
ENSD
Switching Node for the Buck Boost Regulator.
Analog Ground.
Shutdown Mode Select. When this pin is low, the shutdown mode disables. When this pin is high, the shutdown
mode enables.
B4
B5
EN2
PGOOD1
Enable Pin for Buck Boost Regulator.
Power-Good Signal Output. This open-drain output is the power-good signal for the selected VBUSOK, BATOK,
CHG_CMPLT, VOUT2OK, or VOUT1OK bits (see Table 65).
B6
C1
C2
C5
THR
VIN2
STP
PGOOD2
Battery Pack Thermistor Connection.
Input Power for the Buck Regulator.
Stop Switching for the Selected Channel.
Power-Good Signal Output. This open-drain output is the power-good signal for the selected VBUSOK, BATOK,
CHG_CMPLT, VOUT2OK, or VOUT1OK bits (see Table 65).
C6
D1
D2
BSNS
FB1
VID1
Battery Voltage Sense.
Feedback Sensing Input for the Buck Regulator.
Configure Buck Regulator Output Voltage. Connect a resistor from VID1 to AGND1 and AGND2 to program the buck
regulator default output voltage. Float the pin to disable the pin select feature and use the register default set.
D5
D6
ILIM
Input Current-Limit Select. Connect a resistor to AGND1 and AGND2 to set the default input current-limit level.
Float the pin to disable the pin select feature and use the register default set.
Battery Supply-Side Input to Internal Isolation FET.
ISOB
Rev. 0 | Page 10 of 60
Data Sheet
ADP5360
Ball No.
E1
E2
Mnemonic Description
SW1
EN1
RESET
MR
Switching Node for Buck Regulator.
Hardware Enable for Buck Regulators.
Reset Output.
E3
E4
Manual Reset Input.
E5
ICS
Set Charge Current. Connect one resistor to ground to set the default charge current. Float the pin to disable the
pin select feature and use the register default set.
E6
F1
F2
F3
F4
F5
F6
VSYS
PGND1
VIN1
ENCHG
AGND1
VDD
Linear Charger, Supply Side Input to the Internal Isolation FET.
Power Ground for the Buck Regulator.
Input Power for the Buck Regulator.
Logic Input for the Enable Charger Function.
Analog Ground.
Internal Circuit Power Supply.
Power Connection to USB VBUS.
VBUS
Rev. 0 | Page 11 of 60
ADP5360
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VVBUS = 5.0 V, VISOB = 3.6 V, C1 = 2.2 μF, C2 = 1 µF, C3 = C4 = 10 µF, C5 = C6 = 10 μF, C7 = C8 = 10 μF, L1 = L2 = 4.7 μH, and
all registers are at default values, unless otherwise noted.
5.2
5.1
5.0
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
5.2
5.0
4.8
4.6
4.4
4.2
V
V
= 4.4V
= 5V
VSYS
VSYS
V
V
= 4.4V
= 5V
VSYS
VSYS
0
100
200
300
(mA)
400
500
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
I
VSYS
Figure 4. VSYS Load Regulation, VVSYS = 4.4 V and 5 V, VVBUS = 5.5 V,
IVSYS from 1 mA to 400 mA, No Charging
Figure 7. VSYS Accuracy vs. Temperature, VVBUS = 5.5 V
5.5
5.0
4.5
4.0
3.5
0.40
0.35
0.30
0.25
0.20
V
V
= 4.4V
= 5V
VSYS
VSYS
3.0
4
5
6
7
2.5
3.5
4.5
5.5
V
(V)
VBUS
BATTERY VOLTAGE (V)
Figure 8. ISOFET Resistor vs. Battery Voltage
Figure 5. VSYS Line Regulation, VVSYS = 4.4 V and 5 V, No Charging
350
300
250
200
150
100
50
120
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
100
80
60
40
20
0
V
V
V
V
V
= 4.2V
TRM
TRM
TRM
TRM
TRM
= 4.3V
= 4.4V
= 4.5V
= 4.6V
I
V
ISOB
VSYS
0
4.0
4.5
5.0
5.5
(V)
6.0
6.5
2.3
2.8
3.3
3.8
4.3
V
(V)
ISOB
INPUT V
VBUS
Figure 9. Charge Current vs. Input VVBUS, ICHG = 300 mA
Figure 6. Charge Profile, VTRM = 4.2 V, ICHG = 100 mA
Rev. 0 | Page 12 of 60
Data Sheet
ADP5360
105
104
103
102
101
100
99
4.30
4.25
4.20
4.15
4.10
98
97
96
95
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
Figure 13. Charge Current vs. Temperature, ICHG = 100 mA
Figure 10. VTRM vs. Temperature, VTRM = 4.2 V
100
90
80
70
60
50
40
30
20
10
0
1.0
0.8
V
V
V
V
V
= 2.7V
= 3V
= 3.6V
= 4.2V
= 4.6V
ISOB
ISOB
ISOB
ISOB
ISOB
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
V
V
V
= 1.8V
= 3.3V
= 5V
VOUT2
VOUT2
VOUT2
0.001
0.01
0.1
1
10
100
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
OUTPUT CURRENT (mA)
Figure 11. ADC Voltage Sense Accurarcy vs. Temperature, VVBUS = 0 V
Figure 14. Buck Boost Efficiency vs. Output Current, VVIN2 = 3.6 V
100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
V
V
V
= 1.8V
= 3.3V
= 5V
OUT1
OUT1
OUT1
10
V
V
= 1.2V
= 3.3V
OUT1
OUT1
0
0
0
50
100 150 200 250 300 350 400 450 500
OUTPUT CURRENT (mA)
0.001
0.01
0.1
1
10
100
OUTPUT CURRENT (mA)
Figure 12. Buck Efficiency vs. Output Current, VVIN1 = 3.6 V, PWM Mode
Figure 15. Buck Efficiency vs. Output Current, VVIN1 = 3.8 V,
Hysteresis Mode
Rev. 0 | Page 13 of 60
ADP5360
Data Sheet
1.830
1.825
1.820
1.815
1.810
1.805
1.800
1.795
1.790
5.20
5.15
5.10
5.05
5.00
4.95
4.90
4.85
4.80
V
V
= 1.8V HYS
= 1.8V PWM
OUT1
OUT1
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
Figure 16. Buck Output vs. Temperature, VFB1_PWM_FIX and VFB1_HYS_FIX
Accuracy
Figure 19. Buck Boost Output vs. Temperature, VOUT2 Accuracy
2.50
2.48
2.46
2.44
2.42
2.40
600
500
OC_DISCH = 50mA
OC_DISCH = 200mA
OC_DISCH = 600mA
400
300
200
100
0
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
Figure 17. Battery Undervoltage Threshold vs. Temperature, BAT_UV = 2.5 V
Figure 20. Battery Overdischarge Current Threshold vs. Temperature,
VISOB = 3.8 V
4.40
4.39
4.38
4.37
4.36
4.35
4.34
4.33
4.32
4.31
4.30
450
400
350
300
OC_DISCH = 25mA
250
200
150
100
50
OC_DISCH = 150mA
OC_DISCH = 300mA
0
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
Figure 18. Battery Overvoltage Threshold vs. Temperature, VBPOV_RISE = 4.3 V
Figure 21. Battery Overcharge Current Threshold vs. Temperature,
VISOB = 3.8 V
Rev. 0 | Page 14 of 60
Data Sheet
ADP5360
1.0
1.2
1.0
0.8
0.6
0.4
0.2
0
V
V
V
= 2.5V
= 3.6V
= 4.2V
V
= 2.5V
= 3.6V
= 4.2V
ISOB
ISOB
ISOB
ISOB
ISOB
ISOB
V
0.9
V
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
Figure 22. ISOB Quiescent Current vs. Temperature, All Disabled
Figure 24. ISOB Quiescent Current vs. Temperature, Fuel Gauge Sleep Mode
Enabled, Battery Protection Enabled, Buck Enabled, Buck Boost Enabled
1.75
350
V
V
V
= 2.5V
= 3.6V
= 4.2V
V
V
V
= 4V
ISOB
ISOB
ISOB
VBUS
VBUS
VBUS
= 5V
= 6.5V
300
250
200
150
100
50
1.70
1.65
1.60
1.55
1.50
1.45
0
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
Figure 23. ISOB Quiescent Current vs. Temperature in Shipment Mode
Figure 25. VBUS Quiescent Current vs. Temperature
Rev. 0 | Page 15 of 60
ADP5360
Data Sheet
TYPICAL WAVEFORMS
V
VBUS
V
ISOB
V
VSYS
1
3
2
4
V
V
VBUS
ENCHG
2
1
I
ISOB
B
CH1 2.00V B
CH2 2.00V
M200ms
A CH2
2.04V
B
CH1 5.00V B CH2 5.00V
M100ms
A CH2
1.80V
W
W
W
W
W
CH3 5.00V B CH4 100mA Ω B
W
Figure 26. Charge Startup, VVBUS = 5 V, VISOB = 3.8 V,
IILIM = 200 mA, ICHG = 100 mA
Figure 29. Battery Detection Waveform
V
V
VBUS
VBUS
V
V
V
VSYS
VSYS
1
1
2
V
ISOB
ISOB
2
I
ISOB
I
ISOB
3
4
3
4
CH1 5.00V B
CH3 2.00V B
CH2 5.00V
CH4 50.0mA
M200ms
A CH4
116mA
B
B
B
W
W
W
W
CH1 5.00V B CH2 5.00V
M200ms
A CH4
116mA
W
W
B
CH3 2.00V B CH4 50.0mA
W
W
Figure 27. USB Connect and Start Charge, VVBUS = 5 V,
VISOB = 3.8 V, ICHG = 100 mA
Figure 30. USB Disconnect and End Charge, VVBUS = 5 V, VISOB = 3.8 V,
ICHG = 100 mA
V
V
V
VBUS
VSYS
1
VSYS
V
ISOB
ISOB
1
2
3
4
I
I
VSYS
4
B
B
CH1 2.00V B CH2 2.00V
M10.0ms A CH4
19.60000ms
61.0mA
CH1 5.00V
M400µs
A CH4
172mA
W
W
W
W
B
B
CH3 2.00V B CH4 50.0mA
CH4 200mA
T
1.196000ms
W
T
W
Figure 28. VSYS Load Transient, IVSYS = 50 mA to 300 mA
Figure 31. Adaptive Charge Current, VADPICHG[2:0] = 4.6 V,
VVBUS = 5 V with 10 Ω Impedance, ICHG = 100 mA
Rev. 0 | Page 16 of 60
Data Sheet
ADP5360
V
BSNS
V
BSNS
V
V
VSYS
VSYS
1
2
1
V
I
OUT1
2
3
4
I
ISOB
ISOB
4
B
B
CH1 2.00V B CH2 2.00V
M400ms
A CH2
1.64V
B
W
W
W
CH1 2.00V B CH2 2.00V
M200ms A CH1
920mV
W
W
CH4 100mA
CH3 1.00V B CH4 100mA B
W
W
Figure 32. Battery Overvoltage Protection Waveform,
VVBUS = 5 V, OV_CHG = 4.3 V, DGT_OV_CHG = 0.5 sec
Figure 35. Battery Charge Overcurrent Waveform,
VVBUS = 5 V, VISOB = 3.8 V, OC_CHG = 150 mA, DGT_OC_CHG = 10 ms
V
OUT1
V
BSNS
1
3
V
SW1
1
V
VSYS
V
OUT1
2
3
I
I
ISOB
L1
4
4
B
CH1 2.00V B CH2 2.00V
M20.0ms
11.08000ms
A CH2
1.28V
B
CH1 50.0mV
CH3 5.00V
M200µs
0.000000s
A CH3
2.00V
W
W
W
W
CH4 100mA B
CH3 1.00V B CH4 50.0mAB
T
W
T
W
Figure 33. Battery Undervoltage Protection Waveform,
VBUS = 0 V, UV_DISCH = 2.5 V, DGT_UV_DISCH = 30 ms
Figure 36. Buck Steady Hysteresis Waveform, Hysteresis Mode,
VIN2 = 3.8 V, VOUT1 = 1.2 V,
Buck Output Current (IOUT1) = 1 mA
V
V
V
BSNS
V
OUT1
V
V
VSYS
1
3
V
SW1
1
2
OUT1
I
ISOB
I
3
4
L1
4
B
B
W
CH1 2.00V B CH2 2.00V
M4.00ms
A CH2
1.28V
CH1 20.0mV
CH3 5.00V
M2.00µs
A CH3
2.00V
W
W
B
CH3 1.00V B CH4 100mA
CH4 100mAB
W
T
2.040000ms
T
0.000000s
W
W
Figure 37. Buck Steady PWM Waveform, PWM Mode,
VVIN1 = 3.8 V, VOUT1 = 1.2 V, IOUT1 = 1 mA
Figure 34. Battery Discharge Overcurrent Waveform,
VVBUS = 0 V, VISOB = 3.8 V, OC_DISCH = 100 mA, DGT_OC_DISCH = 10 ms
Rev. 0 | Page 17 of 60
ADP5360
Data Sheet
V
OUT1
1
V
OUT1
1
2
V
PGOOD1
I
OUT1
V
SW1
3
4
I
L1
4
B
B
B
B
W
CH1 1.00V
CH3 5.00V
CH2 2.00V
CH4 200mA
M4.00ms
A CH1
600mV
CH1 50.0mV
M4.00ms A CH4
11.96920ms
62.0mA
W
W
W
B
CH4 100mA
T
9.960000ms
T
W
Figure 38. Buck Output Soft Start, Set EN_BUCK High,
PWM Mode, VVIN1 = 3.8 V, VOUT1 = 1.2 V, PGOOD1 Mask to Buck Output
Figure 41. Buck Output Transient Waveform, VVIN1 = 3.8 V, VOUT1 = 1.2 V,
I
OUT1 = 1 mA to 100 mA, Hysteresis Mode
(VOUT1), IOUT1 = 1 mA, tSS1 = 8 ms
V
VOUT2
V
OUT1
V
1
SW2A
1
2
V
V
SW2B
PGOOD1
2
3
V
SW1
3
4
V
STP
V
PGOOD2
4
B
CH1 1.00V
CH3 5.00V
CH2 5.00V
CH4 5.00V
M40.0ms
A CH4
2.50V
W
CH1 5.00V B CH2 5.00V
M4.00ms
A CH1
3.40V
B
W
W
B
CH3 5.00V
CH4 200mA
T
11.08000ms
W
Figure 39. Buck Stop Function Waveform, VVIN1 = 3.8 V, VOUT1 = 1.2 V,
Hysteresis Mode, PGOOD1 Mask to VOUT1, STP_BUCK = 1 Bit
Figure 42. Buck Boost Output Soft Start Waveform, VVIN2 = 3.8 V, VOUT2 = 5 V,
BUCKBST_SS[0:1] = 8 ms, Buck Boost Output Current (IOUT2) = 1 mA,
PGOOD2 Mask to VOUT2
V
VOUT2
V
OUT1
1
2
1
V
V
SW2A
SW2B
I
OUT1
3
4
4
I
L2
B
CH1 50.0mV
M100µs A CH4
289.0000µs
82.0mA
W
B
W
CH1 100mV
CH3 5.00V
CH2 5.00V
CH4 100mA B
M200µs A CH2
0.000000s
2.70V
B
CH4 100mA
T
W
T
W
Figure 40. Buck Output Transient Waveform, VVIN1 = 3.8 V, VOUT1 = 1.2 V,
IOUT1 = 1 mA to 100 mA, PWM Mode
Figure 43. Buck Boost Steady Waveform, VVIN2 = 3.8 V,
VOUT2 = 5 V, IOUT2 = 1 mA
Rev. 0 | Page 18 of 60
Data Sheet
ADP5360
V
OUT1
V
VOUT2
V
INT
1
2
1
V
V
RESET
PGOOD2
2
3
V
SW2A
3
4
V
MR
V
STP
4
CH1 1.00V B CH2 5.00V
M100ms
A
CH1
600mV
B
B
W
W
W
CH1 5.00V B CH2 2.00V B
CH3 5.00V
M4.00ms
A CH4
2.90V
CH3 2.00V B CH4 5.00V
W
W
W
W
CH4 5.00V B
T
12.08000ms
Figure 44. Buck Boost Stop Function Waveform, VVIN2 = 3.8 V,
VVOUT2 = 5 V, PGOOD2 Mask to VOUT2, STP_BUCKBST = 1 Bit
Figure 47. MR Press to Trigger Interrupt and RESET, EN_WD_INT = 1 Bit,
RESET_TIME = 200 ms
V
OUT1
V
VOUT2
V
VSYS
1
1
V
RESET
2
3
I
OUT2
V
MR
4
4
B
B
B
CH1 1.00V B
CH3 2.00V B
CH2 2.00V
CH4 5.00V
M4.00s
A CH1
600mV
CH1 100mV
M4.00ms
CH4
49.0mA
W
W
W
W
B
CH4 50.0mA
T
11.96920ms
W
W
Figure 45. Buck Boost Output Transient Waveform,
VVIN2 = 3.8 V, VVOUT2 = 3.3 V, IOUT2 = 1 mA to 50 mA
Figure 48. Press MR for Greater than 12 sec to Enter Shipment Mode,
EN_MR_SD = 1 Bit, ENSD Pin High
V
OUT1
V
OUT1
1
1
2
3
V
V
VSYS
PGOOD1
2
3
V
RESET
V
MR
V
RESET
4
B
B
B
B
B
B
B
W
CH1 1.00V
CH3 2.00V
CH2 2.00V
CH4 5.00V
M100ms
A CH1
600mV
CH1 1.00V
CH3 2.00V
CH2 2.00V
M40.0ms
A CH1
600mV
W
W
W
W
W
W
Figure 46. RESET Output and VOUT1, VISOB = 3.8 V, VOUT1 = 1.2 V,
RESET_TIME = 200 ms, PGOOD1 Mask to VOUT1
Figure 49. Press MR to Exit Shipment Mode, ENSD Pin High
Rev. 0 | Page 19 of 60
ADP5360
Data Sheet
THEORY OF OPERATION
BATTERY CHARGER
Table 10. VBUS Input Current-Limit Default Set with ILIM Pin
Charger Introduction
RILIM Value (kΩ)
ILIM Value (mA)
The ADP5360 integrates a fully I2C-programmable charger for
single-cell Li-Ion/Li-Poly batteries suitable for a wide range of
portable applications.
100
68
47
36
27
20
15
10
50
100
150
200
250
300
400
500
The linear charger architecture enables up to 500 mA of output
current on the system power supply and up to 320 mA of charge
current into the battery from a dedicated charger.
The charger of the ADP5360 operates from an input voltage of
up to 6.8 V but is tolerant of voltages up to 20 V to alleviate the
concern of USB bus spiking during disconnection or connection
scenarios.
The current-limit defaults to 100 mA to allow compatibility
with a USB host or hub that is not configured. This input
current limit resets to a default value of 100 mA during every
VBUS power-on cycle, thereby protecting the USB port.
The ADP5360 features an internal FET between the linear
charger output and the battery node to permit battery isolation
and system power in a dead battery or no battery scenario,
allowing instanteneous system function when connected to a
USB power supply.
When the input current-limit feature is used, it is possible for
the available input current to be too low for the charger to meet
the programmed charging current (ICHG), and the rate of charge
reduces. In this case, the VBUS_ILIM bit flag sets.
The charger of the ADP5360 enables charging via the mini
VBUS pin (F6 pin) from a wall charger, car charger, or USB host
port. Based on the type of USB source, which is detected by an
external USB detection device, the ADP5360 can apply the proper
current limit for optimal charging and USB compliance. The USB
charger permits correct operation under all USB compliant
sources including wall chargers, host chargers, hub chargers, and
standard hosts and hubs.
A processor controls the USB charger using the I2C to program
the charging current and numerous other parameters, including
the following:
When VVBUS is between 3.9 V and 6.8 V, the VBUSOK bit is set.
Trickle Charge Mode
A deeply discharged Li-Ion cell can exhibit a low cell voltage,
making it unsafe to charge the cell at high current rates. The
ADP5360 charger uses its trickle charge mode to raise the cell
voltage to a safe level for fast charging. A cell with a voltage lower
than VTRK_DEAD charges with ITRK_DEAD. During trickle charge mode,
the CHARGER_STATUS[2:0] bits of the CHARGER_STATUS1
register are set.
During trickle charging, the VSYS node is regulated to VSYS_REG
by the linear regulator. The battery isolation FET is off, therefore
the battery is isolated from the system power supply. Refer to
Table 11 for the VSYS_REG output voltages.
•
•
•
•
•
•
•
•
Trickle charge current level and voltage threshold
Fast charge (constant current) current level
Fast charge (constant voltage) termination voltage level
Fast charge safety timer period
Weak battery threshold detection
End of charge current level for charge completion
Recharge voltage threshold
Table 11. VSYS_REG Output Voltages
V
SYS_REG (V)
VTRM Setting
VSYSTEM = VTRM + 200 mV VSYSTEM = 5 V
VTRM ≤ 4.26 V
4.4
4.5
4.6
4.7
4.8
5
5
5
5
5
VBUS input current limit
4.26V < VTRM ≤ 4.36V
4.36V < VTRM ≤ 4.46V
4.46V < VTRM ≤ 4.56V
4.56V < VTRM ≤ 4.66V
Input Current Limit and USB Compatibility
The VBUS input current limit is programmed via an internal
I2C ILIM register (RILIM) from 50 mA to 500 mA, ensuring
compatibility with different requirements. An external resistor
from the ILIM pin to ground can also set the input current limit
as the default. Floating the ILIM pin activates the register
default value when powering up.
When VVBUS is lower than the set value of VSYS_REG, VVSYS cannot
be regulated, which impacts the charged current (see Figure 9).
Rev. 0 | Page 20 of 60
Data Sheet
ADP5360
The ADP5360 features a dynamic charge current that is
Trickle Charge Mode Timer
adaptive when VVBUS drops too much due to possible high
internal impedance. The dynamic charge current monitors
The duration of trickle charge mode is monitored to ensure that
the battery revives from the deeply discharged state. If trickle
charge mode runs for longer than tTRK without the cell voltage
reaching VTRK_DEAD, a fault condition is assumed and charging
stops. The battery isolation FET turns off, and VSYS is regulated
to VSYS_REG by the linear regulator. The fault condition asserts on
when the CHARGER_STATUS[2:0] bits are set to 0b110,
allowing the user to initiate the fault recovery procedure
specified in the Fault Recovery section.
V
VBUS and reduces the charge current level when VVBUS falls
lower than the threshold, which can be programed by the I2C
interface. When the charge current adapts due to the VVBUS level,
the ADPICHG status bit is set high. By default, this feature is
disabled and can be enabled by the I2C setting.
Fast Charge Mode (Constant Voltage)
As the battery charges, the voltage rises and approaches VTRM
.
The ADP5360 charger monitors VBSNS to determine when charging
ends. However, the internal impedance of the battery pack
combined with the PCB and other parasitic series resistances
creates a voltage drop between the sense point at the BSNS pin
and the cell terminal. To compensate for this voltage drop and
ensure a fully charged cell, theADP5360 enters a constant voltage
charge mode when VBSNS reaches the termination voltage. The
ADP5360 reduces charge current gradually as the cell continues to
charge, maintaining a voltage of VTRM on the BSNS pin. During
constant voltage fast charge mode, the CHARGER_STATUS[2:0]
bits are set to 0b011.
Weak Charge Mode (Constant Current)
When the battery voltage exceeds VTRK_DEAD but is less than
V
WEAK, the charger switches to the weak charge mode, and VSYS
is regulated to VSYS_REG by the battery isolation FET. Note that,
SYSTEM = 5 V is not active on the output of VSYS_REG during
V
charge mode.
During weak charge mode, the battery is charged with
programmed ICHG from VSYS through the isolation FET and
ITRK_DEAD. Due to the VBUS input current limit, the real charge
current (ICHG) from VSYS may be less than the programmed
value. System load can share the current from VSYS. However,
Fast Charge Mode Timer
ITRK_DEAD always charges the battery during weak charge mode.
The duration of fast charge mode is monitored to ensure that
the battery is charging correctly. If the fast charge mode runs for
longer than tCHG without VBSNS reaching VTRM, a fault condition
is assumed, charging stops, the battery isolation FET turns off,
and VSYS regulates to VSYS_REG by the linear regulator. A fault
condition asserts on when the CHARGER_STATUS[2:0] bits
are set to 0b110, allowing the user to initiate the fault recovery
procedure specified in the Fault Recovery section.
Fast Charge Mode (Constant Current)
When the battery voltage exceeds VWEAK, the charger switches to
fast charge mode, charging the battery with ICHG. Address 0x04,
ICHG[4:0] programs ICHG via the I2C interface. During fast charge
mode (constant current), the CHARGER_STATUS[2:0] bits are set
to 0b010. The default ICHG value can be set by the external
resistor from the ICS pin (RICS) to ground. Floating the ICS pin
activates the register default value when powering up.
If the fast charge mode runs for longer than tCHG and the BSNS
pin reaches VTRM but the charge current has not yet fallen lower
than IEND, charging stops by turning off the battery isolation
FET. Note that the linear regulator still works, and VSYS regulates
to VSYS_REG. No fault condition is asserted in this circumstance, and
the ADP5360 attains charge complete status.
Table 12. Charge Current Default Set Using the ICS Pin
RICS Value (kΩ)
ICHG Value (mA)
100
68
47
36
27
20
15
10
10
50
80
100
150
200
250
300
Safety Timer
If the watchdog timer (see the Watchdog Timer section for more
information) expires while in charger mode, theADP5360 charger
initiates tSAFE. Charging continues for a period of tSAFE, then stops
by turning off the battery isolation FET and setting the
CHARGER_STATUS[2:0] bits to 0b110.
During constant current mode, other features can prevent ICHG
from reaching the full programmed value. Input current
limiting for USB compatibility can affect the ICHG value under
certain operating conditions. The battery isolation FET regulates
VVSYS to stay at VSYS_REG. Note that, VSYSTEM = 5 V is not active on
the output of VSYS_REG during charge mode.
Rev. 0 | Page 21 of 60
ADP5360
Data Sheet
therefore allowing the system to be powered at all times. The
battery isolation FET maintains VSYS_REG on the VSYS pin.
Charge Complete
The ADP5360 charger monitors the charging current while in
constant voltage fast charge mode. When EN_TEND is low, the
current falls lower than IEND for tDG, and the charger is stopped
by turning the battery isolation FET off. The system voltage is
maintained at VSYS_REG by the linear regulator and sets the
CHG_CMPLT flag. When EN_TEND is set to high, the charging
current falls lower than IEND for another tEND, stopping the
charger and setting the CHG_CMPLT flag.
When VBUS is lower than VVBUS_OK, the battery isolation FET is
in full conducting status.
The battery isolation FET supplements the battery to support
high current functions on the system power supply when VBUS
current is limited.
When the voltage on VSYS drops lower than ISOB, the battery
isolation FET enters full conducting mode.
Recharge
BATTERY DETECTION
Battery Level Detection
After the detection of charge is complete, and the battery isolation
FET turns off, the ADP5360 charger still monitors the BSNS pin.
If the BSNS pin voltage falls by VRCH, the charger reactivates.
Under most circumstances, triggering the recharge threshold
results in the charger starting in fast charge mode.
The ADP5360 charger features a battery detection mechanism to
detect an absent battery. When the charger starts charging, it
actively sinks and sources current into ISOB and voltage vs.
time is detected. The sink phase detects a charged battery, while
source phase detects a discharged battery.
Battery Charging Enable or Disable
To enable the ADP5360 charging function, set the EN_CHG bit
high or pull the ENCHG pin high. The hardware ENCHG pin is
logically OR’ed with the EN_CHG bit, Address 0x07. If the
charger is disabled, the linear regulator remains turned on and
regulatesVVSYS to VSYS_REG. The battery isolation FET turns off,
and the linear regulator provides the power for the system.
The sink phase sinks current (ISINK) from the ISOB pin and the
BSNS pin for typically 330 ms (see Figure 50). If the BSNS pin is
lower than VBATL when the 330 ms timer expires, the charger starts
the source phase. If the BSNS pin exceeds the VBATL voltage when
the 330 ms timer expires, the charger begins a new charge cycle.
The source phase sources current (ISOURCE) to the ISOB pin or
the BSNS pin for typically 330 ms. If the BSNS pin exceeds
BATTERY ISOLATION FET
The ADP5360 charger features an integrated battery isolation
FET for power path control and battery protection. The battery
isolation FET isolates a deeply discharged Li-Ion cell from the
system power supply in both trickle and fast charge modes,
V
BATH before the 330 ms timer expires, it is assumed that no
battery is present. If the BSNS pin does not exceed VBATH when
the 330 ms timer expires, it is assumed that a battery is present,
and the charger begins a new charge cycle.
SINK PHASE
SOURCE PHASE
V
V
LOGIC
BATL
LOGIC
BATH
STATUS
STATUS
I
SOURCE
tBATOK
tBATOK
OPEN
OR
SHORT
OPEN
OR
SHORT
ISOB
ISOB
I
SINK
OPEN
OPEN
Figure 50. Battery Detection Sequence
Rev. 0 | Page 22 of 60
Data Sheet
ADP5360
EN_THR bit (Address 0x0A) high to enable the THR function. To
save quiescent current the THR node voltage update rate slows
to 30 seconds.
BATTERY TEMPERATURE
Battery Pack Thermistor Input
The ADP5360 charger features battery pack temperature
sensing that precludes charging when the battery pack
temperature is outside of the specified range. The THR pin
provides three programmable current sources: 60 μA, 12 μA,
and 6 μA. Accordingly, the THR pin supports 10 kΩ, 47 kΩ, and
100 kΩ NTC resistors at 25°C. The THR pin is connected
directly to the battery pack thermistor terminal.
If the battery pack thermistor is not connected directly to the
THR pin, a 100 kΩ (tolerance 20%) dummy resistor must be
connected between the THR pin and the AGND1 and AGND2
pins. Leaving the THR pin open results in a false detection of a
<0°C battery temperature, and charging disables.
The ADP5360 charger monitors the voltage on the THR pin and
suspends charging if the voltage is less than 0°C or higher than
60°C. For temperatures greater than 0°C and lower than 60°C, the
THR_STATUS[2:0] bits, Address 0x09, are set accordingly.
When the THR function is enabled, the THR node voltage is
sensed by the ADC and can be read in the 12-bit registers,
THR_V_HIGH and THR_V_LOW. Calculate the external
thermistor value (RNTC) by using the following equation:
JEITA Li-Ion Battery Temperature Charging Specification
R
NTC = (THR_V/60 µA)
The charge of the ADP5360 is compliant with the JEITA Li-Ion
battery charging temperature specifications as shown in Table 13.
The JEITA function can be enabled via the I2C interface. When
the ADP5360 detects a JEITA cool condition, the charging
current reduces, as shown in Table 14.
where:
THR_V is the ADC readback from the THR_V_HIGH and
THR_V_LOW registers.
60 μA is selected by the THR pin source current.
To achieve the battery temperature, the RNTC value must be
known.
When the ADP5360 identifies a hot or cold battery condition,
the battery isolation FET turns off. The VSYS pin is linear regulated
at VSYS_REG and provides power for the system.
When VVBUS is higher than VVBUS_OK_RISE, the THR function is
forced to enable for the charger control requirement. The update
rate is 1 second. When VVBUS is lower than VVBUS_OK_RISE, set the
Table 13. JEITA Li-Ion Battery Charging Specification Defaults
Parameter
JEITA Cold Temperature Limits
JEITA Cool Temperature Limits
Symbol
IJEITA_COLD
IJEITA_COOL
Conditions
No battery charging occurs.
Battery charging occurs at approximately 50% or 10% of programmed
level. See Table 14 for specific charging current reduction levels.
Min Max Unit
0
10
°C
°C
0
JEITATypical Temperature Limits
JEITA Warm Temperature Limits
IJEITA_TYP
Normal battery charging occurs at default and programmed levels.
10
45
45
60
°C
°C
IJEITA_WARM Battery termination voltage (VTRM) is reduced by 100 mV from
programmed value.
JEITA Hot Temperature Limits
IJEITA_HOT
No battery charging occurs.
60
°C
Table 14. JEITA Cool Temperature Limit—Reduced Charge Current Levels
ICHG JEITA Value (mA)
ILIM_JEITA_COOL = 1
ICHG[4:0] Value (mA)
00000 = 10
00001 = 20
00010 = 30
00011 = 40
00100 = 50
00101 = 60
00110 = 70
ILIM_JEITA_COOL = 0
10
10
10
20
20
30
30
40
40
50
50
60
60
10
10
10
10
10
10
10
10
10
10
10
10
10
00111 = 80
01000 = 90
01001 = 100
01010 = 110
01011 = 120
01100 = 130
Rev. 0 | Page 23 of 60
ADP5360
Data Sheet
ICHG JEITA Value (mA)
ILIM_JEITA_COOL = 1
ICHG[4:0] Value (mA)
01101 = 140
01110 = 150
01111 = 160
10000 = 170
10001 = 180
10010 = 190
10011 = 200
10100 = 210
10101 = 220
10110 = 230
10111 = 240
11000 = 250
11001 = 260
11010 = 270
11011 = 280
11100 = 290
11101 = 300
11110 = 310
11111 = 320
ILIM_JEITA_COOL = 0
70
70
80
80
90
90
100
100
110
110
120
120
130
130
140
140
150
150
160
10
20
20
20
20
20
20
20
20
20
20
30
30
30
30
30
30
30
30
Rev. 0 | Page 24 of 60
Data Sheet
ADP5360
Battery Charger Operational Flow Chart
POWER-ON RESET
N
Y
RUN
BATTERY
DETECTION
tSTART
EXPIRED
N
Y
RESET ALL
REGISTERS
VBUSOK
POWER
DOWN
Y
N
V
< V
TRK
BSNS
TRICKLE
CHARGE
FAST CHARGE
N
N
N
VBUSOK
Y
VBUSOK
Y
VBUS_ILIM = HIGH
= I
N
V
< V
I
< I
LIM
BSNS
Y
TRK
VBUS
Y
I
VBUS
LIM
WATCHDOG
EXPIRED
t
TSD110 = HIGH
Y
Y
WD
N
TEMP < T
Y
EXPIRED
TEMP = T
START t
SD
SD
SAFE
I
= 100mA
BUS
N
WATCHDOG
EXPIRED
START tSAFE
TIMER FAULT/
BAD BATTERY
t
/t
SAFE TRK
EXPIRED
t
Y
WD
EXPIRED
I
= 100mA
VBUS
N
N
TIMER FAULT/
BAD BATTERY
(SEE THE FAST CHARGE
MODE TIMER SECTION
AND THE SAFETY
TIMER SECTION)
Y
t
/t
SAFE CHG
RUN
BATTERY
DETECTION
Y
EXPIRED
N
Y
N
N
V
=
CONSTANT CURRENT
MODE CHARGING
BSNS
V
≤
BSNS
– V
N
V
V
≤
V
BSNS
TRM
V
TRM
RCH
NOBAT
Y
CHARGE
COMPLETE
Y
N
CONSTANT VOLTAGE
MODE CHARGING
I
< I
END
OUT
Figure 51. Charger Operational Flowchart
limitation algorithm integrated in theADP5360. The ten open-
circuit battery values and battery capacity are based on the
battery characterization written to the V_SOC_x registers of the
ADP5360 and used for the state of charge calculation. The sense
current information, the battery capacity value, the continuous
load current, and the large voltage drop all determine the state of
the charge change rate. The fuel gauge operates as a coulomb
counter with a high accuracy calculation when high continuous
BATTERY FUEL GAUGE
General Description
The ADP5360 Li-Ion battery fuel gauge is optimized through a
hybrid algorithm to indicate battery remaining capacity. The
battery fuel gauge runs through a coulomb counter and is voltage-
based between 0% to 100%. The battery fuel gauge uses a 12-bit
ADC to measure the battery node voltage and the battery current.
The state of the charge is calculated with an adaptive filter
Rev. 0 | Page 25 of 60
ADP5360
Data Sheet
load current is applied. When the battery voltage reaches terminal
voltage and charging completes, the battery state of the charge
register, BAT_SOC, indicates 100% for battery capacity.
When BAT_SOCACM_H and BAT_SOCACM_L increase and
reache 4096 points, and the battery has compiled nearly 41 full
charges, then the BAT_SOCACM_H and BAT_SOCACM_L
bits overflow and clear. The interrupt SOCACM_INT bit in
Regiser 0x34 immediately asserts, and the system can adjust the
BAT_CAP register manually or select automatic adjustment by
setting the EN_BATCAP_AGE bit high. When selecting the
battery aging automatic adjustment function, the battery
capacity reduction proportion can be programmed by the
BATCAP_AGE bits. When enabling this battery capacity aging
automatic adjustment function, the BAT_CAP register cannot be
rewritten to because this register is automatically adjusted by
the ADP5360.
When the state of charge data is lower than the SOC_LOW_TH[1:0]
bits configuration, the interrupt asserts, and the SOCLOW_INT bit
is set high for as long as the low state of the charge interrupt
feature is allowed.
Operation Mode
The ADP5360 fuel gauge default is shutdown mode to provide
extremely low standby current consumption from the battery.
After enabling the fuel gauge function, the state of charge
initializes and calculates the first data only according to the
battery voltage. Two operation modes can be selected: active
and sleep. The I2C controls fuel gauge operation mode selection.
Battery Capacity Adjustment with Temperature
The Li-Ion battery capacity depends on the ambient operation
temperature. The ADP5360 automatically adjusts the battery
capacity calculation value based on the temperature variation
when setting the EN_BATCAP_TEMP bit high. The
temperature information comes from the THR node voltage
sense. Therefore, the battery THR function must be active, and
the EN_THR bit must be set to high.
During active mode, the battery state of charge updates every
ten seconds, and the battery voltage and instant current (IINS
are sampled every second. The new mapping state of charge
compares to the last state of charge value and then updates
)
using the adaptive state of charge limit. According to the sense
current and input battery capacity, the ADP5360 calculates the
state of charge limit for a state of charge update each cycle.
The BATCAP_TEMP[1:0] bits can program the battery capacity
calculation value adjustment proportion, and this value
decreases as the temperature rises. This battery capacity
adjustment is only effective when the THR node voltage
senses the corresponding range of the TEMP_HIGH_45 to
TEMP_LOW_0 bits (see Figure 52 and Table 17).
105
During sleep mode, the state of charge update cycle is one minute,
and the voltage and the current are sampled every 7.5 seconds.
During this mode, the 12-bit ADC uses intervals and shutdown
mode to save as much quiescent current as possible. Table 15
shows the fuel gauge quiescent current, ADC sample rate, and state
of charge update rate. When the sense current is higher than the
sleep current threshold setting (Address 0x27, SLP_CURR[1:0]
bits), the ADP5360 fuel gauge exits sleep mode and enters active
mode automatically.
100
95
90
85
80
75
Battery Capacity Adjustment with Aging
The ADP5360 features record total battery charged energy
reporting when the device powers up, which allows estimation
of battery aging.
The 12 BAT_SOCACM_H and BAT_SOCACM_L bits
accumulate increased state of charge during every charge cycle.
For example, the state of charge increases from 20% to 80%
during charging, and these bits add 60 points. 100 points indicates
one full charge cycle.
70
0.2%/°C
0.4%/°C
65
0.6%/°C
0.8%/°C
60
0
5
10
15
20
25
30
35
40
45
TEMPERATURE (°C)
Figure 52. Battery Capacity Adjustment by Temperature in Fuel Gauge
Table 15. Fuel Gauge Operating Mode
Operation Mode
Typical Quiescent Current (μA)
ADC Sample Rate (sec)
State of Charge Update Rate
Sleep
0.2
7.5
15
30
60
1
1 min
4 min
8 min
16 min
10 sec
Active
3.5
Rev. 0 | Page 26 of 60
Data Sheet
ADP5360
Flowchart of State of Charge Calculation
ENABLE FUEL GAUGE
FIRST_START = TRUE
READ V
READ I
BSNS
BAT
CALCULATE
SOC-BASED
ON VOC MAPPING
YES
NO
SAMPLE
TIMER OUT?
CALCULATE
FILTER LIMITS
NO
YES
CHARGE
YES
YES
FIRST_START
NO
FIRST_START
NO
FIRST_START = FALSE
NO NO
NEW_SoC <
OLD_SoC
NEW_SoC >
OLD_SoC
YES
YES
NEW_SoC =
OLD_SoC –
DISCHG_LIM
NEW_SoC =
OLD_SoC +
CHG_LIM
NEW_SoC =
NEW_SoC
UDPATE NEW_SoC TO
BAT_SOC REGISTER
NOTES
1. SOC AND SoC MEAN STATE OF CHARGE.
2. FIRST_START IS THE FLAG OF THE FUEL GAUGE FROM DISABLE TO ENABLE.
3. NEW_SOC IS THE LATEST SOC, AND OLD_SOC IS THE SOC BEFORE THE LATEST SOC.
4. DISCHG_LIM AND CHG_LIM ARE THE ADAPTIVE STATE OF CHANGE LIMITS FOR DISCHARGINGAND CHARGING.
Figure 53. Fuel Gauge Algorithm Flowchart (VOC Mapping Indicates Open-Circuit Battery Voltage Corresponding to 10 V_SOC_x Regsiters)
Rev. 0 | Page 27 of 60
ADP5360
Data Sheet
BATTERY PROTECTION
BUCK REGULATOR OPERATION
Operation Mode
The ADP5360 features a full battery protection feature for Li-Ion
and Li-Poly batteries. By default, after VISOB rises higher than
The ADP5360 has two operation modes, PWM and hysteresis
that are controlled by the I2C interface.
VUVLO and exits from shipment mode, battery protection is enabled.
The ADP5360 supports the following fault protections:
PWM Mode
•
•
•
•
Undervoltage protection when the battery overdischarges
Overdischarge current protection
Overvoltage protection when the battery overcharges
Overcharge current protection
In PWM mode, the buck regulator operates at a fixed 1 MHz
frequency that is set by an internal oscillator. At the start of each
oscillator cycle, the high-side MOSFET switch turns on and sends a
positive voltage across the inductor. The inductor current increases
until the current sense signal exceeds the peak inductor current
threshold, which turns off the high-side MOSFET switch. This
threshold is set by the error amplifier output. During the high-side
MOSFET off time, the inductor current decreases through the
low-side MOSFET until the next oscillator clock pulse starts a
new cycle.
When VBSNS is lower than the battery undervoltage threshold after
deglitch time, undervoltage protection triggers, the isolation FET
turns off and isolates all system load to the ISOB pin, and the
BAT_UV_STATUS bit is set high to indicate the battery status
and fault register assertion. During undervoltage protection, the
charger allows charge to the battery if the EN_CHGLB bit,
Address 0x11, is set to high, and the charger exits undervoltage
protection when the battery voltage becomes higher than the
undervoltage threshold. The charger does not allow any charge for
battery safety consideration if the EN_CHGLB bit is set low. Use
the I2C interface to select the undervoltage threshold and
response time.
In PWM mode, the regulator can supply up to 500 mA of average
output current. The regulator can provide lower voltage ripple
in PWM mode, which is useful for noise sensitive applications.
Hysteresis Mode
In hysteresis mode, the buck regulator in the ADP5360 charges
the output voltage to a higher value than the nominal output
voltage with PWM pulses. The buck regulator charges the
output voltage by regulating the constant peak inductor current
that is programed by the I2C interface. When the output sense
signal exceeds the hysteresis upper threshold, the regulator enters
standby mode. In standby mode, the high-side and low-side
MOSFETs and the control circuitry are disabled to allow a low
quiescent current as well as a high efficiency performance.
When the battery discharge current going through the isolation
FET increases and rises higher than the overcurrent threshold
after deglitch time, the overcurrent protection is triggered, and
the isolation FET turns off and isolates all system load to the
ISOB pin. This protection behavior can be selected to latch-up
protection mode or hiccup mode by setting the OC_DIS_HICCUP
bit, Address 0x11. In latch-up protection mode, the isolation
FET turns off and shuts down the VSYS output after retrying
three times. When the fault is removed, clearing the fault
register or a VBUS power reset can recover normal operation.
In hiccup protection mode, the isolation FET attempts to turn
on after the typical 200 ms shutdown time until the system load
fault is removed.
During standby mode, the output capacitor supplies energy into
the load, and the output voltage decreases until the voltage falls
lower than the hysteresis comparator lower threshold. The buck
regulator wakes up and generates the PWM pulses to charge the
output again.
When triggering battery overvoltage protection, the LDO FET
turns off, charging stops, and the LDO FET stays in suspend
status. Duirng this protection, the isolation FET is selectable and
can be turned off or kept turned.
Because the output voltage occasionally enters standby mode
and then recovers, the output voltage ripple in hysteresis mode
is larger than the ripple in PWM mode. The varying switching
frequency creates more noise in the system. Therefore, it is
recommended to use PWM mode during charging status.
When triggering the battery overcharge current, the LDO FET
turns off, charging stops, and the LDO FET stays in suspend status.
The isolation FET also turns off and shuts down the VSYS output.
If selecting the latch-up overcharge protection mode, the charger
remains in suspend status, and the battery does not allow charging
after three retries. If selecting hiccup protection mode, the
charger always attempts to restart the charge until the charger
fault is removed. Clearing the fault register or VBUS power reset
can recover normal operation after the fault is removed.
Use the following equation in hysteresis mode to calculate the
regulator output current:
I
LOAD1_HYS = IPEAK1_HYS/2
where:
I
I
LOAD1_HYS is the regulator output current.
PEAK1_HYS is the inductor peak current.
The maximum regulator output current is 100 mA when the
limitation of the inductor peak current, BUCK_ILIM, is set to
200 mA.
All battery protection function selection must be done when the
ADP5360 powers up. Do not change the battery protection
function during battery fault.
Rev. 0 | Page 28 of 60
Data Sheet
ADP5360
Program Output Voltages
PGOOD Indication
Adjustable output voltage settings are available on the ADP5360
by connecting a resistor through the VID1 pin to the AGND1
and AGND2 pins. The VID detection circuitry works in the
start-up period, and the voltage ID code is sampled and held
into the internal register and does not change until the next
power recycle.
The VOUT1OK bit, Address 0x2F, indicates whether the buck
regulator is working appropriately. A logic high indicates that the
output voltage of the buck regulator is higher than 90% (typical
rising threshold) of the nominal output. When the regulated
output voltage falls lower than 87% (typical falling threshold) of
the nominal output, the VOUT1OK bit goes low.
Table 16 lists the output voltage options for the VID1 pin
configurations. Additional output voltage options from 0.6 V to
3.75 V with a 50 mV step are available on the ADP5360, and to
program these options set the VOUT_BUCKBST[5:0] bits,
Address 0x2C via the I2C interface. The ADP5360 also has a fixed
output voltage that is programmed via the factory fuse. In this
case, connect the VID1 pin to the VIN1 pin.
The status indication of the VOUT1OK bit can be masked to
the hardware pin output of the PGOOD1 pin or PGOOD2 pin
by setting Register PGOODx_MASK with the I2C interface.
Soft Start
The ADP5360 buck regulator has an internal soft start function
that ramps up the output voltage in a controlled manner during
startup, thereby limiting the inrush current. This feature prevents
possible input voltage drops when a battery or a high impedance
power source is connected to the input of the device. The default
typical soft start time is 1 ms for the regulator. Other soft start
times (8 ms, 64 ms, and 512 ms) can be programmed for the
ADP5360 by the I2C interface.
Table 16. VOUT1 Default Set Using the VID1 Pin
VID1 Resistor, RVID1 Value (kΩ)
VOUT1 Value (V)
100
68
47
36
27
20
15
10
3.3
3.0
2.8
2.5
1.8
1.5
1.2
1.0
100% Duty Cycle Operation
When the input voltage approaches the output voltage, the
ADP5360 stops switching and enters 100% duty cycle operation.
The buck connects the output via the inductor and the internal
high-side power switch to the input. When the input voltage is
charged again, and the required duty cycle falls to 95% typical, and
the buck immediately restarts switching and regulation without
allowing overshoot on the output voltage.
For the output voltage settings, the feedback resistor divider is
built into the ADP5360, and the feedback pin (FB1) must be
tied directly to the output. An ultra low power voltage reference
and an integrated high impedance feedback divider network
contribute to the low quiescent current. Floating the VID1 pin
activates the register default value when powering up.
Active Discharge
The ADP5360 integrates an optional discharge switch from
the switching node to ground. This switch turns on when the
associated regulator is disabled to help discharge the output
capacitor quickly. The typical value of the discharge switch is
255 Ω for the regulator.
Enable and Disable
The ADP5360 includes a hardware enable pin (EN1). A logic
high on the EN1 pin starts the buck regulator. Due to the low
quiescent current design, it is typical for the regulator to start
switching after a delay of a few milliseconds from when the
EN1 pin is pulled high. Do not pull the EN1 pin high to the
ISOB pin because that can cause unexpected leakage current. It
is recommended to pull the EN1 pin high to the VSYS pin with
a resistor.
The active discharge feature can be enabled by setting the
DISCHG_BUCK bit, Address 0x29, high for the buck regulator.
Current-Limit Protection
The buck regulator in the ADP5360 has protection circuitry
that limits the direction and the amount of current to a certain
level that flows through the high-side MOSFET and the low-side
MOSFET in cycle by cycle mode. The positive current limit on
the high-side MOSFET limits the amount of current that can
flow from the input to the output. The negative current limit on
the low-side MOSFET prevents the inductor current from
reversing direction and flowing out of the load.
The EN_BUCK bit, Address 0x29, can control the buck enable
and disable, which is logically ANDed with the EN1 pin. For
example, set the EN_BUCK bit high, and use the EN1 pin
control buck to enable or to disable. Alternatively, pull the EN1
pin high and set the EN_BUCK bit via the I2C interface.
Rev. 0 | Page 29 of 60
ADP5360
Data Sheet
Short-Circuit Protection
BUCK BOOST REGULATOR OPERATION
The buck regulator in the ADP5360 includes frequency
foldback to prevent current runaway on a hard short in PWM
mode. When the output voltage at the feedback pin (FB1) falls
lower than 50% of VOUT1 typical, indicating the possibility of a
hard short at the output, the switching frequency is reduced to
half of the internal oscillator frequency. The reduction in the
switching frequency allows more time for the inductor to
discharge, preventing a runaway of output current.
Operation Mode
The buck boost regulator in the ADP5360 is synchronous with
the current mode, switching regulators designed to maintain a
fixed output voltage from an input supply (VIN2) that can be
greater than, equal to, or less than VOUT2.
The buck boost regulator works in hysteresis mode and
regulates the output voltage to a slightly higher value than the
target output voltage with switching pulses. When the output
voltage increases until the output sense signal exceeds the
hysteresis upper threshold, the regulator enters sleep mode. In
sleep mode, the high-side and low-side MOSFET and a majority
of the control circuitry are disabled to allow a low quiescent
current as well as high efficiency performance. During sleep
mode, the output capacitor supplies the energy into the load,
the output voltage decreases until the voltage falls lower than
the hysteresis comparator lower threshold, and the regulator
wakes up and generates the switching pulses to charge the
output again.
Stop Switching
The ADP5360 includes one STP pin that can be configured as a
stop pin to allow the user to temporarily stop the buck regulator
switching.
When applying a logic high level to the STP pin, the corresponding
regulator is forced to stop switching immediately. When
applying a logic low level to the STP pin, the regulator resumes
switching. Note that tens of ns delay time exists from when the
STP signal goes high to when switching fully stops.
The stop signal control is valid only when the regulator is
enabled. Otherwise, the stop signal is ignored.
Program Output Voltages
The ADP5360 buck boost regulator provides output voltage
options from 1.8 V to 2.9 V with a 100 mV step, and 2.95 V
to 5.5 V with 50 mV step, which can be programmed by the
VOUT_BUCKBST[5:0] bits, Address 0x2C, and set via the I2C
interface (see Table 62). The buck boost regulator also provides
a fixed output voltage programmed via the factory fuse.
Using the stop signal for hysteresis mode can generate a power-
good failure due to the slow transient response.
Set the STP_BUCK bit, Register 0x29, low to disable the buck
regulator stop switching feature.
LIMIT BATTERY
CURRENT
BATTERY
CURRENT
For the output voltage settings, the feedback resistor divider is
built in the ADP5360. An ultra low power voltage reference and
an integrated high impedance (50 MΩ typical) feedback divider
network contribute to the low quiescent current.
DC-TO-DC
SWITCHING
NO SWITCHING
Enable and Disable
STP
OUTPUT VOLTAGE
The ADP5360 includes a hardware enable pin (EN2). A logic
high in the EN2 pin starts the buck boost regulator. Because of the
low quiescent current design, it is typical for the regulator to start
switching after a delay of a few milliseconds from when the
EN2 pin pulls high. To avoid unexpected leakage current, do
not pull the EN pin high to the ISOB pin. However, do pull the
EN2 pin high to the VSYS pin with the resistor.
100mA
LOAD
PULSE
LOAD CURRENT
150µs
Figure 54. STP Signal Diagram
The I2C register bit, EN_BUCKBST, Address 0x2B, can also
control the buck boost enable and disable, which are logically
OR’ed with the EN2 pin. For example, set the EN_BUCKBST bit
to low, then use the hardware EN2 pin to control the buck boost
enable and disable, or pull the EN2 pin low, and then set the
EN_BUCKBST bit using the I2C inteface.
Rev. 0 | Page 30 of 60
Data Sheet
ADP5360
The peak current limit is different than the average current
PGOOD Indication
limit on the battery input side. The average battery current is
a factor in different elements including, but not limited to, the
VIN2/VOUT2 relationship, the inductance, the switching
frequency, and the peak current-limit threshold. The average
battery current limit on each buck or buck boost regulator
can be roughly calculated and predicted by these elements.
However, the average current-limit accuracy is difficult to
guarantee due to variations in inductance and switching
frequency. Therefore, a careful calculation must be obtained
if the input source is coming from a weak battery, which
typically has high output impedance.
The VOUT2OK bit, Address 0x2F, indicates whether the buck
boost regulator is working properly. A logic high indicates that
the output voltage of the buck boost regulator is higher than 90%
(typical rising threshold) of the nominal output. When the
regulated output voltage falls lower than 87% (typical falling
threshold) of the nominal output, the VOUT2OK bit goes low.
The VOUT2OK bit status indication can be masked to the
PGOOD1 pin or PGOOD2 pin by setting the PGOODx_MASK
register with the I2C interface.
Soft Start
The ADP5360 buck boost regulator has an internal soft start
function that ramps up the output voltage in a controlled
manner upon startup, thereby limiting the inrush current. This
feature prevents possible input voltage drops when a battery or
a high impedance power source is connected to the input of the
device. The default typical soft start time is 1 ms for the regulator.
Other soft start times (8 ms, 64 ms, and 512 ms) can be
programmed for the ADP5360 by the I2C interface.
Stop Switching
The stop feature also can configure the buck boost regulator with
the STP pin input, which allows the user to temporarily stop
buck boost regulator switching.
When applyin a logic high level to the STP pin, the
corresponding regulator is forced to stop switching
immediately. When applying a logic low level to the STP pin,
the regulator resumes switching. Note that tens of ns delay time
exists from when the STP signal goes high to when switching fully
stops.
Active Discharge
The ADP5360 integrates an optional discharge switch from the
output node to ground. This switch turns on when the associated
regulator is disabled to help discharge the output capacitor
quickly. The typical value of the discharge switch is 255 Ω for the
regulator.
The stop signal control is valid only when the regulator is
enabled. Otherwise, the stop signal is ignored.
Set the STP_BUCKBST bit, Address 0x2B, low to disable the
buck boost regulator stop switching feature.
The active discharge feature can be enabled by setting the
DISCHG_BUCKBST bit, Address 0x2B, high for the buck boost
regulator.
SUPERVISORY
Reset Output
Current-Limit Protection
The ADP5360 provides microprocessor supply voltage supervision
by controlling the reset input of the microprocessor. When the
monitored voltage falls lower than the associated threshold, the
RESET pin asserts correspondingly. Asserting the RESET pin
quickly ensures that the entire system is reset immediately
before any part of the system voltage falls lower than the
recommended operating voltage. The default monitor voltage
is the buck output voltage (VOUT1) and can be selected as
VOUT2 by the I2C interface. The RESET pin monitors both
VOUT1 of the buck and VOUT2 of the buck boost when setting
the VOUT1_RST bit and VOUT2_RST bit of Address 0x2D
both high.
The buck boost regulator in the ADP5360 includes peak current-
limit protection circuitry to limit the amount of positive current
flowing through the high-side MOSFET switch. The peak current
limit on the power switch limits the amount of current that can
flow from the input to the output. The programmable current-
limit threshold feature allows for the use of small size inductors
for low current applications.
Use the BUCKBST_ILIM[2:0] bits, Address 0x2B, via the I2C
interface to program the peak current-limit threshold on the
buck boost regulator. Three bit-programmable options provide
100 mA to 800 mA of peak current limit with a 100 mA step
peak current threshold range. Use the following equation to
find the regulator output current:
I
LOAD2 = VIN2 × IPEAK2/2(VIN2 + VOUT2
where:
LOAD2 is the regulator output current.
IN2 is the regulator input voltage.
PEAK2 is the inductor peak current.
OUT2 is the output voltage.
)
I
V
I
V
Rev. 0 | Page 31 of 60
ADP5360
Data Sheet
If the watchdog timer expires without being reset while in
Manual Reset Input
charger mode, theADP5360 charger assumes there is a software
problem and triggers tSAFE. For more information, see the Safety
Timer section.
The ADP5360 features a manual reset input. When driving the
MR
INT
pin
pin low from high with the deglitch time (tDG), the
asserts an interrupt when the EN_MR_INT bit, Address 0x33, is
MR
set to high. When the
pin transitions from low to high, the
pin output asserts and remains asserted for the duration
of the reset timeout period (tRP) before deasserting. Connect an
MR
SHIPMENT MODE
RESET
The ADP5360 provides optional shipment mode as a default
status after ISOB powers up. During shipment mode, most
function blocks shut down, including the ISOFET and VSYS
output voltages that realize an ultralow shutdown current. In
addition, during shipment mode, the PGOOD1, PGOOD2, and
external pull-up resistor from tthe
a logic high output. To generate a reset, connect an external push-
MR
input to the VDD pin for
button switch between the
pin and ground. Noise immunity
input, and fast transients going in a negative
MR
MR
is provided on the
direction are ignored. A 0.1 μF capacitor between the
RESET
pins have a high output by default.
pin and
Enable shipment mode at initial power up of the ADP5360 by
pulling up the ENSD pin. To disable shipment mode, pull down
the ENSD pin.
ground provides additional noise immunity if required.
VOUT1
tDG
tRP
tRP
In the case where the VBUS voltage goes higher than the UVLO
MR
or the
mode. To re-enter shipment mode, set the EN_SHIPMODE bit,
MR
pin for tSH is pulled down, the ADP5360 exits shipment
RESET
MR
Address 0x36, to high or pull down the
Note that the EN_MR_SD bit, Address 0x2D must be set to
MR
pin for 12 seconds.
MR EXTERNALLY
DRIVEN LOW
tDG
INT
enable the
shipment function.
Figure 55. Manual Reset Timing Diagram
FAULT RECOVERY
When the EN_MR_SD bit, Address 0x2D is set to enable
MR
Before performing fault recovery, ensure that the cause of the
fault is rectified.
shipment mode, pulling down the
12 second time out,and then releasing the
all function blocks, and the ADP5360 then enters shipment
MR
pin for more than a
MR
pin, shuts down
To recover from a fault status, power off the VBUS pin or write
a high to the corresponding bits of the Fault register.
mode. To exit shipment mode, pull the
pin low for tSH, and
THERMAL MANAGEMENT
the ADP5360 restarts with the default factory setting registers.
Thermal Shutdown
Watchdog Timer
The ADP5360 features a shutdown threshold detector. If the die
temperature exceeds TSD, all functions are disabled, and the
TSD110 bit, Address 0x2E, is set. The ADP5360 charger can be
re-enabled when the die temperature drops lower than the TSD
falling limit, and the TSD110 bit is reset. To reset the TSD110
bit, write to the I2C fault register, THERMISTOR_10C
Threshold, Address 0x0D, or cycle the power.
The ADP5360 features a watchdog timer that monitors
microprocessor activity. A timer circuit is cleared with every
write to the RESET_WD bit, Address 0x2D. If the timer counts
RESET
through the preset watchdog timeout period (tWD), a
output asserts. The microprocessor must toggle the
RESET_WD bit to avoid being reset.
RESET
When
is asserted, the watchdog timer clears and does
RESET
not count again until the
output deasserts. To disable
the watchdog timer, set the EN_WD bit, Address 0x2D via the
I2C interface. Note that the watchdog timer is ignored when
RESET
is not activated.
Rev. 0 | Page 32 of 60
Data Sheet
ADP5360
I2C INTERFACE
The ADP5360 includes an I2C-compatible serial interface to
control the battery charging, fuel gauge, buck, and buck boost,
and to read back the system status.
INTERRUPTS
INT
INT
The ADP5360 provides an interrupt output (
interrupt case. During normal operation, the
high using an external pull-up resistor. When an interrupt case
occurs, the ADP5360 pulls the
pin) for an
pin is pulled
I2C ADDRESSES
2
The I2C chip default address is 0x46. Different I2C addresses can
be factory programmable. Having different I2C address options
helps to avoid I2C address conflicts with other I2C slave chipsets
in the system. For different I2C chip address requirements,
contact the local Analog Devices sales or distribution
representative.
INT
pin low to alert the I C host
that an interrupt case has occurred.
INT
Many different interrupt sources can trigger the
pin. By
default, no interrupt sources are configured. To select one or more
INT
interrupt sources to trigger the
pin, set the corresponding bits
to 1 in the INTERRUPT_ENABLE1 and INTERRUPT_ENABLE2
registers.
SDA AND SCL PINS
The ADP5360 has two dedicated I2C interface pins, SDA and SCL.
SDA is an open-drain line for receiving and transmitting data. SCL
is an input line for receiving the clock signal. Pull up these pins to
connect external input and output supplies using external
resistors.
INT
When the
INTERRUPT_FLAG1 and INTERRUPT_FLAG2 registers are
INT
pin is triggered, the corresponding bits in the
set to 1. The interrupt case that triggers the
from the INTERRUPT_FLAG1 and INTERRUPT_FLAG2
registers.
pin is read
Serial data is transferred on the rising edge of SCL. The read
data is generated at the SDA pin in read mode.
To clear an interrupt, write a 1 to the corresponding bit in the
INTERRUPT_FLAG1 and INTERRUPT_FLAG2 registers.
Otherwise, the ADP5360 power recycles. Reading the interrupt
or writing a 0 to the bit does not clear the interrupt.
The subaddress content selects which of the ADP5360 registers
is written to first. The ADP5360 sends an acknowledgement to
the master after the 8-bit data byte is written (see Figure 56 for an
example of the I2C write sequence to a single register). The
ADP5360 increments the subaddress automatically and starts
receiving a data byte at the next register until the master sends
an I2C stop as shown in Figure 56.
0 = WRITE
MASTER STOP
ST
0
0
1
0
1
0
0
0
0
0
0
SP
ADP5360 RECEIVES
DATA
CHIP ADDRESS
SUBADDRESS
Figure 56. I2C Single Register Write Sequence
0 = WRITE
MASTER STOP
ST
0
0
1
0
1
0
0
0
0
0
0
0
0
SP
CHIP ADDRESS
SUBADDRESS
REGISTER N
ADP5360 RECEIVES
DATA TO REGISTER N
ADP5360 RECEIVES
DATA TO REGISTER N + 1
ADP5360 RECEIVES
DATA TO LAST REGISTER
Figure 57. I2C Multiple Register Write Sequence
Rev. 0 | Page 33 of 60
ADP5360
Data Sheet
1 = READ
0 = WRITE
ST
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
ST
0
0
1
0
1
0
0
1
0
1
SP
CHIP ADDRESS
SUBADDRESS
CHIP ADDRESS
ADP5360 SENDS DATA
Figure 58. I2C Single Register Read Sequence
1 = READ
MASTER STOP
0 = WRITE
S
T
S
T
S
P
0
0
1
0
1
0
0
0
0
0
0
0
1
0
1
0
0
1
0
0
0
0
1
CHIP ADDRESS
SUBADDRESS
REGISTER N
CHIP ADDRESS
ADP5360 SENDS
DATA OF REGISTER N
ADP5360 SENDS
DATA OF REGISTER
N + 1
ADP5360 SENDS
DATA OF LAST
REGISTER
Figure 59. I2C Multiple Register Read Sequence
Rev. 0 | Page 34 of 60
Data Sheet
ADP5360
CONTROL REGISTER MAP
Table 17. Register Map
Address Register
(Hex)
Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x00
Manufacture
and Model ID
[7:0]
MANUF[3:0]
MODEL[3:0]
0x01
0x02
0x03
Silicon
Revision
[7:0]
[7:0]
[7:0]
Reserved
REV[3:0]
CHARGER_
VBUS_ILIM
VADPICHG[2:0]
Reserved
VSYSTEM
ILIM[2:0]
ITRK_DEAD[1:0]
CHARGER_
TERMINATION_
SETTING
VTRM[5:0]
0x04
0x05
0x06
0x07
CHARGER_
CURRENT_
SETTING
[7:0]
[7:0]
[7:0]
[7:0]
IEND[2:0]
ICHG[4:0]
CHARGER_
VOLTAGE_
THRESHOLD
DIS_RCH
VRCH[1:0]
VTRK_DEAD[1:0]
VWEAK[2:0]
CHARGER_
TIMER_
SETTING
Reserved
EN_TEND
EN_LDO
EN_CHG_
TIMER
CHG_TMR_PERIOD[1:0]
CHARGER_
FUNCTION_
SETTING
EN_JEITA
VBUS_OV
ILIM_
JEITA_
COOL
Reserved
OFF_ISOFET
EN_EOC
EN_
ADPICHG
EN_CHG
0x08
0x09
0x0A
CHARGER_
STATUS1
[7:0]
[7:0]
[7:0]
ADPICHG
VBUS_ILIM
Reserved
CHARGER_STATUS[2:0]
BAT_CHG_STATUS[2:0]
CHARGER_
STATUS2
THR_STATUS[2:0]
BAT_OV_
STATUS
BAT_UV_
STATUS
BATTERY_
ITHR[1:0]
Reserved
EN_THR
THERMISTOR_
CONTROL
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
THERMISTOR_ [7:0]
60C Threshold
TEMP_HIGH_60[7:0]
TEMP_HIGH_45[7:0]
TEMP_LOW_10[7:0]
TEMP_LOW_0[7:0]
THR_V_LOW[7:0]
THERMISTOR_ [7:0]
45C Threshold
THERMISTOR_ [7:0]
10C Threshold
THERMISTOR_ [7:0]
0C Threshold
THR_VOLTAGE [7:0]
Low
THR_VOLTAGE [7:0]
High
Reserved
Reserved
THR_V_HIGH[11:8]
Battery
[7:0]
ISOFET_
OC_DIS_
HICCUP
OC_CHG_ EN_
HICCUP CHGLB
EN_
BATPRO
Protection
Control
OVCHG
0x12
0x13
Battery
[7:0]
UV_DISCH[3:0]
HYS_UV_DISCH[1:0]
DGT_UV_DISCH[1:0]
Protection
Undervoltage
Setting
Battery
[7:0]
OC_DISCH[2:0]
Reserved
DGT_OC_DISCH[2:0] Reserved
Protection
Overcharge
Setting
Rev. 0 | Page 35 of 60
ADP5360
Data Sheet
Address Register
(Hex)
Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x14
Battery
[7:0]
OV_CHG[4:0]
HYS_OV_CHG[1:0]
DGT_OV_
CHG
Protection
Overvoltage
Setting
0x15
Battery
[7:0]
OC_CHG[2:0]
DGT_OC_CHG[1:0]
Reserved
Protection
Charge
Overcharge
Setting
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
V_SOC_0
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
V_SOC_0[7:0]
V_SOC_5[7:0]
V_SOC_11[7:0]
V_SOC_19[7:0]
V_SOC_28[7:0]
V_SOC_41[7:0]
V_SOC_55[7:0]
V_SOC_69[7:0]
V_SOC_84[7:0]
V_SOC_100[7:0]
BAT_CAP[7:0]
BAT_SOC[6:0]
V_SOC_5
V_SOC_11
V_SOC_19
V_SOC_28
V_SOC_41
V_SOC_55
V_SOC_69
V_SOC_84
V_SOC_100
BAT_CAP
BAT_SOC
Reserved
BAT_
SOCACM_CTL
BATCAP_AGE[1:0]
Reserved
EN_
BATCAP_
TEMP
EN_
BATCAP_
AGE
BATCAP_TEMP[1:0]
0x23
0x24
BAT_
SOCACM_H
[7:0]
[7:0]
BAT_SOCACM[11:4]
BAT_
BAT_SOCACM[3:0]
Reserved
SOCACM_L
0x25
0x26
VBAT_READ_H [7:0]
VBAT_READ[12:5]
VBAT_READ_L
[7:0]
VBAT_READ[4:0]
Reserved
FG_
MODE
0x27
0x28
0x29
0x2A
0x2B
0x2C
FUEL_
[7:0]
SOC_LOW_TH[1:0]
SLP_CURR[1:0]
SLP_TIME[1:0]
EN_FG
EN_BUCK
EN_
GAUGE_MODE
SOC_RESET
[7:0]
SOC_
RESET
BUCK_SS[1:0]
Reserved
Buck Configure [7:0]
BUCK_ILIM[1:0]
BUCK_
MODE
STP_
BUCK
DISCHG_
BUCK
Buck Output
Voltage Setting
[7:0]
[7:0]
[7:0]
BUCK_DLY[1:0]
BUCKBST_SS[1:0]
BUCKBST_DLY[1:0]
VOUT_BUCK[5:0]
Buck Boost
Configure
BUCKBST_ILIM[2:0]
STP_
DISCHG_
BUCKBST BUCKBST
BUCKBST
VOUT_BUCKBST[5:0]
Buck Boost
Output Voltage
Setting
0x2D
0x2E
0x2F
0x30
0x31
Supervisory
Setting
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
VOUT1_
RST
VOUT2_
RST
RESET_
TIME
WD_TIME[1:0]
EN_WD
EN_MR_
SD
RESET_WD
Fault
BAT_UV
BAT_OC
BAT_
CHGOC
BAT_CHGOV
CHG_CMPLT
Reserved
VBUSOK
WD_
TIMEOUT
Reserved TSD110
VOUT2OK VOUT1OK
VOUT2OK_ VOUT1OK_
MASK1
VOUT2OK_ VOUT1OK_
MASK2 MASK2
PGOOD_
STATUS
Reserved
MR_PRESS
BATOK
PGOOD1_
MASK
PG1_REV
PG2_REV
Reserved
Reserved
CHGCMPLT_
MASK1
VBUSOK_
MASK1
BATOK_
MASK1
MASK1
PGOOD2_
MASK
CHGCMPLT_
MASK2
VBUSOK_
MASK2
BATOK_
MASK2
Rev. 0 | Page 36 of 60
Data Sheet
ADP5360
Address Register
(Hex)
Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x32
INTERRUPT_
ENABLE1
[7:0]
EN_
SOCLOW_
INT
EN_
SOCACM_
INT
EN_
ADPICHG_
INT
EN_
BATPRO_INT
EN_THR_
INT
EN_BAT_ EN_CHG_ EN_
INT
INT
VBUS_INT
0x33
INTERRUPT_
ENABLE2
[7:0]
EN_MR_
INT
EN_WD_
INT
EN_
BUCKPG_
INT
EN_
BUCKBSTPG_
INT
Reserved
0x34
0x35
0x36
INTERRUPT_
FLAG1
[7:0]
[7:0]
[7:0]
SOCLOW_
INT
SOCACM_
INT
ADPICHG_
INT
BATPRO_INT
THR_INT
BAT_INT
CHG_INT
VBUS_INT
INTERRUPT_
FLAG2
MR_INT
WD_INT
BUCKPG_
INT
BUCKBSTPG_
INT
Reserved
SHIPMODE
Reserved
EN_
SHIPMODE
Table 18. Manufacturer and Model ID, Address 0x00 Bit Descriptions
Bit(s)
[7:4]
[3:0]
Bit Name
MANUF[3:0]
MODEL[3:0]
Access Default
Description
The 4-bit manufacturer identification bus.
The 4-bit model identification bus.
R
R
0001
0000
Table 19. Silicon Revision, Address 0x01 Bit Descriptions
Bit(s)
[7:4]
[3:0]
Bit Name
Reserved
REV[3:0]
Access Default
Description
Reserved.
R
R
Not applicable
1000
The 4-bit silicon revision identification bus.
Table 20. CHARGER_VBUS_ILIM, Address 0x02 Bit Descriptions
Bit(s) Bit Name Access Default Description
VADPICHG[2:0] R/W 100 = 4.6 V
[7:5]
Adaptive Current Limit to VBUS Voltage Threshold Programming. The current to the
VBUS voltage threshold can be limited to the following programmed values:
010 = 4.4 V.
011 = 4.5 V.
100 = 4.6 V.
101 = 4.7 V.
110 = 4.8 V.
111 = 4.9 V.
Reserved
VSYSTEM
4
3
R
Not applicable
Reserved.
R/W
0 = VTRM + 200 mV
VSYS Voltage Programming.
0 = VTRM + 200 mV.
1 = 5 V.
[2:0]
ILIM[2:0]
R/W
001 = 100 mA
VBUS Pin Input Current-Limit Programming Bus. The current into the VBUS pin
can be limited to the following programmed values:
000 = 50 mA.
001 = 100 mA.
010 = 150 mA.
011 = 200 mA.
100 = 250 mA.
101 = 300 mA.
110 = 400 mA.
111 = 500 mA.
Rev. 0 | Page 37 of 60
ADP5360
Data Sheet
Table 21. CHARGER_TERMINATION_SETTING, Address 0x03 Bit Descriptions
Bit(s) Bit Name
Access Default
Description
[7:2] VTRM[5:0]
R/W
Factory set Termination Voltage Programming Bus. The values of the float voltage can be
programmed by using the following values:
000000 = 3.56 V.
000001 = 3.58 V.
000010 = 3.60 V.
000011 = 3.62 V.
000100 = 3.64 V.
000101 = 3.66 V.
000110 = 3.68 V.
000111 = 3.70 V.
001000 = 3.72 V.
001001 = 3.74 V.
001010 = 3.76 V.
001011 = 3.78 V.
001100 = 3.80 V.
001101 = 3.82 V.
001110 = 3.84 V.
001111 = 3.86 V.
010000 = 3.88 V.
010001 = 3.90 V.
010010 = 3.92 V.
010011 = 3.94 V.
010100 = 3.96 V.
010101 = 3.98 V.
010110 = 4.00 V.
010111 = 4.02 V.
011000 = 4.04 V.
011001 = 4.06 V.
011010 = 4.08 V.
011011 = 4.10 V.
011100 = 4.12 V.
011101 = 4.14 V.
011110 = 4.16 V.
011111 = 4.18 V.
100000 = 4.20 V.
100001 = 4.22 V.
100010 = 4.24 V.
100011 = 4.26 V.
100100 = 4.28 V.
100101 = 4.30 V.
100110 = 4.32 V.
100111 = 4.34 V.
101000 = 4.36 V.
101001 = 4.38 V.
101010 = 4.40 V.
101011 = 4.42 V.
101100 = 4.44 V.
101101 = 4.46 V.
101110 = 4.48 V.
101111 = 4.50 V.
Rev. 0 | Page 38 of 60
Data Sheet
ADP5360
Bit(s) Bit Name
Access Default
Description
110000 = 4.52 V.
110001 = 4.54 V.
110010 = 4.56 V.
110011 = 4.58 V.
110100 = 4.60 V.
110101 = 4.62 V.
110110 = 4.64 V.
110111 to 111111 = 4.66 V.
[1:0]
ITRK_DEAD[1:0] R/W
10 = 5 mA
Trickle and Weak Charge Current Programming Bus. The values of the trickle and weak
charge currents can be programmed by using the following values:
00 = 1 mA.
01 = 2.5 mA.
10 = 5 mA.
11 = 10 mA.
Table 22. CHARGER_CURRENT_SETTING, Address 0x04 Bit Descriptions
Bit(s) Bit Name Access Default
Description
[7:5]
IEND[2:0]
R/W
001 = 5 mA
Termination Current Programming Bus. The values of the termination current can be
programmed by using the following values:
001 = 5 mA.
010 = 7.5 mA.
011 = 12.5 mA.
100 = 17.5 mA.
101 = 22.5 mA.
110 = 27.5 mA.
111 = 32.5 mA.
[4:0]
ICHG[4:0]
R/W
01001 = 100 mA
Fast Charge Current Programming Bus. The values of the constant current charge can
be programmed by using the following values:
00000 = 10 mA.
00001 = 20 mA.
00010 = 30 mA.
00011 = 40 mA.
00100 = 50 mA.
00101 = 60 mA.
00110 = 70 mA.
00111 = 80 mA.
01000 = 90 mA.
01001 = 100 mA.
01010 = 110 mA.
01011 = 120 mA.
01100 = 130 mA.
01101 = 140 mA.
01110 = 150 mA.
01111 = 160 mA.
10000 = 170 mA.
10001 = 180 mA.
10010 = 190 mA.
10011 = 200 mA.
10100 = 210 mA.
10101 = 220 mA.
10110 = 230 mA.
Rev. 0 | Page 39 of 60
ADP5360
Data Sheet
Bit(s) Bit Name Access Default
Description
10111 = 240 mA.
11000 = 250 mA.
11001 = 260 mA.
11010 = 270 mA.
11011 = 280 mA.
11100 = 290 mA.
11101 = 300 mA.
11110 = 310 mA.
11111 = 320 mA.
Table 23. CHARGER_VOLTAGE_THRESHOLD, Address 0x05 Bit Descriptions
Bit(s)
Bit Name
Access
Default
Description
7
DIS_RCH
0 = Enable recharge Recharge Function Disable.
0 = recharge enable.
1 = recharge disable.
[6:5]
[4:3]
VRCH[1:0]
R/W
01 = 120 mV
01 = 2.5 V
Recharge Voltage Programming Bus. The values of the recharge threshold
can be programmed by using the following values:
01 = 120 mV.
10 = 180 mV.
11 = 240 mV.
VTRK_DEAD[1:0]
R/W
R/W
Trickle to Fast Charge Dead Battery Voltage Programming Bus. The values of
the trickle to fast charge threshold can be programmed by using the
following values:
00 = 2.0 V.
01 = 2.5 V.
10 = 2.6 V.
11 = 2.9 V.
[2:0]
VWEAK[2:0]
011 = 3.0 V
Weak Battery Voltage Rising Threshold. The values of the battery voltage
can be programmed by using the following values:
000 = 2.7 V.
001 = 2.8 V.
010 = 2.9 V.
011 = 3.0 V.
100 = 3.1 V.
101 = 3.2 V.
110 = 3.3 V.
111 = 3.4 V.
Table 24. CHARGER_TIMER_SETTING, Address 0x06 Bit Descriptions
Bit(s) Bit Name
Access Default
Description
Reserved
Reserved.
[7:4]
3
R
Not applicable
EN_TEND
R/W
0
When low, this bit disables the charge complete timer (tEND), and a 32 ms
deglitch timer (tDG) remains on this function.
2
EN_CHG_TIMER
R/W
1
When high, the trickle charge timer (tTRK) and the fast charge timer (tCHG) are
enabled. When low, tTRK and tCHG are disabled.
[1:0]
CHG_TMR_PERIOD[1:0] R/W
11
tTRK and tCHG Period.
00 = 15 minutes/150 minutes.
01 = 30 minutes/300 minutes.
10 = 45 minutes/450 minutes.
11 = 60 minutes/600 minutes.
Rev. 0 | Page 40 of 60
Data Sheet
ADP5360
Table 25. CHARGER_FUNCTION_SETTING, Address 0x07 Bit Descriptions
Bit(s) Bit Name
Access
Default
Description
7
EN_JEITA
R/W
0
When low, this bit disables the JEITA Li-Ion temperature battery charging
specification.
6
ILIM_JEITA_COOL
R/W
0
When in temperature cool mode, select the battery charging current.
0 = approximately 50% of programmed charge current.
1 = approximately 10% of programmed charge current.
Reserved
5
4
R/W
R/W
Not applicable Reserved.
OFF_ISOFET
0
When high, ISOFET is forced to turn off, and VSYS is shut down only when the
battery is present.
3
2
1
EN_LDO
R/W
R/W
R/W
1
1
0
When low, the charge LDO is disabled. When high, the charge LDO is enabled.
When high, end of charge is allowed.
EN_EOC
EN_ADPICHG
When high, the VBUS adaptive current-limit function is enabled during charging.
When low, the VBUS adaptive current-limit function is disabled during charging.
0
EN_CHG
R/W
Factory set
When low, charging is disabled. When high and EN_LDO = high, charging is
enabled.
Table 26. CHARGER_STATUS1, Address 0x08 Bit Descriptions
Bit(s) Bit Name Access Default Description
Not applicable When high, this bit indicates that the VBUS voltage is over the threshold of
VVBUS_OK
7
VBUS_OV
R
.
6
5
ADPICHG
R
R
Not applicable When high, this bit indicates that the adaptive charge current is active.
VBUS_ILIM
Not applicable When high, this bit indicates that the current into the VBUS pin is limited by
the high voltage blocking FET and that the charger is not running at the full
programmed ICHG
.
Reserved
[4:3]
[2:0]
R
R
Not applicable Reserved.
CHARGER_STATUS[2:0]
Not applicable Charger Status Bus. The following values are indications for the charger status:
000 = off.
001 = trickle charge.
010 = fast charge (constant current mode).
011 = fast charge (constant voltage mode).
100 = charge complete.
101 = LDO mode.
110 = trickle or fast charge timer expired.
111 = battery detection.
Table 27. CHARGER_STATUS2, Address 0x09 Bit Descriptions
Bit(s) Bit Name
Access Default
Description
[7:5]
THR_STATUS[2:0]
R
Not applicable
THR Pin Status. The following values are indications for the THR pin NTC
resistor value:
000 = off.
001 = battery cold.
010 = battery cool.
011 = battery warm.
100 = battery hot.
111 = thermistor okay.
4
3
BAT_OV_STATUS
BAT_UV_STATUS
R
R
Not applicable
Not applicable
Battery Overvoltage Status.
0 = no battery overvoltage protection.
1 = battery overvoltage protection.
Battery Undervoltage Status.
0 = no battery undervoltage protection.
1 = battery undervoltage protection.
Rev. 0 | Page 41 of 60
ADP5360
Data Sheet
Bit(s) Bit Name
Access Default
Not applicable
Description
[2:0]
BAT_CHG_STATUS[2:0]
R
Battery Status Bus. The following values are indications for battery status:
000 = normal.
001 = no battery.
010 = VBSNS < VTRK_DEAD when in charge.
011 = VTRK ≤ VBSNS < VWEAK when in charge.
100 = VBSNS ≥ VWEAK when in charge.
Table 28. BATTERY_THERMISTOR_CONTROL, Address 0x0A Bit Descriptions
Bit(s) Bit Name Access Default
Description
[7:6]
ITHR[1:0]
R/W
Factory set
Select Battery Thermistor NTC Resistance. The following values are the program values for
the battery thermistor NTC resistance:
00 = 60 μA.
01 = 12 μA.
10, 11 = 6 μA.
Reserved
EN_THR
[5:1]
0
R
Not applicable Reserved.
When high, the ITHR current source is enabled even when the voltage at the VBUS pin is
lower than VVBUS_OK
R/W
0
.
Table 29. THERMISTOR_60C Threshold, Address 0x0B Bit Descriptions
Bit(s)
Bit Name
Access
Default
Description
[7:0]
TEMP_HIGH_60[7:0]
R/W
0x56
Thermistor Voltage Threshold for 60°C.
THERMISTOR_60C Voltage Threshold (V) = (TEMP_HIGH_60 × 0.002) (V)
Table 30. THERMISTOR_45C Threshold, Address 0x0C Bit Descriptions
Bit(s)
Bit Name
Access
Default
Description
[7:0]
TEMP_HIGH_45[7:0]
R/W
0x8F
Thermistor Voltage Threshold for 45°C
THERMISTOR_45C Voltage Threshold (V) = (TEMP_HIGH_45 × 0.002) (V)
Table 31. THERMISTOR_10C Threshold, Address 0x0D Bit Descriptions
Bit(s)
Bit Name
Access
Default
Description
[7:0]
TEMP_LOW_10[7:0]
R/W
0x71
Thermistor Voltage Threshold for 10°C
THERMISTOR_10C Voltage Threshold (V) = (TEMP_LOW_10 × 0.01) (V)
Table 32. THERMISTOR_0C Threshold, Address 0x0E Bit Descriptions
Bit(s)
Bit Name
Access
Default
Description
[7:0]
TEMP_LOW_0[7:0]
R/W
0xB4
Thermistor Voltage Threshold For 0°C
THERMISTOR_0C Voltage Threshold (V) = (TEMP_LOW_0 × 0.01) (V)
Table 33. THR_VOLTAGE Low, Address 0x0F Bit Descriptions
Bit(s)
Bit Name
Access
Default
Description
[7:0]
THR_V_LOW[7:0]
R
Not applicable
8-Bit Thermistor Node Voltage Low (mV)
NTC = THR_V_x[11:0]/ITHR (kΩ)
Table 34. THR_VOLTAGE High, Address 0x10 Bit Descriptions
Bit(s)
[7:4]
[3:0]
Bit Name
Reserved
Access
R
R
Default
Not applicable
Not applicable
Description
Reserved
THR_V_HIGH[11:8]
4-Bit Thermistor Node Voltage High (mV)
NTC = THR_V_x[11:0]/ITHR (kΩ)
Rev. 0 | Page 42 of 60
Data Sheet
ADP5360
Table 35. Battery Protection Control, Address 0x11 Bit Descriptions
Bit(s) Bit Name
Access Default
Description
Reserved
[7:5]
4
R
Not applicable Reserved.
ISOFET_OVCHG
R/W
0
0
When low, ISOFET turns on when the battery charging overvoltage protection is
triggered. When high, the ISOFET turns off when the battery charging overvoltage
protection is triggered.
3
2
OC_DIS_HICCUP
R/W
Battery Discharge Overcurrent Protection Mode Selection.
0 = latch up.
1 = hiccup.
OC_CHG_HICCUP R/W
0
Battery Charge Overcurrent Protection Mode Selection.
0 = latch up.
1 = hiccup.
1
0
EN_CHGLB
EN_BATPRO
R/W
R/W
1
When low, the battery charge is not allowed with the battery undervoltage
protection triggered. When high, the battery charge is allowed with the battery
undervoltage protection triggered.
Factory set
When low, the battery protection function is disabled. When high, the battery
protection function is enabled.
Table 36. Battery Protection Undervoltage Setting, Address 0x12 Bit Descriptions
Bit(s) Bit Name Access Default Description
[7:4]
UV_DISCH[3:0]
R/W
Factory set Battery Undervoltage Protection Threshold. The values of the battery undervoltage
protection threshold can be programmed by using the following values:
0000 = 2.05 V.
0001 = 2.10 V.
0010 = 2.15 V.
0011 = 2.20 V.
0100 = 2.25 V.
0101 = 2.30 V.
0110 = 2.35 V.
0111 = 2.40 V.
1000 = 2.45 V.
1001 = 2.50 V.
1010 = 2.55 V.
1011 = 2.60 V.
1100 = 2.65 V.
1101 = 2.70 V.
1110 = 2.75 V.
1111 = 2.80 V.
[3:2]
[1:0]
HYS_UV_DISCH[1:0] R/W
DGT_UV_DISCH[1:0] R/W
00 = 2%
Battery Undervoltage Protection for Overdischarge Hysteresis. The values of the
battery undervoltage protection can be programmed byusing the following values:
00 = 2% UV_DISCH voltage threshold.
01 = 4% UV_DISCH voltage threshold.
10 = 6% UV_DISCH voltage threshold.
11 = 8% UV_DISCH voltage threshold.
00 = 30 ms
Battery Undervoltage Protection Deglitch Time. The values of the battery
undervoltage protection deglitch time can be programmed by using the following
values:
00 = 30 ms.
01 = 60 ms.
10 = 120 ms.
11 = 240 ms.
Rev. 0 | Page 43 of 60
ADP5360
Data Sheet
Table 37. Battery Protection Overcharge Setting, Address 0x13 Bit Descriptions
Bit(s) Bit Name
Access Default
Description
[7:5]
OC_DISCH[2:0]
R/W Factory set
Battery Overcurrent Protection for Overdischarge Threshold. The values of the
battery overcurrent protection can be programmed by using the following values:
000 = 50 mA.
001 = 100 mA.
010 = 150 mA.
011 = 200 mA.
100 = 300 mA.
101 = 400 mA.
110 = 500 mA.
111 = 600 mA.
Reserved
Reserved
DGT_OC_DISCH[2:0] R/W
4
R
Not applicable
011 = 5 ms
[3:1]
Battery Discharge Overcurrent Protection Deglitch Time Setting. The values of
the battery discharge overcurrent protection can be programmed by using the
following values:
001 = 0.5 ms.
010 = 1 ms.
011 = 5 ms.
100 = 10 ms.
101 = 20 ms.
110 = 50 ms.
111 = 100 ms.
Reserved
Reserved
0
R
Not applicable
Table 38. Battery Protection Overvoltage Setting, Address 0x14 Bit Descriptions
Bit(s) Bit Name Access Default Description
[7:3] OV_CHG[4:0] R/W
Factory set Battery Overvoltage Protection Threshold. The values of the battery overvoltage
protection threshold can be programmed by using the following values:
00000 = 3.55 V.
00001 = 3.60 V.
00010 = 3.65 V.
00011 = 3.70 V.
00100 = 3.75 V.
00101 = 3.80 V.
00110 = 3.85 V.
00111 = 3.90 V.
01000 = 3.95 V.
01001 = 4.00 V.
01010 = 4.05 V.
01011 = 4.10 V.
01100 = 4.15 V.
01101 = 4.20 V.
01110 = 4.25 V.
01111 = 4.30 V.
10000 = 4.35 V.
10001 = 4.40 V.
10010 = 4.45 V.
10011 = 4.50 V.
Rev. 0 | Page 44 of 60
Data Sheet
ADP5360
Bit(s) Bit Name
Access Default
Description
10100 = 4.55 V.
10101 = 4.60 V.
10110 = 4.65 V.
10111 = 4.70 V.
11000 = 4.75 V.
11001 to 11111 = 4.80 V.
[2:1]
HYS_OV_CHG[1:0] R/W
00
Battery Overvoltage Protection for Charge Hysteresis. The values of the battery
overvoltage protection can be programmed by using the following values:
00 = 2% of the voltage of the OV_CHG threshold.
01 = 4% of the voltage of the OV_CHG threshold.
10 = 6% of the voltage of the OV_CHG threshold.
11 = 8% of the voltage of the OV_CHG threshold.
0
DGT_OV_CHG
R/W
0 = 0.5 sec
Battery Overvoltage Protection Deglitch Time. The values of the battery overvoltage
protection deglitch time can be programmed by using the following values:
0 = 0.5 sec.
1 = 1 sec.
Table 39. Battery Protection Charge Overcharge Setting, Address 0x15 Bit Descriptions
Bit(s) Bit Name
Access Default
Description
[7:5]
OC_CHG[2:0]
R/W
Factory set
Battery Overcurrent Protection for Overdischarge Threshold. The values of the
battery overcurrent protection can be programmed by using the following values:
000 = 25 mA.
001 = 50 mA.
010 = 100 mA.
011 = 150 mA.
100 = 200 mA.
101 = 250 mA.
110 = 300 mA.
111 = 400 mA.
[4:3]
[2:0]
DGT_OC_CHG[1:0] R/W
01 = 10 ms
Battery Charge Overcurrent Protection Deglitch Time Setting. The values of the battery
charge overcurrent protection can be programmed byusing the following values:
00 = 5 ms.
01 = 10 ms.
10 = 20 ms.
11 = 40 ms.
Reserved.
Reserved
R
Not applicable
FUEL GAUGE REGISTER BIT DESCRIPTIONS
Table 40. V_SOC_0, Address 0x16 Bit Descriptions
Bit(s)
Bit Name
Access
Default
Description
[7:0]
V_SOC_0[7:0]
R/W
0x7D
Battery Voltage When State of Charge = 0%. The default voltage is 3.5 V.
Battery Voltage (V) = (2.5 + V_SOC_0 × 0.008) (V).
Table 41. V_SOC_5, Address 0x17 Bit Descriptions
Bit(s)
Bit Name
Access
Default
Description
[7:0]
V_SOC_5[7:0]
R/W
0x91
Battery Voltage When State of Charge = 5%. The default voltage is 3.66 V.
Battery voltage (V) = (2.5 + V_SOC_5 × 0.008) (V).
Rev. 0 | Page 45 of 60
ADP5360
Data Sheet
Table 42. V_SOC_11, Address 0x18 Bit Descriptions
Bit(s)
Bit Name
Access
Default
Description
[7:0]
V_SOC_11[7:0]
R/W
0x94
Battery Voltage When State of Charge = 11%. The default voltage is 3.684 V.
Battery voltage (V) = (2.5 + V_SOC_11 × 0.008) (V).
Table 43. V_SOC_19, Address 0x19 Bit Descriptions
Bit(s)
Bit Name
Access
Default
Description
[7:0]
V_SOC_19[7:0]
R/W
0x99
Battery Voltage When State of Charge = 19%. The default voltage is 3.724 V.
Battery voltage (V) = (2.5 + V_SOC_19 × 0.008) (V).
Table 44. V_SOC_28, Address 0x1A Bit Descriptions
Bit(s)
Bit Name
Access
Default
Description
[7:0]
V_SOC_28[7:0]
R/W
0x9E
Battery Voltage When State of Charge = 28%. The default voltage is 3.764 V.
Battery Voltage (V) = (2.5 + V_SOC_28 × 0.008) (V).
Table 45. V_SOC_41, Address 0x1B Bit Descriptions
Bit(s)
Bit Name
Access
Default
Description
[7:0]
V_SOC_41[7:0]
R/W
0xA3
Battery Voltage When State of Charge = 41%. The default voltage is 3.804 V.
Battery Voltage (V) = (2.5 + V_SOC_41 × 0.008) (V).
Table 46. V_SOC_55, Address 0x1C Bit Descriptions
Bit(s)
Bit Name
Access
Default Description
[7:0]
V_SOC_55[7:0]
R/W
0xAB
Battery Voltage When State of Charge = 55%. The default voltage is 3.868 V.
Battery Voltage (V) = (2.5 + V_SOC_55 × 0.008) (V).
Table 47. V_SOC_69, Address 0x1D Bit Descriptions
Bit(s)
Bit Name
Access
Default Description
[7:0]
V_SOC_69[7:0]
R/W
0xB5
Battery Voltage When State of Charge = 69%. The default voltage is 3.948 V.
Battery Voltage (V) = (2.5 + V_SOC_69 × 0.008) (V).
Table 48. V_SOC_84, Address 0x1E Bit Descriptions
Bit(s)
Bit Name
Access
Default Description
[7:0]
V_SOC_84[7:0]
R/W
0xC4
Battery Voltage When State of Charge = 84%. The default voltage is 4.068 V.
Battery Voltage (V) = (2.5 + V_SOC_84 × 0.008) (V).
Table 49. V_SOC_100, Address 0x1F Bit Descriptions
Bit(s)
Bit Name
Access
Default Description
[7:0]
V_SOC_100[7:0]
R/W
0xD5
Battery Voltage When State of Charge = 100%. The default voltage is 4.204 V.
Battery Voltage (V) = (2.5 + V_SOC_100 × 0.008) (V).
Table 50. BAT_CAP, Address 0x20 Bit Descriptions
Bit(s)
Bit Name
Access
Default
Description
[7:0]
BAT_CAP[7:0]
R/W
0x32
Battery Capacity Input
Battery Capacity = (BAT_CAP × 2) mAh
Table 51. BAT_SOC, Address 0x21 Bit Descriptions
Bit(s)
Bit Name
Access
Default
Description
Reserved
Reserved
7
R
R
Not applicable
Not applicable
[6:0]
BAT_SOC[6:0]
Battery State of Charge Output
State of Charge = BAT_SOC %, Only Valued Between 0% to 100%
Rev. 0 | Page 46 of 60
Data Sheet
ADP5360
Table 52. BAT_SOCACM_CTL, Address 0x22 Bit Descriptions
Bit(s) Bit Name
Access Default
Description
[7:6]
BATCAP_AGE[1:0]
R/W
01 = 1.5%
Battery Capacity Reduction Percentage When BAT_SOCACM Overflows.
00 = 0.8 %.
01 = 1.5 %.
10 = 3.1 %.
11 = 6.3 %.
[5:4]
BATCAP_TEMP[1:0] R/W
00 = 0.2%/°C
Battery Capacity Compensation with Temperature Coefficient. The values of the
battery capacity compensation can be programmed by using the following values:
00 = 0.2 %/°C.
01 = 0.4 %/°C.
10 = 0.6 %/°C.
11 = 0.8 %/°C.
Reserved
[3:2]
1
Not applicable Reserved.
EN_BATCAP_TEMP R/W
0
Battery Capacity Temperature Compensation Function Selection.
0 = disable battery capacity temperature compensation.
1 = enable battery capacity temperature compensation.
Battery Capacity Aging Compensation Function Selection.
0 = disable battery capacity aging automatic adjustment.
1 = enable battery capacity aging automatic adjustment.
0
EN_BATCAP_AGE
R/W
0
Table 53. BAT_SOCACM_H, Address 0x23 Bit Descriptions
Bit(s)
Bit Name
Access
Default
Description
[7:0]
BAT_SOCACM[11:4]
R
Not applicable
Highest Eight Bits of an 8-Bit Accumulation of the Charge State
Number of Times for Charging = BAT_SOCACM[11:0]/100
Table 54. BAT_SOCACM_L, Address 0x24 Bit Descriptions
Bit(s)
Bit Name
Access
Default
Description
[7:4]
BAT_SOCACM[3:0]
R
Not applicable
Not applicable
Lowest Four Bits of a 4-Bit Accumulation of the Charge State
Number of Times for Charging = BAT_SOCACM[11:0]/100
Reserved
Reserved
[3:0]
R
Table 55. VBAT_READ_H, Address 0x25 Bit Descriptions
Bit(s)
Bit Name
Access
Default
Description
[7:0]
VBAT_READ[12:5]
R
Not applicable
Battery Voltage Reading of the Highest Eight Bits (mV)
Table 56. VBAT_READ_L, Address 0x26 Bit Descriptions
Bit(s)
[7:3]
[2:0]
Bit Name
VBAT_READ[4:0]
Reserved
Access
R
R
Default
Not applicable
Not applicable
Description
Battery Voltage Reading of the Lowest Five Bits (mV)
Reserved
Table 57. FUEL_GAUGE_MODE, Address 0x27 Bit Descriptions
Bit(s)
Bit Name
Access
Default
Description
[7:6]
SOC_LOW_TH[1:0]
R/W
01 = 11%
Indication of Low State of Charge Threshold
00 = 6%
01 = 11%
10 = 21%
11 = 31%
[5:4]
SLP_CURR[1:0]
R/W
01 = 10 mA
Fuel Gauge Sleep Mode Current Threshold
00 = 5 mA
01 = 10 mA
10 = 20 mA
11 = 40 mA
Rev. 0 | Page 47 of 60
ADP5360
Data Sheet
Bit(s)
Bit Name
Access
Default
Description
[3:2]
SLP_TIME[1:0]
R/W
00 = 1 min
Fuel Gauge Update Rate Of The Sleep Mode
00 = 1 min
01 = 4 min
10 = 8 min
11 = 16 min
1
0
FG_MODE
EN_FG
R/W
R/W
0
0
Fuel Gauge Operation Mode Selection
1 = operate in sleep mode
0 = operate in active mode
Fuel Gauge Function Selection
0 = disable fuel gauge
1 = enable fuel gauge
Table 58. SOC_RESET, Address 0x28 Bit Descriptions
Bit(s) Bit Name Access Default Description
Write 1, then write 0 to refresh the BAT_SOC, VBAT_READ_H, and VBAT_READ_L registers.
Not applicable Reserved.
7
SOC_RESET
Reserved
W
R
0
[6:0]
SWITCHING REGULATOR REGISTER BIT DESCRIPTIONS
Table 59. Buck Configure, Address 0x29 Bit Descriptions
Bit(s)
Bit Name
Access
Default
Description
[7:6]
BUCK_SS[1:0]
R/W
Factory set
Buck Regulator Output Soft Start Time. The values of the soft start
time can be programmed by using the following values:
00 = 1 ms.
01 = 8 ms.
10 = 64 ms.
11 = 512 ms.
[5:4]
BUCK_ILIM[1:0]
R/W
11 = 400 mA
Buck Regulator Peak Current Limit. The values of the peak current
limit can be programmed by using the following values:
00 = 100 mA.
01 = 200 mA.
10 = 300 mA.
11 = 400 mA.
3
2
1
0
BUCK_MODE
STP_BUCK
R/W
R/W
R/W
R/W
Factory set
0 = disable
Factory set
Factory set
Buck Operate Mode Selection.
0 = hystersis mode.
1 = FPWM mode.
Enable Stop Feature to Buck Regulator.
0 = disable pulse stop feature.
1 = enable pulse stop feature.
Configure Output Discharge Functionality for Buck.
0 = disable output discharge function.
1 = enable output discharge function.
Buck Output Control.
DISCHG_BUCK
EN_BUCK
0 = disable buck output.
1 = enable buck output.
Rev. 0 | Page 48 of 60
Data Sheet
ADP5360
Table 60. Buck Output Voltage Setting, Address 0x2A Bit Descriptions
Bit(s) Bit Name
Access Default
Description
[7:6]
BUCK_DLY[1:0]
R/W
00 = 0 μs
Buck Switch Delay Time in Hystersis. The values of the delay time can be programmed
by using the following values:
00 = 0 μs.
01 = 5 μs.
10 = 10 μs.
11 = 20 μs.
[5:0]
VOUT_BUCK[5:0] R/W
Factory set Buck Output Voltage Setting. The values of the voltage setting can be programmed by
using the following values:
000000 = 0.6 V.
000001 = 0.65 V.
…
111111 = 3.75 V.
Table 61. Buck Boost Configure, Address 0x2B Bit Descriptions
Bit(s) Bit Name
Access Default
Description
[7:6]
BUCKBST_SS[1:0]
R/W
Factory set
Buck Boost Regulator Output Soft Start Time. The values of the start time can be
programmed byusing the following values:
00 = 1 ms.
01 = 8 ms.
10 = 64 ms.
11 = 512 ms.
[5:3]
BUCKBST_ILIM[2:0] R/W
011 = 400 mA
Buck Boost Regulator Peak Current Limit. The values of the peak current limit can
be programmed by using the following values:
000 = 100 mA.
001 = 200 mA.
010 = 300 mA.
011 = 400 mA.
100 = 500 mA.
101 = 600 mA.
110 = 700 mA.
111 = 800 mA.
2
1
0
STP_BUCKBST
R/W
0 = disable
Factory set
Factory set
Enable Stop Feature to Buck Boost Regulator.
0 = disable pulse stop feature.
1 = enable pulse stop feature.
Configure Output Discharge Functionality for Buck Boost.
0 = disable output discharge function.
1 = enable output discharge function.
Buck Boost Output Control.
0 = disable buck boost output.
1 = enable buck boost output.
DISCHG_BUCKBST R/W
EN_BUCKBST
R/W
Table 62. Buck Boost Output Voltage Setting, Address 0x2C Bit Descriptions
Bit(s) Bit Name
Access Default
Description
[7:6] BUCKBST_DLY[1:0]
R/W 00 = 0 μs
Buck Boost Switch Delay Time in Hystersis. The values of the delay time can be
programmed by using the following values:
00 = 0 μs.
01 = 5 μs.
10 = 10 μs.
11 = 20 μs.
Rev. 0 | Page 49 of 60
ADP5360
Data Sheet
Bit(s) Bit Name
Access Default
Description
[5:0]
VOUT_BUCKBST[5:0] R/W
Factory set Buck Boost Output Voltage Setting. The values of the voltage setting can be
programmed by using the following values:
000000 = 1.8 V with 100 mV step.
000001 = 1.9 V with 100 mV step.
…
001011 = 2.9 V with 100 mV step.
001100 = 2.95 V with 50 mV step.
…
111111 = 5.5 V with 50 mV step.
SUPERVISORY REGISTER BIT DESCRIPTIONS
Table 63. Supervisory Setting, Address 0x2D Bit Descriptions
Bit(s) Bit Name
Access Default
Description
7
6
5
VOUT1_RST
VOUT2_RST
RESET_TIME
R/W
R/W
R/W
1
Buck Output Voltage Monitor to
Selection.
RESET
0 = disable buck voltage monitor to
1 = enable buck voltage monitor to
.
RESET
.
RESET
0
Buck Boost Output Voltage Monitor to
Selection.
RESET
0 = disable buck boost voltage monitor to
1 = snable buck boost voltage monitor to
.
RESET
.
RESET
0 = 200 ms
Timeout Period Selection. The values of the period selection can be programmed
RESET
by using the following values:
0 = 200 ms.
1 = 1.6 sec.
[4:3]
WD_TIME[1:0] R/W
00 = 12.5 sec Watchdog Timeout Period Selection. The values of the period selection can be
programmed by using the following values:
00 = 12.5 sec.
01 = 25.6 sec.
10 = 50 sec.
11 = 100 sec.
2
1
EN_WD
R/W
R/W
0 = disable
0 = disable
When high, the watchdog timer function is enabled. When low, the watchdog timer
function is disabled.
EN_MR_SD
When high, the device enters shipment mode after
presses low for 12 sec. When
MR
low, disable
to enter shipment mode.
MR
0
RESET_WD
W
0
When high, the watchdog safety timer resets. The RESET_WD bit is reset automatically.
STATUS AND FAULT REGISTER BIT DESCRIPTIONS
Table 64. Fault, Address 0x2E Bit Descriptions1
Bit(s) Bit Name
Access Default
Description
7
6
5
4
3
2
1
0
BAT_UV1
R/W
R/W
R/W
R/W
R
0
0
0
0
When high, this bit indicates that the battery is undervoltage when overdischarging.
When high, this bit indicates that the battery is overcurrent during overdischarge.
When high, this bit indicates that the battery is overcurrent during overcharge.
When high, this bit indicates that the battery is overvoltage during overcharge.
BAT_OC1
BAT_CHGOC1
BAT_CHGOV1
Reserved
WD_TIMEOUT1 R/W
Reserved
TSD1101
Not applicable Reserved.
0
0
0
When high, watchdog timeout occurred.
Reserved.
R/W
R/W
When high, the temperature shutdown fault occurs.
1 To reset the fault bits in the fault register, cycle power on the VBUS pin or write high to the corresponding bits of the fault register.
Rev. 0 | Page 50 of 60
Data Sheet
ADP5360
Table 65. PGOOD_STATUS Register, Address 0x2F Bit Descriptions
Bit(s) Bit Name
Access Default
Description
Reserved
[7:6]
5
R
R
R
Not applicable Reserved.
MR_PRESS
CHG_CMPLT
Not applicable When high, this bit indicates that the
pin is pulled to low after tDG.
MR
4
Not applicable This bit shows battery charge complete.
0 = the charger is not in charge complete status.
1 = the charger is in charge complete status.
3
2
VBUSOK
BATOK
R
R
Not applicable This bit shows the real-time status of the VBUS pin voltage.
0 = the voltage of the VBUS pin is lower than VVBUS_OK or higher than VVBUS_OV
1 = the voltage of the VBUS pin is higher than VVBUS_OK and lower than VVBUS_OV
.
.
Not applicable This bit shows the real-time status of the battery voltage. This bit is only active when
the fuel gauge function is enabled.
0 = battery voltage is less than VWEAK
.
1 = battery voltage is more than VWEAK
.
1
0
VOUT2OK
VOUT1OK
R
R
Not applicable This bit shows real-time power good status for the buck boost regulator. This bit is only
effective in buck boost standalone fixed output mode.
0 = buck boost regulator power-good status is low.
1 = buck boost regulator power-good status is high.
Not applicable This bit shows real-time power-good status for the buck regulator. This bit is not
effective if the buck is configured as load switch mode.
0 = buck power-good status is low.
1 = buck power-good status is high.
Table 66. PGOOD1_MASK Register, Address 0x30 Bit Descriptions
Bit(s) Bit Name
Access
Default
Description
7
PG1_REV
R/W
Factory set
This bit configures the active low output of the PGOOD1 pin.
0 = disable active low.
1 = enable active low.
Reserved
[6:5]
4
Not applicable Reserved.
CHGCMPLT_MASK1 R/W
0
This bit configures the external PGOOD1 pin.
0 = does not send the output charger complete signal to the external PGOOD1 pin.
1 = sends the output charger complete signal to the external PGOOD1 pin.
This bit configures the external PGOOD1 pin.
0 = does not send the output VBUS voltage status signal to the external PGOOD1 pin.
1 = sends the output VBUS voltage status signal to the external PGOOD1 pin.
This bit configures the external PGOOD1 pin.
0 = does not send the output battery voltage okay signal to the external PGOOD1 pin.
1 = sends the output battery voltage okay signal to the external PGOOD1 pin.
This bit configures the external PGOOD1 pin for buck boost output.
0 = does not send the output buck boost PGOOD signal to the external PGOOD1 pin.
1 = sends the output buck boost PGOOD signal to the external PGOOD1 pin.
3
2
1
0
VBUSOK_MASK1
BATOK_MASK1
R/W
R/W
R/W
R/W
Factory set
0
VOUT2OK_MASK1
VOUT1OK_MASK1
0
Factory set
This bit configures the external PGOOD1 pin. This bit is not effective if the buck
is configured in load switch mode.
0 = does not send the output buck PGOOD signal to the external PGOOD1 pin.
1 = sends the output buck PGOOD signal to the external PGOOD1 pin.
Rev. 0 | Page 51 of 60
ADP5360
Data Sheet
Table 67. PGOOD2_MASK Register, Address 0x31 Bit Descriptions
Bit(s) Bit Name
Access Default
Description
7
PG2_REV
R/W
0
This bit configures the active low output of the PGOOD2 pin output.
0 = disable active low.
1 = enable active low.
Reserved
[6:5]
4
Not applicable
0
Reserved.
CHGCMPLT_MASK2 R/W
This bit configures the external PGOOD2 pin.
0 = does not send the output charger complete signal to the external PGOOD2 pin.
1 = sends the output charger complete signal to the external PGOOD2 pin.
This bit configures the external PGOOD2 pin.
0 = does not send the output VBUS voltage status signal to the external
PGOOD2 pin.
3
2
VBUSOK_MASK2
BATOK_MASK2
R/W
R/W
0
0
1 = sends the output VBUS voltage status signal to the external PGOOD2 pin.
This bit configures the external PGOOD2 pin.
0 = does not send the output battery voltage okay signal to the external
PGOOD2 pin.
1 = sends the output battery voltage okay signal to the external PGOOD2 pin.
This bit configures the external PGOOD2 pin for buck boost output.
0 = does not send the output buck boost PGOOD signal to the external PGOOD2 pin.
1 = sends the output buck boost PGOOD signal to the external PGOOD2 pin.
1
0
VOUT2OK_MASK2
VOUT1OK_MASK2
R/W
R/W
0
0
This bit configures the external PGOOD2 pin. This bit is not effective if the buck
is configured in load switch mode.
0 = does not send the output buck PGOOD signal to the external PGOOD2 pin.
1 = sends the output buck PGOOD signal to the external PGOOD2 pin.
Table 68. INTERRUPT_ENABLE1 Register, Address 0x32 Bit Descriptions
Bit(s)
Bit Name
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
Description
7
6
5
4
3
2
1
0
EN_SOCLOW_INT
EN_SOCACM_INT
EN_ADPICHG_INT
EN_BATPRO_INT
EN_THR_INT
0
0
0
0
0
0
0
0
When high, the battery low state of the charge interrupt is allowed.
When high, the state of e tcharge accumulation interrupt is allowed.
When high, the VBUS adaptive charge current-limit interrupt is allowed.
When high, the battery protection interrupt is allowed.
When high, the THR temperature threshold interrupt is allowed.
When high, the battery voltage threshold interrupt is allowed.
When high, the charger mode change interrupt is allowed.
When high, the VBUS pin voltage threshold interrupt is allowed.
EN_BAT_INT
EN_CHG_INT
EN_VBUS_INT
Table 69. INTERRUPT_ENABLE2 Register, Address 0x33 Bit Descriptions
Bit(s)
Bit Name
Access
Default
Description
7
EN_MR_INT
R/W
0
When high, the
press interrupt is allowed.
MR
6
EN_WD_INT
R/W
0
When high, the watchdog alarm interrupt is allowed.
When high, the VOUT1OK change interrupt is allowed.
When high, the VOUT2OK change interrupt is allowed.
Reserved.
5
EN_BUCKPG_INT
EN_BUCKBSTPG_INT
Reserved
R/W
0
4
R/W
0
[3:0]
R/W
Not applicable
Rev. 0 | Page 52 of 60
Data Sheet
ADP5360
Table 70. INTERRUPT_FLAG1 Register, Address 0x34 Bit Descriptions
Bit(s) Bit Name
Access Default
Description
7
6
SOCLOW_INT1
R
R
Not applicable
When high, this bit indicates an interrupt caused by low battery voltage.
SOCACM_INT1
ADPICHG_INT
BATPRO_INT1
Not applicable
Not applicable
Not applicable
When high, this bit indicates an interrupt caused by state of charge accumulation to
4096 points and an overflow of points.
5
4
R
R
When high, this bit indicates an interrupt caused by VBUS input current-limit
adaptive regulation.
When high, this bit indicates an interrupt caused by battery protection triggered with
battery fault events.
3
2
1
0
THR_INT1
BAT_INT1
CHG_INT1
VBUS_INT1
R
R
R
R
Not applicable
Not applicable
Not applicable
Not applicable
When high, this bit indicates an interrupt caused by THR temperature thresholds.
When high, this bit indicates an interrupt caused by battery voltage thresholds.
When high, this bit indicates an interrupt caused by a charger mode change.
When high, this bit indicates an interrupt caused by VBUS voltage threshold.
1 When reading the register, the interrupt bit resets automatically.
Table 71. INTERRUPT_FLAG2 Register, Address 0x35 Bit Descriptions
Bit(s)
7
Bit Name
Access
Default
Description
MR_INT1
R
R
R
R
R
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
When high, this bit indicates an interrupt caused by the
press.
MR
6
WD_INT1
When high, this bit indicates an interrupt caused by the watchdog alarm.
When high, this bit indicates an interrupt caused by a VOUT1OK trigger.
When high, this bit indicates an interrupt caused by a VOUT2OK trigger.
Reserved.
5
BUCKPG_INT1
BUCKBSTPG_INT1
Reserved
4
[3:0]
1 When reading the register, the interrupt bit resets automatically.
Table 72. SHIPMODE Register, Address 0x36 Bit Descriptions
Bit(s) Bit Name
Access Default
Description
Reserved
[7:1]
0
R
Not applicable Reserved.
EN_SHIPMODE R/W
0
When high, the ADP5360 enters shipment mode. When low, shipment mode is disabled.
Rev. 0 | Page 53 of 60
ADP5360
Data Sheet
APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUITS
VSYS
USB
5V
VIN1
SW1
VBUS
VDD
ADP5360
C5
C1
2.2µF
L1
4.7µH
VOUT1
VBUS PROTECTION
LOW IQ
BUCK
10µF
C2
LDO FET
1µF
REGULATOR
C6
10µF
AGNDx
VSYS
PGND1
FB1
VSYS
320mA
LINEAR CHARGER
CONTROL
AND
C3
10µF
VID1
VIN2
VSYS
C7
ISOB
BATTERY
C4
10µF
10µF
PROTECTION
AND
SW2A
BSNS
FUEL GAUGE
PGND2
LOW IQ
BUCK BOOST
REGULATOR
L2
4.7µH
LI-ION
BATTERY
(100mAh)
THR
SW2B
VOUT2
C8
ILIM
ICS
VOUT2
EN2
10µF
EN1
STP
ENCHG
SCL
PGOOD1 MCU
PGOOD2
2
MCU
SDA
INT
I C
INTERFACE
CONTROL
LOGIC
RESET
MR
VDD
R9
ENSD
Figure 60. ADP5360 Application Diagram
VSYS
USB
5V
VIN1
SW1
VBUS
ADP5360
MEMS
MCU
C5
L1
VDD
C1
2.2µF
VBUS PROTECTION
LOW IQ
BUCK
10µF
4.7µH
VDD
AGNDx
VSYS
LDO FET
VOUT1
C2
1µF
REGULATOR
C6
10µF
PGND1
FB1
VSYS
300mA
LINEAR CHARGER
CONTROL
AND
R3
VID1
VIN2
VSYS
C7
C3
10µF
36kΩ
BATTERY
ISOB
PROTECTION
AND
C4
10µF
10µF
SW2A
BSNS
FUEL GAUGE
PGND2
LOW IQ
BUCK BOOST
REGULATOR
L2
4.7µH
LI-ION
THR
BATTERY
(100mAh)
SW2B
R1
15kΩ
ILIM
ICS
VOUT2
C8
VOUT2
EN2
OPTICAL
AFE
VSYS
MCU
R2
68kΩ
10µF
EN1
ENCHG
SCL
STP
PGOOD1
PGOOD2
2
MCU
SDA
INT
I C
INTERFACE
CONTROL
LOGIC
RESET
MR
VDD
R9
ENSD
1MΩ
Figure 61. Li-Ion Battery Charger Application in Healthcare Portable
Rev. 0 | Page 54 of 60
Data Sheet
ADP5360
Buck Input Capacitor Selection
EXTERNAL COMPONENTS
An input capacitor is required to reduce the input voltage ripple,
input ripple current, and source impedance. Place the input
capacitor as close as possible to the VIN1 pin. Use the following
equation to determine the rms input current:
VBUS Capacitor Selection
According to the USB specification, USB peripherals have a
detectable change in capacitance on VBUS when VBUS is
attached. The peripheral device VBUS bypass capacitance must be
at least 1 μF but not larger than 10 μF. The combined capacitance
for the VBUS pin and the VDD pin must not exceed 10 μF at
any temperature or dc bias condition. Suggested VBUS
capacitors are shown in Table 73.
VOUT
V −VOUT
IN
(
)
IRMS ≥ ILOAD(MAX )
VIN
For most applications, the VIN1 pin ties together with the VSYS
pin. The VSYS capacitance is effective, therefore, a 1 µF capacitor
is sufficient for the VIN1 pin. The input capacitor can be
increased without any limit for better input voltage filtering.
Suggested VIN1 capacitors are show in Table 75.
Table 73. Suggested VBUS Capacitors
Vendor Product Number
Murata GRM155R61E225ME15D 2.2
Yageo CC0402MRX5R8BB225 2.2
Value (µF) Voltage (V) Size
25
25
0402
0402
Buck Inductor Selection
VDD Capacitor Selection
The high switching frequency of the ADP5360 buck converter
allows the selection of small chip inductors when the buck
operates in FPWM mode.
The internal supply voltage of the ADP5360 is equipped with a
noise suppressing capacitor at VDD. Use typical VDD
capacitance (1 μF). However, do not exceed 10 μF during
operation. Do not connect any external voltage source, any
resistive load, or any other current load to VDD. Suggested
VDD capacitors are shown in Table 74.
Use the following equation to calculate the peak-to-peak
inductor current ripple (IRIPPLE1):
IRIPPLE1 = VOUT1 × ((VIN1 − VOUT1))/(VIN1 × fSW × L1)
where:
Table 74. Suggested VDD Capacitors
V
V
OUT1 is the buck output voltage.
IN1 is the buck input voltage at the VIN1 node.
Vendor Product Number
Value (µF) Voltage (V) Size
Murata GRM155R60J105KE19D
1
1
6.3
6.3
0402
0402
fSW is the buck switching frequency.
Yageo
CC0402KRX5R5BB105
L1 is the buck output inductor value.
VSYS Capacitor Selection
The minimum dc current rating of the inductor must be greater
than the inductor peak current (IPEAK1). To calculate IPEAK1, use
the following equation:
To guarantee the performance of the charger in various operation
modes, including trickle charge, constant current charge, and
constant voltage charge, it is imperative that the effects of dc bias,
temperature, and tolerances on the behavior of the capacitors be
evaluated for each application. The total VSYS capacitance
consists of all capacitors when VSYS is tied together with the
input node of the buck and buck boost regulators.
IPEAK1 = ILOAD1(MAX) + IRIPPLE1
where ILOAD(MAX) is the output current load.
Inductor conduction losses are caused by the flow of current
through the inductor, which has an associated internal dc
resistance (DCR). Larger inductors have smaller DCR values
that can decrease inductor conduction losses. Inductor core
losses are related to the magnetic permeability of the core material.
Because the buck regulators are high switching frequency dc-to-
dc converters, shielded ferrite core material is recommended for
low core losses and low electromagnetic interference (EMI).
The VSYS capacitance must be ≥10 μF. Suggested VSYS
capacities are shown in Table 75.
Table 75. Suggested VSYS, ISOB, VIN1, VIN2, VOUT1, and
VOUT2 Capacitors
Vendor Product Number
Value (µF) Voltage (V) Size
Murata
Yageo
GRM155R60J106ME44D 10
CC0402MRX5R5BB106 10
6.3
6.3
0402
0402
Suggested buck inductors are shown in Table 76.
Buck Output Capacitor Selection
ISOB Capacitor Selection
Output capacitance is required to minimize the output voltage
overshoot and undershoot and to minimize the output ripple
significantly both in hysteresis mode and FPWM mode.
Capacitors with low equivalent series resistance (ESR) values
produce the lowest output ripple in FPWM mode.
The ISOB effective capacitance must be ≥4.7 μF at any point during
operation. Typically, a nominal capacitance of 10 μF is required to
fulfill the condition at all points of operation. Suggestions for an
ISOB capacitor are show in Table 75.
Suggested buck output capacitors are shown in Table 75.
Rev. 0 | Page 55 of 60
ADP5360
Data Sheet
Buck Boost Input Capacitor Selection
Buck Boost Inductor Selection
An input capacitor is required to reduce the input voltage ripple,
input ripple current, and source impedance. Place the input
capacitor as close as possible to the VIN2 pin.
Inductor conduction losses are caused by the flow of current
through the inductor, which has an associated internal DCR.
Larger inductors have smaller DCR values that can decrease
inductor conduction losses. Inductor core losses are related to
the magnetic permeability of the core material.
For most applications, the VIN2 pin ties together with the VSYS
pin. The VSYS capacitance is effective, therefore, a 1 μF capacitor
is sufficient for the VIN2 pin. The input capacitor can be
increased without any limit for better input voltage filtering.
Suggested VIN2 capacitors are show in Table 75.
Suggested buck boost inductors are shown in Table 76.
Buck Boost Output Capacitor Selection
Output capacitance is required to minimize the output voltage
overshoot and undershoot and to minimize the output ripple
significantly in hysteresis mode.
Suggested buck boost output capacitors are shown in Table 75.
Table 76. Recommended Inductors
Vendor
Wurth
TDK
Model
74479776247A
MLP2016H4R7
Inductance (μH)
4.7
4.7
Dimensions (mm)
2.0 × 1.6 × 1.0
2.0 × 1.6 × 0.85
DCR (mΩ)
140
160
Rated Current (IR) (A)
1.2
1.1
Rev. 0 | Page 56 of 60
Data Sheet
ADP5360
PCB LAYOUT GUIDELINES
Poor layout can affect ADP5360 performance, causing EMI and
electromagnetic compatibility (EMC) problems, ground bounce,
and voltage losses, as well as affect regulation and stability. A
good layout is implemented using the following guidelines:
•
•
Use a dedicated trace to connect the BSNS pin to the
battery pack output node for accurate sensing of the
battery voltage.
Use 0603 size or 0402 size resistors and capacitors to
achieve the smallest possible footprint solution on boards
where space is limited.
•
Place the decoupling capacitor, inductor, input capacitor,
and output capacitor as close as possible to the ADP5360.
Use a ground plane with several vias connecting to the
component side ground to further reduce noise
interference on sensitive circuit nodes.
•
VOUT2
C8
10µF
6.3V/X5R
0402
L2
4.7µH
0806
TO MCU
6
5
4
3
2
1
PGND2
SW2B VOUT2
SCL
SDA
INT
A
TO
BATTERY
SW2A AGND ENSD
EN2 PGOOD1 THR
PGOOD2 BSNS
C7
10µF
6.3V/X5R
0402
B
C
C4
10µF
VIN2
FB1
STP
6.3V/X5R
0402
ISOB
VSYS
ADP5360
VID1
5mm
ISOB
VSYS
ILIM
ICS
D
E
F
SW1
EN1
RESET
ENCHG
MR
C3
10µF
6.3V/X5R
0402
L1
4.7µH
0806
PGND1 VIN1
VDD
VBUS
AGND
C1
2.2µF
25V/X5R
0402
PGND
C6
10µF
6.3V/X5R
0402
C5
10µF
6.3V/X5R
0402
C2
1µF
6.3V/X5R
0402
VBUS
VOUT1
PGND
7mm
TOP LAYER
BOTTOM LAYER
Figure 62. Recommend Layout
Rev. 0 | Page 57 of 60
ADP5360
Data Sheet
FACTORY-PROGRAMMABLE OPTIONS
Table 77. Fuse-Programmable Trim Options for the Different Modes of the ADP5360
Parameter
I2C Address
Value
0x46
Default Setting
0x46
0x56
0x66
0x76
EN_CHG
ITHR
Enable charger
Disable charger
Disable charger
60 μA
60 μA
12 μA
6 μA
VTRM
3.96 V
4.16 V
4.06 V
4.16 V
4.26 V
4.36 V
4.36 V
4.46 V
4.46 V
EN_BATPRO
UV_DISCH
Disable battery protection function
Enable battery protection function
Enable battery protection function
2.5 V
2.2 V
2.5 V
2.6 V
2.8 V
OC_DISCH
OV_CHG
OC_CHG
100 mA
200 mA
400 mA
600 mA
600 mA
4.30 V
4.25 V
4.30 V
4.40 V
4.50 V
100 mA
150 mA
150 mA for the ADP5360ACBZ-1-R7 and 400 mA for
the ADP5360ACBZ-2-R7
200 mA
400 mA
EN_BUCK
BUCK_SS
Disable buck output
Enable buck output
Enable buck output
1 ms
1 ms
8 ms
64 ms
512 ms
BUCK_MODE
Hystersis mode
Hystersis mode
FPWM mode
DISCHG_BUCK
Disable output discharge function
Enable output discharge function
Disable output discharge function
Rev. 0 | Page 58 of 60
Data Sheet
ADP5360
Parameter
Value
Default Setting
VOUT_BUCK
1.0 V
1.2 V
1.2 V for the ADP5360ACBZ-1-R7 and 1.8 V for the
ADP5360ACBZ-2-R7
1.5 V
1.8 V
2.5 V
2.8 V
3.0 V
3.3 V
EN_BUCKBST
BUCKBST_SS
Disable buck boost output
Enable buck boost output
Disable buck boost output
1 ms
1 ms
8 ms
64 ms
512 ms
DISCHG_BUCKBST Disable output discharge function
Enable output discharge function
Disable output discharge function
VOUT_BUCKBST
2.5 V
3.3 V
3.3 V for the ADP5360ACBZ-2-R7 and 5.0 V for the
ADP5360ACBZ-1-R7
3.6 V
4.0 V
4.2 V
4.6 V
5.0 V
5.5 V
PG1_REV
Disable PGOOD1 pin output active low
Enable PGOOD1 pin output active low
Disable PGOOD1 pin output active low
VBUSOK_MASK1
Do not output the VVBUS voltage status signal to the external
PGOOD1 pin
Do not output the VVBUS voltage status signal to the
external PGOOD1 pin
Output the VVBUS voltage status signal to the external PGOOD1 pin
VOUT1OK_MASK1
Do not output the buck PGOOD signal to the external
PGOOD1 pin
Do not output the buck PGOOD signal to the
external PGOOD1 pin
Output the buck PGOOD signal to the external PGOOD1 pin
Rev. 0 | Page 59 of 60
ADP5360
Data Sheet
OUTLINE DIMENSIONS
2.600
2.560
2.520
BOTTOM VIEW
(BALL SIDE UP)
6
5
4
3
2
1
A
B
C
D
E
F
BALL A1
IDENTIFIER
2.00
REF
0.40
BSC
TOP VIEW
(BALL SIDE DOWN)
0.330
0.300
0.270
0.560
0.500
0.440
SIDE VIEW
COPLANARITY
0.04
0.300
0.200
0.170
SEATING
PLANE
0.230
0.200
0.170
Figure 63. 32-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
32-Ball Wafer Level Chip Scale Package [WLCSP]
32-Ball Wafer Level Chip Scale Package [WLCSP]
Package Option
CB-32-2
CB-32-2
ADP5360ACBZ-1-R7
ADP5360ACBZ-2-R7
ADP5360CB-EVALZ
Evaluation Board Assembled with ADP5360ACBZ-1-R7
1 Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D20499-0-11/19(0)
Rev. 0 | Page 60 of 60
相关型号：
ADP5501ACPZ-RL
SPECIALTY ANALOG CIRCUIT, QCC24, 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-2, LFCSP-24
ROCHESTER
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