ADPD106_技术文档

Photometric Front Ends

Data Sheet

ADPD105/ADPD106/ADPD107

FEATURES

GENERAL DESCRIPTION

Multifunction photometric front end

The ADPD105/ADPD106/ADPD107 are highly efficient,

photometric front ends, each with an integrated 14-bit analog-

to-digital converter (ADC) and a 20-bit burst accumulator that

works with flexible light emitting diode (LED) drivers. The

accumulator is designed to stimulate an LED and measure

the corresponding optical return signal. The data output and

functional configuration occur over a 1.8 V I²C interface on the

ADPD105 or SPI on the ADPD106 and ADPD107. The control

circuitry includes flexible LED signaling and synchronous

detection.

Fully integrated AFE, ADC, LED drivers, and timing core

Enables best-in-class ambient light rejection capability

without the need for photodiode optical filters

Three 370 mA LED drivers

Flexible, multiple, short LED pulses per optical sample

20-bit burst accumulator enabling 20 bits per sample period

On-board sample to sample accumulator, enabling up to

27 bits per data read

Low power operation

SPI, I²C interface, and 1.8 V analog/digital core

Flexible sampling frequency ranging from 0.122 Hz to 3820 Hz

FIFO data operation

The analog front end (AFE) features best-in-class rejection of signal

offset and corruption due to modulated interference commonly

caused by ambient light.

APPLICATIONS

Couple the ADPD105/ADPD106/ADPD107 with a low

capacitance photodiode of <100 pF for optimal performance.

The ADPD105/ADPD106/ADPD107 can be used with any LED.

The ADPD105 is available in a 2.46 mm × 1.4 mm WLCSP and a

4 mm × 4 mm LFCSP. The SPI only versions, ADPD106 and

ADPD107, are available in a 2.46 mm × 1.4 mm WLCSP.

Wearable health and fitness monitors

Clinical measurements, for example, SpO₂

Industrial monitoring

Background light measurements

Rev. A

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ADPD105/ADPD106/ADPD107

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

LED Driver Pins and LED Supply Voltage.............................. 31

LED Driver Operation............................................................... 31

Determining the Average Current ........................................... 31

Determining C_VLED..................................................................... 32

LED Inductance Considerations.............................................. 32

Recommended Start-Up Sequence .......................................... 33

Reading Data............................................................................... 33

Clocks and Timing Calibration................................................ 34

Optional Timing Signals Available on GPIO0 and GPIO1 .. 35

Calculating Current Consumption.......................................... 37

Optimizing SNR per Watt......................................................... 38

Applications....................................................................................... 1

General Description......................................................................... 1

Revision History ............................................................................... 3

Functional Block Diagrams............................................................. 4

Specifications..................................................................................... 6

Temperature and Power Specifications ..................................... 6

Performance Specifications......................................................... 7

Analog Specifications................................................................... 8

Digital Specifications ................................................................... 9

Timing Specifications ................................................................ 10

Absolute Maximum Ratings.......................................................... 12

Thermal Resistance .................................................................... 12

Recommended Soldering Profile ............................................. 12

ESD Caution................................................................................ 12

Pin Configurations and Function Descriptions ......................... 13

Typical Performance Characteristics ........................................... 17

Theory of Operation ...................................................................... 19

Introduction................................................................................ 19

Dual Time Slot Operation......................................................... 19

Time Slot Switch......................................................................... 20

Adjustable Sampling Frequency............................................... 22

State Machine Operation........................................................... 23

Normal Mode Operation and Data Flow................................ 23

AFE Operation............................................................................ 25

AFE Integration Offset Adjustment......................................... 25

I²C Serial Interface...................................................................... 27

SPI Port ........................................................................................ 28

Typical Connection Diagram ................................................... 30

Optimizing Power by Disabling Unused Channels and

Amplifiers.................................................................................... 39

TIA ADC Mode.......................................................................... 40

Digital Integrate Mode............................................................... 42

Pulse Connect Mode.................................................................. 45

Synchronous ECG and PPG Measurement Using TIA ADC

Mode ............................................................................................ 45

Register Listing ............................................................................... 48

LED Control Registers............................................................... 52

AFE Global Configuration Registers....................................... 54

System Registers ......................................................................... 59

ADC Registers ............................................................................ 63

Data Registers ............................................................................. 64

Required Start-Up Load Procedure ......................................... 64

Outline Dimensions....................................................................... 65

Ordering Guide .......................................................................... 66

Rev. A | Page 2 of 66

Data Sheet

ADPD105/ADPD106/ADPD107

REVISION HISTORY

1/2017—Rev. 0 to Rev. A

Added Table 16 and WLCSP Input Configurations Section.....21

Changes to Register 0x14, PD1 to PD4 Input Configurations

Section ..............................................................................................21

Changes to Typical Connection Diagram Section .....................30

Added Figure 37 and Table 22.......................................................31

Added Measuring Voltages Using the Current Input Section,

Figure 52, and Figure 53.................................................................47

Changes to Table 28 ........................................................................48

Updated Outline Dimensions........................................................65

Changes to Ordering Guide...........................................................66

Added ADPD106................................................................. Universal

Changes to Features Section and General Description Section.......1

Changes to Figure 1...........................................................................4

Added Figure 2; Renumbered Sequentially ...................................5

Changes to Table 2 ............................................................................6

Changes to Table 9 ..........................................................................12

Added Figure 6 and Table 11; Renumbered Sequentially..........13

Added Figure 8 and Table 13 .........................................................15

Changes to ADPD105 LFCSP Input Configurations

Section ..............................................................................................20

Added Register 0x14, PD1 to PD8 Input Configurations Section

and Figure 19 to Figure 21 .............................................................20

7/2016—Revision 0: Initial Version

Rev. A | Page 3 of 66

ADPD105/ADPD106/ADPD107

Data Sheet

FUNCTIONAL BLOCK DIAGRAMS

AVDD

DVDD

TIME SLOT

SWITCH

ANALOG BLOCK

PDC

AFE:

PD1-2

SIGNAL CONDITIONING

ADPD105/

ADPD106/

ADPD107

TIA

BPF

±1 INTEGRATOR

V

BIAS

WLCSP VERSIONS

VREF

1µF

AFE:

SIGNAL CONDITIONING

TIME SLOT A

TIA

BPF

DATA

±1 INTEGRATOR

14-BIT

ADC

BIAS

TIME SLOT B

DATA

AFE:

PD3-4

SIGNAL CONDITIONING

AFE

GPIO0

GPIO1

CONFIGURATION

TIA

BPF

±1 INTEGRATOR

A

B

PD3-4 ON

BIAS

ADPD105/

ADPD107

ONLY

SLOT

DIGITAL

DATAPATH

AND

INTERFACE

CONTROL

SELECT

AFE:

SIGNAL CONDITIONING

MOSI

TIA

BPF

ADPD106/

ADPD107

ONLY

MISO

SCLK

CS

±1 INTEGRATOR

BIAS

SDA

SCL

ADPD105

ONLY

LEDX3

LEDX2

LEDX1

LED3

LED2

LED1

LED3 LEVEL AND TIMING CONTROL

LED2 LEVEL AND TIMING CONTROL

LED1 LEVEL AND TIMING CONTROL

LED3 DRIVER

LED2 DRIVER

DGND

AGND

LED1 DRIVER

V

LED

LGND

Figure 1. Block Diagram for ADPD105/ADPD106/ADPD107 WLCSP (Chip Scale Package) Versions

Rev. A | Page 4 of 66

Data Sheet

ADPD105/ADPD106/ADPD107

AVDD

DVDD

TIME SLOT

SWITCH

ANALOG BLOCK

PDC

PD1

AFE:

ADPD105

LFCSP

SIGNAL CONDITIONING

TIA

BPF

±1 INTEGRATOR

PD5

V

BIAS

VREF

AFE:

SIGNAL CONDITIONING

PD2

PD6

1µF

TIME SLOT A

TIA

BPF

DATA

±1 INTEGRATOR

14-BIT

ADC

BIAS

TIME SLOT B

DATA

AFE:

SIGNAL CONDITIONING

AFE

PD3

PD7

GPIO0

GPIO1

CONFIGURATION

TIA

BPF

±1 INTEGRATOR

A

B

BIAS

SLOT

SELECT

DIGITAL

DATAPATH

AND

INTERFACE

CONTROL

AFE:

SIGNAL CONDITIONING

PD4

PD8

TIA

BPF

±1 INTEGRATOR

BIAS

SDA

SCL

LEDX3

LEDX2

LEDX1

LED3

LED2

LED1

LED3 LEVEL AND TIMING CONTROL

LED2 LEVEL AND TIMING CONTROL

LED1 LEVEL AND TIMING CONTROL

LED3 DRIVER

LED2 DRIVER

DGND

AGND

LED1 DRIVER

V

LED

LGND

Figure 2. Block Diagram for ADPD105 LFCSP Version

Rev. A | Page 5 of 66

ADPD105/ADPD106/ADPD107

Data Sheet

SPECIFICATIONS

TEMPERATURE AND POWER SPECIFICATIONS

Table 1. Operating Conditions

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

TEMPERATURE RANGE

Operating Range

Storage Range

POWER SUPPLY VOLTAGES

V_DD

−40

−65

+85

+150

°C

Applied at the AVDD and DVDD pins

1.7

1.8

1.9

V

AVDD = DVDD = 1.8 V, T_A= 25°C, unless otherwise noted.

Table 2. Current Consumption

Parameter

Symbol

Test Conditions/Comments

Min Typ Max Unit

POWER SUPPLY (V_DD) CURRENT

V_DDSupply Current¹

SLOTx_LED_OFFSET = 25 μs; LED_PERIOD =19 μs; LED peak

current = 25 mA, single-channel mode

1 Pulse

100 Hz data rate; Time Slot A only

100 Hz data rate; Time Slot B only

100 Hz data rate; both Time Slot A and Time Slot B

100 Hz data rate; Time Slot A only

100 Hz data rate; Time Slot B only

92

75

119

175

155

281

μA

10 Pulses

100 Hz data rate; both Time Slot A and Time Slot B

Peak V_DDSupply Current

(1.8 V)

IV_DD__PEAK

4-Channel Operation

1-Channel Operation

Standby Mode Current

V_LEDSUPPLY CURRENT²

Average Supply Current

V_LEDAor V_LEDB

9.3

4.5

0.3

mA

μA

IV_DD__STANDBY

Peak LED current = 25 mA; LED pulse width = 3 μs

50 Hz data rate

100 Hz data rate

200 Hz data rate

50 Hz data rate

1 Pulse

3.75

7.5

15

38

75

μA

10 Pulses

100 Hz data rate

200 Hz data rate

150

¹V_DDis the voltage applied at the AVDD and DVDD pins.

²V_LEDapplies to the external LED supply voltage for any given LED being driven by the ADPD105/ADPD106/ADPD107 LED drivers under the listed conditions.

Rev. A | Page 6 of 66

Data Sheet

ADPD105/ADPD106/ADPD107

PERFORMANCE SPECIFICATIONS

AVDD = DVDD = 1.8 V, T_A= full operating temperature range, unless otherwise noted.

Table 3.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

DATA ACQUISITION

Resolution

Resolution/Sample

Resolution/Data Read

LED DRIVER

LED Current Slew Rate¹

Rise

Single pulse

64 to 255 pulses

64 to 255 pulses and sample average = 128

14

20

27

Bits

Slew rate control setting = 0; T_A= 25°C; I_LED= 70 mA

Slew rate control setting = 7; T_A= 25°C; I_LED= 70 mA

Slew rate control setting = 0, 1, 2; T_A= 25°C; I_LED= 70 mA

Slew rate control setting = 6, 7; T_A= 25°C; I_LED= 70 mA

LED pulse enabled

Voltage above ground required for LED driver operation

AFE width = 4 μs²

AFE width = 3 μs

Time Slot A only; normal mode; 1 pulse; SLOTA_LED_OFFSET = 23 μs; SLOTA_

LED_PERIOD = 19 μs

Time Slot B only; normal mode; 1 pulse; SLOTA_LED_OFFSET = 23 μs; SLOTA_

LED_PERIOD = 19 μs

Both time slots; normal mode; 1 pulse; SLOTA_LED_OFFSET = 23 μs; SLOTA_

LED_PERIOD = 19 μs

Time Slot A only; normal mode; 8 pulses; SLOTA_LED_OFFSET = 23 μs; SLOTA_

LED_PERIOD = 19 μs

240

mA/μs

mA

1400

3200

4500

Fall

LED Peak Current

Driver Compliance Voltage

LED PERIOD

370

0.6

19

17

V

μs

Sampling Frequency³

0.122

3230 Hz

3820 Hz

1750 Hz

2257 Hz

2531 Hz

1193 Hz

Time Slot B only; normal mode; 8 pulses; SLOTA_LED_OFFSET = 23 μs; SLOTA_

LED_PERIOD = 19 μs

Both time slots; normal mode; 8 pulses; SLOTA_LED_OFFSET = 23 μs; SLOTA_

LED_PERIOD = 19 μs

CATHODE PIN (PDC) VOLTAGE

During All Sampling Periods

Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 1⁴

Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 0

1.8

1.3

1.8

1.3

1.55

0

1.8

1.3

1.55

0

1.8

1.3

1.8

1.3

1.55

0

V

During Slot A Sampling

During Slot B Sampling

During Sleep Periods

Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x0⁴

Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x1

Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x2

Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x3⁵

Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x0⁴

Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x1

Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x2

Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x3⁵

Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 1

Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 0

Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x0

Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x1

Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x2

Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x3

PHOTODIODE INPUT PINS/

ANODE VOLTAGE

During All Sampling Periods

During Sleep Periods

1.3

V

Cathode voltage

¹LED inductance is negligible for these values. The effective slew rate slows with increased inductance.

²Minimum LED period = (2 × AFE width) + 5 μs.

³The maximum values in this specification are the internal ADC sampling rates in normal mode. The I²C read rates in some configurations may limit the output data rate.

⁴This mode may induce additional noise and is not recommended unless absolutely necessary. The 1.8 V setting uses V_DD, which contains greater amounts of

differential voltage noise with respect to the anode voltage. A differential voltage between the anode and cathode injects a differential current across the capacitance

of the photodiode of the magnitude of C × dV/dt.

⁵This setting is not recommended for photodiodes because it causes a 1.3 V forward bias of the photodiode.

Rev. A | Page 7 of 66

ADPD105/ADPD106/ADPD107

Data Sheet

ANALOG SPECIFICATIONS

AVDD = DVDD = 1.8 V, T_A= full operating temperature range, unless otherwise noted. Compensation of the AFE offset is explained in

the AFE Operation section.

Table 4.

Parameter

Test Conditions/Comments

Min Typ

Max Unit

INPUT CAPACITANCE

100

pF

PULSED SIGNAL CONVERSIONS, 3 ꢀs WIDE LED PULSE¹

4 ꢀs wide AFE integration; normal operation,

Register 0x43/Register 0x45 = 0xADA5

Transimpedance amplifier (TIA) feedback resistor

ADC Resolution²

25 kΩ

50 kΩ

100 kΩ

200 kΩ

3.27

1.64

0.82

0.41

nA/LSB

ADC Saturation Level

TIA feedback resistor

25 kΩ

26.8

13.4

6.7

ꢀA

50 kΩ

100 kΩ

200 kΩ

3.35

Ambient Signal Headroom on Pulsed Signal

TIA feedback resistor

25 kΩ

23.6

11.8

5.9

ꢀA

50 kΩ

100 kΩ

200 kΩ

2.95

PULSED SIGNAL CONVERSIONS, 2 ꢀs WIDE LED PULSE¹

ADC Resolution²

3 ꢀs wide AFE integration; normal operation,

Register 0x43/Register 0x45 = 0xADA5

TIA feedback resistor

25 kΩ

4.62

2.31

1.15

0.58

nA/LSB

50 kΩ

100 kΩ

200 kΩ

ADC Saturation Level

TIA feedback resistor

25 kΩ

37.84

18.92

9.46

ꢀA

50 kΩ

100 kΩ

200 kΩ

4.73

Ambient Signal Headroom on Pulsed Signal

FULL SIGNAL CONVERSIONS³

TIA feedback resistor

25 kΩ

50 kΩ

100 kΩ

200 kΩ

12.56

6.28

3.14

1.57

ꢀA

TIA Saturation Level of Pulsed Signal and Ambient Level TIA feedback resistor

25 kΩ

50 kΩ

100 kΩ

200 kΩ

50.4

25.2

12.6

6.3

ꢀA

Rev. A | Page 8 of 66

Data Sheet

ADPD105/ADPD106/ADPD107

Parameter

Test Conditions/Comments

Min Typ

Max Unit

SYSTEM PERFORMANCE

Total Output Noise Floor

Normal mode; per pulse; per channel; no LED; photodiode

capacitance (C_PD) = 70 pF

25 kΩ; referred to ADC input

1.0

LSB rms

25 kΩ; referred to peak input signal for 2 μs LED pulse

25 kΩ; referred to peak input signal for 3 μs LED pulse

25 kΩ; saturation signal-to-noise ratio (SNR) per pulse

per channel⁴

4.6

3.3

78.3

nA rms

dB

50 kΩ; referred to ADC input

1.2

2.8

2.0

76.6

1.7

1.9

1.4

73.6

2.75

1.6

LSB rms

nA rms

dB

LSB rms

nA rms

dB

LSB rms

nA rms

dB

50 kΩ; referred to peak input signal for 2 μs LED pulse

50 kΩ; referred to peak input signal for 3 μs LED pulse

50 kΩ; saturation SNR per pulse per channel⁴

100 kΩ; referred to ADC input

100 kΩ; referred to peak input signal for 2 μs LED pulse

100 kΩ; referred to peak input signal for 3 μs LED pulse

100 kΩ; saturation SNR per pulse per channel⁴

200 kΩ; referred to ADC input

200 kΩ; referred to peak input signal for 2 μs LED pulse

200 kΩ; referred to peak input signal for 3 μs LED pulse

200 kΩ; saturation SNR per pulse per channel⁴

1.1

69.5

−37

DC Power Supply Rejection Ratio (DC PSRR)

dB

¹This saturation level applies to the ADC only and, therefore, includes only the pulsed signal. Any nonpulsatile signal is removed prior to the ADC stage.

²ADC resolution is listed per pulse when the AFE offset is correctly compensated per the AFE Operation section. If using multiple pulses, divide by the number of pulses.

³This saturation level applies to the full signal path and, therefore, includes both the ambient signal and the pulsed signal.

⁴The noise term of the saturation SNR value refers to the receive noise only and does not include photon shot noise or any noise on the LED signal itself.

DIGITAL SPECIFICATIONS

DVDD = 1.7 V to 1.9 V, unless otherwise noted.

Table 5.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

LOGIC INPUTS (GPIOx, SCL, SDA,

SCLK, MOSI, CS)

Input Voltage Level

High

Low

V_IH

V_IL

0.7 × DVDD

3.6

0.3 × DVDD

V

Input Current Level

High

Low

Input Capacitance

LOGIC OUTPUTS

Output Voltage Level

High

I_IH

I_IL

C_IN

−10

+10

μA

pF

10

GPIOx, MOSI

V_OH

V_OL

2 mA high level output current

2 mA low level output current

SDA

2 mA low level output current

SDA

DVDD − 0.5

V

Low

0.5

Output Voltage Level

Low

Output Current Level

Low

V_OL1

I_OL

0.2 × DVDD

V

V_OL1= 0.6 V

6

mA

Rev. A | Page 9 of 66

ADPD105/ADPD106/ADPD107

Data Sheet

TIMING SPECIFICATIONS

Table 6. I²C Timing Specifications

Parameter

I²C PORT¹

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

See Figure 3

SCL

Frequency

400

kHz

Minimum Pulse Width

High

Low

t₁

t₂

600

1300

ns

Start Condition

Hold Time

Setup Time

SDA Setup Time

SCL and SDA

Rise Time

t₃

t₄

t₅

600

100

ns

t₆

t₇

1000

300

ns

Fall Time

Stop Condition

Setup Time

t₈

600

ns

¹Guaranteed by design.

t₃

t₅

t₃

SDA

t₆

t₁

SCL

t₂

t₇

t₄

t₈

Figure 3. I²C Timing Diagram

Rev. A | Page 10 of 66

Data Sheet

ADPD105/ADPD106/ADPD107

Table 7. SPI Timing Specifications

Parameter

SPI PORT

SCLK

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

Frequency

Minimum Pulse Width

High

f_SCLK

10

MHz

t_SCLKPWH

t_SCLKPWL

20

ns

Low

CS

Setup Time

t_CS

CS setup to SCLK rising edge

CS hold from SCLK rising edge

CS pulse width high

10

ns

S

Hold Time

t_CS

H

Pulse Width High

t_CS

PWH

MOSI

ns

Setup Time

Hold Time

MISO Output Delay

t_MOSIS

t_MOSIH

t_MISOD

MOSI setup to SCLK rising edge

MOSI hold from SCLK rising edge

MISO valid output delay from SCLK

falling edge

10

20

ns

t_CSH

t_CSS

t_CSPWH

t_SCLKPWL

t_SCLKPWH

CS

SCLK

MOSI

t_MOSIH

t_MOSIS

MISO

t_MISOD

Figure 4. SPI Timing Diagram

Rev. A | Page 11 of 66

ADPD105/ADPD106/ADPD107

Data Sheet

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED SOLDERING PROFILE

Table 8.

Figure 5 and Table 10 provide details about the recommended

soldering profile.

Parameter

Rating

AVDD to AGND

−0.3 V to +2.2 V

−0.3 V to +3.6 V

−0.3 V to +3.9 V

150°C

DVDD to DGND

GPIO0 to DGND

GPIO1 to DGND

LEDXx to LGND

SCL to DGND

SDA to DGND

CRITICAL ZONE

t_P

T

TO T

P

L

T

P

RAMP-UP

T

L

t_L

T

SMAX

T

SMIN

Junction Temperature

ESD

t_S

RAMP-DOWN

PREHEAT

Human Body Model (HBM)

Charged Device Model (CDM)

Machine Model (MM)

1500 V

500 V

100 V

t25°C TO PEAK

TIME

Figure 5. Recommended Soldering Profile

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Table 10. Recommended Soldering Profile

Profile Feature

Condition (Pb-Free)

Average Ramp Rate (T_Lto T_P)

Preheat

3°C/sec max

Minimum Temperature (T_SMIN

)

150°C

Maximum Temperature (T_SMAX

Time (T_SMINto T_SMAX) (t_S)

T_SMAXto T_LRamp-Up Rate

)

200°C

60 sec to 180 sec

3°C/sec maximum

THERMAL RESISTANCE

Time Maintained Above Liquidous

Temperature

Liquidous Temperature (T_L)

Time (t_L)

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Close attention to

PCB thermal design is required.

217°C

60 sec to 150 sec

+260 (+0/−5)°C

<30 sec

Table 9. Thermal Resistance

Package Type

Peak Temperature (T_P)

Time Within 5°C of Actual Peak

Temperature (t_P)

Ramp-Down Rate

Time from 25°C to Peak Temperature

θ_JA

54.9

60

Unit

°C/W

CP-28-5

CB-16-18

CB-17-1

6°C/sec maximum

8 minutes maximum

60

ESD CAUTION

Rev. A | Page 12 of 66

Data Sheet

ADPD105/ADPD106/ADPD107

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

21 NIC

20 NIC

19 NIC

GPIO0 1

GPIO1 2

DVDD 3

AGND 4

VREF 5

AVDD 6

PD1 7

ADPD105

18 NIC

17 NIC

16 NIC

15 PD8

TOP VIEW

(Not to Scale)

NOTES

1. NIC = NOT INTERNALLY CONNECTED (NONBONDED PAD).

THIS PIN CAN BE GROUNDED.

2. EXPOSED PAD (DIGITAL GROUND). CONNECT THE

EXPOSED PAD TO GROUND.

Figure 6. 28-Lead LFCSP Pin Configuration (ADPD105)

Table 11. 28-Lead LFCSP Pin Function Descriptions

Pin No.

Mnemonic

GPIO0

GPIO1

DVDD

AGND

VREF

AVDD

PD1

PD2

PD3

PD4

PDC

PD5

PD6

PD7

PD8

NIC

LEDX1

LEDX3

LEDX2

LGND

SCL

Type¹

DIO

S

REF

S

AI

AO

AI

Description

1

2

3

4

5

6

7

8

General-Purpose Input/Output (I/O). This pin is used for interrupts and various clocking options.

General-Purpose I/O. This pin is used for interrupts and various clocking options.

1.8 V Digital Supply.

Analog Ground.

Internally Generated ADC Voltage Reference. Buffer this pin with a 1 μF capacitor to AGND.

1.8 V Analog Supply.

Photodiode Current Input (Anode). If not in use, leave this pin floating.

Photodiode Common Cathode Bias.

Photodiode Current Input (Anode). If not in use, leave this pin floating.

Not Internally Connected (Nonbonded Pad). This pin can be grounded.

LED Driver 1 Current Sink. If not in use, leave this pin floating.

LED Driver 3 Current Sink. If not in use, leave this pin floating.

LED Driver 2 Current Sink. If not in use, leave this pin floating.

LED Driver Ground.

9

10

11

12

13

14

15

16 to 22

23

24

25

26

27

28

R

AO

S

DI

DIO

S

I²C Clock Input.

I²C Data Input/Output.

Exposed Pad (Digital Ground). Connect the exposed pad to ground.

SDA

EPAD (DGND)

¹DIO means digital input/output, S means supply, REF means voltage reference, AI means analog input, AO means analog output, R means reserved, and DI means

digital input.

Rev. A | Page 13 of 66

ADPD105/ADPD106/ADPD107

Data Sheet

ADPD105

TOP VIEW, BALL SIDE DOWN

(Not to Scale)

1

2

3

A

B

C

D

E

F

LGND

LEDX2

SDA

DVDD

AGND

AVDD

PD3-4

LEDX3

SCL

LEDX1

GPIO0

DGND

VREF

GPIO1

PD1-2

PDC

Figure 7. ADPD105 Pin Configuration

Table 12. ADPD105 Pin Function Descriptions

Pin No.

A1

A2

B1

B2

B3

Mnemonic

LGND

LEDX2

LEDX3

LEDX1

SDA

Type¹Description

S

LED Driver Ground.

AO

DIO

DI

LED Driver 2 Current Sink. If not in use, leave this pin floating.

LED Driver 3 Current Sink. If not in use, leave this pin floating.

LED Driver 1 Current Sink. If not in use, leave this pin floating.

I²C Data Input/Output (I/O).

C1

SCL

I²C Clock Input.

C2

C3

D2

D3

E1

E2

E3

F1

GPIO0

DVDD

DGND

AGND

GPIO1

VREF

DIO

S

General Purpose I/O. This pin is used for interrupts and various clocking options.

1.8 V Digital Supply.

Digital Ground.

S

Analog Ground.

DIO

REF

S

General Purpose I/O. This pin is used for interrupts and various clocking options.

Internally Generated ADC Voltage Reference. Buffer this pin with a 1 μF capacitor to AGND.

1.8 V Analog Supply.

Photodiode Combined Current Input of Photodiode 1 (PD1) and Photodiode 2 (PD2). If not in use,

leave this pin floating.

AVDD

PD1-2

AI

F2

F3

PDC

PD3-4

AO

AI

Photodiode Common Cathode Bias.

Photodiode Combined Current Input of Photodiode 3 (PD3) and Photodiode 4 (PD4). If not in use,

leave this pin floating.

¹S means supply, AO means analog output, DIO means digital input/output, DI means digital input, REF means voltage reference, AI means analog input, and AO

means analog output.

Rev. A | Page 14 of 66

Data Sheet

ADPD105/ADPD106/ADPD107

ADPD106

TOP VIEW, BALL SIDE DOWN

(Not to Scale)

1

2

3

A

B

C

D

E

F

LEDX2

LGND

GPIO0

DGND

SCLK

VREF

PD1-2

LEDX3

GPIO1

LEDX1

MISO

MOSI

AGND

CS

AVDD

PDC

Figure 8. 16-Ball WLCSP Pin Configuration (ADPD106)

Table 13. 16-Ball WLCSP Pin Function Descriptions

Pin No.

A1

A2

B1

B2

B3

C1

C2

C3

D2

D3

E1

Mnemonic

LEDX2

LGND

LEDX3

LEDX1

GPIO0

GPIO1

MISO

Type¹Description

AO

S

LED Driver 2 Current Sink. If not in use, leave this pin floating.

LED Driver Ground

AO

DIO

DO

S

LED Driver 3 Current Sink. If not in use, leave this pin floating.

LED Driver 1 Current Sink. If not in use, leave this pin floating.

General Purpose I/O. This pin is used for interrupts and various clocking options.

SPI Data Output.

Digital Ground.

DGND

MOSI

SCLK

DI

SPI Data Input.

DI

SPI Clock Input.

CS

DI

SPI Chip Select, Active Low.

E2

E3

F1

F2

AGND

VREF

AVDD

PDC

S

REF

S

AO

AI

Analog Ground.

Internally Generated ADC Voltage Reference. Buffer this pin with a 1 μF capacitor to AGND.

1.8 V Analog Supply.

Photodiode Common Cathode Bias.

F3

PD1-2

Photodiode Combined Current Input of PD1 and PD2. If not in use, leave this pin floating.

¹AO means analog output, S means supply, DIO means digital input/output, DO means digital output, DI means digital input, REF means voltage reference, and

AI means analog input.

Rev. A | Page 15 of 66

ADPD105/ADPD106/ADPD107

Data Sheet

ADPD107

TOP VIEW, BALL SIDE DOWN

(Not to Scale)

1

2

3

A

B

C

D

E

F

LEDX2

LGND

GPIO0

DGND

SCLK

VREF

PD3-4

LEDX3

GPIO1

LEDX1

MISO

MOSI

AGND

CS

AVDD

PD1-2

PDC

Figure 9. ADPD107 Pin Configuration

Table 14. ADPD107 Pin Function Descriptions

Pin No.

A1

A2

B1

B2

B3

C1

C2

C3

D1

D2

D3

E1

Mnemonic

LEDX2

LGND

LEDX3

LEDX1

GPIO0

GPIO1

MISO

Type¹Description

AO

S

LED Driver 2 Current Sink. If not in use, leave this pin floating.

LED Driver Ground.

AO

DIO

DO

S

LED Driver 3 Current Sink. If not in use, leave this pin floating.

LED Driver 1 Current Sink. If not in use, leave this pin floating.

General Purpose I/O. This pin is used for interrupts and various clocking options.

Master Input, Slave Output.

DGND

CS

Digital Ground.

DI

SPI Chip Select. Active low.

MOSI

SCLK

DI

Master Output, Slave Input.

DI

SPI Clock Input.

AVDD

AGND

VREF

PD1-2

PDC

S

1.8 V Analog Supply.

E2

E3

F1

F2

S

Analog Ground.

REF

AI

AO

AI

Internally Generated ADC Voltage Reference. Buffer this pin with a 1 μF capacitor to AGND.

Photodiode Combined Current Input of PD1 and PD2. If not in use, leave this pin floating.

Photodiode Common Cathode Bias.

F3

PD3-4

Photodiode Combined Current Input of PD3 and PD4. If not in use, leave this pin floating.

¹AO means analog output, S means supply, DIO means digital input/output, DO means digital output, DI means digital input, REF means voltage reference, and AI

means analog input.

Rev. A | Page 16 of 66

Data Sheet

ADPD105/ADPD106/ADPD107

TYPICAL PERFORMANCE CHARACTERISTICS

70

3.0

2.5

2.0

1.5

1.0

0.5

0

60

50

40

30

20

10

0

NOISE vs.

NUMBER OF CHANNELS

SQUARE ROOT

OF CHANNEL COUNT

32

33

34

35

36

37

38

39

40

41

1

2

3

4

FREQUENCY (Hz)

NUMBER OF CHANNELS

Figure 10. 32 kHz Clock Frequency Distribution

Figure 13. Noise Multiple of Channel Sum vs. Number of Channels

(Default Settings, Before User Calibration: Register 0x4B = 0x2612)

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

60

50

40

30

20

10

0

50

100

150

200

32.0 32.5 33.0 33.5 34.0 34.5 35.0 35.5 36.0

FREQUENCY (Hz)

TIA GAIN (kΩ)

Figure 11. 32 MHz Clock Frequency Distribution

Figure 14. Referred to Input (RTI) Noise vs. TIA Gain

(Default Settings, Before User Calibration: Register 0x4D = 0x0098)

4.0

400

350

300

250

200

150

100

50

N

= 0.24 × √C + 0.81

LED COARSE SETTING = 0xF

RMS

PD

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

200k

N

= 0.11 × √C + 0.97

RMS

PD

100k

50k

= 0.04 × √C + 1.13

RMS

PD

25k

N

= 0.02 × √C + 1.16

PD

RMS

LED COARSE SETTING = 0x0

LED DRIVER VOLTAGE (V)

0

20

40

60

80

100

120

140

160

PHOTODIODE CAPACITANCE (pF)

Figure 15. LED Driver Current vs. LED Driver Voltage at Various Coarse Settings

Figure 12. RMS Noise vs. Photodiode Capacitance

Rev. A | Page 17 of 66

ADPD105/ADPD106/ADPD107

Data Sheet

45

40

35

30

25

20

360

340

320

300

280

260

240

220

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

LED FINE SETTING, REGISTER 0x25

Figure 16. LED Driver Current vs. LED Fine Setting (Coarse Setting = 0x0)

Figure 17. LED Driver Current vs. LED Fine Setting (Coarse Setting = 0xF)

Rev. A | Page 18 of 66

Data Sheet

ADPD105/ADPD106/ADPD107

THEORY OF OPERATION

INTRODUCTION

DUAL TIME SLOT OPERATION

The ADPD105/ADPD106/ADPD107 operate as a complete

optical transceiver stimulating up to three LEDs and measuring

the return signal on up to two separate current inputs. The core

consists of a photometric front end coupled with an ADC, digital

block, and three independent LED drivers. The core circuitry

stimulates the LEDs and measures the return in the analog block

through one to eight photodiode inputs, storing the results in

discrete data locations. The two inputs can be configured to drive

four simultaneous input channels. Data can be read directly by a

register, or through a FIFO. This highly integrated system includes

an analog signal processing block, digital signal processing block,

I²C communication interface on the ADPD105 or an SPI port on

the ADPD107, and programmable pulsed LED current sources.

The ADPD105/ADPD106/ADPD107 operate in two independent

time slots, Time Slot A and Time Slot B, which are carried out

sequentially. The entire signal path from LED stimulation to data

capture and processing is executed during each time slot. Each

time slot has a separate datapath that uses independent settings

for the LED driver, AFE setup, and the resulting data. Time Slot A

and Time Slot B operate in sequence for every sampling period, as

shown in Figure 18.

The timing parameters are defined as follows:

t_A(μs) = SLOTA_LED_OFFSET + n_A× SLOTA_LED_PERIOD

where n_Ais the number of pulses for Time Slot A (Register 0x31,

Bits[15:8]).

The LED driver is a current sink and is agnostic to LED supply

voltage and LED type. The photodiode (PDx) inputs can

accommodate any photodiode with an input capacitance of less

than 100 pF. The ADPD105/ADPD106/ADPD107 are designed

to produce a high SNR for relatively low LED power while greatly

reducing the effect of ambient light on the measured signal.

t_B(μs) = SLOTB_LED_OFFSET + n_B× SLOTB_LED_PERIOD

where n_Bis the number of pulses for Time Slot B (Register 0x36,

Bits[15:8]).

Calculate the LED period using the following equation:

LED_PERIOD, minimum = 2 × AFE_WIDTH + 11

t₁and t₂are fixed and based on the computation time for each

slot. If a slot is not in use, these times do not add to the total

active time. Table 15 defines the values for these LED and

sampling time parameters.

ACTIVE

t_A

t₁

t_B

t₂

n_APULSES

n_BPULSES

SLEEP

TIME SLOT A

TIME SLOT B

1/f

SAMPLE

Figure 18. Time Slot Timing Diagram

Table 15. LED Timing and Sample Timing Parameters

Parameter

Register

Bits

Test Conditions/Comments

Min Typ Max Unit

SLOTA_LED_OFFSET¹

0x30

0x35

0x31

0x36

[7:0] Delay from power-up to LEDA rising edge

[7:0] Delay from power-up to LEDB rising edge

[7:0] Time between LED pulses in Time Slot A; SLOTx_AFE_WIDTH = 4 ꢀs 19

[7:0] Time between LED pulses in Time Slot B; SLOTx_AFE_WIDTH = 4 ꢀs 19

Compute time for Time Slot A

23

63

μs

SLOTB_LED_OFFSET¹

SLOTA_LED_PERIOD²

SLOTB_LED_PERIOD²

t₁

t₂

t_SLEEP

68

20

Compute time for Time Slot B

Sleep time between sample periods

222

¹Setting the SLOTx_LED_OFFSET below the specified minimum value may cause failure of ambient light rejection for large photodiodes.

²Setting the SLOTx_LED_PERIOD below the specified minimum value can cause invalid data captures.

Rev. A | Page 19 of 66

ADPD105/ADPD106/ADPD107

Data Sheet

TIME SLOT SWITCH

ADPD105 LFCSP Input Configurations

PD1

PD2

PD3

PD4

PD5

PD6

PD7

PD8

CH1

CH2

CH3

CH4

Up to eight photodiodes (PD1 to PD8) can be connected to the

ADPD105 in the LFCSP package. The photodiode anodes are

connected to the PD1 to PD8 input pins; the photodiode

cathodes are connected to the cathode pin, PDC. The anodes are

assigned in three different configurations depending on the

settings of Register 0x14 (see Figure 22, Figure 23, and Figure 21).

A switch sets which photodiode group is connected during Time

Slot A and Time Slot B. See Table 17 for the time slot switch

registers. It is important to leave any unused inputs floating for

proper operation of the devices. The photodiode inputs are

current inputs and as such, these pins are also considered to be

voltage outputs. Tying these inputs to a voltage may saturate the

analog block.

Register 0x14, PD1 to PD8 Input Configurations

PD1

CH1

PD2

INPUT CONFIGURATION FOR

REGISTER 0x14[11:8] = 4

REGISTER 0x14[7:4] = 4

Figure 20. PD5 to PD8 Connection

PD3

PD1

CH2

PD4

CH1

PD2

PD5

PD3

CH3

PD6

CH2

PD4

PD7

PD5

CH4

PD8

CH3

PD6

INPUT CONFIGURATION FOR

REGISTER 0x14[11:8] = 5

REGISTER 0x14[7:4] = 5

PD7

Figure 19. PD1 to PD4 Connection

CH4

PD8

INPUT CONFIGURATION FOR

REGISTER 0x14[11:8] = 1

REGISTER 0x14[7:4] = 1

Figure 21. 2 to 1 PD Current Summation

Rev. A | Page 20 of 66

Data Sheet

ADPD105/ADPD106/ADPD107

Table 16. Time Slot Switch (Register 0x14)

Address

Bits

Name

Description

0x14

[11:8]

SLOTB_PD_SEL

Selects connection of photodiode for Time Slot B as shown in Figure 22, Figure 23,

and Figure 21.

0x0: inputs are floating in Time Slot B.

0x1: all PDx pins (PD1 to PD8) are connected during Time Slot B.

0x4: PD5 to PD8 are connected during Time Slot B.

0x5: PD1 to PD4 are connected during Time Slot B.

Other: reserved.

[7:4]

SLOTA_PD_SEL

Selects connection of photodiode for Time Slot A as shown in Figure 22, Figure 23,

and Figure 21.

0x0: inputs are floating in Time Slot A.

0x1: all PDx pins (PD1 to PD8) are connected during Time Slot A.

0x4: PD5 to PD8 are connected during Time Slot A.

0x5: PD1 to PD4 are connected during Time Slot A.

Other: reserved.

WLCSP Input Configurations

Up to two photodiodes can be connected to four channels of the

ADPD105 and ADPD107 WLCSP models. The ADPD106

accommodates a single photodiode that can be connected to

Channel 1 and Channel 2. The photodiode anodes are connected

to the PD1-2 and PD3-4 input pins; the photodiode cathodes are

connected to the cathode pin, PDC. The anodes are assigned in

two different configurations depending on the settings of

Register 0x14 (see Figure 22 and Figure 23).

PD1-2

CH1

CH2

CH3

CH4

Register 0x14, PD1 to PD4 Input Configurations

Figure 22 shows the configuration where each of the PD inputs

is connected to two channels. This configuration is the high

dynamic range mode used for large photodiode currents. Figure 23

shows the configuration where each of the inputs to the device

is connected to a single channel. This mode allows the user to

maximize SNR for situations where lower photodiode currents are

expected.

PD3-4

A switch sets which photodiode group is connected during Time

Slot A and Time Slot B. See Table 17 for the time slot switch

registers. It is important to leave any unused inputs floating for

proper operation of the devices. The photodiode inputs are

current inputs and, as such, these pins are also considered to be

voltage outputs. Tying these inputs to a voltage may saturate the

analog block.

INPUT CONFIGURATION FOR

REGISTER 0x14[11:8] = 5

REGISTER 0x14[7:4] = 5

Figure 22. PD1 to PD4 Connection

PD1-2

CH1

Note that the ADPD106 only includes the options shown for the

PD1-2 input pin shown in Figure 22 and Figure 23.

PD3-4

CH2

INPUT CONFIGURATION FOR

REGISTER 0x14[11:8] = 1

REGISTER 0x14[7:4] = 1

Figure 23. Current Summation—Two Photodiodes Summed into One Current

Rev. A | Page 21 of 66

ADPD105/ADPD106/ADPD107

Data Sheet

Table 17. Time Slot Switch (Register 0x14)

Address

Bits

Name

Description

0x14

[11:8]

SLOTB_PD_SEL

Selects connection of photodiode forTime Slot B as shown in Figure 22 and Figure 23.

0x0: inputs are floating in Time Slot B.

0x1: PD1-2 is connected to Channel 1; PD3-4 is connected to Channel 2 during Time Slot B.

0x5: PD1-2 is connected to Channel 1 and Channel 2; PD3-4 is connected to Channel 3

and Channel 4 during Time Slot B.

Other: reserved.

[7:4]

SLOTA_PD_SEL

Selects connection of photodiode for Time Slot A as shown in Figure 22 and Figure 23.

0x0: inputs are floating in Time Slot A.

0x1: PD1-2 is connected to Channel 1; PD3-4 is connected to Channel 2 during Time Slot A.

0x5: PD1-2 is connected to Channel 1 and Channel 2; PD3-4 is connected to Channel 3

and Channel 4 during Time Slot A.

Other: reserved.

appropriate input buffer using Register 0x4F, Bit 1, for the

GPIO0 pin, or Register 0x4F, Bit 5, for the GPIO1 pin.

3. Write 0x4000 to Register 0x38.

4. Write 0x2 to Register 0x10 to start the sampling operations.

5. Apply the external sync signal on the selected pin at the

desired rate; sampling occurs at that rate. As with normal

sampling operations, read the data using the FIFO or the

data registers.

ADJUSTABLE SAMPLING FREQUENCY

Register 0x12 controls the sampling frequency setting of the

ADPD105/ADPD106/ADPD107 and Register 0x4B, Bits[5:0]

further tunes this clock for greater accuracy. The sampling

frequency is governed by an internal 32 kHz sample rate clock

that also drives the trans-ition of the internal state machine. The

maximum sampling frequencies for some sample conditions

are listed in Table 3. The maximum sample frequency for all

conditions is determined by the following equation:

The maximum frequency constraints also apply in this case.

f

_{SAMPLE, MAX}= 1/(t_A+ t₁+ t_B+ t₂+ t_{SLEEP, MIN})

Providing an External 32kHz Clock

where t_{SLEEP, MIN}is the minimum sleep time required between

samples.

The ADPD105/ADPD106/ADPD107 have an option for the

user to provide an external 32 kHz clock to the devices for

system synchronization or for situations where a clock with

better accuracy than the internal 32 kHz clock is required. The

external 32 kHz clock is provided on the GPIO1 pin. To enable

the 32 kHz external clock, use the following procedure at startup:

If a given time slot is not in use, elements from that time slot do

not factor into the calculation. For example, if Time Slot A is

not in use, t_Aand t₁do not add to the sampling period and the

new maximum sampling frequency is calculated as follows:

1. Drive the GPIO1 pin to a valid logic level or with the

desired 32 kHz clock prior to enabling the GPIO1 pin as an

input. Do not leave the pin floating prior to enabling it.

2. Write 01 to Register 0x4F, Bits[6:5] to enable the GPIO1 pin as

an input.

f

_{SAMPLE, MAX}= 1/(t_B+ t₂+ t_{SLEEP, MIN})

See the Dual Time Slot Operation section for the definitions of

t_A, t₁, t_B, and t₂.

External Sync for Sampling

3. Write 10 to Register 0x4B, Bits[8:7] to configure the devices to

use an external 32 kHz clock. This setting disables the

internal 32 kHz clock and enables the external 32 kHz clock.

4. Write 0x1 to Register 0x10 to enter program mode.

5. Write additional control registers in any order while the

devices are in program mode to configure the devices as

required.

The ADPD105/ADPD106/ADPD107 provide an option to use

an external sync signal to trigger the sampling periods. This

external sample sync signal can be provided either on the

GPIO0 pin or the GPIO1 pin. This functionality is controlled

by Register 0x4F, Bits[3:2]. When enabled, a rising edge on

the selected input specifies when the next sample cycle occurs.

When triggered, there is a delay of one to two internal sampling

clock (32 kHz) cycles, and then the normal start-up sequence

occurs. This sequence is the same as when the normal sample

timer providesthe trigger. To enable the external sync signal

feature, use the following procedure:

6. Write 0x2 to Register 0x10 to start the normal sampling

operation.

1. Write 0x1 to Register 0x10 to enter program mode.

2. Write the appropriate value to Register 0x4F, Bits[3:2] to

select whether the GPIO0 pin or the GPIO1 pin specifies

when the next sample cycle occurs. Also, enable the

Rev. A | Page 22 of 66

Data Sheet

ADPD105/ADPD106/ADPD107

when writing registers or changing modes. Because no power

cycling occurs in this mode, the devices may consume higher

current in program mode than in normal operation. To place

the devices in program mode, write 0x1 to Register 0x10, Bits[1:0].

STATE MACHINE OPERATION

During each time slot, the ADPD105/ADPD106/ADPD107

operate according to a state machine. The state machine

operates in the following sequence, shown in Figure 24.

In normal operation, the ADPD105/ADPD106/ADPD107 pulse

light and collect data. Power consumption in this mode depends

on the pulse count and data rate. To place the devices in normal

sampling mode, write 0x2 to Register 0x10, Bits[1:0].

STANDBY

REGISTER 0x10 = 0x0000

ULTRALOW POWER MODE

NO DATA COLLECTION

ALL REGISTER VALUES ARE RETAINED.

NORMAL MODE OPERATION AND DATA FLOW

In normal mode, the ADPD105/ADPD106/ADPD107 follow a

specific pattern set up by the state machine. This pattern is shown

in the corresponding data flow in Figure 25. The pattern is as

follows:

PROGRAM

REGISTER 0x10 = 0x0001

SAFE MODE FOR PROGRAMING REGISTERS

NO DATA COLLECTION

DEVICE IS FULLY POWERED IN THIS MODE.

1. LED pulse and sample. The ADPD105/ADPD106/ADPD107

pulse external LEDs. The response of a photodiode or photo-

diodes to the reflected light is measured by the ADPD105/

ADPD106/ADPD107. Each data sample is constructed from

the sum of n individual pulses, where n is user configurable

between 1 and 255.

2. Intersample averaging. If desired, the logic can average n

samples, from 2 to 128 in powers of 2, to produce output

data. New output data is saved to the output registers every

N samples.

3. Data read. The host processor reads the converted results

from the data register or the FIFO.

4. Repeat. The sequence has a few different loops that enable

different types of averaging while keeping both time slots

close in time relative to each other.

NORMAL OPERATION

REGISTER 0x10 = 0x0002

LEDs ARE PULSED AND PHOTODIODES ARE SAMPLED

STANDARD DATA COLLECTION

DEVICE POWER IS CYCLED BY INTERNAL STATE MACHINE.

Figure 24. State Machine Operation Flowchart

The ADPD105/ADPD106/ADPD107 operate in one of three

modes: standby, program, and normal sampling mode.

Standby mode is a power saving mode in which no data collection

occurs. All register values are retained in this mode. To place

the devices in standby mode, write 0x0 to Register 0x10,

Bits[1:0]. The devices power up in standby mode.

Program mode is used for programming registers. Always cycle

the ADPD105/ADPD106/ADPD107 through program mode

[14 + LOG

(

n

× N )] BITS

A A

2

UP TO 27 BITS

[14 + LOG (n )] BITS

UP TO 20 BITS

N

2

A

16-BIT CLIP

IF VAL ≤ (2 – 1)

VAL = VAL

16 BITS

16

N

A

16

ELSE VAL = 2 – 1

1

14 BITS

n

A

20-BIT CLIP

IF VAL ≤ (2 – 1)

20

n

A

n

A

VAL = VAL

20

ELSE VAL = 2 – 1

14-BIT

ADC

0

1

REGISTER

0x11[13]

[14 + LOG (n )] BITS

2

A

16-BIT

DATA

REGISTERS

32-BIT DATA

REGISTERS

UP TO 22 BITS

FIFO

ADC OFFSET

SAMPLE 1: TIME SLOT A

SAMPLE 1: TIME SLOT B

0

1

SAMPLE N : TIME SLOT A

A

SAMPLE N : TIME SLOT B

B

TIME SLOT A

TIME SLOT B

N

B

16-BIT CLIP

16

IF VAL ≤ (2 – 1)

NOTES

1. n AND n = NUMBER OF LED PULSES FOR TIME SLOT A AND TIME SLOT B.

N

B

VAL = VAL

A

B

[14 + LOG (n )] BITS

UP TO 20 BITS

16

16 BITS

2

B

ELSE VAL = 2 – 1

1

2. N AND N = NUMBER OF AVERAGES FOR TIME SLOT A AND TIME SLOT B.

A

B

[14 + LOG (n × N )] BITS

2 B B

UP TO 27 BITS

Figure 25. ADPD105/ADPD106/ADPD107 Datapath

Rev. A | Page 23 of 66

ADPD105/ADPD106/ADPD107

Data Sheet

LED Pulse and Sample

data is still acquired by the AFE at the sampling frequency,

f

_SAMPLE(Register 0x12), but new data is written to the registers at

At each sampling period, the selected LED driver drives a series

of LED pulses, as shown in Figure 26. The magnitude, duration,

and number of pulses are programmable over the I²C interface.

Each LED pulse coincides with a sensing period so that the sensed

value represents the total charge acquired on the photodiode in

response to only the corresponding LED pulse. Charge, such as

ambient light, that does not correspond to the LED pulse is

rejected.

the rate of f_SAMPLE/N every N^thsample. This new data consists of

the sum of the previous N samples. The full 32-bit sum is stored

in the 32-bit registers. However, before sending this data to the

FIFO, a divide by N operation occurs. This divide operation

maintains bit depth to prevent clipping on the FIFO.

Use this between sample averaging to lower the noise while

maintaining 16-bit resolution. If the pulse count registers are

kept to 8 or less, the 16-bit width is never exceeded. Therefore,

when using Register 0x15 to average subsequent pulses, many

pulses can be accumulated without exceeding the 16-bit word

width. This averaging can reduce the number of FIFO reads

required by the host processor.

After each LED pulse, the photodiode output relating the pulsed

LED signal is sampled and converted to a digital value by the

14-bit ADC. Each subsequent conversion within a sampling

period is summed with the previous result. Up to 255 pulse values

from the ADC can be summed in an individual sampling period.

There is a 20-bit maximum range for each sampling period.

Data Read

Averaging

The host processor reads output data from the ADPD105/

ADPD107 via the I²C protocol on the ADPD105 or the SPI port

on the ADPD107. Data is read from the data registers or from

the FIFO. New output data is made available every N samples,

where N is the user configured averaging factor. The averaging

factors for Time Slot A and Time Slot B are configurable

independently of each other. If they are the same, both time slots

can be configured to save data to the FIFO. If the two averaging

factors are different, only one time slot can save data to the FIFO;

data from the other time slot can be read from the output

registers.

The ADPD105/ADPD106/ADPD107 offer sample accumulation

and averaging functionality to increase signal resolution.

Within a sampling period, the AFE can sum up to 256 sequential

pulses. As shown in Figure 25, samples acquired by the AFE are

clipped to 20 bits at the output of the AFE. Additional resolution,

up to 27 bits, can be achieved by averaging between sampling

periods. This accumulated data of N samples is stored as 27-bit

values and can be read out directly by using the 32-bit output

registers or the 32-bit FIFO configuration.

When using the averaging feature set up by Register 0x15,

subsequent pulses can be averaged by powers of 2. The user can

select from 2, 4, 8 … up to 128 samples to be averaged. Pulse

The data read operations are described in more detail in the

Reading Data section.

SHOWN WITH f

= 10 Hz

SAMPLE

OPTICAL SAMPLING

LOCATIONS

0

0.5

1.0

1.5

2.0

2.5

3.0

TIME (s)

LED

CURRENT

(I

)

LED

NUMBER OF LED PULSES (n_AOR n_B

)

Figure 26. Example of a Photoplethysmography (PPG) Signal Sampled at a Data Rate of 10 Hz Using Five Pulses per Sample

Rev. A | Page 24 of 66

Data Sheet

ADPD105/ADPD106/ADPD107

important to verify proper AFE position for every new hardware

design or the LED width.

AFE OPERATION

The timing within each pulse burst is important for optimizing

the operation of the ADPD105/ADPD106/ADPD107. Figure 27

shows the timing waveforms for a single time slot as an LED pulse

response propagates through the analog block of the AFE. The

first graph, shown in green, shows the ideal LED pulsed output.

The filtered LED response, shown in blue, shows the output of

the analog integrator. The third graph, shown in orange, illustrates

an optimally placed integration window. When programmed to

the optimized value, the full signal of the filtered LED response

can be integrated. The AFE integration window is then applied to

the output of the band-pass filter (BPF) and the result is sent to

the ADC and summed for N pulses. If the AFE window is not

correctly sized or located, all of the receive signal is not properly

reported and system performance is not optimal; therefore, it is

AFE INTEGRATION OFFSET ADJUSTMENT

The AFE integration width must be equal or larger than the LED

width. As AFE width increases, the output noise increases and

the ability to suppress high frequency content from the environ-

ment decreases. It is therefore desirable to keep the AFE integration

width small. However, if the AFE width is too small, the LED

signal is attenuated. With most hardware selections, the AFE

width produces the optimal SNR at 1 ꢀs more than the LED

width. After setting LED width, LED offset, and AFE width, the

ADC offset can then be optimized. The AFE offset must be

manually set such that the falling edge of the first segment of the

integration window matches the zero crossing of the filtered LED

response.

LED WIDTH

REGISTER 0x30 [12:8]

REGISTER 0x35 [12:8]

N LED PULSES

REGISTER 0x31 [15:8]

LED PERIOD

REGISTER 0x36 [15:8]

REGISTER 0x31 [7:0]

LED DRIVE STRENGTH

LED OFFSET

REGISTER 0x36 [7:0]

REGISTER 0x30 [7:0]

REGISTER 0x35 [7:0]

LED PULSE

REGISTER 0x22, REGISTER 0x23,

REGISTER 0x24, REGISTER 0x25

FOR N PULSES

CONTROLLED BY:

TIA SETTINGS

AFE SETTINGS

REGISTER 0x42,

REGISTER 0x43,

REGISTER 0x44,

REGISTER 0x45

FILTERED LED

RESPONSE

9µs + AFE OFFSET

REGISTER 0x39 [10:0]

REGISTER 0x3B [10:0]

AFE INTEGRATION

WINDOW

FOR N PULSES

AFE

WIDTH

REGISTER 0x39 [15:11]

REGISTER 0x3B [15:11]

AFE

WIDTH

ADC

CONVERSION

ADC

CONVERSION

+

TIME (µs)

Figure 27. AFE Operation Diagram

Rev. A | Page 25 of 66

ADPD105/ADPD106/ADPD107

Data Sheet

AFE Integration Offset Starting Point

The register can be thought of as 2^{11 − 1}of these 31.25 ns steps, or

it can be broken into an AFE coarse setting using Bits[10:5] to

represent 1 μs steps and Bits[4:0] to represent 31.25 ns steps.

Sweeping the AFE position from the starting point to find a

local maximum is the recommended way to optimize the AFE

offset. The setup for this test is to allow the LED light to fall on

the photodiode in a static way. This test is typically done with a

reflecting surface at a fixed distance. The AFE position can then

be swept to look for changes in the output level. When adjusting

the AFE position, it is important to sweep the position using the

31.25 ns steps. Typically, a local maximum is found within 2 μs

of the starting point for most systems. Figure 28 shows an example

of an AFE sweep, where 0 on the x-axis represents the AFE starting

point defined previously. Each data point in Figure 28 corresponds

to one 31.25 ns step of the SLOTx_AFE_OFFSET. The optimal

location for SLOTx_AFE_OFFSET in this example is 0.687 μs

from the AFE starting point.

The starting point of this offset, as expressed in microseconds, is set

such that the falling edge of the integration window aligns with the

falling edge of the LED.

LED_FALLING_EDGE = SLOTx_LED_OFFSET +

SLOTx_LED_WIDTH

and,

AFE_INTEGRATION_FALLING_EDGE = 9 +

SLOTx_AFE_OFFSET + SLOTx_AFE_WIDTH

If both falling edges are set equal to each other, solve for

SLOTx_AFE_OFFSET to obtain the following equation:

AFE_OFFSET_STARTING_POINT = SLOTx_LED_

OFFSET + SLOTx_LED_WIDTH − 9 – SLOTx_AFE_

WIDTH

Setting the AFE offset to any point in time earlier than the

starting point is equivalent to setting the integration in the

future; the AFE cannot integrate the result from an LED pulse

that has not yet occurred. As a result, a SLOTx_AFE_OFFSET

value less than the AFE_OFFSET_STARTING_POINT value is an

erroneous setting. Such a result may indicate that current in the

TIA is operating in the reverse direction from intended, where

the LED pulse is causing the current to leave the TIA rather

than enter it.

100

0.687

95

90

85

80

75

Because, for most setups, the SLOTx_AFE_WIDTH is 1 μs

wider than the SLOTx_LED_WIDTH, the AFE_OFFSET_

STARTING_POINT value is typically 10 μs less than the

SLOTx_LED_OFFSET value. Any value less than SLOTx_LED_

OFFSET – 10 is erroneous. The optimal AFE offset is some time

after the AFE_OFFSET_STARTING_POINT value. The band-

pass filter response, LED response, and photodiode response

each add some delay. In general, the component choice, board

layout, SLOTx_LED_OFFSET, and SLOTx_LED_WIDTH are

the variables that can change the SLOTx_AFE_OFFSET value.

After a specific design is set, the SLOTx_AFE_OFFSET value

can be locked down and does not need to be optimized further.

0

0.15 0.30 0.45 0.60 0.75 0.90 1.05 1.20 1.35 1.50

AFE OFFSET FROM STARTING POINT (µs)

Figure 28. AFE Sweep Example

Table 18 lists some typical LED and AFE values after optimization.

In general, it is not recommended to use the SLOTx_AFE_OFFSET

numbers in Table 18 without first verifying them against the AFE

sweep method. Repeat this method for every new LED width and

with every new set of hardware made with the ADPD105/

ADPD107. For maximum accuracy, it is recommended that the

32 MHz clock be calibrated prior to sweeping the AFE.

Sweeping the AFE Position

The AFE offsets for Time Slot A and Time Slot B are controlled

by Bits[10:0] of Register 0x39 and Register 0x3B, respectively.

Each LSB represents one cycle of the 32 MHz clock, or 31.25 ns.

Table 18. AFE Window Settings

LED Register 0x30 or Register 0x35

AFE Register 0x39 or Register 0x3B

Comment

0x0219

0x0319

0x1A08

0x21FE

2 μs LED pulse, 3 μs AFE width, 25 μs LED delay

3 μs LED pulse, 4 μs AFE width, 25 μs LED delay

Rev. A | Page 26 of 66

Data Sheet

ADPD105/ADPD106/ADPD107

I²C SERIAL INTERFACE

4. Write the desired SLAVE_ADDRESS bits using Register 0x09,

Bits[7:1]. While writing to Register 0x09, Bits[7:1], write

0xAD to Register 0x09, Bit[15:8]. Register 0x09 must be

written to immediately after writing to Register 0x0D.

5. Repeat Step 1 to Step 4 for all the devices that need

SLAVE_ADDRESS changed.

The ADPD105 supports an I²C serial interface via the SDA

(data) and SCL (clock) pins. All internal registers are accessed

through the I²C interface. The ADPD105 is an I²C only device

and does not support an SPI.

The ADPD105 conforms to the UM10204 I²C-Bus Specification

and User Manual, Rev. 05—9 October 2012, available from NXP

Semiconductors. It supports a fast mode (400 kbps) data transfer.

Register read and write are supported, as shown in Figure 29.

Figure 3 shows the timing diagram for the I²C interface.

6. Set the GPIO0 and GPIO1 pins as desired for normal

operation using the new SLAVE_ADDRESS for each device.

I²C Write and Read Operations

Figure 29 illustrates the ADPD105 I²C write and read operations.

Single-word and multiword read operations are supported. For

a single register read, the host sends a no acknowledge (NACK)

after the second data byte is read and a new register address is

needed for each access.

Slave Address

The default 7-bit I²C slave address for the device is 0x64,

2

W

followed by the R/ bit. For a write, the default I C slave

address is 0xC8; for a read, the default I²C address is 0xC9. The

slave address is configurable by writing to Register 0x09, Bits[7:1].

When multiple ADPD105 devices are on the same bus lines, the

GPIO0 and GPIO1 pins can be used to select specific devices

for the address change. Register 0x0D can be used to select a

key to enable address changes in specific devices. Use the

following procedure to change the slave address when multiple

ADPD105 devices are connected to the same I²C bus lines:

For multiword operations, each pair of data bytes is followed by

an acknowledge from the host until the last byte of the last word

is read. The host indicates the last read word by sending a no

acknowledge. When reading from the FIFO (Register 0x60), the

data is automatically advanced to the next word in the FIFO

and the space is freed. When reading from other registers, the

register address is automatically advanced to the next register,

except at Register 0x5F or Register 0x7F, where the address does

not increment. This autoincrementing allows lower overhead

reading of sequential registers.

1. Using Register 0x4F, enable the input buffer of the GPIO1 pin,

the GPIO0 pin, or both, depending on the key being used.

2. For the device identified as requiring an address change,

set the GPIO0 and/or GPIO1 pins high or low to match the

key being used.

All register writes are single word only and require 16 bits (one

word) of data.

3. Write the SLAVE_ADDRESS_KEY bits using Register 0x0D,

Bits[15:0] to match the desired function. The allowed keys

are shown in Table 33.

The software reset (Register 0x0F, Bit 0) returns an acknowledge.

The device then returns to standby mode with all registers in

the default state.

Table 19. Definition of I²C Terminology

Term

Description

SCL

Serial clock.

SDA

Serial address and data.

Master

Slave

Start (S)

Start (Sr)

Stop (P)

ACK

The master is the device that initiates a transfer, generates clock signals, and terminates a transfer.

The slave is the device addressed by a master. The ADPD105 operates as a slave device.

A high to low transition on the SDA line while SCL is high; all transactions begin with a start condition.

Repeated start condition.

A low to high transition on the SDA line while SCL is high. A stop condition terminates all transactions.

During the acknowledge or no acknowledge clock pulse, the SDA line is pulled low and remains low.

During the acknowledge or no acknowledge clock pulse, the SDA line remains high.

After a start (S), a 7-bit slave address is sent, which is followed by a data direction bit (read or write).

A 1 indicates a request for data.

NACK

Slave Address

Read (R)

Write (W)

A 0 indicates a transmission.

Rev. A | Page 27 of 66

ADPD105/ADPD106/ADPD107

Data Sheet

2

I

C WRITE

REGISTER WRITE

MASTER START

SLAVE

SLAVE ADDRESS + WRITE

REGISTER ADDRESS

DATA[15:8]

DATA[7:0]

STOP

ACK

2

I

C SINGLE WORD READ MODE

REGISTER READ

MASTER START

SLAVE

ACK

SLAVE ADDRESS + WRITE

REGISTER ADDRESS

Sr

SLAVE ADDRESS + READ

NACK

STOP

ACK

DATA[15:8]

ACK

DATA[7:0]

2

I

C MULTIWORD READ MODE

REGISTER READ

MASTER START

SLAVE

ACK/NACK

SLAVE ADDRESS + WRITE

ACK

DATA[7:0]

DATA TRANSFERRED

n (DATA[15:8]+ACK+DATA[7:0] + ACK/NACK)

NOTES

1. THE SHADED AREAS REPRESENT WHEN THE DEVICE IS LISTENING.

Figure 29. I²C Write and Read Operations

SPI PORT

The first byte written in a SPI transaction is a 7-bit address,

which is the location of the address being accessed, followed by

The ADPD106 and ADPD107 are SPI only devices. They do not

support the I²C interface. The SPI port uses a 4-wire interface,

the W/ bit. This bit determines whether the communication is

R

CS

consisting of the , MOSI, MISO, and SCLK signals, and it is

a write (Logic Level 1) or a read (Logic Level 0). This format is

shown in Table 21.

CS

always a slave port. The

signal goes low at the beginning of a

transaction and high at the end of a transaction. The SCLK signal

latches MOSI on a low to high transition. The MISO data is shifted

out of the device on the falling edge of SCLK and must be clocked

into a receiving device, such as a microcontroller, on the SCLK

rising edge. The MOSI signal carries the serial input data, and

the MISO signal carries the serial output data. The MISO signal

remains three state until a read operation is requested, which

allows other SPI-compatible peripherals to share the same MISO

line. All SPI transactions have the same basic format shown in

Table 20. A timing diagram is shown in Figure 4. Write all data

MSB first.

R

Bit 4

Table 21. SPI Address and Write/ Byte Format

Bit 0

Bit 1

Bit 2

Bit 3

Bit 5

Bit 6

Bit 7

A6

A5

A4

A3

A2

A1

A0

W/R

The format for the SPI communications slave port is commonly

known as SPI Mode 3, where clock polarity (CPOL) = 1 and

clock phase (CPHA) = 1 (see Figure 30). The base value of the

clock is 1. Data is captured on the rising edge of the clock, and

data is propagated on the falling edge.

The maximum read and write speed for the SPI slave port is

10 MHz.

Table 20. Generic Control Word Sequence

Byte 0

Byte 1

Byte 2

Subsequent Bytes

Address[6:0], Data[15:8]

W/R

Data[7:0]

Data[15:8], Data[7:0]

SCLK

(CPOL = 1)

CS

1

2

3

4

5

6

7

8

CYCLE #

MISO

Z

(CPHA = 1)

MOSI

Figure 30. Clock Polarity and Phase for the SPI Slave Port (CPOL = 1, CPHA = 1)

Rev. A | Page 28 of 66

Data Sheet

ADPD105/ADPD106/ADPD107

A sample timing diagram for a multiple word SPI write operation

to a register is shown in Figure 31. A sample timing diagram of

a single-word SPI read operation is shown in Figure 32. The

MISO pin transitions from being three-state to being driven

read operation is shown in Figure 33. In Figure 31 to Figure 33,

rising edges on SCLK are indicated with an arrow, signifying

that the data lines are sampled on the rising edge.

When performing multiple word reads or writes, the data

address is automatically incremented to the next consecutive

address for subsequent transactions except for Address 0x5F,

Address 0x60 (FIFO), and Address 0x7F.

R

following the reception of a valid bit. In this example, Byte 0

R

contains the address and the W/ bit, and subsequent bytes

carry the data. A sample timing diagram of a multiple word SPI

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22

CS

SCLK

MOSI

ADDRESS[6:0]

DATA BYTE 1

DATA BYTE 2

DATA BYTE N

W/R

Figure 31. SPI Slave Write Clocking (Burst Write Mode, N Bytes)

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

CS

SCLK

MOSI

MISO

ADDRESS[6:0]

W/R

DATA BYTE 1

DATA BYTE 2

Figure 32. SPI Slave Read Clocking (Single-Word Mode, Two Bytes)

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22

CS

SCLK

MOSI

MISO

ADDRESS[6:0]

W/R

DATA BYTE 1

DATA BYTE 2

DATA BYTE N

Figure 33. SPI Slave Read Clocking (Burst Read Mode, N Bytes)

Rev. A | Page 29 of 66

ADPD105/ADPD106/ADPD107

Data Sheet

1.8V

TYPICAL CONNECTION DIAGRAM

ADPD105

Figure 34 shows a typical circuit used for wrist-based heart rate

measurement with the ADPD105 WLCSP using a green LED.

The 1.8 V I²C communication lines, SCL and SDA, along with

the GPIO0 and GPIO1 lines, connect to a system

DVDD

PDC

0.1µF

1.8V

AVDD

0.1µF

PD1-2

PD3-4

AGND

DGND

LGND

VLED

microprocessor or sensor hub. The I²C signals can have pull-up

resistors connected to a 1.8 V or a 3.3 V power supply. The

GPIO0 and GPIO1 signals are only compatible with a 1.8 V

supply and may need a level translator. The circuit shown in

Figure 34 is identical for the ADPD107, except the I²C interface

is replaced by an SPI. There are multiple ways to connect

photodiodes to the 8-channel ADPD105 LFCSP, as shown in

Table 22 and Figure 37. The photodiode anodes are connected

to the PD1 to PD8 input pins and the photodiode cathodes are

connected to the cathode pin, PDC.

10kΩ 10kΩ

4.7µF

SCL

SDA

TO DIGITAL

INTERFACE

LEDX1

VREF

GPIO0

GPIO1

1µF

Figure 34. Typical Wrist-Based HRM Measurement

1

2

3

A

B

LGND

LEDX2

Provide the 1.8 V supply, V_DD, to AVDD and DVDD. The LED

supply uses a standard regulator circuit according to the peak

current requirements specified in Table 3 and calculated in the

LED Driver Pins and LED Supply Voltage section.

SDA

LEDX3

SCL

LEDX1

GPIO0

DGND

VREF

C

D

E

F

DVDD

AGND

For best noise performance, connect AGND, DGND, and

LGND together at a large conductive surface, such as a ground

plane, a ground pour, or a large ground trace.

The number of photodiodes or LEDs used varies depending on

the application as well as the dynamic range and SNR required.

For example, in an application where a single, large photodiode

is used, the dynamic range can be increased by splitting the current

between multiple inputs. This is achieved by connecting the anode

of the photodiode to multiple channels so that the current can

be split evenly among the number of channels connected,

effectively increasing the dynamic range over a single channel

configuration. Alternatively, in situations where the photodiode is

small or the signal is greatly attenuated, SNR can be maximized

by connecting the anode of the photodiode to just a single channel.

It is important to leave the unused input floating for proper device

operation.

GPIO1

PD1-2

AVDD

PD3-4

PDC

Figure 35. ADPD105 Connection and PCB Layout Diagram (Top View)

1

2

3

A

B

LEDX2

LGND

Figure 35 and Figure 36 show the recommended connection

diagram and printed circuit board (PCB) layout for the

ADPD105 and ADPD107, respectively. The current input pins,

PD1-2 and PD3-4, have a typical voltage of 1.3 V during the

sampling period. During the sleep period, these pins are

connected to the cathode pin. The cathode and anode voltages

are listed in Table 3.

GPIO0

DGND

SCLK

VREF

PD3-4

LEDX3

GPIO1

LEDX1

MISO

C

MOSI

D

E

CS

AGND

AVDD

PD1-2

F

PDC

Figure 36. ADPD107 Connection and PCB Layout Diagram, Dashed Line

Traces From Blind Vias (Top View)

Rev. A | Page 30 of 66

Data Sheet

ADPD105/ADPD106/ADPD107

PD1

7

PD1

PD8

7

15

14

15

14

15

14

15

14

8

PD1

7

PD8

7

15

14

15

14

PD1

PD8

7

15

14

8

Figure 37. Photodiode Configuration Options for the ADPD105 LFCSP

Table 22. Typical Photodiode Anode to Input Channel Connections for the ADPD105 LFCSP^{1, 2}

Input Channel

Photodiode Anode Configuration

PD1

D1

NC

D1

NC

D1

NC

D1

PD2

NC

D1

NC

D1

D2

NC

D2

PD3

NC

D1

NC

D1

D3

NC

D3

PD4

NC

D1

NC

D1

D4

NC

D4

PD5

NC

D1

NC

D1

D2

NC

D1

D5

PD6

NC

D1

NC

D2

NC

D2

D6

PD7

NC

D1

NC

D2

NC

D3

D7

PD8

NC

D1

NC

D2

NC

D4

D8

Single Photodiode (PD1)

Two Photodiodes (PD1, PD2)

Four Photodiodes (PD1 to PD4)

Eight Photodiodes (PD1 to PD8)

¹Dx refers to the diode connected to the specified channel.

²NC means do not connect under the conditions provided in Table 21. Leave all unused inputs floating.

requirements for the bypass capacitor (C_VLED) and the supply

voltages of the LEDs (V_LEDx).

LED DRIVER PINS AND LED SUPPLY VOLTAGE

The LEDX1, LEDX2, and LEDX3 pins have an absolute maximum

voltage rating of 3.6 V. Any voltage exposure over this rating affects

the reliability of the device operation and, in certain circumstances,

causes the device to cease proper operation. The voltage of the

LEDx pins must not be confused with the supply voltages for the

LED themselves (V_LEDx). V_LEDxis the voltage applied to the anode of

the external LED, whereas the LEDXx pin is the input of the

internal current driver, and the pins are connected to the

cathode of the external LED.

ADPD105/

ADPD106/

V

LEDx

SUPPLY

ADPD107

C

VLED

LGND

LEDx

Figure 38. V_LEDxSupply Schematic

DETERMINING THE AVERAGE CURRENT

The ADPD105/ADPD106/ADPD107 drive an LED in a series of

short pulses. Figure 39 shows the typical ADPD105/ADPD106/

ADPD107 configuration of a pulse burst sequence.

19µs

LED DRIVER OPERATION

The LED driver for the ADPD105/ADPD106/ADPD107 is a

current sink. The compliance voltage, measured at the driver

pin with respect to ground, required to maintain the

3µs

programmed LED current level is a function of the current

required. Figure 15 shows the typical compliance voltages

required at the various coarse LED settings. Figure 38 shows the

basic schematic of how the ADPD105/ADPD106/ADPD107

connect to an LED through the LED driver. The Determining the

Average Current and the Determining CVLED sections define the

I

LED_MAX

Figure 39. Typical LED Pulse Burst Sequence Configuration

Rev. A | Page 31 of 66

ADPD105/ADPD106/ADPD107

Data Sheet

In this example, the LED pulse width, t_{LED_PULSE}, is 3 μs, and the

LED pulse period, t_{LED_PERIOD}, is 19 μs. The LED being driven is a

pair of green LEDs driven to a 250 mA peak. The goal of C_VLED

is to buffer the LED between individual pulses. In the worst case

scenario, where the pulse train shown in Figure 39 is a continuous

sequence of short pulses, the V_LEDxsupply must supply the

average current. Therefore, calculate I_{LED_AVERAGE}as follows:

To correctly size the C_VLEDcapacitor, do not deplete it during the

pulse of the LED to the point where the voltage on the capacitor is

less than the forward bias on the LED. To calculate the minimum

value for the V_LEDxbypass capacitor, use the following equation:

t_{LED_PULSE} I_{LED_ MAX}

(2)

C_VLED



V_{LED_ MIN}(V_{FB _ LED_ MAX} 0.2)

where:

_{LED_PULSE}is the LED pulse width.

_{LED_MAX}is the maximum forward-biased current on the LED

used in operating the device.

I

_{LED_AVERAGE}= (t_{LED_PULSE}/t_{LED_PERIOD}) × I_{LED_MAX}

where:

_{LED_AVERAGE}is the average current needed from the V_LEDxsupply

(1)

t

I

during the pulse period, and it is also the V_LEDxsupply current

rating.

_{LED_MAX}is the peak current setting of the LED.

For the numbers shown in Equation 1, I_{LED_AVERAGE}= 3/19 ×

_{LED_MAX}. For typical LED timing, the average V_LEDxsupply

V

_{LED_MIN}is the lowest voltage from the VLEDx supply with no load.

_{FB_LED_MAX}is the maximum forward-biased voltage required on

I

the LED to achieve I_{LED_MAX}

.

The numerator of the C_VLEDequation sets up the total discharge

amount in coulombs from the bypass capacitor to satisfy a

single programmed LED pulse of the maximum current. The

denominator represents the difference between the lowest voltage

from the V_LEDxsupply and the LED required voltage. The LED

required voltage is the voltage of the anode of the LED such that

the 0.2 V compliance of the LED driver and the forward-biased

voltage of the LED operating at the maximum current is satisfied.

For a typical ADPD105/ADPD106/ADPD107 example, assume

that the lowest value for the V_LEDxsupply is 4.4 V, and that the

peak current is 250 mA for two 528 nm LEDs in parallel. The

minimum value for C_VLEDis then equal to 3 μF.

I

current is 3/19 × 250 mA = 39.4 mA, indicating that the V_LEDx

supply must support a dc current of 40 mA.

DETERMINING C_VLED

To determine the C_VLEDcapacitor value, determine the maximum

forward-biased voltage, V_{FB_LED_MAX}, of the LED in operation.

The LED current, I_{LED_MAX}, converts to V_{FB_LED_MAX}as shown in

Figure 40. In this example, 250 mA of current through two green

LEDs in parallel yields V_{FB_LED_MAX}= 3.95 V. Any series resistance

in the LED path must also be included in this voltage. When

designing the LED path, keep in mind that small resistances can

add up to large voltage drops due to the LED peak current being

very large. In addition, these resistances can be unnecessary

constraints on the V_LEDxsupply.

C

_VLED= (3 × 10⁻⁶× 0.250)/(4.4 – (3.95 + 0.2)) = 3 μF

(3)

As shown in the Equation 3, as the minimum supply voltage drops

close to the maximum anode voltage, the demands on C_VLED

become more stringent, forcing the capacitor value higher. It is

important to insert the correct values into Equation 2, Equation 2,

4.5

TWO 528nm LEDs

ONE 850nm LED

4.0

3.5

3.0

2.5

2.0

1.5

1.0

and Equation 3. For example, using an average value for V_LED

_

MIN

instead of the worst case value for V_LED__MINcan cause a serious

design deficiency, resulting in a C_VLEDvalue that is too small and

that causes insufficient optical power in the application. Therefore,

adding a sufficient margin on C_VLEDis strongly recommended. Add

additional margin to C_VLEDto account for derating of the capacitor

value over voltage, bias, temperature, and other factors over the life

of the component.

LED INDUCTANCE CONSIDERATIONS

The LED drivers (LEDXx) on the ADPD105/ADPD106/ADPD107

have configurable slew rate settings (Register 0x22, Bits[6:4],

Register 0x23, Bits[6:4], and Register 0x24, Bits[6:4]). These slew

rates are defined in Table 3. Even at the lowest setting, careful

consideration must be taken in board design and layout. If a large

series inductor, such as a long PCB trace, is placed between the

LED cathode and one of the LEDXx pins, voltage spikes from

the switched inductor can cause violations of absolute maximum

and minimum voltages on the LEDXx pins during the slew

portion of the LED pulse.

0

50

100

150

200

250

LED DRIVER CURRENT SETTING (mA)

Figure 40. Example of the Average LED Forward-Bias Voltage Drop as a

Function of the Driver Current

Rev. A | Page 32 of 66

Data Sheet

ADPD105/ADPD106/ADPD107

To verify that there are no voltage spikes on the LEDXx pins due

to parasitic inductance, use an oscilloscope on the LEDXx pins to

monitor the voltage during normal operation. Any positive spike

>3.6 V may damage the devices.

READING DATA

The ADPD105/ADPD106/ADPD107 provide multiple methods

for accessing the sample data. Each time slot can be independently

configured to provide data access using the FIFO or the data

registers. Interrupt signaling is also available to simplify timely data

access. The FIFO is available to loosen the system timing

requirements for data accesses.

In addition, a negative spike <−0.3 V may also damage the devices.

RECOMMENDED START-UP SEQUENCE

At power-up, the device is in standby mode (Register 0x10 =

0x0), as shown in Figure 24. The ADPD105/ADPD106/

ADPD107 do not require a particular power-up sequence.

Reading Data Using the FIFO

The ADPD105/ADPD106/ADPD107 include a 128-byte FIFO

memory buffer that can be configured to store data from either

or both time slots. Register 0x11 selects the kind of data from

each time slot to be written to the FIFO. Note that both time

slots can be enabled to use the FIFO, but only if their output

data rate is the same.

From standby mode, to begin measurement, initiate the

ADPD105/ADPD106/ADPD107 as follows:

1. Set the CLK32K_EN bit (Register 0x4B, Bit 7) to start the

sample clock (32 kHz clock). This clock controls the state

machine. If this clock is off, the state machine is not able to

transition as defined by Register 0x10.

2. Write 0x1 to Register 0x10 to force the device into program

mode. Step 1 and Step 2 can be swapped, but the actual

state transition does not occur until both steps occur.

3. Write additional control registers in any order while the

device is in program mode to configure the devices as

required.

Output data rate = f_SAMPLE/N

where:

f

_SAMPLEis the sampling frequency.

N is the averaging factor for each time slot (N_Afor Time Slot A

and N_Bfor Time Slot B). In other words, N_A= N_Bmust be true

to store data from both time slots in the FIFO.

Data packets are written to the FIFO at the output data rate. A

data packet for the FIFO consists of a complete sample for each

enabled time slot. Data for each photodiode channel can be stored

as either 16 or 32 bits. Each time slot can store 2, 4, 8, or 16 bytes of

data per sample, depending on the mode and data format. To

ensure that data packets are intact, new data is only written to

the FIFO if there is sufficient space for a complete packet. Any

new data that arrives when there is not enough space is lost.

The FIFO continues to store data when sufficient space exists.

Always read FIFO data in complete packets to ensure that data

packets remain intact.

4. Write 0x2 to Register 0x10 to start normal sampling

operation.

To terminate normal operation, follow this sequence to place

the ADPD105/ADPD106/ADPD107 in standby mode:

1. Write 0x1 to Register 0x10 to force the devices into

program mode.

2. Write to the registers in any order while the devices are in

program mode.

3. Write 0x00FF to Register 0x00 to clear all interrupts. If

desired, clear the FIFO as well by writing 0x80FF to

Register 0x00.

4. Write 0x0 to Register 0x10 to force the devices into standby

mode.

5. Optionally, stop the 32 kHz clock by resetting the CLK32K_

EN bit (Register 0x4B, Bit 7). Register 0x4B, Bit 7 = 0 is the

only write that must be written when the device is in standby

mode (Register 0x10 = 0x0). If 0 is written to this bit while in

program mode or normal mode, the devices become

unable to transition into any other mode, including standby

mode, even if they are subsequently written to do so. As a

result, the power consumption in what appears to be standby

mode is greatly elevated. For this reason, and due to the very

low current draw of the 32 kHz clock while in operation, it

is recommended from an ease of use perspective to keep the

32 kHz clock running after it is turned on.

The number of bytes currently stored in the FIFO is available in

Register 0x00, Bits[15:8]. A dedicated FIFO interrupt is also

available and automatically generates when a specified amount

of data is written to the FIFO.

Interrupt-Based Method

To read data from the FIFO using an interrupt-based method,

use the following procedure:

1. In program mode, set the configuration of the time slots as

desired for operation.

2. Write Register 0x11 with the desired data format for each

time slot.

3. Set FIFO_THRESH in Register 0x06, Bits[13:8] to the

interrupt threshold. A recommended value for this is the

number of 16-bit words in a data packet, minus 1. This

causes an interrupt to generate when there is at least one

complete packet in the FIFO.

4. Enable the FIFO interrupt by writing a 0 to the FIFO_

INT_MASK in Register 0x01, Bit 8. Also, configure the

interrupt pin (GPIO0) by writing the appropriate value to

the bits in Register 0x02.

Rev. A | Page 33 of 66

ADPD105/ADPD106/ADPD107

Data Sheet

5. Enter normal operation mode by setting Register 0x10 to 0x2.

6. When an interrupt occurs

write 0 to Bit 5. To enable the interrupt for Time Slot B,

write 0 to Bit 6. Either or both interrupts can be set.

2. Configure the interrupt pin (GPIOx) by writing the

appropriate value to the bits in Register 0x02.

3. An interrupt generates when the data registers are updated.

4. The interrupt handler must perform the following:

a. Read Register 0x00 and observe Bit 5 or Bit 6 to confirm

which interrupt has occurred. This step is not required if

only one interrupt is in use.

a. There is no requirement to read the FIFO_SAMPLES bits,

because the interrupt is generated only if there is one or

more full packets. Optionally, the interrupt routine can

check for the presence of more than one available

packet by reading these bits.

b. Read a complete packet using one or more multiword

accesses using Register 0x60. Reading the FIFO

automatically frees the space for new samples.

b. Read the data registers before the next sample can be

written. The system must have interrupt latency and

service time short enough to respond before the next

data update, based on the output data rate.

c. Write a 1 to Bit 5 or Bit 6 in Register 0x00 to clear the

interrupt.

The FIFO interrupt automatically clears immediately upon

reading any data from the FIFO and is set again only when the

FIFO is written and the number of words is above the threshold.

Polling Method

To read data from the FIFO in a polling method, use the

following procedure:

If both time slots are in use, it is possible to use only the

Time Slot B interrupt to signal when all registers can be read. It

is recommended to use the multiword read to transfer the data

from the data registers.

1. In program mode, set the configuration of the time slots as

desired for operation.

2. Write Register 0x11 with the desired data format for each

time slot.

3. Enter normal operation mode by setting Register 0x10 to 2.

Reading Data from Registers Without Interrupts

If the system interrupt response is not fast or predictable enough to

use the interrupt method, or if the interrupt pin (GPIOx) is not

used, it is possible to obtain reliable data access by using the data

hold mechanism. To guarantee that the data read from the registers

is from the same sample time, it is necessary to prevent the

update of samples while reading the current values. The method

for doing register reads without interrupt timing is as follows:

Next, begin the polling operations.

1. Wait for the polling interval to expire.

2. Read the FIFO_SAMPLES bits (Register 0x00, Bits[15:8]).

3. If FIFO_SAMPLES ≥ the packet size, read a packet using

the following steps:

a. Read a complete packet using one or more multiword

accesses via Register 0x60. Reading the FIFO

automatically frees the space for new samples.

b. Repeat Step 1.

1. Write a 1 to SLOTA_DATA_HOLD or SLOTB_DATA_

HOLD (Register 0x5F, Bit 1 and Bit 2, respectively) for the

time slot requiring access (both time slots can be accessed).

This setting prevents sample updates.

2. Read the registers as desired.

When a mode change is required, or any other disruption to

normal sampling is necessary, the FIFO must be cleared. Use

the following procedure to clear the state and empty the FIFO:

3. Write a 0 to the SLOTA_DATA_HOLD or SLOTB_DATA_

HOLD bits (Register 0x5F, Bit 1 and Bit 2, respectively)

previously set. Sample updates are allowed again.

1. Enter program mode by setting Register 0x10 to 0x1.

2. Write 1 to Register 0x00, Bit 15.

Because a new sample may arrive while the reads are occurring,

this method prevents the new sample from partially overwriting

the data being read.

Reading Data from Registers Using Interrupts

The latest sample data is always available in the data registers and is

updated simultaneously at the end of each time slot. The data value

for each photodiode channel is available as a 16-bit value in Regis-

ter 0x64 through Register 0x67 for Time Slot A, and Register 0x68

through Register 0x6B for Time Slot B. If allowed to reach their

maximum value, Register 0x64 through Register 0x6B clip. If

Register 0x64 through Register 0x6B saturate, the unsaturated (up

to 27 bits) values for each channel are available in Register 0x70

through Register 0x77 for Time Slot A and Register 0x78 through

Register 0x7F for Time Slot B. Sample interrupts are available to

indicate when the registers are updated and can be read. To use

the interrupt for a given time slot, use the following procedure:

CLOCKS AND TIMING CALIBRATION

The ADPD105/ADPD106/ADPD107 operate using two internal

time bases: a 32 kHz clock sets the sample timing, and a 32 MHz

clock controls the timing of the internal functions such as LED

pulsing and data capture. Both clocks are internally generated

and exhibit device to device variation of approximately 10%

(typical).

Heart rate monitoring applications require an accurate time

base to achieve an accurate count of beats per minute. The

ADPD105/ADPD106/ADPD107 provide a simple calibration

procedure for both clocks.

1. Enable the sample interrupt by writing a 0 to the appropriate

bit in Register 0x01. To enable the interrupt for Time Slot A,

Rev. A | Page 34 of 66

Data Sheet

ADPD105/ADPD106/ADPD107

Calibrating the 32 kHz Clock

OPTIONAL TIMING SIGNALS AVAILABLE ON

GPIO0 AND GPIO1

Calibrating the 32 kHz clock also calibrates items associated

with the output data rate. Calibration of this clock is important

for applications where an accurate data rate is important, such

as heart rate measurements.

The ADPD105/ADPD106/ADPD107 provide a number of

different timing signals, available via the GPIO0 and GPIO1 pins,

to enable ease of system synchronization and flexible triggering

options. Each of the GPIOx pins can be configured as an open-

drain output if they are to share the bus with other drivers, or

they can be configured to always drive the bus. Both outputs

also have polarity control in situations where a timing signal

must be inverted from the default.

To calibrate the 32 kHz clock,

1. Set the sampling frequency to the highest the system can

handle, such as 2000 Hz. Because the 32 kHz clock controls

sample timing, its frequency is readily accessible via the

GPIO0 pin. Configure the interrupt by writing the appropriate

value to the bits in Register 0x02 and set the interrupt to occur

at the sampling frequency by writing 0 to Register 0x01,

Bit 5 or Bit 6. Monitor the GPIO0 pin. The interrupt

frequency must match the set sample frequency.

2. If the monitored interrupt frequency is less than the set

sampling frequency, increase the CLK32K_ADJUST bit

(Register 0x4B, Bits[5:0]). If the monitored interrupt

frequency is larger than the set sampling frequency,

decrease the CLK32K_ADJUST bits.

Table 23. GPIOx Control Settings

Pin Name

Register[Bits] Setting Description

GPIO0

0x02[0]

0x02[1]

0x02[2]

0x02[8]

0x02[9]

0x4F[6]

0: polarity active high

1: polarity active low

0: always drives the bus

1: drives the bus when asserted

0: disables the GPIO0 pin drive

1: enables the GPIO0 pin drive

0: polarity active high

1: polarity active low

0: always drives the bus

GPIO1

3. Repeat Step b until the monitored interrupt signal

frequency is close enough to the set sampling frequency.

1: drives the bus when asserted

0: disables the GPIO1 pin drive

1: enables the GPIO1 pin drive

Calibrating the 32 MHz Clock

Calibrating the 32 MHz clock also calibrates items associated

with the fine timing within a sample period, such as LED pulse

width and spacing, assuming that the 32 kHz clock has been

calibrated.

The various available timing signals are controlled by the

settings in Register 0x0B. Bits[12:8] of this register control the

timing signals available on GPIO1, and Bits[4:0] control the

timing signals available on GPIO0. All of the timing signals

described in this data sheet are available on either (or both) of

the GPIO0 and GPIO1 pins. Timing diagrams are shown in

Figure 41 and Figure 42. The time slot settings used to generate

the timing diagrams are described in Table 24.

To calibrate the 32 MHz clock,

1. Write 0x1 to Register 0x5F, Bit 0.

2. Enable the CLK_RATIO calculation by writing 0x1 to

Register 0x50, Bit 5. This function counts the number of

32 MHz clock cycles in two cycles of the 32 kHz clock.

With this function enabled, this cycle value is stored in

Register 0x0A, Bits[11:0] and nominally this ratio is 2000

(0x7D0).

Table 24. ADPD105/ADPD106/ADPD107 Settings Used for

Timing Diagrams Shown in Figure 41 and Figure 42

Register Setting Description

3. Calculate the 32 MHz clock error as follows:

0x31

0x36

0x15

0x0118 Time Slot A: 1 LED pulse

0x0418 Time Slot B: 4 LED pulses

0x0120 Time Slot A decimation = 4, Time Slot B

decimation = 2

Clock Error = 32 MHz × (1 − CLK_RATIO/2000)

4. Adjust the frequency by setting Bits[7:0] in Register 0x4D

per the following equation:

CLK32M_ADJUST = Clock Error/109 kHz

5. Write 0x0 to Register 0x50, Bit 5 to reset the CLK_RATIO

function.

Repeat Step 2 through Step 5 until the desired accuracy is

achieved.

Write 0x0 to Register 0x5F, Bit 0. Also, set the GPIO0 pin back

to the mode desired for normal operation.

Rev. A | Page 35 of 66

ADPD105/ADPD106/ADPD107

Data Sheet

SLEEP

SLOT A

SLOT B

SLOT A

SLOT B

0x02

0x05

0x06

0x07

0x0F

Figure 41. Optional Timing Signals Available on GPIOx—Register 0x0B, Bits[12:8] or Bits[4:0] = 0x02, 0x05, 0x06, 0x07, and 0x0F

SLEEP

SLOT A/B

SLEEP

SLOT A/B

SLEEP

0x02

0x0C

0x0D

0x0E

Figure 42. Optional Timing Signals Available on GPIOx—Register 0x0B, Bits[12:8] or Bits[4:0] = 0x02, 0x0C, 0x0D, and 0x0E

ADPD103 Backward Compatibility

Pulse Outputs

Setting Register 0x0B = 0 provides backward compatibility to

the ADPD103. The GPIO0 pin mirrors the functionality of the

ADPD103 INT pin. The GPIO1 pin mirrors the functionality of

the ADPD103 PDSO pin.

Three options are available to provide a copy of the LED pulse

outputs. Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x05

provides a copy of the Time Slot A LED pulses on the respective

pin. A setting of 0x06 provides the Time Slot B pulses, and a

setting of 0x07 provides the pulse outputs of both time slots.

Interrupt Function

Output Data Cycle Signal

Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x01 configures

the respective pin to perform the interrupt function as defined

by the settings in Register 0x01.

There are three options available to provide a signal that

indicates when the output data is written to the output data

registers or to the FIFO. Setting Register 0x0B, Bits[12:8] or

Bits[4:0] = 0x0C provides a signal that indicates that a data

value is written for Time Slot A. A setting of 0x0D provides a

signal that indicates that a data value is written for Time Slot B,

and 0x0E provides a signal to indicate that a value is written for

either time slot. The signal asserts at the end of the time slot,

when the output data is already written, and deasserts at the

start of the subsequent sample. This timing signal is especially

useful in situations where the FIFO is being used. For example,

one of the GPIOx pins can be configured to provide an interrupt

after the FIFO reaches the FIFO threshold set in Register 0x06,

Bits[13:8], while the other GPIOx pin can be configured to

provide the output data cycle signal. This signal can be used to

trigger a peripheral device, such as an accelerometer, so that

time aligned signals are provided to the processor.

Sample Timing

Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x02 configures

the respective pin to provide a signal that asserts at the beginning

of the first time slot of the current sample and deasserts at the

end of the last time slot of the current sample. For example, if

both time slots are enabled, this signal asserts at the beginning

of Time Slot A and deasserts at the end of Time Slot B. If only a

single time slot is enabled, the signal asserts at the beginning of

the enabled time slot and deasserts at the end of this same time slot.

Rev. A | Page 36 of 66

Data Sheet

ADPD105/ADPD106/ADPD107

f_S/2 Output

CALCULATING CURRENT CONSUMPTION

Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x0F configures

the respective pin to provide a signal that toggles at half the

sampling rate. This timing signal is useful in, for example,

situations where more than two LEDs per sample are required.

This signal can be used as a select signal to a multiplexer being

used to mux two LEDs into a single LED driver, providing the

ability to drive up to four separate LEDs per sample period. In

such a case, the ADPD105/ADPD106/ADPD107 are operated at

2× the sampling rate and the LED settings can be reconfigured

during the sleep period between samples. If identical LED settings

(current and timing) are used for the LEDs being muxed, then

up to four LEDs can be sampled per sampling period without

host inter-vention. An example of this configuration is shown in

Figure 43.

The current consumption of the ADPD105/ADPD106/ADPD107

depends on the user selected operating configuration, as

determined by the following equations.

Total Power Consumption

To calculate the total power consumption, use Equation 4.

Total Power = I_{VDD_AVG}× V_DD+ I_{LEDA_AVG}× V_LEDA

_{LEDB_AVG}× V_LEDB

Average V_DDSupply Current

To calculate the average V_DDsupply current, use Equation 5.

_{VDD_AVG}= DR × ((I_{AFE_A}× t_SLOTA) + (I_{AFE_B}× t_SLOTB) +

+

I

(4)

(5)

I

Q_{PROC_X}) + I_{VDD_STANDBY}

where:

DR is the data rate in Hz.

_{VDD_STANDBY}= 0.2 μA.

_{PROC_X}is an average charge associated with a processing time,

The f_S/2 timing signal always starts in an active low state when

the device switches from standby mode to normal operating

mode and transitions to a high state at the completion of the

first sample.

I

Q

as follows:

When only Time Slot A is enabled,

Q

_{PROC_A}(C) = 0.135 × 10⁻⁶+ (186 × 10⁻⁶× (2.69 × 10⁻³+

(6.2 × 10⁻³/SCALE_A × I_{LEDA_PK}))

When only Time Slot B is enabled,

Q

_{PROC_B}(C) = 0.135 × 10⁻⁶+ (134 × 10⁻⁶× (2.69 × 10⁻³+

(6.2 × 10⁻³/SCALE_A × I_{LEDA_PK}))

When Time Slot A and Time Slot B are enabled,

Q

_{PROC_AB}(C) = 0.135 × 10⁻⁶+ (206 × 10⁻⁶× (2.69 × 10⁻³+

(6.2 × 10⁻³/SCALE_A × I_{LEDA_PK}))

_{AFE_x}(A) = 3.0 × 10⁻³+ (1.5 × 10⁻³× NUM_CHANNELS) +

Figure 43. Example Using the f_S/2 Timing Signal

I

Logic 0 Output

(5.7 × 10⁻³/SCALE_X × I_{LEDX_PK}

_SLOTx(sec) = LEDx_OFFSET + LEDx_PERIOD ×

PULSE_COUNT

where:

NUM_CHANNELS is the number of active channels.

_{LEDX_PK}is the peak LED current, expressed in amps, for whichever

LED is enabled in that particular timeslot. Note that in the Q_PROC

calculations, the processing charge only scales as a function of

the LED current setting for the LED configured to operate in

Time Slot A, regardless of whether or not Time Slot A is enabled.

For this reason, be sure to minimize the LED peak current for

the Time Slot A LED to save power when Time Slot A is not

being used.

)

(6)

Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x10 configures

the respective pin to provide a Logic 0 output.

t

(7)

Logic 1 Output

Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x11 configures

the respective pin to provide a Logic 1 output.

I

32 kHz Oscillator Output

Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x13 configures

the respective pin to provide a copy of the on-board 32 kHz

oscillator.

SCALE_X is the scale factor for the LED current drive determined

by Bit 13 of the LEDX_DRV registers: Register 0x22, Register 0x23,

and Register 0x24.

LEDx_OFFSET is the pulse start time offset expressed in

seconds.

LEDx_PERIOD is the pulse period expressed in seconds.

PULSE_COUNT is the number of pulses.

Rev. A | Page 37 of 66

ADPD105/ADPD106/ADPD107

Data Sheet

Note that if either Time Slot A or Time Slot B are disabled, I_{AFE_x}= 0

for that respective time slot. Additionally, if operating in digital

integrate mode, power savings can be realized by setting

Register 0x3C, Bits[8:3] = 010010. This setting disables the

band-pass filters that are bypassed in digital integrate mode,

changing the AFE power contribution calculation to

optimized, the user can then increase the number of pulses to

achieve the desired system SNR.

Optimizing SNR per Watt in a Signal Limited System

In practice, optimizing for peak SNR is not always practical.

One scenario in which the PPG signal has a poor SNR is the

signal limited regime. In this scenario, the LED current reaches

an upper limit before the desired dc return level is achieved.

I

_{AFE_x}(mA) = 3.0 × 10⁻³+ (1.0 × 10⁻³× NUM_CHANNELS) +

(5.7 × 10⁻³/SCALE_X × I_{LEDX_PK}

)

(8)

Tuning in this case starts where the peak SNR tuning stops. The

starting point is nominally a 50k gain, as long as the lowest LED

current setting of 8 mA does not saturate the photodiode and the

50k gain provides enough protection against intense background

light. In these cases, use a 25k gain as the starting point.

Average V_LEDASupply Current

To calculate the average V_LEDAsupply current, use Equation 9.

I

_{LED_AVG_A}= SLOTA_LED_WIDTH × I_{LEDA_PK}× DR ×

PULSE_COUNT

where:

(9)

The goal of the tuning process is to bring the dc return signal to a

specific ADC range, such as 50% or 60%. The ADC range choice is

a function of the margin of headroom needed to prevent saturation

as the dc level fluctuates over time. The SNR of the PPG waveform

is always some percentage of the dc level. If the target level cannot

be achieved at the base gain, increase the gain and repeat the

procedure. The tuning system may need to place an upper limit

on the gain to prevent saturation from ambient signals.

SLOTA_LED_WIDTH is the LED pulse width expressed in

seconds.

I

_{LEDA_PK}is the peak current, expressed in amps, for whichever

LED is selected for Time Slot A.

Average V_LEDBSupply Current

To calculate the average V_LEDBsupply current, use Equation 10.

_{LED_AVG_B}= SLOTB_LED_WIDTH × I_{LEDB_PK}× DR ×

PULSE_COUNT

where:

I

Tuning the Pulse Count

(10)

After the LED peak current and TIA gain are optimized,

increasing the number of pulses per sample increases the SNR

by the square root of the number of pulses. There are two ways to

increase the pulse count. The pulse count registers (Register 0x31,

Bits[15:8], and Register 0x36, Bits[15:8]) change the number of

pulses per internal sample. Register 0x15, Bits[6:4] and Bits[10:8],

controls the number of internal samples that are averaged together

before the data is sent to the output. Therefore, the number of

pulses per sample is the pulse count register multiplied by the

number of subsequent samples being averaged. In general, the

internal sampling rate increases as the number of internal

sample averages increase to maintain the desired output data

rate. The SNR/watt is most optimal with pulse count values of

16 or less. Above pulse count values of 16, the square root

relationship does not hold in the pulse count register. However,

this relationship continues to hold when averaged between

samples using Register 0x15.

SLOTB_LED_WIDTH is the LED pulse width expressed in

seconds.

I

_{LEDB_PK}is the peak current, expressed in amps, for whichever

LED is selected for Time Slot B.

OPTIMIZING SNR PER WATT

The ADPD105/ADPD106/ADPD107 offer a variety of

parameters that the user can adjust to achieve the best signal.

One of the key goals of system performance is to obtain the best

system SNR for the lowest total power. This goal is often referred

to as optimizing SNR/watt. Even in systems where only the SNR

matters and power is a secondary concern, there may be a lower

power or a high power means of achieving the same SNR.

Optimizing for Peak SNR

The first step in optimizing for peak SNR is to find a TIA gain

and LED level that gives the best performance where the

number of LED pulses remains constant. If peak SNR is the

goal, the noise section of Table 4 can be used as a guide. It is

important to note that the SNR improves as a square root of the

number of pulses averaged together, whereas the increase in the

LED power consumed is directly proportional to the number of

LED pulses. In other words, for every doubling of the LED pulse

count, there is a doubling of the LED power consumed and a 3 dB

SNR improvement. As a result, avoid any change in the gain con-

figuration that provides less than 3 dB of improvement for a 2×

power penalty; any TIA gain configuration that provides more

than 3 dB of improvement for a 2× power penalty is a good

choice. If peak SNR is the goal and there is no issue saturating

the photodiode with LED current at any gain, the 50k TIA gain

setting is an optimal choice. After the SNR per pulse per channel is

Note that increasing LED peak current increases SNR almost

directly proportional to LED power, whereas increasing the

number of pulses by a factor of n results in only a nominal√(n)

increase in SNR.

When using the sample sum/average function (Register 0x15),

the output data rate decreases by the number of summed

samples. To maintain a static output data rate, increase the

sample frequency (Register 0x12) by the same factor as that

selected in Register 0x15. For example, for a 100 Hz output data

rate and a sample sum/average of four samples, set the sample

frequency to 400 Hz.

Rev. A | Page 38 of 66

Data Sheet

ADPD105/ADPD106/ADPD107

Dual-Channel AFE Mode

OPTIMIZING POWER BY DISABLING UNUSED

CHANNELS AND AMPLIFIERS

Single-Channel AFE Mode

In situations where two of the four channels are in use, the

other two channels can be disabled. Enable Channel 1 and

Channel 2 (with Channel 3 and Channel 4 disabled) by writing

0x7 to Register 0x37, Bits[15:13]. Operate Channel 3 and Channel 4

in dual channel mode (with Channel 1 and Channel 2 disabled)

by writing 0x7 to both Register 0x3C, Bits[5:3] and Register 0x37,

Bits[12:10].

When using a single photodiode in an application, with that

photodiode connected to a single AFE channel (either Channel 1

or Channel 2), the ADPD105/ADPD106/ADPD107 have an

option to power down the unused channels, placing the device in

single AFE channel mode. Because three of the four AFE channels

are turned off in this mode, the power consumption is considerably

reduced.

Three-channel mode can also be achieved with the appropriate

settings. See Table 25 for the settings required to power down

different combinations of channels. Refer to the Time Slot

Switch section to determine the different combinations of the

PDx inputs and enabled channels required to optimize the

system configuration for maximum SNR and lowest power.

If only Channel 1 is being used, disable Channel 2, Channel 3, and

Channel 4 by writing 0x7 to Register 0x3C, Bits[8:6]. If only

Channel 2 is being used, disable Channel 1 by writing 0x7 to

Register 0x3C, Bits[5:3], and disable Channel 3 and Channel 4

by writing 0x7 to Register 0x37, Bits[15:13].

Table 25. Channel Power-Down Settings

Register 0x3C,

Bits[8:6]

Register 0x3C,

Bits[5:3]

Register 0x37,

Bits[15:13]

Register 0x37,

Bits[12:10]

Number of Channels Channels Enabled

1

2

3

4

Channel 1

Channel 2

Channel 1, Channel 2

Channel 3, Channel 4

Channel 2, Channel 3, Channel 4 0x0

All channels 0x0

0x7

0x0

0x7

0x0

0x7

0x0

Not applicable

0x7

0x0

0x7

0x0

Rev. A | Page 39 of 66

ADPD105/ADPD106/ADPD107

Data Sheet

mode from the ADPD103 that is kept in the ADPD105/

ADPD106/ADPD107 for backward compatibility.

Powering Down Individual Amplifiers for Additional

Power Savings

Each channel includes a TIA, a BPF, and an integrator, which

can also be configured as a buffer (see Figure 44).Options are

built into the devices to power down individual amplifiers in the

signal path. For example, in digital integrate mode, the BPF is

bypassed but left powered up by default. The BPF can be disabled

completely, which saves 1/3 of the power dissipated by the AFE

during the sampling phase. See the descriptions for Register 0x3C

and Register 0x37 in Table 30 for information on how to disable

the individual amplifiers.

The recommended TIA ADC mode is one in which the band-

pass filter is bypassed and the integrator is configured as an

inverting buffer. This mode is enabled by writing 0xAE65 to

Register 0x43 (Time Slot A) and/or Register 0x45 (Time Slot B)

to bypass the band-pass filter. Additionally, Bit 7 of Register 0x42

(Time Slot A) and/or Register 0x44 (Time Slot B) must be set to

1 to configure the integrator as a buffer. With the ADC offset

register(s) for the desired channel set to 0, the output of the

ADC is at ~3000 codes for a single pulse and a zero input

current condition. As the input current from the photodiode

increases, the ADC output increases toward 16,384.

BPF

TIA

The ADC output (ADC_OUT) is calculated as follows:

ADC_OUT= 8192 ((2 V_BIAS− 2iR_F− 1.8 V)/146 μV/LSB) (11)

where:

±1 INTEGRATOR

V

BIAS

Figure 44. Signal Path Block Diagram

V

_BIASis the bias voltage for the TIA (the default value is 1.265 V).

i is the input current to the TIA.

R_Fis the TIA feedback resistor.

It is important to leave any unused input channels floating for

proper device operation.

In Equation 11, use + for the inverting configuration and use −

when using the noninverting configuration with the buffer.

TIA ADC MODE

There is a way to put the devices into a mode that effectively runs

the TIA directly into the ADC without using the analog band-pass

filter and integrator as shown in Figure 45. This mode is referred to

as TIA ADC mode. There are two basic applications of TIA ADC

mode. In normal operation, all of the background light is blocked

from the signal chain, and therefore cannot be measured. TIA_

ADC mode can be used to measure the amount of background/

ambient light. This mode can also be used to measure other dc

input currents, such as leakage resistance.

Equation 11 is an approximation and does not account for

internal offsets and gain errors. The calculation also assumes

that the ADC offset registers are set to 0

One time slot can be used in TIA ADC mode at the same time

the other time slot is being used in normal pulsed mode. This

capability is useful for monitoring ambient and pulsed signals at

the same time. The ambient signal is monitored during the time

slot configured for TIA ADC mode, while the pulsed signal,

with the ambient signal rejected, is monitored in the time slot

configured for normal mode.

OPTIONAL

BUFFER

–1

ADC

TIA

Protecting Against TIA Saturation in Normal Operation

V

One of the reasons to monitor TIA ADC mode is to protect

against environments that may cause saturation. One concern

when operating in high light conditions, especially with larger

photodiodes, is that the TIA stage may become saturated while

the ADPD105/ADPD106/ADPD107 continue to communicate

data. The resulting saturation is not typical. The TIA, based on its

settings, can only handle a certain level of photodiode current.

Based on the way the ADPD105/ADPD106/ADPD107 are

configured, if there is a current level from the photodiode that is

larger than the TIA can handle, the TIA output during the LED

pulse effectively extends the current pulse, making it wider. The

AFE timing is then violated because the positive portion of the

band-pass filter output extends into the negative section of the

integration window. Thus, the photosignal is subtracted from

itself, causing the output signal to decrease when the effective

light signal increases.

BIAS

Figure 45. TIA ADC Mode Block Diagram

When the devices are in TIA ADC mode, the band-pass filter

and the integrator stage are bypassed. This bypass effectively

wires the TIA directly into the ADC. At the set sampling

frequency, the ADC samples Channel 1 through Channel 4 in

sequential order, and each sample is taken at 1 μs intervals.

There are two modes of operation in TIA ADC mode. One

mode is an inverting configuration where TIA ADC mode

directly drives the ADC. This mode is enabled by setting

Register 0x43 (Time Slot A) and/or Register 0x45 (Time Slot B)

to 0xB065, which bypasses the band-pass filter and the

integrator. With the ADC offset register(s) for the desired

channel set to 0, the output of the ADC is at ~13,000 codes for a

single pulse and a zero input current condition. As the input

current from the photodiode increases, the ADC output

decreases toward 0. This configuration is a legacy TIA ADC

To measure the response from the TIA and verify that this stage

is not saturating, place the device in TIA ADC mode and slightly

modify the timing. Specifically, sweep SLOTx_AFE_OFFSET

Rev. A | Page 40 of 66

Data Sheet

ADPD105/ADPD106/ADPD107

until two or three of the four channels reach a minimum value

(note that TIA is in an inverting configuration). All four channels

do not reach this minimum value because, typically, 3 μs LED

pulse widths are used and the ADC samples the four channels

sequentially at 1 μs intervals. This procedure aligns the ADC

sampling time with the LED pulse to measure the total amount of

light falling on the photodetector (for example, background light +

LED pulse).

between the anode and cathode, or between the anode and

some other supply or ground. In normal operation, the ambient

rejection feature of the ADPD105/ADPD106/ADPD107 masks

the primary effects of these resistances, making it very difficult to

detect them. However, even at 1 MΩ to 10 MΩ, such resistance

can impact performance significantly through added noise or

decreased dynamic range. TIA ADC mode can be used to screen

for these assembly issues.

If this minimum value is above 0 LSB, the TIA is not saturated.

However, take care, because even if the result is not 0 LSB,

operating the device near saturation can quickly result in

saturation if light conditions change. A safe operating region

is typically at ¾ full scale and lower. Use Table 26 to determine

how the input codes map to ADC levels on a per channel per

pulse basis. These codes are not the same as in normal mode

because the band-pass filter and integrator are not unity-gain

elements.

Measuring Shunt Resistance on the Photodiode

A shunt resistor across the photodiode does not generally affect

the output level of the device in operation because the effective

impedance of the TIA is very low, especially if the photodiode is

held to 0 V in operation. However, such resistance can add noise

to the system, degrading performance. The best way to detect

photodiode leakage, also called photodiode shunt resistance, is

to place the device in TIA ADC mode in the dark and vary the

operation mode cathode voltage. Setting the cathode to 1.3 V

places 0 V across the photodiode because the anode is always at

1.3 V while in operation. Setting the cathode to 1.8 V places

0.5 V across the photodiode. Using the register settings in Table 3

to control the cathode voltage, measure the TIA ADC value at

both voltages. Next, divide the voltage difference of 0.5 V by the

difference of the ADC result after converting it to a current. This

result is the approximate shunt resistance. Values greater than

10 MΩ may be difficult to measure, but this method is useful in

identifying gross failures.

Coarse Ambient Light Measurement

Using the typical values in Table 26, TIA ADC mode can be used

to measure or quantify the amount of background or ambient light

present on the photodetector. The settings are the same in the

method described in the Protecting Against TIA Saturation in

Normal Operation section, except the timing used in the

normal operating mode is sufficient for this mode. There is no

need to sweep SLOTx_AFE_OFFSET. If SLOTx_AFE_OFFSET is

in the same place as the normal mode operation, the TIA ADC

mode does not return the same value, regardless of whether the

LED is on or off.

Measuring TIA Input Shunt Resistance

A resistance to develop between the TIA input and another

supply or ground on the PCB is an example of another problem

that can occur. These resistances can force the TIA into saturation

prematurely. This premature saturation, in turn, takes away

dynamic range from the device in operation and adds a Johnson

noise component to the input. To measure these resistances, place

the device in TIA ADC mode in the dark and start by measuring

the TIA ADC offset level with the photodiode inputs disconnected

(Register 0x14, Bits[11:8] = 0 or Register 0x14, Bits[7:4] = 0).

From this, subtract the value of TIA ADC mode with the

darkened photodiode connected and convert the difference

into a current. If the value is positive, and the ADC signal

decreased, the resistance is to a voltage higher than 1.3 V, such

as V_DD. Current entering the TIA causes the output to drop. If

the output difference is negative due to an increase of codes at

the ADC, current is being pulled out of the TIA and there is a

shunt resistance to a lower potential than 1.3 V, such as ground.

In TIA_MODE, the dark level is a high level near 13,000 LSBs

per channel per pulse (see Table 26). To measure this value, select

no photodiode by writing a 0x0 to Register 0x14, Bits[11:8] for

Time Slot B or Register 0x14, Bits[7:4] for Time Slot A. This

setting internally opens the photodiode connection and gives

a baseline LSB value that coincides with a zero signal input.

After Register 0x14 is restored to its normal value, while

connecting the photodiode to the TIA, this TIA ADC result can

be subtracted from the open photodiode case to yield a

background light measurement. Use Table 26 to translate this

measurement into an input photocurrent. Use this result for

coarse absolute measurements only, because it is typically only

accurate to within 10%.

Measuring PCB Parasitic Input Resistance

During the process of mounting the ADPD105/ADPD106/

ADPD107, undesired resistance can develop on the inputs through

assembly errors or debris on the PCB. These resistances can form

Rev. A | Page 41 of 66

ADPD105/ADPD106/ADPD107

Data Sheet

Table 26. Analog Specifications for TIA ADC and Digital Integrate Modes

Parameter

Test Conditions/Comments

Typ

Unit

TIA ADC/Digital Integration Saturation Levels

Values expressed per channel, per sample; TIA feedback resistor

25 kΩ

50 kΩ

100 kΩ

200 kΩ

38.32

19.16

9.58

ꢀA

4.79

TIA ADC Resolution

Values expressed per channel, per sample; TIA feedback resistor

25 kΩ

50 kΩ

100 kΩ

200 kΩ

2.92

1.5

0.73

0.37

nA/LSB

Output with No Input Photocurrent

ADC offset (Register 0x18 to Register 0x21) = 0x0

13,000 LSB

The other writes required to switch to digital integration mode

are listed in Table 27.

DIGITAL INTEGRATE MODE

Digital integrate mode is built into the ADPD105/ADPD106/

ADPD107 and allows the device to accommodate longer

LED/AFE pulse widths and different types of sensors at the

input. The analog integration mode described in the AFE

Operation section is ideally suited for applications requiring a

large LED duty cycle, or applications that require customization

of the sampling scheme. Digital integrate mode allows the

integration function to be performed after the ADC in the

digital domain. This mode enables the device to handle a much

wider range of sensors at the input.

When using digital integrate mode, up to two photodiodes can

be connected to the ADPD105/ADPD106/ADPD107 inputs; one

photodiode per PDx input group (PD1/PD2/PD3/PD4 or PD5/

PD6/PD7/PD8). Never connect the same photodiode across the

two PDx groups. In digital integrate mode, there are options to

connect the photodiode to all four AFE channels (PD1/PD2/PD3/

PD4 or PD5/PD6/PD7/PD8), or just a single AFE channel (PD1

or PD5). When connecting to a single AFE channel, write 0x1

to Register 0x54, Bit 14 for Time Slot A, or, for Time Slot B,

write 0x1 to Register 0x54, Bit 15.

In digital integrate mode, the ADC performs a conversion every

1 μs during the integration window. During the integration

window, the digital engine either adds to or subtracts from

the previous sample. The band-pass filter is bypassed and the

integrator is converted to a voltage buffer, allowing the digital

engine to perform the integration function. In this mode, after

the timing is optimized, the output of the ADC increases as the

light level on the photodiode increases.

When connecting to a single AFE channel, there is also an

option to turn off Channel 2, Channel 3, and Channel 4 (and to

save power) by writing 0x7 to Register 0x55, Bits[15:13]. When

connecting to all four channels (PD1/PD2/PD3/PD4 or PD5/

PD6/PD7/PD8), write 0x0 (default)to Register 0x54, Bit 14 for

Time Slot A, or write 0x0 (default) to Register 0x54, Bit 15 for

Time Slot B. Ensure that all AFE channels are powered up by

writing 0x0 to Register 0x55, Bits[15:13].

The integration window is a combination of negative and positive

windows where the duration of these windows is set by SLOTx_

AFE_WIDTH. At the end of the digital integration window, the

resulting sum is sent to the decimate unit as the sample for that

LED pulse. There is one sample per time slot for every sample

cycle. Table 27 lists the registers required for placing the device

in digital integrate mode.

Connecting the single photodiode to a single AFE channel offers

the best SNR performance in cases where signal is limited, whereas

connecting the single photodiode to all four AFE channels offers

the best dynamic range in cases where signal is large.

Digital Integration Sampling Modes

There are two sampling modes that can be used while the

device is in digital integration mode. These modes are single-

sample pair mode and double-sample pair mode.

There may also be changes needed in the SLOTx_AFE_OFFSET

registers and FIFO configuration register (0x11). To read the

final value through the FIFO, set the appropriate values in Regis-

ter 0x11, Bits[4:2] for Time Slot A, and Register 0x11, Bits[8:6]

for Time Slot B. Alternatively, the final output is also available

through the data registers; Register 0x64, Register 0x70, and

Register 0x74 for Time Slot A, and Register 0x68, Register 0x78,

and Register 0x7C for Time Slot B.

In single-sample pair mode, there is a single negative sample

region and a single positive sample region, shown in Figure 48

and Figure 49. To use single-sample pair mode, write 0x1 to

Register 5A, Bit 5 for Time Slot A, or Register 5A, Bit 6 for

Time Slot B. The negative sample region starts at SLOTx_AFE_

OFFSET + 9 and its duration (the number of samples taken) is set

by SLOTx_AFE_WIDTH. The positive sample region starts at

SLOTx_AFE_OFFSET + 9 + SLOTx_AFE_WIDTH, and its

duration is also set by SLOTx_AFE_WIDTH. Set the timing

such that the negative sample region falls entirely in the flat

To put the ADPD105/ADPD106/ADPD107 into digital

integration mode during Time Slot A, write 0x1 to Register 0x58,

Bit 12. To put the ADPD105/ADPD106/ADPD107 into digital

integration mode in Time Slot B, write 0x1 to Register 0x58, Bit 13.

Rev. A | Page 42 of 66

Data Sheet

ADPD105/ADPD106/ADPD107

(dark) portion of the LED response, whereas the positive

sample region falls in the pulsed region of the LED response.

Placing the LED pulse offset, SLOTx_LED_OFFSET, at the

beginning of SLOTx_AFE_OFFSET + 9 + SLOTx_AFE_WIDTH

achieves this timing. The output is the difference of the signals

in the two regions.

Background Values

In digital integrate mode, the digital integration background

value, DI_BACKGROUND, or dark values are also stored and

available as output data. This is in addition to the output value

during the LED pulse, DI_OUTPUT, which has the dark value

subtracted. DI_BACKGROUND is the sum of the negative

region samples.

Double-sample pair mode is another way to sample. In this

mode, there are two negative sample regions and one long

positive sample region (see Figure 46 and Figure 47). To use

double-sample pair mode, write 0x0 to Register 0x5A, Bit 5 for

Time Slot A, or Bit 6 for Time Slot B. The first negative sample

region starts at SLOTx_AFE_OFFSET + 9 and its duration is set

by SLOTx_AFE_WIDTH. The positive sample region starts at

SLOTx_AFE_OFFSET + 9+ SLOTx_AFE_WIDTH and its

duration is twice the SLOTx_AFE_WIDTH. After this, there is

another negative sample region that starts at SLOTx_AFE_OFFSET

+ 9 + 3 × SLOTx_AFE_WIDTH, and its duration is SLOTx_AFE_

WIDTH. Set the timing such that both of the negative sample

regions fall in the flat (dark) portion of the LED response and

the positive sample region falls in the pulsed portion of the LED

response. Placing the LED pulse offset, SLOTx_LED_OFFSET

at the beginning of SLOTx_AFE_OFFSET + 9 + SLOTx_AFE_

WIDTH achieves this timing. The output is calculated by

summing the response of all the regions in a negative/positive/

negative manner. The double-sample pair mode is useful for cases

when the background light is not constant because it has better

background rejection, but it also uses more power than single-

sample pair mode.

To include these values in the FIFO, set Register 0x11, Bits[4:2]

for Time Slot A, and Register 0x11, Bits[8:6] for Time Slot B. For

16-bit data, set this value to 0x3; for 32-bit data, set this value to

0x04. These settings are also available through the data registers;

Register 0x65, Register 0x71, and Register 0x75 for Time Slot A,

and Register 0x69, Register 0x79, and Register 0x7D for Time

Slot B. It is recommended that the channel offsets (Register 0x18 to

Register 0x21) be set to 0x1F00 when including the background

values in the FIFO in digital integration mode. These channel

offsets do not affect the sample values, but do provide more

headroom for the background values.

Saturation Detection in Digital Integrate Mode

In normal operation, when using the band-pass filter and the

integrator, the ADC almost always saturates before the TIA.

Unlike in normal operation, saturation of the TIA or the ADC

cannot be detected solely by looking at the signal value where

the signal value is the positive sample region minus the reference

region in digital integrate mode. This is because the integrated

value does not by itself contain any information indicating

whether one of the ADC conversions during the integration

period exceeded the ADC output range. As a result, the real-

time output may have saturated only for a fraction of the ADC

conversions within a sample and the final accumulated sum may

not reflect this. To detect TIA saturation in digital integration

mode, both the background values, DI_BACKGROUND, and

the signal values, DI_OUTPUT, must be collected. Refer to the

Background Values section for the correct settings for

Sample Timing Modes

There are two options for timing the sample regions: gapped

mode and continuous mode.

In gapped timing mode, there is a space between the negative and

positive sample regions. The width of this region is specified by

SLOTA_AFE_FOFFSET for Time Slot A and SLOTB_AFE_

FOFFSET for Time Slot B in 31.25 ns steps. To enable this feature,

write 0x1 to Register 0x5A, Bit 7. This bit enables gapped timing

for the time slot (or time slots) that are in digital integrate mode.

This mode is helpful when there are unwanted transients in the

LED response that must be ignored for an accurate output.

Register 0x11 that provide these values.

For single-sample pair mode, saturation has occurred when

(DI_OUTPUT/(min(SLOTx_LED_WIDTH,

SLOTx_AFE_WIDTH)) + DI_BACKGROUND/

AFE_WIDTH)/NUM_PULSES > 0x3FFF

If there are no concerns about LED response transients, select

continuous timing mode. In this mode, there is no space

between the negative and positive sample regions. Write 0x0 to

Register 0x5A, Bit 7 for continuous timing of the sample regions.

For double-sample pair mode, saturation has occurred when

(DI_OUTPUT/(min(SLOTx_LED_WIDTH, 2 ×

SLOTx_AFE_WIDTH)) + DI_BACKGROUND/(2 ×

SLOTx_AFE_WIDTH))/NUM_PULSES > 0x3FFF

Both gapped and continuous sample timing modes can be used

with single-sample pair or double-sample pair mode. Example

timing diagrams are shown in Figure 46, Figure 47, Figure 48,

and Figure 49.

Rev. A | Page 43 of 66

ADPD105/ADPD106/ADPD107

Data Sheet

LED

SAMPLE

SLOTx_AFE_OFFSET + 9

NEGATIVE

SAMPLE

REGION

POSITIVE SAMPLE REGION

NEGATIVE

SAMPLE

REGION

Figure 46. Digital Integration Mode in Double-Sample Pair Mode with Continuous Sample Timing

LED

SAMPLE

SLOTx_AFE_OFFSET + 9

NEGATIVE

SAMPLE

REGION

POSITIVE SAMPLE

REGION

NEGATIVE

SAMPLE

REGION

SLOTx_AFE_FOFFSET

Figure 47. Digital Integration Mode in Double-Sample Pair Mode with Gapped Sample Timing

LED

SAMPLE

SLOTx_AFE_OFFSET + 9

NEGATIVE

SAMPLE

REGION

POSITIVE

SAMPLE

REGION

SLOTx_AFE_FOFFSET

Figure 48. Digital Integration Mode in Single-Sample Pair Mode with Gapped Sample Timing

LED

SAMPLE

SLOTx_AFE_OFFSET + 9

NEGATIVE

SAMPLE

REGION

POSITIVE

SAMPLE

REGION

Figure 49. Digital Integration Mode in Single-Sample Pair Mode with Continuous Sample Timing

Rev. A | Page 44 of 66

Data Sheet

ADPD105/ADPD106/ADPD107

Table 27. Configuration Registers to Switch Between the Normal Sample Mode, TIA ADC Mode, and Digital Integration Mode

Normal

Mode

Value

Digital

Integration

Mode Value

Data

Address Bits

TIA ADC

Mode Value

Bit Name

Description

0x42

[15:8] SLOTA_AFE_MODE

0x1C

Not applicable 0x1D

In normal mode, this setting configures the

integrator block for optimal operation. In

digital integration mode, this setting

configures the integrator block as a buffer.

This setting is not important for TIA ADC

mode.

7

SLOTA_INT_AS_BUF

0x0

0x1

Not applicable 0: normal integrator configuration.

1: convert integrator to buffer amplifier (this is

done automatically in digital integrate mode).

0x43

0x44

[15:0] SLOTA_AFE_CFG

[15:8] SLOTB_AFE_MODE

0xADA5

0xAE65

Time Slot A AFE connection.

0xAE65 bypasses the band-pass filter.

0xB065 can also be used in TIA ADC mode.

This setting bypasses the BPF and the

integrator.

0x1C

Not applicable 0x1D

In normal mode, this setting configures the

integrator block for optimal operation. In

digital integration mode, this setting

configures the integrator block as a buffer.

This setting is not important for TIA ADC

mode.

7

SLOTB_INT_AS_BUF

0x0

0x1

Not applicable 0: normal integrator configuration.

1: convert integrator to buffer amplifier (this is

done automatically in digital integrate mode).

0x45

[15:0] SLOTB_AFE_CFG

0xADA5

0xAE65

Time Slot B AFE connection.

0xAE65 bypasses the band-pass filter.

0xB065 can also be used in TIA ADC mode.

This setting bypasses the BPF and the

integrator.

0x4E

0x58

[15:0] ADC_TIMING

Not

applicable

Not applicable 0x0040

Set ADC clock to 1 MHz in TIA ADC mode.

13

SLOTB_DIGITAL_INT_EN 0x0

0x0

0x1

Digital integrate mode enable, Time Slot B.

0: disable.

1: enable.

12

SLOTA_DIGITAL_INT_EN 0x0

0x0

0x1

Digital integrate mode enable, Time Slot A.

0: disable.

1: enable.

0x5A

[15:0] DIG_INT_CFG

Not

applicable

Not applicable Variable

Configuration of digital integration depends

on the use case. This register is ignored for

other modes.

To enable pulse connect mode, the device is configured identically

to normal mode, except that Register 0x14, Bits[3:2] = 0 for

Time Slot B, and Register 0x14, Bits[1:0] = 0 for Time Slot A.

PULSE CONNECT MODE

In pulse connect mode, the photodiode input connections are

pulsed according to the timing set up in the LED pulse timing

registers. In this mode, if the LED pulse timing is set up to provide

a 2 μs LED pulse, the device pulses the connection to the photo-

diode input for 2 μs instead of providing a 2 μs LED pulse. This

mode is an alternate to TIA ADC mode, allowing the entire

signal path, including the band-pass filter and integrator, to be

used to measure ambient light as well as other types of measure-

ments with different types of sensors (for example, ECGs).

SYNCHRONOUS ECG AND PPG MEASUREMENT

USING TIA ADC MODE

In wearable devices developed for monitoring the health care of

patients, it is often necessary to have synchronized measurements

of biomedical signals. For example, a synchronous measurement of

patient ECG and PPG can be used to determine the pulse wave

transit time (PWTT), which can then be used to estimate blood

pressure.

Rev. A | Page 45 of 66

ADPD105/ADPD106/ADPD107

Data Sheet

The circuit shown in Figure 50 shows a synchronous ECG and

PPG measurement using the AD8233 and the ADPD105. The

AD8233 implements a two-pole high-pass filter with a cutoff

frequency at 0.3 Hz, and a two-pole low-pass filter with a cutoff

frequency of 37 Hz. The output of the AD8233 is fed to one of

the current inputs of the ADPD105 through a 50 kꢁ resistor to

convert the voltage output of the AD8233 into a current.

ECG measurements. Data can be read out of the on-chip FIFO

or straight from data registers. The ADPD105 channel used to

process the ECG signal is set up in TIA ADC mode and the input

bias voltage must be set to the 0.90 V setting using Bits[5:4] of

Register 0x42 if the ECG signal is on Time Slot A, or Register 0x44

on Time Slot B. The TIA gain setting can be set to optimize the

dynamic range of the signal path. The channel used to process

the PPG signal is configured in its normal operating mode.

Figure 51 shows a plot of a synchronized ECG and PPG

measurement using the AD8233 with the ADPD105.

The ADPD105 is configured to alternately measure the

photodiode signal and the ECG signal from the AD8233 on

consecutive timeslots to provide fully synchronized PPG and

1.8V

4.7µF

10Mꢀ

HPDRIVE

+IN

HPSENSE

IAOUT

10Mꢀ

1.8V

180kꢀ

LA

RA

–IN

REFIN

10Mꢀ

0.1µF

4.7µF

+V

S

10Mꢀ

RLDFB

RLD

0.1µF

1nF

360kꢀ

RL

GND

AD8233

1.8V

SW

FR

AC/DC

SDN

1Mꢀ

OPAMP+

REFOUT

OPAMP–

OUT

100kꢀ 6.8nF

250kꢀ

TO DIGITAL

INTERFACE

RLD SDN

LOD

2.7nF

1Mꢀ

1.8V

ADPD105

50kꢀ

DVDD

AVDD

PD1-2

0.1µF

VLED

PDC

AGND

DGND

LGND

1.8V

PD3-4

10kꢀ 10kꢀ

LEDX1

SCL

SDA

VREF

TO DIGITAL

INTERFACE

1µF

GPIO0

GPIO1

Figure 50. Synchronized PPG and ECG Measurement Using ADPD105 with the AD8233

10000

52000

9500

9000

51500

PPG

8500

8000

51000

ECG

7500

7000

50500

6500

50000

6000

SAMPLE RATE (ms)

Figure 51. Plot of Synchronized ECG and PPG Waveforms

Rev. A | Page 46 of 66

Data Sheet

ADPD105/ADPD106/ADPD107

Measuring Voltages Using the Current Inputs

voltage source through a series resistance, R_INmust be taken

into consideration. The conversion gain from a voltage into a

current can be determined by following the schematic in Figure 52.

In some situations, as in a case where a synchronized ECG and

PPG measurement is being attempted, a voltage measurement

must be made using the current inputs of the ADPD105/

ADPD106/ADPD107. First, convert the voltage source to a

current by placing a series resistor, R_S, in series between the

voltage source and the current input of the device, as shown in

Figure 52.

I_IN= (V_IN− TIA_VREF)/(R_S+ R_IN)

Typically, R_INis approximately 13 kꢁ. The value of R_INvaries as

a function of supply voltage. This variability is shown in Figure 53

45

+85°C

+25°C

0°C

40

–40°C

ADPD105/ADPD106/

ADPD107

35

30

25

20

15

10

5

R

IN

S

V

IN

I

IN

ADC

TIA

TIA_VREF

Figure 52. Using the ADPD105/ADPD106/ADPD107 Inputs with Voltage Sources

Secondly, there is a switch resistance, R_IN, that must be taken

into consideration when converting a voltage source to a

current. This switch resistance is not a factor in a typical

photodiode application since the device is only dealing with

input currents and these currents are not a function of the input

resistance. However, when driving the device inputs from a

0

1.70

1.75

1.80

1.85

1.90

1.95

V

SUPPLY VOLTAGE (V)

DD

Figure 53. Variability of Switch Input Resistance as a Function of V_DDSupply

Voltage

Rev. A | Page 47 of 66

ADPD105/ADPD106/ADPD107

Data Sheet

REGISTER LISTING

Table 28. Numeric Register Listing¹

Bit 15

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 1

Bit 8

Bit 0

Hex.

Addr. Name

Bits

Bit 7

Reset

RW

0x00 Status

[15:8]

FIFO_SAMPLES[7:0]

0x0000 R/W

[7:0] Reserved

[15:8]

SLOTB_INT

SLOTA_INT

Reserved

0x01 INT_MASK

Reserved

FIFO_INT_ 0x00FF R/W

MASK

[7:0] Reserved

SLOTB_INT_

MASK

SLOTA_INT_

MASK

0x02 GPIO_DRV

[15:8]

[7:0]

Reserved

GPIO1_DRV GPIO1_POL 0x0000 R/W

GPIO0_ENA GPIO0_DRV GPIO0_POL

0x06 FIFO_

THRESH

[15:8]

[7:0]

Reserved

FIFO_THRESH[5:0]

0x0000 R/W

0x0516

0x00C8 R/W

0x0000

Reserved

REV_NUM[7:0]

0x08 DEVID

[15:8]

[7:0]

R

DEV_ID[7:0]

0x09 I2CS_ID

0x0A CLK_RATIO

[15:8]

[7:0]

ADDRESS_WRITE_KEY[7:0]

SLAVE_ADDRESS[6:0]

Reserved

[15:8]

[7:0]

Reserved

CLK_RATIO[11:8]

R

CLK_RATIO[7:0]

0x0B GPIO_CTRL [15:8]

[7:0]

Reserved

GPIO1_ALT_CFG[4:0]

GPIO0_ALT_CFG[4:0]

0x0000 R/W

0x0D SLAVE_

ADDRESS_

[15:8]

[7:0]

SLAVE_ADDRESS_KEY[15:8]

SLAVE_ADDRESS_KEY[7:0]

KEY

0x0F SW_RESET

[15:8]

[7:0]

Reserved

0x0000 R/W

0x1000 R/W

SW_RESET

Mode[1:0]

0x10 Mode

[15:8]

[7:0]

Reserved

0x11 SLOT_EN

[15:8]

Reserved

RDOUT_

MODE

FIFO_OVRN_

PREVENT

Reserved

SLOTB_

FIFO_

MODE[2]

[7:0]

SLOTB_FIFO_MODE[1:0]

SLOTB_EN

SLOTA_FIFO_MODE[2:0]

Reserved

SLOTA_EN

0x12 FSAMPLE

[15:8]

FSAMPLE[15:8]

FSAMPLE[7:0]

0x0028 R/W

0x0541 R/W

0x0600 R/W

0x2000 R/W

0x2000 RW

[7:0]

0x14 PD_LED_

SELECT

[15:8]

Reserved

SLOTB_PD_SEL[3:0]

SLOTB_LED_SEL[1:0] SLOTA_LED_SEL[1:0]

SLOTB_NUM_AVG[2:0]

Reserved

[7:0]

SLOTA_PD_SEL[3:0]

Reserved

0x15 NUM_AVG

[15:8]

[7:0] Reserved

SLOTA_NUM_AVG[2:0]

0x18 SLOTA_CH1_ [15:8]

SLOTA_CH1_OFFSET[15:8]

SLOTA_CH1_OFFSET[7:0]

SLOTA_CH2_OFFSET[15:8]

SLOTA_CH2_OFFSET[7:0]

SLOTA_CH3_OFFSET[15:8]

SLOTA_CH3_OFFSET[7:0]

SLOTA_CH4_OFFSET[15:8]

SLOTA_CH4_OFFSET[7:0]

SLOTB_CH1_OFFSET[15:8]

SLOTB_CH1_OFFSET[7:0]

SLOTB_CH2_OFFSET[15:8]

SLOTB_CH2_OFFSET[7:0]

SLOTB_CH3_OFFSET[15:8]

SLOTB_CH3_OFFSET[7:0]

SLOTB_CH4_OFFSET[15:8]

SLOTB_CH4_OFFSET[7:0]

OFFSET

[7:0]

0x19 SLOTA_CH2_ [15:8]

OFFSET

[7:0]

0x1A SLOTA_CH3_ [15:8]

OFFSET

[7:0]

0x1B SLOTA_CH4_ [15:8]

OFFSET

[7:0]

0x1E SLOTB_CH1_ [15:8]

OFFSET

[7:0]

0x1F SLOTB_CH2_ [15:8]

OFFSET

[7:0]

0x20 SLOTB_CH3_ [15:8]

OFFSET

[7:0]

0x21 SLOTB_CH4_ [15:8]

OFFSET

[7:0]

Rev. A | Page 48 of 66

Data Sheet

ADPD105/ADPD106/ADPD107

Bit 15

Bit 7

Bit 14

Bit 6

Bit 13

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 1

Bit 8

Bit 0

Hex.

Addr. Name

Bits

Bit 5

Reset

RW

0x22 ILED3_

COARSE

[15:8]

Reserved

ILED3_SCALE

ILED3_SLEW[2:0]

ILED1_SCALE

ILED1_SLEW[2:0]

Reserved

0x3000 R/W

0x630C R/W

0x0320 R/W

0x0818 R/W

0x0000 R/W

[7:0] Reserved

[15:8]

ILED3_COARSE[3:0]

Reserved

0x23 ILED1_

COARSE

Reserved

[7:0] Reserved

[15:8] Reserved

[7:0] Reserved

[15:8]

ILED1_COARSE[3:0]

0x24 ILED2_

COARSE

ILED2_SCALE Reserved

ILED2_SLEW[2:0]

ILED3_FINE[4:0]

ILED2_COARSE[3:0]

0x25 ILED_FINE

ILED2_FINE[4:2]

ILED1_FINE[4:0]

SLOTA_LED_WIDTH[4:0]

[7:0]

ILED2_FINE[1:0]

Reserved

0x30

SLOTA_LED_ [15:8]

PULSE

[7:0]

SLOTA_LED_OFFSET[7:0]

SLOTA_LED_NUMBER[7:0]

SLOTA_LED_PERIOD[7:0]

0x31 SLOTA_

NUMPULSES

[15:8]

[7:0]

0x34 LED_

DISABLE

[15:8]

Reserved

SLOTB_

LED_DIS

SLOTA_

LED_DIS

[7:0]

Reserved

0x35 SLOTB_LED_ [15:8]

Reserved

SLOTB_LED_WIDTH[4:0]

0x0320 R/W

0x0818 R/W

0x0000 R/W

PULSE

[7:0]

SLOTB_LED_OFFSET[7:0]

SLOTB_LED_NUMBER[7:0]

SLOTB_LED_PERIOD[7:0]

0x36 SLOTB_

NUMPULSES

[15:8]

[7:0]

0x37 ALT_PWR_

DN

[15:8]

[7:0]

CH34_DISABLE[15:13]

CH2_DISABLE[12:10]

Reserved

0x38 EXT_SYNC_ [15:8]

EXT_SYNC_STARTUP[15:8]

EXT_SYNC_STARTUP[7:0]

0x000

R/W

STARTUP

[7:0]

0x39 SLOTA_AFE_ [15:8]

SLOTA_AFE_WIDTH[4:0]

SLOTA_AFE_OFFSET[2:0]

SLOTB_AFE_WIDTH[4:0]

SLOTB_AFE_OFFSET[2:0]

Reserved

SLOTA_AFE_OFFSET[5:3]

SLOTA_AFE_FOFFSET[4:0]

SLOTB_AFE_OFFSET[5:3]

SLOTB_AFE_FOFFSET[4:0]

0x22FC R/W

0x3006 R/W

WINDOW

[7:0]

0x3B SLOTB_AFE_ [15:8]

WINDOW

[7:0]

0x3C AFE_PWR_

CFG1

[15:8]

Reserved

V_CATHODE AFE_

POWER-

DOWN[5]

[7:0]

AFE_POWERDOWN[4:0]

SLOTA_AFE_MODE[7:0]

SLOTA_TIA_VBIAS[1:0]

Reserved

0x42 SLOTA_

TIA_CFG

[15:8]

0x1C38 R/W

[7:0] SLOTA_INT_

AS_BUF

SLOTA_TIA_

IND_EN

Reserved (write 0x1)

SLOTA_TIA_GAIN[1:0]

0x43 SLOTA_

AFE_CFG

[15:8]

[7:0]

SLOTA_AFE_CFG[15:8]

SLOTA_AFE_CFG[7:0]

SLOTB_AFE_MODE[7:0]

0xADA5 R/W

0x1C38 R/W

0x44 SLOTB_

TIA_CFG

[15:8]

[7:0] SLOTB_INT_

AS_BUF

SLOTB_

TIA_IND_EN

SLOTB_TIA_VBIAS[1:0]

Reserved (write 0x1)

SLOTB_TIA_GAIN[1:0]

0x45 SLOTB_

AFE_CFG

[15:8]

[7:0]

SLOTB_AFE_CFG[15:8]

SLOTB_AFE_CFG[7:0]

Reserved

0xADA5 R/W

0x4B SAMPLE_

CLK

[15:8]

CLK32K_ 0x2612 R/W

BYP

[7:0] CLK32K_EN

Reserved

CLK32K_ADJUST[5:0]

0x4D CLK32M_

ADJUST

[15:8]

[7:0]

Reserved

0x0098 R/W

0x0060 R/W

CLK32M_ADJUST[7:0]

ADC_TIMING[15:8]

ADC_TIMING[7:0]

Reserved

0x4E ADC_CLOCK [15:8]

[7:0]

0x4F EXT_SYNC_ [15:8]

SEL

0x2090 R/W

Reserved

[7:0] Reserved

GPIO1_OE

GPIO1_IE

Reserved

EXT_SYNC_SEL[1:0] GPIO0_IE

Reserved

0x50 CLK32M_

CAL_EN

[15:8]

Reserved

0x0000 R/W

[7:0] Reserved

GPIO1_CTRL

CLK32M_

CAL_EN

0x54 AFE_PWR_

CFG2

[15:8] SLOTB_

SLOTA_

SINGLE_CH_

DIG_INT

SLEEP_V_CATHODE [1:0]

SLOTB_V_CATHODE[1:0] SLOTA_V_CATHODE[1:0] 0x0020 R/W

SINGLE_CH_

DIG_INT

[7:0] REG54_VCAT_

ENABLE

Reserved

0x55 TIA_INDEP_ [15:8]

DIGINT_POWER[2:0]

Reserved

SLOTB_TIA_GAIN_4[1:0]

SLOTA_TIA_GAIN_3[1:0]

SLOTB_TIA_GAIN_3[1:0] 0x0000 R/W

SLOTA_TIA_GAIN_2[1:0]

GAIN

[7:0]

SLOTB_TIA_GAIN_2[1:0]

SLOTA_TIA_GAIN_4[1:0]

Rev. A | Page 49 of 66

ADPD105/ADPD106/ADPD107

Data Sheet

Bit 15

Bit 7

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 1

Bit 8

Bit 0

Hex.

Addr. Name

Bits

Reset

RW

0x58 DIGITAL_

INT_EN

[15:8]

Reserved

SLOTB_

DIGITAL_

INT_EN

SLOTA_

DIGITAL_INT_

EN

Reserved

0x0000 R/W

[7:0]

Reserved

0x5A DIG_

INT_CFG

[15:8]

[7:0] DIG_INT_

GAPMODE

SLOTB_DIG_

INT_SAMPLE_ INT_SAMPLE_

MODE

SLOTA_DIG_

Reserved

MODE

0x5F DATA_

[15:8]

[7:0]

Reserved

ACCESS_CTL

Reserved

SLOTB_

DATA_

HOLD

SLOTA_

DATA_

HOLD

DIGITAL_

CLOCK_

ENA

0x60 FIFO_

ACCESS

[15:8]

[7:0]

FIFO_DATA[15:8]

0x0000

R

FIFO_DATA[7:0]

0x64 SLOTA_

PD1_16BIT

[15:8]

[7:0]

SLOTA_CH1_16BIT[15:8]

SLOTA_CH1_16BIT[7:0]

SLOTA_CH2_16BIT[15:8]

SLOTA_CH2_16BIT[7:0]

SLOTA_CH3_16BIT[15:8]

SLOTA_CH3_16BIT[7:0]

SLOTA_CH4_16BIT[15:8]

SLOTA_CH4_16BIT[7:0]

SLOTB_CH1_16BIT[15:8]

SLOTB_CH1_16BIT[7:0]

SLOTB_CH2_16BIT[15:8]

SLOTB_CH2_16BIT[7:0]

SLOTB_CH3_16BIT[15:8]

SLOTB_CH3_16BIT[7:0]

SLOTB_CH4_16BIT[15:8]

SLOTB_CH4_16BIT[7:0]

SLOTA_CH1_LOW[15:8]

SLOTA_CH1_LOW[7:0]

SLOTA_CH2_LOW[15:8]

SLOTA_CH2_LOW[7:0]

SLOTA_CH3_LOW[15:8]

SLOTA_CH3_LOW[7:0]

SLOTA_CH4_LOW[15:8]

SLOTA_CH4_LOW[7:0]

SLOTA_CH1_HIGH[15:8]

SLOTA_CH1_HIGH[7:0]

SLOTA_CH2_HIGH[15:8]

SLOTA_CH2_HIGH[7:0]

SLOTA_CH3_HIGH[15:8]

SLOTA_CH3_HIGH[7:0]

SLOTA_CH4_HIGH[15:8]

SLOTA_CH4_HIGH[7:0]

SLOTB_CH1_LOW[15:8]

SLOTB_CH1_LOW[7:0]

SLOTB_CH2_LOW[15:8]

SLOTB_CH2_LOW[7:0]

SLOTB_CH3_LOW[15:8]

SLOTB_CH3_LOW[7:0]

SLOTB_CH4_LOW[15:8]

SLOTB_CH4_LOW[7:0]

SLOTB_CH1_HIGH[15:8]

SLOTB_CH1_HIGH[7:0]

SLOTB_CH2_HIGH[15:8]

SLOTB_CH2_HIGH[7:0]

0x65 SLOTA_

PD2_16BIT

[15:8]

[7:0]

0x66 SLOTA_

PD3_16BIT

[15:8]

[7:0]

0x67 SLOTA_

PD4_16BIT

[15:8]

[7:0]

0x68 SLOTB_

PD1_16BIT

[15:8]

[7:0]

0x69 SLOTB_

PD2_16BIT

[15:8]

[7:0]

0x6A SLOTB_

PD3_16BIT

[15:8]

[7:0]

0x6B SLOTB_

PD4_16BIT

[15:8]

[7:0]

0x70 A_PD1_

LOW

[15:8]

[7:0]

0x71 A_PD2_

LOW

[15:8]

[7:0]

0x72 A_PD3_

LOW

[15:8]

[7:0]

0x73 A_PD4_

LOW

[15:8]

[7:0]

0x74 A_PD1_

HIGH

[15:8]

[7:0]

0x75 A_PD2_

HIGH

[15:8]

[7:0]

0x76 A_PD3_

HIGH

[15:8]

[7:0]

0x77 A_PD4_

HIGH

[15:8]

[7:0]

0x78 B_PD1_

LOW

[15:8]

[7:0]

0x79 B_PD2_

LOW

[15:8]

[7:0]

0x7A B_PD3_

LOW

[15:8]

[7:0]

0x7B B_PD4_

LOW

[15:8]

[7:0]

0x7C B_PD1_

HIGH

[15:8]

[7:0]

0x7D B_PD2_

HIGH

[15:8]

[7:0]

Rev. A | Page 50 of 66

Data Sheet

ADPD105/ADPD106/ADPD107

Bit 15

Bit 7

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 1

Bit 8

Bit 0

Hex.

Addr. Name

Bits

Reset

RW

0x7E B_PD3_

HIGH

[15:8]

[7:0]

[15:8]

[7:0]

SLOTB_CH3_HIGH[15:8]

SLOTB_CH3_HIGH[7:0]

SLOTB_CH4_HIGH[15:8]

SLOTB_CH4_HIGH[7:0]

0x0000

R

0x7F B_PD4_

HIGH

0x0000

R

¹The recommended values are not shown. Only power-on reset values are shown in Table 28. The recommended values are largely dependent on use case. See Table 29

to Table 35 for the recommended values.

Rev. A | Page 51 of 66

ADPD105/ADPD106/ADPD107

Data Sheet

LED CONTROL REGISTERS

Table 29. LED Control Registers

Default

Value

Address Data Bit

Access

R/W

Name

Description

0x14

[15:12]

[11:8]

0x0

Reserved

Write 0x0 to these bits for proper operation.

0x5

R/W

SLOTB_PD_SEL

PDx connection selection for Time Slot B. See Figure 22 and Figure 23

0x0: all photodiode inputs are floating.

0x1: all photodiode inputs are connected during Time Slot B.

0x5: PD1/PD2/PD3/PD4 are connected during Time Slot B.

Other: reserved.

[7:4]

[3:2]

[1:0]

0x4

0x0

0x1

R/W

SLOTA_PD_SEL

SLOTB_LED_SEL

SLOTA_LED_SEL

PDx connection selection for Time Slot A. See Figure 22 and

Figure 23.

0x0: all photodiode inputs are floating.

0x1: all photodiode inputs are connected during Time Slot A.

0x5: PD1/PD2/PD3/PD4 are connected during Time Slot A.

Other: reserved.

Time Slot B LED configuration. These bits determine which LED is

associated with Time Slot B.

0x0: pulse PDx connection to AFE.

0x1: LEDX1 pulses during Time Slot B.

0x2: LEDX2 pulses during Time Slot B.

0x3: LEDX3 pulses during Time Slot B.

Time Slot A LED configuration. These bits determine which LED is

associated with Time Slot A.

0x0: pulse PDx connection to AFE.

0x1: LEDX1 pulses during Time Slot A.

0x2: LEDX2 pulses during Time Slot A.

0x3: LEDX3 pulses during Time Slot A.

Write 0x0.

0x22

[15:14]

13

0x0

0x1

R/W

Reserved

ILED3_SCALE

LEDX3 current scale factor.

1: 100% strength.

0: 40% strength; sets the LEDX3 driver in low power mode.

LEDX3 Current Scale = 0.4 + 0.6 × (Register 0x22, Bit 13).

Write 0x1.

12

0x1

0x0

R/W

Reserved

[11:7]

[6:4]

Reserved

Write 0x0.

ILED3_SLEW

LEDX3 driver slew rate control. The slower the slew rate, the safer

the performance in terms of reducing the risk of overvoltage of the

LED driver.

0x0: the slowest slew rate.

…

0x7: the fastest slew rate.

[3:0]

0x0

R/W

ILED3_COARSE

LEDX3 coarse current setting. Coarse current sink target value of

LEDX3 in standard operation.

0x0: lowest coarse setting.

…

0xF: highest coarse setting.

LED3_PEAK= LED3_COARSE× LED3_FINE× LED3_SCALE

where:

LED3_PEAKis the LEDX3 peak target value (mA).

LED3_COARSE= 50.3 + 19.8 × (Register 0x22, Bits[3:0]).

LED3_FINE= 0.74 + 0.022 × (Register 0x25, Bits[15:11]).

LED3_SCALE= 0.4 + 0.6 × (Register 0x22, Bit 13).

Rev. A | Page 52 of 66

Data Sheet

ADPD105/ADPD106/ADPD107

Default

Value

Address Data Bit

Access

R/W

Name

Description

0x23

[15:14]

13

0x0

0x1

Reserved

ILED1_SCALE

Write 0x0.

R/W

LEDX1 current scale factor.

1: 100% strength.

0: 40% strength; sets the LEDX1 driver in low power mode.

LEDX1 Current Scale = 0.4 + 0.6 × (Register 0x23, Bit 13).

12

0x1

0x0

R/W

Reserved

Write 0x1.

Write 0x0.

[11:7]

[6:4]

Reserved

ILED1_SLEW

LEDX1 driver slew rate control. The slower the slew rate, the safer

the performance in terms of reducing the risk of overvoltage of the

LED driver.

0: the slowest slew rate.

…

7: the fastest slew rate.

[3:0]

0x0

R/W

ILED1_COARSE

LEDX1 coarse current setting. Coarse current sink target value of

LEDX1 in standard operation.

0x0: lowest coarse setting.

…

0xF: highest coarse setting.

LED1_PEAK= LED1_COARSE× LED1_FINE× LED1_SCALE

where:

LED1_PEAKis the LEDX1 peak target value (mA).

LED1_COARSE= 50.3 + 19.8 × (Register 0x23, Bits[3:0]).

LED1_FINE= 0.74 + 0.022 × (Register 0x25, Bits[4:0]).

LED1_SCALE= 0.4 + 0.6 × (Register 0x23, Bit 13).

0x24

[15:14]

13

0x0

0x1

R/W

Reserved

Write 0x0.

ILED2_SCALE

LEDX2 current scale factor.

1: 100% strength.

0: 40% strength; sets the LEDX2 driver in low power mode.

LED2 Current Scale = 0.4 + 0.6 × (Register 0x24, Bit 13)

12

0x1

0x0

R/W

Reserved

Write 0x1.

Write 0x0.

[11:7]

[6:4]

Reserved

ILED2_SLEW

LEDX2 driver slew rate control. The slower the slew rate, the safer

the performance in terms of reducing the risk of overvoltage of the

LED driver.

0: the slowest slew rate.

…

7: the fastest slew rate.

[3:0]

0x0

R/W

ILED2_COARSE

LEDX2 coarse current setting. Coarse current sink target value of

LEDX2 in standard operation.

0x0: lowest coarse setting.

…

0xF: highest coarse setting.

LED2_PEAK= LED2_COARSE× LED2_FINE× LED2_SCALE

where:

LED2_PEAKis the LEDX2 peak target value (mA).

LED2_COARSE= 50.3 + 19.8 × (Register 0x24, Bits[3:0]).

LED2_FINE= 0.74 + 0.022 × (Register 0x25, Bits[10:6]).

LED2_SCALE= 0.4 + 0.6 × (Register 0x24, Bit 13).

Rev. A | Page 53 of 66

ADPD105/ADPD106/ADPD107

Data Sheet

Default

Value

Address Data Bit

Access

Name

Description

0x25

[15:11]

0xC

R/W

ILED3_FINE

LEDX3 fine adjust. Current adjust multiplier for LED3.

LEDX3 fine adjust = 0.74 + 0.022 × (Register 0x25, Bits[15:11]).

See Register 0x22, Bits[3:0], for the full LED3 formula.

LEDX2 fine adjust. Current adjust multiplier for LED2.

LEDX2 fine adjust = 0.74 + 0.022 × (Register 0x25, Bits[10:6]).

See Register 0x24, Bits[3:0], for the full LED2 formula.

Write 0x0.

[10:6]

0xC

R/W

ILED2_FINE

5

0x0

0xC

R/W

Reserved

[4:0]

ILED1_FINE

LEDX1 fine adjust. Current adjust multiplier for LED1.

LEDX1 fine adjust = 0.74 + 0.022 × (Register 0x25, Bits[4:0]).

See Register 0x23, Bits[3:0], for the full LED1 formula.

Write 0x0.

0x30

0x31

[15:13]

[12:8]

[7:0]

0x0

R/W

Reserved

0x3

SLOTA_LED_WIDTH

SLOTA_LED_OFFSET

SLOTA_LED_NUMBER

LED pulse width (in 1 ꢀs step) for Time Slot A.

LED offset width (in 1 ꢀs step) for Time Slot A.

0x20

0x08

[15:8]

LED Time Slot A pulse count. n_A: number of LED pulses in Time

Slot A. This is typically LED1. Adjust in the application. A setting of

six pulses (0x06) is typical.

[7:0]

[15:10]

9

0x18

0x00

0x0

R/W

SLOTA_LED_PERIOD

Reserved

LED Time Slot A pulse period (in 1 ꢀs step).

Write 0x0.

0x34

SLOTB_LED_DIS

Time Slot B LED disable. 1: disables the LED assigned toTime Slot B.

Register 0x34 keeps the drivers active and prevents them from

pulsing current to the LEDs. Disabling both LEDs via this register is

often used to measure the dark level.

Use Register 0x11 instead to enable or disable the actual time slot

usage and not only the LED.

8

0x0

R/W

SLOTA_LED_DIS

Time Slot A LED disable. 1: disables the LED assigned to Time Slot A.

Use Register 0x11 instead to enable or disable the actual time slot

usage and not only the LED.

[7:0]

0x00

0x0

R/W

Reserved

Write 0x00.

0x35

0x36

[15:13]

[12:8]

[7:0]

Reserved

Write 0x0.

0x3

SLOTB_LED_WIDTH

SLOTB_LED_OFFSET

LED pulse width (in 1 ꢀs step) for Time Slot B.

LED offset width (in 1 ꢀs step) for Time Slot B.

0x20

0x08

[15:8]

R/W

SLOTB_LED_NUMBER LED Time Slot B pulse count. n_B: number of LED pulses in Time Slot B.

This is typically LED2. A setting of six pulses (0x06) is typical.

[7:0]

0x18

SLOTB_LED_PERIOD

LED Time Slot B pulse period (in 1 ꢀs step).

AFE GLOBAL CONFIGURATION REGISTERS

Table 30. AFE Global Configuration Registers

Default

Value

Address

Data Bit

Access

Name

Description

0x37

[15:13]

0x0

R/W

CH34_DISABLE

Power-down options for Channel 3 and Channel 4 only.

Bit 13: power down Channel 3, Channel 4 TIA op amp.

Bit 14: power down Channel 3, Channel 4 BPF op amp.

Bit 15: power down Channel 3, Channel 4 integrator op amp.

Bit 10: power down Channel 2 TIA op amp.

Bit 11: power down Channel 2 BPF op amp.

Bit 12: power down Channel 2 integrator op amp.

Write 0x000.

[12:10]

[9:0]

0x0

R/W

CH2_DISABLE

Reserved

0x000

Rev. A | Page 54 of 66

Data Sheet

ADPD105/ADPD106/ADPD107

Default

Value

Address

Data Bit

Access

R/W

Name

Description

0x3C

[15:14]

[13:11]

10

0x0

0x6

0x0

Reserved

V_CATHODE

Write 0x0.

R/W

Write 0x6.

R/W

Reserved.

9

R/W

0x0: 1.3 V (identical to anode voltage); recommended setting.

0x1: 1.8 V (reverse bias photodiode by 550 mV). This

setting may add noise.

[8:3]

0x00

R/W

AFE_POWERDOWN

AFE channels power-down select.

0x0: keeps all channels on.

Bit 3: power down Channel 1 TIA op amp.

Bit 4: power down Channel 1 BPF op amp.

Bit 5: power down Channel 1 integrator op amp.

Bit 6: power down Channel 2, Channel 3, and Channel 4

TIA op amp.

Bit 7: power down Channel 2, Channel 3, and Channel 4

BPF op amp.

Bit 8: power down Channel 2, Channel 3, and Channel 4

integrator op amp.

[2:0]

15

0x6

0x0

R/W

Reserved

Write 0x6.

0x54

SLOTB_SINGLE_CH_DIG_INT

0: in Time Slot B, use all four photodiode channels in

parallel for digital integration (default setting for highest

dynamic range).

1: in Time Slot B, use only Channel 1 for digital integration.

This limits connection to PD1 or PD5.

14

0x0

R/W

SLOTA_SINGLE_CH_DIG_INT

SLEEP_V_CATHODE

0: in Time Slot A, use all four photodiode channels in

parallel for digital integration (default setting for highest

dynamic range)

1: in Time Slot A, use only Channel 1 for digital integration.

This limits connection to PD1 or PD5.

[13:12]

If Bit 7 = 1; this setting is applied to the cathode voltage

while the device is in sleep mode. The anode voltage is

always set to the cathode voltage in sleep mode.

0x0: V_DD(1.8 V).

0x1: 1.3 V.

0x2: 1.55 V.

0x3: 0.0 V.

[11:10]

0x0

R/W

SLOTB_V_CATHODE

SLOTA_V_CATHODE

REG54_VCAT_ENABLE

If Bit 7 = 1; this setting is applied to the cathode voltage

while the device is in Time Slot B operation. The anode

voltage is always 1.3 V in Time Slot B mode.

0x0: V_DD(1.8 V).

0x1: 1.3 V.

0x2: 1.55 V.

0x3: 0.0 V (this forward biases a diode at the input).

[9:8]

If Bit 7 = 1; this setting is applied to the cathode voltage

while the device is in Time Slot A operation. The anode

voltage is always 1.3 V in Time Slot A mode.

0x0: V_DD(1.8 V).

0x1: 1.3 V.

0x2: 1.55 V.

0x3: 0.0 V (this forward biases a diode at the input).

7

0x0

R/W

0: use the cathode voltage settings defined by Register 0x3C,

Bit 9.

1: override Register 0x3C, Bit 9 with cathode settings

defined by Register 0x54, Bits[13:8].

[6:0]

0x20

Reserved

Reserved.

Rev. A | Page 55 of 66

ADPD105/ADPD106/ADPD107

Data Sheet

Default

Value

Address

Data Bit

[15:14]

13

Access

R/W

Name

Description

0x58

0x0

Reserved

Reserved.

0x0

R/W

SLOTB_DIGITAL_INT_EN

0x0: Time Slot B operating in normal mode.

0x1: Time Slot B operating in digital integration mode.

0x0: Time Slot A operating in normal mode.

0x1: Time Slot A operating in digital integration mode.

Reserved.

12

0x0

R/W

SLOTA_DIGITAL_INT_EN

[11:0]

[15:8]

7

0x000

0x00

0x0

R/W

Reserved

0x5A

Reserved

Write 0x0.

DIG_INT_GAPMODE

Digital integrate gapped mode enable.

0: no gap between negative and positive sample regions.

1: use SLOTA_AFE_FOFFSET for Time Slot A or SLOTB_AFE_

FOFFSET for Time Slot B to specify the gap in ꢀs.

6

0x0

R/W

SLOTB_DIG_INT_SAMPLE_

MODE

Digital integrate single sample pair mode for Time Slot B.

0: double sample pair mode.

1: single sampled pair mode.

5

0x0

SLOTA_DIG_INT_SAMPLE_

MODE

Digital integrate single sample pair mode for Time Slot A.

0: double sample pair mode.

1: single sampled pair mode.

[4:0]

0x00

Reserved

Write 0x00.

Table 31. AFE Configuration Registers, Time Slot A

Data

Bit

Default

Value

Address

Access Name

Description

0x39

[15:11]

[10:5]

0x4

R/W

SLOTA_AFE_WIDTH

AFE integration window width (in 1 ꢀs step) for Time Slot A.

0x17

SLOTA_AFE_OFFSET

SLOTA_AFE_FOFFSET

SLOTA_AFE_MODE

AFE integration window coarse offset (in 1 ꢀs step) for

Time Slot A.

[4:0]

0x1C

R/W

AFE integration window fine offset (in 31.25 ns step) for

Time Slot A.

0x42

[15:8]

0x1C: Time Slot A AFE setting for normal mode. All four blocks

of the signal chain are in use during normal mode (the TIA, the

BPF, followed by the integrator, and finally the ADC).

0x1D: Time Slot A AFE setting for digital integrate mode.

0: normal integrator configuration.

1: converts integrator to buffer amplifier (this is done

automatically in digital integrate mode).

7

6

0x0

R/W

SLOTA_INT_AS_BUF

SLOTA_TIA_IND_EN

Enable Time Slot A TIA gain individual settings. When it is

enabled, the Channel 1 TIA gain is set via Register 0x42,

Bits[1:0], and the Channel 2 through Channel 4 TIA gain is set

via Register 0x55, Bits[5:0].

0: disable TIA gain individual setting.

1: enable TIA gain individual setting.

Set V_BIASof the TIA for Time Slot A.

0: 1.14 V.

[5:4]

0x3

R/W

SLOTA_TIA_VBIAS

1: 1.01 V.

2: 0.90 V.

3: 1.27 V (default recommended).

Reserved. Write 0x1.

[3:2]

[1:0]

0x2

0x0

R/W

Reserved

SLOTA_TIA_GAIN

Transimpedance amplifier gain for Time Slot A. When

SLOTA_TIA_IND_EN is enabled, this value is for Time Slot B,

Channel 1 TIA gain. When SLOTA_TIA_IND_EN is disabled, it is

for all four Time Slot A channel TIA gain settings.

0: 200 kΩ.

1: 100 kΩ.

2: 50 kΩ.

3: 25 kΩ.

Rev. A | Page 56 of 66

Data Sheet

ADPD105/ADPD106/ADPD107

Data

Bit

Default

Value

Address

Access Name

Description

0x43

[15:0]

0xADA5

R/W

SLOTA_AFE_CFG

AFE connection in Time Slot A.

0xADA5: analog full path mode (TIA_BPF_INT_ADC).

0xAE65: TIA ADC mode (if Register 0x42, Bit 7 = 1).

0xB065: TIA ADC mode (if Register 0x42, Bit 7 = 0).

0xAE65: digital integration mode.

Others: reserved.

0x55

[15:13]

0x0

R/W

DIGINT_POWER

Power-down for Channel 2, Channel 3, and Channel 4 in digital

integration mode.

0: keep all channels powered up.

7: powers down Channel 2, Channel 3, and Channel 4.

[12]

0x0

R/W

Reserved

Write 0x0.

[11:10]

SLOTB_TIA_GAIN_4

TIA gain for Time Slot B, Channel 4 (PD4).

0: 200 kΩ

1: 100 kΩ.

2: 50 kΩ.

3: 25 kΩ.

[9:8]

[7:6]

[5:4]

[3:2]

[1:0]

0x0

R/W

SLOTB_TIA_GAIN_3

SLOTB_TIA_GAIN_2

SLOTA_TIA_GAIN_4

SLOTA_TIA_GAIN_3

SLOTA_TIA_GAIN_2

TIA gain for Time Slot B, Channel 3 (PD3).

0: 200 kΩ

1: 100 kΩ.

2: 50 kΩ.

3: 25 kΩ.

TIA gain for Time Slot B, Channel 2 (PD2).

0: 200 kΩ

1: 100 kΩ.

2: 50 kΩ.

3: 25 kΩ.

TIA gain for Time Slot A, Channel 4 (PD4).

0: 200 kΩ

1: 100 kΩ.

2: 50 kΩ.

3: 25 kΩ.

TIA gain for Time Slot A, Channel 3 (PD3).

0: 200 kΩ

1: 100 kΩ.

2: 50 kΩ.

3: 25 kΩ.

TIA gain for Time Slot A, Channel 2 (PD2).

0: 200 kΩ

1: 100 kΩ.

2: 50 kΩ.

3: 25 kΩ.

0x5A

[15:8]

[7]

0x00

0x0

R/W

Reserved

Write 0x0.

DIG_INT_GAPMODE

Digital integration gapped mode enable.

0: no gap between negative and positive sample regions.

1: use SLOTA_AFE_FOFFSET for Time Slot A or SLOTB_AFE_

FOFFSET for Time Slot B to specify the gap in ꢀs.

[6]

0x0

R/W

SLOTB_DIG_INT_SAMPLEMODE

SLOTA_DIG_INT_SAMPLEMODE

Reserved

Digital integration single-sample pair mode for Time Slot B.

0: double-sample pair mode.

1: single-sampled pair mode.

[5]

0x0

Digital integration single-sample pair mode for Time Slot A.

0: double-sample pair mode.

1: single-sampled pair mode.

[4:0]

0x00

Write 0x0.

Rev. A | Page 57 of 66

ADPD105/ADPD106/ADPD107

Data Sheet

Table 32. AFE Configuration Registers, Time Slot B

Data

Address Bit

DefaultValue Access

Name

Description

0x3B

[15:11] 0x04

R/W

SLOTB_AFE_WIDTH

SLOTB_AFE_OFFSET

AFE integration window width (in 1 ꢀs step) forTime Slot B.

[10:5]

0x17

0x1C

R/W

AFE integration window coarse offset (in 1 ꢀs step) for

Time Slot B.

[4:0]

SLOTB_AFE_FOFFSET

SLOTB_AFE_MODE

AFE integration window fine offset (in 31.25 ns step) for

Time Slot B.

0x44

[15:8]

0x1C: Time Slot B AFE setting for normal mode

(TIA_BPF_INT_ADC).

0x1D: Time Slot B AFE setting for digital integrate mode.

0: normal integrator configuration.

1: convert integrator to buffer amplifier (this is done

automatically in digital integrate mode).

7

6

0x0

R/W

SLOTB_INT_AS_BUF

SLOTB_TIA_IND_EN

Enable Time Slot B TIA gain individual settings. When it is

enabled, the Channel 1 TIA gain is set via Register 0x44,

Bits[1:0], and the Channel 2 through Channel 4 TIA gain is

set via Register 0x55, Bits[11:6].

0: disable TIA gain individual setting.

1: enable TIA gain individual setting.

Set VBIAS of the TIA for Time Slot B.

0: 1.14 V.

[5:4]

0x3

R/W

SLOTB_TIA_VBIAS

1: 1.01 V.

2: 0.90 V.

3: 1.27 V (default recommended).

Write 0x1.

[3:2]

[1:0]

0x2

0x0

R/W

Reserved

SLOTB_TIA_GAIN

Transimpedance amplifier gain for Time Slot B. When

SLOTB_TIA_IND_EN is enabled, this value is for Time Slot B,

Channel 1 TIA gain. When SLOTB_TIA_IND_EN is disabled,

it is for all four Time Slot B channel TIA gain settings.

0: 200 kΩ.

1: 100 kΩ.

2: 50 kΩ.

3: 25 kΩ.

0x45

0x58

[15:0]

0xADA5

R/W

SLOTB_AFE_CFG

AFE connection in Time Slot B.

0xADA5: analog full path mode (TIA_BPF_INT_ADC).

0xAE65: TIA ADC mode (if Register 0x44, Bit 7 = 1).

0xB065: TIA ADC mode (if Register 0x44, Bit 7 = 0).

0xAE65: digital integration mode.

Others: reserved.

[15:14] 0x0

R/W

Reserved

Write 0x0.

13

0x0

SLOTB_DIGITAL_INT_EN

Digital integration mode, enable Time Slot B.

0: disable.

1: enable.

12

0x0

R/W

SLOTA_DIGITAL_INT_EN

Reserved

Digital integration mode, enable Time Slot A.

0: disable.

1: enable.

[11:0]

0x0000

Write 0x0000.

Rev. A | Page 58 of 66

Data Sheet

ADPD105/ADPD106/ADPD107

SYSTEM REGISTERS

Table 33. System Registers

Data

Address Bit

Default

Access Name

Description

0x00

[15:8]

0x00

R/W

FIFO_SAMPLES

FIFO status. Number of available bytes to be read from the FIFO. When

comparing this to the FIFO length threshold (Register 0x06, Bits[13:8]),

note that the FIFO status value is in bytes and the FIFO length

threshold is in words, where one word = two bytes.

Write 1 to Bit 15 to clear the contents of the FIFO.

Write 0x1 to clear this bit to 0x0.

7

6

0x0

R/W

Reserved

SLOTB_INT

Time Slot B interrupt. Describes the type of interrupt event. A 1

indicates an interrupt of a particular event type has occurred. Write a 1

to clear the corresponding interrupt. After clearing, the register goes to

0. Writing a 0 to this register has no effect.

5

0x0

R/W

SLOTA_INT

Time Slot A interrupt. Describes the type of interrupt event. A 1 indicates

an interrupt of a particular event type has occurred. Write a 1 to clear

the corresponding interrupt. After clearing, the register goes to 0.

Writing a 0 to this register has no effect

[4:0]

[15:9]

8

0x00

0x1

R/W

Reserved

Write 0x1F to clear these bits to 0x00.

Write 0x00.

0x01

Reserved

FIFO_INT_MASK

Sends an interrupt when the FIFO data length has exceeded the FIFO

length threshold in Register 0x06, Bits[13:8]. A 0 enables the interrupt.

7

6

0x1

R/W

Reserved

Write 0x1.

SLOTB_INT_MASK

Sends an interrupt on the Time Slot B sample. Write a 1 to disable the

interrupt. Write a 0 to enable the interrupt.

5

0x1

R/W

SLOTA_INT_MASK

Sends an interrupt on the Time Slot A sample. Write a 1 to disable the

interrupt. Write a 0 to enable the interrupt.

[4:0]

0x1F

R/W

Reserved

GPIO1_DRV

Write 0x1F.

0x02

[15:10] 0x00

Write 0x0000.

9

0x0

GPIO1 drive.

0: the GPIO1 pin is always driven.

1: the GPIO1 pin is driven when the interrupt is asserted; otherwise, it is

left floating and requires a pull-up or pull-down resistor, depending on

polarity (operates as open drain). Use this setting if multiple devices

must share the GPIO1 pin.

8

0x0

R/W

GPIO1_POL

GPIO1 polarity.

0: the GPIO1 pin is active high.

1: the GPIO1 pin is active low.

Write 0x00

[7:3]

2

0x00

0x0

R/W

Reserved

GPIO0_ENA

GPIO0 pin enable.

0: disable the GPIO0 pin. The GPIO0 pin floats, regardless of interrupt

status. The status register (Address 0x00) remains active.

1: enable the GPIO0 pin.

GPIO0 drive.

0: the GPIO0 pin is always driven.

1: the GPIO0 pin is driven when the interrupt is asserted; otherwise, it is

left floating and requires a pull-up or pull-down resistor, depending on

polarity (operates as open drain). Use this setting if multiple devices

must share the GPIO0 pin.

1

0

0x0

R/W

GPIO0_DRV

GPIO0_POL

GPIO0 polarity.

0: the GPIO0 pin is active high.

1: the GPIO0 pin is active low.

Rev. A | Page 59 of 66

ADPD105/ADPD106/ADPD107

Data Sheet

Data

Address Bit

Default

Access Name

Description

0x06

[15:14] 0x0

R/W

Reserved

Write 0x0.

[13:8]

0x00

FIFO_THRESH

FIFO length threshold. An interrupt is generated when the number of

data-words in the FIFO exceeds the value in FIFO_THRESH. The interrupt

pin automatically deasserts when the number of data-words available

in the FIFO no longer exceeds the value in FIFO_THRESH.

[7:0]

[15:8]

[7:0]

[15:8]

[7:1]

0

0x00

0x04

0x16

0x00

0x64

0x0

R/W

R

Reserved

REV_NUM

DEV_ID

Write 0x00.

0x08

0x09

Revision number.

Device ID.

R

W

R/W

R

ADDRESS_WRITE_KEY Write 0xAD when writing to SLAVE_ADDRESS. Otherwise, do not access.

SLAVE_ADDRESS

Reserved

I²C slave address.

Do not access.

Write 0x0.

0x0A

0x0B

[15:12] 0x0

R

Reserved

[11:0]

0x000

R

CLK_RATIO

When the CLK32M_CAL_EN bit (Register 0x50, Bit 5) is set, the device

calculates the number of 32 MHz clock cycles in two cycles of the 32 kHz

clock. The result, nominally 2000 (0x07D0), is stored in the CLK_RATIO bits.

[15:13] 0x0

R/W

Reserved

Write 0x0.

[12:8]

0x00

GPIO1_ALT_CFG

Alternate configuration for the GPIO1 pin.

0x0: GPIO1 is backward compatible to the ADPD103 PDSO pin

functionality.

0x1: interrupt function provided on GPIO1, as defined in Register 0x01.

0x2: asserts at the start of the first time slot, deasserts at end of last

time slot.

0x5: Time Slot A pulse output.

0x6: Time Slot B pulse output.

0x7: pulse output of both time slots.

0xC: output data cycle occurred for Time Slot A.

0xD: output data cycle occurred for Time Slot B.

0xE: output data cycle occurred.

0xF: toggles on every sample, which provides a signal at half the

sampling rate.

0x10: ouput = 0

0x11: output = 1

0x13: 32 kHz oscillator output.

Remaining settings are not supported.

Write 0x0.

[7:5]

[4:0]

0x0

R/W

Reserved

0x00

GPIO0_ALT_CFG

Alternate configuration for the GPIO0 pin.

0x0: GPIO0 is backward compatible to the ADPD103 INT pin functionality.

0x1: interrupt function provided on GPIO0, as defined in Register 0x01.

0x2: asserts at the start of the first time slot, deasserts at end of last

time slot.

0x5: Time Slot A pulse output.

0x6: Time Slot B pulse output.

0x7: pulse output of both time slots.

0xC: output data cycle occurred for Time Slot A.

0xD: output data cycle occurred for Time Slot B.

0xE: output data cycle occurred.

0xF: toggles on every sample, which provides a signal at half the

sampling rate.

0x10: output = 0.

0x11: output = 1.

0x13: 32 kHz oscillator output.

Remaining settings are not supported.

Rev. A | Page 60 of 66

Data Sheet

ADPD105/ADPD106/ADPD107

Data

Address Bit

Default

Access Name

Description

0x0D

[15:0]

0x0000

R/W

SLAVE_ADDRESS_KEY Enable changing the I²C address using Register 0x09.

0x04AD: enable address change always.

0x44AD: enable address change if GPIO0 is high.

0x84AD: enable address change if GPIO1 is high.

0xC4AD: enable address change if both GPIO0 and GPIO1 are high.

0x0F

0x10

[15:1]

0

0x0000

0x0

R

Reserved

Write 0x0000.

R/W

SW_RESET

Software reset. Write 0x1 to reset the device. This bit clears itself after a

reset. For I²C communications, this command returns an acknowledge

and the device subsequently returns to standby mode with all registers

reset to the default state.

[15:2]

[1:0]

0x0000

0x0

R/W

Reserved

Mode

Write 0x000.

Determines the operating mode of the ADPD105/ADPD106/ADPD107.

0x0: standby.

0x1: program.

0x2: normal operation.

0x11

[15:14] 0x0

R/W

Reserved

Reserved.

13

0x0

RDOUT_MODE

Readback data mode for extended data registers.

0x0: block sum of N samples.

0x1: block average of N samples.

12

0x1

R/W

FIFO_OVRN_PREVENT 0x0: wrap around FIFO, overwriting old data with new.

0x1: new data if FIFO is not full (recommended setting).

[11:9]

[8:6]

0x0

R/W

Reserved

Reserved.

SLOTB_FIFO_MODE

Time Slot B FIFO data format.

0: no data to FIFO.

1: 16-bit sample in digital integration mode or 16-bit sum of all four

channels when not in digital integration mode.

2: 32-bit sample in digital integration mode or 32-bit sum of all four

channels when not in digital integration mode.

3: 16-bit sample and 16-bit background value in digital integration mode.

4: 32-bit sample and 32-bit background value in digital integration

mode or four channels of 16-bit sample data for Time Slot B when not

in digital integration mode.

6: four channels of 32-bit extended sample data for Time Slot B when

not in digital integration mode.

Others: reserved.

The selected Time Slot B data is saved in the FIFO. Available only if Time

Slot A has the same averaging factor, N (Register 0x15, Bits[10:8] =

Bits[6:4]), or if Time Slot A is not saving data to the FIFO (Register 0x11,

Bits[4:2] = 0).

5

0x0

R/W

SLOTB_EN

Time Slot B enable. 1: enables Time Slot B.

Time Slot A FIFO data format.

0: no data to FIFO.

[4:2]

SLOTA_FIFO_MODE

1: 16-bit sample in digital integration mode or 16-bit sum of all

four channels when not in digital integration mode.

2: 32-bit sample in digital integration mode or 32-bit sum of all

four channels when not in digital integration mode.

3: 16-bit sample and 16-bit background value in digital integration mode.

4: 32-bit sample and 32-bit background value in digital integration

mode or four channels of 16-bit sample data for Time Slot B when not

in digital integration mode.

6: four channels of 32-bit extended sample data for Time Slot B when

not in digital integration mode.

Others: reserved.

1

0

0x0

R/W

Reserved

Write 0x0.

SLOTA_EN

Time Slot A enable. 1: enables Time Slot A.

Rev. A | Page 61 of 66

ADPD105/ADPD106/ADPD107

Data Sheet

Data

Address Bit

Default

0x0000

0x13

Access Name

Description

0x38

0x4B

[15:0]

R/W

EXT_SYNC_STARTUP

Write 0x4000 when EXT_SYNC_SEL is b01 or b10. Otherwise, write 0x0.

Write 0x26.

[15:9]

8

Reserved

0x0

CLK32K_BYP

Bypass internal 32 kHz oscillator.

0x0: normal operation.

0x1: provide external clock on the GPIO1 pin. The user must set

Register 0x4F, Bits[6:5] = 01 to enable the GPIO1 pin as an input.

7

0x0

R/W

CLK32K_EN

Sample clock power-up. Enables the data sample clock.

0x0: clock disabled.

0x1: normal operation.

6

0x0

R/W

Reserved

Write 0x0.

[5:0]

0x12

CLK32K_ADJUST

Data sampling (32 kHz) clock frequency adjust. This register is used to

calibrate the sample frequency of the device to achieve high precision

on the data rate as defined in Register 0x12. Adjusts the sample master

32 kHz clock by 0.6 kHz per LSB. For a 100 Hz sample rate as defined in

Register 0x12, 1 LSB of Register 0x4B, Bits[5:0], is 1.9 Hz.

Note that a larger value produces a lower frequency. See the Clocks

and Timing Calibration section for more information regarding clock

adjustment.

00 0000: maximum frequency.

10 0010: typical center frequency.

11 1111: minimum frequency.

Write 0x00.

0x4D

[15:8]

[7:0]

0x00

0x98

R/W

Reserved

CLK32M_ADJUST

Internal timing (32 MHz) clock frequency adjust. This register is used to

calibrate the internal clock of the device to achieve precisely timed LED

pulses. Adjusts the 32 MHz clock by 109 kHz per LSB.

See the Clocks and Timing Calibration section for more information

regarding clock adjustment.

0000 0000: minimum frequency.

1001 1000: default frequency.

1111 1111: maximum frequency.

0x0040: ADC clock speed = 1 MHz.

0x0060: ADC clock speed = 500 kHz.

Write 0x20.

0x4E¹

0x4F

[15:0]

0x0060

R/W

ADC_TIMING¹

[15:8]

0x20

0x1

0x0

0x1

0x0

R/W

Reserved

7

Reserved

Write 0x1.

6

GPIO1_OE

GPIO1_IE

GPIO1 pin output enable.

GPIO1 pin input enable.

5

4

Reserved

Write 0x1.

[3:2]

EXT_SYNC_SEL

Sample sync select.

00: use the internal 32 kHz clock with FSAMPLE to select sample timings.

01: use the GPIO0 pin to trigger sample cycle.

10: use the GPIO1 pin to trigger sample cycle.

11: reserved.

1

0x0

R/W

GPIO0_IE

Reserved

GPIO1_CTRL

GPIO0 pin input enable.

0

0x0

Write 0x0.

0x50

[15:7]

6

0x000

0x0

Write 0x000.

Controls the GPIO1 output when the GPIO1 output is enabled

(GPIO1_OE = 0x1).

0x0: GPIO1 output driven low.

0x1: GPIO1 output driven by the AFE power-down signal.

5

0x0

R/W

CLK32M_CAL_EN

Reserved

As part of the 32 MHz clock calibration routine, write 1 to begin the

clock ratio calculation. Read the result of this calculation from the

CLK_RATIO bits in Register 0x0A.

Reset this bit to 0 prior to reinitiating the calculation.

Write 0x0.

[4:0]

0x00

Rev. A | Page 62 of 66

Data Sheet

ADPD105/ADPD106/ADPD107

Data

Address Bit

Default

0x0000

0x0

Access Name

Description

0x5F

[15:3]

2

R/W

Reserved

Write 0x0000.

SLOTB_DATA_HOLD

Setting this bit prevents the update of the data registers corresponding to

Time Slot B. Set this bit to ensure that unread data registers are not

updated, guaranteeing a contiguous set of data from all four photodiode

channels.

1: hold data registers for Time Slot B.

0: allow data register update.

1

0

0x0

R/W

SLOTA_DATA_HOLD

Setting this bit prevents the update of the data registers corresponding to

Time Slot A. Set this bit to ensure that unread data registers are not

updated, guaranteeing a contiguous set of data from all four photodiode

channels.

1: hold data registers for Time Slot A.

0: allow data register update.

DIGITAL_CLOCK_ENA Set to 1 in order to enable the 32 MHz clock when calibrating the 32 MHz

clock. Always disable the 32 MHz clock following the calibration by

resetting this bit to 0.

¹Clock speed setting is only relevant during digital integrate mode.

ADC REGISTERS

Table 34. ADC Registers

Data

Address Bits

Default Access Name

0x0028 R/W FSAMPLE

Description

0x12

[15:0]

Sampling frequency: f_SAMPLE= 32 kHz/(Register 0x12, Bits[15:0] × 4).

For example, 100 Hz = 0x0050; 200 Hz = 0x0028.

Write 0x0.

0x15

[15:11] 0x00

R/W

Reserved

[10:8]

0x6

SLOTB_NUM_AVG

Sample sum/average for Time Slot B. Specifies the averaging factor, N_B,

which is the number of consecutive samples that is summed and averaged

after the ADC. Register 0x70 to Register 0x7F hold the data sum. Register 0x64

to Register 0x6B and the data buffer in Register 0x60 hold the data average,

which can be used to increase SNR without clipping, in 16-bit registers.

The data rate is decimated by the value of the SLOTB_NUMB_AVG bits.

0: 1.

1: 2.

2: 4.

3: 8.

4: 16.

5: 32.

6: 64.

7: 128.

Write 0x0.

7

0x0

R/W

Reserved

[6:4]

SLOTA_NUM_AVG

Sample sum/average for Time Slot A. N_A: same as Bits[10:8] but for

Time Slot A. See description in Register 0x15, Bits[10:8].

[3:0]

0x0

R/W

Reserved

Write 0x0.

0x18

0x19

0x1A

0x1B

0x1E

[15:0]

0x2000 R/W

SLOTA_CH1_OFFSET Time Slot A Channel 1 ADC offset. The value to subtract from the raw ADC

value. A value of 0x2000 is typical.

[15:0]

SLOTA_CH2_OFFSET Time Slot A Channel 2 ADC offset. The value to subtract from the raw ADC

value. A value of 0x2000 is typical.

SLOTA_CH3_OFFSET Time Slot A Channel 3 ADC offset. The value to subtract from the raw ADC

value. A value of 0x2000 is typical.

SLOTA_CH4_OFFSET Time Slot A Channel 4 ADC offset. The value to subtract from the raw ADC

value. A value of 0x2000 is typical.

SLOTB_CH1_OFFSET Time Slot B Channel 1 ADC offset. The value to subtract from the raw ADC

value. A value of 0x2000 is typical.

Rev. A | Page 63 of 66

ADPD105/ADPD106/ADPD107

Data Sheet

Data

Address Bits

Default Access Name

Description

0x1F

0x20

0x21

[15:0]

0x2000 R/W

SLOTB_CH2_OFFSET Time Slot B Channel 2 ADC offset. The value to subtract from the raw ADC

value. A value of 0x2000 is typical.

[15:0]

SLOTB_CH3_OFFSET Time Slot B Channel 3 ADC offset. The value to subtract from the raw ADC

value. A value of 0x2000 is typical.

SLOTB_CH4_OFFSET Time Slot B Channel 4 ADC offset. The value to subtract from the raw ADC

value. A value of 0x2000 is typical.

DATA REGISTERS

Table 35. Data Registers

Data

Address Bits

Access Name

FIFO_DATA

Description

0x60

0x64

0x65

0x66

0x67

0x68

0x69

0x6A

0x6B

0x70

0x71

0x72

0x73

0x74

0x75

0x76

0x77

0x78

0x79

0x7A

0x7B

0x7C

0x7D

0x7E

0x7F

[15:0]

R

Next available word in FIFO.

[15:0]

SLOTA_CH1_16BIT

SLOTA_CH2_16BIT

SLOTA_CH3_16BIT

SLOTA_CH4_16BIT

SLOTB_CH1_16BIT

SLOTB_CH2_16BIT

SLOTB_CH3_16BIT

SLOTB_CH4_16BIT

SLOTA_CH1_LOW

SLOTA_CH2_LOW

SLOTA_CH3_LOW

SLOTA_CH4_LOW

SLOTA_CH1_HIGH

SLOTA_CH2_HIGH

SLOTA_CH3_HIGH

SLOTA_CH4_HIGH

SLOTB_CH1_LOW

SLOTB_CH2_LOW

SLOTB_CH3_LOW

SLOTB_CH4_LOW

SLOTB_CH1_HIGH

SLOTB_CH2_HIGH

SLOTB_CH3_HIGH

SLOTB_CH4_HIGH

16-bit value of Channel1 in Time Slot A.

16-bit value of Channel 2 in Time Slot A.

16-bit value of Channel 3 in Time Slot A.

16-bit value of Channel 4 in Time Slot A.

16-bit value of Channel 1 in Time Slot B.

16-bit value of Channel 2 in Time Slot B.

16-bit value of Channel 3 in Time Slot B.

16-bit value of Channel 4 in Time Slot B.

Low data-word for Channel 1 in Time Slot A.

Low data-word for Channel 2 in Time Slot A.

Low data-word for Channel 3 in Time Slot A.

Low data-word for Channel 4 in Time Slot A.

High data-word for Channel 1 in Time Slot A.

High data-word for Channel 2 in Time Slot A.

High data-word for Channel 3 in Time Slot A.

High data-word for Channel 4 in Time Slot A.

Low data-word for Channel 1 in Time Slot B.

Low data-word for Channel 2 in Time Slot B.

Low data-word for Channel 3 in Time Slot B.

Low data-word for Channel 4 in Time Slot B.

High data-word for Channel 1 in Time Slot B.

High data-word for Channel 2 in Time Slot B.

High data-word for Channel 3 in Time Slot B.

High data-word for Channel 4 in Time Slot B.

2. Write 0x0001 to Register 0x10 to enter program mode.

REQUIRED START-UP LOAD PROCEDURE

3. Write to the other registers; the register order is not

important while the device is in program mode.

4. Write 0x0002 to Register 0x10 to start normal sampling

operation.

The required start-up load procedure is as follows:

1. Write to 0x1 to Register 0x4B, Bit 7 to enable the clock that

drives the state machine.

Rev. A | Page 64 of 66

Data Sheet

ADPD105/ADPD106/ADPD107

OUTLINE DIMENSIONS

0.25

0.20

0.15

4.10

4.00 SQ

3.90

PIN 1

INDICATOR

PIN 1

INDICATOR

22

28

1

21

0.40

BSC

EXPOSED

PAD

2.70

2.60 SQ

2.50

7

15

14

8

0.45

0.40

0.35

0.20 MIN

TOP VIEW

BOTTOM VIEW

0.80

0.75

0.70

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-WGGE.

Figure 54. 28-Lead Lead Frame Chip Scale Package [LFCSP]

4 mm × 4 mm Body and 0.75 mm Package Height

(CP-28-5)

Dimensions shown in millimeters

1.44

1.40

1.36

3

2

1

0.225

A

B

C

D

E

F

BALL A1

IDENTIFIER

2.00

REF

2.50

2.46

2.42

0.40

BSC

BOTTOM VIEW

(BALL SIDE UP)

TOP VIEW

(BALL SIDE DOWN)

0.235

0.300

0.330

0.300

0.270

0.560

0.500

0.440

END VIEW

COPLANARITY

0.05

SEATING

PLANE

0.230

0.200

0.170

0.300

0.260

0.220

Figure 55. 16-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-16-18)

Dimensions shown in millimeters

Rev. A | Page 65 of 66

ADPD105/ADPD106/ADPD107

Data Sheet

1.44

1.40

1.36

3

2

1

A

B

C

D

E

F

BALL A1

IDENTIFIER

2.00

REF

2.50

2.46

2.42

0.40

BSC

BOTTOM VIEW

(BALL SIDE UP)

TOP VIEW

(BALL SIDE DOWN)

0.80 REF

0.330

0.300

0.270

0.560

0.500

0.440

END VIEW

COPLANARITY

0.05

SEATING

PLANE

0.230

0.200

0.170

0.300

0.260

0.220

Figure 56. 17-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-17-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

ADPD105BCPZ

ADPD105BCPZRL

ADPD105BCBZR7

ADPD106BCBZR7

ADPD107BCBZR7

EVAL-ADPD105Z-GEN

Temperature Range Package Description

Package Option

CP-28-5

CB-16-18

CB-17-1

−40°C to +85°C

28-Lead Lead Frame Chip Scale Package [LFCSP]

16-Ball Wafer Level Chip Scale Package [WLCSP]

17-Ball Wafer Level Chip Scale Package [WLCSP]

Generic ADPD105 Evaluation Board²

¹Z = RoHS Compliant Part.

²This evaluation board is used for the ADPD105, ADPD106, and ADPD107.

registered trademarks are the property of their respective owners.

D14693-0-1/17(A)

Rev. A | Page 66 of 66


型号：	ADPD106
厂家：	ADI
描述：	Photometric Front Ends
文件：	总66页 (文件大小：884K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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