ADPD188GG [ADI]
Integrated Optical Module with Ambient Light Rejection and Two LEDs;型号: | ADPD188GG |
厂家: | ADI |
描述: | Integrated Optical Module with Ambient Light Rejection and Two LEDs |
文件: | 总61页 (文件大小:1068K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Integrated Optical Module with Ambient
Light Rejection and Two LEDs
Data Sheet
ADPD188GG
FEATURES
GENERAL DESCRIPTION
3.8 mm × 5.0 mm × 0.9 mm module with integrated optical
components
2 green LEDs, 2 PDs with IR cut filter
2 external sensor inputs
3, 370 mA LED drivers
20-bit burst accumulator enabling 20 bits per sample period
On-board sample to sample accumulator enabling up to
27 bits per data read
Custom optical package made to work under a glass window
Optimized SNR for signal limited cases
I2C or SPI communications
The ADPD188GG is a complete photometric system designed to
measure optical signals from ambient light and from synchronous
reflected light emitting diode (LED) pulses. Synchronous measure-
ment offers best-in-class rejection of ambient light interference,
both dc and ac. The module integrates a highly efficient photo-
metric front end, two LEDs, and two photodiode (PD). All of
these items are housed in a custom package that prevents light
from going directly from the LED to the photodiode without first
entering the subject.
The front end of the application specific integrated circuit (ASIC)
consists of a control block, a 14-bit analog-to-digital converter
(ADC) with a 20-bit burst accumulator, and three flexible,
independently configurable LED drivers. The control circuitry
includes flexible LED signaling and synchronous detection.
The analog front end (AFE) features best-in-class rejection of
signal offset and corruption due to modulated interference
commonly caused by ambient light. The data output and
functional configuration occur over a 1.8 V I2C interface or a
serial peripheral interface (SPI) port.
APPLICATIONS
Optical heart rate monitoring
Reflective PPG measurement
CNIBP measurement
FUNCTIONAL BLOCK DIAGRAM
VDD1
VDD2
PDC
ADPD188GG
PD1
EXT_IN1
CH1
BPF
BPF
±1 INTEGRATOR
±1 INTEGRATOR
TIA_VREF
VREF
PD2
1µF
EXT_IN2
CH2
TIA_VREF
PDC
PDET1
PD3
CS
CH3
BPF
BPF
±1 INTEGRATOR
±1 INTEGRATOR
SCLK
MOSI
MISO
TIME SLOT A
TIA_VREF
DATA
PDET2
PD4
14-BIT
ADC
CH4
TIME SLOT B
DATA
SDA
SCL
VLED1
TIA_VREF
GREEN
GPIO0
GPIO1
DIGITAL
INTERFACE
AND
LED1/DNC
CONTROL
LED1 DRIVER
LED3 DRIVER
LED3
LED2
LED2 DRIVER
LGND
AGND
DGND
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN WHEN USING INTERNAL LEDs.
Figure 1.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog
Devices. Trademarks and registeredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2018–2020 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADPD188GG
Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
Typical Connection Diagram................................................... 22
Land Pattern ............................................................................... 22
Recommended Start-Up Sequence.......................................... 23
Reading Data............................................................................... 23
Clocks and Timing Calibration................................................ 24
Optional Timing Signals Available on GPIO0 and GPIO1 . 25
LED Driver Pins and LED Supply Voltage............................. 26
LED Driver Operation............................................................... 26
Determining the Average Current........................................... 27
Determining CVLED ..................................................................... 27
Using External LEDs ................................................................. 28
Calculating Current Consumption.......................................... 28
Mechanical Considerations for Covering the ADPD188GG ... 31
TIA ADC Mode.......................................................................... 31
Pulse Connect Mode.................................................................. 33
Applications ...................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications .................................................................................... 3
Analog Specifications................................................................... 5
Digital Specifications ................................................................... 6
Timing Specifications .................................................................. 7
Absolute Maximum Ratings ........................................................... 9
Thermal Resistance...................................................................... 9
Recommended Soldering Profile ............................................... 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions .......................... 10
Typical Performance Characteristics........................................... 11
Theory of Operation ...................................................................... 13
Introduction................................................................................ 13
Optical Components.................................................................. 13
Dual Time Slot Operation......................................................... 14
Time Slot Switch......................................................................... 15
Adjustable Sampling Frequency............................................... 16
External Synchronization for Sampling.................................. 16
State Machine Operation .......................................................... 16
Normal Mode Operation and Data Flow................................ 17
Communications Interface ........................................................... 19
I2C Interface ................................................................................ 19
SPI Port........................................................................................ 20
Applications Information.............................................................. 22
Synchronous ECG and PPG Measurement Using TIA ADC
Mode ............................................................................................ 34
Float Mode .................................................................................. 35
Register Listing ............................................................................... 42
LED Control Registers............................................................... 46
AFE Configuration Registers.................................................... 48
Float Mode Registers ................................................................. 52
System Registers......................................................................... 55
ADC Registers ............................................................................ 59
Data Registers ............................................................................. 60
Outline Dimensions....................................................................... 61
Ordering Guide .......................................................................... 61
REVISION HISTORY
4/2020—Rev. A to Rev. B
10/2018—Rev. 0 to Rev. A
Change to Applications Section ..................................................... 1
Changes to Table 4 and Figure 2.................................................... 7
Change to Reset Column, Table 26.............................................. 42
Added Endnote 1, Table 27........................................................... 46
Changes to Table 32....................................................................... 55
Changes to Figure 24 and Figure 25............................................ 22
Changes to Calibrating the 32 kHz Clock Section..................... 25
Added Improving SNR Using Integrator Chopping Section and
Figure 32; Renumbered Sequentially........................................... 29
Added Table 18; Renumbered Sequentially ............................... 30
Changes to Table 26....................................................................... 42
Changes to Table 29....................................................................... 50
Changes to Table 30....................................................................... 51
Changes to Address 0x58 Description Column, Table 31........ 53
2/2018—Revision 0: Initial Version
Rev. B | Page 2 of 61
Data Sheet
ADPD188GG
SPECIFICATIONS
The voltage applied at the VDD1 and VDD2 pins (VDD) = 1.8 V, and TA = full operating temperature range, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max Unit
CURRENT CONSUMPTION
See the Calculating Current Consumption section for the relevant
equations
Peak VDD Supply Current
VDD Standby Current
Single-channel (Register 0x3C, Bits[8:3] = 0x38)
4.5
0.3
mA
µA
Average VDD Supply Current
100 Hz data rate; LED offset = 25 µs; LED pulse period (tLED_PERIOD) =
13 µs; LED peak current = 25 mA
1 Pulse
Time Slot A only
Time Slot B only
Both Time Slot A and Time Slot B
Time Slot A only
Time Slot B only
Both Time Slot A and Time Slot B
LED peak current = 25 mA
50 Hz data rate
100 Hz data rate
200 Hz data rate
53
41
76
107
95
µA
µA
µA
µA
µA
µA
10 Pulses
184
Average VLED Supply Current
1 Pulse
3.75
7.5
15
38
75
µA
µA
µA
µA
µA
µA
10 Pulses
50 Hz data rate
100 Hz data rate
200 Hz data rate
150
SATURATION ILLUMINANCE1
Direct Illumination
Blackbody color temperature (T = 5500 K)2, PDET1 and PDET2
multiplexed into a single channel (1.2 mm2active area)
Transimpedance amplifier (TIA) gain = 25 kΩ
TIA gain = 50 kΩ
58.8
29.4
14.7
7.4
kLux
kLux
kLux
kLux
TIA gain = 100 kΩ
TIA gain = 200 kΩ
DATA ACQUISITION
ADC Resolution
Per Sample
Per Data Read
LED PERIOD
Single pulse
14
20
27
19
17
Bits
Bits
Bits
64 pulses to 255 pulses
64 pulses to 255 pulses; 128 samples averaged
AFE width = 4 µs3
AFE width = 3 µs
Time Slot A or Time Slot B; normal mode; 1 pulse;
SLOTA_LED_OFFSET = 23 µs; SLOTA_PERIOD = 19 µs
13
11
0.122
µs
µs
Sampling Frequency4
2000 Hz
Both time slots; normal mode; 1 pulse;
SLOTA_LED_OFFSET = 23 µs; SLOTA_PERIOD = 19 µs
Time Slot A or Time Slot B; normal mode; 8 pulses;
SLOTA_LED_OFFSET = 23 µs; SLOTA_PERIOD = 19 µs
0.122
0.122
0.122
1600 Hz
1600 Hz
1000 Hz
Both time slots; normal mode; 8 pulses;
SLOTA_LED_OFFSET = 23 µs; SLOTA_PERIOD = 19 µs
Rev. B | Page 3 of 61
ADPD188GG
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max Unit
CATHODE PIN (PDC) VOLTAGE
During All Sampling Periods
Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 15
Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 0
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x05
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x1
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x2
1.8
1.3
1.8
1.3
TIA_VREF +
0.25
0
1.8
1.3
TIA_VREF +
0.25
0
1.8
1.3
1.8
1.3
TIA_VREF +
0.25
V
V
V
V
V
During Time Slot A Sampling
During Time Slot B Sampling
During Sleep Periods
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x36
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x05
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x1
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x2
V
V
V
V
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x36
Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 1
Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 0
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x0
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x1
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x2
V
V
V
V
V
V
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x3
0
V
LEDs
LED Peak Current Setting
Adjustable via the Register 0x22 through Register 0x25
settings
12
370
mA
Dominant Wavelength7
LED1; Green LED
Luminous Intensity
Photodiode
IF = 40 mA
λ = 525 nm, IF = 40 mA at 25°C
525
nm
2800
3200 mcd
A/W
Responsivity
Wavelength, λ = 525 nm
0.25
Active Area
Photodiode 1
Photodiode 2
0.4
0.8
mm2
mm2
POWER SUPPLY VOLTAGES
VDD
VLED1
DC Power Supply Rejection
Ratio (PSRR)
The ADPD188GG does not require a specific power-up sequence
Applied at the VDD1 and VDD2 pins
1.7
4
1.8
4.5
24
1.9
5.0
V
V
dB
8, 9
At 75% full scale input signal
TEMPERATURE RANGE
Operating
−40
+85
°C
1 Saturation illuminance refers to the amount of ambient light that saturates the ADPD188GG signal. Actual results may vary by factors of up to 2× from typical
specifications. As a point of reference, Air Mass 1.5 (AM1.5) sunlight (brightest sunlight) produces 100 kLux.
2 Blackbody color temperature (T = 5800 K) closely matches the light produced by solar radiation (sunlight).
3 Minimum LED period = (2 × AFE width) + 5 µs.
4 The maximum values in this specification are the internal ADC sampling rates in normal mode. The I2C read rates in some configurations may limit the output data rate.
5 This mode may induce additional noise and is not recommended unless necessary. The 1.8 V setting uses VDD, which contains greater amounts of differential voltage
noise with respect to the anode voltage. A differential voltage between the anode and cathode injects a differential current across the capacitance of the photodiode
of the magnitude of C × dV/dt.
6 This setting is not recommended for photodiodes because it causes a 1.3 V forward bias of the photodiode.
7 IF is the forward current of the diode.
8 Set VLEDx such that the maximum desired LED current is achievable with the turn on voltage of the LEDs that are wired to the LEDx/DNC pins. The LEDx/DNC pins are
connected to the LEDx driver, which can be modeled as current sinks (see Figure 1). When an appropriate VLEDx is used, the voltage at the LEDx/DNC pins adjusts
automatically to accommodate the LED turn on voltage and the LED current.
9 See Figure 9 for the current limitation at the minimum VLED supply voltage, VLED
.
Rev. B | Page 4 of 61
Data Sheet
ADPD188GG
ANALOG SPECIFICATIONS
VDD1 = VDD2 = 1.8 V, and TA = full operating temperature range, unless otherwise noted.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max Unit
EXT_INx SERIES RESISTANCE (R_IN)1
Measured from −3 µA to +3 µA
6.5
kΩ
PULSED SIGNAL CONVERSIONS, 3 μs
4 μs wide AFE integration; normal operation,
Register 0x43 and Register 0x45 = 0xADA5
TIA feedback resistor
25 kΩ
WIDE LED PULSE2
ADC Resolution3
3.27
1.64
0.82
0.41
nA/LSB
nA/LSB
nA/LSB
nA/LSB
50 kΩ
100 kΩ
200 kΩ
ADC Saturation Level
TIA feedback resistor
25 kΩ
26.8
13.4
6.7
μA
μA
μA
μA
50 kΩ
100 kΩ
200 kΩ
3.35
Ambient Signal Headroom on Pulsed
Signal
TIA feedback resistor
25 kΩ
50 kΩ
100 kΩ
200 kΩ
23.6
11.8
5.9
μA
μA
μA
μA
2.95
PULSED SIGNAL CONVERSIONS, 2 μs
WIDE LED PULSE2
ADC Resolution3
3 μs wide AFE integration; normal operation, Register 0x43
and Register 0x45 = 0xADA5
TIA feedback resistor
25 kΩ
4.62
2.31
1.15
0.58
nA/LSB
nA/LSB
nA/LSB
nA/LSB
50 kΩ
100 kΩ
200 kΩ
ADC Saturation Level
TIA feedback resistor
25 kΩ
37.84
18.92
9.46
μA
μA
μA
μA
50 kΩ
100 kΩ
200 kΩ
4.73
Ambient Signal Headroom on Pulsed
Signal
TIA feedback resistor
25 kΩ
50 kΩ
100 kΩ
200 kΩ
12.56
6.28
3.14
1.57
μA
μA
μA
μA
FULL SIGNAL CONVERSIONS4
TIA Saturation Level Pulsed Signal and
Ambient Level
TIA feedback resistor
25 kΩ
50 kΩ
100 kΩ
200 kΩ
50.4
25.2
12.6
6.3
μA
μA
μA
μA
TIA Linear Range
TIA feedback resistor
25 kΩ
42.8
21.4
10.7
5.4
μA
μA
μA
μA
50 kΩ
100 kΩ
200 kΩ
Rev. B | Page 5 of 61
ADPD188GG
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max Unit
SYSTEM PERFORMANCE
Total Output Noise Floor
Normal mode; per pulse; per channel; no LED; photodiode
capacitance (CPD) = 25 pF
25 kΩ; referred to ADC input
25 kΩ; referred to peak input signal for 2 µs LED pulse
25 kΩ; referred to peak input signal for 3 µs LED pulse
25 kΩ; saturation signal-to-noise ratio (SNR) per pulse per
channel5
1.0
4.6
3.3
78.3
LSB rms
nA rms
nA rms
dB
50 kΩ; referred to ADC input
1.1
2.5
1.8
77.4
1.2
LSB rms
nA rms
nA rms
dB
LSB rms
nA rms
nA rms
dB
LSB rms
nA rms
nA rms
dB
50 kΩ; referred to peak input signal for 2 µs LED pulse
50 kΩ; referred to peak input signal for 3 µs LED pulse
50 kΩ; saturation SNR per pulse per channel5
100 kΩ; referred to ADC input
100 kΩ; referred to peak input signal for 2 µs LED pulse
100 kΩ; referred to peak input signal for 3 µs LED pulse
100 kΩ; saturation SNR per pulse per channel5
200 kΩ; referred to ADC input
1.4
0.98
76.7
1.4
0.81
0.57
75.3
200 kΩ; referred to peak input signal for 2 µs LED pulse
200 kΩ; referred to peak input signal for 3 µs LED pulse
200 kΩ; saturation SNR per pulse per channel5
1 The R_IN value can be ignored for current source inputs or for PD inputs. This value is important for calculating correct voltages for voltage inputs through a resistor.
2 This saturation level applies to the ADC only and, therefore, includes only the pulsed signal. Any nonpulsatile signal is removed prior to the ADC stage.
3 ADC resolution is listed per pulse. If using multiple pulses, divide by the number of pulses.
4 This saturation level applies to the full signal path and, therefore, includes both the ambient signal and the pulsed signal.
5 The noise term of the saturation SNR value refers to the receive noise only and does not include photon shot noise or any noise on the LED signal itself.
DIGITAL SPECIFICATIONS
VDD1 = VDD2 = 1.7 V to 1.9 V, unless otherwise noted.
Table 3.
Parameter
LOGIC INPUTS
Input Voltage Level
High
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
VIH
VIH
VIL
GPIOx, SCLK, MOSI, CS
SCL, SDA
0.7 × VDDx
0.7 × VDDx
VDDx
V
V
High
Low
3.6
0.3 × VDDx
Input Current Level
High
Low
Input Capacitance
LOGIC OUTPUTS
Output Voltage Level
High
IIH
IIL
CIN
−10
−10
+10
+10
µA
µA
pF
10
GPIOx, MISO
VOH
VOL
2 mA high level output current
2 mA low level output current
SDA
2 mA low level output current
SDA
VDDx − 0.5
V
V
Low
0.5
Output Voltage Level
Low
Output Current Level
Low
VOL1
IOL
0.2 × VDDx
V
VOL1 = 0.6 V
6
mA
Rev. B | Page 6 of 61
Data Sheet
ADPD188GG
TIMING SPECIFICATIONS
I2C Timing Specifications
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
SCL
Frequency
1
0.4
Mb/sec
Minimum Pulse Width
High
Low
t1
t2
370
530
ns
ns
START CONDITION
Hold Time
t3
t4
t5
t9
260
260
50
ns
ns
ns
ns
Setup Time
SDA SETUP TIME
SDA HOLD TIME
SCL AND SDA
Rise Time
0
t6
t7
1000
300
ns
ns
Fall Time
STOP CONDITION
Setup Time
t8
260
ns
t5
t3
t3
t9
SDA
SCL
t6
t1
t2
t7
t4
t8
Figure 2. I2C Timing Diagram
Rev. B | Page 7 of 61
ADPD188GG
Data Sheet
SPI Timing Specifications
Table 5.
Parameter
SCLK
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
Frequency
Minimum Pulse Width
High
fSCLK
10
MHz
tSCLKPWH
tSCLKPWL
20
20
ns
ns
Low
CS
Setup Time
tCS
CS setup to SCLK rising edge
CS hold from SCLK rising edge
CS pulse width high
10
10
10
ns
ns
ns
S
Hold Time
tCS
H
Pulse Width High
tCS
PWH
MOSI
Setup Time
Hold Time
ns
ns
tMOSIS
tMOSIH
tMISOD
MOSI setup to SCLK rising edge
MOSI hold from SCLK rising edge
10
10
MISO OUTPUT DELAY
MISO valid output delay from SCLK
falling edge
21
ns
tCSH
tCSS
tCSPWH
tSCLKPWL
tSCLKPWH
CS
SCLK
MOSI
tMOSIH
tMOSIS
MISO
tMISOD
Figure 3. SPI Timing Diagram
Rev. B | Page 8 of 61
Data Sheet
ADPD188GG
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED SOLDERING PROFILE
Table 6.
Figure 4 and Table 8 provide details about the recommended
soldering profile.
Parameter
Rating
VDD1, VDD2 to AGND
VDD1, VDD2 to DGND
EXT_IN1/EXT_IN2
−0.3 V to +2.2 V
−0.3 V to +2.2 V
−0.3 V to +2.2V
−0.3 V to +2.2 V
−0.3 V to +2.2 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +5.0 V
CRITICAL ZONE
P
T
TO T
P
L
T
P
GPIO0/GPIO1 to DGND
MISO/MOSI/SCLK/CS to DGND
LEDx/DNC to LGND
SCL/SDA to DGND
T
L
T
L
SMAX
T
SMIN
VLEDx to LGND1
tS
RAMP-DOWN
PREHEAT
Electrostatic Discharge (ESD)
Human Body Model (HBM)
Charged Device Model (CDM)
Machine Model (MM)
Solder Reflow (Pb-Free)
Peak Temperature
Time at Peak Temperature
Temperature Range
Powered
3000 V
1250 V
100 V
t25°C TO PEAK
TIME
Figure 4. Recommended Soldering Profile
260 (+0/−5)°C
<30 sec
Table 8. Recommended Soldering Profile
Profile Feature
Condition (Pb-Free)
Average Ramp Rate (TL to TP)
Preheat
2°C/sec max
−40°C to +85°C
−40°C to +105°C
105°C
Storage
Junction Temperature
Minimum Temperature (TSMIN
)
150°C
Maximum Temperature (TSMAX
Time, TSMIN to TSMAX (tS)
TSMAX to TL Ramp-Up Rate
)
200°C
60 sec to 120 sec
2°C/sec max
1 The absolute maximum voltage allowable between VLEDx and LGND is the
voltage that causes the LEDx/DNC pins to reach or exceed their absolute
maximum voltage.
Time Maintained Above Liquidous
Temperature
Liquidous Temperature (TL)
Time (tL)
Peak Temperature (TP)
Time Within 5°C of Actual Peak
Temperature (tP)
Ramp-Down Rate
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
217°C
60 sec to 150 sec
260 (+0/−5)°C
<30 sec
3°C/sec max
Time 25°C to Peak Temperature
8 minutes max
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
ESD CAUTION
Table 7. Thermal Resistance
Package Type1
CE-24-1
ASIC
Supply Pins
θJA
Unit
VDD1, VDD2
VLED1
67
°C/W
LED1
156 °C/W
1 Thermal impedance simulated values are based on JEDEC 2S2P and two
thermal vias. See JEDEC JESD51.
Rev. B | Page 9 of 61
ADPD188GG
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
19
18
17
16
15
14
13
1
2
3
4
5
6
PDC
EXT_IN2
NIC
CS
SCLK
MOSI
MISO
GPIO1
GPIO0
SDA
ADPD188GG
TOP VIEW
VDD2
VLED1
NIC
(Not to Scale)
NIC
7
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN
WHEN USING INTERNAL LEDs.
2. NIC = NO INTERNAL CONNECTION.
Figure 5. Pin Configuration
Table 9. Pin Function Descriptions
Pin No. Mnemonic Type1
Description
Photodiode Common Cathode Bias.
1
2
3
4
5
6
7
PDC
EXT_IN2
NIC
VDD2
VLED1
NIC
AO
AI
NIC
S
S
NIC
NIC
EXT_IN2 Current Input.
No Internal Connection. This pin is not internally connected.
1.8 V Supply.
Green LED Anode Supply Voltage.
No Internal Connection. This pin is not internally connected.
No Internal Connection. This pin is not internally connected.
NIC
8
9
LED1/DNC
LED3
LED2
LGND
SCL
AO/DNC LED1 Driver Current Sink (LED1)/Do Not Connect (DNC). Do not connect to this pin when using internal LEDs.
AO
AO
S
LED3 Driver Current Sink. If not in use, leave this pin floating.
LED2 Driver Current Sink. If not in use, leave this pin floating.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
LED Driver Ground.
DI
I2C Clock Input.
SDA
DO
DIO
DIO
DO
DI
I2C Data Output.
GPIO0
GPIO1
MISO
MOSI
SCLK
General-Purpose Input/Output 0.
General-Purpose Input/Output 1.
SPI Master Input, Slave Output.
SPI Master Output, Slave Input.
DI
SPI Clock Input.
CS
DI
SPI Chip Select (Active Low).
DGND
AGND
VREF
VDD1
EXT_IN1
S
Digital Ground.
S
Analog Ground.
REF
S
Internally Generated ADC Voltage Reference. Connect a 1 µF ceramic capacitor from VREF to ground.
1.8 V Supply.
AI
EXT_IN1 Current Input.
1 AO is analog output, AI is analog input, NIC is not internally connected, S is supply, DNC is do not connect, DI is digital input, DO is digital output, DIO is digital input/output, and
REF is analog reference.
Rev. B | Page 10 of 61
Data Sheet
ADPD188GG
TYPICAL PERFORMANCE CHARACTERISTICS
0.35
FILTERED ADPD188
0.30
0.25
0.20
0.15
0.10
0.05
0
20
15
10
5
0
27.5 28.0 28.5 29.0 29.5 30.0 30.5 31.0 31.5 32.0
FREQUENCY (MHz)
200
300
400
500
600
700
800
900
1000
1100
WAVELENGTH (nm)
Figure 8. 32 MHz Clock Frequency Distribution; Default Settings;
Before User Calibration, Register 0x4D = 0x425E
Figure 6. Typical Photodiode Responsivity
400
30
LED COARSE SETTING = 0xF
350
300
250
200
150
100
25
20
15
10
5
50
LED COARSE SETTING = 0x0
0
0
–25
–20
–15
–10
–5
0
5
10
15
SAMPLE FREQUENCY DEVIATION FROM NOMINAL (%)
LED DRIVER VOLTAGE (V)
Figure 9. LED Driver Current vs. LED Driver Voltage at Various Coarse Settings
Figure 7. 32 kHz Clock Frequency Distribution; Default Settings;
Before User Calibration, Register 0x4B = 0x2612
Rev. B | Page 11 of 61
ADPD188GG
Data Sheet
0°
20°
0°
20°
HORIZONTAL
VERTICAL
HORIZONTAL
VERTICAL
1.0
0.8
1.0
0.8
40°
40°
60°
60°
80°
80°
0.6
0.6
0.4
0.2
0.2
0.4
0.6
0.6
0.4
0.2
0.2
0.4
Figure 10. PD1 Relative Sensitivity vs. Angular Displacement
Figure 12. LED Relative Intensity vs. Angular Displacement
0°
20°
1.0
0.8
HORIZONTAL
VERTICAL
40°
60°
80°
0.6
0.4
0.2
0.2
0.4
0.6
Figure 11. PD2 Relative Sensitivity vs. Angular Displacement
Rev. B | Page 12 of 61
Data Sheet
ADPD188GG
THEORY OF OPERATION
This highly integrated system works well in environments where
ambient light is poorly controlled and the signal modulation
ratio is low. As a result, the device produces high SNR for
relatively low LED power.
INTRODUCTION
The ADPD188GG is a complete, integrated, optical module
designed for photoplethysmography (PPG) measurements.
The module contains two optical detectors. Photodiode 1 (PDET1)
has 0.4 mm2 of active area and is connected to Channel 3 of the
ASIC. Photodiode 2 (PDET2) has 0.8 mm2 of active area and is
connected to Channel 4 of the ASIC. The two photodiodes can be
combined into a single detector with 1.2 mm2 of active area.
Both photo-diodes are coated with an infrared (IR) cut filter
that maximizes ambient light rejection without the need for other
light cancellation techniques.
OPTICAL COMPONENTS
Photodiode
The ADPD188GG integrates a 1.2 mm2 deep junction photodiode.
The optical sensing area is a dual detector that is connected to
Channel PD3 and Channel PD4 in the ASIC. The photodiodes
are accessible from Time Slot A or Time Slot B. The responsivity
of the ADPD188GG photodiode is shown in Figure 6.
The module combines the dual photodetector with two green
LEDs, and a mixed-signal, photometric, front-end ASIC into a
single compact device for optical measurements. The on-board
ASIC includes an analog signal processing block, an ADC, a
digital signal processing block, an I2C and SPI communication
interface, and three, independently programmable, pulsed LED
current sources.
LEDs
The ADPD188GG module integrates two green LEDs.
Table 10. LED Dominant Wavelength
LED Color
Driver
Typical Wavelength (nm)
Green (2×)
LED1
525
In addition to the integrated LEDs, the ADPD188GG has the
ability to drive external LEDs.
The core circuitry stimulates the LEDs and measures the
corresponding optical return signals in discrete data locations.
Data can be read from output registers directly or through a
first in, first out (FIFO) buffer.
1.67
1.42
PD1
PD2
5.0
Figure 13. Optical Component Locations
Rev. B | Page 13 of 61
ADPD188GG
Data Sheet
The timing parameters in Figure 14 are defined as follows:
DUAL TIME SLOT OPERATION
tA (µs) = 25 + nA × 19
The ADPD188GG operates in two independent time slots,
Time Slot A and Time Slot B, which are carried out sequentially.
The entire signal path from LED stimulation to data capture and
processing is executed during each time slot. Each time slot has
a separate datapath that uses independent settings for the LED
driver, AFE setup, and the resulting data. Time Slot A and
Time Slot B operate in sequence for every sampling period, as
shown in Figure 14.
where nA is the number of pulses for Time Slot A (Register 0x31,
Bits[15:8]).
tB (µs) = 25 + nB × 19
where nB is the number of pulses for Time Slot B (Register 0x36,
Bits[15:8]).
t1 = 68 µs, the processing time for Time Slot A
t2 = 20 µs, the processing time for Time Slot B
f
SAMPLE is the sampling frequency (Register 0x12, Bits[15:0]).
ACTIVE
tA
t1
tB
t2
nA PULSES
nB PULSES
SLEEP
TIME SLOT A
TIME SLOT B
1/f
SAMPLE
Figure 14. Time Slot Timing Diagram
Table 11. Recommended AFE and LED Timing Configuration
Address
Register Name
SLOTx_LEDMODE
SLOTx_AFEMODE
Time Slot A
0x30
0x39
Time Slot B
0x35
0x3B
Recommended Setting
0x0319
0x2209
Rev. B | Page 14 of 61
Data Sheet
ADPD188GG
PDC
TIME SLOT SWITCH
PDET2
Multiple configurations of the four input channels are supported,
depending on the settings of Register 0x14. The integrated
photodiodes can either be routed to Channel 3 and Channel 4,
or summed together into Channel 1. The external EXT_IN1
and EXT_IN2 inputs can be routed to Channel 1 and Channel 2,
respectively, or summed into Channel 2. See Figure 15 and
Figure 16 for the supported configurations. In Figure 15 and
Figure 16, PDET1 is Photodiode 1, and PDET2 is Photodiode 2.
PDET1
CH1
See Table 12 for the time slot switch registers. It is important to
leave any unused inputs floating for proper operation of the
devices. The photodiode inputs are current inputs and, as such,
these pins are also considered to be voltage outputs. Tying these
inputs to a voltage may saturate the analog block.
EXT_IN1
EXT_IN2
CH2
INPUT CONFIGURATION FOR
REGISTER 0x14[11:8] = 1
REGISTER 0x14[7:4] = 1
EXT_IN1
CH1
Figure 16. Current Summation
EXT_IN2
CH2
PDC
PDET1
CH3
PDC
PDET2
CH4
INPUT CONFIGURATION FOR
REGISTER 0x14[11:8] = 5
REGISTER 0x14[7:4] = 5
Figure 15. PD1 to PD4 Connection
Table 12. Time Slot Switch (Register 0x14)
Address
Bits
Name
Description
0x14
[11:8]
SLOTB_PD_SEL
These bits select the connection of input channels for Time Slot B as shown in Figure 15 and
Figure 16.
0x0: inputs are floating in Time Slot B.
0x1: PDET1 and PDET2 are connected to Channel 1; EXT_IN1 and EXT_IN2 are connected
to Channel 2 during Time Slot B.
0x5: EXT_IN1 is connected to Channel 1, EXT_IN2 is connected to Channel 2, PDET1 is
connected to Channel 3, and PDET2 is connected to Channel 4 during Time Slot B.
Other: reserved.
[7:4]
SLOTA_PD_SEL
These bits select the connection of input channels for Time Slot A as shown in Figure 15 and
Figure 16.
0x0: inputs are floating in Time Slot A.
0x1: PDET1 and PDET2 are connected to Channel 1; EXT_IN1 and EXT_IN2 are connected
to Channel 2 during Time Slot A.
0x5: EXT_IN1 is connected to Channel 1, EXT_IN2 is connected to Channel 2, PDET1 is
connected to Channel 3, and PDET2 is connected to Channel 4 during Time Slot A.
Other: reserved.
Rev. B | Page 15 of 61
ADPD188GG
Data Sheet
Providing an External 32 kHz Clock
ADJUSTABLE SAMPLING FREQUENCY
The ADPD188GG has an option for the user to provide an
external 32 kHz clock to the device for system synchronization
or for situations where a clock with better accuracy than the
internal 32 kHz clock is required. The external 32 kHz clock is
provided on the GPIO1 pin only. To enable the 32 kHz external
clock, use the following procedure at startup:
Register 0x12 controls the sampling frequency setting of the
ADPD188GG and Register 0x4B, Bits[5:0] further tunes this
clock for greater accuracy. The sampling frequency is governed
by an internal 32 kHz sample rate clock that also drives the
transition of the internal state machine. The maximum sampling
frequencies for some sample conditions are listed in Table 1. The
maximum sample frequency for all conditions, fSAMPLE,_MAX, is
determined by the following equation:
1. Drive the GPIO1 pin to a valid logic level or with the
desired 32 kHz clock prior to enabling the GPIO1 pin as
an input. Do not leave the pin floating prior to enabling it.
2. Write 0x1 to Register 0x4F, Bits[6:5] to enable the
GPIO1 pin as an input.
3. Write 0x2 to Register 0x4B, Bits[8:7] to configure the devices
to use an external 32 kHz clock. This setting disables the
internal 32 kHz clock and enables the external 32 kHz clock.
4. Write 0x1 to Register 0x10 to enter program mode.
5. Write additional control registers in any order while the
device is in program mode to configure the device as
required.
f
SAMPLE_MAX = 1/(tA + t1 + tB + t2 + tSLEEP_MIN)
where tSLEEP_MIN is the minimum sleep time required between
samples. See the Dual Time Slot Operation section for the
definitions of tA, t1, tB, and t2.
If a given time slot is not in use, elements from that time slot do
not factor into the calculation. For example, if Time Slot A is
not in use, tA and t1 do not add to the sampling period and the
new maximum sampling frequency is calculated as follows:
f
SAMPLE_MAX = 1/(tB + t2 + tSLEEP_MIN)
6. Write 0x2 to Register 0x10 to start the normal sampling
EXTERNAL SYNCHRONIZATION FOR SAMPLING
operation
The ADPD188GG provides an option to use an external
synchronization signal to trigger the sampling periods. This
external sample synchronization signal can be provided either
on the GPIO0 pin or the GPIO1 pin. This functionality is
controlled by Register 0x4F, Bits[3:2]. When enabled, a rising
edge on the selected input specifies when the next sample cycle
occurs. When triggered, there is a delay of one to two internal
sampling clock (32 kHz) cycles, and then the normal start-up
sequence occurs. This sequence is the same as when the normal
sample timer provides the trigger. To enable the external
synchronization signal feature, use the following procedure:
STATE MACHINE OPERATION
During each time slot, the ADPD188GG operates according to
a state machine. The state machine operates in the sequence
shown in Figure 17.
STANDBY
REGISTER 0x10 = 0x0000
ULTRALOW POWER MODE
NO DATA COLLECTION
ALL REGISTER VALUES ARE RETAINED.
1. Write 0x1 to Register 0x10 to enter program mode.
2. Write the appropriate value to Register 0x4F, Bits[3:2] to
select whether the GPIO0 pin or the GPIO1 pin specifies
when the next sample cycle occurs. Also, enable the
appropriate input buffer using Register 0x4F, Bit 1, for the
GPIO0 pin, or Register 0x4F, Bit 5, for the GPIO1 pin.
3. Write 0x4000 to Register 0x38.
PROGRAM
REGISTER 0x10 = 0x0001
SAFE MODE FOR PROGRAMMING REGISTERS
NO DATA COLLECTION
DEVICE IS FULLY POWERED IN THIS MODE.
NORMAL OPERATION
4. Write 0x2 to Register 0x10 to start the sampling
operations.
REGISTER 0x10 = 0x0002
LEDs ARE PULSED AND PHOTODIODES ARE SAMPLED
STANDARD DATA COLLECTION
DEVICE POWER IS CYCLED BY INTERNAL STATE MACHINE.
5. Apply the external synchronization signal on the selected
pin at the desired rate; sampling occurs at that rate. As
with normal sampling operations, read the data using the
FIFO or the data registers. The maximum frequency
constraints also apply in this case.
Figure 17. State Machine Operation Flowchart
Rev. B | Page 16 of 61
Data Sheet
ADPD188GG
The ADPD188GG operates in one of three modes: standby,
program, or normal sampling mode.
NORMAL MODE OPERATION AND DATA FLOW
In normal mode, the ADPD188GG follows a specific pattern set
up by the state machine. This pattern is shown in the corres-
ponding data flow diagram in Figure 18. The pattern, in order,
is as follows:
Standby mode is a power saving mode in which data collection
does not occur. All register values are retained in this mode. To
place the device in standby mode, write 0x0 to Register 0x10,
Bits[1:0]. The device powers up in standby mode.
1. LED pulse and sample. The ADPD188GG pulses external
LEDs. The response of the photodiode to the reflected light
is measured by the ADPD188GG. Each data sample is
constructed from the sum of n individual pulses, where n
is user configurable between 1 and 255.
2. Intersample averaging. If desired, the logic can average n
samples, from 2 to 128 in powers of 2, to produce output
data. New output data is saved to the output registers every
N samples.
3. Data read. The host processor reads the converted results
from the data register or the FIFO.
4. Repeat. The sequence has a few different loops that enable
different types of averaging while keeping both time slots
close in time relative to each other.
Program mode is used for programming registers. Always cycle
the ADPD188GG through program mode when writing registers
or changing modes. Because power cycling does not occur in this
mode, the device may consume higher current in program mode
than in normal operation. To place the device in program mode,
write 0x1 to Register 0x10, Bits[1:0].
In normal operation, the ADPD188GG pulses light and collects
data. Power consumption in this mode depends on the pulse
count and data rate. To place the device in normal sampling
mode, write 0x2 to Register 0x10, Bits[1:0].
[14 + LOG (n × N )] BITS
2
A
A
UP TO 27 BITS
[14 + LOG (n )] BITS
UP TO 20 BITS
N
2
A
A
16-BIT CLIP
IF VAL ≤ (2 – 1)
VAL = VAL
16 BITS
16
N
A
16
ELSE VAL = 2 – 1
1
14 BITS
14 BITS
n
A
20-BIT CLIP
IF VAL ≤ (2 – 1)
20
n
A
n
A
VAL = VAL
20
ELSE VAL = 2 – 1
0
1
14-BIT
ADC
1
REGISTER
0x11[13]
[14 + LOG (n )] BITS
2
A
16-BIT
DATA
REGISTERS
32-BIT DATA
REGISTERS
UP TO 22 BITS
FIFO
ADC OFFSET
SAMPLE 1: TIME SLOT A
SAMPLE 1: TIME SLOT B
0
1
SAMPLE N : TIME SLOT A
A
SAMPLE N : TIME SLOT B
B
TIME SLOT A
TIME SLOT B
N
B
16-BIT CLIP
16
IF VAL ≤ (2 – 1)
NOTES
1. n AND n = NUMBER OF LED PULSES FOR TIME SLOT A AND TIME SLOT B.
N
B
VAL = VAL
A
B
[14 + LOG (n )] BITS
UP TO 20 BITS
16
16 BITS
2
B
ELSE VAL = 2 – 1
1
2. N AND N = NUMBER OF AVERAGES FOR TIME SLOT A AND TIME SLOT B.
A
B
[14 + LOG (n × N )] BITS
2
B
B
UP TO 27 BITS
Figure 18. State Machine Operating Sequence (Datapath)
Rev. B | Page 17 of 61
ADPD188GG
Data Sheet
data is still acquired by the AFE at the sampling frequency,
SAMPLE (see Register 0x12), but new data is written to the
LED Pulse and Sample
f
At each sampling period, the selected LED driver drives a series
of LED pulses, as shown in Figure 19. The magnitude, duration,
and number of pulses are programmable over the communications
interface. Each LED pulse coincides with a sensing period so
that the sensed value represents the total charge acquired on the
photodiode in response to only the corresponding LED pulse.
Charge, such as ambient light that does not correspond to the
LED pulse, is rejected.
registers at the rate of fSAMPLE/N every Nth sample. This new data
consists of the sum of the previous N samples. The full 32-bit
sum is stored in the 32-bit registers. However, before sending
this data to the FIFO, a divide by N operation occurs. This
divide operation maintains bit depth to prevent clipping on the
FIFO.
Use this between sample averaging to lower the noise while
maintaining 16-bit resolution. If the pulse count registers are
kept to 8 or less, the 16-bit width is never exceeded. Therefore,
when using Register 0x15 to average subsequent pulses, many
pulses can be accumulated without exceeding the 16-bit word
width. This setting can reduce the number of FIFO reads
required by the host processor.
After each LED pulse, the photodiode output relating to the
pulsed LED signal is sampled and converted to a digital value
by the 14-bit ADC. Each subsequent conversion within a
sampling period is summed with the previous result. Up to 255
pulse values from the ADC can be summed in an individual
sampling period. There is a 20-bit maximum range for each
sampling period.
Data Read
Averaging
The host processor reads output data from the ADPD188GG
via the communications interface, from the data registers, or from
the FIFO. New output data is made available every N samples,
where N is the user configured averaging factor. The averaging
factors for Time Slot A and Time Slot B are configurable
independently of each other. If the factors are the same, both
time slots can be configured to save data to the FIFO. If the two
averaging factors are different, only one time slot can save data
to the FIFO; data from the other time slot can be read from the
output registers.
The ADPD188GG offers sample accumulation and averaging
functionality to increase signal resolution.
Within a sampling period, the AFE can sum up to 256 sequential
pulses. As shown in Figure 18, samples acquired by the AFE are
clipped to 20 bits at the output of the AFE. Additional resolution,
up to 27 bits, can be achieved by averaging between sampling
periods. This accumulated data of N samples is stored as 27-bit
values and can be read out directly by using the 32-bit output
registers or the 32-bit FIFO configuration.
The data read operations are described in more detail in the
Reading Data section.
When using the averaging feature set up by the register, subse-
quent pulses can be averaged by powers of 2. The user can
select from 2, 4, 8, …, up to 128 samples to be averaged. Pulse
SHOWN WITH f
SAMPLE
= 10Hz
OPTICAL SAMPLING
LOCATIONS
0
0.5
1.0
1.5
TIME (Seconds)
2.0
2.5
3.0
LED
CURRENT
(I
)
LED
NUMBER OF LED PULSES (nA OR nB
)
Figure 19. Example of a PPG Signal Sampled at a Data Rate of 10 Hz Using Five Pulses per Sample
Rev. B | Page 18 of 61
Data Sheet
ADPD188GG
COMMUNICATIONS INTERFACE
The ADPD188GG supports both an SPI and I2C serial interface,
although only one can be used at any given time in the actual
application. All internal registers are accessed through the
selected communications interface.
For multiword operations, each pair of data bytes is followed by
an acknowledge (ACK) from the host until the last byte of the
last word is read. The host indicates the last read word by
sending a no acknowledge. When reading from the FIFO
(Register 0x60), the data is automatically advanced to the next
word in the FIFO, and the space is freed. When reading from
other registers, the register address is automatically advanced to
the next register, allowing the user to read without readdressing
each register, thereby reducing the amount of overhead
required to read multiple registers. This auto-increment does
not apply to the register that precedes the FIFO, Register 0x5F,
or the last data register, Register 0x7E.
I2C INTERFACE
The ADPD188GG I2C conforms to the UM10204 I2C-Bus
Specification and User Manual, Rev. 05—9 October 2012,
available from NXP Semiconductors. The device supports fast
mode (400 kbps) data transfer. Register read and write operations
are supported, as shown in Figure 20. The 7-bit I2C slave address
2
CS
for the device is 0x64. If the I C interface is being used, the
pin must be pulled high to disable the SPI port.
All register writes are single-word only and require 16 bits
(one word) of data.
Single-word and multiword read operations are supported. For
a single register read, the host sends a no acknowledge (NACK)
after the second data byte is read and a new register address is
needed for each access.
The software reset (Register 0x0F, Bit 0) returns an
acknowledge. The device then returns to standby mode with all
registers in the default state.
Table 13. Definitions of I2C Terminology
Term
Description
SCL
Serial clock.
SDA
Serial address and data.
Master
Slave
Start (S)
Start (Sr)
Stop (P)
ACK
The device that initiates a transfer, generates clock signals, and terminates a transfer.
The device addressed by a master. The ADPD188GG operates as a slave device.
A high to low transition on the SDA line while SCL is high; all transactions begin with a start condition.
Repeated start condition.
A low to high transition on the SDA line while SCL is high. A stop condition terminates all transactions.
During the acknowledge (ACK) or no acknowledge (NACK) clock pulse, the SDA line is pulled low, and it remains low.
During the ACK or NACK clock pulse, the SDA line remains high.
NACK
Slave Address
Read (R)
Write (W)
After a start (S), a 7-bit slave address is sent, which is followed by a data direction bit (read or write).
A 1 indicates a request for data.
A 0 indicates a transmission.
2
I
C WRITE
REGISTER WRITE
MASTER START
SLAVE
SLAVE ADDRESS + WRITE
REGISTER ADDRESS
DATA[15:8]
DATA[7:0]
STOP
ACK
ACK
ACK
ACK
2
I
C SINGLE-WORD READ MODE
REGISTER READ
MASTER START
SLAVE
ACK
SLAVE ADDRESS + WRITE
REGISTER ADDRESS
REGISTER ADDRESS
Sr
Sr
SLAVE ADDRESS + READ
SLAVE ADDRESS + READ
NACK
STOP
STOP
DATA[15:8]
ACK
ACK
ACK
ACK
ACK
ACK
DATA[7:0]
2
I
C MULTIWORD READ MODE
REGISTER READ
MASTER START
SLAVE
ACK/NACK
SLAVE ADDRESS + WRITE
ACK
DATA[15:8]
DATA[7:0]
DATA TRANSFERRED
NOTES
1. THE SHADED AREAS REPRESENT WHEN THE DEVICE IS LISTENING.
Figure 20. I2C Write and Read Operations
Rev. B | Page 19 of 61
ADPD188GG
Data Sheet
R
Table 15. SPI Address and Write/ Byte Format
SPI PORT
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
CS
The SPI port uses a 4-wire interface, consisting of the
,
A6
A5
A4
A3
A2
A1
A0
W/R
MOSI, MISO, and SCLK signals, and it is always a slave port.
CS
The
signal goes low at the beginning of a transaction and
Data on the MOSI pin is captured on the rising edge of the
high at the end of a transaction. The SCLK signal latches MOSI
on a low to high transition. The MISO data is shifted out of the
device on the falling edge of SCLK and must be clocked into a
receiving device, such as a microcontroller, on the SCLK rising
edge. The MOSI signal carries the serial input data, and the
MISO signal carries the serial output data. The MISO signal
remains three-state until a read operation is requested, which
allows other SPI-compatible peripherals to share the same
MISO line. All SPI transactions have the same basic format
shown in Table 14. A timing diagram is shown in Figure 3.
Write all data MSB first.
clock, and data is propagated on the MISO pin on the falling
edge of the clock. The maximum read and write speed for the
SPI slave port is 10 MHz.
A sample timing diagram for a multiple word SPI write operation
to a register is shown in Figure 21. A sample timing diagram of
a single-word SPI read operation is shown in Figure 22. The
MISO pin transitions from being three-state to being driven
following the reception of a valid bit. In this example, Byte 0
contains the address and the W/ bit, and subsequent bytes
carry the data. A sample timing diagram of a multiple word SPI
read operation is shown in Figure 23. In Figure 21 to Figure 23,
rising edges on SCLK are indicated with an arrow, signifying
that the data lines are sampled on the rising edge.
R
R
Table 14. Generic Control Word Sequence
Byte 0
Byte 1
Byte 2
Subsequent Bytes
Address[6:0], Data[15:8]
W/R
Data[7:0]
Data[15:8], Data[7:0]
When performing multiple word reads or writes, the data
address is automatically incremented to the next consecutive
address for subsequent transactions except for Address 0x5F,
Address 0x60 (FIFO), and Address 0x7F.
The first byte written in a SPI transaction is a 7-bit address,
which is the location of the address being accessed, followed by
the W/ bit. This bit determines whether the communication is
R
a write (Logic Level 1) or a read (Logic Level 0). This format is
shown in Table 15.
Rev. B | Page 20 of 61
Data Sheet
ADPD188GG
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
CS
SCLK
MOSI
ADDRESS[6:0]
DATA BYTE 1
DATA BYTE 2
DATA BYTE N
Figure 21. SPI Slave Write Clocking (Burst Write Mode, N Bytes)
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CS
SCLK
MOSI
MISO
ADDRESS[6:0]
W/R
DATA BYTE 1
DATA BYTE 2
Figure 22. SPI Slave Read Clocking (Single-Word Mode, Two Bytes)
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
CS
SCLK
MOSI
MISO
ADDRESS[6:0]
W/R
DATA BYTE 1
DATA BYTE 2
DATA BYTE N
Figure 23. SPI Slave Read Clocking (Burst Read Mode, N Bytes)
Rev. B | Page 21 of 61
ADPD188GG
Data Sheet
APPLICATIONS INFORMATION
0.1µF
TYPICAL CONNECTION DIAGRAM
1.8V
1.0µF
Figure 24 shows the recommended connection diagram for the
ADPD188GG using the SPI communications port. Figure 25
shows a circuit using the I2C port. The desired communications
port, together with the GPIO0 and GPIO1 lines, connects to a
system microprocessor or sensor hub. When using the SPI port,
the I2C interface must be disabled by connecting the SDA and
SCL pins high to 1.8 V. When using the I2C interface, the SPI is
PDC
CS
1.8V
1
2
3
4
5
6
7
19
18
17
16
15
14
13
EXT_IN2
SCLK
MOSI
MISO
NIC
1.8V
0.1µF
CS
disabled by connecting to 1.8 V. Tie the unused inputs, SCLK
VDD2
ADPD188GG
and MOSI, to ground. The EXT_IN1 and EXT_IN 2 pins are
current inputs and can be connected to external sensors. A voltage
source can be connected to the EXT_IN1 and EXT_IN2 pins
through a series resistance, effectively converting the voltage
into a current (see the Using the EXT_IN 1 and EXT_IN 2
Inputs with a Voltage Source section).
VLED1
NIC
V
GPIO1
GPIO0
1.8V
LED1
C
VLED
NIC
10kΩ
SDA
Provide a regulated 1.8 V supply, tied to VDD1 and VDD2. The
VLEDx level uses a standard regulator circuit according to the
peak current requirements specified in Table 1 and calculated
in the Calculating Current Consumption section. Place 0.1 µF
ceramic decoupling capacitors as close as possible to VDD1 and
VDD2; a 1.0 µF ceramic capacitor must be placed as close as
possible to the VREF pin.
SCL
10kΩ
1.8V
Figure 25. I2C Mode Connection Diagram
LAND PATTERN
Figure 26 shows the recommended PCB footprint (land pattern).
Table 8 and Figure 4 provide the recommended soldering profile.
2.0mm
For best noise performance, connect AGND, DGND, and
LGND together at a large conductive surface such as a ground
plane, ground pour, or large ground trace.
0.28mm
0.56mm
0.1µF
1.8V
0.3mm
1.0µF
3.0mm
0.2mm
PDC
1
2
3
4
5
6
7
19
18
17
16
15
14
13
CS
0.18mm
EXT_IN2
SCLK
MOSI
MISO
GPIO1
GPIO0
Figure 26. Land Pattern
NIC
VDD2
ADPD188GG
1.8V
VLED
0.1µF
LED1
VLED1
V
C
NIC
NIC
SDA
1.8V
Figure 24. SPI Mode Connection Diagram
Rev. B | Page 22 of 61
Data Sheet
ADPD188GG
Reading Data Using the FIFO
RECOMMENDED START-UP SEQUENCE
The ADPD188GG includes a 128-byte FIFO memory buffer
that can be configured to store data from either or both time
slots. Register 0x11 selects the type of data from each time slot
to be written to the FIFO. Note that both time slots can be enabled
to use the FIFO, but only if their output data rate is the same.
At power-up, the device is in standby mode (Register 0x10 =
0x0), as shown in Figure 17. The ADPD188GG does not
require a particular power-up sequence.
From standby mode, to begin measurement, initiate the
ADPD188GG as follows:
Output Data Rate = fSAMPLE/Nx
1. Set the CLK32K_EN bit (Register 0x4B, Bit 7) to start the
sample clock (32 kHz clock). This clock controls the state
machine. If this clock is off, the state machine is not able to
transition as defined by Register 0x10.
2. Write 0x1 to Register 0x10 to force the device into
program mode. Step 1 and Step 2 can be swapped, but the
actual state transition does not occur until both steps
occur.
3. Write additional control registers in any order while the
device is in program mode to configure the devices as
required.
4. Write 0x2 to Register 0x10 to start normal sampling
operation.
where:
f
SAMPLE is the sampling frequency.
Nx is the averaging factor for each time slot (NA for Time Slot A
and NB for Time Slot B). In other words, NA = NB must be true
to store data from both time slots in the FIFO.
Data packets are written to the FIFO at the output data rate. A
data packet for the FIFO consists of a complete sample for each
enabled time slot. Data for each photodiode channel can be stored
as either 16 or 32 bits. Each time slot can store 2, 4, 8, or 16 bytes of
data per sample, depending on the mode and data format. To
ensure that data packets are intact, new data is only written to
the FIFO if there is sufficient space for a complete packet. Any
new data that arrives when there is not enough space is lost.
The FIFO continues to store data when sufficient space exists.
Always read FIFO data in complete packets to ensure that data
packets remain intact.
To terminate normal operation, follow this sequence to place
the ADPD188GG in standby mode:
1. Write 0x1 to Register 0x10 to force the devices into
program mode.
2. Write to the registers in any order while the devices are in
program mode.
3. Write 0x00FF to Register 0x00 to clear all interrupts. If
desired, clear the FIFO as well by writing 0x80FF to
Register 0x00.
4. Write 0x0 to Register 0x10 to force the devices into
standby mode.
The number of bytes currently stored in the FIFO is available in
Register 0x00, Bits[15:8]. A dedicated FIFO interrupt is also
available and automatically generates when a specified amount
of data is written to the FIFO.
Interrupt-Based Method
To read data from the FIFO using an interrupt-based method,
use the following procedure:
5. Optionally, stop the 32 kHz clock by resetting the CLK32K_
EN bit (Register 0x4B, Bit 7). Register 0x4B, Bit 7 = 0 is the
only write that must be written when the device is in standby
mode (Register 0x10 = 0x0). If 0 is written to this bit while in
program mode or normal mode, the devices become
unable to transition into any other mode, including standby
mode, even if they are subsequently written to do so. As a
result, the power consumption in what appears to be standby
mode is greatly elevated. For this reason, and due to the very
low current draw of the 32 kHz clock while in operation, it
is recommended from an ease of use perspective to keep the
32 kHz clock running after it is turned on.
1. In program mode, set the configuration of the time slots as
desired for operation.
2. Write Register 0x11 with the desired data format for each
time slot.
3. Set FIFO_THRESH in Register 0x06, Bits[13:8] to the
interrupt threshold. A recommended value for this is the
number of 16-bit words in a data packet, minus 1. This
causes an interrupt to generate when there is at least one
complete packet in the FIFO.
4. Enable the FIFO interrupt by writing a 0 to the FIFO_
INT_MASK in Register 0x01, Bit 8. Also, configure the
interrupt pin (GPIO0) by writing the appropriate value to
the bits in Register 0x02.
READING DATA
5. Enter normal operation mode by setting Register 0x10 to 0x2.
6. When an interrupt occurs,
The ADPD188GG provides multiple methods for accessing the
sample data. Each time slot can be independently configured to
provide data access using the FIFO or the data registers. Interrupt
signaling is also available to simplify timely data access. The
FIFO is available to loosen the system timing requirements for
data accesses.
a. There is no requirement to read the FIFO_SAMPLES bits,
because the interrupt is generated only if there is one or
more full packets. Optionally, the interrupt routine can
check for the presence of more than one available
packet by reading these bits.
Rev. B | Page 23 of 61
ADPD188GG
Data Sheet
b. Read a complete packet using one or more multiword
accesses using Register 0x60. Reading the FIFO
automatically frees the space for new samples.
3. An interrupt generates when the data registers are
updated.
4. The interrupt handler must perform the following:
a. Read Register 0x00 and observe Bit 5 or Bit 6 to confirm
which interrupt has occurred. This step is not required if
only one interrupt is in use.
The FIFO interrupt automatically clears immediately upon
reading any data from the FIFO and is set again only when the
FIFO is written and the number of words is above the
threshold.
b. Read the data registers before the next sample can be
written. The system must have interrupt latency and
service time short enough to respond before the next
data update, based on the output data rate.
c. Write a 1 to Bit 5 or Bit 6 in Register 0x00 to clear the
interrupt.
Polling Method
To read data from the FIFO in a polling method, use the
following procedure:
1. In program mode, set the configuration of the time slots as
If both time slots are in use, it is possible to use only the
Time Slot B interrupt to signal when all registers can be read. It
is recommended to use the multiword read to transfer the data
from the data registers.
desired for operation.
2. Write Register 0x11 with the desired data format for each
time slot.
3. Enter normal operation mode by setting Register 0x10 to
2.
Reading Data from Registers Without Interrupts
Next, begin the polling operations.
If the system interrupt response is not fast or predictable enough to
use the interrupt method, or if the interrupt pin (GPIOx) is not
used, it is possible to obtain reliable data access by using the data
hold mechanism. To guarantee that the data read from the
registers is from the same sample time, it is necessary to prevent
the update of samples while reading the current values. The
method for doing register reads without interrupt timing is as
follows:
1. Wait for the polling interval to expire.
2. Read the FIFO_SAMPLES bits (Register 0x00, Bits[15:8]).
3. If FIFO_SAMPLES ≥ the packet size, read a packet using
the following steps:
a. Read a complete packet using one or more multiword
accesses via Register 0x60. Reading the FIFO
automatically frees the space for new samples.
b. Repeat Step 1.
1. Write a 1 to SLOTA_DATA_HOLD or SLOTB_DATA_
HOLD (Register 0x5F, Bit 1 and Bit 2, respectively) for the
time slot requiring access (both time slots can be accessed).
This setting prevents sample updates.
2. Read the registers as desired.
3. Write a 0 to the SLOTA_DATA_HOLD or
SLOTB_DATA_
When a mode change is required, or any other disruption to
normal sampling is necessary, the FIFO must be cleared. Use
the following procedure to clear the state and empty the FIFO:
1. Enter program mode by setting Register 0x10 to 0x1.
2. Write 1 to Register 0x00, Bit 15.
HOLD bits (Register 0x5F, Bit 1 and Bit 2, respectively)
previously set. Sample updates are allowed again.
Reading Data from Registers Using Interrupts
The latest sample data is always available in the data registers and is
updated simultaneously at the end of each time slot. The data value
for each photodiode channel is available as a 16-bit value in Regis-
ter 0x64 through Register 0x67 for Time Slot A, and Register 0x68
through Register 0x6B for Time Slot B. If allowed to reach their
maximum value, Register 0x64 through Register 0x6B clip. If
Register 0x64 through Register 0x6B saturate, the unsaturated
(up to 27 bits) values for each channel are available in Register
0x70 through Register 0x77 for Time Slot A and Register 0x78
through Register 0x7F for Time Slot B. Sample interrupts are
available to indicate when the registers are updated and can be
read. To use the interrupt for a given time slot, use the
following procedure:
Because a new sample may arrive while the reads are occurring,
this method prevents the new sample from partially overwriting
the data being read.
CLOCKS AND TIMING CALIBRATION
The ADPD188GG operates using two internal time bases. A
32 kHz clock sets the sample timing, and a 32 MHz clock
controls the timing of internal functions such as LED pulsing
and data capture. Both clocks are internally generated and
exhibit device to device variation of approximately 10% (typical).
Heart rate monitoring (HRM) applications require an accurate
time base to achieve an accurate count of beats per minute. The
ADPD188GG provides a simple calibration procedure for both
clocks.
1. Enable the sample interrupt by writing a 0 to the appropriate
bit in Register 0x01. To enable the interrupt for Time Slot A,
write 0 to Bit 5. To enable the interrupt for Time Slot B,
write 0 to Bit 6. Either or both interrupts can be set.
2. Configure the interrupt pin (GPIOx) by writing the
appropriate value to the bits in Register 0x02.
Calibrating the 32 kHz Clock
This procedure calibrates items associated with the output data
rate. Calibration of this clock is important for items where an
accurate data rate is important, such as heart rate measurements.
Rev. B | Page 24 of 61
Data Sheet
ADPD188GG
To calibrate the 32 kHz clock,
OPTIONAL TIMING SIGNALS AVAILABLE ON
1. Set the sampling frequency to the highest the system can
handle, such as 2000 Hz. Because the 32 kHz clock
controls sample timing, its frequency is readily accessible
via the GPIO0 pin. Configure the interrupt by writing the
appropriate value to Bits[2:0] in Register 0x02 and set the
interrupt to occur at the sampling frequency by writing
0x0 to Register 0x01, Bit 5 or Bit 6. Monitor the GPIO0 pin.
The interrupt frequency must match the set sample
frequency.
2. If the monitored interrupt frequency is less than the set
sampling frequency, decrease the CLK32K_ADJUST bits
(Register 0x4B, Bits[5:0]). If the monitored interrupt
frequency is larger than the set sampling frequency,
increase the CLK32K_ADJUST bits.
GPIO0 AND GPIO1
The ADPD188GG provides a number of different timing
signals, available via the GPIO0 and GPIO1 pins, to enable ease
of system synchronization and flexible triggering options. Each
GPIOx pin can be configured as an open-drain output if they
are sharing the bus with other drivers, or they can be
configured to always drive the bus. Both outputs also have
polarity control in situations where a timing signal must be
inverted from the default.
Table 16. GPIOx Control Settings
Pin Name
Register, Bits Setting Description
GPIO0
0x02, Bit 0
0x02, Bit 1
0x02, Bit 2
0x02, Bit 8
0x02, Bit 9
0x4F, Bit 6
0: polarity active high
1: polarity active low
0: always drives the bus
1: drives the bus when asserted
0: disables the GPIO0 pin drive
1: enables the GPIO0 pin drive
0: polarity active high
1: polarity active low
0: always drives the bus
3. Repeat Step 1 until the monitored interrupt signal
frequency is close to the set sampling frequency.
Calibrating the 32 MHz Clock
This procedure calibrates items associated with the fine timing
within a sample period, such as LED pulse width and spacing,
and assumes that the 32 kHz clock is already calibrated.
GPIO1
To calibrate the 32 MHz clock,
1: drives the bus when asserted
0: disables the GPIO1 pin drive
1: enables the GPIO1 pin drive
1. Write 0x1 to Register 0x5F, Bit 0.
2. Enable the CLK_RATIO calculation by writing 0x1 to
Register 0x50, Bit 5 (CLK32M_CAL_EN). This function
counts the number of 32 MHz clock cycles in two cycles of
the 32 kHz clock. With this function enabled, this value is
stored in Register 0x0A, Bits[11:0] and nominally this ratio
is 2000 (0x07D0).
3. Calculate the 32 MHz clock error as follows:
Clock Error = 32 MHz × (1 − CLK_RATIO/2000)
4. Adjust the frequency by setting Bits[7:0] in Register 0x4D
per the following equation:
The various available timing signals are controlled by the
settings in Register 0x0B, Bits[12:8] of this register control the
timing signals available on GPIO1, and Bits[4:0] control the
timing signals available on GPIO0. All of the timing signals
described in this data sheet are available on either (or both) of
the GPIO0 and GPIO1 pins. Timing diagrams are shown in
Figure 27 and Figure 28. The time slot settings used to generate
the timing diagrams are described in Table 17.
CLK32M_ADJUST = Clock Error/109 kHz
5. Write 0x0 to Register 0x50, Bit 5 to reset the CLK_RATIO
function.
6. Repeat Step 1 through Step 5 until the desired accuracy is
achieved.
Table 17. ADPD188GG Settings Used for the Timing
Diagrams Shown in Figure 27 and Figure 28
Register Setting Description
0x31
0x36
0x15
0x0118 Time Slot A: 1 LED pulse
0x0418 Time Slot B: 4 LED pulses
0x0120 Time Slot A decimation = 4, Time Slot B
decimation = 2
7. Write 0x1 to Register 0x5F, Bit 0, and set the GPIO0 pin
back to the mode desired for normal operation.
SLEEP
SLOT A
SLOT B
SLOT A
SLOT B
Figure 27. Optional Timing Signals Available on GPIOx—Register 0x0B, Bits[12:8] or Bits[4:0] = 0x02, 0x05, 0x06, 0x07, and 0x0F
Rev. B | Page 25 of 61
ADPD188GG
Data Sheet
SLEEP
SLEEP
SLEEP
SLOT A/B
SLOT A/B
SLOT A/B
SLOT A/B
SLOT A/B
SLOT A/B
SLEEP
SLEEP
0x02
0x0C
0x0D
0x0E
Figure 28. Optional Timing Signals Available on GPIOx—Register 0x0B, Bits[12:8] or Bits[4:0] = 0x02, 0x0C, 0x0D, and 0x0E
Interrupt Function
fS/2 Output
Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x01 configures
the respective pin to perform the interrupt function as defined
by the settings in Register 0x01.
Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x0F configures
the respective pin to provide a signal that toggles at half the
sampling rate. The fS/2 timing signal always starts in an active
low state when the device switches from standby mode to
normal operating mode and transitions to a high state at the
completion of the first sample.
Sample Timing
Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x02 configures
the respective pin to provide a signal that asserts at the beginning
of the first time slot of the current sample and deasserts at the
end of the last time slot of the current sample. For example, if
both time slots are enabled, this signal asserts at the beginning
of Time Slot A and deasserts at the end of Time Slot B. If only a
single time slot is enabled, the signal asserts at the beginning of
the enabled time slot and deasserts at the end of this same time slot.
Logic 0 Output
Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x10 configures
the respective pin to provide a Logic 0 output.
Logic 1 Output
Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x11 configures
the respective pin to provide a Logic 1 output.
Pulse Outputs
32 kHz Oscillator Output
Three options are available to provide a copy of the LED pulse
outputs. Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x05
provides a copy of the Time Slot A LED pulses on the respective
pin. A setting of 0x06 provides the Time Slot B pulses, and a
setting of 0x07 provides the pulse outputs of both time slots.
Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x13 configures
the respective pin to provide a copy of the on-board 32 kHz
oscillator.
LED DRIVER PINS AND LED SUPPLY VOLTAGE
The LED driver pins (LED1/DNC, LED2, and LED3) have an
absolute maximum voltage rating of 3.6 V. Any voltage exposure
over this rating affects the reliability of the device operation and,
in certain circumstances, causes the device to completely cease
proper operation. The voltage of the LED driver pins must not be
confused with the supply voltages for the LEDs themselves (VLED1
and VLED2). These are the voltages applied to the anodes of the
internal LEDs connected at VLED1.
Output Data Cycle Signal
There are three options available to provide a signal that
indicates when the output data is written to the output data
registers or to the FIFO. Setting Register 0x0B, Bits[12:8] or
Bits[4:0] = 0x0C provides a signal that indicates that a data
value is written for Time Slot A. A setting of 0x0D provides a
signal that indicates that a data value is written for Time Slot B,
and 0x0E provides a signal to indicate that a value is written for
either time slot. The signal asserts at the end of the time slot,
when the output data is already written, and deasserts at the
start of the subsequent sample. This timing signal is especially
useful in situations where the FIFO is being used. For example,
one of the GPIOx pins can be configured to provide an interrupt
after the FIFO reaches the FIFO threshold set in Register 0x06,
Bits[13:8], while the other GPIOx pin can be configured to
provide the output data cycle signal. This signal can be used to
trigger a peripheral device, such as an accelerometer, so that
time aligned signals are provided to the processor.
LED DRIVER OPERATION
The LED drivers for the ADPD188GG are current sinks. Typical
LED driver current vs. LED driver voltage is shown in Figure 9.
Figure 24 shows the basic schematic of how the ADPD188GG
connects to an LED through the LED driver. The Determining
the Average Current section and the Determining CVLED
section define the requirements for the bypass capacitor (CVLED
)
and the supply voltages of the LEDs (VLED).
Rev. B | Page 26 of 61
Data Sheet
ADPD188GG
4.5
4.0
3.5
3.0
2.5
2.0
DETERMINING THE AVERAGE CURRENT
When the ADPD188GG drives an LED, it drives the LED in a
series of short pulses. Figure 29 shows the typical ADPD188GG
configuration of a pulse burst sequence. In this sequence, the
LED pulse width, tLED_PULSE, is 3 µs, and the LED pulse period,
tLED_PERIOD, is 19 µs. The goal of CVLED is to buffer the LED between
individual pulses. In the worst case scenario, where the pulse
train shown in Figure 29 is a continuous sequence of short
pulses, the VLED supply must supply the average current.
Therefore, calculate ILED_AVERAGE as follows:
I
LED_AVERAGE = (tLED_PULSE/tLED_PERIOD) × ILED_PEAK
where:
LED_AVERAGE is the average current needed from the VLED supply. It is
also the VLED supply current rating.
LED_PEAK is the peak current setting of the LED.
(1)
LED DRIVER CURRENT (mA)
I
Figure 30. Typical LED Forward-Bias Voltage Drop as a Function of the
LED Driver Current
I
For the CVLED capacitor to be sized correctly, do not deplete it
during the pulse of the LED to the point where the voltage on
the capacitor is less than the forward-bias on the LED. To calculate
the minimum value for the VLED bypass capacitor, use the
following equation:
For the numbers shown in Figure 29, ILED_AVERAGE = 3/19 ×
ILED_PEAK. For typical LED timing, the average VLED supply
current is 3/19 × 250 mA = 39.4 mA, indicating that the VLED
supply must support a dc current of 40 mA.
19µs
t
LED_PULSE ×ILED _ PEAK
(2)
CVLED
=
VLED _ MIN − (VFB _ LED _ MAX + 0.6)
3µs
where:
LED_PULSE is the LED pulse width.
LED_PEAK is the maximum forward-bias current on the LED used
in operating the device.
t
I
I
LEAD_PEAK
VLED_MIN is the lowest voltage from the VLED supply with no load.
V
FB_LED_MAX is the maximum forward-bias voltage required on
the LED to achieve ILED_PEAK
.
Figure 29. Typical LED Pulse Burst Sequence Configuration
The numerator of the CVLED equation sets up the total discharge
amount in coulombs from the bypass capacitor to satisfy a
single programmed LED pulse of the maximum current. The
denominator represents the difference between the lowest voltage
from the VLED supply and the LED required voltage. The LED
required voltage is the voltage of the anode of the LED such that
the 0.6 V compliance of the LED driver at 200 mA and the
forward-bias voltage of the LED operating at the maximum
current is satisfied. For a typical ADPD188GG example, assume
that the lowest value for the VLED supply is 4.4 V, and that the
peak current is 200 mA for two 525 nm LEDs in parallel. The
minimum value for CVLED is then equal to 4 µF.
DETERMINING CVLED
To determine the CVLED capacitor value, determine the maximum
forward-bias voltage, VFB_LED_MAX, of the LED in operation.
From Figure 30, ILED_PEAK converts to VFB_LED_MAX. For example,
with a 200 mA current, VFB_LED_MAX is 3.65 V. Any series
resistance in the LED path must also be included in this voltage.
When designing the LED path, keep in mind that small
resistances can add up to large voltage drops when a 200 mA
current is driven through the resistor. These resistances can be
unnecessary constraints on the VLED supply.
C
VLED = (3 × 10−6 × 0.20)/(4.4 – (3.65 + 0.6)) = 4.0 µF
(3)
As shown in Equation 3, the minimum supply voltage drops close
to the maximum anode voltage, and the demands on CVLED
become more stringent, forcing the capacitor value higher. It is
important to plug the correct values into these equations. For
example, using an average value for VLED_MIN instead of the
worst-case value for VLED_MIN can cause a problem; therefore,
adding sufficient margin on CVLED is strongly recommended.
Rev. B | Page 27 of 61
ADPD188GG
Data Sheet
tSLOTx (sec) = LEDx_OFFSET + LEDx_PERIOD ×
PULSE_COUNT
where:
NUM_CHANNELS is the number of active channels.
LEDX_PK is the peak LED current, expressed in amps, for the LED
enabled in that particular time slot.
USING EXTERNAL LEDS
(7)
The ADPD188GG LED driver is also connected to an external
package pin so that the driver can drive external LEDs, if desired.
Figure 31 shows a connection diagram that enables driving
external LEDs.
I
V
= 1.8V
DD
SCALE_X is the scale factor for the LED current drive determined
by Bit 13 of the ILED_COARSE register.
C3
0.1µF
V
NC
LED
LEDx_OFFSET is the pulse start time offset expressed in
seconds.
C
VLED
LEDx_PERIOD is the pulse period expressed in seconds.
PULSE_COUNT is the number of pulses.
C2
1µF
ADPD188GG
LED1
VREF
SCL
TO HOST
PROCESSOR
Note that if either Time Slot A or Time Slot B are disabled, IAFE_x
0 for that respective time slot.
=
SDA
GPIOx
LEDx/DNC
Average VLEDA Supply Current
To calculate the average VLEDA supply current, use Equation 8.
LED_AVG_A = SLOTA_LED_WIDTH × ILEDA_PK × DR ×
PULSE_COUNT
where:
I
Figure 31. Using the ADPD188GG LED Drivers to Drive External LEDs
(8)
CALCULATING CURRENT CONSUMPTION
SLOTA_LED_WIDTH is the LED pulse width expressed in
seconds.
The current consumption of the ADPD188GG depends on the
user selected operating configuration, as described in the
following equations.
ILEDA_PK is the peak current, expressed in amps, for the Time Slot A
LED.
Total Power Consumption
Average VLEDB Supply Current
To calculate the total power consumption, use Equation 4.
To calculate the average VLEDB supply current, use Equation 9.
LED_AVG_B = SLOTB_LED_WIDTH × ILEDB_PK × DR ×
PULSE_COUNT
where:
SLOTB_LED_WIDTH is the LED pulse width expressed in
seconds.
Total Power = IVDD_AVERAGE × VDD + ILED_AVERAGE × VLED
where:
VDD_AVERAGE is the average VDD supply current (supplied at
VDD1 and VDD2).
DD is the voltage applied at the VDD1 and VDD2 pins.
LED_AVERAGE is the average LED supply current.
LED is the voltage at the VLEDx pins, respectively.
(4)
I
(9)
I
V
I
V
ILEDB_PK is the peak current, expressed in amps, for the Time Slot B
LED.
Average VDD Supply Current
Optimizing SNR per Watt in a Signal Limited System
To calculate the average VDD supply current, use Equation 5.
In practice, optimizing for peak SNR is not always practical.
One scenario in which the PPG signal has a poor SNR is the
signal limited regime. In this scenario, the LED current reaches
an upper limit before the desired dc return level is achieved.
IVDD_AVG = DR × ((IAFE_A × tSLOTA) + (IAFE_B × tSLOTB) +
QPROC_x) + IVDD_STANDBY
(5)
where:
DR is the data rate in Hz.
VDD_STANDBY = 0.2 µA.
PROC_x is an average charge associated with a processing time,
Tuning in this case starts where the peak SNR tuning stops. The
starting point is nominally a 50k gain, as long as the lowest LED
current setting of 12 mA does not saturate the photodiode and the
50k gain provides enough protection against intense background
light. In these cases, use a 25k gain as the starting point.
I
Q
as follows:
When only Time Slot A is enabled,
Q
PROC_A (C) = 0.35 × 10−6
When only Time Slot B is enabled,
PROC_B (C) = 0.24 × 10−6
When Time Slot A and Time Slot B are enabled,
PROC_AB (C) = 0.40 × 10−6
AFE_x (A) = 3.0 × 10−3 + (1.5 × 10−3 × NUM_CHANNELS) +
(4.6 × 10−3 × ILEDX_PK/ SCALE_X)
(6)
The goal of the tuning process is to bring the dc return signal to a
specific ADC range, such as 50% or 60%. The ADC range choice is
a function of the margin of headroom needed to prevent saturation
as the dc level fluctuates over time. The SNR of the PPG waveform
is always some percentage of the dc level. If the target level cannot
be achieved at the base gain, increase the gain and repeat the
procedure. The tuning system may need to place an upper limit
on the gain to prevent saturation from ambient signals.
Q
Q
I
Rev. B | Page 28 of 61
Data Sheet
ADPD188GG
integrator sequence are subtracted and the sequences with a
normal integrator sequence are added. An example diagram of
the integrator chopping sequence is shown in Figure 32.
Tuning the Pulse Count
After the LED peak current and TIA gain are optimized,
increasing the number of pulses per sample increases the SNR by
the square root of the number of pulses. There are two ways to
increase the pulse count. The pulse count registers (Register 0x31,
Bits[15:8], and Register 0x36, Bits[15:8]) change the number of
pulses per internal sample. Register 0x15, Bits[6:4] and Bits[10:8],
controls the number of internal samples that are averaged together
before the data is sent to the output. Therefore, the number of
pulses per sample is the pulse count register multiplied by the
number of subsequent samples being averaged. In general, the
internal sampling rate increases as the number of internal sample
averages increase to maintain the desired output data rate. The
SNR/watt is most optimal with pulse count values of 16 or less.
Above pulse count values of 16, the square root relationship does
not hold in the pulse count register. However, this relationship
continues to hold when averaged between samples using
Register 0x15.
The result is that any low frequency signal contribution from
the integrator is eliminated, leaving only the integrated signal,
which results in higher SNR, especially at higher numbers of
pulses and at lower TIA gains where the noise contribution of
the integrator becomes more pronounced.
Digital chopping is enabled using the registers and bits detailed
in Table 18. The bit fields define the chopping operation for the
first four pulses. This 4-bit sequence is then repeated for all
subsequent pulses. In Figure 32, a sequence is shown where the
second and fourth pulses are inverted while the first and third
pulses remain in the default polarity (noninverted). This configura-
tion is achieved by setting Register 0x17, Bits[3:0] = 0xA and
Register 0x1D, Bits[3:0] = 0xA for Time Slot A and Time Slot B,
respectively. To complete the operation, the math must be
adjusted using Register 0x58. In this example, set Register 0x58,
Bits[9:8] and Register 0x58, Bits[11:10] to b01 to add the third
pulse and subtract the fourth pulse for Time Slot A and Time
Slot B, respectively. Set Register 0x58, Bits[2:1] and Register
0x58, Bits[6:5] to b01 to add the first pulse and subtract the
second pulse for Time Slot A and Time Slot B, respectively.
This sequence then repeats for every subsequent sequence of
four pulses. An even number of pulses must be used with
integrator chop mode.
Note that increasing LED peak current increases SNR almost
directly proportional to LED power, whereas increasing the
number of pulses by a factor of n results in only a nominal √(n)
increase in SNR.
When using the sample sum/average function (Register 0x15), the
output data rate decreases by the number of summed samples. To
maintain a static output data rate, increase the sample
frequency (Register 0x12) by the same factor as that selected in
Register 0x15. For example, for a 100 Hz output data rate and a
sample sum/average of four samples, set the sample frequency to
400 Hz.
When using integrator chop mode, the ADC offset registers
(Register 0x18 through Register 0x1B for Time Slot A, and
Register 0x1E through Register 0x21 for Time Slot B) must be
set to 0. These settings are required because any digital offsets
at the output of the ADC are automatically eliminated when the
math is adjusted to subtract the inverted integration sequences
while the default integration sequences are added. Integrator
chop mode also eliminates the need to manually null the ADC
offsets at startup in a typical application. Note that the elimination
of the offset using chop mode may clip at least half of the noise
signal when no input signal is present, which makes measuring
the noise floor during characterization of the system difficult.
For this reason, perform noise floor characterization of the system
either with chop mode disabled or with chop mode enabled but
with a minimal signal present at the input that increases the
noise floor enough such that it is no longer clipped.
Improving SNR Using Integrator Chopping
The last stage in the analog front end that is integrated into the
ADPD188GG data path is a charge integrator. The integrator
uses an on and off integration sequence, synchronized to the
emitted light pulse, which acts as an additional high-pass filter
to remove offsets, drifts, and low frequency noise from the
previous stages. However, the integrating amplifier can itself
introduce low frequency signal content at a low level. The
ADPD188GG has an integrator chop mode that enables
additional chopping in the digital domain to remove this signal.
This chopping is achieved by using even numbers of pulses per
sample and inverting the integration sequence for half of those
sequences. In the calculation to combine the digitized result of
each of the pulses of the sample, the sequences with an inverted
Rev. B | Page 29 of 61
ADPD188GG
Data Sheet
PULSE 1
PULSE 2
PULSE 3
PULSE 4
LED
BAND-PASS
FILTER
OUTPUT
INTEGRATOR
SEQUENCE
+
–
–
+
+
–
–
+
ADC
+
–
+
–
Figure 32. Diagram of Integrator Chopping Sequence
Table 18. Register Settings for Integrator Chop Mode
Hex
Addr.
Data
Bit(s)
Bit Name
Description
0x17
0x1D
0x58
[3:0]
INTEG_ORDER_A Integration sequence order for Time Slot A. Each bit corresponds to the polarity of the integration
sequence of a single pulse in a four-pulse sequence. Bit 0 controls the integration sequence of
Pulse 1, Bit 1 controls Pulse 2, Bit 2 controls Pulse 3, and Bit 3 controls Pulse 4. After four pulses, the
sequence repeats.
0: normal integration sequence.
1: reversed integration sequence.
[3:0]
INTEG_ORDER_B Integration sequence order for Time Slot B. Each bit corresponds to the polarity of the integration
sequence of a single pulse in a four-pulse sequence. Bit 0 controls the integration sequence of
Pulse 1, Bit 1 controls Pulse 2, Bit 2 controls Pulse 3, and Bit 3 controls Pulse 4. After four pulses, the
sequence repeats.
0: normal integration sequence.
1: reversed integration sequence
[11:10]
FLT_MATH34_B
FLT_MATH34_A
FLT_MATH12_B
FLT_MATH12_A
Time Slot B control for adding and subtracting Sample 3 and Sample 4 in a four-pulse sequence (or
any multiple of four pulses, for example, Sample 15 and Sample 16 in a 16-pulse sequence).
00: add third and fourth.
01: add third and subtract fourth.
10: subtract third and add fourth.
11: subtract third and fourth.
[9:8]
[6:5]
[2:1]
Time Slot A control for adding and subtracting Sample 3 and Sample 4 in a four-pulse sequence
(or any multiple of four pulses, for example, Sample 15 and Sample 16 in a 16-pulse sequence).
00: add third and fourth.
01: add third and subtract fourth.
10: subtract third and add fourth.
11: subtract third and fourth.
Time Slot B control for adding and subtracting Sample 1 and Sample 2 in a four-pulse sequence (or
any multiple of four pulses, for example, Sample 13 and Sample 14 in a 16-pulse sequence).
00: add first and second.
01: add first and subtract second.
10: subtract first and add second.
11: subtract first and second.
Time Slot A control for adding and subtracting Sample 1 and Sample 2 in a four-pulse sequence
(or any multiple of four pulses, for example, Sample 13 and Sample 14 in a 16-pulse sequence).
00: add first and second.
01: add first and subtract second.
10: subtract first and add second.
11: subtract first and second.
Rev. B | Page 30 of 61
Data Sheet
ADPD188GG
from the photodiode increases, the ADC output decreases
toward 0.
MECHANICAL CONSIDERATIONS FOR COVERING
THE ADPD188GG
When configuring the integrator as a buffer, there is the option
of either using a gain of 1 or a gain of 0.7. Using the gain of 0.7
increases the usable dynamic range at the input to the TIA. The
buffer gain is set using Register 0x42, Bit 9 for Time Slot A and
Register 0x44, Bit 9 for Time Slot B. Setting this bit to 0 (default)
sets a gain of 1. Setting this bit to 1 configures the buffer with a
gain of 0.7.
In some applications, it may be necessary to cover the
ADPD188GG to protect it from moisture. The ADPD188GG is
designed with this requirement in mind. The unique cross section
of the device, as shown in Figure 13, prevents light from going
directly from the LED to the detector even with a reasonably thick
window. It is recommended that the window thickness be
<0.7 mm and the air gap between the module and the window
be kept to <0.5 mm for optimal operation.
The ADC output (ADCOUT) is calculated as follows:
TIA ADC MODE
ADCOUT = 8192 (((2 × TIA_VREF – 2 × i × RF − 1.8 V)/
146 µV/LSB) × SLOTx_BUF_GAIN)
(11)
Figure 33 shows a way to put the ADPD188GG into a mode
that effectively runs the TIA directly into the ADC without
using the analog band-pass filter (BPF) and integrator. This
mode is referred to as TIA ADC mode. There are two basic
applications of TIA ADC mode. In normal operation, all of the
background light is blocked from the signal chain, and therefore,
cannot be measured. TIA ADC mode can measure the amount
of background and ambient light. This mode can also measure
other dc input currents, such as leakage resistance.
where:
TIA_VREF is the bias voltage for the TIA (the default value is
1.265 V).
i is the input current to the TIA.
RF is the TIA feedback resistor.
SLOTx_BUF_GAIN is either 0.7 or 1, based on the setting of
Register 0x42, Bit 9 and Register 0x44, Bit 9.
Equation 11 is an approximation and does not account for
internal offsets and gain errors. The calculation also assumes
that the ADC offset registers are set to 0.
V
ADPD188GG
IN
OPTIONAL
BUFFER
R
S
R_IN
One time slot can be used in TIA ADC mode at the same time
the other time slot is being used in normal pulsed mode. This
capability is useful for monitoring ambient and pulsed signals
at the same time. The ambient signal is monitored during the
time slot configured for TIA ADC mode, while the pulsed
signal, with the ambient signal rejected, is monitored in the
time slot configured for normal mode.
TIA
ADC
TIA_VREF
Figure 33. TIA ADC Mode Block Diagram
When the devices are in TIA ADC mode, the BPF and the
integrator stage are bypassed. This bypass effectively wires the
TIA directly into the ADC. At the set sampling frequency, the
ADC samples Channel 1 through Channel 4 in sequential
order, and each sample is taken at 1 µs intervals.
Protecting Against TIA Saturation in Normal Operation
One of the reasons to monitor TIA ADC mode is to protect
against environments that may cause saturation. One concern
when operating in high light conditions, especially with larger
photodiodes, is that the TIA stage may become saturated while
the ADPD188GG continue to communicate data. The resulting
saturation is not typical. The TIA, based on its settings, can only
handle a certain level of photodiode current. Based on the way
the ADPD188GG is configured, if there is a current level from the
photodiode that is larger than the TIA can handle, the TIA output
during the LED pulse effectively extends the current pulse,
making it wider. The AFE timing is then violated because the
positive portion of the band-pass filter output extends into the
negative section of the integration window. Thus, the
There are two modes of operation in TIA ADC mode. One
mode is an inverting configuration where TIA ADC mode
directly drives the ADC. This mode is enabled by setting
Register 0x43 (Time Slot A) and/or Register 0x45 (Time Slot B)
to 0xB065, which bypasses the BPF and the integrator. With the
ADC offset register(s) for the desired channel set to 0 and the
TIA_VREF set to 1.265 V, the output of the ADC is at ~13,000
codes for a single pulse and a zero input current condition. As
the input current from the photodiode increases, the ADC
output decreases toward 0.
The recommended TIA ADC mode is one in which the BPF is
bypassed and the integrator is configured as a buffer. This
mode is enabled by writing 0xAE65 to Register 0x43 (Time Slot
A) and/or Register 0x45 (Time Slot B) to bypass the BPF.
Additionally, to configure the integrator as a buffer, set Bit 7 of
Register 0x42 (Time Slot A) and/or Register 0x44 (Time Slot B)
to 1, and set Bit 7 of Register 0x58 to 1. With the ADC offset
register(s) for the desired channel set to 0 and TIA_VREF set to
1.265 V, the output of the ADC is at ~13,000 codes for a single
pulse and a zero input current condition. As the input current
photosignal is subtracted from itself, causing the output signal
to decrease when the effective light signal increases.
To measure the response from the TIA and verify that this stage
is not saturating, place the device in TIA ADC mode and slightly
modify the timing. Specifically, sweep SLOTx_AFE_OFFSET until
two or three of the four channels reach a minimum value (note
that TIA is in an inverting configuration). All four channels do not
reach this minimum value because, typically, 3 µs LED pulse
widths are used and the ADC samples the four channels
Rev. B | Page 31 of 61
ADPD188GG
Data Sheet
sequentially at 1 µs intervals. This procedure aligns the ADC
sampling time with the LED pulse to measure the total amount of
light falling on the photodetector (for example, background light +
LED pulse).
that can occur. These resistances can force the TIA into saturation
prematurely. This premature saturation, in turn, takes away
dynamic range from the device in operation and adds a Johnson
noise component to the input. To measure these resistances, place
the device in TIA ADC mode in the dark and start by measuring
the TIA ADC offset level with the photodiode inputs disconnected
(Register 0x14, Bits[11:8] = 0 or Register 0x14, Bits[7:4] = 0).
From this, subtract the value of TIA ADC mode with the
darkened photodiode connected and convert the difference
into a current. If the value is positive, and the ADC signal
decreased, the resistance is to a voltage higher than 1.3 V, such
as VDD. Current entering the TIA causes the output to drop. If
the output difference is negative due to an increase of codes at
the ADC, current is being pulled out of the TIA and there is a
shunt resistance to a lower potential than 1.3 V, such as ground.
To ensure that the TIA does not saturate, a safe operating
region is typically at ¾ full scale and lower. Use Table 19 to
determine how the output codes map to ADC levels on a per
channel per pulse basis. These codes are not the same as in
normal mode because the band-pass filter and integrator are
not unity-gain elements.
Measuring PCB Parasitic Input Resistance
During the process of mounting the ADPD188GG, undesired
resistance can develop on the inputs through assembly errors or
debris on the PCB. These resistances can form between the anode
and cathode, or between the anode and some other supply or
ground. In normal operation, the ambient rejection feature of the
ADPD188GG masks the primary effects of these resistances,
making it very difficult to detect them. However, even at 1 MΩ to
10 MΩ, such resistance can impact performance significantly
through added noise or decreased dynamic range. TIA ADC
mode can be used to screen for these assembly issues.
Using the EXT_IN 1 and EXT_IN 2 Inputs with a Voltage
Source
The ADPD188GG can be used for voltage inputs. Voltage
inputs can be measured in normal mode or in TIA ADC mode.
If these inputs are not a result of stimulation from the LED
driver, TIA ADC mode is preferred. To understand the
conversion gain from a voltage through a series resistor, RS, the
current can be determined by following the schematic in Figure 34.
Measuring Shunt Resistance on the Photodiode
A shunt resistor across the photodiode/EXT_INx does not
generally affect the output level of the device in operation because
the effective impedance of the TIA is very low, especially if the
photodiode is held to 0 V in operation. However, such resistance
can add noise to the system, degrading performance. The best way
to detect photodiode leakage, also called photodiode shunt
resistance, is to place the device in TIA ADC mode in the dark
and vary the operation mode cathode voltage. Setting the cathode
to 1.3 V places 0 V across the photodiode because the anode is
always at 1.3 V while in operation. Setting the cathode to 1.8 V
places 0.5 V across the photodiode. Using the register settings in
Table 1 to control the cathode voltage, measure the TIA ADC
value at both voltages. Next, divide the voltage difference of
0.5 V by the difference of the ADC result after converting it to a
current. This result is the approximate shunt resistance. Values
greater than 10 MΩ may be difficult to measure, but this method is
useful in identifying gross failures.
V
IN
ADPD188GG
OPTIONAL
BUFFER
R
S
R_IN
EXT_INx
TIA
ADC
TIA_VREF
Figure 34. ADPD188GG Used for Voltage Inputs
Input Current = (VIN − TIA_VREF)/(RS + R_IN)
Values for R_IN are listed in Table 2. R_IN is not needed for
photodiode or other current inputs because the current of these
inputs are not a function of the input resistance. Conversion from
input current in amps to ADC codes (LSBs) follows Table 19 in
TIA ADC mode. Current conversion in normal mode is listed
in Table 2. The offset level shown in Table 19 represents the
expected code value with zero current input. The conversion
gain in nA/LSB can be added onto this for nonzero input currents.
Measuring TIA Input Shunt Resistance
A resistance to develop between the TIA input and another
supply or ground on the PCB is an example of another problem
Table 19. Analog Specifications for TIA ADC Mode and Digital Integrate Mode
Parameter
Test Conditions/Comments
Typ
Unit
TIA ADC Offset Level
Floating input (Input current = 0A); Register 0x43 and Register 0x45 = 0xAE65; Register 0x42
and Register 0x44, Bit 7 = 1, Register 0x58, Bit 7 = 1
TIA_VREF = Register 0x42 and Register 0x44, Bits[5:4] = 0 (1.14 V)
TIA_VREF = Register 0x42 and Register 0x44, Bits[5:4] = 1 (1.01 V)
TIA_VREF = Register 0x42 and Register 0x44, Bits[5:4] = 2 (0.89 V)
TIA_VREF = Register 0x42 and Register 0x44, Bits[5:4] = 3 (1.27 V); recommended for PD inputs
11400
9700
8100
LSB
LSB
LSB
LSB
13200
Rev. B | Page 32 of 61
Data Sheet
ADPD188GG
Parameter
Test Conditions/Comments
Typ
Unit
TIA ADC Saturation
Levels1
Values expressed per channel, per sample; buffer gain = 1
25 kΩ
50 kΩ
100 kΩ
38.32
19.16
9.58
μA
μA
μA
μA
200 kΩ
4.79
TIA ADC Resolution
Values expressed per channel, per sample; buffer gain = 1
25 kΩ
50 kΩ
100 kΩ
200 kΩ
2.92
1.5
0.73
0.37
nA/LSB
nA/LSB
nA/LSB
nA/LSB
1 TIA linear dynamic range is 85% of listed saturation levels
Table 20. Configuration Registers to Switch Between Normal Sample Mode and TIA ADC Mode
Data
Address Bits
Normal
Mode Value
TIA ADC
Mode Value
Bit Name
Description
0x42
[15:10] SLOTA_AFE_MODE
0x07
Not applicable In normal mode, this setting configures the integrator
block for optimal operation. This setting is not important
for TIA ADC mode.
[9]
[7]
SLOTA_BUF_GAIN
0x0
0x0
0: buffer gain = 1.0.
1: buffer gain = 0.7.
SLOTA_INT_AS_BUF 0x0
0x1
0: normal integrator configuration.
1: convert integrator to buffer amplifier in TIA ADC mode
(required for 0x43 = 0xAE65).
0x43
0x44
[15:0]
[15:10
SLOTA_AFE_CFG
0xADA5
0xAE65
Time Slot A AFE connection.
0xAE65: bypasses the band-pass filter.
0xB065: can also be used in TIA ADC mode. This setting
bypasses the BPF and the integrator.
SLOTB_AFE_MODE
SLOTB_BUF_GAIN
0x07
0x0
Not applicable In normal mode, this setting configures the integrator
block for optimal operation. This setting is not important
for TIA ADC mode.
[9]
[7]
0x0
0: buffer gain = 1.0.
1: buffer gain = 0.7.
SLOTB_INT_AS_BUF 0x0
0x1
0: normal integrator configuration.
1: convert integrator to buffer amplifier (required for 0x45 =
0xAE65).
0x45
0x58
[15:0]
[7]
SLOTB_AFE_CFG
ENA_INT_AS_BUF
0xADA5
0xAE65
0x1
Time Slot B AFE connection.
0xAE65: bypasses the band-pass filter.
0xB065: can also be used in TIA ADC mode. This setting
bypasses the band-pass filter (BPF) and the integrator.
0x0
Enables the ability to configure the integrator as a buffer in
TIA ADC mode
signal path, including the band-pass filter and integrator, to be
used to measure ambient light as well as other types of measure-
ments with different types of sensors (for example, ECG).
PULSE CONNECT MODE
In pulse connect mode, the photodiode input connections are
pulsed according to the timing set up in the LED pulse timing
registers. In this mode, if the LED pulse timing is set up to provide
a 2 µs LED pulse, the device pulses the connection to the photo-
diode input for 2 µs instead of providing a 2 µs LED pulse. This
mode is an alternate to TIA ADC mode, allowing the entire
To enable pulse connect mode, the device is configured identically
to normal mode, except that Register 0x14, Bits[3:2] = 0 for
Time Slot B, and Register 0x14, Bits[1:0] = 0 for Time Slot A.
Rev. B | Page 33 of 61
ADPD188GG
Data Sheet
input bias voltage must be set to the 0.90 V setting using Bits[5:4]
of Register 0x42 if the ECG signal is on Time Slot A, or
Register 0x44 on Time Slot B. The TIA gain setting can be set to
optimize the dynamic range of the signal path. The channel
used to process the PPG signal is configured in its normal
operating mode. Figure 35 shows a plot of a synchronized ECG
and PPG measurement using the AD8233 with the
ADPD188GG.
SYNCHRONOUS ECG AND PPG MEASUREMENT
USING TIA ADC MODE
In wearable devices developed for monitoring the health care of
patients, it is often necessary to have synchronized measurements
of biomedical signals. For example, a synchronous measurement
of patient ECG and PPG can be used to determine the pulse
wave transit time (PWTT), which can then be used to estimate
blood pressure.
10000
The circuit shown in Figure 36 shows a synchronous ECG and
PPG measurement using the AD8233 and the ADPD188GG.
The AD8233 implements a two-pole, high-pass filter with a
cutoff frequency at 0.3 Hz, and a two-pole, low-pass filter with
a cutoff frequency of 37 Hz. The output of the AD8233 is fed to
the EXT_IN1 current input of the ADPD188GG through a
200 kΩ resistor to convert the voltage output of the AD8233
into a current.
52000
9500
9000
51500
PPG
8500
8000
51000
ECG
7500
7000
50500
The ADPD188GG is configured to alternately measure the
photodiode signal and the ECG signal from the AD8233 on
consecutive time slots to provide fully synchronized PPG and
ECG measurements. Data can be read out of the on-chip FIFO
or straight from data registers. The ADPD188GG channel used
to process the ECG signal is set up in TIA ADC mode and the
6500
50000
6000
SAMPLE RATE (ms)
Figure 35. Plot of Synchronized ECG and PPG Waveforms
1.8V
4.7µF
10MΩ
HPDRIVE
+IN
HPSENSE
IAOUT
10MΩ
10MΩ
1.8V
180kΩ
180kΩ
LA
RA
–IN
REFIN
10MΩ
0.1µF
4.7µF
+V
S
RLDFB
RLD
10MΩ
0.1µF
1nF
360kΩ
RL
GND
AD8233
1.8V
SW
FR
AC/DC
SDN
1MΩ
1MΩ
OPAMP+
REFOUT
OPAMP–
OUT
100kΩ 6.8nF
250kΩ
TO DIGITAL
INTERFACE
RLD SDN
LOD
2.7nF
1MΩ
1.8V
ADPD188GG
200kΩ
5V
EXT_IN1
VLED1
VDD1
VDD2
0.1µF
0.1µF
AGND
DGND
LGND
CVLED
1.8V
10kΩ 10kΩ
LED1/DNC
VREF
SCL
SDA
TO DIGITAL
INTERFACE
1µF
GPIO0
GPIO1
Figure 36. Synchronized PPG and ECG Measurement Using the ADPD188GG with the AD8233
Rev. B | Page 34 of 61
Data Sheet
ADPD188GG
Float Mode Measurement Cycle
FLOAT MODE
Figure 37 shows the float mode measurement cycle timing
diagram, and the following details the points shown:
The ADPD188GG has a unique operating mode, float mode,
that allows excellent SNR at low power in low light situations.
In float mode, the photodiode is first preconditioned to a
known state and then the photodiode anode is disconnected
from the receive path of the ADPD188GG for a preset amount
of float time. During the float time, light falls on the
photodiode, either from ambient light, pulsed LED light, or a
combination of the two depending on the operating mode.
Charge from the sensor is stored directly on the capacitance of
the sensor. At the end of the float time, the photodiode switches
back into the receive path of the ADPD188GG and an inrush of
the accumulated charge occurs, which is subsequently integrated
by the integrator of the ADPD188GG, allowing the maximum
amount of charge to be processed per pulse with the minimum
amount of noise added by the signal path. The charge is
integrated externally on the capacitance of the photodiode for
as long as it takes to acquire maximum charge, independent of
the amplifiers of the signal path, which adds noise to the signal.
•
•
•
The precondition period is shown prior to Point A. The
photodiode is connected to the TIA, and the photocurrent
flows into the TIA. The photodiode anode is held at 0.9 V
(Register 0x42 and Register 0x44, Bits[5:4] = 0x2 sets TIA_
VREF = 0.9 V). The photodiode is reverse biased to a
maximum reverse bias of ~250 mV by setting Register 0x54,
Bit 7 = 1 and Register 0x54, Bits[9:8] = 0x2 (for Time Slot
A). At this point, the output of the TIA (TIA_OUT) =
TIA_VREF − (IPD × RF), where IPD is the current flowing
from the PD into the ADPD1080/ADPD1081 input, and
the integrator is off.
At Point A, the photodiode is disconnected from the
receive path. Light continues to fall on the photodiode
producing a charge that accumulates directly on the
photodiode capacitance. As the charge accumulates, the
voltage at the floating photo-diode anode rises. The TIA is
disconnected from the input to the ADPD188GG so that
no current flows through the TIA, and the TIA output is at
TIA_VREF. Just prior to Point B, the integrator resets to 0.
In the Float Mode for Synchronous LED Measurements
section, the LED pulses during the time period between
Point A and Point D. Float times of <4 µs are not allowed.
At Point B, the integrator begins its positive integration
phase. Small dc offsets between the TIA output and the
integrator reference causes the integrator output to ramp
up for positive offsets or ramp down for negative offsets.
The photodiode continues to accumulate charge during
this period.
Amplifier and ADC noise values are constant for a given
measurement. For optimal SNR, it is desirable to have a greater
amount of signal (charge) per measurement. In normal mode,
because the pulse time is fixed, the charge per measurement can
be increased only by increasing the LED drive current. For high
light conditions, this is sufficient. In low light conditions,
however, there is a limit to the available current. In addition,
high current pulses can cause ground noise in some systems.
Green LEDs have lower efficiency at high currents, and many
battery designs do not deliver high current pulses as efficiently.
Float mode allows the user the flexibility to increase the
amount of charge per measurement by either increasing the
LED drive current or by increasing the float time. This
•
•
At Point C, the integrator begins its negative integration
phase. This reversal in polarity begins to cancel any signal
caused by offsets. This offset cancellation continues through
Point F, where all offsets are cancelled completely.
At Point D, the photodiode switches into the receive path
where all the charge that has accumulated on the photodiode
capacitance during the float time is dumped into the TIA. The
typical charge dump time is less than 2 µs. As the current
flows through the TIA, the output of the TIA responds
with a large negative signal. Because the integrator is in the
negative integration phase at this point, the output of the
integrator rises as the input current to the device integrates
back to total charge. Between Point D and Point E, any
light incident on the photodiode produces additional
photocurrent, which is immediately integrated by the
integrator as charge.
flexibility is especially useful in low current transfer ratio (CTR)
conditions, for example, 10 nA/mA, where normal mode
requires multiple pulses to achieve an acceptable level of SNR.
In float mode, the signal path bypasses the BPF and uses only
the TIA and integrator. In normal mode, the shape of the pulse
is known (typically either 2 µs or 3 µs) and is consistent across
devices and conditions. The shape of the signal coming through
the BPF is also predictable, which allows a user to align the
integrator timing with the zero crossing of the filtered signal. In
float mode, the shape of the signal produced by the charge
dump can differ across devices and conditions. A filtered signal
cannot be reliably aligned; therefore, the BPF cannot be used.
In float mode, the entire charge dump is integrated in the
negative cycle of the integrator and the positive cycle cancels
any offsets.
•
•
At Point E, the TIA disconnects from the receive path and
the TIA output returns to TIA_VREF. Between Point E
and Point F, the integrator completes the negative
integration phase and cancellation of the offsets.
At Point F, the integrator output is held until sampled by the
ADC.
Rev. B | Page 35 of 61
ADPD188GG
Data Sheet
25.0µs
30.0µs
35.0µs
A
D
E
CONNECT
FLOAT
F
C
B
+ PHASE
PHASE
INTEGRATOR
CHARGE ON PD
TIA OUTPUT
INTEGRATOR
RESPONSE
DON’T CARE
INTEGRATOR
RESET
ADC READ
Figure 37. Float Mode Measurement Cycle Timing Diagram
Float Mode Limitations
V is the amount of voltage change across the photodiode before
the photodiode becomes nonlinear.
When using float mode, the limitations of the mode must be
well understood. For example, there is a finite amount of
charge that can accumulate on the capacitance of the
For a typical discrete optical design using a 7 mm2 photodiode
with 70 pF capacitance and 450 mV of headroom, the maximum
amount of charge that can be stored on the photodiode
capacitance is 31.5 pC.
photodiode, and there is also a maximum amount of charge that
can be integrated by the integrator. Based on an initial reverse
bias of 250 mV on the photodiode and assuming that the
photodiode begins to become nonlinear at ~200 mV of forward
bias, there is ~450 mV of headroom for the anode voltage to
increase from its starting point at the beginning of the float time
before the charge ceases to accumulate in a linear fashion. It is
desirable to operate only in the linear region of the photodiode
(see Figure 38). To verify that float mode is operating in the
linear region of the diode, the user can perform a simple check.
Record data at a desired float time, and then record data at half
the float time. It is recommended that the ratio of the two received
signals be 2:1. If this ratio does not hold true, the diode is likely
beginning to forward bias at the longer float time and becomes
nonlinear.
In addition, consider the maximum amount of charge the
integrator of the ADPD188GG can integrate. The integrator
can integrate up to 7.6 pC. When this charge is referred back to
the input, consider the TIA gain. When the TIA gain is at
200 kΩ, the input referred charge is at a 1:1 ratio to the
integrated charge on the integrator. For 100 kΩ gain, it is 2:1;
for 50 kΩ gain, it is 4:1; and for 25 kΩ gain, it is 8:1. For the
previous example using a photodiode with 70 pF capacitance,
use 50 kΩ TIA gain and set the float timing such that, for a
single pulse, the output of the ADC is at 70% of full scale, which
is a typical operating condition. Under these operating conditions,
5.3 pC integrates per pulse by the integrator for 21.2 pC of
charge accumulated on the photodiode capacitance. For small
CTR, however, it can take a long time to accumulate 21.2 pC of
charge on the photodiode capacitance, in which case, use higher
TIA gains according to how much charge can be accumulated in a
given amount of time. Ultimately, float times are determined by
the type of measurement being made (ambient or pulsed LED),
the photodiode capacitance, and the CTR of the system.
PD BEGINS TO
FORWARD BIAS
RECOMMENDED
FLOAT MODE
OPERATING REGION
Float Mode for Ambient Light Measurements
Float mode is used for ambient light measurements where the
background light is sufficiently small. Use TIA ADC mode for
ambient light measurements of higher intensities. Small
amounts of light can be measured with adequate float times,
allowing the incoming charge to accumulate to levels large
enough to be measured above the noise floor of the system. The
source of this light can be any combination of synchronous
light (for example, from a pulsed LED) and asynchronous light
(that is, background). If there is no system generated light
source, the measurement is simply a measure of the
background light.
FLOAT TIME (µs)
Figure 38. Transfer Function of Integrated Charge on the Photodiode vs.
Float Time
The maximum amount of charge that can be stored on the
photodiode capacitance and remain in the linear operating
region of the sensor can be estimated by
Q = CV
where:
Q is the integrated charge.
C is the capacitance of the photodiode.
Rev. B | Page 36 of 61
Data Sheet
ADPD188GG
Use a two pulse differential measurement technique to cancel
out electrical drifts and offsets. Take two measurements, each
of a different float time. The first float time is considerably
shorter than the second pulse. After the two measurements are
taken, Measurement 1 is subtracted from Measurement 2,
which effectively cancels out any offset and drift common to
both measurements. What is left is an ambient light
measurement based on an amount of charge that is integrated
over a time that is the difference of the first and second float
times. For example, if Float Time 1 is 6 µs and Float Time 2 is
26 µs, the ambient light measurement is based on 20 µs of
charge integrated on the photodiode capacitance with any
offset and drift removed. In float mode for ambient light, the
number of pulses must be set to two to cancel drifts and offsets
because only the first pulse can be short. More than two pulses
can be used; however, pulses two through n are always the same
length. If drift cancellation is not required, any number of
pulses can be used and added together. Figure 39 shows an
example of float ambient mode timing, and Table 21 details the
relevant registers that must be configured.
0x59[12:8]/0x5E[12:8]
0x30[12:8]/0x35[12:8]
PRECONDITION TIME
(FLT_PRECON_x)
CHARGE DUMP TIME
(SLOTx_LED_WIDTH)
FLOAT 1 TIME
CONNECT/FLOAT
0x30[7:0]/0x35[7:0]
0x31[7:0]/0x36[7:0]
TIMETO FIRST CHARGE DUMP
FLOAT 2 TIME (SLOTx_PERIOD)
(SLOTx_LED OFFSET)
INTEGRATOR SEQUENCE
0x39[15:11]/0x3B[15:11]
INTEGRATION TIME (SLOTx_AFE_WIDTH)
ACCUMULATED
CHARGE ON PD
Figure 39. Example of Float Ambient Mode Timing
Table 21. Float Ambient Mode Registers
Register
Group
Register Name
Time Slot A
Time Slot B
Float Mode Description
Float Mode
Operation
SLOTx_LED_SEL
0x14, Bits[1:0]
0x14, Bits[3:2]
Set to 0 to enable float mode.
FLT_EN_x
0x5E, Bits[14:13] 0x59, Bits[14:13] Set to 3 to enable float between connect pulses.
FLT_MATH12_x
SLOTx_AFE_CFG
SLOTx_TIA_VREF
SLOTx_V_CATHODE
0x58, Bits[2:1]
0x43, Bits[15:0]
0x42, Bits[5:4]
0x54, Bits[9:8]
0x58, Bits[6:5]
0x45, Bits[15:0]
0x44, Bits[5:4]
Set to 2 to subtract first pulse and add second pulse.
Set to 0xAE65 for TIA and integrator, bypass BPF.
Set to 2 for TIA_VREF = 0.9 V.
0x54, Bits[11:10] Set to 2 for 250 mV reverse bias on the photodiode at
the precondition.
REG54_VCAT_ENABLE 0x54, Bit 7
0x54, Bit 7
Set to 1 to override Register 0x3C cathode voltage
settings.
Float Mode
Timing
FLT_PRECON_x
0x5E, Bits[12:8]
0x59, Bits[12:8]
Precondition time (to start of Float 1 time).
SLOTx_PERIOD
SLOTx_PERIOD
SLOTx_LED_WIDTH
0x31, Bits[7:0]
0x37, Bits[1:0]
0x30, Bits[12:8]
0x36, Bits[7:0]
0x37, Bits[9:8]
0x35, Bits[12:8]
8 LSBs of float period in µs; Float 2 time = SLOTx_PERIOD
2 MSBs of float period.
Connect time in µs; this is the amount of time given to
dump the accumulated charge from the photodiode
capacitance; typically, this is set to 2 µs.
SLOTx_LED_OFFSET
0x30, Bits[7:0]
0x35, Bits[7:0]
Time to first charge dump; Float 1 time =
(SLOTx_LED_OFFSET + SLOTx_LED_WIDTH) −
FLT_PRECONx.
SLOTx_AFE_WIDTH
SLOTx_AFE_OFFSET
0x39, Bits[15:11] 0x3B, Bits[15:11]
Integration time in µs; set to FLT_CONNx + 1.
Integrator start time in 31.25 ns increments; set to
(SLOTx_LED_OFFSETx − SLOTx_AFE_WIDTH − 9.25) µs.
0x39, Bits[10:0]
0x3B, Bits[10:0]
SLOTx_PULSES
0x31, Bits[15:8]
0x36, Bits[15:8]
Number of pulses; set to 2 for float ambient mode.
Rev. B | Page 37 of 61
ADPD188GG
Data Sheet
The return from the LED + ambient + offset is present in one of
the pulses. In the other, only the ambient light and offset is
present. A subtraction of the two pulses is made that eliminates
ambient light as well as any offset and drift. It is recommended
to use groups of four pulses for measurement where the LED is
flashed on Pulse 2 and Pulse 3. The accumulator adds Pulse 2
and Pulse 3 and then subtract Pulse 1 and Pulse 4. To gain
additional SNR, use multiple groups of four pulses.
Float Mode for Synchronous LED Measurements
In float LED mode, photocurrent is generated from ambient
light and pulsed LED light during the float time. Float LED
mode is desirable in low signal conditions where the CTR is
<10 nA/mA. In addition, float mode is a good option in
situations where the user wants to limit the LED drive current
of the green LEDs in a heart rate measurement to keep the
forward voltage drop of the green LED to a level that allows the
elimination of a boost converter for the LED supply. For
example, the LED current can be limited to 10 mA to ensure
that the LED voltage drop is ~3 V so that it can operate directly
from the battery without the need of a boost converter. Float
mode accumulates the received charge during longer LED
pulses without adding noise from the signal path, effectively
yielding the highest SNR and/or photon attainable.
The settings of FLT_LED_FIRE_x, Register 0x5A, Bits[15:8]
determine if the LED fires in which pulse position. Which pulse
positions are added or subtracted is configured in the FLT_
MATH12x and FLT_MATH34x bits of Register 0x58. These
sequences are repeated in groups of four pulses. The value
written to the FIFO or data registers is dependent on the total
number of pulses per sample period. For example, if the device
is setup for 32 pulses, the 4 pulse sequence, as defined in FLT_
LED_FIRE_x and FLT_MATHxxx, repeats eight times and a
single register or FIFO write of the final value based on 32 pulses
executes. Table 22 details the relevant registers for float LED mode.
As with float ambient mode, multiple pulses cancel electrical
offsets and drifts; however, in float LED mode, the ambient
light must also be cancelled because only the reflected return
from the LED pulses is desired. To achieve this, use an even
number of equal length pulses. For every pair of pulses, the
LED flashes in one of the pulses and does not flash in the other.
Table 22. Float LED Mode Registers
Register Address
Time Slot A Time Slot B
0x14, Bits[1:0] 0x14, Bits[3:2]
0x5E, Bits[14:13] 0x59, Bits[14:13] Set to 3 to enable float between connect pulses.
Group
Register Name
SLOTx_LED_SEL
FLT_EN_x
Float Mode Description
Float Mode
Operation
Set to 0 to enable float mode.
FLT_MATH12_x
FLT_MATH34_x
SLOTx_AFE_CFG
SLOTx_TIA_VREF
SLOTx_V_CATHODE
0x58, Bits[2:1]
0x58, Bits[9:8]
0x43, Bits[15:0]
0x42, Bits[5:4]
0x54, Bits[9:8]
0x58, Bits[6:5]
Set to 2 to subtract first pulse and add second pulse.
0x58, Bits[11:10] Set to 1 to add third pulse and subtract fourth pulse.
0x45, Bits[15:0]
0x44, Bits[5:4]
Set to 0xAE65 for TIA + integrator, bypass BPF.
Set to 2 for TIA_VREF = 0.9 V.
0x54, Bits[11:10] Set to 2 for 250 mV reverse bias on the photodiode at the
precondition.
REG54_VCAT_ENABLE
FLT_LED_SELECT_x
0x54, Bit 7
0x54, Bit 7
Set to 1 to override Register 0x3C cathode voltage settings.
0x3E, Bits[15:14] 0x3F[15:14]
LED selection for float LED mode.
00 = no LED.
01 = LED1.
10 = LED2.
11 = LED3.
Float Mode
Timing
FLT_PRECON_x
SLOTx_PERIOD
0x5E, Bits[12:8]
0x31, Bits[7:0]
0x59, Bits[12:8]
0x36, Bits[7:0]
Precondition time (to start of float 1 time).
8 LSBs of float period in μs. Float 2 time = SLOTx_PERIOD.
Float 2 time is valid for every pulse subsequent to the first
pulse. Float 1 time must be set equal to Float 2 time in
float LED mode.
SLOTx_PERIOD
0x37, Bits[1:0]
0x30, Bits[12:8]
0x37, Bits[9:8]
0x35, Bits[12:8]
2 MSBs of float period.
SLOTx_LED_WIDTH
Connect time in μs, which is the amount of time given to
dump the accumulated charge from the photodiode
capacitance. Typically, it is set to 2 μs.
SLOTx_LED_OFFSET
0x30, Bits[7:0]
0x35, Bits[7:0]
Time to first charge dump. Float 1 time =
(SLOTx_LED_OFFSET + SLOTx_LED_WIDTH) –
FLT_PRECONx. Float 1 time must be equal to Float 2 time
for float LED mode.
Rev. B | Page 38 of 61
Data Sheet
ADPD188GG
Register Address
Time Slot A Time Slot B
0x39,Bits[15:11] 0x3B, Bits[15:11]
Group
Register Name
Float Mode Description
SLOTx_AFE_WIDTH
SLOTx_AFE_OFFSET
Integration time in μs. set to FLT_CONN + 1.
Integrator start time in 31.25 ns increments. Set to
(SLOTx_LED_OFFSET – SLOTx_AFE_WIDTH − 9.25) μs.
0x39, Bits[10:0]
0x3B, Bits[10:0]
SLOTx_PULSES
0x31, Bits[15:8]
0x36, Bits[15:8]
Number of pulses; must be set in multiples of 2,
minimum 2.
FLT_LED_WIDTH_x
FLT_LED_OFFSET_x
FLT_LED_FIRE_x
0x3E, Bits[12:8]
0x3E, Bits[7:0]
0x5A, Bits[11:8]
0x3F, Bits[12:8]
0x3F, Bits[7:0]
0x5A, Bits[15:12]
LED pulse width for float LED mode in μs.
Time of first LED pulse in float LED mode.
In any given sequence of four pulses, fire the LED in the
selected position. Selections are active low (that is, fire LED
if 0). For example, in a sequence of four pulses on Time Slot B,
Register 0x5A, Bit 12 is the first pulse, and Register 0x5A,
Bit 15 is the fourth pulse. For a sequence of four pulses, fire
the LED in the second and third pulses by writing 0x9 to
Register 0x5A, Bits[15:12].
A timing diagram for a four pulse float LED sequence for
Time Slot B is shown in Figure 40. In this example, the device is
set up for LED pulses of 12 μs that fall within a float period of
16 μs, 2 μs of which are used for dumping of the accumulated
charge on the photodiode. The integration time is set to 3 μs, which
is 1 μs more than the charge dump time to allow for timing margin
when integrating the incoming charge. Note, there is a 9 μs offset
built into the integration start time. Take this offset into account
when setting the SLOTx_AFE_OFFSET value. As shown in
Figure 40, the time of the first charge dump is set to 30 μs. SLOTx_
AFE_OFFSET is set to 0x238 (17.75 μs), taking into account the
3 μs integration time, the 9 μs offset, and an additional 250 ns
for edge placement margin.
To calculate SLOTx_AFE_OFFSET, use the following equation:
SLOTx_AFE_OFFSET = SLOTx_LED_OFFSET –
SLOTx_AFE_WIDTH − 9.25 μs
Placement of the integration period is such that the negative
phase of the integration is centered on the charge dump phase.
The TIA is an inverting stage, therefore, placing the negative
phase of the integration during the dumping of the charge from
the photodiode causes the integrator to increase with the
negative going output signal from the TIA.
The LED flashes in the second and third pulses of the four pulse
sequence. Setting Register 0x58, Bits[6:5] = 2 and Register 0x58,
Bits[11:10] = 1 forces the device to add the second and third
pulses while subtracting the first and fourth pulses, effectively
cancelling out the ambient light and electrical offsets and drift.
Rev. B | Page 39 of 61
ADPD188GG
Data Sheet
PRECONDITION
0x35[12:8] = 0x2
CHARGE DUMPTIME = 2µs
0x36[7:0] = 0x10
FLOAT PERIOD = 16µs
CONNECT/FLOAT
MASKED
LED PULSE
FLASH LED
FLASH LED
MASKED LED PULSE
LED PULSES
0x5A[15:12] = 0x9
MASK PULSE 1 AND MASK PULSE 4
FLASH PULSE 2 AND FLASH PULSE 3
0x3F[12:8] = 0xC
LED PW = 12µs
ACCUMULATED
CHARGE ON PD
INTEGRATOR
OUTPUT
INTEGRATOR
SEQUENCE
0x3B[15:11] = 0x3
INTEGRATION
TIME = 3µs
INTEGRATOR
RESET
ADC READ
t = 0
t = 16µs, 0x59[12:8] = 0x10
PRECONDITIONING TIME
t = 17µs, 0x3F[7:0] = 0x11
LED PULSE OFFSET
t = 26.75µs, 0x3B[10:0] = 0x238
START OF INTEGRATION TIME
t = 30µs, 0x35[7:0] = 0x1E
TIME OF FIRST CHARGE DUMP
Figure 40. Example Timing Diagram of Four Pulse Float LED Mode Sequence
A comparison of float ambient mode vs. float LED mode is shown in Table 23 and Table 24.
Table 23. Float Ambient Mode—Measure Ambient Light Level
Pulse Float Time
Integrated Charge
Calculation
Result
Ambient Measurement = Ambient 2 − Ambient 1 (offset cancels)
1
2
3
4
Shorter
Longer
Offset, Ambient 1 (shorter time) Subtract
Offset, Ambient 1 (shorter time) Add
Not applicable Not applicable
Not applicable Not applicable
Not applicable
Not applicable
Table 24. Float LED Mode—Measurement Synchronous Reflected Light from LED
Pulse Float Time Integrated Charge Calculation Result
1
2
3
4
Equal
Equal
Equal
Equal
Offset + Ambient
Subtract
Add
Add
Sync LED response = reflected LED return (offset and ambient cancel)
Offset + Ambient + LED
Offset + Ambient + LED
Offset + Ambient
Subtract
Rev. B | Page 40 of 61
Data Sheet
ADPD188GG
The user sets an ambient level threshold in the BG_THRESH
register, which is the threshold by which the ADC result of the
subtract cycles in float LED mode are compared against. The
subtract cycles in float LED mode are the positions in the pulse
sequence in which the LED pulse is masked; therefore, it is the
background level measurement. The ADC result is equal to the
raw ADC output minus the contents of the ADC offset register
(Register 0x18 to Register 0x1B and Register 0x1E to
Register 0x21). In the BG_COUNT register, the user sets a limit
on the number of cycles that BG_THRESH is exceeded by the
ADC result before the BG_STATUS bit is set for any particular
channel. Every time the BG_THRESH value is exceeded by the
ADC result during a subtract cycle, an internal counter
Monitoring Ambient Light Levels in Float LED Mode
In real-world applications, it is common for the ambient light
levels to change constantly. When using float LED mode,
increasing amounts of ambient light can approach levels where
it uses an unacceptable amount of the dynamic range of the
charge that can stored on the photodiode capacitance. For this
reason, it is required that the ambient light level is monitored
so that configuration changes can be made when necessary, for
example, float time, TIA gain, and operating mode. There are
two ways to monitor ambient light levels. One way is to use
TIA ADC mode in the alternate time slot and continuously
monitor the ambient light level. The other way is to use a
feature of the ADPD188GG where the ambient light level is
automatically monitored in the background during float mode
operation and is compared against a user-defined threshold. If
the ambient light level exceeds this threshold by some user-
defined number of times, a flag is set by the device that can be
read by the user or can be output to a GPIO. Table 25 lists all
the registers used to monitor the ambient light level while in
float LED mode.
increments. Each channel has its own counter. When this count
exceeds the limit set in the BG_COUNT register, the
BG_STATUS bit is set for the channel. The user can periodically
monitor the BG_STATUS register to check for asserted bits.
Alternatively, a GPIOx pin can be asserted if a BG_STATUS flag
is set. See Table 25 for the various logical combinations of
BG_STATUS flags and interrupts that can be brought out on a
GPIOx.
Table 25. Registers for Monitoring the Ambient Light Level in Float LED Mode
Register
Float Mode Register Name
Time Slot A
Time Slot B
Description
BG_STATUS_x
0x04, Bits[3:0]
0x04, Bits[7:4]
Status of comparison between background light level and background
threshold value (BG_THRESH). A 1 in any bit location means the threshold
has been crossed BG_COUNT number of times. This register is cleared once
it is read.
Bit 0: Time Slot A, Channel 1 exceeded threshold count.
Bit 1: Time Slot A, Channel 2 exceeded threshold count.
Bit 2: Time Slot A, Channel 3 exceeded threshold count.
Bit 3: Time Slot A, Channel 4 exceeded threshold count.
Bit 4: Time Slot B, Channel 1 exceeded threshold count.
Bit 5: Time Slot B, Channel 2 exceeded threshold count.
Bit 6: Time Slot B, Channel 3 exceeded threshold count.
Bit 7: Time Slot B, Channel 4 exceeded threshold count.
BG_THRESH_x
BG_COUNT_x
0x16, Bits[13:0] 0x1C[13:0]
0x16, Bits[15:14] 0x1C[15:14]
The background threshold that is compared against the ADC result during
the subtract cycles during float mode. If the ADC result exceeds the value
in this register, BG_COUNT is incremented.
This is the number of times the ADC value exceeds the BG_THRESH_x value
during the float mode subtract cycles before the BG_STATUS bit is set.
0x0: never set BG_STATUS.
0x1: set when BG_THRESH_x is exceeded 1 time.
0x02: set when BG_THRESH_x is exceeded 4 times.
0x03: set when BG_THRESH_x is exceeded 16 times.
GPIO0 asserts for the following conditions:
0x10: logical OR of BG_STATUS_x, Bits[3:0].
0x1A: logical OR of BG_STATUS_x, Bits[7:4].
0x1B: logical OR of BG_STATUS_x, Bits[7:0].
0x1C: logical OR of BG_STATUS_x, Bits[7:0] and INT.
GPIO1 asserts for the following conditions:
0x10: logical OR of BG_STATUS_x, Bits[3:0].
0x1A: logical OR of BG_STATUS_x, Bits[7:4].
0x1B: logical OR of BG_STATUS_x, Bits[7:0].
0x1C: logical OR of BG_STATUS_x, Bits[7:0] and INT.
GPIO0_ALT_CFG
GPIO1_ALT_CFG
0x0B[4:0]
0x0B[4:0]
0x0B[12:8]
0x0B[12:8]
Rev. B | Page 41 of 61
ADPD188GG
Data Sheet
REGISTER LISTING
The recommended values are not shown. Only power-on reset values are shown in Table 26. The recommended values are largely
dependent on use case.
Table 26. Numeric Register Listing
Bit 15
Bit 14
Bit 6
Bit 13
Bit 5
Bit 12
Bit 4
Bit 11
Bit 3
Bit 10
Bit 2
Bit 9
Bit 1
Bit 8
Bit 0
Hex.
Addr. Name
Bits
Bit 7
Reset
R/W
0x00 Status
[15:8]
FIFO_SAMPLES[7:0]
0x0000 R/W
[7:0] Reserved
[15:8]
SLOTB_INT
SLOTA_INT
Reserved
0x01 INT_MASK
Reserved
FIFO_INT_
MASK
0x00FF R/W
[7:0] Reserved
SLOTB_INT_ SLOTA_INT_
MASK MASK
Reserved
0x02 GPIO_
DRV
[15:8]
[7:0]
Reserved
Reserved
GPIO1_DRV GPIO1_POL
GPIO0_DRV GPIO0_POL
0x0000 R/W
0x0000 R/W
0x0000 R/W
GPIO0_ENA
0x04 BG_
STATUS
[15:8]
[7:0]
Reserved
Reserved
BG_STATUS_B[3:0]
BG_STATUS_A[3:0]
FIFO_THRESH[5:0]
0x06 FIFO_
THRESH
[15:8]
[7:0]
Reserved
0x08 DEVID
[15:8]
[7:0]
REV_NUM[7:0]
DEV_ID[7:0]
0x0A16
0x00C8 R/W
0x0000
R
0x09 I2CS_ID
[15:8]
[7:0]
ADDRESS_WRITE_KEY[7:0]
SLAVE_ADDRESS[6:0]
Reserved
0x0A CLK_
RATIO
[15:8]
[7:0]
Reserved
CLK_RATIO[11:8]
R
CLK_RATIO[7:0]
0x0B GPIO_
CTRL
[15:8]
[7:0]
Reserved
Reserved
GPIO1_ALT_CFG[4:0]
GPIO0_ALT_CFG[4:0]
0x0000 R/W
0x0000 R/W
0x0D SLAVE_
ADDRESS_
KEY
[15:8]
[7:0]
SLAVE_ADDRESS_KEY[15:8]
SLAVE_ADDRESS_KEY[7:0]
0x0F SW_RESET
[15:8]
[7:0]
Reserved
Reserved
0x0000 R/W
0x0000 R/W
0x1000 R/W
SW_RESET
Mode[1:0]
0x10 Mode
[15:8]
[7:0]
Reserved
Reserved
0x11 SLOT_EN
[15:8]
Reserved
RDOUT_
MODE
FIFO_OVRN_
PREVENT
Reserved
SLOTB_
FIFO_
MODE[2]
[7:0]
SLOTB_FIFO_MODE[1:0]
SLOTB_EN
SLOTA_FIFO_MODE[2:0]
Reserved
SLOTA_EN
0x12 FSAMPLE
[15:8]
FSAMPLE[15:8]
FSAMPLE[7:0]
0x0028 R/W
0x0541 R/W
0x0600 R/W
0x0000 R/W
[7:0]
0x14 PD_LED_
SELECT
[15:8]
Reserved
SLOTB_PD_SEL[3:0]
[7:0]
SLOTA_PD_SEL[3:0]
Reserved
SLOTB_LED_SEL[1:0]
SLOTA_LED_SEL[1:0]
SLOTB_NUM_AVG[2:0]
0x15 NUM_
AVG
[15:8]
[7:0] Reserved
SLOTA_NUM_AVG[2:0]
Reserved
0x16 BG_
MEAS_A
[15:8]
[7:0]
BG_COUNT_A[1:0]
BG_THRESH_A[13:8]
BG_THRESH_A[7:0]
0x17 INT_SEQ_A
[15:8]
[7:0]
Reserved
0x0000 R/
W
Reserved
INTEG_ORDER_A[3:0]
0x18 SLOTA_
CH1_
[15:8]
[7:0]
SLOTA_CH1_OFFSET[15:8]
SLOTA_CH1_OFFSET[7:0]
0x2000 R/W
OFFSET
0x19 SLOTA_
CH2_
[15:8]
[7:0]
SLOTA_CH2_OFFSET[15:8]
SLOTA_CH2_OFFSET[7:0]
0x2000 R/W
0x2000 R/W
0x2000 R/W
0x0000 R/W
OFFSET
0x1A SLOTA_
CH3_
[15:8]
[7:0]
SLOTA_CH3_OFFSET[15:8]
SLOTA_CH3_OFFSET[7:0]
OFFSET
0x1B SLOTA_
CH4_
[15:8]
[7:0]
SLOTA_CH4_OFFSET[15:8]
SLOTA_CH4_OFFSET[7:0]
OFFSET
0x1C BG_MEAS_B
[15:8
BG_COUNT_B[1:0]
BG_THRESH_B[13:8]
BG_THRESH_B[7:0]
Rev. B | Page 42 of 61
Data Sheet
ADPD188GG
Bit 15
Bit 7
Bit 14
Bit 6
Bit 13
Bit 5
Bit 12
Bit 4
Bit 11
Bit 3
Bit 10
Bit 2
Bit 9
Bit 1
Bit 8
Bit 0
Hex.
Addr. Name
Bits
Reset
R/W
0x1D INT_SEQ_B
[15:8]
[7:0]
Reserved
0x0000 R/
W
Reserved
INTEG_ORDER_B[3:0]
0x1E SLOTB_CH1_ [15:8]
SLOTB_CH1_OFFSET[15:8]
SLOTB_CH1_OFFSET[7:0]
SLOTB_CH2_OFFSET[15:8]
SLOTB_CH2_OFFSET[7:0]
SLOTB_CH3_OFFSET[15:8]
SLOTB_CH3_OFFSET[7:0]
SLOTB_CH4_OFFSET[15:8]
SLOTB_CH4_OFFSET[7:0]
0x2000 R/W
OFFSET
[7:0]
0x1F SLOTB_CH2_ [15:8]
0x2000 R/W
0x2000 R/W
0x2000 R/W
0x3000 R/W
0x3000 R/W
0x3000 R/W
0x630C R/W
0x0320 R/W
0x0818 R/W
0x0000 R/W
OFFSET
[7:0]
0x20 SLOTB_CH3_ [15:8]
OFFSET
[7:0]
0x21 SLOTB_CH4_ [15:8]
OFFSET
[7:0]
0x22 ILED3_
COARSE
[15:8]
Reserved
ILED3_SCALE
ILED3_SLEW[2:0]
ILED1_SCALE
Reserved
[7:0] Reserved
[15:8]
ILED3_COARSE[3:0]
Reserved
0x23 ILED1_
COARSE
Reserved
Reserved
[7:0] Reserved
[15:8]
ILED1_SLEW[2:0]
ILED2_SCALE
ILED1_COARSE[3:0]
Reserved
0x24 ILED2_
COARSE
[7:0] Reserved
[15:8]
ILED2_SLEW[2:0]
ILED3_FINE[4:0]
Reserved
ILED2_COARSE[3:0]
ILED2_FINE[4:2]
ILED1_FINE[4:0]
0x25 ILED_FINE
[7:0]
ILED2_FINE[1:0]
Reserved
0x30
SLOTA_LED_ [15:8]
SLOTA_LED_WIDTH[4:0]
SLOTA_LED_OFFSET[7:0]
PULSE
[7:0]
0x31 SLOTA_
NUMPULSES
[15:8]
[7:0]
SLOTA_PULSES[7:0]
SLOTA_PERIOD[7:0]
0x34 LED_
DISABLE
[15:8]
Reserved
SLOTB_
LED_DIS
SLOTA_
LED_DIS
[7:0]
Reserved
0x35 SLOTB_
LED_PULSE
[15:8]
[7:0]
Reserved
SLOTB_LED_WIDTH[4:0]
0x0320 R/W
0x0818 R/W
0x0000 R/W
SLOTB_LED_OFFSET[7:0]
SLOTB_PULSES[7:0]
SLOTB_PERIOD[7:0]
CH2_DISABLE[12:10]
0x36 SLOTB_
NUMPULSES
[15:8]
[7:0]
0x37 ALT_PWR_
DN
[15:8]
[7:0]
CH34_DISABLE[15:13]
SLOTB_PERIOD[9:8]
SLOTA_PERIOD[9:8]
Reserved
0x38 EXT_SYNC_
STARTUP
[15:8]
[7:0]
EXT_SYNC_STARTUP[15:8]
EXT_SYNC_STARTUP[7:0]
0x000
R/W
0x39 SLOTA_AFE_ [15:8]
SLOTA_AFE_WIDTH[4:0]
SLOTA_AFE_OFFSET[10:8]
0x22FC R/W
0x22FC R/W
WINDOW
[7:0]
SLOTA_AFE_OFFSET[7:0]
SLOTB_AFE_OFFSET[7:0]
0x3B SLOTB_
AFE_
[15:8]
[7:0]
SLOTB_AFE_WIDTH[4:0]
SLOTB_AFE_OFFSET[10:8]
WINDOW
0x3C AFE_PWR_
CFG1
[15:8]
Reserved
Reserved
Reserved
V_CATHODE AFE_
0x3006 R/W
POWER-
DOWN[5]
[7:0]
AFE_POWERDOWN[4:0]
Reserved
FLT_LED_WIDTH_A[4:0]
0x3E SLOTA_
FLOAT_LED
[15:8]
[7:0]
FLT_LED_SELECT_A[1:0]
Reserved
0x0320 R/W
0x0320 R/W
0x1C38 R/W
FLT_LED_OFFSET_A[7:0]
0x3F SLOTB_
FLOAT_LED
[15:8]
[7:0]
FLT_LED_SELECT_B[1:0]
Reserved
FLT_LED_WIDTH_B[4:0]
FLT_LED_OFFSET_B[7:0]
0x42 SLOTA_
TIA_CFG
[15:8]
SLOTA_AFE_MODE[5:0]
SLOTA_
BUF_GAIN
SLOTA_TIA_GAIN[1:0]
Reserved
[7:0] SLOTA_INT_ SLOTA_TIA_
AS_BUF IND_EN
SLOTA_TIA_VREF[1:0]
Reserved (write 0x1)
0x43 SLOTA_
AFE_CFG
[15:8]
[7:0]
SLOTA_AFE_CFG[15:8]
SLOTA_AFE_CFG[7:0]
SLOTB_AFE_MODE[5:0]
0xADA5 R/W
0x1C38 R/W
0x44 SLOTB_
TIA_CFG
[15:8]
SLOTB_
BUF_GAIN
Reserved
[7:0] SLOTB_INT_ SLOTB_
AS_BUF TIA_IND_EN
SLOTB_TIA_VREF[1:0]
Reserved (write 0x1)
SLOTB_TIA_GAIN[1:0]
0x45 SLOTB_
AFE_CFG
[15:8]
[7:0]
SLOTB_AFE_CFG[15:8]
SLOTB_AFE_CFG[7:0]
Reserved
0xADA5 R/W
0x2612 R/W
0x4B SAMPLE_
CLK
[15:8]
CLK32K_
BYP
[7:0] CLK32K_EN Reserved
CLK32K_ADJUST[5:0]
Rev. B | Page 43 of 61
ADPD188GG
Data Sheet
Bit 15
Bit 7
Bit 14
Bit 6
Bit 13
Bit 5
Bit 12
Bit 4
Bit 11
Bit 3
Bit 10
Bit 2
Bit 9
Bit 1
Bit 8
Bit 0
Hex.
Addr. Name
Bits
Reset
R/W
0x4D CLK32M_
ADJUST
[15:8]
[7:0]
Reserved
0x0098 R/W
0x2090 R/W
0x0000 R/W
CLK32M_ADJUST[7:0]
Reserved
0x4F EXT_SYNC_
SEL
[15:8]
[7:0] Reserved
[15:8]
GPIO1_OE
GPIO1_IE
Reserved
EXT_SYNC_SEL[1:0]
Reserved
GPIO0_IE
Reserved
0x50 CLK32M_
CAL_EN
[7:0] Reserved
GPIO1_CTRL CLK32M_
CAL_EN
Reserved
0x54 AFE_PWR_
CFG2
[15:8]
Reserved
SLEEP_V_CATHODE[1:0]
SLOTA_TIA_GAIN_4[1:0]
SLOTB_V_CATHODE[1:0]
Reserved
SLOTA_V_CATHODE[1:0]
0x0020 R/W
[7:0] REG54_
VCAT_
ENABLE
0x55 TIA_INDEP_
GAIN
[15:8]
Reserved
SLOTB_TIA_GAIN_2[1:0]
Reserved
FLT_MATH12_B[1:0]
SLOTB_TIA_GAIN_4[1:0]
SLOTA_TIA_GAIN_3[1:0]
FLT_MATH34_B[1:0]
SLOTB_TIA_GAIN_3[1:0]
SLOTA_TIA_GAIN_2[1:0]
FLT_MATH34_A[1:0]
0x0000 R/W
0x0000 R/W
[7:0]
[15:8]
[7:0]
0x58 Math
ENA_INT_
AS_BUF
Reserved
Reserved FLT_MATH12_A[1:0]
Reserved
0x59 FLT_
CONFIG_B
[15:8]
[7:0]
Reserved
FLT_EN_B[1:0]
FLT_LED_FIRE_B[3:0]
FLT_EN_A[1:0]
FLT_PRECON_B[4:0]
0x0808 R/W
0x0010 R/W
0x0808 R/W
0x0000 R/W
Reserved
0x5A FLT_
LED_FIRE
[15:8]
[7:0]
FLT_LED_FIRE_A[3:0]
FLT_PRECON_A[4:0]
Reserved (write 0x10)
0x5E FLT_
CONFIG_A
[15:8]
[7:0]
Reserved
Reserved
Reserved
0x5F
DATA_
ACCESS_CTL
[15:8]
[7:0]
Reserved
SLOTB_
DATA_
HOLD
SLOTA_
DATA_
HOLD
DIGITAL_
CLOCK_
ENA
0x60 FIFO_
ACCESS
[15:8]
[7:0]
FIFO_DATA[15:8]
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
FIFO_DATA[7:0]
0x64 SLOTA_
PD1_16BIT
[15:8]
[7:0]
SLOTA_CH1_16BIT[15:8]
SLOTA_CH1_16BIT[7:0]
SLOTA_CH2_16BIT[15:8]
SLOTA_CH2_16BIT[7:0]
SLOTA_CH3_16BIT[15:8]
SLOTA_CH3_16BIT[7:0]
SLOTA_CH4_16BIT[15:8]
SLOTA_CH4_16BIT[7:0]
SLOTB_CH1_16BIT[15:8]
SLOTB_CH1_16BIT[7:0]
SLOTB_CH2_16BIT[15:8]
SLOTB_CH2_16BIT[7:0]
SLOTB_CH3_16BIT[15:8]
SLOTB_CH3_16BIT[7:0]
SLOTB_CH4_16BIT[15:8]
SLOTB_CH4_16BIT[7:0]
SLOTA_CH1_LOW[15:8]
SLOTA_CH1_LOW[7:0]
SLOTA_CH2_LOW[15:8]
SLOTA_CH2_LOW[7:0]
SLOTA_CH3_LOW[15:8]
SLOTA_CH3_LOW[7:0]
SLOTA_CH4_LOW[15:8]
SLOTA_CH4_LOW[7:0]
SLOTA_CH1_HIGH[15:8]
SLOTA_CH1_HIGH[7:0]
SLOTA_CH2_HIGH[15:8]
SLOTA_CH2_HIGH[7:0]
SLOTA_CH3_HIGH[15:8]
SLOTA_CH3_HIGH[7:0]
SLOTA_CH4_HIGH[15:8]
SLOTA_CH4_HIGH[7:0]
0x65 SLOTA_
PD2_16BIT
[15:8]
[7:0]
0x66 SLOTA_
PD3_16BIT
[15:8]
[7:0]
0x67 SLOTA_
PD4_16BIT
[15:8]
[7:0]
0x68 SLOTB_
PD1_16BIT
[15:8]
[7:0]
0x69 SLOTB_
PD2_16BIT
[15:8]
[7:0]
0x6A SLOTB_
PD3_16BIT
[15:8]
[7:0]
0x6B SLOTB_
PD4_16BIT
[15:8]
[7:0]
0x70 A_PD1_LOW [15:8]
[7:0]
0x71 A_PD2_LOW [15:8]
[7:0]
0x72 A_PD3_LOW [15:8]
[7:0]
0x73 A_PD4_LOW [15:8]
[7:0]
0x74 A_PD1_HIGH [15:8]
[7:0]
0x75 A_PD2_HIGH [15:8]
[7:0]
0x76 A_PD3_HIGH [15:8]
[7:0]
0x77 A_PD4_HIGH [15:8]
[7:0]
Rev. B | Page 44 of 61
Data Sheet
ADPD188GG
Bit 15
Bit 7
Bit 14
Bit 6
Bit 13
Bit 5
Bit 12
Bit 4
Bit 11
Bit 3
Bit 10
Bit 2
Bit 9
Bit 1
Bit 8
Bit 0
Hex.
Addr. Name
Bits
Reset
R/W
0x78
B_PD1_LOW [15:8]
[7:0]
SLOTB_CH1_LOW[15:8]
SLOTB_CH1_LOW[7:0]
SLOTB_CH2_LOW[15:8]
SLOTB_CH2_LOW[7:0]
SLOTB_CH3_LOW[15:8]
SLOTB_CH3_LOW[7:0]
SLOTB_CH4_LOW[15:8]
SLOTB_CH4_LOW[7:0]
SLOTB_CH1_HIGH[15:8]
SLOTB_CH1_HIGH[7:0]
SLOTB_CH2_HIGH[15:8]
SLOTB_CH2_HIGH[7:0]
SLOTB_CH3_HIGH[15:8]
SLOTB_CH3_HIGH[7:0]
SLOTB_CH4_HIGH[15:8]
SLOTB_CH4_HIGH[7:0]
0x0000
R
0x79 B_PD2_LOW [15:8]
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
R
R
R
R
R
R
R
[7:0]
0x7A B_PD3_LOW [15:8]
[7:0]
0x7B B_PD4_LOW [15:8]
[7:0]
0x7C B_PD1_HIGH [15:8]
[7:0]
0x7D B_PD2_HIGH [15:8]
[7:0]
0x7E B_PD3_HIGH [15:8]
[7:0]
0x7F B_PD4_HIGH [15:8]
[7:0]
Rev. B | Page 45 of 61
ADPD188GG
Data Sheet
LED CONTROL REGISTERS
Table 27. LED Control Registers
Default
Value
Address Data Bit
Access
R/W
Name
Description
0x14
[15:12]
[11:8]
0x0
Reserved
Write 0x0 to these bits for proper operation.
0x5
R/W
SLOTB_PD_SEL
PDx connection selection for Time Slot B. See the Time Slot Switch
section for detailed descriptions.
[7:4]
[3:2]
0x4
0x0
R/W
R/W
SLOTA_PD_SEL
SLOTB_LED_SEL
PDx connection selection for Time Slot A. See the Time Slot Switch
section for detailed descriptions.
Time Slot B LED configuration. These bits determine which LED is
associated with Time Slot B.
0x0: pulse PDx connection to AFE. Float mode and pulse connect
mode enable.
0x1: LEDX1 pulses during Time Slot B.
0x2: LEDX2 pulses during Time Slot B.
0x3: LEDX3 pulses during Time Slot B.
[1:0]
0x1
R/W
SLOTA_LED_SEL
Time Slot A LED configuration. These bits determine which LED is
associated with Time Slot A.
0x0: pulse PDx connection to AFE. Float mode and pulse connect
mode enable.
0x1: LEDX1 pulses during Time Slot A.
0x2: LEDX2 pulses during Time Slot A.
0x3: LEDX3 pulses during Time Slot A.
Write 0x0.
0x22
[15:14]
13
0x0
0x1
R/W
R/W
Reserved
ILED3_SCALE
LEDX3 current scale factor.
1: 100% strength.
0: 10% strength; sets the LEDX3 driver in low power mode.
LEDX3 Current Scale = 0.1 + 0.9 × (Register 0x22, Bit 13).
Write 0x1.
12
0x1
0x0
0x0
R/W
R/W
R/W
Reserved
[11:7]
[6:4]
Reserved
Write 0x0.
ILED3_SLEW
LEDX3 driver slew rate control. The slower the slew rate, the safer
the performance in terms of reducing the risk of overvoltage of the
LED driver.
0x0: the slowest slew rate.
…
0x7: the fastest slew rate.
[3:0]1
0x0
R/W
ILED3_COARSE
LEDX3 coarse current setting. Coarse current sink target value of
LEDX3 in standard operation.
0x0: lowest coarse setting.
…
0xF: highest coarse setting.
LED3PEAK = LED3COARSE × LED3FINE × LED3SCALE
where:
LED3PEAK is the LEDX3 peak target value (mA).
LED3COARSE = 44.5 + 17.8 × (Register 0x22, Bits[3:0]).
LED3FINE = 0.73 + 0.022 × (Register 0x25, Bits[15:11]).
LED3SCALE = 0.1 + 0.9 × (Register 0x22, Bit 13).
0x23
[15:14]
13
0x0
0x1
R/W
R/W
Reserved
Write 0x0.
ILED1_SCALE
LEDX1 current scale factor.
1: 100% strength.
0: 10% strength; sets the LEDX1 driver in low power mode.
LEDX1 Current Scale = 0.1 + 0.9 × (Register 0x23, Bit 13).
12
0x1
0x0
R/W
R/W
Reserved
Reserved
Write 0x1.
Write 0x0.
[11:7]
Rev. B | Page 46 of 61
Data Sheet
ADPD188GG
Default
Value
Address Data Bit
Access
Name
Description
[6:4]
0x0
R/W
ILED1_SLEW
LEDX1 driver slew rate control. The slower the slew rate, the safer
the performance in terms of reducing the risk of overvoltage of the
LED driver.
0: the slowest slew rate.
…
7: the fastest slew rate.
[3:0]1
0x0
R/W
ILED1_COARSE
LEDX1 coarse current setting. Coarse current sink target value of
LEDX1 in standard operation.
0x0: lowest coarse setting.
…
0xF: highest coarse setting.
LED1PEAK = LED1COARSE × LED1FINE × LED1SCALE
where:
LED1PEAK is the LEDX1 peak target value (mA).
LED1COARSE = 44.5 + 17.8 × (Register 0x23, Bits[3:0]).
LED1FINE = 0.73 + 0.022 × (Register 0x25, Bits[4:0]).
LED1SCALE = 0.1 + 0.9 × (Register 0x23, Bit 13).
0x24
[15:14]
13
0x0
0x1
R/W
R/W
Reserved
Write 0x0.
ILED2_SCALE
LEDX2 current scale factor.
1: 100% strength.
0: 40% strength; sets the LEDX2 driver in low power mode.
LED2 Current Scale = 0.1 + 0.9 × (Register 0x24, Bit 13)
12
0x1
0x0
0x0
R/W
R/W
R/W
Reserved
Write 0x1.
Write 0x0.
[11:7]
[6:4]
Reserved
ILED2_SLEW
LEDX2 driver slew rate control. The slower the slew rate, the safer
the performance in terms of reducing the risk of overvoltage of the
LED driver.
0: the slowest slew rate.
…
7: the fastest slew rate.
[3:0]1
0x0
R/W
ILED2_COARSE
LEDX2 coarse current setting. Coarse current sink target value of
LEDX2 in standard operation.
0x0: lowest coarse setting.
…
0xF: highest coarse setting.
LED2PEAK = LED2COARSE × LED2FINE × LED2SCALE
where:
LED2PEAK is the LEDX2 peak target value (mA).
LED2COARSE = 44.5 + 17.8 × (Register 0x24, Bits[3:0]).
LED2FINE = 0.73 + 0.022 × (Register 0x25, Bits[10:6]).
LED2SCALE = 0.1 + 0.9 × (Register 0x24, Bit 13).
0x251
[15:11]
[10:6]
0xC
0xC
R/W
R/W
ILED3_FINE
ILED2_FINE
LEDX3 fine adjust. Current adjust multiplier for LED3.
LEDX3 fine adjust = 0.73 + 0.022 × (Register 0x25, Bits[15:11]).
See Register 0x22, Bits[3:0], for the full LED3 formula.
LEDX2 fine adjust. Current adjust multiplier for LED2.
LEDX2 fine adjust = 0.73 + 0.022 × (Register 0x25, Bits[10:6]).
See Register 0x24, Bits[3:0], for the full LED2 formula.
Write 0x0.
5
0x0
0xC
R/W
R/W
Reserved
[4:0]
ILED1_FINE
LEDX1 fine adjust. Current adjust multiplier for LED1.
LEDX1 Fine Adjust = 0.73 + 0.022 × (Register 0x25, Bits[4:0]).
See Register 0x23, Bits[3:0], for the full LED1 formula.
Rev. B | Page 47 of 61
ADPD188GG
Data Sheet
Default
Value
Address Data Bit
Access
R/W
Name
Description
0x30
[15:13]
[12:8]
[7:0]
0x0
Reserved
Write 0x0.
0x3
R/W
SLOTA_LED_WIDTH
SLOTA_LED_OFFSET
SLOTA_PULSES
LED pulse width (in 1 µs step) for Time Slot A.
LED offset width (in 1 µs step) for Time Slot A.
0x20
0x08
R/W
0x31
0x34
[15:8]
R/W
LED Time Slot A pulse count. nA: number of LED pulses in
Time Slot A.
[7:0]
[15:10]
9
0x18
0x00
0x0
R/W
R/W
R/W
SLOTA_PERIOD
Reserved
8 LSBs of LED Time Slot A pulse period (in 1 µs step).
Write 0x0.
SLOTB_LED_DIS
Time Slot B LED disable. 1: disables the LED assigned to Time Slot B.
Register 0x34 keeps the drivers active and prevents them from
pulsing current to the LEDs. Disabling both LEDs via this register
is often used to measure the dark level.
Use Register 0x11 instead to enable or disable the actual time slot
usage and not only the LED.
8
0x0
R/W
SLOTA_LED_DIS
Time Slot A LED disable. 1: disables the LED assigned to Time Slot A.
Use Register 0x11 instead to enable or disable the actual time slot
usage and not only the LED.
[7:0]
0x00
0x0
R/W
R/W
Reserved
Write 0x00.
0x35
0x36
[15:13]
[12:8]
[7:0]
Reserved
Write 0x0.
0x3
SLOTB_LED_WIDTH
SLOTB_LED_OFFSET
SLOTB_PULSES
SLOTB_PERIOD
LED pulse width (in 1 µs step) for Time Slot B.
LED offset width (in 1 µs step) for Time Slot B.
LED Time Slot B pulse count. nB: number of LED pulses in Time Slot B.
8 LSBs of LED Time Slot B pulse period (in 1 µs step).
0x20
0x08
0x18
[15:8]
[7:0]
R/W
R/W
1 LED equations provide an estimate of the LED current to within 20% at 25°C when applying 5.0 V on the VLEDx pin. This current varies with the VLEDx supply level
and temperature.
AFE CONFIGURATION REGISTERS
Table 28. AFE Global Configuration Registers
Default
Value
Address
Data Bit
Access
Name
Description
0x37
[15:13]
0x0
R/W
CH34_DISABLE
Power-down options for Channel 3 and Channel 4 only.
Bit 13: power down Channel 3, Channel 4 TIA op amp.
Bit 14: power down Channel 3, Channel 4 BPF op amp.
Bit 15: power down Channel 3, Channel 4 integrator op amp.
Bit 10: power down Channel 2 TIA op amp.
Bit 11: power down Channel 2 BPF op amp.
Bit 12: power down Channel 2 integrator op amp.
8 MSBs of LED Time Slot B pulse period.
Write 0x00
[12:10]
0x0
R/W
CH2_DISABLE
[9:8]
[7:2]
[1:0]
[15:14]
[13:11]
10
0x0
0x00
0x0
0x0
0x6
0x0
0x0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SLOTB_PERIOD
Reserved
SLOTA_PERIOD
Reserved
8 MSBs of LED Time Slot A pulse period.
Write 0x0.
0x3C
Reserved
Write 0x6.
Reserved
Reserved.
9
V_CATHODE
0x0: 1.3 V (identical to anode voltage).
0x1: 1.8 V (reverse bias photodiode by 550 mV). This
setting may add noise.
Rev. B | Page 48 of 61
Data Sheet
ADPD188GG
Default
Value
Address
Data Bit
Access
Name
Description
[8:3]
0x00
R/W
AFE_POWERDOWN
AFE channels power-down select.
0x0: keeps all channels on.
Bit 3: power down Channel 1 TIA op amp.
Bit 4: power down Channel 1 BPF op amp.
Bit 5: power down Channel 1 integrator op amp.
Bit 6: power down Channel 2, Channel 3, and Channel 4
TIA op amp.
Bit 7: power down Channel 2, Channel 3, and Channel 4
BPF op amp.
Bit 8: power down Channel 2, Channel 3, and Channel 4
integrator op amp.
[2:0]
0x6
0x0
0x0
R/W
R/W
R/W
Reserved
Write 0x6.
Write 0x0.
0x54
[15:14]
[13:12]
Reserved
SLEEP_V_CATHODE
If Bit 7 = 1; this setting is applied to the cathode voltage
while the device is in sleep mode.
0x0: VDD.
0x1:AFE VREF during idle, VDD during sleep.
0x2: floating.
0x3: 0.0 V.
[11:10]
[9:8]
7
0x0
0x0
0x0
R/W
R/W
R/W
SLOTB_V_CATHODE
SLOTA_V_CATHODE
REG54_VCAT_ENABLE
If Bit 7 = 1; this setting is applied to the cathode voltage
while the device is in Time Slot B operation. The anode
voltage is determined by Register 0x44, Bits[5:4].
0x0: VDD (1.8 V).
0x1: equal to PD anode voltage.
0x2: sets a reverse PD bias of ~250 mV (recommended
setting).
0x3: 0.0 V (this forward biases a diode at the input).
If Bit 7 = 1; this setting is applied to the cathode voltage
while the device is in Time Slot A operation. The anode
voltage is determined by Register 0x42, Bits[5:4].
0x0: VDD (1.8 V).
0x1: equal to PD anode voltage.
0x2: sets a reverse PD bias of ~250 mV (recommended
setting).
0x3: 0.0 V (this forward biases a diode at the input).
0: use the cathode voltage settings defined by Register 0x3C,
Bit 9.
1: override Register 0x3C, Bit 9 with cathode settings
defined by Register 0x54, Bits[13:8].
[6:0]
0x20
0x0
R/W
R/W
R/W
Reserved
Reserved.
Write 0x0.
0x55
[15:12]
[11:10]
Reserved
0x0
SLOTB_TIA_GAIN_4
TIA gain for Time Slot B, Channel 4 when Register 0x44,
Bit 6 = 1.
0: 200 kΩ.
1: 100 kΩ.
2: 50 kΩ.
3: 25 kΩ.
[9:8]
0x0
R/W
SLOTB_TIA_GAIN_3
TIA gain for Time Slot B, Channel 3 when Register 0x44,
Bit 6 = 1.
0: 200 kΩ
1: 100 kΩ.
2: 50 kΩ.
3: 25 kΩ.
Rev. B | Page 49 of 61
ADPD188GG
Data Sheet
Default
Value
Address
Data Bit
Access
Name
Description
[7:6]
[5:4]
[3:2]
[1:0]
0x0
0x0
0x0
0x0
R/W
SLOTB_TIA_GAIN_2
TIA gain for Time Slot B, Channel 2 when Register 0x44,
Bit 6 = 1.
0: 200 kΩ
1: 100 kΩ.
2: 50 kΩ.
3: 25 kΩ.
R/W
R/W
R/W
SLOTA_TIA_GAIN_4
SLOTA_TIA_GAIN_3
SLOTA_TIA_GAIN_2
TIA gain for Time Slot A, Channel 4 when Register 0x42,
Bit 6 = 1.
0: 200 kΩ
1: 100 kΩ.
2: 50 kΩ.
3: 25 kΩ.
TIA gain for Time Slot A, Channel 3 when Register 0x42,
Bit 6 = 1.
0: 200 kΩ
1: 100 kΩ.
2: 50 kΩ.
3: 25 kΩ.
TIA gain for Time Slot A, Channel 2 when Register 0x42,
Bit 6 = 1.
0: 200 kΩ
1: 100 kΩ.
2: 50 kΩ.
3: 25 kΩ.
Table 29. AFE Configuration Registers, Time Slot A
Data
Address Bit
Default
Value
Access Name
Description
0x17
[15:4]
[3:0]
0x000
0x0
R/W
R/W
Reserved
INTEG_ORDER_A
Write 0x000
Integration sequence order for Time Slot A. Each bit corresponds to the
polarity of the integration sequence of a single pulse in a four-pulse
sequence. Bit 0 controls the integration sequence of Pulse 1, Bit 1 controls
Pulse 2, Bit 2 controls Pulse 3, and Bit 3 controls Pulse 4. After four pulses,
the sequence repeats.
0: normal integration sequence.
1: reversed integration sequence.
0x39
0x42
[15:11] 0x4
R/W
R/W
R/W
R/W
SLOTA_AFE_WIDTH AFE integration window width (in 1 µs step) for Time Slot A.
SLOTA_AFE_OFFSET AFE integration window offset for Time Slot A in 31.25 ns steps.
[10:0]
0x2FC
[15:10] 0x07
SLOTA_AFE_MODE
SLOTA_BUF_GAIN
Set to 0x07.
9
0x0
0: integrator as buffer gain = 1.
1: integrator as buffer gain = 0.7.
Set to 0.
8
7
0x0
0x0
R/W
R/W
Reserved
SLOTA_INT_AS_BUF 0: normal integrator configuration.
1: converts integrator to buffer amplifier (used in TIA ADC mode only).
6
0x0
R/W
SLOTA_TIA_IND_EN Enable Time Slot A TIA gain individual settings. When it is enabled, the
Channel 1 TIA gain is set via Register 0x42, Bits[1:0], and the Channel 2
through Channel 4 TIA gain is set via Register 0x55, Bits[5:0].
0: disable TIA gain individual setting.
1: enable TIA gain individual setting.
[5:4]
0x3
R/W
SLOTA_TIA_VREF
Set VREF of the TIA for Time Slot A.
0: 1.14 V.
1: 1.01 V.
2: 0.90 V.
3: 1.27 V (default recommended).
Rev. B | Page 50 of 61
Data Sheet
ADPD188GG
Data
Address Bit
Default
Value
Access Name
Description
[3:2]
[1:0]
0x2
0x0
R/W
R/W
Reserved
SLOTA_TIA_GAIN
Reserved. Write 0x1.
Transimpedance amplifier gain for Time Slot A. When SLOTA_TIA_IND_EN
is enabled, this value is for Time Slot B, Channel 1 TIA gain. When
SLOTA_TIA_IND_EN is disabled, it is for all four Time Slot A channel TIA
gain settings.
0: 200 kΩ.
1: 100 kΩ.
2: 50 kΩ.
3: 25 kΩ.
0x43
[15:0]
0xADA5 R/W
SLOTA_AFE_CFG
AFE connection in Time Slot A.
0xADA5: analog full path mode (TIA→BPF→INT→ADC).
0xAE65: TIA ADC mode (must set Register 0x42, Bit 7 = 1 and Register
0x58, Bit 7 = 1).
0xB065: TIA ADC mode (if Register 0x42, Bit 7 = 0).
Others: reserved.
Table 30. AFE Configuration Registers, Time Slot B
Data
Address Bit
Default
Value
Access Name
Description
0x1D
[15:4]
[3:0]
0x000
0x0
R/W
R/W
Reserved
INTEG_ORDER_B
Write 0x000
Integration sequence order for Time Slot B. Each bit corresponds to the
polarity of the integration sequence of a single pulse in a four-pulse
sequence. Bit 0 controls the integration sequence of Pulse 1, Bit 1 controls
Pulse 2, Bit 2 controls Pulse 3, and Bit 3 controls Pulse 4. After four pulses,
the sequence repeats.
0: normal integration sequence.
1: reversed integration sequence
0x3B
0x44
[15:11] 0x04
[10:0] 0x17
[15:10] 0x07
R/W
R/W
R/W
R/W
SLOTB_AFE_WIDTH AFE integration window width (in 1 µs step) for Time Slot B.
SLOTB_AFE_OFFSET AFE integration window offset for Time Slot B in 31.25 ns steps.
SLOTB_AFE_MODE
SLOTB_BUF_GAIN
Set to 0x07.
9
0x0
0: integrator as buffer gain = 1.
1: integrator as buffer gain = 0.7.
Set to 0.
8
7
0x0
0x0
R/W
R/W
Reserved
SLOTB_INT_AS_BUF 0: normal integrator configuration.
1: convert integrator to buffer amplifier (used in TIA ADC mode only).
6
0x0
R/W
SLOTB_TIA_IND_EN Enable Time Slot B TIA gain individual settings. When it is enabled, the
Channel 1 TIA gain is set via Register 0x44, Bits[1:0], and the Channel 2
through Channel 4 TIA gain is set via Register 0x55, Bits[11:6].
0: disable TIA gain individual setting.
1: enable TIA gain individual setting.
[5:4]
0x3
R/W
SLOTB_TIA_VREF
Reserved
Set VREF of the TIA for Time Slot B.
0: 1.14 V.
1: 1.01 V.
2: 0.90 V.
3: 1.27 V (default recommended).
Write 0x1.
[3:2]
0x2
R/W
Rev. B | Page 51 of 61
ADPD188GG
Data Sheet
Data
Address Bit
Default
Value
Access Name
R/W SLOTB_TIA_GAIN
Description
[1:0]
0x0
Transimpedance amplifier gain for Time Slot B. When SLOTB_TIA_ IND_EN is
enabled, this value is for Time Slot B, Channel 1 TIA gain. When
SLOTB_TIA_IND_EN is disabled, it is for all four Time Slot B channel TIA gain
settings.
0: 200 kΩ.
1: 100 kΩ.
2: 50 kΩ.
3: 25 kΩ.
0x45
[15:0]
0xADA5 R/W
SLOTB_AFE_CFG
AFE connection in Time Slot B.
0xADA5: analog full path mode (TIA→BPF→INT→ADC).
0xAE65: TIA ADC mode (must set Register 0x44, Bit 7 = 1 and Register
0x58, Bit 7 = 1).
0xB065: TIA ADC mode (if Register 0x44, Bit 7 = 0).
Others: reserved.
FLOAT MODE REGISTERS
Table 31. Float Mode Registers
Default
Value
Address Data Bit
Access
Name
Description
0x04
[15:8]
[7:4]
0x0
R
R
Reserved
BG_STATUS_B
Not applicable.
0x0
Status of comparison between background light level and
background threshold value for Time Slot B (BG_THRESH_B). A 1
in any bit location means the threshold has been crossed
BG_COUNT_B number of times. This register is cleared once it is
read.
Bit 4: Time Slot B, Channel 1 exceeded threshold count.
Bit 5: Time Slot B, Channel 2 exceeded threshold count.
Bit 6: Time Slot B, Channel 3 exceeded threshold count.
Bit 7: Time Slot B, Channel 4 exceeded threshold count.
[3:0]
0x0
R
BG_STATUS_A
Status of comparison between background light level and
background threshold value for Time Slot A (BG_THRESH_A).
A 1 in any bit location means the threshold has been crossed
BG_COUNT_A number of times. This register is cleared once it is
read.
Bit 0: Time Slot A, Channel 1 exceeded threshold count.
Bit 1: Time Slot A, Channel 2 exceeded threshold count.
Bit 2: Time Slot A, Channel 3 exceeded threshold count.
Bit 3: Time Slot A, Channel 4 exceeded threshold count.
0x16
[15:14]
[13:0]
0x0
0x0
R/W
R/W
BG_COUNT_A
BG_THRESH_A
For Time Slot A, this is the number of times the ADC value
exceeds the BG_THRESH_A value during the float mode subtract
cycles before the BG_STATUS_A bit is set.
0: never set BG_STATUS_A.
1: set when BG_THRESH_A is exceeded 1 time.
2: set when BG_THRESH_A is exceeded 4 times.
3: set when BG_THRESH_A is exceeded 16 times.
The background threshold for Time Slot A that is compared
against the ADC result during the subtract cycles during float
mode. If the ADC result exceeds the value in this register,
BG_COUNT_A is incremented.
Rev. B | Page 52 of 61
Data Sheet
ADPD188GG
Default
Value
Address Data Bit
Access
Name
Description
0x1C
[15:14]
0x0
R/W
BG_COUNT_B
For Time Slot B, this is the number of times the ADC value
exceeds the BG_THRESH_B value during the float mode subtract
cycles before the BG_STATUS_B bit is set.
0: never set BG_STATUS_B.
1: set when BG_THRESH_B is exceeded 1 time.
2: set when BG_THRESH_B is exceeded 4 times.
3: set when BG_THRESH_B is exceeded 16 times.
[13:0]
0x0
0x0
R/W
R/W
BG_THRESH_B
The background threshold for Time Slot B that is compared
against the ADC result during the subtract cycles during float
mode. If the ADC result exceeds the value in this register,
BG_COUNT_B is incremented.
0x3E
0x3F
0x58
[15:14]
FLT_LED_SELECT_A
Time Slot A LED selection for float LED mode.
0: no LED selected.
1: LED1.
2: LED2.
3: LED3.
13
0
R/W
R/W
R/W
R/W
Reserved
Write 0x0.
[12:8]
[7:0]
0x03
0x20
0x0
FLT_LED_WIDTH_A
FLT_LED_OFFSET_A
FLT_LED_SELECT_B
Time Slot A LED pulse width for LED float mode in 1 µs steps.
Time to first LED pulse in float mode for Time Slot A.
[15:14]
Time Slot B LED selection for float LED mode.
0: no LED selected.
1: LED1.
2: LED2.
3: LED3.
13
0
R/W
R/W
R/W
R/W
R/W
Reserved
Write 0x0.
[12:8]
[7:0]
0x03
0x20
0x0
0x0
FLT_LED_WIDTH_B
FLT_LED_OFFSET_B
Reserved
Time Slot B LED pulse width for LED float mode in 1 µs steps.
Time to first LED pulse in Float mode for Time Slot A.
Reserved.
[15:12]
[11:10]
FLT_MATH34_B
Time Slot B control for adding and subtracting Sample 3 and
Sample 4 in a four-pulse sequence (or any multiple of four pulses,
for example, Sample 15 and Sample 16 in a 16-pulse sequence).
00: add third and fourth.
01: add third and subtract fourth.
10: subtract third and add fourth.
11: subtract third and fourth.
[9:8]
0x0
R/W
FLT_MATH34_A
Time Slot A control for adding and subtracting Sample 3 and
Sample 4 in a four-pulse sequence (or any multiple of four pulses,
for example, Sample 15 and Sample 16 in a 16-pulse sequence).
00: add third and fourth.
01: add third and subtract fourth.
10: subtract third and add fourth.
11: subtract third and fourth.
7
0x0
0x0
R/W
R/W
ENA_INT_AS_BUF
FLT_MATH12_B
Set to 1 to enable the configuration of the integrator as a buffer in
TIA ADC mode.
[6:5]
Time Slot B control for adding and subtracting Sample 1 and
Sample 2 in a four-pulse sequence (or any multiple of four pulses,
for example, Sample 13 and Sample 14 in a 16-pulse sequence).
00: add first and second.
01: add first and subtract second.
10: subtract first and add second.
11: subtract first and second.
Write 0x0.
[4:3]
0x0
R/W
Reserved
Rev. B | Page 53 of 61
ADPD188GG
Data Sheet
Default
Value
Address Data Bit
Access
Name
Description
[2:1]
0x0
R/W
FLT_MATH12_A
Time Slot A control for adding and subtracting Sample 1 and
Sample 2 in a four-pulse sequence (or any multiple of four pulses,
for example, Sample 13 and Sample 14 in a 16-pulse sequence).
00: add first and second.
01: add first and subtract second.
10: subtract first and add second.
11: subtract first and second.
Write 0x0.
0
0x0
0x0
0x0
R/W
R/W
R/W
Reserved
Reserved
FLT_EN_B
0x59
15
Write 0x0.
[14:13]
0: default setting, float disabled for Time Slot B.
1: reserved.
2: reserved.
3: enable float mode.
[12:8]
0x08
R/W
FLT_PRECON_B
Float mode preconditioning time for Time Slot B. Time to start of
first float time, which is typically 16 µs.
[7:0]
0x08
0x0
R/W
R/W
Reserved
Write 0x08.
0x5A
[15:12]
FLT_LED_FIRE_B
In any given sequence of four pulses, fire the LED in the selected
position by writing a zero into that pulse position. Mask the LED
pulse (that is, do not fire LED) by writing a 1 into that position. In a
sequence of four pulses on Time Slot B, Register 0x5A, Bit 12, is
the first pulse, Bit 13 is the second pulse, Bit 14 is the third pulse,
and Bit 15 is the fourth pulse.
[11:8]
0x0
R/W
FLT_LED_FIRE_A
In any given sequence of four pulses, fire the LED in the selected
position by writing a zero into that pulse position. Mask the LED
pulse (that is, do not fire LED) by writing a 1 into that position. In a
sequence of four pulses on Time Slot A, Register 0x5A, Bit 8, is the
first pulse, Bit 9 is the second pulse, Bit 10 is the third pulse, and
Bit 11 is the fourth pulse.
[7:0]
15
0x10
0x0
R/W
R/W
R/W
Reserved
Reserved
FLT_EN_A
Write 0x10.
0x5E
Write 0x0.
[14:13]
0x0
0: default setting, float disabled for Time Slot A.
1: reserved
2: reserved
3: enable float mode in Time Slot A.
[12:8]
[7:0]
0x08
0x08
R/W
R/W
FLT_PRECON_A
Reserved
Float mode preconditioning time for Time Slot A. Time to start of
first float time, which is typically 16 µs.
Write 0x08.
Rev. B | Page 54 of 61
Data Sheet
ADPD188GG
SYSTEM REGISTERS
Table 32. System Registers
Default
Value
Address Data Bit
Access
Name
Description
0x00
[15:8]
0x00
R/W
FIFO_SAMPLES
FIFO status. Number of available bytes to be read from the FIFO.
When comparing this to the FIFO length threshold (Register 0x06,
Bits[13:8]), note that the FIFO status value is in bytes and the FIFO
length threshold is in words, where one word = two bytes.
Write 1 to Bit 15 to clear the contents of the FIFO.
Write 0x1 to clear this bit to 0x0.
7
6
0x0
0x0
R/W
R/W
Reserved
SLOTB_INT
Time Slot B interrupt. Describes the type of interrupt event. A 1
indicates an interrupt of a particular event type has occurred. Write
a 1 to clear the corresponding interrupt. After clearing, the register
goes to 0. Writing a 0 to this register has no effect.
5
0x0
R/W
SLOTA_INT
Time Slot A interrupt. Describes the type of interrupt event. A 1
indicates an interrupt of a particular event type has occurred. Write a
1 to clear the corresponding interrupt. After clearing, the register
goes to 0. Writing a 0 to this register has no effect.
[4:0]
[15:9]
8
0x00
0x00
0x1
R/W
R/W
R/W
Reserved
Write 0x1F to clear these bits to 0x00.
Write 0x00.
0x01
Reserved
FIFO_INT_MASK
Sends an interrupt when the FIFO data length has exceeded the
FIFO length threshold in Register 0x06, Bits[13:8]. A 0 enables the
interrupt.
7
6
0x1
0x1
R/W
R/W
Reserved
Write 0x1.
SLOTB_INT_MASK
Sends an interrupt on the Time Slot B sample. Write a 1 to disable
the interrupt. Write a 0 to enable the interrupt.
5
0x1
R/W
SLOTA_INT_MASK
Sends an interrupt on the Time Slot A sample. Write a 1 to disable
the interrupt. Write a 0 to enable the interrupt.
[4:0]
[15:10]
9
0x1F
0x00
0x0
R/W
R/W
R/W
Reserved
Reserved
GPIO1_DRV
Write 0x1F.
0x02
Write 0x0000.
GPIO1 drive.
0: the GPIO1 pin is always driven.
1: the GPIO1 pin is driven when the interrupt is asserted; otherwise,
it is left floating and requires a pull-up or pull-down resistor,
depending on polarity (operates as open drain). Use this setting if
multiple devices must share the GPIO1 pin.
8
0x0
R/W
GPIO1_POL
GPIO1 polarity.
0: the GPIO1 pin is active high.
1: the GPIO1 pin is active low.
Write 0x00.
[7:3]
2
0x00
0x0
R/W
R/W
Reserved
GPIO0_ENA
GPIO0 pin enable.
0: disable the GPIO0 pin. The GPIO0 pin floats, regardless of
interrupt status. The status register (Address 0x00) remains active.
1: enable the GPIO0 pin.
GPIO0 drive.
0: the GPIO0 pin is always driven.
1: the GPIO0 pin is driven when the interrupt is asserted; otherwise,
it is left floating and requires a pull-up or pull-down resistor,
depending on polarity (operates as open drain). Use this setting if
multiple devices must share the GPIO0 pin.
1
0
0x0
0x0
R/W
R/W
GPIO0_DRV
GPIO0_POL
GPIO0 polarity.
0: the GPIO0 pin is active high.
1: the GPIO0 pin is active low.
Rev. B | Page 55 of 61
ADPD188GG
Data Sheet
Default
Value
Address Data Bit
Access
R/W
Name
Description
0x06
[15:14]
[13:8]
0x0
Reserved
FIFO_THRESH
Write 0x0.
0x00
R/W
FIFO length threshold. An interrupt is generated when the number of
data-words in the FIFO exceeds the value in FIFO_THRESH. The interrupt
pin automatically deasserts when the number of data-words available
in the FIFO no longer exceeds the value in FIFO_THRESH.
[7:0]
[15:8]
[7:0]
[15:8]
[7:1]
0
0x00
0x0A
0x16
0x00
0x64
0x0
R/W
R
Reserved
REV_NUM
DEV_ID
Write 0x00.
0x08
0x09
Revision number.
Device ID.
R
W
R/W
R
ADDRESS_WRITE_KEY Write 0xAD when writing to SLAVE_ADDRESS. Otherwise, do not access.
SLAVE_ADDRESS
Reserved
I2C slave address.
Do not access.
Write 0x0.
0x0A
0x0B
[15:12]
[11:0]
0x0
R
Reserved
0x000
R
CLK_RATIO
When the CLK32M_CAL_EN bit (Register 0x50, Bit 5) is set, the
device calculates the number of 32 MHz clock cycles in two cycles of
the 32 kHz clock. The result, nominally 2000 (0x07D0), is stored in
the CLK_RATIO bits.
[15:13]
[12:8]
0x0
R/W
R/W
Reserved
Write 0x0.
0x00
GPIO1_ALT_CFG
Alternate configuration for the GPIO1 pin.
0x00: GPIO1 is backward compatible to the ADPD103 PDSO pin
functionality.
0x01: interrupt function provided on GPIO1, as defined in Register 0x01.
0x02: asserts at the start of the first time slot, deasserts at end of last
time slot.
0x05: Time Slot A pulse output.
0x06: Time Slot B pulse output.
0x07: pulse output of both time slots.
0x0C: output data cycle occurred for Time Slot A.
0x0D: output data cycle occurred for Time Slot B.
0x0E: output data cycle occurred.
0x0F: toggles on every sample, which provides a signal at half the
sampling rate.
0x10: output = 0.
0x11: output = 1.
0x13: 32 kHz oscillator output.
Remaining settings are not supported.
Write 0x0.
[7:5]
[4:0]
0x0
R/W
R/W
Reserved
0x00
GPIO0_ALT_CFG
Alternate configuration for the GPIO0 pin.
0x0: GPIO0 is backward compatible to the ADPD103 INT pin
functionality.
0x1: interrupt function provided on GPIO0, as defined in Register 0x01.
0x2: asserts at the start of the first time slot, deasserts at end of last
time slot.
0x5: Time Slot A pulse output.
0x6: Time Slot B pulse output.
0x7: pulse output of both time slots.
0xC: output data cycle occurred for Time Slot A.
0xD: output data cycle occurred for Time Slot B.
0xE: output data cycle occurred.
0xF: toggles on every sample, which provides a signal at half the
sampling rate.
0x10: output = 0.
0x11: output = 1.
0x13: 32 kHz oscillator output.
Remaining settings are not supported.
Rev. B | Page 56 of 61
Data Sheet
ADPD188GG
Default
Value
Address Data Bit
Access
Name
Description
0x0D
[15:0]
0x0000 R/W
SLAVE_ADDRESS_KEY Enable changing the I2C address using Register 0x09.
0x04AD: enable address change always.
0x44AD: enable address change if GPIO0 is high.
0x84AD: enable address change if GPIO1 is high.
0xC4AD: enable address change if both GPIO0 and GPIO1 are high.
0x0F
0x10
[15:1]
0
0x0000
0x0
R
Reserved
Write 0x0000.
R/W
SW_RESET
Software reset. Write 0x1 to reset the device. This bit clears itself
after a reset. For I2C communications, this command returns an
acknowledge and the device subsequently returns to standby mode
with all registers reset to the default state.
[15:2]
[1:0]
0x0000 R/W
Reserved
Mode
Write 0x000.
0x0
R/W
Determines the operating mode of the ADPD1080/ADPD1081.
0x0: standby.
0x1: program.
0x2: normal operation.
0x11
[15:14]
13
0x0
0x0
R/W
R/W
Reserved
Reserved.
RDOUT_MODE
Readback data mode for extended data registers.
0x0: block sum of N samples.
0x1: block average of N samples.
12
0x1
R/W
FIFO_OVRN_PREVENT 0x0: wrap around FIFO, overwriting old data with new.
0x1: new data if FIFO is not full (recommended setting).
[11:9]
[8:6]
0x0
0x0
R/W
R/W
Reserved
Reserved.
SLOTB_FIFO_MODE
Time Slot B FIFO data format.
0: no data to FIFO.
1: 16-bit sum of all four channels.
2: 32-bit sum of all four channels.
4: four channels of 16-bit sample data for Time Slot B.
6: four channels of 32-bit extended sample data for Time Slot B.
Others: reserved.
The selected Time Slot B data is saved in the FIFO. Available only if
Time Slot A has the same averaging factor, N (Register 0x15, Bits[10:8]
= Bits[6:4]), or if Time Slot A is not saving data to the FIFO (Register 0x11,
Bits[4:2] = 0).
5
0x0
0x0
R/W
R/W
SLOTB_EN
Time Slot B enable. 1: enables Time Slot B.
Time Slot A FIFO data format.
[4:2]
SLOTA_FIFO_MODE
0: no data to FIFO.
1: 16-bit sum of all four channels.
2: 32-bit sum of all four channels.
4: four channels of 16-bit sample data for Time Slot A.
6: four channels of 32-bit extended sample data for Time Slot A.
Others: reserved.
1
0x0
0x0
R/W
R/W
Reserved
Write 0x0.
0
SLOTA_EN
Time Slot A enable. 1: enables Time Slot A.
Write 0x4000 when EXT_SYNC_SEL is 01 or 10. Otherwise, write 0x0.
Write 0x13.
0x38
0x4B
[15:0]
[15:9]
8
0x0000 R/W
EXT_SYNC_STARTUP
Reserved
0x13
0x0
R/W
R/W
CLK32K_BYP
Bypass internal 32 kHz oscillator.
0x0: normal operation.
0x1: provide external clock on the GPIO1 pin. The user must set
Register 0x4F, Bits[6:5] = 01 to enable the GPIO1 pin as an input.
7
6
0x0
0x0
R/W
R/W
CLK32K_EN
Reserved
Sample clock power-up. Enables the data sample clock.
0x0: clock disabled.
0x1: normal operation.
Write 0x0.
Rev. B | Page 57 of 61
ADPD188GG
Data Sheet
Default
Value
Address Data Bit
Access
Name
Description
[5:0]
0x12
R/W
CLK32K_ADJUST
Data sampling (32 kHz) clock frequency adjust. This register is used
to calibrate the sample frequency of the device to achieve high
precision on the data rate as defined in Register 0x12. Adjusts the
sample master 32 kHz clock by 0.6 kHz per LSB. For a 100 Hz sample
rate as defined in Register 0x12, 1 LSB of Register 0x4B, Bits[5:0], is
1.9 Hz.
Note that a larger value produces a lower frequency. See the Clocks
and Timing Calibration section for more information regarding clock
adjustment.
00 0000: maximum frequency.
10 0010: typical center frequency.
11 1111: minimum frequency.
Write 0x00.
0x4D
[15:8]
[7:0]
0x00
0x98
R/W
R/W
Reserved
CLK32M_ADJUST
Internal timing (32 MHz) clock frequency adjust. This register is used
to calibrate the internal clock of the device to achieve precisely
timed LED pulses. Adjusts the 32 MHz clock by 109 kHz per LSB.
See the Clocks and Timing Calibration section for more information
regarding clock adjustment.
0000 0000: minimum frequency.
1001 1000: default frequency.
1111 1111: maximum frequency.
Write 0x20.
0x4F
[15:8]
0x20
0x1
0x0
0x0
0x1
0x0
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
7
Reserved
Write 0x1.
6
GPIO1_OE
GPIO1_IE
GPIO1 pin output enable.
GPIO1 pin input enable.
Write 0x1.
5
4
Reserved
[3:2]
EXT_SYNC_SEL
Sample sync select.
00: use the internal 32 kHz clock with FSAMPLE to select sample
timings.
01: use the GPIO0 pin to trigger sample cycle.
10: use the GPIO1 pin to trigger sample cycle.
11: reserved.
1
0x0
R/W
R/W
R/W
R/W
GPIO0_IE
Reserved
Reserved
GPIO1_CTRL
GPIO0 pin input enable.
Write 0x0.
0
0x0
0x50
[15:7]
6
0x000
0x0
Write 0x000.
Controls the GPIO1 output when the GPIO1 output is enabled
(GPIO1_OE = 0x1).
0x0: GPIO1 output driven low.
0x1: GPIO1 output driven by the AFE power-down signal.
5
0x0
R/W
R/W
CLK32M_CAL_EN
As part of the 32 MHz clock calibration routine, write 1 to begin the
clock ratio calculation. Read the result of this calculation from the
CLK_RATIO bits in Register 0x0A.
Reset this bit to 0 prior to reinitiating the calculation.
[4:0]
[15:3]
2
0x00
Reserved
Write 0x0.
0x5F
0x0000 R/W
0x0 R/W
Reserved
Write 0x0000.
SLOTB_DATA_HOLD
Setting this bit prevents the update of the data registers corresponding
to Time Slot B. Set this bit to ensure that unread data registers are not
updated, guaranteeing a contiguous set of data from all four
photodiode channels.
1: hold data registers for Time Slot B.
0: allow data register update.
Rev. B | Page 58 of 61
Data Sheet
ADPD188GG
Default
Value
Address Data Bit
Access
Name
Description
1
0x0
R/W
SLOTA_DATA_HOLD
Setting this bit prevents the update of the data registers corresponding
to Time Slot A. Set this bit to ensure that unread data registers are not
updated, guaranteeing a contiguous set of data from all four
photodiode channels.
1: hold data registers for Time Slot A.
0: allow data register update.
0
0x0
R/W
DIGITAL_CLOCK_ENA
Set to 1 in order to enable the 32 MHz clock when calibrating the
32 MHz clock. Always disable the 32 MHz clock following the
calibration by resetting this bit to 0.
ADC REGISTERS
Table 33. ADC Registers
Default
Address Data Bits Value
Access Name
Description
0x12
[15:0]
0x0028
R/W
FSAMPLE
Sampling frequency: fSAMPLE = 32 kHz/(Register 0x12, Bits[15:0] × 4).
For example, 100 Hz = 0x0050; 200 Hz = 0x0028.
Write 0x0.
0x15
[15:11]
[10:8]
0x00
0x6
R/W
R/W
Reserved
SLOTB_NUM_AVG
Sample sum/average for Time Slot B. Specifies the averaging factor,
NB, which is the number of consecutive samples that is summed and
averaged after the ADC. Register 0x70 to Register 0x7F hold the data
sum. Register 0x64 to Register 0x6B and the data buffer in Register 0x60
hold the data average, which can be used to increase SNR without
clipping, in 16-bit registers. The data rate is decimated by the value
of the SLOTB_NUMB_AVG bits.
0: 1.
1: 2.
2: 4.
3: 8.
4: 16.
5: 32.
6: 64.
7: 128.
Write 0x0.
7
0x0
0x0
R/W
R/W
Reserved
[6:4]
SLOTA_NUM_AVG
Sample sum/average for Time Slot A. NA: same as Bits[10:8] but for
Time Slot A. See description in Register 0x15, Bits[10:8].
[3:0]
0x0
R/W
R/W
Reserved
Write 0x0.
0x18
0x19
0x1A
0x1B
0x1E
0x1F
0x20
0x21
[15:0]
0x2000
SLOTA_CH1_OFFSET Time Slot A Channel 1 ADC offset. The value to subtract from the
raw ADC value. A value of 0x2000 is typical.
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
0x2000
0x2000
0x2000
0x2000
0x2000
0x2000
0x2000
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SLOTA_CH2_OFFSET Time Slot A Channel 2 ADC offset. The value to subtract from the
raw ADC value. A value of 0x2000 is typical.
SLOTA_CH3_OFFSET Time Slot A Channel 3 ADC offset. The value to subtract from the
raw ADC value. A value of 0x2000 is typical.
SLOTA_CH4_OFFSET Time Slot A Channel 4 ADC offset. The value to subtract from the
raw ADC value. A value of 0x2000 is typical.
SLOTB_CH1_OFFSET Time Slot B Channel 1 ADC offset. The value to subtract from the
raw ADC value. A value of 0x2000 is typical.
SLOTB_CH2_OFFSET Time Slot B Channel 2 ADC offset. The value to subtract from the
raw ADC value. A value of 0x2000 is typical.
SLOTB_CH3_OFFSET Time Slot B Channel 3 ADC offset. The value to subtract from the
raw ADC value. A value of 0x2000 is typical.
SLOTB_CH4_OFFSET Time Slot B Channel 4 ADC offset. The value to subtract from the
raw ADC value. A value of 0x2000 is typical.
Rev. B | Page 59 of 61
ADPD188GG
Data Sheet
DATA REGISTERS
Table 34. Data Registers
Address
0x60
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
Data Bits
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
Access
Name
Description
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
FIFO_DATA
Next available word in FIFO.
SLOTA_CH1_16BIT
SLOTA_CH2_16BIT
SLOTA_CH3_16BIT
SLOTA_CH4_16BIT
SLOTB_CH1_16BIT
SLOTB_CH2_16BIT
SLOTB_CH3_16BIT
SLOTB_CH4_16BIT
SLOTA_CH1_LOW
SLOTA_CH2_LOW
SLOTA_CH3_LOW
SLOTA_CH4_LOW
SLOTA_CH1_HIGH
SLOTA_CH2_HIGH
SLOTA_CH3_HIGH
SLOTA_CH4_HIGH
SLOTB_CH1_LOW
SLOTB_CH2_LOW
SLOTB_CH3_LOW
SLOTB_CH4_LOW
SLOTB_CH1_HIGH
SLOTB_CH2_HIGH
SLOTB_CH3_HIGH
SLOTB_CH4_HIGH
16-bit value of Channel1 in Time Slot A.
16-bit value of Channel 2 in Time Slot A.
16-bit value of Channel 3 in Time Slot A.
16-bit value of Channel 4 in Time Slot A.
16-bit value of Channel 1 in Time Slot B.
16-bit value of Channel 2 in Time Slot B.
16-bit value of Channel 3 in Time Slot B.
16-bit value of Channel 4 in Time Slot B.
Low data-word for Channel 1 in Time Slot A.
Low data-word for Channel 2 in Time Slot A.
Low data-word for Channel 3 in Time Slot A.
Low data-word for Channel 4 in Time Slot A.
High data-word for Channel 1 in Time Slot A.
High data-word for Channel 2 in Time Slot A.
High data-word for Channel 3 in Time Slot A.
High data-word for Channel 4 in Time Slot A.
Low data-word for Channel 1 in Time Slot B.
Low data-word for Channel 2 in Time Slot B.
Low data-word for Channel 3 in Time Slot B.
Low data-word for Channel 4 in Time Slot B.
High data-word for Channel 1 in Time Slot B.
High data-word for Channel 2 in Time Slot B.
High data-word for Channel 3 in Time Slot B.
High data-word for Channel 4 in Time Slot B.
Rev. B | Page 60 of 61
Data Sheet
ADPD188GG
OUTLINE DIMENSIONS
3.90
3.80
3.70
0.30
0.25
0.20
PIN 1
INDEX AREA
0.45
0.40
0.35
PIN 1
INDEX AREA
20
24
5.10
5.00
4.90
19
1
2.42
BSC
0.87
REF
3.00
REF
0.50
BSC
1.68
REF
2.20
BSC
13
7
1.00
BSC
12
8
TOP VIEW
3.13 BSC
BOTTOM VIEW
1.60
BSC
0.10
2.00
REF
1.00
0.90
0.80
0.70 BSC
END VIEW
0.20 BSC
COPLANARITY
0.08
SEATING
PLANE
Figure 41. 24-Terminal Chip Array Small Outline No Lead Cavity [LGA_CAV]
3.80 mm × 5.00 mm Body and 0.9 mm Package Height
(CE-24-1)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Package
Model1, 2
Package Description
Option
CE-24-1
CE-24-1
ADPD188GG-ACEZR7
ADPD188GG-ACEZRL
EVAL-ADPD188GGZ
−40°C to +85°C
−40°C to +85°C
24-Terminal Chip Array Small Outline No Lead Cavity [LGA_CAV], 7” Tape and Reel
24-Terminal Chip Array Small Outline No Lead Cavity [LGA_CAV], 13” Tape and Reel
Evaluation Board
1 Z = RoHS Compliant Part.
2 EVAL-ADPDUCZ is the microcontroller board, ordered separately, required to interface with the EVAL-ADPD188GGZ evaluation board.
©2018–2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16111-4/20(B)
Rev. B | Page 61 of 61
相关型号:
©2020 ICPDF网 联系我们和版权申明