ADPD4101BCBZR7_技术文档

Multimodal Sensor Front End

Data Sheet

ADPD4100/ADPD4101

FEATURES

GENERAL DESCRIPTION

Multimodal analog front end

8 input channels with multiple operation modes for various

sensor measurements

The ADPD4100/ADPD4101 operate as a complete multimodal

sensor front end, stimulating up to eight light emitting diodes

(LEDs) and measuring the return signal on up to eight separate

current inputs. Twelve time slots are available, enabling 12 separate

measurements per sampling period.

The data output and functional configuration utilize an I²C

interface on the ADPD4101 or a serial port interface (SPI) on

the ADPD4100. The control circuitry includes flexible LED

signaling and synchronous detection. The devices use a 1.8 V

analog core and 1.8 V/3.3 V compatible digital input/output (I/O).

Dual-channel processing with simultaneous sampling

12 programmable time slots for synchronized sensor

measurements

Flexible input multiplexing to support differential and

single-ended sensor measurements

8 LED drivers, 4 of which can be driven simultaneously

Flexible sampling rate from 0.004 Hz to 9 kHz using internal

oscillators

On-chip digital filtering

The analog front end (AFE) rejects signal offsets and corruption

from asynchronous modulated interference, typically from

ambient light, eliminating the need for optical filters or externally

controlled dc cancellation circuitry. Multiple operating modes

are provided, enabling the ADPD4100/ADPD4101 to be a sensor

hub for synchronous measurements of photodiodes, biopotential

electrodes, resistance, capacitance, and temperature sensors. The

multiple operation modes accommodate various sensor measure-

ments, including, but not limited to, photoplethysmography

(PPG), electrocardiography (ECG), electrodermal activity

(EDA), impedance, capacitance, temperature, gas detection,

smoke detection, and aerosol detection for various healthcare,

industrial, and consumer applications.

SNR of transmit and receive signal chain: 100 dB

AC ambient light rejection: 60 dB up to 1 kHz

400 mA total LED peak drive current

Total system power dissipation: 30 µW (combined LED and

AFE power), continuous PPG measurement at 75 dB SNR,

25 Hz ODR, 100 nA/mA CTR

SPI and I²C communications supported

512-byte FIFO size

APPLICATIONS

Wearable health and fitness monitors: heart rate monitors

(HRMs), heart rate variability (HRV), stress, blood pressure

estimation, SpO₂, hydration, body composition

Industrial monitoring: CO, CO₂, smoke, and aerosol detection

Home patient monitoring

The ADPD4100/ADPD4101 are available in a 3.11 mm ×

2.14 mm, 0.4 mm pitch, 33-ball WLCSP and 35-ball WLCSP.

FUNCTIONAL BLOCK DIAGRAM

AVDD

DVDD1

DVDD2

IOVDD

ADPD4100/ADPD4101

LED4B

LED3B

LED LEVEL

LED2B

LED1B

LED4A

LED3A

LED2A

LED1A

AND

MUX CONTROL

LED

AGND

DGND

IOGND

DRIVERS

HIGH

FREQUENCY

AND LOW

FREQUENCY

OSCILLATORS

CS

SCLK

MOSI

MISO

LGND

DIGITAL PROCESSING,

INTERFACE AND

INTEGRATOR

TIMING

TIMING CONTROL,

FIFO, PROGRAM AND

DATA REGISTERS,

COMMUNICATIONS

SCL

SDA

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

CH 1 SIGNAL

CONDITIONING

ADC

GPIO0

GPIO1

GPIO2

GPIO3

TIA_VREF

CH 2 SIGNAL

CONDITIONING

VREF

VC1

INTEGRATOR

TIMING

VC1

VC2

VOLTAGE

REFERENCES

VREF

VC2

TIA_VREF

NOTES

V

ICM

1. CS, SCLK, MOSI, AND MISO PINS ARE ON THE ADPD4100.

2. SCL AND SDA PINS ARE ON THE ADPD4101.

3. TIA_VREF IS THE INTERNAL VOLTAGE REFERENCE SIGNAL FOR THE TRANSIMPEDANCE AMPLIFIER.

Figure 1.

Rev. 0

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Tel: 781.329.4700

Technical Support

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ADPD4100/ADPD4101

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Time Slot Operation .................................................................. 23

Execution Modes........................................................................ 24

Host Interface.............................................................................. 24

Applications Information.............................................................. 28

Operating Mode Overview ....................................................... 28

Analog Integration Mode.......................................................... 28

Digital Integration Mode........................................................... 40

TIA ADC Mode.......................................................................... 42

Protecting Against TIA Saturation in Normal Operation .... 42

ECG Measurement with the ADPD4100/ADPD4101 .......... 44

Register Map ................................................................................... 51

Register Details ............................................................................... 70

Global Configuration Registers................................................ 70

Interrupt Status and Control Registers.................................... 72

Threshold Setup and Control Registers .................................. 82

Clock and Timestamp Setup and Control Registers.............. 84

System Registers ......................................................................... 84

I/O Setup and Control Registers .............................................. 86

Time Slot Configuration Registers........................................... 89

AFE Timing Setup Registers..................................................... 94

LED Control and Timing Registers ......................................... 96

ADC Offset Registers................................................................. 97

Output Data Registers ............................................................... 97

Outline Dimensions..................................................................... 100

Ordering Guide ........................................................................ 101

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Temperature and Power Specifications ..................................... 3

Performance Specifications......................................................... 4

Digital Specifications ................................................................... 6

Timing Specifications .................................................................. 6

Absolute Maximum Ratings............................................................ 9

Thermal Resistance ...................................................................... 9

Electrostatic Discharge (ESD) Ratings ...................................... 9

ESD Caution.................................................................................. 9

Pin Configurations and Function Descriptions ......................... 10

Typical Performance Characteristics ........................................... 13

Theory of Operation ...................................................................... 15

Introduction ................................................................................ 15

Analog Signal Path ..................................................................... 15

LED Drivers ................................................................................ 16

Determining C_VLED...................................................................... 17

Datapath, Decimation, Subsampling, and FIFO.................... 18

Clocking....................................................................................... 21

Time Stamp Operation .............................................................. 22

Low Frequency Oscillator Calibration .................................... 22

High Frequency Oscillator Calibration ................................... 22

REVISION HISTORY

6/2020—Revision 0: Initial Version

Rev. 0 | Page 2 of 101

Data Sheet

ADPD4100/ADPD4101

SPECIFICATIONS

TEMPERATURE AND POWER SPECIFICATIONS

Table 1. Operating Conditions

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

TEMPERATURE RANGE

Operating

Storage

−40

−65

+85

+150

°C

POWER SUPPLY VOLTAGE

Supply, V_DD

Input/Output Driver Supply, IOV_DD

Applied at the AVDD, DVDD1, and DVDD2 pins

Applied at the IOVDD pin

1.7

1.8

1.9

3.6

V

AVDD = DVDDx = IOVDD = 1.8 V, T_A= 25°C, unless otherwise noted.

Table 2. Current Consumption

Parameter

Symbol

Test Conditions/Comments

Min Typ Max Unit

POWER SUPPLY (V_DD)

CURRENT

V_DDSupply Current¹

Signal-to-noise ratio (SNR) = 75 dB, 25 Hz output data rate (ODR),

single time slot, 1 MHz low frequency oscillator frequency

SNR = 75 dB, 25 Hz ODR, single time slot, 32 kHz low frequency

oscillator frequency

Combined LED and AFE power, continuous PPG measurement at

75 dB SNR, 25 Hz ODR, 100 nA/mA current transfer ratio (CTR),

1 MHz low frequency oscillator frequency

10

8

µA

μW

Total System Power

Dissipation

30

Combined LED and AFE power, continuous PPG measurement at

75 dB SNR, 25 Hz ODR, 100 nA/mA CTR, 32 kHz low frequency

oscillator frequency

26

μW

Peak V_DDSupply Current

(1.8 V)

1-Channel Operation

Standby Mode Current

IV_DD__PEAK

IV_DD__STANDBY

Peak V_DDcurrent during time slot sampling

3.8

0.20

mA

µA

¹V_DDis the voltage applied at the AVDD and DVDDx pins.

Rev. 0 | Page 3 of 101

ADPD4100/ADPD4101

Data Sheet

PERFORMANCE SPECIFICATIONS

AVDD = DVDDx = IOVDD = 1.8 V, T_A= full operating temperature range, unless otherwise noted.

Table 3.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

DATA ACQUISITION

Datapath Width

32

Bits

FIRST IN, FIRST OUT (FIFO) SIZE

LED DRIVER

512

Bytes

LED Peak Current per Driver

LED Peak Current, Total

Driver Compliance Voltage

LEDxx Pin Voltage¹

LED pulse enabled

Using multiple LED drivers simultaneously

For any LED driver output at LED_CURRENTx_x = 0x7F

1.5

200

400

300

3.6

mA

mV

V

mA

µs

Highest LED Peak Current per Driver²

For any LED driver at LED_CURRENTx_x = 0x7F

AFE width = 4 µs³

176

11

200

208

LED PERIOD

AFE width = 3 µs

9

µs

SAMPLING RATE⁴

OSCILLATOR DRIFT

32 kHz Oscillator

Single time slot, four data bytes to FIFO, 2 µs LED pulse

0.004

9000 Hz

Percent variation from 25°C to 85°C

Percent variation from +25°C to −40°C

Percent variation from 25°C to 85°C

Percent variation from +25°C to −40°C

Percent Variation from 25°C to 85°C

Percent Variation from +25°C to −40°C

6

−8.5

3

−4

1

−1.5

%

1 MHz Oscillator

32 MHz Oscillator

¹LEDxx refers to LED1A, LED2A, LED3A, LED4A, LED1B, LED2B, LED3B, and LED4B.

²The maximum value in this specification is the maximum value at LED driver current setting = 0x7F on LED Driver LED1A, and the minimum value in this specification

is the minimum value at LED driver current setting = 0x7F on LED Driver LED4B. Typically, the LED peak current is the highest on LED1A and the lowest on LED4B,

while the rest of the drivers fall in between, and the LED peak current of the LEDxA drivers are higher than that of LEDxB drivers of the same number. For example, the

LED peak current of LED3A is higher than that of LED3B.

³Minimum LED period = (2 × AFE width) + 3 µs.

⁴The maximum value in this specification is the internal ADC sampling rate using the internal 1 MHz state machine clock. The I²C and SPI read rates in some

configurations may limit the ODR.

Table 4.

Parameter

Test Conditions/Comments

Min Typ Max Unit

TRANSIMPEDANCE AMPLIFIER (TIA) GAIN

12.5

200

kΩ

PULSED SIGNAL CONVERSIONS, 3 μs LED

PULSE

ADC Resolution¹

4 μs integration width, continuous connect mode

TIA feedback resistor

12.5 kΩ

6.2

3.1

1.5

0.77

0.38

nA/LSB

25 kΩ

50 kΩ

100 kΩ

200 kΩ

TIA feedback resistor

12.5 kΩ

ADC Saturation Level²

50

25

12.5

6.22

3.11

μA

25 kΩ

50 kΩ

100 kΩ

200 kΩ

Rev. 0 | Page 4 of 101

Data Sheet

ADPD4100/ADPD4101

Parameter

Test Conditions/Comments

Min Typ Max Unit

PULSED SIGNAL CONVERSIONS, 2 μs LED

PULSE

ADC Resolution¹

3 μs integration width, continuous connect mode

TIA feedback resistor

12.5 kΩ

8.2

4.1

2.04

1.02

0.51

nA/LSB

25 kΩ

50 kΩ

100 kΩ

200 kΩ

TIA feedback resistor

12.5 kΩ

ADC Saturation Level²

67

33

16.7

8.37

4.19

μA

25 kΩ

50 kΩ

100 kΩ

200 kΩ

FULL SIGNAL CONVERSIONS

TIA Linear Dynamic Range (per Channel)

Total input current, 1% compression point, TIA_VREF = 1.265 V

12.5 kΩ

25 kΩ

50 kΩ

100 kΩ

200 kΩ

72

38

18.7

9.3

4.6

μA

SYSTEM PERFORMANCE

Referred to Input Noise

Continuous connect mode, single pulse, single channel,

floating input, TIA_VREF = 1.265 V, 3 μs integration time

12.5 kΩ TIA gain

25 kΩ TIA gain

50 kΩ TIA gain

100 kΩ TIA gain

200 kΩ TIA gain

8.2

4.1

2.2

1.2

0.61

nA rms

Referred to Input Noise

Continuous connect mode, single pulse, single channel, 90%

full-scale input signal, no ambient light, TIA_VREF = 1.265 V,

VCx = TIA_VREF + 215 mV, 2 μs LED pulse, photodiode

capacitance (C_PD) = 70 pF, input resistor = 500 Ω

12.5 kΩ TIA gain

25 kΩ TIA gain

50 kΩ TIA gain

100 kΩ TIA gain

10.3

5.3

2.7

1.5

0.97

76

75

74

72

nA rms

dB

200 kΩ TIA gain

SNR

12.5 kΩ TIA gain, single pulse

25 kΩ TIA gain, single pulse

50 kΩ TIA gain, single pulse

100 kΩ TIA gain, single pulse

200 kΩ TIA gain, single pulse

100 kΩ TIA gain, 100 Hz ODR, 80 pulses, C_PD= 70 pF, 0.5 Hz to

20 Hz bandwidth, transmit and receive signal chain

100

dB

AC Ambient Light Rejection

DC to 1 kHz, linear range of TIA, TIA gain = 25 kΩ, 50 kΩ,

100 kΩ, 200 kΩ

60

dB

DC to 1 kHz, linear range of TIA, TIA gain = 12.5 kΩ

DC Power Supply Rejection Ratio (PSRR) At 75% full scale input

55

50

dB

¹ADC resolution is listed per pulse. If using multiple pulses, divide by the number of pulses.

²ADC saturation level applies to pulsed signal only, because ambient signal is rejected prior to ADC conversion.

Rev. 0 | Page 5 of 101

ADPD4100/ADPD4101

Data Sheet

DIGITAL SPECIFICATIONS

IOVDD = 1.7 V to 3.6 V, unless otherwise noted.

Table 5. Digital Specifications

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

LOGIC INPUTS

Input Voltage Level

SCL, SDA

High

Low

V_IH

V_IL

0.7 × IOVDD

−0.3

3.6

V

+0.3 × IOVDD

GPIOx, MISO, MOSI, SCLK, CS

High

V_IH

V_IL

0.7 × IOVDD

−0.3

IOVDD + 0.3

+0.3 × IOVDD

V

Low

Input Current Level

High

All logic inputs

I_IH

I_IL

C_IN

10

µA

pF

Low

−10

Input Capacitance

LOGIC OUTPUTS

Output Voltage Level

GPIOx, MISO

High

Low

SDA

Low

Output Current Level

Low

2

V_OH

V_OL

2 mA high level output current

2 mA low level output current

IOVDD – 0.5

V

0.5

0.4

V_OL1

I_OL

3 mA low level output current

SDA

V_OL1= 0.4 V

V

20

mA

TIMING SPECIFICATIONS

Table 6. I²C Timing Specifications for the ADPD4101

Parameter

TIMING REQUIREMENTS

I²C Port¹

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

See Figure 2

SCL

Frequency

1

Mbps

Minimum Pulse Width

High

Low

t₁

t₂

260

500

ns

Start Condition

Hold Time

Setup Time

SDA

t₃

t₄

260

ns

Hold Time²

Setup Time

SCL and SDA

Rise Time

t₅

t₆

0

50

ns

t₇

t₈

120

ns

Fall Time

Stop Condition

Setup Time

t₉

260

ns

¹Guaranteed by design.

²Both timing requirement and switching characteristic.

Rev. 0 | Page 6 of 101

Data Sheet

ADPD4100/ADPD4101

Table 7. SPI Timing Specifications for the ADPD4100

Parameter

TIMING REQUIREMENTS

SPI Port

Symbol

Test Conditions/Comments

Min Typ Max Unit

SCLK

Frequency

f_SCLK

24

MHz

Minimum Pulse Width

High

Low

t_SCLKPWH

t_SCLKPWL

15

ns

CS

Setup Time

t_CS

CS setup to SCLK rising edge

CS hold from SCLK rising edge

CS pulse width high

11

5

ns

S

Hold Time

t_CS

H

Pulse Width High

t_CS

15

PWH

MOSI

Setup Time

Hold Time

t_MOSIS

t_MOSIH

MOSI setup to SCLK rising edge

MOSI hold from SCLK rising edge

5

ns

SWITCHING CHARACTERISTICS

MISO Output Delay

t_MISOD

MISO valid output delay from SCLK falling edge

Register 0x00B4 = 0x0050 (default)

21.5 ns

14.0 ns

Register 0x00B4 = 0x005F (maximum slew rate,

maximum drive strength for SPI)

Table 8. Timing Specifications for Provision of External Low Frequency Oscillator

Parameter

Min

Typ

Max

Unit

FREQUENCY

1 MHz Low Frequency Oscillator

32 kHz Low Frequency Oscillator

DUTY CYCLE

500

10

2000

100

kHz

1 MHz Low Frequency Oscillator

32 kHz Low Frequency Oscillator

10

90

%

Rev. 0 | Page 7 of 101

ADPD4100/ADPD4101

Data Sheet

Timing Diagrams

t₆

t₃

SDA

SCL

t₅

t₁

t₇

t₂

t₈

t₄

t₉

Figure 2. I²C Timing Diagram for the ADPD4101

t_CSH

t_CSS

t_CSPWH

t_SCLKPWL

t_SCLKPWH

CS

SCLK

MOSI

t_MOSIH

t_MOSIS

MISO

t_MISOD

Figure 3. SPI Timing Diagram for the ADPD4100

Rev. 0 | Page 8 of 101

Data Sheet

ADPD4100/ADPD4101

ABSOLUTE MAXIMUM RATINGS

Table 9.

ELECTROSTATIC DISCHARGE (ESD) RATINGS

Parameter

Rating

The following ESD information is provided for handling of ESD

sensitive devices in an ESD protected area only.

AVDD to AGND

DVDD1, DVDD2 to DGND

IOVDD to DGND

GPIOx, MOSI, MISO, SCLK, CS, SCL,

SDA to DGND

LEDxx to LGND

−0.3 V to +2.2 V

−0.3 V to +3.9 V

Human body model (HBM) per ANSI/ESDA/JEDEC JS-001 and

charged device model (CDM) per ANSI/ESDA/JEDEC JS-002.

Machine model (MM) per ANSI/ESD STM5.2. MM voltage

values are for characterization only.

−0.3 V to +3.9 V

150°C

Junction Temperature

ESD Ratings for ADPD4100/ADPD4101

Table 11. ADPD4100/ADPD4101, 35-Ball and 33-Ball WLCSP

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

ESD Model

Withstand Threshold (V)

Class

HBM

CDM

MM

2000

1250

100

2

C3

Not applicable

ESD CAUTION

THERMAL RESISTANCE

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Close attention to

PCB thermal design is required.

θ_JAis the natural convection junction to ambient thermal

resistance measured in a one cubic foot sealed enclosure. θ_JCis

the junction to case thermal resistance.

Table 10. Thermal Resistance

Package Type¹

CB-35-2

θ_JA

θ_JC

Unit

°C/W

41.89

42.15

0.98

CB-33-1

¹The thermal resistance values are defined as per the JESD51-12 standard.

Rev. 0 | Page 9 of 101

ADPD4100/ADPD4101

Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

ADPD4100

BOTTOM VIEW, BALL SIDE UP

(Not to Scale)

5

4

3

2

1

A

B

C

D

E

F

LED1A

LED2A

LED3A

LED4A

LED4B

LED3B

SCLK

CS

GPIO2

MISO

MOSI

DVDD1

IN7

LED2B

GPIO3

IOVDD

IOGND

IN3

LGND

GPIO0

LED1B

GPIO1

DVDD2

AGND

AVDD

VREF

VC1

DGND

IN5

IN1

IN2

IN6

IN8

G

VC2

IN4

Figure 4. ADPD4100 Pin Configuration

Table 12. ADPD4100 Pin Function Descriptions

Pin No. Mnemonic Type¹Description

A5

A4

A3

A2

A1

B5

B4

B3

B2

B1

C5

C4

C3

C2

C1

D5

D4

D3

D2

D1

E5

E4

E3

E2

E1

F5

F4

F3

LED1A

LED2A

LED3A

LED4A

LED4B

LGND

LED1B

LED2B

LED3B

GPIO2

GPIO0

GPIO1

GPIO3

SCLK

AO

S

AO

DIO

DI

LED Driver 1A Current Sink. If not in use, leave this pin floating.

LED Driver 2A Current Sink. If not in use, leave this pin floating.

LED Driver 3A Current Sink. If not in use, leave this pin floating.

LED Driver 4A Current Sink. If not in use, leave this pin floating.

LED Driver 4B Current Sink. If not in use, leave this pin floating.

LED Driver Ground.

LED Driver 1B Current Sink. If not in use, leave this pin floating.

LED Driver 2B Current Sink. If not in use, leave this pin floating.

LED Driver 3B Current Sink. If not in use, leave this pin floating.

General-Purpose I/O 2. This pin is used for interrupts and various clocking options.

General-Purpose I/O 0. This pin is used for interrupts and various clocking options.

General-Purpose I/O 1. This pin is used for interrupts and various clocking options.

General-Purpose I/O 3. This pin is used for interrupts and various clocking options.

SPI Clock Input.

MISO

AVDD

DVDD2

IOVDD

CS

DO

S

DI

SPI Master Input/Slave Output.

1.8 V Analog Supply.

1.8 V Digital Supply.

1.8 V/3.3 V I/O Driver Supply.

SPI Chip Select Input.

MOSI

VREF

DI

REF

S

AO

AI

SPI Master Output/Slave Input.

Internally Generated ADC Voltage Reference. Buffer this pin with a 1 µF capacitor to AGND.

Analog Ground.

I/O Driver Ground.

Digital Ground.

1.8 V Digital Supply.

Output Voltage Source 1 for Photodiode Common Cathode Bias or Other Sensor Stimulus.

Current Input 1. If not in use, leave this pin floating.

Current Input 3. If not in use, leave this pin floating.

AGND

IOGND

DGND

DVDD1

VC1

IN1

IN3

AI

Rev. 0 | Page 10 of 101

Data Sheet

ADPD4100/ADPD4101

Pin No. Mnemonic Type¹Description

F2

F1

IN5

IN7

VC2

IN2

IN4

IN6

IN8

AI

AO

AI

Current Input 5. If not in use, leave this pin floating.

Current Input 7. If not in use, leave this pin floating.

Output Voltage Source 2 for Photodiode Common Cathode Bias or Other Sensor Stimulus.

Current Input 2. If not in use, leave this pin floating.

Current Input 4. If not in use, leave this pin floating.

Current Input 6. If not in use, leave this pin floating.

G5

G4

G3

G2

G1

Current Input 8. If not in use, leave this pin floating.

¹AO means analog output, S means supply, DIO means digital input/output, DI means digital input, DO means digital output, REF means voltage reference, and AI

means analog input.

ADPD4101

BOTTOM VIEW, BALL SIDE UP

(Not to Scale)

5

4

3

2

1

A

B

C

D

E

F

LED1A

LED2A

LED3A

LED4A

LED4B

LED3B

SDA

GPIO2

SCL

LED2B

GPIO3

IOVDD

IOGND

IN3

LGND

GPIO0

LED1B

GPIO1

DVDD2

AGND

AVDD

VREF

VC1

DGND

IN5

DVDD1

IN7

IN1

IN2

IN6

IN8

G

VC2

IN4

Figure 5. ADPD4101 Pin Configuration

Table 13. ADPD4101 Pin Function Descriptions

Pin No.

A5

A4

A3

A2

A1

B5

Mnemonic

LED1A

LED2A

LED3A

LED4A

LED4B

LGND

Type¹

AO

S

Description

LED Driver 1A Current Sink. If not in use, leave this pin floating.

LED Driver 2A Current Sink. If not in use, leave this pin floating.

LED Driver 3A Current Sink. If not in use, leave this pin floating.

LED Driver 4A Current Sink. If not in use, leave this pin floating.

LED Driver 4B Current Sink. If not in use, leave this pin floating.

LED Driver Ground.

B4

B3

B2

B1

C5

C4

C3

C2

C1

D5

D4

D3

E5

LED1B

LED2B

LED3B

GPIO2

GPIO0

GPIO1

GPIO3

SDA

AO

DIO

DI

S

REF

S

LED Driver 1B Current Sink. If not in use, leave this pin floating.

LED Driver 2B Current Sink. If not in use, leave this pin floating.

LED Driver 3B Current Sink. If not in use, leave this pin floating.

General-Purpose I/O 2. This pin is used for interrupts and various clocking options.

General-Purpose I/O 0. This pin is used for interrupts and various clocking options.

General-Purpose I/O 1. This pin is used for interrupts and various clocking options.

General-Purpose I/O 3. This pin is used for interrupts and various clocking options.

I²C Data Input/Output.

SCL

I²C Clock Input.

AVDD

DVDD2

IOVDD

VREF

1.8 V Analog Supply.

1.8 V Digital Supply.

1.8 V/3.3 V I/O Driver Supply.

Internally Generated ADC Voltage Reference. Buffer this pin with a 1 µF capacitor to AGND.

Analog Ground.

E4

AGND

Rev. 0 | Page 11 of 101

ADPD4100/ADPD4101

Data Sheet

Pin No.

E3

E2

E1

F5

Mnemonic

IOGND

DGND

DVDD1

VC1

Type¹

S

AO

AI

Description

I/O Driver Ground.

Digital Ground.

1.8 V Digital Supply.

Output Voltage Source 1 for Photodiode Common Cathode Bias or Other Sensor Stimulus.

Current Input 1. If not in use, leave this pin floating.

F4

IN1

F3

IN3

AI

Current Input 3. If not in use, leave this pin floating.

F2

IN5

AI

Current Input 5. If not in use, leave this pin floating.

F1

IN7

AI

Current Input 7. If not in use, leave this pin floating.

G5

G4

G3

G2

G1

VC2

IN2

IN4

IN6

AO

AI

Output Voltage Source 2 for Photodiode Common Cathode Bias or Other Sensor Stimulus.

Current Input 2. If not in use, leave this pin floating.

Current Input 4. If not in use, leave this pin floating.

Current Input 6. If not in use, leave this pin floating.

Current Input 8. If not in use, leave this pin floating.

IN8

¹AO means analog output, S means supply, DIO means digital input/output, DI means digital input, DO means digital output, REF means voltage reference, and AI

means analog input.

Rev. 0 | Page 12 of 101

Data Sheet

ADPD4100/ADPD4101

TYPICAL PERFORMANCE CHARACTERISTICS

0.20

9

0.18

8

7

6

5

4

3

2

1

0

12.5kΩ GAIN

25kΩ GAIN

50kΩ GAIN

100kΩ GAIN

200kΩ GAIN

LED_CURRENT1_x 0x7 = 10mA

LED_CURRENT1_x 0x19 = 40mA

LED_CURRENT1_x 0x4A = 120mA

LED_CURRENT1_x 0x7F = 200mA

0.16

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0

100 200 300 400 500 600 700 800 900 1000

INPUT CAPACITANCE (pF)

LED1A DRIVER COMPLIANCE (V)

Figure 6. LED Driver Current vs. LED1A Driver Compliance at LED_CURRENT1_x =

0x7 (10 mA), 0x19 (40 mA), 0x4A (120 mA), and 0x7F (200 mA)

Figure 9. Input Referred Noise vs. Input Capacitance,

Integrator Input Resistor = 400 kΩ

0

96

94

92

90

88

86

84

82

80

78

76

–10

–20

–30

–40

–50

200kΩ GAIN

100kΩ GAIN

50kΩ GAIN

–60

1

10

100

1k

10k

100k

1M

1

10

100

FREQUENCY (Hz)

NUMBER OF LED PULSES

Figure 7. AC PSRR vs. Frequency

Figure 10. SNR vs. Number of LED Pulses in Continuous Connect Mode,

_PD= 70 pF, Integrator Input Resistor = 400 kΩ, 90% Full Scale

C

9

10000

1000

100

8

7

6

5

4

3

2

1

0

200kΩ GAIN

100kΩ GAIN

50kΩ GAIN

10

0

20

40

60

80

100 120 140 160 180 200

76

78

80

82

84

86

88

90

92

94

96

TIA GAIN (kΩ)

SNR (dB)

Figure 8. Input Referred Noise vs. TIA Gain, C_PD= 70 pF, Integrator Input

Resistor = 400 kΩ

Figure 11. Total Power Consumption vs SNR in Continuous Connect Mode

Including LED Power, C_PD= 70 pF, Integrator Input Resistor = 400 kΩ, ODR =

25 Hz, CTR = 150 nA/mA, LED Supply Voltage = 4 V, 90% of Full Scale

Rev. 0 | Page 13 of 101

ADPD4100/ADPD4101

Data Sheet

0

–10

–20

–30

–40

–50

–60

–70

160

140

120

100

80

60

40

20

0

1

10

100

1k

10k

100k

FREQUENCY (Hz)

FREQUENCY (MHz)

Figure 12. Ambient Light Rejection vs. Frequency

Figure 14. 1 MHz Clock Frequency Distribution, Untrimmed

90

200

180

160

140

120

100

80

70

60

50

40

30

20

10

0

60

40

20

0

FREQUENCY (kHz)

FREQUENCY (MHz)

Figure 13. 32 kHz Clock Frequency Distribution, Untrimmed

Figure 15. 32 MHz Clock Frequency Distribution, Untrimmed

Rev. 0 | Page 14 of 101

Data Sheet

ADPD4100/ADPD4101

THEORY OF OPERATION

that require instantaneous sampling of two sensors. Each

channel contains a TIA with programmable gain, a BPF with a

high-pass corner at 100 kHz and a low-pass cutoff frequency of

390 kHz, and an integrator capable of integrating 7.5 pC per

sample. Each channel is time multiplexed into a 14-bit ADC. In

Figure 16, R_Fis the TIA feedback resistor, and R_INTis the series

resistor to the input of the integrator.

INTRODUCTION

The ADPD4100/ADPD4101 operate as a complete multimodal

sensor front end, stimulating up to eight LEDs and measuring

the return signal on up to eight separate current inputs. Twelve

time slots are available, enabling 12 separate measurements per

sampling period. The analog inputs can be driven single-ended

or in differential pairs. The eight analog inputs are multiplexed

into a single channel or two independent channels, enabling

simultaneous sampling of two sensors.

6.3pF

R

F

R

INT

IN1

IN2

IN3

IN4

BPF

TIA

R

The AFE consists of a TIA, band-pass filter (BPF), integrator,

and analog-to-digital converter (ADC). The digital block

provides multiple operating modes, programmable timing, four

general-purpose input/output (GPIO) pins, block averaging,

and a selectable second- through fourth-order cascaded

integrator comb (CIC) filter. Eight independent LED drivers are

provided that can each drive up to 200 mA. Four LED drivers can

be enabled in any time slot and can be programmed from

1.5 mA to 200 mA monotonically, with a 7-bit register setting.

The LED drivers enabled in any time slot can provide a total

combined maximum of 400 mA of LED current.

R

INT

F

6.3pF

ADC

R

IN5

IN6

IN7

IN8

F

R

INT

TIA

BPF

INT

R

F

6.3pF

Figure 16. Analog Signal Path Block Diagram

Analog Input Multiplexer

The ADPD4100/ADPD4101 support eight analog input pins.

Each input can be used as a single-ended input or as part of a

differential pair. Figure 17 shows a single representation of the

input switch matrix, which allows programmable connection to

the two AFE channels. Each pair of inputs has an exact duplicate

of this multiplexer: IN1 and IN2, IN3 and IN4, IN5 and IN6, and

IN7 and IN8. The connections are programmable per time slot.

The core circuitry provides stimulus to the sensors connected

to the inputs of the device and measures the response, storing

the results in discrete data locations. The eight inputs can drive

two simultaneous input channels, either in a single-ended or

differential configuration. Data is read directly by a register or

through a FIFO method. This highly integrated system includes

an analog signal processing block, digital signal processing block,

an I²C communication interface on the ADPD4101 or an SPI

port on the ADPD4100, programmable pulsed LED current

sources, and pulsed voltage sources for sensors that require

voltage excitation.

When making optical measurements, the ADPD4100/ADPD4101

provide 60 dB of ac ambient light rejection using a synchronous

modulation scheme with pulses as short as 1 μs combined with

a BPF. Ambient light rejection is automatic without the need of

external control loops, dc current subtraction, or digital

algorithms.

IN1

TIA

IN2

TIA_VREF

The LED driver is a current sink and is independent from the LED

supply voltage and the LED type. The inputs can be connected

to any sensor that provides currents up to 200 μA. The

ADPD4100/ADPD4101 can also interface with voltage output

sensors with a series resistor placed between the sensor output and

the ADPD4100/ADPD4101 inputs to convert the voltage to a

current. The ADPD4100/ADPD4101 produce a high SNR for

relatively low LED power while greatly reducing the effect of

ambient light on the measured signal.

TIA

THERE ARE FOUR

COPIES OF SWITCH MATRIX.

ONE COPY FOR EACH

INPUT PAIR.

TIA_VREF

ANALOG SIGNAL PATH

*ALL BIAS CONNECTIONS SHOWN ARE ONLY AVAILABLE DURING

SLEEP AND PRECONDITIONING PERIODS. THE SWITCHES TO

THESE BIAS LEVEL ARE OPEN DURING TIME SLOTS WITH THE

RESPECTIVE INPUTS SELECTED.

The ADPD4100/ADPD4101 analog signal path consists of eight

current inputs that can be configured as single-ended or

differential pairs into one of two independent channels. The

two channels can be sampled simultaneously for applications

Figure 17. Analog Input Multiplexer

Rev. 0 | Page 15 of 103

ADPD4100/ADPD4101

Data Sheet

V

LED1

The PAIR12, PAIR34, PAIR56, and PAIR78 bits select whether

the matching input pair is used as two single-ended inputs or as

a differential pair. This selection is valid for all active time slots.

The INP12_x, INP34_x, INP56_x, and INP78_x bits specify

whether the input pair is enabled during the corresponding

time slot and, if enabled, which input is connected to which

AFE channel.

V

LED2

C

VLED

LEDxA

C

VLED

LEDxB

LED_CURRENTx_x

LED_DRIVESIDEx_x

NOTES

The sleep conditions are used for any inputs that are not enabled.

Sleep conditions are determined by the INP_SLEEP_12,

INP_SLEEP_34, INP_SLEEP_56, and INP_SLEEP_78 bits,

which specify the state for the input pairs during sleep and

when the inputs are not active. Inputs are only considered active

during the precondition and pulse regions for time slots where

they are enabled.

C

IS THE BYPASS CAPACITOR.

VLED

Figure 18. Block Diagram of LED Driver Output Pair

The LED driver output pins (LED1A, LED1B, LED2A, LED2B,

LED3A, LED3B, LED4A, and LED4B) have a maximum

allowable pin voltage of 3.6 V. A ny v olt age exposure over this

rating affects the reliability of the device operation and, in

certain circumstances, causes the device to cease proper

operation. The voltage of the LED driver output pins must not

be confused with the supply voltages for the LED themselves.

Preconditioning of the sensor connected to the input is provided to

set the operating point at the input just prior to sampling. There

are several different options for preconditioning determined by

the PRECON_x bits. The PRECON_x bits are provided for each

time slot to specify the precondition for enabled inputs or input

pairs during the corresponding time slot. Preconditioning options

include: float the input(s), VC1, VC2, input common-mode

voltage (V_ICM), TIA_VREF, TIA input, and short the input pair.

The preconditioning time at the start of each time slot is

programmable using the PRE_WIDTH_x bits. The default

preconditioning period is 8 µs.

V

_LEDxis the voltage applied to the anode of the external LED

whereas the LED output driver pin is connected to the cathode

of the external LED. The compliance voltage is the amount of

headroom voltage at the LED driver pin, measured with respect

to ground, required to maintain the programmed LED current

level and is a function of the current required. Figure 6 shows

the typical compliance voltages required at various LED current

settings for LED driver LED1A, and Figure 19 shows the typical

compliance voltages for all the LED drivers at the maximum LED

current setting. Due to internal layout of the LED driver circuitry,

some drivers output more or less current than others at any

given setting. Typically, the LED1A and LED1B drivers are ~3%

higher than the LED4A and LED4B drivers, respectively, with

the 2× and 3× drivers falling somewhere in between. Also, the

LEDxA drivers are ~3% higher than the LEDxB driver of the

same number.

The block diagram in Figure 17 shows all the bias levels that can

be switched into the input connections during sleep and

preconditioning. These connections are not available during the

sampling phase of a time slot in which the input is selected.

Second AFE Channel

The second AFE channel is disabled by default. When disabled,

the three amplifiers (TIA, BPF, and integrator) are automatically

powered down, and no ADC cycles occur for the second

channel. Digital integration and impulse response mode do not

use the second channel.

0.20

0.18

0.16

0.14

0.12

0.10

The second AFE channel can be enabled with the CH2_EN_x

bits on a per time slot basis. When the second channel is

enabled, ADC conversions and the datapath bits of the second

channel operate. When data is being written to the FIFO, the

Channel 2 data is written after the Channel 1 data.

0.08

Channel 2 TIA gain, integrator resistor, and buffer gain (when

in digital integrate or TIA ADC mode) are set separately from

Channel 1.

LED4B

LED4A

0.06

LED3B

LED3A

LED2B

LED2A

0.04

0.02

0

LED1B

LED1A

LED DRIVERS

The ADPD4100/ADPD4101 have four LED drivers, each of

which is brought out to two LED driver outputs providing a

total of eight LED output drivers. The device can drive up to four

LEDs simultaneously, one from each driver pair. The LED output

driver is a current sink. Figure 18 shows an example of a single

LED driver output pair.

0

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

LED DRIVER VOLTAGE (V)

Figure 19. LED Driver Current vs. LED Driver Voltage for LED Drivers (LEDxA,

LEDxB) for LED_CURRENTx_x = 0x7F

Rev. 0 | Page 16 of 101

Data Sheet

ADPD4100/ADPD4101

Either side of each LED driver output pair, but not both, can be

driven in any of the 12 available time slots. Up to four LED

driver outputs can be enabled in any time slot using the LED_

DRIVESIDE1_x, LED_DRIVESIDE2_x, LED_DRIVESIDE3_x,

and LED_DRIVESIDE4_x bits. The current is set on a per

driver, per time slot basis using the LED_CURRENT1_x, LED_

CURRENT2_x, LED_CURRENT3_x, and LED_CURRENT4_x

bits. Each driver can be programmed from 1.5 mA to 200 mA

with a monotonic 7-bit setting, as shown in Figure 20. Each

setting from 1 to 127 increases the LED drive current by ~1.5 mA.

Setting LED_CURRENTx_x = 0 disables that particular driver.

LED Driver Protection from LED Driver Pin Overvoltage

In typical designs, no external components are needed on the

LED driver. However, in some cases where the LED driver pin

voltage has the possibility to be pulled above 3.6 V, an external

NPN bipolar junction transistor (BJT) type transistor can be

connected to the LED driver pin, as shown in Figure 21. This

additional transistor serves as a protection of the LED driver

pin from exceeding the maximum allowable LEDxx pin voltage

of 3.6 V.

Protecting the LED driver pins from overvoltage is required

when (V_LEDx− LED turn on voltage) > 3.6 V, or when the

voltage source has a shunt resistance of less than 10 MΩ and the

supply voltage is above 3.6 V. For example, V_LEDxof 6 V can be

used without pulling the LED driver pins up past 3.6 V for low

leakage LEDs such as some green and blue LEDs. Typically,

when V_LEDx< 6 V, the protection transistor is not necessary.

Although each driver can be programmed to 200 mA and up to

four LED drivers can be enabled in any time slot, there is a

limitation of a total of 400 mA of combined LED driver current

that can be provided in any time slot. It is up to the user to

program the LED drivers such that this 400 mA limit is not

exceeded. If the 400 mA limit is exceeded by the user settings,

priority is given, in the following order, to LED1x, LED2x,

LED3x, and LED4x. For example, if the user settings have

LED1A set to 150 mA, LED2B set to 150 mA, and LED3A set to

150 mA in a single time slot, LED1A and LED2B both provide

150 mA. However, LED3A is limited to 100 mA to maintain the

400 mA total LED drive current limit for the device.

250

V

LED1

C

VLED

V

BASE

LEDxx

200

150

100

NOTES

1. C

2. V

IS THE BYPASS CAPACITOR.

IS THE BASE VOLTAGE.

VLED

BASE

Figure 21. LED Driver Overvoltage Protection Circuit

The NPN BJT selection must follow these guidelines:

•

The current capacity must match the maximum LED

driver current on the LED. The maximum LED driver

current is 200 mA for one LED driver and 400 mA for

multiple LED drivers connected to the same LED.

The voltage rating of the transistor must exceed the supply

being used on the load.

The base emitter voltage must be ≤0.9 V at the maximum

LED driver current on the LED.

Lower collector emitter voltages at the maximum LED

driver current on the LED provide more operating room

for the load being driven.

50

0

•

0

16

32

48

64

80

96

112

LED_CURRENTx_x SETTING

Figure 20. LED Driver Current vs. LED_CURRENTx_x Setting

LED Driver Protection from High Inductance

If the total inductance in the path between the LED and the

ADPD4100/ADPD4101 LED driver pin (LEDxA or LEDxB)

and in the path between the LED and the LED supply voltage

(V_LEDx) is significant due to the use of long wires and multiple

connectors, connect a reverse biased protection diode to a

suitable high supply voltage such as V_LEDxat the LED driver pin

used. That is, connect a reverse biased protection diode

DETERMINING C_VLED

To determine the bypass capacitor (C_VLED) value, determine the

maximum forward-biased voltage, V_{FB_LED_MAX}, of the LED in

operation. The maximum LED current, I_{LED_MAX}, converts to

V_{FB_LED_MAX}as shown in Figure 22. In this example, 125 mA of

between the LED driver pin used and V_LEDx

.

current through two green LEDs in parallel yields V_{FB_LED_MAX}

=

3.5 V. Any series resistance in the LED path must also be

included in this voltage. When designing the LED path, keep in

mind that small resistances can add up to large voltage drops

due to the LED peak current being large. In addition, these

resistances can be unnecessary constraints on the V_LEDxsupply.

Rev. 0 | Page 17 of 101

ADPD4100/ADPD4101

Data Sheet

4.5

voltage is the voltage of the anode of the LED such that the compli-

ance of the LED driver and the forward-biased voltage of the

LED operating at the maximum current is satisfied. At a 125 mA

drive current, the compliance voltage of the driver is ~0.4 V. For

a typical ADPD4100/ADPD4101 example, assume that the

lowest value for the V_LEDxsupply is 4.5 V and that the peak

current is 125 mA for two 528 nm LEDs in parallel. The

minimum value for C_VLEDis then equal to 1 µF.

TWO 528nm LEDs

ONE 850nm LED

4.0

3.5

3.0

2.5

2.0

1.5

1.0

C

_VLED= (3 × 10⁻⁶× 0.125)/(4.5 – (3.5 + 0.4)) = 0.625 nF (2)

As shown in Equation 2, as the minimum supply voltage drops

close to the maximum anode voltage, the demands on C_VLED

become more stringent, forcing the capacitor value higher. It is

important to insert the correct values into Equation 2. For

0

50

100

150

200

250

LED DRIVER CURRENT SETTING (mA)

example, using an average value for V_LED

worst case value for V_{LED MIN}can cause a serious design

__MINinstead of the

Figure 22. Example of the Average LED Forward-Biased Voltage Drop as a

Function of the LED Driver Current Setting

_

deficiency, resulting in a C_VLEDvalue that is too small, causing

insufficient optical power in the application.

To correctly size the C_VLEDcapacitor, do not deplete it during the

pulse of the LED to the point where the voltage on the capacitor

is less than the forward bias on the LED. Calculate the minimum

value for C_VLEDas follows:

Additionally, multiple pulses can cause further droop on the

V_LEDxsupply if the C_VLEDcapacitor is not fully recharged

between pulses. Therefore, adding a sufficient margin on C_VLED

is strongly recommended. Add additional margin to C_VLEDto

account for multiple pulses and derating of the capacitor value

over voltage, bias, temperature, and other factors over the life of

the component.

C

_VLED= (t_{LED_PW}× I_{LED_MAX})/(V_{LED_MIN}− (V_{FB_LED_MAX}+ V_COMP)) (1)

where:

_{LED_PW}is the LED pulse width.

_{LED_MAX}is the maximum forward-biased current on the LED

used in operating the devices.

t

I

DATAPATH, DECIMATION, SUBSAMPLING, AND

FIFO

V

_{LED_MIN}is the lowest voltage from the V_LEDxsupply with no load.

V

_{FB_LED_MAX}is the maximum forward-biased voltage required on

the LED to achieve I_{LED_MAX}

.

ADC samples are gathered for each pulse in each time slot and

combine to create a running positive and negative sum for each

time slot. These sums are each kept as a 32-bit unsigned value

register and saturate if the values overflow 32 bits. Each ADC

sample is added to either the positive or negative sum based on

the SUBTRACT_x bits for the current pulse in standard sampling

mode, or in the lit or dark acquisition regions for digital

integration mode. Figure 23 shows the datapath structure.

V

_COMPis the compliance voltage of the LED driver at the

programmed LED drive level.

The numerator of Equation 1 sets up the total discharge amount

in coulombs from the bypass capacitor to satisfy a single pro-

grammed LED pulse of the maximum current. The denominator

represents the difference between the lowest voltage from the

V_LEDxsupply and the LED required voltage. The LED required

Rev. 0 | Page 18 of 101

Data Sheet

ADPD4100/ADPD4101

ADC

CHx_ADC_ADJUST_x

(14 BITS UNSIGNED)

+

–

15 BITS SIGNED

ACCORDING TO

SUBTRACT OR DIGITAL

INTEGRATION REGION

POSITIVE ACCUMULATION

NEGATIVE ACCUMULATION

32 BITS SIGNED

ADD 2048 IF

ZERO_ADJUST_x = 1

CLIP

LIT

DARK

32 BITS UNSIGNED

PER CHANNEL

AND PER TIME SLOT

32 BITS UNSIGNED

DECIMATION

+

–

CLIP

SIGNAL

32 BITS UNSIGNED

CLIP

SIGNAL

32 BITS UNSIGNED

DARK

32 BITS UNSIGNED

PER CHANNEL

AND PER TIME SLOT

DATA REGISTERS

Figure 23. Datapath Block Diagram

Rev. 0 | Page 19 of 101

ADPD4100/ADPD4101

Data Sheet

At the end of the pulse operations in each time slot, the lit and

dark values are clipped to positive numbers and are sent to the

decimation unit. At the end of time slot operations, if the

decimated value is ready, the signal value is calculated by

subtracting the dark value from the lit value. Then, the data

registers that are ready are updated, and the selected values are

written to the FIFO. The data interrupt for that time slot is also

set at this time for each updated time slot.

time the decimated data is presented to the FIFO. For example,

if Time Slot A is operating at 300 Hz but decimating to 25 Hz,

and Time Slot B is set to subsample by 12, both time slots write

the FIFO during the same time slot sequence and at the same rate.

More complicated patterns can be made if the decimate and

subsample rates for the enabled time slots are different. The

user must manage the varying packet sizes by reading the data

in multiples of the repeating packet size. For example, if Time

Slot A is not decimating or subsampling, Time Slot B is subsam-

pling every second cycle, and Time Slot C is subsampling every

fourth cycle, the data pattern written to the FIFO is A, AB, A,

ABC, and so on, as the repeating packet.

Decimation

The DECIMATE_FACTOR_x bits determine the number of

time slot values used to create a 32-bit final sample value at a

rate of

Decimation and subsampling have the same effect on the output

data rate. The only difference is that the decimated time slots

operate every input cycle but produce data at the slower rate

using the on-chip decimating filter. The subsampling time slots

only occur at the slower rate.

Sample Rate =

(1/TIMESLOT_PERIOD_x)/(DECIMATE_FACTOR_x + 1)

If DECIMATE_FACTOR_x is 0, the output sample rate equals

the time slot rate. The final value is the sum of the decimated

samples. There is no divide by (DECIMATE_FACTOR_x + 1)

operation performed on the decimated data, but final data

values can be bit shifted to the right before being written to the

FIFO, creating a direct average when the number of samples is a

power of 2. DECIMATE_TYPE_x selects the method of

decimation used. A setting of 0 selects a simple block sum with

other settings allowing higher order CIC filters up to fourth

order. If using higher order CIC filters for the signal data, the

dark data still uses the simple block sum at the same decimation

rate. Each time slot maintains its own block sum or CIC filter

state. The entire decimation path uses a 32-bit datapath. When

using the CIC filter, the number of bits required for the result is

dependent on the number of pulses, the decimation rate and the

order of the CIC filter according to the following equation:

Status bytes are written to the FIFO every wake-up period,

regardless of which time slots execute. Using the same example

as the different decimate and subsample rates scenario, but with

a status byte enabled, the pattern is AS, ABS, AS, ABCS, and so

on, where S is a status byte.

FIFO

Data is written to the FIFO at the end of each sampling period.

This packet can include 0, 8-, 16-, 24-, or 32-bit data for each of

the dark data, lit data, and signal data values. The bit alignment

of the data written to the FIFO is selectable with a shift of 0 bits

to 31 bits, with saturation provided. Lower bits are ignored. The

DARK_SHIFT_x, LIT_SHIFT_x, and SIGNAL_SHIFT_x bits

select the number of bits to shift the output data to the right

before writing to the FIFO. The DARK_SIZE_x, LIT_SIZE_x,

and SIGNAL_SIZE_x bits select the number of bytes of each

field to be written from 0 bytes to 4 bytes. When set to 0, no

data is written for that data type. If there are any nonzero bits at

more significant bit positions than those selected, the data

written to the FIFO is saturated. If both channels are enabled,

all selected Channel 1 data values are written to the FIFO first,

followed by the Channel 2 data.

N

_BITS= 14 + log₂(Number of Pulses) + (log₂(Decimation

Rate))(CIC Order)

It is up to the user to ensure that there is no undesired overflow.

Final data results can be read from data registers or a 512-byte

data FIFO. Data written to the FIFO is configurable to allow the

different data registers, formats, and data sizes as required. Each

time slot can use its own decimation rate. Data from each time

slot is written to the FIFO at its respective ODR.

For example, in modes that utilize dark data, the eight upper

bits of the dark data can be stored with 24 appropriately selected

bits from the signal data for each time slot to allow detection of

whether the ambient light is becoming large, while limiting the

size of the amount of data transferred.

Subsampling

The ADPD4100/ADPD4101 support a subsampling mode that

allows selected time slots to run at slower sampling rates than

the programmed sampling rate. For example, in a multiparameter

application where most of the measurements need to be taken

at a sampling rate of 300 Hz but one of the measurements only

needs to be taken at 25 Hz, the subsampling mode can be used

on the time slot that only needs to operate at 25 Hz. To enable

subsampling mode for a specific time slot, set the SUBSAMPLE_x

bit to 1 and set the DECIMATE_FACTOR_x bits to the desired

subsampling rate. The subsampled time slot then samples only

once every (DECIMATE_FACTOR_x + 1) cycles, instead of

operating every time slot sequence. If other time slots are decimat-

ing at the same rate, the subsampled cycles occur at the same

Data is written to the FIFO at the end of the sampling period

only if there is enough FIFO space left to write data for each

active time slot. For example, if one active time slot is running

at an ODR of 100 Hz and a second time slot is decimating by 4

or subsampling at 1/4^ththe rate of the first time slot for an ODR

of 25 Hz, data is only written to the FIFO at the end of the

sampling period if there is enough room for both active time

slots to write data, regardless of whether the time slot that is

decimating or subsampling is supposed to write data during

Rev. 0 | Page 20 of 101

Data Sheet

ADPD4100/ADPD4101

that sampling period. It is up to the user to manage the data

appropriately at the microprocessor end when using time slots

with different decimation and/or subsampling rates.

To operate with the on-chip low frequency oscillator, use the

following writes. Set the LFOSC_SEL bit to 0 to select the

32 kHz clock or 1 if the 1 MHz clock is desired. Then, set either

the OSC_1M_EN or OSC_32K_EN bit to 1 to turn on the

desired internal oscillator. The internal 32 kHz clock frequency

is set using the 6-bit OSC_32K_ADJUST bits. The internal

1 MHz clock frequency is set using the 10-bit OSC_1M_FREQ_

ADJ bits.

The FIFO is never written with partial packets of data. If there

is not enough room for all of the data that is to be written to the

FIFO for all enabled time slots and any selected status bytes, no

data is written from any of the time slots during that period and

the INT_FIFO_OFLOW status bit is set.

If higher timing precision is required than can be provided by

the on-chip low frequency oscillator, the low frequency oscillator

can be driven directly from an external source provided on a

GPIOx input. To enable an external low frequency clock, use

the following writes. Enable one of the GPIOx inputs using the

GPIO_PIN_CFGx bits. Next, use the ALT_CLK_GPIO bits to

choose the enabled GPIOx input to be used for the external low

frequency oscillator. Set the ALT_CLOCKS bits to 0x1 to select

an external low frequency oscillator. Finally, use the

LFOSC_SEL bit to match whether a 32 kHz or 1 MHz clock is

being provided.

The order of samples written to the FIFO (if selected) is dark

data followed by signal data. The byte order for multibyte words

is shown in Table 14.

Table 14. Byte Order for FIFO Writes

Size

Byte Order (After Shift)

8

[7:0]

16

24

32

[15:8], [7:0]

[15:8], [7:0], [23:16]

[15:8], [7:0], [31:24], [23:16]

The FIFO size is 512 bytes. When the FIFO is empty, a read opera-

tion returns 0xFF, and the INT_FIFO_UFLOW status bit is set.

In a third method, an external 32 MHz clock is used for both

the high frequency clock and to be divided down to generate

the low frequency clock. To use this method, follow the

previous instructions for an external low frequency clock but

set the ALT_CLOCKS bits to 0x3, and use the LFOSC_SEL bit

to determine if a divide by 32 or 1000 is used to generate the

low frequency clock so that either a 32 kHz or 1 MHz clock is

generated from the external 32 MHz clock.

In addition to the FIFO, the signal and dark 32-bit registers can

be directly read. These registers are effectively two-stage registers

where there is an internal data register that updates with every

sample, and a latched output data register that is accessed by the

host. The data interrupts can be used to align the access of these

registers to just after the registers are written. If using the interrupt

timing is troublesome, use the HOLD_REGS_x bits to prevent an

update of the output registers during an access not aligned to

the interrupt. Setting the HOLD_REGS_x bits blocks the update

of the latched output data register and ensures that the dark and

signal values read by the host are from the same sample point. If

additional samples occur while the HOLD_REGS_x bit is set,

the samples are written to the internal data register but not

latched into the output data register that is accessed by the host.

Setting the HOLD_REGS_x bit to 0 reenables the pass through

of new data.

High Frequency Oscillator

A 32 MHz high frequency oscillator is generated internally or

can be provided externally. This high frequency clock clocks the

high speed state machine, which controls the AFE operations

during the time slots, such as LED timing and integration times.

The high frequency oscillator can be internally generated by setting

the ALT_CLOCKS bits to 0x0 or 0x1. When selected, the

internal 32 MHz oscillator is enabled automatically by the low

speed state machine during the appropriate wake-up time or

during the 32 MHz oscillator calibration routine.

After all time slots have completed, the optional status bytes are

written to the FIFO. See the Optional Status Bytes section for

more information.

The high frequency oscillator can also be driven from an external

source. To provide an external 32 MHz high frequency oscillator,

enable one of the GPIO inputs using the GPIO_PIN_CFGx bits.

Then, use the ALT_CLK_GPIO bits to choose the enabled

GPIOx input for the external high frequency oscillator. Finally,

write 0x2 or 0x3 to the ALT_CLOCKS bits to select an external

high frequency oscillator. Writing 0x2 provides only the high

frequency oscillator from the external source, whereas writing

0x3 generates both the low frequency oscillator and high

frequency oscillator from the external 32 MHz source. When

using an external 32 MHz oscillator, it must be kept running

continuously for proper device operation.

CLOCKING

Low Frequency Oscillator

A low frequency oscillator clocks the low speed state machine,

which sets the time base used to control the sample timing,

wake-up states, and overall operation. There are three options

for low frequency oscillator generation. The first option is an

internal, selectable 32 kHz or 1 MHz oscillator. The second

option is for the host to provide a low frequency oscillator

externally. Finally, the low frequency oscillator can be generated

by a divide by 32 or divide by 1000 of an external high frequency

clock source at 32 MHz. When powering up the device, it is

expected that the low frequency oscillator be enabled and left

running continuously.

Rev. 0 | Page 21 of 101

ADPD4100/ADPD4101

Data Sheet

The time stamp can calibrate the low frequency oscillator as

described in the Low Frequency Oscillator Calibration section.

The host can also use TIMESTAMP_SLOT_DELTA to determine

when the next time slot occurs. TIMESTAMP_SLOT_DELTA

can determine the arrival time of the samples currently in the

FIFO. TIMESTAMP_SLOT_DELTA does not account for the

decimation factor.

TIME STAMP OPERATION

The time stamp feature is useful for calibration of the low fre-

quency oscillator as well as providing the host with timing

information during time slot operation. Timestamping is sup-

ported by the use of any GPIO as a time stamp request input,

the CAPTURE_TIMESTAMP bit to enable capture of the time

stamp trigger, a time counter running in the low frequency

oscillator domain, and two output registers. The output bits include

TIMESTAMP_COUNT_x, which holds the number of low

frequency oscillator cycles between time stamp triggers, and

TIMESTAMP_SLOT_DELTA, which holds the number of low

frequency oscillator cycles remaining to the next time slot start.

The time stamp trigger is edge sensitive and can be set to either

trigger on the rising edge (default) or falling edge using

TIMESTAMP_INV.

LOW FREQUENCY OSCILLATOR CALIBRATION

The time stamp circuitry can calibrate either the 32 kHz or

1 MHz low frequency oscillator circuit by adjusting the

frequency to match the timing of the time stamp triggers.

Simply compare the TIMESTAMP_COUNT_x value in low

frequency oscillator cycles to the actual time stamp trigger

period and adjust the OSC_32K_ADJUST or OSC_1M_FREQ_

ADJ value accordingly.

The setup for using the time stamp operation is as follows:

1. Set CLK_CAL_ENA = 1 to enable the oscillator calibration

circuitry.

2. Configure a GPIO to support the time stamp input using the

appropriate GPIO_PIN_CFGx bits. Select the matching

GPIOx to provide the time stamp using the TIMESTAMP_

GPIO bits.

HIGH FREQUENCY OSCILLATOR CALIBRATION

3. Configure the ADPD4100/ADPD4101 for operation and

The high frequency oscillator is calibrated by comparing

multiples of its cycles with multiple cycles of the low frequency

oscillator, which is calibrated to the system time. Calibration of

the low frequency oscillator precedes calibration of the high

frequency oscillator. The method for calibrating the high

frequency oscillator is as follows:

enable the low frequency oscillator.

4. If the TIMESTAMP_SLOT_DELTA function is desired,

start the time slot operation by placing the device in go

mode using the OP_MODE bit (see Table 15). For low

frequency oscillator calibration, it is only required that the

low frequency oscillator be enabled. The device does not

have to be in go mode for low frequency oscillator

calibration.

1. Set CLK_CAL_ENA = 1 to enable the oscillator calibration

circuitry.

2. Write 1 to the OSC_32M_CAL_START bit.

3. The ADPD4100/ADPD4101 automatically power up the

high frequency oscillator.

4. The device automatically waits for the high frequency

oscillator to be stable.

5. An internal counter automatically counts the number of

32 MHz high frequency oscillations that occur during

128 cycles of the 1 MHz low frequency oscillator or

4 cycles of the 32 kHz low frequency oscillator, depending

on which low frequency oscillator is enabled based on the

setting of the LFOSC_SEL bit.

6. The OSC_32M_CAL_COUNT bits are updated with the

final count.

7. The 32 MHz oscillator automatically powers down

following calibration unless time slots are active.

8. The device resets the OSC_32M_CAL_START bit

indicating the count has been updated.

Use the following procedure to capture the time stamp:

1. Set the CAPTURE_TIMESTAMP bit to 1 to enable the

capture of the time stamp on the next rising edge of the

selected GPIOx input.

2. The host provides the initial time stamp trigger on the

selected GPIOx at an appropriate time.

3. The CAPTURE_TIMESTAMP bit is cleared when the

time stamp signal is captured unless the TIMESTAMP_

ALWAYS_EN bit is set, in which case, the capture of the

time stamp is always enabled. Reenable the capture if

necessary.

4. The host provides a subsequent time stamp trigger on the

selected GPIO at an appropriate time.

5. The number of low frequency oscillator cycles that

occurred between time stamp triggers can be read from the

TIMESTAMP_COUNT_x bits.

The host must continue to handle the FIFO and/or data register

data normally during time stamp processing.

The OSC_32M_FREQ_ADJ bits adjust the frequency of the

32 MHz oscillator to the desired frequency. When using an external

low frequency oscillator, the 32 MHz oscillator calibration is per-

formed with respect to the externally provided low frequency

oscillator.

If using a dedicated pin for a time stamp that does not have

transitions other than the time stamp, set the TIMESTAMP_

ALWAYS_EN bit to avoid automatic clearing of the CAPTURE_

TIMESTAMP bit. This setting removes the need to enable the

time stamp capture each time.

Note that when the calibrations of the low frequency and high

frequency oscillators are complete, set CLK_CAL_ENA = 0 to

disable the clocking of the oscillator calibration circuitry to

Rev. 0 | Page 22 of 101

Data Sheet

ADPD4100/ADPD4101

reduce the power consumption. CLK_CAL_ENA defaults to 0

so that the calibration circuitry is disabled by default.

Offset = 64 × (Number of 1 MHz Low Frequency Oscillator

Cycles) × TIMESLOT_OFFSET_x

If using the 32 kHz low frequency oscillator,

TIME SLOT OPERATION

Offset = 2 × (Number of 32 kHz Low Frequency Oscillator

Cycles) × TIMESLOT_OFFSET_x

Operation of the ADPD4100/ADPD4101 is controlled by an

internal configurable controller that generates all the timing

needed to generate sampling regions and sleep periods.

Measurements of multiple sensors and control of synchronous

stimulus sources are handled by multiple time slots. The device

provides up to 12 time slots for multisensor applications. The

enabled time slots are repeated at the sampling rate, which is

configured by the 23-bit TIMESLOT_PERIOD_x bits in the

TS_FREQ register. The following formula determines the

sampling rate:

For example, if TIMESLOT_OFFSET_C is set to 0x040 and the

1 MHz low frequency oscillator is used, the offset from the start

of Time Slot A to the start of Time Slot C is

Offset = (64 × 1 µs × 64) = 4.096 ms

The sampling rate is controlled by the low frequency oscillator.

The low frequency oscillator is driven by one of three sources as

described in the Clocking section.

If the sampling period is set too short to allow the enabled time

slots to complete, a full cycle of enabled time slot samples are

skipped, effectively reducing the overall sample rate. For example,

if the sampling rate is set to 100 Hz (10 ms period) and the total

amount of time required to complete all enabled time slots is

11 ms, the next cycle of time slots does not begin until t = 20 ms,

effectively reducing the sampling rate to 50 Hz.

Sampling Rate = Low Frequency Oscillator Frequency (Hz) ÷

TIMESLOT_PERIOD_x

Each time slot allows the creation of one or more LED and/or

modulation pulses, and the acquisition of the photodiode or

other sensor current based on that stimulus. The operating

parameters for each time slot are highly configurable.

Figure 24 shows the basic time slot operation sequence. Each

time slot is repeated at the sampling rate, followed by an ultra

low power sleep period. By default, subsequent time slots are

initiated immediately following the end of the previous time

slot. In addition, there is an option to add an offset to the start

of the subsequent time slots using the TIMESLOT_OFFSET_x

bits. Figure 25 shows the TIMESLOT_ OFFSET_B bits being

used to offset the start of Time Slot B. In this case, each time

slot still operates at the sampling rate, but there is a sleep period

between Time Slot A and Time Slot B. The wake period shown

in Figure 24 and Figure 25 is used to power up and stabilize the

analog circuitry before data acquisition begins. If the

If TIMESLOT_OFFSET_x is set too short to allow the previous

time slot to finish, the time slot occurs immediately after the

previous time slot. Time slots always occur in A through L order.

Using External Synchronization for Sampling

An external signal driven to a configured GPIO pin can be used to

wake the device from sleep instead of the TIMESLOT_PERIOD_x

counter, which allows external control of the sample rate and time.

This mode of operation is enabled using the EXT_SYNC_EN

bit and uses the GPIOx pin selected by the EXT_SYNC_GPIO

bits. If using this feature, be sure to enable the selected GPIOx

pin as an input using the appropriate GPIO_PIN_CFGx bits.

TIMESLOT_OFFSET_B bits are set to 0, the time slot starts as

soon as the previous time slot finishes.

When operating with external synchronization and set in go

mode, the device enters sleep first and waits for the next

external synchronization signal before waking up. This external

synchronization signal is then synchronized to the low frequency

oscillator and then starts the wake-up sequence. If an additional

external synchronization is provided prior to completing time

slot operations, it is ignored.

The time slot offset is always applied to the Time Slot A start

time. For example, TIMESLOT_OFFSET_D is an offset added

to the beginning of Time Slot A, not Time Slot C, which

immediately precedes Time Slot D.

The amount of offset applied is dependent on the low frequency

oscillator used. If using the 1 MHz low frequency oscillator,

SLEEP

WAKE

TIME SLOT A

TIME SLOT B

TIME SLOT L

SLEEP

WAKE TIME SLOT A

TIMESLOT_PERIOD_x/

LOW FREQUENCY OSCILLATOR(s)

Figure 24. Basic Time Slot Operation Sequence

SLEEP

WAKE

TIME SLOT A

SLEEP

WAKE

TIME SLOT B

SLEEP

WAKE

TIME SLOT A

TIME SLOT_OFFSET_B

TIMESLOT_PERIOD_x/

LOW FREQUENCY OSCILLATOR(s)

Figure 25. Time Slot Operation with Offset Using TIMESLOT_OFFSET_B

Rev. 0 | Page 23 of 101

ADPD4100/ADPD4101

Data Sheet

Level Interrupts

EXECUTION MODES

A state machine in the low frequency oscillator clock domain

controls sleep times, wake-up cycles, and the start of time slot

operations. The low frequency oscillator serves as the time base

for all time slot operations, controls the sample rates, and clocks

the low frequency state machine. This state machine controls all

operations and is controlled by the OP_MODE bit.

Two level interrupt status bits, INT_LEV0_x and INT_LEV1_x,

provide an interrupt when the dark data or signal data values

cross above or below a programmed threshold level.

Two comparison circuits are available per time slot. The

INT_LEV0_x or INT_LEV1_x status bits are set when the data

register update meets the criteria set by the associated

THRESH0_TYPE_x, THRESH0_DIR_x, THRESH0_CHAN_x

settings, or by the associated THRESH1_TYPE_x,

Table 15. OP_MODE Bit Setting Descriptions

OP_MODE Setting Mode

Description

THRESH1_DIR_x, and THRESH1_CHAN_x settings.

0

Standby All operations stopped. Time

slot actions reset. Low power

standby state.

The Level 0 interrupt operates as follows. The user sets an 8-bit

threshold value in the THRESH0_VALUE_x bits for the

corresponding time slot. This value is then shifted to the left by

anywhere from 0 bits to 24 bits, specified by the setting of the

THRESH0_SHIFT_x bits. A comparison is then made between

the shifted threshold value and the register chosen by the

THRESH0_TYPE_x bits and the THRESH0_CHAN_x bit. The

INT_LEV0_x status bit is set if the selected data register meets

the criteria set in the THRESH0_DIR_x bits. The Level 1 interrupt

operates in the same fashion.

1

Go

Transitioning to this state from

standby mode starts time slot

operation.

At power-up and following any subsequent reset operations, the

ADPD4100/ADPD4101 are in standby mode. The user can

write 0 to the OP_MODE bit to immediately stop operations

and return to standby mode.

Register writes that affect operating modes cannot occur during

go mode. The user must enter standby mode before changing

the control registers. Standby mode resets the digital portion of

the ADC, all of the pulse generators, and the state machine.

TIA Ceiling Detection Interrupts

When the TIA ceiling detection is enabled, the TIA ceiling

detection information is latched onto the INT_TCLN1_x bits in

Register 0x0004 for Channel 1 and the INT_TCLN2_x bits in

Register 0x0005 for Channel 2 separately for each time slot.

Therefore, the TIA ceiling detection information can be read for

all enabled channels in all enabled time slots separately. The

latched status bits remain set until they are cleared when the

TIA is driven into the region above the threshold, and the

associated status bits turn to 1. Note that these status bits

remain set until they are cleared.

When OP_MODE is set to 1, the device immediately starts the

first wake-up sequence and time slot operations unless using an

external synchronization trigger. If using an external synchroniza-

tion trigger, the device enters the sleep state before the first

wake-up and time slot regions begin.

HOST INTERFACE

The ADPD4100/ADPD4101 provide two methods of communica-

tion with the host, a SPI port and I²C interface. The device also

provides numerous FIFO, data register, error, and threshold

status bits, each of which can be provided by an interrupt function

from a GPIO, read from status registers, or appended as optional

status bytes at the end of a FIFO packet.

These status bits can be driven to Interrupt X or Interrupt Y by

setting the relevant registers in Table 31, or they can be monitored

by optional status bytes.

Clearing Interrupt Status Bits

Interrupt Status Bits

All status bits are set regardless of whether the status bit is routed

to one of the interrupt outputs, Interrupt X or Interrupt Y. The

status bits are independent of the interrupt enable bits. The

status bits are always set by the corresponding event. The

interrupt bits stay set until they are either manually or

automatically cleared.

Data Register Interrupts

The data interrupt status bits, INT_DATA_x for each time slot,

are set every time the data registers for that time slot are

updated. The state of the HOLD_REGS_x bit has no effect on

the interrupt logic.

The user can manually clear a given interrupt by writing a 1 to

the matching interrupt status bit. In addition, the data interrupt

status bits can be configured to clear automatically. When the

INT_ACLEAR_DATA_x or INT_ACLEAR_FIFO bit is set, the

appropriate interrupt status bit is automatically cleared when

any matching data register or FIFO register is read. Automatic

clearing of the interrupt status bits removes the need to

manually clear these interrupts.

FIFO Threshold Interrupt

The FIFO threshold interrupt status bit, INT_FIFO_TH, is set

when the number of bytes in the FIFO exceeds the value stored

in the FIFO_TH register. The INT_FIFO_TH bit is cleared

automatically when a FIFO read reduces the number of bytes

below the value in the FIFO_TH register, which allows the user

to set an appropriate data size for their host needs.

Rev. 0 | Page 24 of 101

Data Sheet

ADPD4100/ADPD4101

host with DMA or with an interrupt. Each of the different

interrupt status bits can be routed to Interrupt X or Interrupt Y,

or both.

Optional Status Bytes

There is an option to append each data packet with status bits. This

option is useful for hosts that cannot spare an interrupt channel

to service. The status bytes can each be individually selected in

the FIFO_STATUS_BYTES register. Each bit in the FIFO_

STATUS_BYTES register enables a status byte that is appended

to the data packet in the FIFO. If any bit in the FIFO_STATUS_

BYTES register is set to 1, the byte that is appended to the data

packet contains the status bits, as shown in Table 16. Table 16

shows the order, enable bit, and contents of each status byte.

For each interrupt, there is an associated Interrupt X and

Interrupt Y enable bit. See Table 31 for a full list of available

interrupts that can be brought out on Interrupt X and Interrupt Y.

The logic for the Interrupt X and Interrupt Y function is a logic

AND of the status bit with its matching enable bit. All enabled

status bits are then logically OR’ed to create the interrupt

function. The enable bits do not affect the status bits.

General-Purpose I/Os

The 4-bit sequence number cycles from 0 to 15 and is

incremented with a wraparound every time the time slot

sequence completes. This sequence number can also be made

available bitwise on the GPIOx pins.

The ADPD4100/ADPD4101 provide four general-purpose I/O

pins: GPIO0, GPIO1, GPIO2, and GPIO3. These GPIOs can be

used as previously described in the Interrupt Outputs, Interrupt

X and Interrupt Y section for interrupt outputs or for providing

external clock signals to the device. The GPIOs can also be used

for many different control signals, as synchronization controls

to external devices, as well as test signals that are useful during

system debugging. All of the available signals that can be

brought out on a GPIOx pin are listed in Table 35.

Interrupt Outputs, Interrupt X and Interrupt Y

The ADPD4100/ADPD4101 support two separate interrupt

outputs, Interrupt X and Interrupt Y. Each interrupt has the option

to be driven to any of the four GPIOx pins. The two different

interrupt outputs can be generated for a host processor if desired.

For example, the FIFO threshold interrupt, INT_FIFO_TH, can

be routed to Interrupt X and used to drive the direct memory

access (DMA) channel of the host, while the INT_FIFO_OFLOW

and INT_FIFO_UFLOW interrupts can be routed to Interrupt

Y and used to drive an additional host interrupt pin. Another

example case includes routing the data interrupt from a single

time slot to Interrupt X and the FIFO threshold interrupt to

Interrupt Y. The host receives one interrupt when the interrupt

of that particular channel occurs and the host can then read

that register directly. Interrupt Y, in this case, is handled by the

IOVDD Supply Voltage Consideration

The ADPD4100/ADPD4101 can operate with IOVDD as low as

1.7 V and as high as 3.6 V. LOW_IOVDD_EN in Register 0x00B4

is set to 0x1 for IOVDD lower than 3 V. 0x1 is the default value

for this bit because the typical IOVDD value is 1.8 V.

If 3 V or higher is supplied for IOVDD, the LOW_IOVDD_EN

bit must be set to 0x0 for proper operation.

Table 16. FIFO Status Byte Order and Contents

Contents¹

Byte Order

Enable Bit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

4-bit sequence

DATA_C DATA_B

Bit 1

Bit 0

0

1

2

3

4

5

6

7

8

ENA_STAT_SUM

ENA_STAT_D1

ENA_STAT_D2

ENA_STAT_L0

ENA_STAT_L1

ENA_STAT_LX

ENA_STAT_TC1²

ENA_STAT_TC2²

ENA_STAT_TCX²

0

Any LEV1_x

DATA_F

0

Any LEV0_x

DATA_E

0

DATA_H

0

DATA_G

0

DATA_D

DATA_L

LEV0_D

LEV1_D

LEV0_L

DATA_A

DATA_I

LEV0_A

LEV1_A

LEV0_I

DATA_K

LEV0_C

LEV1_C

LEV0_K

DATA_J

LEV0_B

LEV1_B

LEV0_J

LEV0_H

LEV1_H

LEV1_L

LEV0_G

LEV1_G

LEV1_K

LEV0_F

LEV1_F

LEV1_J

LEV0_E

LEV1_E

LEV1_I

TCLN1_E

TCLN2_E

TCLN2_I

TCLN1_H TCLN1_G TCLN1_F

TCLN2_H TCLN2_G TCLN2_F

TCLN2_L TCLN2_K TCLN2_J

TCLN1_D TCLN1_C TCLN1_B TCLN1_A

TCLN2_D TCLN2_C TCLN2_B TCLN2_A

TCLN1_L TCLN1_K TCLN1_J TCLN1_I

¹DATA_x refers to the data register interrupts for the corresponding time slot. LEV0_x and LEV1_x refer to Level 0 and Level 1 time slot interrupts, respectively, for

Time Slot A through Time Slot L.

²These status bytes are associated with TIA ceiling detection. See the Protecting Against TIA Saturation with TIA Ceiling Detection section for more information.

Rev. 0 | Page 25 of 101

ADPD4100/ADPD4101

Data Sheet

SPI and I²C Interface

starting with the MSB. In addition, multiple registers can be

read if additional 16-bit data is shifted out prior to deassertion

CS

The ADPD4100 contains a SPI port, and the ADPD4101

contains an I²C interface. The SPI and I²C interfaces operate

synchronously with their respective input clocks and require no

internal clocks to operate.

of the

signal.

It is recommended that reading from the FIFO is performed

byte wise. There is no requirement to read multiples of 16 bits.

I²C Operations

The ADPD4101 supports fast-mode plus (see the I²C

specification from NXP for more information).

The ADPD4100/ADPD4101 have an internal power-on reset

circuit that sets the device into a known idle state during the

initial power-up. After the power-on reset is released,

approximately 2 μs to 6 ꢀs after the DVDDx supply is active, the

The I²C operations require addressing the device as well as

choosing the register that is being read or written. An I²C

register write is shown in Figure 28 and Figure 29. The SDA pin

is bidirectional and open drain, where different bit times are

driven in a predetermined way by the master or the slave. The

ADPD4101 acts as a slave on the I²C bus. Start and stop bit

operations are shown as S and P in Figure 28 and Figure 29. The

I²C port supports both 7-bit and 15-bit addresses. If accessing

Address 0x007F or lower, a 7-bit address can be used. If the first

address bit after the slave address acknowledge (ACK) is a 0, a

7-bit address is used, as shown in the short read and write

operations (see Figure 28 to Figure 31). If the first bit after a

slave address acknowledge is 1, a 15-bit address is used as

shown in the long read and write operations (see Figure 32 and

Figure 33).

device can be read and written through the SPI or I²C interface.

The registers are accessed using addresses within a 15-bit

address space. Each address references a 15-bit register with one

address reserved for the FIFO read accesses. For both the I²C

and SPI interfaces, reads and writes auto-increment to the next

register if additional words are accessed as part of the same

access sequence. This automatic address increment occurs for

all addresses except the FIFO address, one less than the FIFO

address and the last used address, which is 0x277. Reads from

the FIFO address continue to access the next byte from the FIFO.

SPI Operations

The SPI single register write operation is shown in Figure 26.

The first two bytes contain the 15-bit register address and specifies

that a write is requested. The remaining two bytes are the 16 data

bits to write to the register. The register write occurs only when

Figure 28 shows the first half of the short register write operation.

The first byte indicates that the ADPD4101 is being addressed

with a write operation. The ADPD4101 indicates that it has

been addressed by driving an acknowledge. The next byte

operation is a write of the address of the register to be written.

CS

all 16 bits are shifted in prior to deassertion of the signal.

In addition, multiple registers can be written if additional 16-bit

CS

data is shifted in before deassertion of the

signal. The

register address automatically increments to the next register

after each 16 bits of data.

S

short

The MSB is the L/ bit (long/

). When this bit is low, a 7-bit

S

address follows. If the L/ bit is high, a 15-bit address follows.

The ADPD4101 sends an acknowledge following the register

address.

The SPI single register read operation is shown in Figure 27.

The first two bytes contain the 15-bit register address and

specifies that a read is requested. Register bits are shifted out

SCLK

CS

A14 A13 A12 A11 A10 A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

MOSI

Wr

Figure 26. SPI Write Operation

SCLK

CS

MOSI

MISO

A14 A13 A12 A11 A10 A9

A8

A7

A6

A5

A4

A2

A1

A0

Rd

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

A0

D3

D2

D1

D0

Figure 27. SPI Read Operation

SCL

SDA

S

SLVA6 SLVA5 SLVA4 SLVA3 SLVA2 SLVA1

SLVA

WRITE

ACK

L/S

A6

A5

A4

A3

A2

A1

ACK

D15

GRAY BACKGROUND MEANS DRIVEN BY ADPD4101

Figure 28. I²C Short Write First Half

SCL

SDA

D15

D14

D13

D12

D11

D10

D9

D8

ACK

D7

D6

D5

D4

D3

D2

D1

D0

ACK

P

Figure 29. I²C Short Write Second Half

Rev. 0 | Page 26 of 101

Data Sheet

ADPD4100/ADPD4101

The rest of the write operation is shown in Figure 29, which

shows the two data bytes that are written to the 16-bit register.

Registers are written only when all 16 bits are shifted in before a

stop bit occurs. The ADPD4101 sends an acknowledge for each

byte received. Additional pairs of byte operations can be repeated

prior to the stop bit occurring. The address auto-increments

after each complete write. Register writes occur only after each

pair of bytes is written.

register read data one byte at a time. The host acknowledges

each byte after it is sent by the ADPD4101, if additional bytes

are to be read. The same address incrementing is used for reads

as well.

To read multiple bytes from the FIFO or from sequential

registers, simply repeat the middle byte operation as shown in

Figure 31.

The first portion of a long write operation is shown in Figure 32.

The second half of the long write is the same as for the short

write, as shown in Figure 29.

The I²C short read operations are shown in Figure 30 and

Figure 31. Like the write operation, the first byte pair selects the

S

ADPD4101 and specifies the register address (with the L/ bit

The first half of a long read operation is shown in Figure 33.

The second half is the same as shown in Figure 31.

low) to read from.

Figure 31 shows the rest of the read operation. This sequence

starts with a start bit, selects the ADPD4101, and indicates that

a read operation follows. The ADPD4101 sends an acknowledge

to indicate data to be sent. The ADPD4101 then shifts out the

SCL

SDA

S

SLVA6 SLVA5 SLVA4 SLVA3 SLVA2 SLVA1 SLVA WRITE ACK

L/S

A6

A5

A4

D6

A3

A2

D3

A1

A0

ACK

Figure 30. I²C Short Read First Half

SCL

SDA

S

ACK

P

SLVA2 SLVA1 SLVA0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D5

D4

D2

D1

D0

SLVA6 SLVA5 SLVA4 SLVA3

READ

NACK

Figure 31. I²C Short Read Second Half

SCL

S

SLVA6 SLVA5 SLVA4 SLVA3 SLVA2 SLVA1 SLVA0 WRITE ACK

A14 A13 A12 A11 A10

A9

A8

ACK

A7

A6

A5

A4

A3

A2

A1

A0

ACK D15

SDA

L/S

Figure 32. I²C Long Write First Half

SCL

SDA

S

SLVA6 SLVA5 SLVA4 SLVA3 SLVA2 SLVA1 SLVA0 WRITE ACK

A14

A13

A12

A11

A10

A9

A8

ACK

A7

A6

A5

A4

A3

A2

A1

A0

ACK

L/S

Figure 33. I²C Long Read First Half

Rev. 0 | Page 27 of 101

ADPD4100/ADPD4101

Data Sheet

APPLICATIONS INFORMATION

Continuous Connect Mode

OPERATING MODE OVERVIEW

Continuous connect mode is used for a single analog integration

of incoming charge per ADC conversion and is the most common

operating mode for the ADPD4100/ADPD4101. In continuous

connect mode, most of the dynamic range of the integrator is

used when integrating the charge from the sensor response to a

single stimulus event, for example, an LED pulse. The TIA is

continuously connected to the inputs after the precondition

period by setting MOD_TYPE_x to 0. Therefore, the input

connection is not modulated in continuous connect mode.

The ADPD4100/ADPD4101 are effectively charge measuring

devices that can interface with many different sensors, enabling

optical and electrical measurements in various healthcare,

industrial and consumer applications, such as PPG, ECG, EDA,

impedance, capacitance, and temperature measurements, and

gas, smoke, and aerosol detection. A selection of operating

modes are built into the device to optimize each of the different

sensor measurements supported.

ANALOG INTEGRATION MODE

Continuous connect mode is the typical operating mode used

for a PPG measurement, where an LED is pulsed into human

tissue and the resultant charge from the photodiode response is

integrated and subsequently converted by the ADC. Figure 34

shows an example of a typical PPG measurement circuit.

Analog integration mode refers to the modes of operation

where the incoming charge from the sensor response to a

stimulus event is integrated by the integrator in the

ADPD4100/ADPD4101. There are several different analog

integration modes, including continuous connect mode, float

mode, pulse connect modulation, modulation of stimulus

source, multiple integration mode, and sleep float mode.

VCx

R

6.3pF

F

There is also a digital integration mode, where the integrator is

configured as a buffer and the ADC samples are digitally

integrated (see the Digital Integration Mode section for more

information).

R

INT

INx

TIA

BPF

ADC

INT

R

F

SWITCH

V

LED1

6.3pF

C

VLED

TIA_VREF

Connection Modulation Types

LEDx

The ADPD4100/ADPD4101 use three different types of modula-

tion connections to a sensor, controlled by the MOD_TYPE_x

bits. Table 17 shows the different functions controlled by MOD_

TYPE_x. The default mode of operation is MOD_TYPE_x = 0,

where there is no modulation of the input connection, and is

the mode used as described in the Continuous Connect Mode

section.

Figure 34. Typical PPG Measurement Circuit

Set the PRECON_x bits to 0x5 to set the anode of the photodiode

to the TIA_VREF potential during the preconditioning period.

The VCx pin is connected to the cathode of the photodiode and

is set to TIA_VREF + 215 mV to apply a 215 mV reverse bias

across the photodiode, which reduces the photodiode capacitance

and reduces the noise of the signal path. Set TIA_VREF to

1.27 V using the AFE_TRIM_VREF_x bits for maximum

dynamic range.

Table 17. Modulation Connections Based on MOD_TYPE_x

MOD_TYPE_x

(Decimal)

Connect Function

0

TIA is continuously connected to INx after the

precondition period. There is no modulation of

the input connection.

The LED pulse is controlled with the LED_OFFSET_x and LED_

WIDTH_x bits. The default LED offset (LED_OFFSET_x =

0x10) is 16 μs from the end of the preconditioning period and is

suitable for most use cases. Recommended LED pulse width is 2

μs when using the BPF. Short LED pulse widths provide the

greatest amount of ambient light rejection and the lowest power

dissipation. The period is automatically calculated by the

ADPD4100/ADPD4101. The automatic calculation is based on

the integration width selected and the number of ADC conver-

sions. To use the automatic calculation, leave the MIN_PERIOD_x

bits at its default value of 0. If a longer period is desired, for

example, if a specific pulse frequency is desired, use the

MIN_PERIOD_x bits to enable a longer period.

1

2

Float mode operation. The TIA is connected to

INx only during the modulation pulse and

disconnected (floated) between pulses.

Nonfloat mode connection modulation. The

TIA is connected to INx during the modulation

pulse and connected to the precondition value

between pulses.

Rev. 0 | Page 28 of 101

Data Sheet

ADPD4100/ADPD4101

In continuous connect mode using 2 µs LED pulses, the

automatic period calculation is

SNR. The ADC conversions can be set to 1, 2, 3, or 4, based on

the ADC_COUNT_x bits.

Period = (2 + 2 × INTEG_WIDTH_x + (Number of

Channels Enabled × (ADC_COUNT_x + 1)))

If two channels are enabled, Channel 1 occurs first, followed by

Channel 2.

The integration pulses are controlled with the INTEG_

OFFSET_x and INTEG_WIDTH_x bits. It is recommended

that an integration width of 1 μs greater than the LED width be

used because the signal spreads due to the response of the BPF.

By setting the integration width 1 μs wider than the LED width,

a maximum amount of charge from the incoming signal is

integrated.

The total number of pulses is equal to NUM_INT_x × NUM_

REPEAT_x. In continuous connect mode, NUM_INT_x = 1 for

a single integration sequence per ADC conversion. Therefore,

the total number of pulses is controlled by NUM_REPEAT_x.

Increasing the number of pulses reduces the noise floor of the

measurement by a factor of √n, where n is the total number of

pulses.

The number of ADC conversions defaults to a single ADC

conversion. However, oversampling is available for increased

Figure 35 shows the timing operation where a single integration

cycle is used per ADC conversion. Table 18 details the relevant

registers using continuous connect mode for a PPG measurement.

Table 18. Continuous Connect Mode Settings

Time Slot A Register

Group

Address¹

Bit Field Name

SAMPLE_TYPE_x

AFE_PATH_CFG_x

INPxx_x

Description

Signal Path

Setup

0x0100, Bits[13:12]

0x0101, Bits[8:0]

0x0102, Bits[15:0]

0x0103, Bits[14:12]

0x0103, Bits[7:6], Bits[1:0]

0x0104, Bits[5:0]

0x0104, Bits[9:8]

0x0108, Bits[13:12]

Leave at the default setting (0) for default sampling mode.

Set to 0x0DA for TIA, BPF, integrator, and ADC.

Enable desired inputs.

PRECON_x

Set to 0x5 to precondition anode of the photodiode to TIA_VREF.

Set to 0x2 to set ~215 mV reverse bias across the photodiode.

Select TIA gain.

VCx_SEL_x

TIA_GAIN_CHx_x

AFE_TRIM_VREF_x

MOD_TYPE_x

Set to 0x3 to set TIA_VREF = 1.27 V for maximum dynamic range.

Set to 0 for continuous TIA connection to inputs following

preconditioning.

Timing

0x0109, Bits[7:0]

LED_OFFSET_x

Sets start time of first LED pulse in 1 μs increments. 0x10 default

(16 μs).

0x0109, Bits[15:8]

0x010A, Bits[4:0]

0x010B, Bits[12:0]

LED_WIDTH_x

INTEG_WIDTH_x

INTEG_OFFSET_x

Sets width of LED pulse in 1 μs increments. 2 μs recommended.

Integration time in µs. Set to LED_WIDTH_x + 1.

Integration sequence start time = INTEG_OFFSET_x. Optimize as

described in the Optimizing Position of Integration Sequence

section.

0x0107, Bits[15:8]

0x0107, Bits[7:0]

NUM_INT_x

NUM_REPEAT_x

Set to 1 for a single integration per group of ADC conversions.

With NUM_INT_x = 1, NUM_REPEAT_x sets the total number of

pulses.

LED Settings

0x0105, Bit 15 and Bit 7;

0x0106, Bit 15 and Bit 7

0x0105, Bits[14:8], Bits[6:0];

0x0106, Bits[14:8], Bits[6:0]

LED_DRIVESIDEx_x

LED_CURRENTx_x

SUBTRACT_x

Select LED for time slot used.

Set LED current for selected LED.

Integrator

0x010D, Bits[7:4]

Four-pulse subtract pattern. Set to 1 to negate the math operation

in the matching position in a group of four pulses. The LSB maps to

the first pulse.

Chop Mode²

0x010D, Bits[3:0]

REVERSE_INTEG_x

Four-pulse integration reverse pattern. Set to 1 to reverse the

integrator positive and negative pulse order in the matching

position in a group of four pulses. The LSB maps to the first pulse.

¹This is the Time Slot A register address. Add 0x020 for the identical register address for each subsequent time slot. For example, Register 0x0100 is the location for

SAMPLE_TYPE_A. For Time Slot B, this register is at Address 0x0120. For Time Slot C, this register is at Address 0x0140. For Time Slot D, this register is at

Address 0x0160, and so on.

²See the Improving SNR Using Integrator Chopping section for more information about integrator chop mode.

Rev. 0 | Page 29 of 101

ADPD4100/ADPD4101

Data Sheet

integrator timing for all TIA gain settings without reoptimizing

for each TIA gain setting, 200 kΩ TIA gain optimal timing must

be used for the other TIA gain settings.

Optimizing Position of Integration Sequence

It is critical that the zero crossing of the output response of the

BPF be aligned with the integration sequence such that the

positive integration is aligned with the positive portion of the

BPF output response and the negative integration is aligned with

the negative portion of the BPF output response (see Figure 35).

Improving SNR Using Multiple Pulses

The ADPD4100/ADPD4101 use short LED pulses, on the order

of 2 μs or 3 μs. The SNR of a single pulse is approximately 72 dB

to 76 dB, depending on the TIA gain. The SNR can be extended

to ~100 dB by increasing the number of pulses per sample and

filtering to a relevant signal bandwidth, for example, 0.5 Hz to

20 Hz for a heart rate signal. The SNR increases as the square

root of the number of pulses. Thus, for every doubling of pulses,

3 dB of SNR increase is achieved. The number of pulses is

increased with the NUM_REPEAT_x bits. The resulting data

for a particular time slot is the summation of ADC conversions

that are NUM_REPEAT_x times. If the number of bits required

for the result is larger than the number of output bits desired by

the user, the most significant bits of the accumulated values can

be selected by DARK_SHIFT_x, LIT_SHIFT_x, and

A simple test to find the zero crossing is to set up the circuit so

that the LED is reflecting off a reflector at a fixed distance from

the photodiode such that a steady dc level of photodiode current

is provided to the ADPD4100/ADPD4101. Monitor the output

while sweeping the integrator offset, INTEG_OFFSET_x,

Bits[12:5], from a low value to a high value in 1 μs steps. The

zero crossing is located when a relative maxima is seen at the

output. The zero crossing can then be identified with much finer

precision by sweeping the INTEG_OFFSET_x, Bits[4:0] in

31.25 ns increments. It is critical to identify the zero crossing in

such a fine precision to achieve the highest SNR performance.

The optimal timing point is a function of TIA bandwidth which

varies with TIA gain. To achieve the maximum SNR at each TIA

gain setting, it is recommended that the user find the optimal

timing point at each TIA gain setting for a given use case.

Because there is minimal device to device variation in this

optimal timing point, that same integrator offset timing for

each gain setting can be used for all devices. To use the same

SIGNAL_SHIFT_x bits. DARK_SHIFT_x, LIT_SHIFT_x, and

SIGNAL_SHIFT_x shift the output data to the right before

writing to the FIFO. For example, an 18-bit accumulated value

can be shifted to write only the upper 16 bits to the FIFO.

Optionally, 24-bit or 32-bit output can be written to the FIFO.

START OF TIME SLOT

PRECONDITION

PRE_WIDTH_x

LED_OFFSET_x

PERIOD

LED_WIDTH_x

(AUTOMATICALLY CALCULATED)

LED

TIA OUTPUT

BPF OUTPUT

INTEG_OFFSET_x

ZERO CROSSING

INTEG_WIDTH_x

–

INTEGRATOR

SEQUENCE

–

+

INTEGRATOR

OUTPUT

ADC CONVERSION(S)

ADC CHANNEL 1

ADC CHANNEL 2

(IF ENABLED)

REPEAT NUM_REPEAT_x TIMES

Figure 35. Single Analog Integration per ADC Conversion with Continuous Connect Mode

Rev. 0 | Page 30 of 101

Data Sheet

ADPD4100/ADPD4101

bits = 0xA to reverse the integration sequence for the second and

fourth pulses. To complete the operation, the math must be

adjusted by setting the SUBTRACT_x bits = 0xA. An even

number of pulses must be used with integrator chop mode.

Improving SNR Using Integrator Chopping

The last stage in the ADPD4100/ADPD4101 datapath is a

charge integrator. The integrator uses an on and off integration

sequence, synchronized to the emitted light pulse, which acts as

an additional high-pass filter to remove offsets, drifts, and low

frequency noise from the previous stages. However, the

integrating amplifier can itself introduce low frequency signal

content. The ADPD4100/ADPD4101 have a mode that enables

additional chopping in the digital domain to remove this signal.

Chopping is achieved by using an even number of pulses per

sample and inverting the integration sequence for half of those

sequences. When the calculation is performed to combine the

digitized result of each of the pulses of the sample, the sequences

with an inverted integrator sequence are subtracted and the

sequences with a normal integrator sequence are added. An

example diagram of the integrator chopping sequence is shown

in Figure 36.

Because integrator chopping eliminates the low frequency noise

contribution from the integrator, it is recommended to always

keep integrator chop mode enabled in continuous connect

mode to achieve optimal SNR performance.

When using integrator chopping, the ADC offset bits,

CH1_ADC_ADJUST_x and CH2_ADC_ADJUST_x, must be

set to 0, because when the math is adjusted to subtract inverted

integration sequences while default integration sequences are

added, any digital offsets at the output of the ADC are automati-

cally eliminated. Integrator chop mode also eliminates the need

to manually null the ADC offsets at startup in a typical application.

Note that the elimination of the offset using integrator chop

mode can clip at least half of the noise signal when no input

signal is present, which makes it difficult to measure the noise

floor during characterization of the system. There are three

options for performing noise floor characterization of the system.

The result of chopping is that any low frequency signal contribu-

tion from the integrator is eliminated, leaving only the

integrated signal and resulting in higher SNR, especially at

higher numbers of pulses and at lower TIA gains where the

noise contribution of the integrator becomes more pronounced.

•

Integrator chop mode disabled.

Integrator chop mode enabled but with a minimal signal

present at the input, which increases the noise floor

enough such that it is no longer clipped.

Setting the ZERO_ADJUST_x bit = 1, which adds 2048 codes

to the end result.

Digital chopping is enabled using the registers and bits detailed

in Table 19. The bits define the chopping operation for the first

four pulses. This 4-bit sequence is then repeated for all

subsequent sequence of four pulses. In Figure 36, a sequence is

shown where the second and fourth pulses are inverted while the

first and third pulses remain in the default polarity (noninverted).

This configuration is achieved by setting the REVERSE_INTEG_x

•

PULSE 1

PULSE 2

PULSE 3

PULSE 4

LED

BPF OUTPUT

INTEGRATOR

SEQUENCE

–

+

ADC

+

–

+

–

Figure 36. Diagram of Integrator Chopping Sequence

Table 19. Register Settings for Integrator Chop Mode

Time Slot A

Register

Group

Address¹

Bit Field Name

Description

Integrator

Chop Mode

0x010D, Bits[7:4]

SUBTRACT_x

Four-pulse subtract pattern. Set to 1 to negate the math operation in the

matching position in a group of four pulses. The LSB maps to the first pulse.

0x010D, Bits[3:0]

REVERSE_INTEG_x Four-pulse integration reverse pattern. Set to 1 to reverse the integrator positive

and negative pulse order in the matching position in a group of four pulses. The

LSB maps to the first pulse.

¹This is the Time Slot A register address. Add 0x020 for the identical register address for each subsequent time slot. For example, Register 0x010D is the location for

SUBTRACT_A. For Time Slot B, this register is at Address 0x012D, For Time Slot C, this register is at Address 0x014D. For Time Slot D, this register is at Address 0x016D,

and so on.

Rev. 0 | Page 31 of 101

ADPD4100/ADPD4101

Data Sheet

In float LED mode, multiple pulses are used to cancel electrical

offsets, drifts, and ambient light. To achieve this ambient light

rejection, an even number of equal length pulses is used. For

every pair of pulses, the LED flashes in one of the pulses and

does not flash in the other. The return from the combination of

the LED, ambient light, and offset is present in one of the pulses.

In the other, only the ambient light and offset is present. A

subtraction of the two pulses is made that eliminates ambient

light as well as any offset and drift. It is recommended to use

groups of four pulses for measurement where the LED is flashed

on Pulse 2 and Pulse 3. The accumulator adds Pulse 2 and Pulse 3

and then subtracts Pulse 1 and Pulse 4. To gain additional SNR,

use multiple groups of four pulses.

Float Mode Operation

The ADPD4100/ADPD4101 have a unique operating mode, float

mode, that allows high SNR at low power in low light situations.

In float mode, the photodiode is first preconditioned to a known

state. Then, the photodiode anode is disconnected from the

receive path of the device for a preset amount of float time.

During the float time, light falls on the photodiode, either from

ambient light, pulsed LED light, or a combination of the two

depending on the operating mode. Charge from the sensor is

stored directly on the capacitance of the sensor, C_PD. At the end

of the float time, the photodiode is switched into the receive

path of the ADPD4100/ADPD4101 and an inrush of the

accumulated charge occurs, which is then integrated, allowing

the maximum amount of charge to be processed per pulse with

the minimum amount of noise added by the signal path. The

charge is integrated externally on the capacitance of the

photodiode for as long as it takes to acquire maximum charge,

independent of the amplifiers of the signal path, effectively

integrating noise free charge. Float mode allows the user the

flexibility to increase the amount of charge per measurement by

either increasing the LED drive current or by increasing the

float time.

For each group of four pulses, the settings of LED_DISABLE_x

determine if the LED flashes in a specific pulse position. Which

pulse positions are added or subtracted is configured in the

SUBTRACT_x bits. These sequences are repeated in groups of

four pulses. The value written to the FIFO or data registers is

dependent on the total number of pulses per sample period.

With NUM_INT_x set to 1, NUM_REPEAT_x determines the

total number of pulses. For example, if the device is set up for

32 pulses, the four-pulse sequence, as defined in

LED_DISABLE_x and SUBTRACT_x, repeats eight times and a

single register or FIFO write of the final value based on

32 pulses executes.

In float mode, the signal path bypasses the BPF and uses only

the TIA and integrator. The BPF is bypassed because the shape

of the signal produced when transferring the charge from the

photodiode by modulating the connection to the TIA can differ

across devices and conditions. A filtered signal from the BPF is

not able to be reliably aligned with the integration sequence.

Therefore, the BPF cannot be used. In float mode, the entire

charge transfer is integrated in the negative cycle of the

integrator, and the positive cycle cancels any offsets.

In float mode, the MIN_PERIOD_x bits must be set to control

the pulse period. The automatic period calculation is not

designed to work with float mode. Set the MIN_PERIOD_x

bits, in 1 μs increments, to accommodate the amount of float

time and connect time required.

Placement of the integration sequence is such that the negative

phase of the integration is centered on the charge transfer

phase. The TIA is an inverting stage. Therefore, placing the

negative phase of the integration during the transferring of the

charge from the photodiode causes the integrator to increase

with the negative going output signal from the TIA.

Float LED Mode for Synchronous LED Measurements

Float LED mode is desirable in low signal conditions where the

CTR is below 5 nA/mA. In addition, float mode is an ideal

option when limiting the LED drive current of the green LEDs

in a heart rate measurement to keep the forward voltage drop of

the green LED to a level that allows the elimination of a boost

converter for the LED supply. For example, the LED current can

be limited to 10 mA to ensure that the LED voltage drop is ~3 V

so that it can operate directly from the battery without the need

of a boost converter. Float mode accumulates the received

charge during longer LED pulses without adding noise from the

signal path, effectively yielding the highest SNR per photon

attainable.

In the example shown in Figure 37, the LED flashes in the

second and third pulses of the four-pulse sequence.

SUBTRACT_x is set up to add the second and third pulses

while subtracting the first and fourth pulses, effectively

cancelling out the ambient light, electrical offsets, and drift.

Table 20 details the relevant registers for float LED mode.

Rev. 0 | Page 32 of 101

Data Sheet

ADPD4100/ADPD4101

START OF TIME SLOT

PRECONDITION

PRE_WIDTH_x

(DEFAULT 8µs)

MOD_OFFSET_x

MIN_PERIOD_x

MOD_WIDTH_x

CONNECT/FLOAT

MASKED LED PULSE

FLASH LED

MASKED LED PULSE

LED PULSES

MASK PULSE 1 AND PULSE 4

FLASH PULSE 2 AND PULSE 3

LED_OFFSET_x

LED_WIDTH_x

ACCUMULATED

CHARGE ON PD

INTEGRATOR

OUTPUT

INTEG_OFFSET_x

INTEGRATOR

SEQUENCE

INTEG_WIDTH_x

INTEGRATOR

RESET

ADC READ

Figure 37. Four-Pulse Float Mode Operation

Table 20. Float LED Mode Settings

Time Slot A

Group

Register Address¹

0x0100, Bits[13:12]

0x0100, Bits[11:10]

0x0101, Bits[8:0]

0x0102, Bits[15:0]

0x0103, Bits[14:12]

Bit Field Name

SAMPLE_TYPE_x

INPUT_R_SELECT_x

AFE_PATH_CFG_x

INPxx_x

Description

Signal Path Setup

Leave at the default setting (0) for default sampling mode.

Set to 0x0 for 500 Ω series input resistor.

Set to 0x0E6 for TIA, integrator, and ADC. Bypass BPF.

Enable desired inputs.

Set to 0x4 to precondition anode of photodiode to the input of

the TIA.

PRECON_x

0x0103, Bits[7:6], Bits[1:0]

0x0104, Bits[5:0]

0x0104, Bits[9:8]

VCx_SEL_x

Set to 0x2 to set ~215 mV reverse bias across photodiode.

Select TIA gain (100 kΩ or 200 kΩ for float mode).

Set to 0x2 to set TIA_VREF = 0.9 V.

TIA_GAIN_CHx_x

AFE_TRIM_VREF_x

NUM_INT_x

Float Mode

Configuration

0x0107, Bits[15:8]

0x0107, Bits[7:0]

Set to 1 for a single integration per group of ADC conversions.

Number of sequence repeats. Must be set to a multiple of 2 for

float mode.

NUM_REPEAT_x

0x0108, Bits[13:12]

0x0108, Bits[9:0]

MOD_TYPE_x

MIN_PERIOD_x

Set to 0x1 for float mode operation.

Set the period to accommodate float time plus connect time, in

1 μs increments.

0x010A, Bits[4:0]

INTEG_WIDTH_x

Integration time in µs. Set to MOD_WIDTH_x + 1.

0x010A, Bits[10:8],

Bits[14:12]

CHx_AMP_DISABLE_x Set 0x010A, Bit 9 to 1 to power down BPF for Channel 1, Bit 13

to 1 to power down BPF for Channel 2 if Channel 2 is enabled.

0x010B, Bits[12:0]

INTEG_OFFSET_x

Integration sequence start time. Set to (MOD_OFFSET_x −

INTEG_WIDTH_x – 250 ns).

0x010C, Bits[15:8]

MOD_WIDTH_x

Sets width of connect pulse in 1 μs increments. Typical values

of 2 μs or 3 μs.

0x010C, Bits[7:0]

0x010D, Bits[7:4]

MOD_OFFSET_x

SUBTRACT_x

Sets start time of first connect pulse in 1 μs increments.

In any given sequence of four pulses, negate the math

operation in the selected position. Selections are active high

(that is, subtract if 1) and the LSB of this register maps to the

first pulse. For a float mode sequence, add pulses when the LED

flashes and subtract pulses when the LED is disabled, according

to LED_DISABLE_x.

Rev. 0 | Page 33 of 101

ADPD4100/ADPD4101

Data Sheet

Time Slot A

Group

Register Address¹

Bit Field Name

Description

LED Settings

0x0105, Bit 15 and Bit 7;

0x0106, Bit 15 and Bit 7

LED_DRIVESIDEx_x

Select LED for time slot used.

0x0105, Bits[14:8], Bits[6:0];

0x0106, Bits[14:8], Bits[6:0]

LED_CURRENTx_x

Set LED current for selected LED.

0x0109, Bits[7:0]

0x0109, Bits[15:8]

0x010D, Bits[15:12]

LED_OFFSET_x

LED_WIDTH_x

LED_DISABLE_x

Sets start time of first LED pulse in 1 μs increments.

Sets width of LED pulse in 1 μs increments.

In any given sequence of four pulses, disable the LED pulse in

the selected position. Selections are active high (that is, disable

LED if 1) and the LSB of this register maps to the first pulse. For

a sequence of four pulses, it is recommended to turn on the

LED in the second and third pulses by writing 0x9 to this

register.

¹This is the Time Slot A register address. Add 0x020 for the identical register address for each subsequent time slot. For example, Register 0x0100 is the location for

SAMPLE_TYPE_A. For Time Slot B, this register is at Address 0x0120. For Time Slot C, this register is at Address 0x0140. For Time Slot D, this register is at

Address 0x0160, and so on.

Float Mode Limitations

When using float mode, the limitations of the mode must be

well understood. For example, a finite amount of charge can

PD BEGINS TO

FORWARD BIAS

accumulate on the capacitance of the photodiode, and there is a

maximum amount of charge that can be integrated by the

integrator. Based on an initial reverse bias of 215 mV on the

photodiode and assuming that the photodiode begins to

become nonlinear at ~200 mV of forward bias, there is ~450 mV

of headroom for the anode voltage to increase from its starting

point at the beginning of the float time before the charge ceases

to accumulate in a linear fashion. It is desirable to operate only

in the linear region of the photodiode (see Figure 38). To verify

that float mode is operating in the linear region of the

photodiode, the user can perform a simple check. Record data

at a desired float time and then record data at half the float

time. The recommended ratio of the two received signals is 2:1.

If this ratio does not hold true, the photodiode is likely

beginning to forward bias at the longer float time and becomes

nonlinear.

RECOMMENDED

FLOAT MODE

OPERATING REGION

FLOAT TIME (µs)

Figure 38. Integrated Charge on the Photodiode (PD) vs. Float Time

In addition, consider the maximum amount of charge the

integrator of the ADPD4100/ADPD4101 can integrate. The

integrator can integrate up to 7.6 pC. When this charge is referred

back to the input, consider the TIA gain. When the TIA gain is

at 200 kΩ, the input referred charge is at a 1:1 ratio to the

integrated charge on the integrator. For 100 kΩ gain, it is 2:1.

For 50 kΩ gain, it is 4:1. For 25 kΩ gain, it is 8:1. For the previous

example using a photodiode with 70 pF capacitance, use a 50 kΩ

TIA gain and set the float timing such that, for a single pulse, the

output of the ADC is at 70% of full scale, which is a typical

operating condition. Under these operating conditions, the

integrator integrates 5.3 pC per pulse for 21.2 pC of charge

accumulated on the photodiode capacitance. The amount of

time to accumulate charge on C_PDis inversely proportional to

CTR. TIA gain settings of 100 kΩ or 200 kΩ may be required

based on the CTR of the measurement and how much charge

can be accumulated in a given amount of time. Ultimately, the

type of measurement being made (ambient or pulsed LED), the

photodiode capacitance, and the CTR of the system determine

the float times.

The maximum amount of charge that can be stored on the

photodiode capacitance and remain in the linear operating

region of the sensor is estimated by

Q = C_PDV

where:

Q is the integrated charge.

C_PDis the capacitance of the photodiode.

V is the amount of voltage change across the photodiode before

the photodiode becomes nonlinear.

For a typical discrete optical design using a 7 mm²photodiode

with 70 pF capacitance and 450 mV of headroom, the maximum

amount of charge that can store on the photodiode capacitance

is 31.5 pC.

Rev. 0 | Page 34 of 101

Data Sheet

ADPD4100/ADPD4101

The BPF is bypassed for this measurement. When a stimulus

pulse is provided on the VCx pin, the capacitor response is a

positive spike on the rising edge that then settles back toward

TIA_VREF, followed by a negative spike on the falling edge of

the stimulus pulse. The integration sequence is centered such

that the positive and negative integration sequences completely

integrate the charge from the positive and negative TIA

responses, respectively (see Figure 41).

Pulse Connect Modulation

Pulse connect modulation is useful for ambient light measure-

ments or any other sensor measurements that do not require a

synchronous stimulus. This mode works by preconditioning the

sensor to some level selected by the PRECON_x bits and then

only connecting the sensor to the input of the TIA during the

modulation pulse. When not connected to the TIA, the sensor

is connected to a low input impedance node at the TIA_VREF

voltage. Any sensor current during this time is directed into the

AFE. Therefore, no charge accumulates on the sensor. This lack of

charge accumulation is in contrast to float mode, which fully

disconnects the sensor between modulation pulses. The

MOD_TYPE_x bits must be set to 0x2 for pulse connect mode.

The advantage of using this mode for nonsynchronous sensor

measurements is that it allows the user to take advantage of the

noise performance benefits of the full signal path using the BPF

and integrator. Figure 40 shows a timing diagram for pulse

connect modulation type measurements.

Pulsing of the VC1 and VC2 pins is controlled by the

VCx_PULSE_x, VCx_ALT_x, and VCx_SEL_x bits while

timing of the modulation is controlled by the MOD_OFFSET_x

and MOD_WIDTH_x bits. Table 21 shows the relevant registers

for modulating the stimulus to the sensor.

Mutual Capacitance-Based Proximity Measurement

One of the applications of the ADPD4100/ADPD4101 based on

capacitance measurement is the proximity measurement. A

mutual capacitance-based proximity measurement application,

for example, is based on modulation of the stimulus source in

principle, and is shown in Figure 39. However, this application

requires two electrodes along with the circuit shown in Figure 39,

one of which is connected to an input of the ADPD4100/

ADPD4101 and the other connected to VC1 or VC2. The

capacitor between INx and VCx, in this case, is the representation

of the capacitance formed between two electrodes, instead of a

physical capacitor.

Modulation of Stimulus Source

The ADPD4100/ADPD4101 have operating modes that

modulate the VC1 and VC2 signals. These modes are useful for

providing a pulsed stimulus to the sensor being measured. For

example, a bioimpedance measurement can be made where one

electrode to the human is being pulsed by the VC1 or VC2

output and the response is measured on a second electrode

connected to the TIA input. This mode is also useful for a

capacitance measurement, as shown in Figure 39, where one of

the VCx pins is connected to one side of the capacitor and the

other side is connected to the TIA input.

A proximity event represents the proximity of tissue to the two

electrodes mentioned. At the proximity event, a capacitance of

ΔC is formed between the electrodes and human tissue. ΔC varies

due to the varying proximity of tissue to the electrodes. Therefore,

total capacitance, which is the sum of the capacitance of the

capacitance between two electrodes represented as C and the

capacitance ΔC formed between human tissue and the electrode,

changes.

R

F

R

INT

INx

TIA

R

INT

TIA_VREF

C

R

INT

VCx

F

Figure 39. Modulate Stimulus for Capacitance Measurement

START OF TIME SLOT

PRECONDITION

PRE_WIDTH_x

(DEFAULT 8µs)

SENSOR

MOD_OFFSET_x

PERIOD

MOD_WIDTH_x

(AUTOMATICALLY CALCULATED)

CONNECT TIA

TO SENSOR

TIA OUTPUT

BPF OUTPUT

INTEG_WIDTH_x

–

INTEG_OFFSET_x

INTEGRATOR

SEQUENCE

–

+

INTEGRATOR

OUTPUT

CONVERSION(S)

ADC CHANNEL 1

ADC CHANNEL 2

(IF ENABLED)

REPEAT NUM_REPEAT_x TIMES

Figure 40. Timing Diagram for Pulse Connect Modulation

Rev. 0 | Page 35 of 101

ADPD4100/ADPD4101

Data Sheet

One can determine the changing proximity by reading the

change in ADC output when ΔC is induced through the change

in the proximity of the human tissue. To be able to determine

proximity, baseline measurement without tissue in proximity

must be taken either at the same input or at another input with

an electrode attached and configured the same way.

from the positive and negative TIA responses, which is essential

to integrate the maximum ac charge.

Then, ΔC is proportionate to the change in ADC output, which

is a function of the charge integrated, read at the proximity

event. For example, when VC2 is pulsed by 215 mV by setting

VC2_PULSE_x to 2, VC2_ALT_x to 2, and VC2_SEL_x to 2,

ΔC is calculated as follows:

Integrator timing width must be long enough to allow the

positive TIA response to fully settle before the negative edge of

the TIA response occurs. Also, as shown in Figure 41, the

integration timing must be centered so that the positive and

ΔC = (−Δ(ADC Output in LSB) × 0.92 fC/LSB ×

(R_INT/2R_F)/Number of Pulses)/(2 × 0.215 V)

Table 21 shows the relevant registers for this measurement.

negative integration sequences completely integrate the charge

START OF TIME SLOT

PRECONDITION

SENSOR

PRE_WIDTH_x

MOD_WIDTH_x

PERIOD

(AUTOMATICALLY CALCULATED)

(DEFAULT 8µs)

MOD_OFFSET_x

MODULATE

STIMULUS

TIA OUTPUT

INTEG_OFFSET_x

INTEG_WIDTH_x

–

INTEGRATION

SEQUENCE

+

–

+

INTEGRATOR

OUTPUT

ADC CHANNEL 1

Figure 41. Timing Diagram for Modulate Stimulus Operation

Table 21. Modulate Stimulus Settings

Time Slot A

Group

Register Address¹

Bit Field Name

SAMPLE_TYPE_x

AFE_PATH_CFG_x

INPxx_x

Description

Modulate Stimulus 0x0100, Bits[13:12]

Setup

Leave at the default setting (0) for default sampling mode.

Set to 0x0E6 for TIA, integrator, and ADC. Bypass BPF.

Enable desired inputs.

0x0101, Bits[8:0]

0x0102, Bits[15:0]

0x0103, Bits[14:12]

0x0103, Bits[11:10], Bits[5:4]

PRECON_x

Set to 0x5 to precondition sensor to TIA_VREF.

VCx_PULSE_x

VCx pulse control. Set to 0x2 to pulse to the alternate voltage during a

modulation pulse.

0x0103, Bits[9:8], Bits[3:2]

0x0103, Bits[7:6], Bits[1:0]

0x0104, Bits[5:0]

VCx_ALT_x

Select the alternate state for VCx during the modulation pulse.

Set to 0x1 to set VCx to TIA_VREF as primary state.

Select TIA gain.

VCx_SEL_x

TIA_GAIN_CHx_x

AFE_TRIM_VREF_x

MOD_OFFSET_x

MOD_WIDTH_x

0x0104, Bits[9:8]

Set to 0x2 to set TIA_VREF = 0.9 V.

Modulate Stimulus 0x010C, Bits[7:0]

Sets start time of first modulation pulse in 1 μs increments.

Timing

0x010C, Bits[15:8]

Sets width of modulation pulse in 1 μs increments. Typical values of 6 μs to

12 μs.

0x010A, Bits[4:0]

INTEG_WIDTH_x

Integration time in ꢀs. Set to MOD_WIDTH_x + 1 or MOD_WIDTH_x + 2.

0x010A, Bits[10:8], Bits[14:12]

CHx_AMP_DISABLE_x Set 0x010A, Bit 9 to 1 to power down BPF for Channel 1, Bit 13 to 1 to power

down BPF for Channel 2 if Channel 2 is enabled.

0x010B, Bits[12:0]

INTEG_OFFSET_x

Integration sequence start time. Set to MOD_OFFSET_x − 1 (if INTEG_WIDTH =

MOD_WIDTH − 1) or MOD_OFFSET_x – 2 (if INTEG_WIDTH = MOD_WIDTH − 2)

and then sweep INTEG_OFFSET_x, Bits[4:0] in 31.25 ns steps to find optimal

operating point.

0x0107, Bits[15:8]

0x0107, Bits[7:0]

NUM_INT_x

Set to 1 for a single integration per ADC conversion.

NUM_REPEAT_x

Number of sequence repeats. SNR increases as √n, where n =

NUM_REPEAT_x × NUM_INT_x.

0x0108, Bits[13:12]

MOD_TYPE_x

Set to 0x0 for continuous TIA connection.

¹This is the Time Slot A register address. Add 0x020 for the identical register address for each subsequent time slot. For example, Register 0x0100 is the location for

SAMPLE_TYPE_A. For Time Slot B, this register is at Address 0x0120. For Time Slot C, this register is at Address 0x0140. For Time Slot D, this register is at

Address 0x0160, and so on.

Rev. 0 | Page 36 of 101

Data Sheet

ADPD4100/ADPD4101

capacitance-based measurement. The integration sequence

must be centered in such a way that all the dc shift is canceled

and remaining small ac charge due to the change in proximity is

integrated. Figure 43 shows integration sequence timing with

respect to the TIA_VREF pulse to cancel dc shift and integrate

ac charge. The constant part in the TIA output represents the dc

charge, and it must be canceled by the integration sequence so

that only the surge charge accumulation at the positive and the

negative edges of the TIA_VREF pulse are integrated.

Self Capacitance-Based Proximity Measurement

Capacitive proximity measurements can be performed by

measuring self capacitance. As in mutual capacitance-based

proximity measurement, the BPF is bypassed by setting

AFE_PATH_CFG_x to 0E6.

Self capacitance based proximity measurement, however,

requires only one electrode connected to one of the inputs of

ADPD4100/ADPD4101. Capacitance measurement in this case

is performed by creating the voltage difference. To create the

voltage difference, pulse TIA_VREF while the input used is

preconditioned to TIA_VREF, and read the change in the ADC

output when ΔC is induced through the change in the

proximity of the human tissue.

However, the baseline measurement without tissue in proximity

is needed to determine true ΔC, which is proportionate to the

change in ADC output read at the proximity event.

Calculate ΔC as follows. For example, when TIA_VREF is

pulsed from 0.9 V to 1.14 V by setting VREF_PULSE_VAL_x to

0, AFE_TRIM_VREF_x to 2, and VREF_PULSE_x to 1, ΔC

then becomes

This measurement modality makes use of the capacitance of the

human body to the earth, and ΔC formed due to tissue proximity.

The human body capacitance allows the use of TIA_VREF

pulsing at the input as a voltage difference needed to measure

ΔC. Figure 42 shows a representation of this measurement.

ΔC = (Δ(ADC Output in LSB) × 0.92 fC/LSB ×

(R_INT/2R_F)/Number of Pulses)/(2 × (1.14 V − 0.9 V))

Table 22 summarizes the relevant registers for this measurement.

Integrator chop mode can be enabled for this measurement.

Because TIA_VREF is pulsed at the input, all the extra voltage

at pulsing shows up the same way at the TIA output. Therefore,

TIA has only a positive response compared to the mutual

C

INT

R

ELECTRODE

F

C

R

INT

INx

TIA

R

INT

TIA_VREF

INT

F

C

INT

Figure 42. Self Capacitance Measurement

START OF TIME SLOT

PRECONDITION

SENSOR

PRE_WIDTH_x

(DEFAULT 8µs)

MOD_WIDTH_x

PERIOD

MOD_OFFSET_x

(AUTOMATICALLY CALCULATED)

PULSE TIA_VREF

TIA OUTPUT

INTEG_OFFSET_x

INTEG_WIDTH_x

–

INTEGRATION

SEQUENCE

+

–

+

Figure 43. Timing Diagram for Self Capacitance-Based Proximity Measurement

Table 22. Relevant Registers for Self Capacitance Based Proximity Measurement

Group

Time Slot A Register Address¹

Bit Field Name

Description

Self Capacitance-Based

Proximity Setup

0x0100, Bits[13:12]

SAMPLE_TYPE_x

Leave at the default setting (0) for default

sampling mode.

0x0101, Bits[8:0]

AFE_PATH_CFG_x

Set to 0x0E6 for TIA, integrator, and ADC.

Bypass BPF.

0x0102, Bits[15:0]

0x0103, Bits[14:12]

0x0104, Bits[5:0]

0x0104, Bits[7:6]

0x0104, Bits[9:8]

0x0104, Bits[10]

INPxx_x

PRECON_x

TIA_GAIN_CHx_x

VREF_PULSE_VAL_x

AFE_TRIM_VREF_x

VREF_PULSE_x

Enable desired inputs.

Set to 0x5 to precondition sensor to TIA_VREF.

Select TIA gain.

Select 0x0 to pulse TIA_VREF to 1.14 V.

Set to 0x2 to set TIA_VREF = 0.9 V.

Set to 0x1 to pulse TIA_VREF.

Rev. 0 | Page 37 of 101

ADPD4100/ADPD4101

Data Sheet

Group

Time Slot A Register Address¹

Bit Field Name

Description

Self Capacitance-Based

Proximity Timing

0x010C, Bits[7:0]

MOD_OFFSET_x

Sets start time of first modulation pulse in 1 μs

increments. Typical value of 16 μs.

0x010C, Bits[15:8]

MOD_WIDTH_x

Sets width of modulation pulse in 1 μs

increments. Typical value of 6 μs.

0x010A, Bits[4:0]

INTEG_WIDTH_x

Integration time in µs. Typical value of 10 μs .

0x010A, Bits[10:8], Bits[14:12]

CHx_AMP_DISABLE_x Set 0x010A, Bit 9 to 1 to power down BPF for

Channel 1, Bit 13 to 1 to power down BPF for

Channel 2 if Channel 2 is enabled.

0x010B, Bits[12:0]

INTEG_OFFSET_x

Integration sequence start time. Set to typical

value of 9 μs and then sweep INTEG_OFFSET_x,

Bits[4:0] in 31.25 ns steps to find optimal

operating point.

0x0107, Bits[15:8]

0x0107, Bits[7:0]

0x0108, Bits[13:12]

NUM_INT_x

Set to 1 for a single integration per ADC

conversion

Number of sequence repeats. SNR increases as

√n, where n = NUM_REPEAT_x × NUM_INT_x.

NUM_REPEAT_x

MOD_TYPE_x

Set to 0x0 for continuous TIA connection.

¹This is the Time Slot A register address. Add 0x020 for the identical register address for each subsequent time slot. For example, Register 0x0100 is the location for

SAMPLE_TYPE_A. For Time Slot B, this register is at Address 0x0120. For Time Slot C, this register is at Address 0x0140. For Time Slot D, this register is at

Address 0x0160, and so on.

integrations, using most of the available dynamic range (75%)

per ADC conversion while leaving 25% of headroom for margin

so that the integrator does not saturate as the input level varies.

As each pulse is applied to the LED, the charge from the

response is integrated and held. The charge from the response

to each subsequent pulse is added to the previous total

integrated charge, as shown in Figure 44, until NUM_INT_x

integrations is reached.

Multiple Integration Mode

Multiple integration mode provides multiple analog

integrations of incoming charge per ADC conversion. This

mode is most useful when there is a small response that uses a

small amount of the available dynamic range per stimuli event.

Multiple integration mode allows multiple integrations of

charge prior to an ADC conversion so that a larger amount of

the available dynamic range of the integrator is utilized.

In multiple integration mode, the minimum period is

automatically calculated. In the example shown, the minimum

period is calculated at 2 × INTEG_WIDTH_x so that

subsequent pulses occur immediately following the completion

of the previous integration. Extra time is automatically added to

accommodate the ADC conversions at the end of NUM_INT_x

integrations.

Figure 44 shows multiple integration mode using the LED as

the stimulus. The number of LED pulses and subsequent

integrations of charge from the photodiode response is

determined by the setting of the NUM_INT_x bits. Following

the final integration, there is a single ADC conversion. This

process is repeated NUM_REPEAT_x times.

Prior to setting the number of integrations using the NUM_INT_x

bits, set the TIA gain to 200 kΩ and determine the optimal LED

current setting, which is close to the maximum current. When

the TIA gain and LED current are set, measure how much of the

integrator dynamic range is used to integrate the charge created

by a single LED pulse. If the amount of integrator dynamic range

used for a single pulse is less than half the available dynamic

range, it may be desirable to use multiple integrations prior to

an ADC conversion. For example, if the amount of integrator

dynamic range used for a single pulse is 1/8 of the available

dynamic range, set NUM_INT_x to 0x6 to use six pulses and

Use NUM_REPEAT_x to increase the iterations to improve the

overall SNR. The entire multiple integration per ADC conversion

process repeats NUM_REPEAT_x number of times. Increasing

NUM_REPEAT_x serves the same purpose as multiple pulses

in continuous connect mode, where n pulses improve the SNR

by √n. In multiple integration mode, the SNR increases by √n,

where n = NUM_REPEAT_x. The total number of LED pulses

in this mode is equal to NUM_INT_x × NUM_REPEAT_x.

Integrator chop mode is recommended for multiple integration

mode for optimal SNR performance.

Rev. 0 | Page 38 of 101

Data Sheet

ADPD4100/ADPD4101

START OF TIME SLOT

PRECONDITION

PRE_WIDTH_x

(DEFAULT 8µs)

CALCULATED

PERIOD

LED_OFFSET_x

LED_WIDTH_x

LED

TIA OUTPUT

BPF OUTPUT

INTEG_OFFSET_x

INTEGRATOR

SEQUENCE

+

–

+

–

+

–

+

–

INTEG_WIDTH_x

INTEGRATOR

OUTPUT

ADC CONVERT

NUM_INT_x

NUM_REPEAT_x TIMES

Figure 44. Multiple Integration Mode with LED as Stimulus

Table 23. Relevant Settings for Multiple Integration Mode

Time Slot A

Group

Register Address¹

0x0100, Bits[13:12]

0x0101, Bits[8:0]

0x0102, Bits[15:0]

0x0103, Bits[14:12]

Bit Field Name

SAMPLE_TYPE_x

AFE_PATH_CFG_x

INPxx_x

Description

Multiple Integration

Mode Using LED as

Stimulus

Leave at the default setting (0) for default sampling mode.

Set to 0x0DA for TIA, BPF, integrator, and ADC.

Enable desired inputs.

Set to 0x5 to precondition anode of the photodiode to

TIA_VREF.

PRECON_x

0x0103, Bits[7:6], Bits[1:0]

0x0104, Bits[5:0]

0x0104, Bits[9:8]

VCx_SEL_x

TIA_GAIN_CHx_x

AFE_TRIM_VREF_x

Set to 0x2 to set ~215 mV reverse bias across photodiode.

Set the TIA gain to 200 kΩ.

Set to 0x3 to set TIA_VREF = 1.27 V for maximum dynamic

range.

0x0108, Bits[13:12]

0x0107, Bits[15:8]

MOD_TYPE_x

NUM_INT_x

Set to 0 for continuous TIA connection to inputs following

preconditioning.

Timing

Set to a number that utilizes most of the dynamic range of

integrator available, leaving some margin for fluctuations in

input level.

0x0107, Bits[7:0]

NUM_REPEAT_x

Set NUM_REPEAT_x to the number of times to repeat the

multiple integration sequence. SNR increases by a factor of

√(NUM_REPEAT_x). Total number of pulses is equal to

NUM_REPEAT_x × NUM_INT_x.

0x010A, Bits[4:0]

0x010B, Bits[12:0]

INTEG_WIDTH_x

INTEG_OFFSET_x

Integration time in µs. Set to LED_WIDTH_x + 1.

Integration sequence start time = INTEG_OFFSET_x. Optimize as

described in the Optimizing Position of Integration Sequence

section.

LED Settings

0x0105, Bit 15 and Bit 7;

0x0106, Bit 15 and Bit 7

0x0105, Bits[14:8], Bits[6:0];

0x0106, Bits[14:8], Bits[6:0]

LED_DRIVESIDEx_x

LED_CURRENTx_x

SUBTRACT_x

Select LED for time slot used.

Set LED current for selected LED.

Integrator Chop Mode

0x010D, Bits[7:4]

Four-pulse subtract pattern. Set to 1 to negate the math

operation in the matching position in a group of four pulses.

The LSB maps to the first pulse.

0x010D, Bits[3:0]

REVERSE_INTEG_x

Four-pulse integration reverse pattern. Set to 1 to reverse the

integrator positive and negative pulse order in the matching

position in a group of four pulses. The LSB maps to the first

pulse.

¹This is the Time Slot A register address. Add 0x020 for the identical register address for each subsequent time slot. For example, Register 0x0100 is the location for

SAMPLE_TYPE_A. For Time Slot B, this register is at Address 0x0120, For Time Slot C, this register is at Address 0x0140. For Time Slot D, this register is at

Address 0x0160, and so on.

Rev. 0 | Page 39 of 101

ADPD4100/ADPD4101

Data Sheet

in the dark output data registers. Both signal and dark values

can be written to the FIFO.

DIGITAL INTEGRATION MODE

The ADPD4100/ADPD4101 support a digital integration mode

to accommodate sensors that require longer pulses than can be

supported in the typical analog integration modes. Digital

integration mode allows the system to use a larger LED duty

cycle than the analog integration modes, which may result in

the highest achievable levels of SNR, at the expense of lower

ambient light rejection.

The ADPD4100/ADPD4101 support one-region and two-

region digital integration modes. In one-region digital

integration mode, an equal number of dark and lit samples are

taken where all of the dark samples are taken in the dark region

just prior to the lit region. One-region digital integration mode

is illustrated in the timing diagram in Figure 46. In two-region

digital integration mode, an equal number of dark and lit

samples are taken. However, the dark region is split such that

half of the samples are taken in the dark region prior to the lit

region, and the other half is taken in the dark region following

the lit region. The two-region digital integration mode results in

higher ambient light rejection than the one-region digital

integration mode in situations with a varying ambient light

level. A timing diagram for two-region digital integration mode

is shown in Figure 47.

R

F

INx

ADC

TIA

R

BUF

TIA_VREF

F

VCx

Figure 45. Signal Path for Digital Integration Mode

In digital integration mode, the BPF is bypassed and the

integrator is configured as a buffer, resulting in the signal path

shown in Figure 45. Digital integration regions are configured

by the user and separated into lit and dark regions. The LED is

pulsed in the lit region, and the LED is off in the dark region.

ADC samples are taken at 1 μs intervals within the lit and dark

regions and are then digitally integrated. The integration of the

ADC samples from the dark region is subtracted from the

integration of the ADC samples from the lit region and the

result is written into the relevant signal output data registers.

The sum of the samples from just the dark region are available

Table 24 shows the relevant register settings for the digital

integration modes of operation. Note that only a single channel

can be used in digital integration mode. Two channels are not

supported for digital integration mode of operation. The MIN_

PERIOD_x bits must also be manually set with the correct

period because the minimum period is not automatically

calculated in digital integration mode.

START OF TIME SLOT

PRECONDITION

MIN_PERIOD_x (MUST BE SET,

NOT AUTOMATICALLY CALCULATED)

LED_WIDTH_x

LED_OFFSET_x

PRECONDITION

PRE_WIDTH_x

LED

ADC

CONVERSIONS

NUM_INT_x

DARK1_OFFSET_x

LIT_OFFSET_x

NUM_REPEAT_x

Figure 46. One-Region Digital Integration Mode Timing Diagram

START OF TIME SLOT

PRECONDITION

MIN_PERIOD_x (MUST BE SET,

NOT AUTOMATICALLY CALCULATED)

LED_OFFSET_x

LED_WIDTH_x

PRECONDITION

PRE_WIDTH_x

LED

ADC CONVERSIONS

DARK1_OFFSET_x

LIT_OFFSET_x

DARK2_OFFSET_x

NUM_INT_x

2 × NUM_INT_x

NUM_REPEAT_x

Figure 47. Two-Region Digital Integration Mode Timing Diagram

Rev. 0 | Page 40 of 101

Data Sheet

ADPD4100/ADPD4101

Table 24. Relevant Settings for Digital Integration Modes

Time Slot A

Group

Register Address¹

Bit Field Name

Description

Signal Path

Setup

0x0100, Bits[13:12]

SAMPLE_TYPE_x

Set to 0x1 for one-region digital integration mode. Set to 0x2 for

two-region digital integration mode.

0x0101, Bits[8:0]

AFE_PATH_CFG_x

Set to 0x0E6 for TIA, integrator, and ADC. Bypass BPF. Integrator

is automatically configured as a buffer when one-region or two-

region digital integration mode is selected.

0x0102, Bits[15:0]

0x0103, Bits[14:12]

0x0103, Bits[7:6], Bits[1:0]

0x0104, Bits[5:0]

0x0104, Bits[9:8]

0x0104, Bits[12:11]

0x010A, Bit 11

INPxx_x

PRECON_x

Enable desired inputs.

Set to 0x5 to precondition anode of photodiode to TIA_VREF.

Set to 0x2 to set ~215 mV reverse bias across photodiode.

Select TIA gain.

Set to 0x3 to set TIA_VREF = 1.265 V.

Set to 0x0 or 0x1 to set buffer gain = 1.

Set to 1 to convert integrator to buffer.

VCx_SELECT_x

TIA_GAIN_CHx_x

AFE_TRIM_VREF_x

CH1_TRIM_INT_x

AFE_INT_C_BUF_x

0x010A, Bits[10:8]

0x0107, Bits[15:8]

CH1_AMP_DISABLE_x Set 0x010A, Bit 9 to 1 to power down BPF.

Timing

NUM_INT_x

Set to the number of desired ADC conversions in the dark and lit

regions.

0x0107, Bits[7:0]

0x0108, Bits[9:0]

NUM_REPEAT_x

MIN_PERIOD_x

Number of sequence repeats.

Set the period. Automatic period calculation is not supported in

digital integration mode.

0x0113, Bits[8:0]

0x0114, Bits[6:0]

0x0114, Bits[15:7]

LIT_OFFSET_x

DARK1_OFFSET_x

DARK2_OFFSET_x

Set to the time of the first ADC conversion in the lit region.

Set to the time of the first ADC conversion in the Dark 1 region.

Set to the time of the first ADC conversion in the Dark 2 region.

Only used in two-region digital integration mode.

LED Settings 0x0105, Bit 15 and Bit 7;

0x0106, Bit 15 and Bit 7

LED_DRIVESIDEx_x

LED_CURRENTx_x

Select LED for time slot used.

0x0105, Bits[14:8], Bits[6:0];

0x0106, Bits[14:8], Bits[6:0]

Set LED current for selected LED.

0x0109, Bits[7:0]

0x0109, Bits[15:8]

LED_OFFSET_x

LED_WIDTH_x

Sets start time of first LED pulse in 1 μs increments.

Sets width of LED pulse in 1 μs increments.

¹This is the Time Slot A register address. Add 0x020 for the identical register address for each subsequent time slot. For example, Register 0x0100 is the location for

SAMPLE_TYPE_A. For Time Slot B, this register is at Address 0x0120. For Time Slot C, this register is at Address 0x0140. For Time Slot D, this register is at

Address 0x0160, and so on.

Timing Recommendations for Digital Integration Modes

DARK2_OFFSET_x = (LED_OFFSET_x + LED_WIDTH_x + t_D)

When setting the timing for digital integration mode, it is

important to place the ADC samples such that the signal being

sampled is given time to settle prior to the sample being taken.

Settling time of the input signal is affected by photodiode

capacitance and TIA settling time. Figure 48 shows an example

of proper placement of the ADC sampling edges. Calculations

for the offset values are as follows:

This setting only applies to two-region digital integration mode.

LED_OFFSET_x

LED_WIDTH_x

LED

OUTPUT

TIA

OUTPUT

ADC

SAMPLES

t_D

DARK1_OFFSET_x

LIT_OFFSET_x

DARK2_OFFSET_x

DARK1_OFFSET_x = (LED_OFFSET_x – (NUM_INT_x + 2))

Add a value of 2 to the number of ADC conversions such that

there is 2 μs of margin added to placement of the Dark 1 region

samples with respect to the beginning of the LED pulse.

Figure 48. Proper Placement of ADC Sampling Edges in Digital Integration Mode

LIT_OFFSET_x = (LED_OFFSET_x + t_D)

where t_Dis the delay built into the offset setting to allow settling

time of the signal. This value must be characterized in the final

application. A value in the range of 3 µs to 5 µs is typically

recommended as the t_Dvalue.

Rev. 0 | Page 41 of 101

ADPD4100/ADPD4101

Data Sheet

Buffer Gain is either 0.7 or 1 based on the setting of

CHx_TRIM_INT_x.

TIA ADC MODE

Figure 49 shows TIA ADC mode, which bypasses the BPF and

routes the TIA output through a buffer, directly into the ADC.

TIA ADC mode is useful in applications, such as ambient light

sensing, and measuring other dc signals, such as leakage

resistance. In photodiode measurement applications using the

BPF, all background light is blocked from the signal chain and,

therefore, cannot be measured. TIA ADC mode can measure

the amount of background and ambient light. This mode can also

measure currents from other dc sources, such as leakage

resistance.

Equation 3 is an approximation and does not account for

internal offsets and gain errors. The calculation also assumes

that the ADC offset registers are set to 0.

Configuring one time slot in TIA ADC mode is useful for

monitoring ambient and pulsed signals at the same time. The

ambient signal is monitored during the time slot configured for

TIA ADC mode, while the pulsed signal, with the ambient

signal rejected, is monitored in the time slot configured for

measuring the desired LED pulsed signal.

R

F

PROTECTING AGAINST TIA SATURATION IN

NORMAL OPERATION

INx

ADC

TIA

R

BUF

TIA_VREF

One concern when operating in high light conditions, especially

with larger photodiodes, is that the TIA stage may become

saturated while the ADPD4100/ADPD4101 continue to

F

communicate data. The resulting saturation is not typical. The TIA,

based on its settings, can only handle a certain level of photodiode

current. Based on the way the ADPD4100/ADPD4101 are config-

ured, if there is a current level from the photodiode that is larger

than the TIA can handle, the TIA output during the LED pulse

effectively extends the current pulse, making it wider. The AFE

timing is then violated because the positive portion of the BPF

output extends into the negative section of the integration window.

Thus, the photosignal is subtracted from itself, causing the output

signal to decrease when the effective light signal increases.

Figure 49. TIA ADC Mode Block Diagram

When the devices are in TIA ADC mode, the BPF is bypassed

and the integrator stage is reconfigured as a buffer. If both

Channel 1 and Channel 2 are enabled in a single time slot, the

ADC samples Channel 1 and then Channel 2 in sequential

order in 1 µs intervals.

The recommended TIA ADC mode is one in which the BPF is

bypassed and the integrator is configured as an inverting buffer.

This mode is enabled by writing 0x0E6 to AFE_PATH_CFG_x

(Register 0x0101, Bits[8:0] for Time Slot A) to enable a signal

path that includes the TIA, integrator, and ADC. Additionally,

to configure the integrator as a buffer, set INTEG_SETUP_x

(Register 0x010A, Bit 11 for Time Slot A). With the ADC offset

bits, ADC_OFF1_x and ADC_OFF2_x, set to 0 and TIA_VREF

set to 1.265 V, the output of the ADC is at ~3000 codes for a

single pulse and a zero input current condition. As the input

current from the photodiode increases, the ADC output

increases toward 16,384 LSBs.

Protecting Against TIA Saturation in Normal Operation

with TIA ADC Mode

TIA ADC mode monitoring is one of the ways to protect against

environments that may cause saturation. To measure the response

from the TIA and verify that this stage is not saturating, place the

device in TIA ADC mode and slightly modify the timing.

Specifically, sweep INTEG_OFFSET_x until a maximum is

achieved. This procedure aligns the ADC sampling time with

the LED pulse to measure the total amount of light falling on the

photodetector (for example, background light and LED pulse).

When configuring the integrator as a buffer, there is the option

of either using a gain of 1 or a gain of 0.7. Using the gain of 0.7

increases the usable dynamic range at the input to the TIA.

However, it is possible to overrange the ADC in this configuration

and care must be taken to not saturate the ADC. To set the buffer

gain, use the CHx_TRIM_INT_x bits. Setting CHx_TRIM_

INT_x to 0x0 or 0x1 sets a gain of 1. Setting CHx_TRIM_INT_x to

0x2 or 0x3 configures the buffer with a gain of 0.7.

If this minimum value is below 16,384 LSBs, the TIA is not

saturated. However, take care, because even if the result is not

16,384 LSBs, operating the device near saturation can quickly

result in saturation if light conditions change. A safe operating

region is typically at ¾ full scale and lower. The ADC resolution

when operating in TIA ADC mode with a buffer gain = 1 is

shown in Table 25. These codes are not the same as in modes

with the BPF and integrator enabled because the BPF and

integrator are not unity-gain elements.

Calculate the ADC output (ADC_OUT) as follows:

ADC_OUT= 8192 − (((2 × TIA_VREF − 2 × I_{INPUT_TIA}× R_F−

1.8 V)/146 µV/LSB) × Buffer Gain)

(3)

Table 25. ADC Resolution in TIA ADC Mode

where:

TIA Gain (kΩ)

ADC Resolution (nA/LSB)

TIA_VREF is the internal voltage reference signal for the TIA

(the default value is 1.265 V).

12.5

25

50

100

200

5.84

2.92

1.46

0.73

0.37

I

_{INPUT_TIA}is the input current to the TIA.

R_Fis the TIA feedback resistor.

Rev. 0 | Page 42 of 101

Data Sheet

ADPD4100/ADPD4101

Figure 50 illustrates the internal circuitry for TIA ceiling

detection. V_TIAO+and V_TIAO− represent the positive and negative

outputs of the TIA, respectively, and V_THis the threshold voltage

that the TIA output voltages are being compared to.

Protecting Against TIA Saturation with TIA Ceiling

Detection

While the TIA ADC mode monitoring helps to avoid

saturation, there may be cases where the voltage at the output

terminals of the TIA may exceed the typical operation levels

that ensure no current saturation for some amount of time

while the actual measurement is in the process. If the current

fed into the inputs of the TIA is high enough, it could result in

exceeding the typical operating points of TIA depending on the

TIA gain and the TIA reference voltage settings. In this case,

measurements can be distorted or may not be done. High levels

of photodiode current or high levels of ambient current may

cause the output voltages of the TIA to go above a limit that is

close to saturation.

TIA_CEIL_DETECT_EN_x

V

TH

V

TIAO+

INT_TCLN1_x

(INT_TCLN2_x FOR CHANNEL 2)

V

TH

V

TIAO–

Figure 50. Schematic of TIA Ceiling Detection Circuit

Due to different TIA reference voltage settings and different

TIA gains, different amounts of input current can result in

exceeding the threshold. Higher TIA reference voltage

(TIA_VREF) and lower TIA gain increase the input current

level at which the TIA output voltage exceeds the threshold

voltage and, therefore, increase the range in terms of current.

The ADPD4100/ADPD4101 have a TIA ceiling detection

feature that uses voltage comparators at the outputs of the TIA

stage to detect whether the TIA output voltage exceeds a certain

range. This range ensures the TIA output to be far enough from

the ceiling of the total TIA range by some margin. Therefore, if

the TIA output voltage exceeds the range even for a small amount

of time, the user is informed about the status of voltage at the

TIA outputs and can take action to avoid a possible saturation.

Table 26 shows the typical input current needed to trigger TIA

ceiling detection for different TIA gain and different TIA_VREF

while using 2 µs LED pulses in continuous connect mode.

Table 26. Typical Input Currents to Trigger TIA Ceiling

Detection

Voltage comparators compare the positive and negative output

terminals to a certain threshold voltage, which sets the effective

TIA output voltage range, and send an output bit indicating

whether the TIA output voltage is beyond the range.

TIA Gain

(kΩ)

Input Current (µA) at

TIA_VREF = 0.9 V

Input Current (µA) at

TIA_VREF = 1.3 V

25

21.9

10.6

5.2

33.6

16.7

8.4

50

To enable this feature, TIA_CEIL_DETECT_EN_x must be set

to 1. Each time slot has its own TIA_CEIL_DETECT_EN_x bit

that can be controlled individually. The feature is turned on for

Channel 1, and Channel 2 if Channel 2 is also enabled within

the time slot. When the comparators are enabled, the TIA ceiling

detection information is latched onto the INT_TCLN1_x bits in

Register 0x0004 for Channel 1 and INT_TCLN2_x bits in

Register 0x0005 for Channel 2 separately for each time slot. The

interrupt output turns to 1 if either output exceeds the threshold

voltage.

100

200

2.6

4.2

Figure 51 illustrates the trigger points for TIA ceiling detection

with respect to different TIA_VREF values. Trigger points for

different TIA gains can be found in Table 26.

TIA OUTPUT VOLTAGE (V)

0,0

INPUT CURRENT (µA)

TIA _VREF = 0.9V

TIA _VREF = 1.3V

Figure 51. Illustration of Trigger Points for TIA Ceiling Detection for TIA_VREF = 0.9 V and TIA_VREF = 1.3 V, Points Marked by Black Crosses

Rev. 0 | Page 43 of 101

ADPD4100/ADPD4101

Data Sheet

measurement regardless of whether low impedance wet

electrodes or high impedance dry electrodes are used.

ECG MEASUREMENT WITH THE

ADPD4100/ADPD4101

In sleep float mode, the sensing capacitor floats all the time

except the charge transfer, accumulating charge from the ECG

signal. The accumulated charge is then transferred into the

ADPD4100/ADPD4101 during a specified time slot for charge

measurement. The device must be configured to float the inputs

for the ECG during the preconditioning period and during

sleep. The inputs are connected to the external capacitor only

during the charge transfer. At all other times, the inputs for the

ECG are floating, resulting in a float time of 1/t_P, where t_Pis the

sampling rate of the ADPD4100/ADPD4101. For example, the

float time in sleep float mode is ~3.3 ms for the sampling rate of

300 Hz.

The ADPD4100/ADPD4101 can be used for ECG applications

with the simple addition of an external RC network consisting

of two 500 kΩ resistors in series with the inputs and a 470 pF

capacitor across the inputs, as shown in Figure 52. The electrical

equivalent model for an electrode is shown together with the

RC circuit, external to the ADPD4100/ADPD4101.

The 500 kΩ resistors limit the current that can be injected into

or pulled from the body in the case of shorted input pins. The

470 pF capacitor serves as the sensing capacitor for the ECG

signal. The ECG signal is integrated onto the sensing capacitor.

The value of this capacitor is chosen such that an acceptable

SNR is achieved and the time constant of the RC network and

the electrode skin contact allows sufficient charge accumulation

on the sensing capacitor during the sampling period.

An advantage of using sleep float in ECG measurements is the

longer charging time for the sensing capacitor. In sleep float

mode, charge accumulation on the sensing capacitor happens

during the sleep and during all other enabled time slots. The

time slot associated with the sleep float mode is only used to

transfer the charge from the sensing capacitor to the ADPD4100/

ADPD4101 amplifier. Sleep float mode also allows the use of

other time slots for different sensor-based applications while

ECG is being measured because the sensing capacitor floats

regardless of the types of applications that the other time slots

enable.

The RC network of the 500 kΩ resistors and the 470 pF

capacitor also acts as a low-pass filter, which helps reduce the

high frequency noise due to electrode skin contact.

For multilead ECG measurement, each lead requires a separate

pair of inputs and the RC network of two 500 kΩ resistors and

the 470 pF capacitor, as shown in Figure 52.

SKIN/ELECTRODE

INTERFACE

ADPD4100/

R

P

ADPD4101

V

R

F

R

DC

S

RA

LA

Another advantage of using sleep float mode in ECG measure-

ments is the reduced power consumption and noise. In sleep

float mode, while the sensing capacitor is floating, it is discon-

nected from the amplifier and the amplifier is not powered.

Therefore, sleep float mode reduces the power consumption by

using the passive charging time to transfer the ECG signal from

the body onto the sensing capacitor while the amplifier and all

the later stages are powered down. The passive charging process

of the sampling capacitor associated with sleep float mode also

reduces the noise as the charging process is noise free.

R

IN

500kΩ

INx

C

R

P

470pF

TIA

R

P

500kΩ

R

IN

V

R

S

F

C

P

NOTES

1. RA is right arm. LA is left arm.

Figure 52. Circuit for Measuring Single-Lead ECG with the

ADPD4100/ADPD4101

Sleep Float Mode

A timing diagram for sleep float mode is shown in Figure 53.

The ADPD4100/ADPD4101 ECG measurement operates in

sleep float mode. Sleep float mode allows a robust ECG

The relevant register settings for sleep float mode are shown in

Table 27.

START OF TIME SLOT

SEQUENCE TIMING WAKE

CONNECT/FLOAT

TIME SLOT A (TS A)

MOD_WIDTH_x

TS B

TS X

SLEEP

WAKE

MOD_OFFSET_x

ACCUMULATED

CHARGE ON CAPACITOR

INTEGRATOR

OUTPUT

INTEG_OFFSET_x

INTEGRATOR

SEQUENCE

INTEG_WIDTH_x

ADC READ

Figure 53. Sleep Float Mode Timing Diagram

Rev. 0 | Page 44 of 101

Data Sheet

ADPD4100/ADPD4101

Table 27. Relevant Configuration Registers for ECG Measurement Using Sleep Float Mode

Time Slot A

Group

Register Address¹Bit Field Name

Description

Signal Path Setup 0x0100, Bits[13:12] SAMPLE_TYPE_x

0x0100, Bits[11:10] INPUT_R_SELECT_x

Leave at the default setting (0) for default sampling mode.

Set to 0x0 for 500 Ω series input resistor.

0x0101, Bits[8:0]

0x0101, Bits[15:12] PRE_WIDTH_x

AFE_PATH_CFG_x

Set to 0x0E6 for TIA, integrator, and ADC. Bypass the BPF.

Set to 0 to skip preconditioning period.

0x0102, Bits[15:0]

INPxx_x

Set to 0x7 to enable desired inputs connected to Channel 1 as defined

in PAIRxx.

0x0103, Bits[4:12]

0x0020, Bits[15:0]

0x0021, Bits[3:0]

0x0104, Bits[5:0]

0x0104, Bits[9:8]

0x0107, Bits[15:8]

0x0107, Bits[7:0]

PRECON_x

INP_SLEEP_xx

PAIRxx

TIA_GAIN_CHx_x

AFE_TRIM_VREF_x

NUM_INT_x

Set to 0x0 to float the inputs during preconditioning.

Set to 0x0 to float inputs during sleep.

Set to 1 to configure selected inputs as a differential pair.

Select TIA gain.

Set to 0x2 to set TIA_VREF = 0.9 V.

Float Mode

Configuration

Set to 1 for a single integration per group of ADC conversions.

Number of sequence repeats.

NUM_REPEAT_x

0x0108, Bits[13:12] MOD_TYPE_x

Set to 0x1 for float type operation.

0x0108, Bits[9:0]

MIN_PERIOD_x

Set to 0. Minimum period is not applicable to sleep float mode with a

single integration.

0x010A, Bits[4:0]

INTEG_WIDTH_x

Integration time in µs. Set to MOD_WIDTH_x + 1.

0x010A, Bits[10:8],

Bits[14:12]

CHx_AMP_DISABLE_x Set 0x010A, Bit 9 to 1 to power down BPF for Channel 1, Bit 13 to 1 to

power down BPF for Channel 2 if Channel 2 is enabled.

0x010B, Bits[12:0]

INTEG_OFFSET_x

Integration sequence start time. Set to (MOD_OFFSET_x −

INTEG_WIDTH_x – 250 ns).

0x010C, Bits[15:8]

MOD_WIDTH_x

Sets width of connect pulse in 1 μs increments. MOD_WIDTH_x ×

NUM_REPEAT_x determines the time to transfer the charge from the

external capacitor. Set MOD_WIDTH_x × NUM_REPEAT_x to

approximately three time constants based on the time constant created

between the external capacitor and the series input resistor (500 Ω or

6500 Ω based on setting of INPUT_R_SELECT_x).

0x010C, Bits[7:0]

MOD_OFFSET_x

Sets start time of first connect pulse in 1 μs increments. Set to

INTEG_WIDTH_x + 3.

¹This is the Time Slot A register address. Add 0x020 for the identical register address for each subsequent time slot. For example, Register 0x0100 is the location for

SAMPLE_TYPE_A. For Time Slot B, this register is at Address 0x0120. For Time Slot C, this register is at Address 0x0140. For Time Slot D, this register is at

Address 0x0160, and so on.

To accommodate the dc offset voltage without reducing the size

of the sensing capacitor, the recommendation is to reduce the

TIA gain to 50 kΩ or 100 kΩ, and to transfer the accumulated

charge in multiple short pulses. For example, to transfer 47 pC

of charge from the sensing capacitor to the integrator, the TIA

gain of 50 kΩ can accommodate 30 pC of charge per sample.

Setting R_IN= 6.5 kΩ limits the rate of charge transfer into the

TIA with an RC time constant of 2 × 6.5 kΩ × 470 pF = 6.1 μs.

Using multiple short modulation pulses, which can be as short

as 1 µs, allows a smaller percentage of the overall charge to be

transferred and integrated per pulse to avoid saturating the TIA.

Multiple transfer cycles are then used to fully discharge the

sensing capacitor. The ADPD4100/ADPD4101 automatically

sum the results of the transfer cycles and report the total charge.

The timing for this mode is the same as shown in Figure 53

except the device is set up for multiple modulation pulses.

Sleep Float Mode with Multiple Charge Transfers

In ECG measurement, there can be a dc offset voltage on the

order of tens or hundreds of millivolts or even greater when the

electrode skin contact impedance is high and/or the electrodes

are made of different materials with large half cell potential

mismatch. The dc offset voltage uses a significant amount of the

dynamic range available for the ECG measurement. The

maximum amount of charge that the ADPD4100/ADPD4101

can accommodate for a single sample is ~7.5 pC with the

200 kΩ TIA gain setting. The maximum allowable charge per

sample scales inversely with the gain of the TIA. The presence

of a large dc offset voltage creates excess charge on the sensing

capacitor, which can saturate the input to the ADC. For

example, 100 mV of dc offset voltage adds an additional 47 pC

of charge to the 470 pF capacitor.

Rev. 0 | Page 45 of 101

ADPD4100/ADPD4101

Data Sheet

#ADPD4100 ECG Measurement with high DC

offset

Recommended Configurations for ECG Measurement

The following is one of the recommended configurations for

ECG measurement if the dc offset voltage (V_DC, see Figure 52) is

negligible or low, less than 30 m V.

0009 0080 # 32MHz oscillator trim

000B 02B2 # 1MHz oscillator trim

000D 0D05 # Sampling rate 300 Hz

000F 0006 # 1MHz low frequency oscillator

0010 0000 # Timeslot A enabled

0020 2220 # Float inputs 1&2 during sleep

#ADPD4100 ECG Measurement with small DC

offset

0009 0080 # 32MHz oscillator trim

000B 02B2 # 1MHz oscillator trim

000D 0D05 # Sampling rate 300 Hz

000F 0006 # 1MHz low frequency oscillator

0010 0000 # Timeslot A enabled

0021 0001 # IN1/IN2 configured as a

differential pair

# Timeslot configuration #

0020 2220 # Float input 1&2 during sleep

### Timeslot A - Sleep float mode ECG with

multiple charge transfers

0021 0001 # IN1/IN2 configured as a

differential pair

0100 0400 # Input resistor 6500 Ω

0101 00E6 # skip preconditioning,

bandpass filter bypassed

# Timeslot configuration #

### Timeslot A - Sleep float mode ECG with

multiple charge transfers

0102 0007 # IN1&IN2 differential pair to

channel 1

0100 0000 # Input resistor 500 Ω

0103 0000 # float during preconditioning

0104 02C3 # TIA gain 25k, Vref = 0.88V

0105 0000 # LEDs off

0101 00E6 # skip preconditioning,

bandpass filter bypassed

0102 0007 # IN1&IN2 differential pair to

channel 1

0106 0000 # LEDs off

0103 0000 # float during preconditioning

0104 02C1 # TIA gain 100k, Vref = 0.88V

0105 0000 # LEDs off

0107 010C # 12 pulses

0108 1000 # float mode, minimum period

010A 0203 # Integrator pulse width,

bandpass filter powered down

0106 0000 # LEDs off

010B 01A0 # Integrator pulse timing

offset

0107 0102 # 2 pulses

0108 1000 # float mode, minimum period

010C 0210 # Modulation pulse width and

offset

010A 0203 # Integrator pulse width,

bandpass filter powered down

010D 0000 # Chopping mode disabled

010E 0000 # no ADC offset

010B 01A0 # Integrator pulse timing

offset

010F 0000 # no ADC offset

010C 0210 # Modulation pulse width and

offset

0110 0003 # Configure number of bytes

written to the registers

010D 0000 # Chopping mode disabled

010E 0000 # no ADC offset

To account for the cases where dc offset voltage is moderate,

different configurations can be utilized. In general, higher dc

offset voltage cases require low TIA gain and 6500 Ω input

resistor selection, whereas lower dc offset voltage cases can use

higher TIA gain and 500 Ω input resistor selection to achieve

the lowest noise performance. In addition, NUM_REPEAT_x

can be increased to allow the full discharge of the sampling

capacitor. Table 28 summarizes the relevant registers for

handling different dc offset voltage levels.

010F 0000 # no ADC offset

0110 0003 # Configure number of bytes

written to the registers

If the dc offset voltage is large, use the following recommended

configuration, which can handle up to 450 mV of dc offset

voltage. There are only three register setting changes, and the

rest is the same as the previous configuration. The input resistor

is changed to 6500 Ω by setting INPUT_R_SELECT_x to 1, TIA

gain is reduced to 25 kΩ by setting TIA_GAIN_CH1_x to 3,

and the number of modulation pulses is increased to 12 by

setting NUM_REPEAT_x to 12.

Rev. 0 | Page 46 of 101

Data Sheet

ADPD4100/ADPD4101

ECG and three-electrode lead off detection are measured as

follows:

Improving SNR with Integrator Chopping in ECG

Measurements

Integrator chopping can also improve SNR in ECG measurements

with the sleep float mode by eliminating low frequency noise

content. The procedure to enable integrator chop mode is the

same as explained previously in the Improving SNR Using

Integrator Chopping section. However, ECG measurements

with integrator chopping require additional considerations. The

sign of the dc offset voltages in Figure 52 can be positive or

negative. When the sign of the net dc offset voltage is negative,

integrator chop mode can result in clipping of the ECG signal.

To prevent clipping of the ECG signal, lit data must be used.

Figure 23 shows the datapath. In Figure 23, lit and dark values

can be optionally written to FIFO. This option allows the use of

negative signal values by writing both lit and dark values to the

FIFO, and the user can perform a signed subtract in external

processing of the data to calculate the signal value. Therefore,

integrator chopping can be used regardless of the sign of net dc

offset voltage.

1. ECG is measured in Time Slot A as defined in the ECG

Measurement with the ADPD4100/ADPD4101 section.

2. Lead off detection of the ECG electrodes is taken in

Time Slot B by making simultaneous single-ended

impedance measurements of ECG Electrode 1 (E1) and

Electrode 2 (E2) into Channel 1 and Channel 2, respectively.

When both ECG electrodes, E1 and E2, are making contact

with the skin during the measurement, an ECG signal is visible.

The impedance measurements of the E1 and E2 electrodes have

some readout indicating that contact is being made with the

skin and current is flowing into the ADPD4100/ADPD4101

through the body of low impedance when the stimulus is

applied. When either ECG electrode stops making contact with

the skin or is loose, there is no ECG signal in the acquired trace.

When contact between both electrodes and the skin is restored,

the ECG signal appears immediately. Because two inputs and

two channels are allocated to detect leadoff condition for two

electrodes, this measurement method can determine if one

electrode loses contact with skin or both electrodes lose contact.

This measurement can also detect which one of the electrodes

loses contact with skin if only one electrode loses contact.

Lead Off Detection

To perform a lead off detection measurement, the ADPD4100/

ADPD4101 measure the impedance of the electrode skin

contacts to determine whether one or more of the electrodes are

not making contact with the skin. Lead off measurement can be

performed in two different ways based on the number of

electrodes used.

Figure 55 illustrates a representation of ADC output changes in

different cases for leadoff condition. In Figure 55, before

Time t_A, both ECG electrodes make contact with the skin. At

Time t_A, E1 is disconnected from the skin. The time between t_A

and t_Bshows the case where only E1 is disconnected from the

skin. At Time t_B, E1 starts to make contact with skin and output

of the two channels go to their initial levels. At Time t_C, only E2

is disconnected from the skin and it stays disconnected until

Time t_D. At Time t_E, E2 starts making contact with the skin

again. At Time t_E, both E1 and E2 are disconnected from the

skin, and they stay disconnected until Time t_F. At Time t_F, both

E1 and E2 start making contact with the skin. Therefore, lead

off condition is detected in all electrode connection cases, and

three-electrode lead off measurement detects and distinguishes

all the different cases. The level of actual ADC outputs

Three-Electrode Lead Off Measurement

The three-electrode configuration requires a third electrode

connected to an unused VCx pin to provide a stimulus to the

body. The RC network of the ECG measurement is bypassed by

wiring the electrodes directly to a separate set of inputs through

25 kΩ resistors. The response from the stimulus is measured

from this separate set of inputs. Three-electrode lead off

measurement is capable of determining which electrode is loose

or has lost the contact with the skin. Figure 54 shows the circuit

for the three-electrode lead off detection measurement. R_BODYis

the resistance of the body.

ADPD4100/

ADPD4101

associated with Channel 1 and Channel 2 may differ because

the type and placement of the electrodes may be different in

each case, and R_BODYdiffers from person to person, which

affects the amount of current that each channel receives.

47pF

25kΩ

IN3

IN1

E1

500kΩ

CH1

CH2

CHANNEL 1

CHANNEL 2

R

470pF

BODY

500kΩ

IN2

IN4

E2

25kΩ

47pF

R

BODY

47pF

25kΩ

VC2

E3

Figure 54. Circuit Used for Three-Electrode Lead Off Detection Measurement

t_At_Bt_C

t_Dt_E

t_F

TIME

Figure 55. Graph of Three-Electrode Lead Off Measurement

Rev. 0 | Page 47 of 101

ADPD4100/ADPD4101

Data Sheet

Table 28. Relevant Register Settings to Handle Different DC Offset Voltage Levels in ECG Measurements

Time Slot A Register Address¹

Bit Field Name

Description

0x0100, Bits[11:10]

INPUT_R_SELECT_x

Set to 0x0 for 500 Ω series input resistor. Set to 0x1 for 6500 Ω series input

resistor.

0x0104, Bits[5:0]

0x0107, Bits[7:0]

TIA_GAIN_CHx_x

NUM_REPEAT_x

Select TIA gain.

Number of sequence repeats.

¹This is the Time Slot A register address. Add 0x020 for the identical register address for each subsequent time slot. For example, Register 0x0100 is the location for

SAMPLE_TYPE_A. For Time Slot B, this register is at Address 0x0120. For Time Slot C, this register is at Address 0x0140. For Time Slot D, this register is at

Address 0x0160, and so on.

0110 0003 # Configure number of bytes

written to the registers

The following configuration enables low dc offset ECG

measurement in Time Slot A and three-electrode lead off

detection in Time Slot B:

# ADPD4100 ECG Measurement with small DC

offset in Timeslot A and Three-Electrode

Lead-Off Measurement in Timeslot B

# Timeslot B – Three-Electrode Lead-Off

Detection on IN3/4

0120 4000

# CH2 active

0009 0080 # 32MHz oscillator trim

000B 02B2 # 1MHz oscillator trim

000D 0D05 # Sampling rate 300 Hz

000F 0006 # 1MHz low frequency oscillator

0010 0100 # Timeslot A and B enabled

0121 40DA

BPF-INT-ADC

# 8 µs preconditioning, TIA-

0122 0050

0123 5A45

pulse VC2_VREF by 215 mV

# IN3 to CH1, IN4 to CH2

# Precondition to TIA_VREF,

0124 E212

TIA_VREF=0.88V

# 50k TIA GAIN both channels,

0020 2200 # Float input 1&2 and 3&4

during sleep

0125 0000

0126 0000

# LEDs off

0021 0001 # IN1/IN2 configured as a

differential pair

# LEDs off

0127 0110

# 16 pulses, single

integration

# Timeslot configuration #

0128 0000

012A 0003

# continuous TIA connection

# Integrator pulse width

# Integrator pulse timing

# ADPD4100 ECG Measurement with small DC

offset

0100 0000 # Input resistor 500 Ω

012B 0216

offset

0101 00E6 # skip preconditioning,

bandpass filter bypassed

012C 0210

offset

# Modulation pulse width and

0102 0007 # IN1&IN2 differential pair to

channel 1

012D 0000

012E 0000

012F 0000

0130 0003

# Integrator chopping off

# No ADC Offset

0103 0000 # float during preconditioning

0104 02C1 # TIA gain 100k, TIA_VREF =

0.88V

# No ADC Offset

# Configure number of bytes

0105 0000 # LEDs off

written to the registers

0106 0000 # LEDs off

Two-Electrode Lead Off Measurement

0107 0102 # 2 pulses

This measurement method can detect the lead off condition

without requiring a third electrode at the expense of not being

able to differentiate if one electrode or both electrodes have lost

contact with skin. Two-electrode lead off measurement is useful

in cases where either a separate electrode is not available, a

smaller form factor with less components is desired, or the

power requirement is tighter because power consumption of

two-electrode lead off measurement is lower. In two-electrode

lead off measurement, the stimulus from an unused VCx pin to

the body can be provided through one of the ECG electrodes.

Only one separate input is used to detect the lead off condition

through the impedance measurement.

0108 1000 # float mode, minimum period

010A 0203 # Integrator pulse width,

bandpass filter powered down

010B 01A0 # Integrator pulse timing

offset

010C 0210 # Modulation pulse width and

offset

010D 0000 # Chopping mode disabled

010E 0000 # no ADC offset

010F 0000 # no ADC offset

Rev. 0 | Page 48 of 101

Data Sheet

ADPD4100/ADPD4101

Figure 56 shows a circuit that can be used for the two-electrode

lead off detection measurement. R_BODYis the resistance of the

body.

ADPD4100/

ADPD4101

47pF

25kΩ

IN3

IN1

t_At_Bt_C

t_Dt_E

t_F

E1

500kΩ

TIME

R

470pF

CH1

Figure 57. Graph of Two-Electrode Lead Off Measurement

BODY

IN2

500kΩ

The following configuration enables low dc offset ECG

measurement in Time Slot A and two-electrode lead off

detection in Time Slot B:

E2

47pF

VC2

25kΩ

VC2

# ADPD4100 ECG Measurement with small DC

offset in Timeslot A and Two-Electrode

Lead-Off Measurement in Timeslot B

Figure 56. Circuit Used for Two-Electrode Lead Off Detection Measurement

0009 0080 # 32MHz oscillator trim

000B 02B2 # 1MHz oscillator trim

000D 0D05 # Sampling rate 300 Hz

000F 0006 # 1MHz low frequency oscillator

0010 0100 # Timeslot A and B enabled

ECG and two-electrode lead off detection are measured as

follows:

1. ECG is measured in Time Slot A as defined in the ECG

Measurement with the ADPD4100/ADPD4101 section.

2. Lead off detection of the ECG electrodes is taken in

Time Slot B by making a single-ended measurement for

impedance between the E1 and E2 ECG electrodes into

Channel 1, as shown in Figure 56.

0020 2200 # Float input 1&2 and 3&4

during sleep

0021 0001 # IN1/IN2 configured as a

differential pair

When the ECG electrodes are making contact with the skin

during the measurement, an ECG signal and a value for the

impedance measurement indicating that some current is

flowing through R_BODYare visible. When either electrode stops

making contact with the skin, there is no ECG signal, and a

much smaller value at the ADC output is observed for the

impedance measurement indicating that there is no current

flowing through the low impedance R_BODY. When both electrode

skin contacts are restored, the ECG signal appears immediately.

Because only one input and one channel are allocated to detect

lead off condition for two electrodes, the impedance measurement

shows a much smaller value when either electrode loses contact

with skin and, thus, it is a common indicator for both electrodes.

# Timeslot configuration #

# ADPD4100 ECG Measurement with small DC

offset

0100 0000 # Input resistor 500 Ω

0101 00E6 # skip preconditioning,

bandpass filter bypassed

0102 0007 # IN1&IN2 differential pair to

channel 1

0103 0000 # float during preconditioning

0104 02C1 # TIA gain 100kΩ, TIA_VREF =

Figure 57 illustrates a representation of ADC output changes in

different cases. Before Time t_A, both ECG electrodes make

contact with the skin. At Time t_A, only E1 is disconnected from

the skin. At Time t_B, it starts to make contact with the skin again

and both electrodes make contact until t_C. At t_C, only E2 is

disconnected from the skin and it stays disconnected until t_D. At

t_D, E2 starts making contact with the skin again, and they stay

connected until tE. At t_E, both electrodes are disconnected. At

t_F, both electrodes start making contact again. Therefore, lead

off detection measurement can be achieved for all cases, and

lead off condition is represented by lower ADC output for the

impedance measurement.

0.88V

0105 0000 # LEDs off

0106 0000 # LEDs off

0107 0102 # 2 pulses

0108 1000 # float mode, minimum period

010A 0203 # Integrator pulse width,

bandpass filter powered down

010B 01A0 # Integrator pulse timing

offset

010C 0210 # Modulation pulse width and

offset

010D 0000 # Chopping mode disabled

010E 0000 # no ADC offset

010F 0000 # no ADC offset

Rev. 0 | Page 49 of 101

ADPD4100/ADPD4101

Data Sheet

0110 0003 # Configure number of bytes

written to the registers

0126 0000

# LEDs off

0127 0110

# 16 pulses, single

integration

0128 0000

012A 0003

# continuous TIA connection

# Integrator pulse width

# Integrator pulse timing

# Timeslot B – Two-Electrode Lead-Off

Detection on IN3

0120 0000

# 1 channel enabled

012B 0216

offset

0121 40DA

INT-ADC

# 8us precondition, TIA-BPF-

012C 0210

offset

# Modulation pulse width and

0122 0010

# IN3 to CH1, IN4

disconnected

012D 0000

012E 0000

012F 0000

0130 0003

# Integrator chopping off

# No ADC Offset

0123 5A45

pulse VC2_VREF by 215 mV

# Precondition to TIA_VREF,

# No ADC Offset

0124 E212

channels, TIA_VREF=0.88V

# 50 kΩ TIA GAIN both

# Configure number of bytes

written to the registers

0125 0000

# LEDs off

Rev. 0 | Page 50 of 101

Data Sheet

ADPD4100/ADPD4101

REGISTER MAP

Table 29. ADPD4100 Register Map Summary

Bit 15

Bit 14

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 1

Bit 8

Bit 0

Reg

Name

Bits

Bit 7

Bit 6

Reset

R/W

0x0000

FIFO_

STATUS

[15:8]

CLEAR_FIFO INT_FIFO_ INT_FIFO_

Reserved

FIFO_BYTE_COUNT[10:8]

0x0000

R/W

UFLOW

OFLOW

[7:0]

FIFO_BYTE_COUNT[7:0]

0x0001

0x0002

0x0003

0x0004

0x0005

INT_

STATUS_

DATA

[15:8]

INT_FIFO_TH

Reserved

INT_

DATA_L

INT_

DATA_K

INT_

DATA_J

INT_

DATA_I

0x0000

R/W

[7:0]

INT_DATA_H INT_DATA_G INT_

DATA_F

INT_

DATA_E

INT_

DATA_D

INT_

DATA_C

INT_

DATA_B DATA_A

INT_

STATUS_

LEV0

[15:8]

[7:0]

Reserved

INT_LEV0_L INT_

LEV0_K

INT_LEV0_E INT_LEV0_D INT_

LEV0_C

INT_LEV1_L INT_

LEV1_K

INT_LEV1_E INT_LEV1_D INT_

LEV1_C

INT_TCLN1_L INT_

INT_

LEV0_J

INT_

LEV0_I

INT_LEV0_H INT_LEV0_G INT_

INT_

LEV0_B

INT_

LEV0_A

LEV0_F

INT_

STATUS_

LEV1

[15:8]

[7:0]

Reserved

INT_

LEV1_J

INT_

LEV1_I

INT_LEV1_H INT_LEV1_G INT_

INT_

LEV1_B

INT_

LEV1_A

LEV1_F

INT_

STATUS_TC1

[15:8]

[7:0]

Reserved

INT_

TCLN1_K TCLN1_J TCLN1_I

INT_ INT_ INT_

TCLN1_C TCLN1_B TCLN1_A

INT_ INT_

TCLN2_K TCLN2_J TCLN2_I

INT_ INT_ INT_

INT_

TCLN1_H

INT_

TCLN1_G

INT_

TCLN1_F

INT_

TCLN1_E

INT_

TCLN1_D

INT_

STATUS_TC2

[15:8]

[7:0]

Reserved

INT_TCLN2_L INT_

INT_

TCLN2_H

TCLN2_G

TCLN2_F

TCLN2_E

TCLN2_D

TCLN2_C TCLN2_B TCLN2_A

0x0006

0x0007

FIFO_TH

[15:8]

[7:0]

Reserved

FIFO_TH[9:8]

0x0000

0x8FFF

R/W

FIFO_TH[7:0]

INT_ACLEAR [15:8]

INT_ACLEAR_

FIFO

Reserved

INT_

ACLEAR_

DATA_L

INT_

ACLEAR_ ACLEAR_ ACLEAR_

DATA_K

INT_

DATA_J

INT_

DATA_I

INT_

[7:0]

INT_ACLEAR_ INT_

INT_

DATA_H

ACLEAR_

DATA_G

ACLEAR_ ACLEAR_

ACLEAR_

DATA_D

ACLEAR_ ACLEAR_ ACLEAR_

DATA_F

DATA_E

DATA_C

DATA_B DATA_A

0x0008

0x0009

0x000A

CHIP_ID

OSC32M

[15:8]

[7:0]

Version

0x02C2

0x0080

0x0000

R

CHIP_ID

Reserved

[15:8]

[7:0]

R/W

OSC_32M_FREQ_ADJ[7:0]

OSC32M_

CAL

[15:8]

OSC_32M_

CAL_START

OSC_32M_CAL_COUNT[14:8]

[7:0]

OSC_32M_CAL_COUNT[7:0]

0x000B

0x000C

OSC1M

OSC32K

[15:8]

Reserved

CLK_CAL_

ENA

OSC_1M_FREQ_

ADJ[9:8]

0x02B2

0x0012

R/W

[7:0]

OSC_1M_FREQ_ADJ[7:0]

Reserved

[15:8]

CAPTURE_

TIMESTAMP

[7:0]

Reserved

OSC_32K_ADJUST[5:0]

TIMESLOT_PERIOD_L[15:8]

0x000D

0x000E

0x000F

TS_FREQ

TS_FREQH

SYS_CTL

[15:8]

[7:0]

0x2710

0x0000

R/W

TIMESLOT_PERIOD_L[7:0]

Reserved

[15:8]

[7:0]

Reserved

TIMESLOT_PERIOD_H[6:0]

[15:8]

[7:0]

SW_RESET

Reserved

ALT_CLOCKS[1:0]

ALT_CLK_GPIO[1:0]

LFOSC_

SEL

OSC_

1M_EN

32K_EN

0x0010

0x0011

OPMODE

STAMP_L

[15:8]

[7:0]

Reserved

TIMESLOT_EN[3:0]

0x0000

R/W

R

Reserved

OP_MODE

[15:8]

[7:0]

TIMESTAMP_COUNT_L[15:8]

TIMESTAMP_COUNT_L[7:0]

Rev. 0 | Page 51 of 101

ADPD4100/ADPD4101

Data Sheet

Bit 15

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 1

Bit 8

Bit 0

Reg

Name

Bits

Bit 7

Reset

R/W

0x0012

STAMP_H

[15:8]

[7:0]

TIMESTAMP_COUNT_H[15:8]

TIMESTAMP_COUNT_H[7:0]

TIMESTAMP_SLOT_DELTA[15:8]

TIMESTAMP_SLOT_DELTA[7:0]

0x0000

R

0x0013

0x0014

STAMPDELTA [15:8]

[7:0]

0x0000

R

INT_ENABLE_ [15:8]

XD

INTX_EN_

FIFO_TH

INTX_EN_

FIFO_

INTX_EN_ Reserved

FIFO_

INTX_EN_

DATA_L

INTX_EN_ INTX_EN_ INTX_EN_ 0x0000

DATA_K DATA_J DATA_I

R/W

UFLOW

OFLOW

[7:0]

INTX_EN_

DATA_H

INTX_EN_

DATA_G

INTX_EN_ INTX_EN_ INTX_EN_

DATA_C DATA_B DATA_A

INTY_EN_ INTY_EN_ INTY_ EN_ 0x0000

DATA_K DATA_J DATA_I

DATA_F

DATA_E

DATA_D

0x0015

INT_ENABLE_ [15:8]

YD

INTY_EN_

FIFO_TH

INTY_EN_

FIFO_

INTY_EN_ Reserved

FIFO_

INTY_EN_

DATA_L

R/W

UFLOW

OFLOW

[7:0]

INTY_EN_

DATA_H

INTY_EN_

DATA_G

INTY_EN_ INTY_EN_

INTY_EN_

DATA_D

INTY_EN_ INTY_EN_ INTY_EN_

DATA_C DATA_B DATA_A

INTX_EN_ INTX_EN_ INTX_EN_ 0x0000

LEV0_K LEV0_J LEV0_I

INTX_EN_ INTX_EN_ INTX_EN_

LEV0_C LEV0_B LEV0_A

INTX_EN_ INTX_EN_ INTX_EN_ 0x0000

LEV1_K LEV1_J LEV1_I

INTX_EN_ INTX_EN_ INTX_EN_

LEV1_C LEV1_B LEV1_A

DATA_F

DATA_E

0x0016

0x0017

0x0018

0x0019

0x001A

0x001B

0x001C

0x001D

0x001E

INT_ENABLE_ [15:8]

XL0

Reserved

INTX_EN_

LEV0_L

R/W

[7:0]

INTX_EN_

LEV0_H

INTX_EN_

LEV0_G

INTX_EN_ INTX_EN_ INTX_EN_

LEV0_F

LEV0_E

LEV0_D

INT_ENABLE_ [15:8]

XL1

Reserved

INTX_EN_

LEV1_L

[7:0]

INTX_EN_

LEV1_H

INTX_EN_

LEV1_G

INTX_EN_ INTX_EN_ INTX_EN_

LEV1_F

LEV1_E

LEV1_D

INT_ENABLE_ [15:8]

XT1

Reserved

INTX_EN_

TCLN1_L

INTX_EN_ INTX_EN_ INTX_EN_ 0x0000

TCLN1_K TCLN1_J TCLN1_I

[7:0]

INTX_EN_

TCLN1_H

INTX_EN_

TCLN1_G

INTX_EN_ INTX_EN_ INTX_EN_

TCLN1_F

INTX_EN_ INTX_EN_ INTX_EN_

TCLN1_C TCLN1_B TCLN1_A

TCLN1_E

TCLN1_D

INT_ENABLE_ [15:8]

XT2

Reserved

INTX_EN_

TCLN2_L

INTX_EN_ INTX_EN_ INTX_EN_ 0x0000

TCLN2_K TCLN2_J TCLN2_I

[7:0]

INTX_EN_

TCLN2_H

INTX_EN_

TCLN2_G

INTX_EN_ INTX_EN_ INTX_EN_

TCLN2_F

INTX_EN_ INTX_EN_ INTX_EN_

TCLN2_C TCLN2_B TCLN2_A

TCLN2_E

TCLN2_D

INT_ENABLE_ [15:8]

YL0

Reserved

INTY_EN_

LEV0_L

INTY_EN_ INTY_EN_ INTY_EN_ 0x0000

LEV0_K

INTY_EN_ INTY_EN_ INTY_EN_

LEV0_C LEV0_B LEV0_A

INTY_EN_ INTY_EN_ INTY_EN_ 0x0000

LEV1_K LEV1_J LEV1_I

INTY_EN_ INTY_EN_ INTY_EN_

LEV1_C LEV1_B LEV1_A

LEV0_J

LEV0_I

[7:0]

INTY_EN_

LEV0_H

INTY_EN_

LEV0_G

INTY_EN_ INTY_EN_

LEV0_F LEV0_E

INTY_EN_

LEV0_D

INT_ENABLE_ [15:8]

YL1

Reserved

INTY_EN_

LEV1_L

[7:0]

INTY_EN_

LEV1_H

INTY_EN_

LEV1_G

INTY_EN_ INTY_EN_

LEV1_F LEV1_E

INTY_EN_

LEV1_D

INT_ENABLE_ [15:8]

YT1

Reserved

INTY_EN_

TCLN1_L

INTY _EN_ INTY _EN_ INTY _EN_ 0x0000

TCLN1_K TCLN1_J TCLN1_I

[7:0]

INTY _EN_

TCLN1_H

INTY _EN_ INTY_EN_ INTY_EN_

TCLN1_G TCLN1_F TCLN1_E

Reserved

INTY_EN_

TCLN1_D

INTY_EN_ INTY_EN_ INTY_EN_

TCLN1_C TCLN1_B TCLN1_A

INT_ENABLE_ [15:8]

YT2

INTY_EN_

TCLN2_L

INTY_EN_ INTY_EN_ INTY_EN_ 0x0000

TCLN2_K TCLN2_J TCLN2_I

[7:0]

INTY_EN_

TCLN2_H

INTY_EN_

TCLN2_G

INTY_EN_ INTY_EN_

TCLN2_F

INTY_EN_

TCLN2_D

INTY_EN_ INTY_EN_ INTY_EN_

TCLN2_C TCLN2_B TCLN2_A

TCLN2_E

FIFO_

STATUS_

BYTES

[15:8]

[7:0]

Reserved

ENA_

0x0000

STAT_TCX

ENA_

STAT_TC2

STAT_TC1

STAT_LX

STAT_L1

STAT_L0

STAT_D2 STAT_D1 STAT_

SUM

0x0020

0x0021

0x0022

INPUT_SLEEP [15:8]

INP_SLEEP_78[3:0]

INP_SLEEP_34[3:0]

INP_SLEEP_56[3:0]

INP_SLEEP_12[3:0]

0x0000

R/W

[7:0]

INPUT_CFG [15:8]

[7:0]

Reserved

PAIR78

VC2_SLEEP[1:0]

VC1_SLEEP[1:0]

GPIO_DRV[1:0]

PAIR56

PAIR34

PAIR12

GPIO_CFG

[15:8]

GPIO_SLEW[1:0]

GPIO_PIN_CFG3[2:0]

GPIO_PIN_ 0x0000

CFG2[2]

[7:0]

[15:8]

[7:0]

GPIO_PIN_CFG2[1:0]

GPIO_PIN_CFG1[2:0]

GPIO_PIN_CFG0[2:0]

0x0023

GPIO01

Reserved

GPIOOUT1[6:0]

GPIOOUT0[6:0]

0x0000

R/W

Rev. 0 | Page 52 of 101

Data Sheet

ADPD4100/ADPD4101

Bit 15

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 10

Bit 2

Bit 9

Bit 1

Bit 8

Bit 0

Reg

Name

Bits

Bit 7

Bit 3

Reset

R/W

0x0024

GPIO23

[15:8]

[7:0]

Reserved

GPIOOUT3[6:0]

GPIOOUT2[6:0]

0x0000

R/W

0x0025

0x0026

GPIO_IN

[15:8]

[7:0]

Reserved

TIMESTAMP_ TIMESTAMP TIMESTAMP_GPIO[1:0] Reserved

0x0000

R

Reserved

GPIO_INPUT[3:0]

GPIO_EXT

[15:8]

TS_GPIO_ 0x0000

SLEEP

R/W

[7:0]

EXT_

EXT_SYNC_GPIO[1:0]

INV

_ALWAYS_

EN

SYNC_EN

0x002E

DATA_

HOLD_FLAG

[15:8]

[7:0]

Reserved

HOLD_

REGS_L

HOLD_

REGS_K

HOLD_

REGS_J

HOLD_

REGS_I

0x0000

R/W

HOLD_

REGS_H

HOLD_

REGS_F

HOLD_

REGS_E

HOLD_

REGS_D

HOLD_

REGS_C

HOLD_

REGS_B

HOLD_

REGS_A

REGS_G

0x002F

0x0030

0x0031

0x0032

0x0033

0x0034

0x0035

0x0036

0x0037

0x0038

0x0039

0x003A

0x003B

0x003C

0x003D

0x003E

0x003F

0x0040

0x0041

0x0042

FIFO_DATA [15:8]

[7:0]

FIFO_DATA[15:8]

0x0000

R

FIFO_DATA[7:0]

SIGNAL1_L_A[15:8]

SIGNAL1_L_A[7:0]

SIGNAL1_H_A[15:8]

SIGNAL1_H_A[7:0]

SIGNAL2_L_A[15:8]

SIGNAL2_L_A[7:0]

SIGNAL2_H_A[15:8]

SIGNAL2_H_A[7:0]

DARK1_L_A[15:8]

DARK1_L_A[7:0]

SIGNAL1_L_A [15:8]

[7:0]

SIGNAL1_H_A [15:8]

[7:0]

SIGNAL2_L_A [15:8]

[7:0]

SIGNAL2_H_A [15:8]

[7:0]

DARK1_L_A [15:8]

[7:0]

DARK1_H_A [15:8]

[7:0]

DARK1_H_A[15:8]

DARK1_H_A[7:0]

DARK2_L_A[15:8]

DARK2_L_A[7:0]

DARK2_L_A [15:8]

[7:0]

DARK2_H_A [15:8]

[7:0]

DARK2_H_A[15:8]

DARK2_H_A[7:0]

SIGNAL1_L_B[15:8]

SIGNAL1_L_B[7:0]

SIGNAL1_H_B[15:8]

SIGNAL1_H_B[7:0]

SIGNAL2_L_B[15:8]

SIGNAL2_L_B[7:0]

SIGNAL2_H_B[15:8]

SIGNAL2_H_B[7:0]

DARK1_L_B[15:8]

DARK1_L_B[7:0]

SIGNAL1_L_B [15:8]

[7:0]

SIGNAL1_H_B [15:8]

[7:0]

SIGNAL2_L_B [15:8]

[7:0]

SIGNAL2_H_B [15:8]

[7:0]

DARK1_L_B [15:8]

[7:0]

DARK1_H_B [15:8]

[7:0]

DARK1_H_B[15:8]

DARK1_H_B[7:0]

DARK2_L_B[15:8]

DARK2_L_B[7:0]

DARK2_L_B [15:8]

[7:0]

DARK2_H_B [15:8]

[7:0]

DARK2_H_B[15:8]

DARK2_H_B[7:0]

SIGNAL1_L_C[15:8]

SIGNAL1_L_C[7:0]

SIGNAL1_H_C[15:8]

SIGNAL1_H_C[7:0]

SIGNAL2_L_C[15:8]

SIGNAL1_L_C [15:8]

[7:0]

SIGNAL1_H_C [15:8]

[7:0]

SIGNAL2_L_C [15:8]

[7:0]

SIGNAL2_H_C [15:8]

[7:0]

SIGNAL2_L_C[7:0]

SIGNAL2_H_C[15:8]

SIGNAL2_H_C[7:0]

0x0043

0x0000

R

Rev. 0 | Page 53 of 101

ADPD4100/ADPD4101

Data Sheet

Bit 15

Bit 7

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 1

Bit 8

Bit 0

Reg

Name

Bits

Reset

R/W

0x0044

DARK1_L_C [15:8]

DARK1_L_C[15:8]

DARK1_L_C[7:0]

0x0000

R

[7:0]

DARK1_H_C [15:8]

[7:0]

0x0045

0x0046

0x0047

0x0048

0x0049

0x004A

0x004B

0x004C

0x004D

0x004E

0x004F

0x0050

0x0051

0x0052

0x0053

0x0054

0x0055

0x0056

0x0057

0x0058

0x0059

0x005A

0x005B

0x005C

0x005D

0x005E

DARK1_H_C[15:8]

DARK1_H_C[7:0]

DARK2_L_C[15:8]

DARK2_L_C[7:0]

0x0000

R

DARK2_L_C [15:8]

[7:0]

DARK2_H_C [15:8]

[7:0]

DARK2_H_C[15:8]

DARK2_H_C[7:0]

SIGNAL1_L_D[15:8]

SIGNAL1_L_D[7:0]

SIGNAL1_H_D[15:8]

SIGNAL1_H_D[7:0]

SIGNAL2_L_D[15:8]

SIGNAL2_L_D[7:0]

SIGNAL2_H_D[15:8]

SIGNAL2_H_D[7:0]

DARK1_L_D[15:8]

DARK1_L_D[7:0]

DARK1_H_D[15:8]

DARK1_H_D[7:0]

DARK2_L_D[15:8]

DARK2_L_D[7:0]

DARK2_H_D[15:8]

DARK2_H_D[7:0]

SIGNAL1_L_E[15:8]

SIGNAL1_L_E[7:0]

SIGNAL1_H_E[15:8]

SIGNAL1_H_E[7:0]

SIGNAL2_L_E[15:8]

SIGNAL2_L_E[7:0]

SIGNAL2_H_E[15:8]

SIGNAL2_H_E[7:0]

DARK1_L_E[15:8]

DARK1_L_E[7:0]

SIGNAL1_L_D [15:8]

[7:0]

SIGNAL1_H_D [15:8]

[7:0]

SIGNAL2_L_D [15:8]

[7:0]

SIGNAL2_H_D [15:8]

[7:0]

DARK1_L_D [15:8]

[7:0]

DARK1_H_D [15:8]

[7:0]

DARK2_L_D [15:8]

[7:0]

DARK2_H_D [15:8]

[7:0]

SIGNAL1_L_E [15:8]

[7:0]

SIGNAL1_H_E [15:8]

[7:0]

SIGNAL2_L_E [15:8]

[7:0]

SIGNAL2_H_E [15:8]

[7:0]

DARK1_L_E [15:8]

[7:0]

DARK1_H_E [15:8]

[7:0]

DARK1_H_E[15:8]

DARK1_H_E[7:0]

DARK2_L_E[15:8]

DARK2_L_E[7:0]

DARK2_L_E [15:8]

[7:0]

DARK2_H_E [15:8]

[7:0]

DARK2_H_E[15:8]

DARK2_H_E[7:0]

SIGNAL1_L_F[15:8]

SIGNAL1_L_F[7:0]

SIGNAL1_H_F[15:8]

SIGNAL1_H_F[7:0]

SIGNAL2_L_F[15:8]

SIGNAL2_L_F[7:0]

SIGNAL2_H_F[15:8]

SIGNAL2_H_F[7:0]

DARK1_L_F[15:8]

DARK1_L_F[7:0]

SIGNAL1_L_F [15:8]

[7:0]

SIGNAL1_H_F [15:8]

[7:0]

SIGNAL2_L_F [15:8]

[7:0]

SIGNAL2_H_F [15:8]

[7:0]

DARK1_L_F [15:8]

[7:0]

DARK1_H_F [15:8]

[7:0]

DARK1_H_F[15:8]

DARK1_H_F[7:0]

DARK2_L_F[15:8]

DARK2_L_F[7:0]

DARK2_L_F [15:8]

[7:0]

Rev. 0 | Page 54 of 101

Data Sheet

ADPD4100/ADPD4101

Bit 15

Bit 7

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 1

Bit 8

Bit 0

Reg

Name

Bits

Reset

R/W

0x005F

DARK2_H_F [15:8]

DARK2_H_F[15:8]

DARK2_H_F[7:0]

SIGNAL1_L_G[15:8]

SIGNAL1_L_G[7:0]

SIGNAL1_H_G[15:8]

SIGNAL1_H_G[7:0]

SIGNAL2_L_G[15:8]

SIGNAL2_L_G[7:0]

SIGNAL2_H_G[15:8]

SIGNAL2_H_G[7:0]

DARK1_L_G[15:8]

DARK1_L_G[7:0]

DARK1_H_G[15:8]

DARK1_H_G[7:0]

DARK2_L_G[15:8]

DARK2_L_G[7:0]

DARK2_H_G[15:8]

DARK2_H_G[7:0]

SIGNAL1_L_H[15:8]

SIGNAL1_L_H[7:0]

SIGNAL1_H_H[15:8]

SIGNAL1_H_H[7:0]

SIGNAL2_L_H[15:8]

SIGNAL2_L_H[7:0]

SIGNAL2_H_H[15:8]

SIGNAL2_H_H[7:0]

DARK1_L_H[15:8]

DARK1_L_H[7:0]

DARK1_H_H[15:8]

DARK1_H_H[7:0]

DARK2_L_H[15:8]

DARK2_L_H[7:0]

DARK2_H_H[15:8]

DARK2_H_H[7:0]

SIGNAL1_L_I[15:8]

SIGNAL1_L_I[7:0]

SIGNAL1_H_I[15:8]

SIGNAL1_H_I[7:0]

SIGNAL2_L_I[15:8]

SIGNAL2_L_I[7:0]

SIGNAL2_H_I[15:8]

SIGNAL2_H_I[7:0]

DARK1_L_I[15:8]

DARK1_L_I[7:0]

0x0000

R

[7:0]

SIGNAL1_L_G [15:8]

[7:0]

0x0060

0x0061

0x0062

0x0063

0x0064

0x0065

0x0066

0x0067

0x0068

0x0069

0x006A

0x006B

0x006C

0x006D

0x006E

0x006F

0x0070

0x0071

0x0072

0x0073

0x0074

0x0075

0x0076

0x0077

0x0078

0x0079

0x0000

R

SIGNAL1_H_G [15:8]

[7:0]

SIGNAL2_L_G [15:8]

[7:0]

SIGNAL2_H_G [15:8]

[7:0]

DARK1_L_G [15:8]

[7:0]

DARK1_H_G [15:8]

[7:0]

DARK2_L_G [15:8]

[7:0]

DARK2_H_G [15:8]

[7:0]

SIGNAL1_L_H [15:8]

[7:0]

SIGNAL1_H_H [15:8]

[7:0]

SIGNAL2_L_H [15:8]

[7:0]

SIGNAL2_H_H [15:8]

[7:0]

DARK1_L_H [15:8]

[7:0]

DARK1_H_H [15:8]

[7:0]

DARK2_L_H [15:8]

[7:0]

DARK2_H_H [15:8]

[7:0]

SIGNAL1_L_I [15:8]

[7:0]

SIGNAL1_H_I [15:8]

[7:0]

SIGNAL2_L_I [15:8]

[7:0]

SIGNAL2_H_I [15:8]

[7:0]

DARK1_L_I

[15:8]

[7:0]

DARK1_H_I [15:8]

[7:0]

DARK1_H_I[15:8]

DARK1_H_I[7:0]

DARK2_L_I

[15:8]

[7:0]

DARK2_L_I[15:8]

DARK2_L_I[7:0]

DARK2_H_I [15:8]

DARK2_H_I[15:8]

DARK2_H_I[7:0]

[7:0]

SIGNAL1_L_J [15:8]

[7:0]

SIGNAL1_L_J[15:8]

SIGNAL1_L_J[7:0]

SIGNAL1_H_J[15:8]

SIGNAL1_H_J[7:0]

SIGNAL1_H_J [15:8]

[7:0]

Rev. 0 | Page 55 of 101

ADPD4100/ADPD4101

Data Sheet

Bit 15

Bit 7

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 1

Bit 8

Bit 0

Reg

Name

Bits

Reset

R/W

0x007A

SIGNAL2_L_J [15:8]

SIGNAL2_L_J[15:8]

SIGNAL2_L_J[7:0]

SIGNAL2_H_J[15:8]

SIGNAL2_H_J[7:0]

DARK1_L_J[15:8]

DARK1_L_J[7:0]

0x0000

R

[7:0]

SIGNAL2_H_J [15:8]

[7:0]

0x007B

0x007C

0x007D

0x007E

0x007F

0x0080

0x0081

0x0082

0x0083

0x0084

0x0085

0x0086

0x0087

0x0088

0x0089

0x008A

0x008B

0x008C

0x008D

0x008E

0x008F

0x00B4

0x0000

0x0050

R

DARK1_L_J

[15:8]

[7:0]

DARK1_H_J [15:8]

[7:0]

DARK1_H_J[15:8]

DARK1_H_J[7:0]

DARK2_L_J[15:8]

DARK2_L_J[7:0]

R

DARK2_L_J

[15:8]

[7:0]

R

DARK2_H_J [15:8]

DARK2_H_J[15:8]

DARK2_H_J[7:0]

SIGNAL1_L_K[15:8]

SIGNAL1_L_K[7:0]

SIGNAL1_H_K[15:8]

SIGNAL1_H_K[7:0]

SIGNAL2_L_K[15:8]

SIGNAL2_L_K[7:0]

SIGNAL2_H_K[15:8]

SIGNAL2_H_K[7:0]

DARK1_L_K[15:8]

DARK1_L_K[7:0]

DARK1_H_K[15:8]

DARK1_H_K[7:0]

DARK2_L_K[15:8]

DARK2_L_K[7:0]

DARK2_H_K[15:8]

DARK2_H_K[7:0]

SIGNAL1_L_L[15:8]

SIGNAL1_L_L[7:0]

SIGNAL1_H_L[15:8]

SIGNAL1_H_L[7:0]

SIGNAL2_L_L[15:8]

SIGNAL2_L_L[7:0]

SIGNAL2_H_L[15:8]

SIGNAL2_H_L[7:0]

DARK1_L_L[15:8]

DARK1_L_L[7:0]

DARK1_H_L[15:8]

DARK1_H_L[7:0]

DARK2_L_L[15:8]

DARK2_L_L[7:0]

DARK2_H_L[15:8]

DARK2_H_L[7:0]

Reserved

R

[7:0]

SIGNAL1_L_K [15:8]

[7:0]

R

SIGNAL1_H_K [15:8]

[7:0]

R

SIGNAL2_L_K [15:8]

[7:0]

R

SIGNAL2_H_K [15:8]

[7:0]

R

DARK1_L_K [15:8]

[7:0]

R

DARK1_H_K [15:8]

[7:0]

R

DARK2_L_K [15:8]

[7:0]

R

DARK2_H_K [15:8]

[7:0]

R

SIGNAL1_L_L [15:8]

[7:0]

R

SIGNAL1_H_L [15:8]

[7:0]

R

SIGNAL2_L_L [15:8]

[7:0]

R

SIGNAL2_H_L [15:8]

[7:0]

R

DARK1_L_L [15:8]

[7:0]

R

DARK1_H_L [15:8]

[7:0]

R

DARK2_L_L [15:8]

[7:0]

R

DARK2_H_L [15:8]

[7:0]

R

IO_ADJUST

[15:8]

[7:0]

R/W

Reserved (set LOW_

Reserved Reserved

SPI_SLEW[1:0]

SPI_DRV[1:0]

to 0x0)

IOVDD_EN (set to 0x0) (set to 0x1)

0x00B6

0x00B7

0x0100

I2C_KEY

[15:8]

[7:0]

I2C_KEY_MATCH[3:0]

I2C_KEY[11:8]

0x0000

0x0048

R/W

I2C_KEY[7:0]

I2C_SLAVE_KEY2[7:0]

I2C_SLAVE_ADDR[6:0]

I2C_ADDR

TS_CTRL_A

[15:8]

[7:0]

Reserved

[15:8]

SUBSAMPLE_A CH2_EN_A

SAMPLE_TYPE_A[1:0] INPUT_R_SELECT_A[1:0] TIMESLOT_OFFSET_ 0x0000

A[9:8]

[7:0]

TIMESLOT_OFFSET_A[7:0]

Rev. 0 | Page 56 of 101

Data Sheet

ADPD4100/ADPD4101

Bit 15

Bit 7

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 1

Bit 8

Bit 0

Reg

Name

Bits

Reset

R/W

0x0101

TS_PATH_A [15:8]

PRE_WIDTH_A[3:0]

Reserved

TS_

GPIO_A

AFE_

PATH_

CFG_A[8]

0x40DA

R/W

[7:0]

AFE_PATH_CFG_A[7:0]

0x0102

0x0103

0x0104

INPUTS_A

[15:8]

[7:0]

INP78_A[3:0]

INP34_A[3:0]

INP56_A[3:0]

INP12_A[3:0]

VC2_PULSE_A[1:0]

0x0000

0x03C0

R/W

CATHODE_A [15:8]

[7:0]

Reserved

PRECON_A[2:0]

VC1_PULSE_A[1:0]

VC2_ALT_A[1:0]

VC1_SEL_A[1:0]

VC2_SEL_A[1:0]

VC1_ALT_A[1:0]

AFE_TRIM_A [15:8]

TIA_CEIL_

DETECT_EN_A

CH2_TRIM_INT_A[1:0]

CH1_TRIM_INT_A[1:0] VREF_

AFE_TRIM_VREF_

A[1:0]

PULSE_A

[7:0]

VREF_PULSE_VAL_A[1:0]

LED_

DRIVESIDE2_A

TIA_GAIN_CH2_A[2:0]

TIA_GAIN_CH1_A[2:0]

0x0105

0x0106

LED_

POW12_A

[15:8]

LED_CURRENT2_A[6:0]

LED_CURRENT1_A[6:0]

LED_CURRENT4_A[6:0]

LED_CURRENT3_A[6:0]

0x0000

0x0101

R/W

[7:0]

LED_

DRIVESIDE1_A

LED_

POW34_A

[15:8]

[7:0]

LED_

DRIVESIDE4_A

LED_

DRIVESIDE3_A

0x0107

0x0108

0x0109

0x010A

COUNTS_A

PERIOD_A

[15:8]

[7:0]

NUM_INT_A[7:0]

NUM_REPEAT_A[7:0]

MOD_TYPE_A[1:0]

R/W

[15:8]

[7:0]

Reserved

MIN_PERIOD_A[9:8] 0x0000

0x0210

MIN_PERIOD_A[7:0]

LED_WIDTH_A[7:0]

LED_OFFSET_A[7:0]

LED_

PULSE_A

[15:8]

[7:0]

INTEG_

SETUP_A

[15:8]

SINGLE_

INTEG_A

CH2_AMP_DISABLE_A[2:0]

AFE_INT_

C_BUF_A

INTEG_WIDTH_A[4:0]

INTEG_OFFSET_A[12:8]

INTEG_OFFSET_A[7:0]

CH1_AMP_DISABLE_A[2:0]

0x0003

[7:0]

ADC_COUNT_A[1:0]

Reserved

0x010B

0x010C

0x010D

0x010E

0x010F

INTEG_OS_A [15:8]

[7:0]

0x0214

0x0001

0x0000

R/W

MOD_

PULSE_A

[15:8]

[7:0]

MOD_WIDTH_A[7:0]

MOD_OFFSET_A[7:0]

PATTERN_A [15:8]

[7:0]

LED_DISABLE_A[3:0]

SUBTRACT_A[3:0]

MOD_DISABLE_A[3:0]

REVERSE_INTEG_A[3:0]

ADC_OFF1_A [15:8]

[7:0]

Reserved

CH1_ADC_ADJUST_A[13:8]

CH1_ADC_ADJUST_A[7:0]

CH2_ADC_ADJUST_A[13:8]

ADC_OFF2_A [15:8]

ZERO_

Reserved

ADJUST_A

[7:0]

CH2_ADC_ADJUST_A[7:0]

DARK_SHIFT_A[4:0]

0x0110

0x0111

0x0112

0x0113

DATA_

FORMAT_A

[15:8]

[7:0]

DARK_SIZE_A[2:0]

0x0003

0x0000

0x0026

R/W

SIGNAL_SHIFT_A[4:0]

SIGNAL_SIZE_A[2:0]

LIT_DATA_

FORMAT_A

[15:8]

[7:0]

Reserved

LIT_SHIFT_A[4:0]

Reserved

LIT_SIZE_A[2:0]

DECIMATE_FACTOR_A[6:4]

DECIMATE_TYPE_A[3:0]

DECIMATE_A [15:8]

[7:0]

DECIMATE_FACTOR_A[3:0]

DIGINT_

LIT_A

[15:8]

Reserved

LIT_

OFFSET_

A[8]

[7:0]

[15:8]

[7:0]

LIT_OFFSET_A[7:0]

0x0114

0x0115

0x0116

DIGINT_

DARK_A

DARK2_OFFSET_A[8:1]

0x2306

0x0000

R/W

DARK2_

OFFSET_A[0]

DARK1_OFFSET_A[6:0]

THRESH_

CFG_A

[15:8]

[7:0]

Reserved

THRESH1_TYPE_A[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_A[1:0]

CHAN_A DIR_A

THRESH0_SHIFT_A[4:0]

THRESH0_VALUE_A[7:0]

THRESH1_

CHAN_A

THRESH1_

DIR_A

THRESH0_A [15:8]

[7:0]

Reserved

Rev. 0 | Page 57 of 101

ADPD4100/ADPD4101

Data Sheet

Bit 15

Bit 7

Bit 14

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 1

Bit 8

Bit 0

Reg

Name

Bits

Bit 6

Reset

R/W

0x0117

THRESH1_A [15:8]

[7:0]

Reserved

THRESH1_SHIFT_A[4:0]

THRESH1_VALUE_A[7:0]

0x0000

R/W

0x0120

0x0121

TS_CTRL_B

[15:8]

SUBSAMPLE_B CH2_EN_B

SAMPLE_TYPE_B[1:0] INPUT_R_SELECT_B[1:0]

TIMESLOT_

OFFSET_B[9:8]

0x0000

0x40DA

R/W

[7:0]

TIMESLOT_OFFSET_B[7:0]

TS_PATH_B [15:8]

[7:0]

PRE_WIDTH_B[3:0]

Reserved

TS_GPIO_B AFE_

PATH_

CFG_B[8]

AFE_PATH_CFG_B[7:0]

0x0122

0x0123

0x0124

INPUTS_B

[15:8]

[7:0]

INP78_B[3:0]

INP34_B[3:0]

PRECON_B[2:0]

VC1_PULSE_B[1:0]

INP56_B[3:0]

INP12_B[3:0]

0x0000

0x03C0

R/W

CATHODE_B [15:8]

[7:0]

Reserved

VC2_PULSE_B[1:0]

VC1_ALT_B[1:0]

VC2_ALT_B[1:0]

VC1_SEL_B[1:0]

VC2_SEL_B[1:0]

AFE_TRIM_B [15:8]

TIA_CEIL_

DETECT_EN_B

CH2_TRIM_INT_B[1:0]

CH2_TRIM_INT_B[1:0] VREF_

PULSE_B

AFE_TRIM_

VREF_B[1:0]

[7:0]

VREF_PULSE_VAL_B[1:0]

TIA_GAIN_CH2_B[2:0]

LED_CURRENT2_B[6:0]

TIA_GAIN_CH1_B[2:0]

0x0125

0x0126

LED_

POW12_B

[15:8]

LED_

0x0000

0x0101

R/W

DRIVESIDE2_B

[7:0]

LED_

DRIVESIDE1_B

LED_CURRENT1_B[6:0]

LED_CURRENT4_B[6:0]

LED_CURRENT3_B[6:0]

LED_

POW34_B

[15:8]

[7:0]

LED_

DRIVESIDE4_B

LED_

DRIVESIDE3_B

0x0127

0x0128

0x0129

0x012A

COUNTS_B

PERIOD_B

[15:8]

[7:0]

NUM_INT_B[7:0]

NUM_REPEAT_B[7:0]

MOD_TYPE_B[1:0]

R/W

[15:8]

[7:0]

Reserved

MIN_PERIOD_B[9:8] 0x0000

0x0210

MIN_PERIOD_B[7:0]

LED_WIDTH_B[7:0]

LED_OFFSET_B[7:0]

LED_

PULSE_B

[15:8]

[7:0]

INTEG_

SETUP_B

[15:8]

SINGLE_

INTEG_B

CH2_AMP_DISABLE_B[2:0]

AFE_INT_C_

BUF_B

CH1_AMP_DISABLE_B[2:0]

0x0003

[7:0]

ADC_COUNT_B[1:0]

Reserved

INTEG_WIDTH_B[4:0]

0x012B

0x012C

0x012D

0x012E

0x012F

INTEG_OS_B [15:8]

[7:0]

INTEG_ OFFSET_B[12:8]

INTEG_OFFSET_B[7:0]

0x0214

0x0001

0x0000

R/W

MOD_

PULSE_B

[15:8]

[7:0]

MOD_WIDTH_B[7:0]

MOD_OFFSET_B[7:0]

PATTERN_B [15:8]

[7:0]

LED_DISABLE_B[3:0]

SUBTRACT_B[3:0]

MOD_DISABLE_B[3:0]

REVERSE_INTEG_B[3:0]

ADC_OFF1_B [15:8]

[7:0]

Reserved

CH1_ADC_ADJUST_B[13:8]

CH1_ADC_ADJUST_B[7:0]

CH2_ADC_ADJUST_B[13:8]

ADC_OFF2_B [15:8]

ZERO_

Reserved

ADJUST_B

[7:0]

CH2_ADC_ADJUST_B[7:0]

DARK_SHIFT_B[4:0]

0x0130

0x0131

0x0132

0x0133

DATA_

FORMAT_B

[15:8]

[7:0]

DARK_SIZE_B[2:0]

0x0003

0x0000

0x0026

R/W

SIGNAL_SHIFT_B[4:0]

SIGNAL_SIZE_B[2:0]

LIT_DATA_

FORMAT_B

[15:8]

[7:0]

Reserved

LIT_SHIFT_B[4:0]

Reserved

LIT_SIZE_B[2:0]

DECIMATE_FACTOR_B[6:4]

DECIMATE_TYPE_B[3:0]

DECIMATE_B [15:8]

[7:0]

DECIMATE_FACTOR_B[3:0]

DIGINT_LIT_B [15:8]

Reserved

LIT_

OFFSET_

B[8]

[7:0]

LIT_OFFSET_B[7:0]

0x0134

DIGINT_

DARK_B

[15:8]

[7:0]

DARK2_OFFSET_B[8:1]

0x2306

R/W

DARK2_

DARK1_OFFSET_B[6:0]

OFFSET_B[0]

Rev. 0 | Page 58 of 101

Data Sheet

ADPD4100/ADPD4101

Bit 15

Bit 7

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 1

Bit 8

Bit 0

Reg

Name

Bits

Reset

R/W

0x0135

THRESH_

CFG_B

[15:8]

Reserved

0x0000

R/W

[7:0]

THRESH1_

CHAN_B

THRESH1_

DIR_B

THRESH1_TYPE_B[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_ B[1:0]

CHAN_B DIR_B

THRESH0_SHIFT_B[4:0]

THRESH0_VALUE_B[7:0]

THRESH1_SHIFT_B[4:0]

THRESH1_VALUE_B[7:0]

0x0136

0x0137

0x0140

THRESH0_B [15:8]

Reserved

0x0000

R/W

[7:0]

THRESH1_B [15:8]

[7:0]

Reserved

TS_CTRL_C

[15:8]

SUBSAMPLE_C CH2_EN_C

SAMPLE_TYPE_C[1:0] INPUT_R_SELECT_C[1:0] TIMESLOT_OFFSET_ 0x0000

C[9:8]

[7:0]

TIMESLOT_OFFSET_C[7:0]

0x0141

TS_PATH_C [15:8]

[7:0]

PRE_WIDTH_C[3:0]

Reserved

TS_

GPIO_C

AFE_PATH 0x40DA

_CFG_C[8]

R/W

AFE_PATH_CFG_C[7:0]

0x0142

0x0143

0x0144

INPUTS_C

[15:8]

[7:0]

INP78_C[3:0]

INP34_C[3:0]

INP56_C[3:0]

INP12_C[3:0]

0x0000

R/W

CATHODE_C [15:8]

[7:0]

Reserved

PRECON_C[2:0]

VC1_PULSE_C[1:0]

VC2_PULSE_C[1:0]

VC1_ALT_C[1:0]

VC2_ALT_C[1:0]

0x0000

0x03C0

VC2_SEL_C[1:0]

VC1_SEL_C[1:0]

AFE_TRIM_C [15:8]

TIA_CEIL_

DETECT_EN_C

CH2_TRIM_INT_C[1:0]

CH1_TRIM_INT_C[1:0] VREF_

PULSE_C

AFE_TRIM_

VREF_C[1:0]

[7:0]

VREF_PULSE_VAL_C[1:0]

TIA_GAIN_CH2_C[2:0]

LED_CURRENT2_C[6:0]

TIA_GAIN_CH1_C[2:0]

0x0145

0x0146

LED_

POW12_C

[15:8]

LED_

0x0000

0x0101

R/W

DRIVESIDE2_C

[7:0]

LED_

DRIVESIDE1_C

LED_CURRENT1_C[6:0]

LED_CURRENT4_C[6:0]

LED_CURRENT3_C[6:0]

LED_

POW34_C

[15:8]

[7:0]

LED_

DRIVESIDE4_C

LED_

DRIVESIDE3_C

0x0147

0x0148

0x0149

0x014A

COUNTS_C

PERIOD_C

[15:8]

[7:0]

NUM_INT_C[7:0]

NUM_REPEAT_C[7:0]

MOD_TYPE_C[1:0]

R/W

[15:8]

[7:0]

Reserved

MIN_PERIOD_C[9:8] 0x0000

0x0210

MIN_PERIOD_C[7:0]

LED_WIDTH_C[7:0]

LED_OFFSET_C[7:0]

LED_

PULSE_C

[15:8]

[7:0]

INTEG_

SETUP_C

[15:8]

SINGLE_

INTEG_C

CH2_AMP_DISABLE_C[2:0]

AFE_INT_C_

BUF_C

CH1_AMP_DISABLE_C[2:0]

0x0003

[7:0]

ADC_COUNT_C[1:0]

Reserved

INTEG_WIDTH_C[4:0]

INTEG_OFFSET_C[12:8]

0x014B

0x014C

0x014D

0x014E

0x014F

INTEG_OS_C [15:8]

[7:0]

0x0214

0x0001

0x0000

R/W

INTEG_OFFSET_C[7:0]

MOD_WIDTH_C[7:0]

MOD_OFFSET_C[7:0]

MOD_

PULSE_C

[15:8]

[7:0]

PATTERN_C [15:8]

[7:0]

LED_DISABLE_C[3:0]

SUBTRACT_C[3:0]

MOD_DISABLE_C[3:0]

REVERSE_INTEG_C[3:0]

ADC_OFF1_C [15:8]

[7:0]

Reserved

CH1_ADC_ADJUST_C[13:8]

CH1_ADC_ADJUST_C[7:0]

CH2_ADC_ADJUST_C[13:8]

ADC_OFF2_C [15:8]

ZERO_

ADJUST_C

Reserved

[7:0]

CH2_ADC_ADJUST_C[7:0]

DARK_SHIFT_C[4:0]

0x0150

0x0151

0x0152

DATA_

FORMAT_C

[15:8]

[7:0]

DARK_SIZE_C[2:0]

0x0003

0x0000

R/W

SIGNAL_SHIFT_C[4:0]

SIGNAL_SIZE_C[2:0]

LIT_DATA_

FORMAT_C

[15:8]

[7:0]

Reserved

LIT_SHIFT_C[4:0]

Reserved

LIT_SIZE_C[2:0]

DECIMATE_FACTOR_C[6:4]

DECIMATE_TYPE_C[3:0]

DECIMATE_C [15:8]

[7:0]

DECIMATE_FACTOR_C[3:0]

Rev. 0 | Page 59 of 101

ADPD4100/ADPD4101

Data Sheet

Bit 15

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 1

Bit 8

Bit 0

Reg

Name

Bits

Bit 7

Reset

R/W

0x0153

DIGINT_LIT_C [15:8]

Reserved

LIT_

0x0026

R/W

OFFSET_

C[8]

[7:0]

LIT_OFFSET_C[7:0]

0x0154

0x0155

DIGINT_

DARK_C

[15:8]

[7:0]

DARK2_OFFSET_C[8:1]

0x2306

0x0000

R/W

DARK2_

OFFSET_C[0]

DARK1_OFFSET_C[6:0]

THRESH_

CFG_C

[15:8]

[7:0]

Reserved

THRESH1_TYPE_C[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_ C[1:0]

CHAN_C DIR_C

THRESH0_SHIFT_C[4:0]

THRESH0_VALUE_C[7:0]

THRESH1_SHIFT_C[4:0]

THRESH1_VALUE_C[7:0]

THRESH1_

CHAN_C

THRESH1_

DIR_C

0x0156

0x0157

0x0160

THRESH0_C [15:8]

[7:0]

Reserved

0x0000

R/W

THRESH1_C [15:8]

[7:0]

Reserved

TS_CTRL_D [15:8]

SUBSAMPLE_ CH2_EN_D

D

SAMPLE_TYPE_D[1:0] INPUT_R_SELECT_D[1:0] TIMESLOT_OFFSET_ 0x0000

D[9:8]

[7:0]

TIMESLOT_OFFSET_D[7:0]

0x0161

TS_PATH_D [15:8]

PRE_WIDTH_D[3:0]

Reserved

TS_

AFE_

0x40DA

R/W

GPIO_D

PATH_

CFG_D[8]

[7:0]

AFE_PATH_CFG_D[7:0]

0x0162

0x0163

0x0164

INPUTS_D

[15:8]

[7:0]

INP78_D[3:0]

INP34_D[3:0]

INP56_D[3:0]

INP12_D[3:0]

0x0000

0x03C0

R/W

CATHODE_D [15:8]

[7:0]

Reserved

PRECON_D[2:0]

VC1_PULSE_D[1:0]

VC2_PULSE_D[1:0]

VC1_ALT_D[1:0]

VC2_ALT_D[1:0]

VC1_SEL_D[1:0]

VC2_SEL_D[1:0]

AFE_TRIM_D [15:8]

TIA_CEIL_

DETECT_EN_D

CH2_TRIM_INT_D[1:0]

CH1_TRIM_INT_D[1:0] VREF_

PULSE_D

AFE_TRIM_VREF_

D[1:0]

[7:0]

VREF_PULSE_VAL_D[1:0]

TIA_GAIN_CH2_D[2:0]

TIA_GAIN_CH1_D[2:0]

0x0165

0x0166

LED_

POW12_D

[15:8]

LED_

DRIVESIDE2_D

LED_CURRENT2_D[6:0]

LED_CURRENT1_D[6:0]

LED_CURRENT4_D[6:0]

LED_CURRENT3_D[6:0]

0x0000

0x0101

R/W

[7:0]

LED_

DRIVESIDE1_D

LED_

POW34_D

[15:8]

[7:0]

LED_

DRIVESIDE4_D

LED_

DRIVESIDE3_D

0x0167

0x0168

0x0169

0x016A

COUNTS_D [15:8]

[7:0]

NUM_INT_D[7:0]

NUM_REPEAT_D[7:0]

MOD_TYPE_D[1:0]

R/W

PERIOD_D

[15:8]

[7:0]

Reserved

MIN_PERIOD_D[9:8] 0x0000

0x0210

MIN_PERIOD_D[7:0]

LED_WIDTH_D[7:0]

LED_OFFSET_D[7:0]

LED_

PULSE_D

[15:8]

[7:0]

INTEG_

SETUP_D

[15:8]

SINGLE_

INTEG_D

CH2_AMP_DISABLE_D[2:0]

AFE_INT_C_

BUF_D

CH1_AMP_DISABLE_D[2:0]

0x0003

[7:0]

ADC_COUNT_D[1:0]

Reserved

INTEG_WIDTH_D[4:0]

0x016B

0x016C

0x016D

0x016E

0x016F

INTEG_OS_D [15:8]

[7:0]

INTEG_OFFSET_D[12:8]

INTEG_OFFSET_D[7:0]

0x0214

0x0001

0x0000

R/W

MOD_

PULSE_D

[15:8]

[7:0]

MOD_WIDTH_D[7:0]

MOD_OFFSET_D[7:0]

PATTERN_D [15:8]

[7:0]

LED_DISABLE_D[3:0]

SUBTRACT_D[3:0]

MOD_DISABLE_D[3:0]

REVERSE_INTEG_D[3:0]

ADC_OFF1_D [15:8]

[7:0]

Reserved

CH1_ADC_ADJUST_D[13:8]

CH1_ADC_ADJUST_D[7:0]

CH2_ADC_ADJUST_D[13:8]

ADC_OFF2_D [15:8]

ZERO_

ADJUST_D

Reserved

[7:0]

CH2_ADC_ADJUST_D[7:0]

DARK_SHIFT_D[4:0]

SIGNAL_SHIFT_D[4:0]

Rev. 0 | Page 60 of 101

0x0170

DATA_

FORMAT_D

[15:8]

[7:0]

DARK_SIZE_D[2:0]

SIGNAL_SIZE_D[2:0]

0x0003

R/W

Data Sheet

ADPD4100/ADPD4101

Bit 15

Bit 7

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 1

Bit 8

Bit 0

Reg

Name

Bits

Reset

R/W

0x0171

LIT_DATA_

FORMAT_D

[15:8]

[7:0]

Reserved

0x0000

R/W

LIT_SHIFT_D[4:0]

Reserved

LIT_SIZE_D[2:0]

0x0172

0x0173

DECIMATE_D [15:8]

[7:0]

DECIMATE_FACTOR_D[6:4]

DECIMATE_TYPE_D[3:0]

0x0000

0x0026

R/W

DECIMATE_FACTOR_D[3:0]

DIGINT_LIT_D [15:8]

Reserved

LIT_

OFFSET_

D[8]

[7:0]

LIT_OFFSET_D[7:0]

0x0174

0x0175

DIGINT_

DARK_D

[15:8]

[7:0]

DARK2_OFFSET_D[8:1]

0x2306

0x0000

R/W

DARK2_

OFFSET_D[0]

DARK1_OFFSET_D[6:0]

THRESH_

CFG_D

[15:8]

[7:0]

Reserved

THRESH1_TYPE_D[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_D[1:0]

CHAN_D DIR_D

THRESH0_SHIFT_D[4:0]

THRESH0_VALUE_D[7:0]

THRESH1_SHIFT_D[4:0]

THRESH1_VALUE_D[7:0]

THRESH1_

CHAN_D

THRESH1_

DIR_D

0x0176

0x0177

0x0180

THRESH0_D [15:8]

Reserved

0x0000

R/W

[7:0]

THRESH1_D [15:8]

[7:0]

Reserved

TS_CTRL_E

[15:8]

SUBSAMPLE_E CH2_EN_E

SAMPLE_TYPE_E[1:0]

INPUT_R_SELECT_E[1:0] TIMESLOT_OFFSET_ 0x0000

E[9:8]

[7:0]

TIMESLOT_OFFSET_E[7:0]

Reserved

0x0181

TS_PATH_E [15:8]

[7:0]

PRE_WIDTH_E[3:0]

TS_GPIO_E AFE_PATH 0x40DA

_CFG_E[8]

R/W

AFE_PATH_CFG_E[7:0]

0x0182

0x0183

0x0184

INPUTS_E

[15:8]

[7:0]

INP78_E[3:0]

INP34_E[3:0]

INP56_E[3:0]

INP12_E[3:0]

VC2_PULSE_E[1:0]

0x0000

0x03C0

R/W

CATHODE_E [15:8]

[7:0]

Reserved

PRECON_E[2:0]

VC1_PULSE_E[1:0]

VC2_ALT_E[1:0]

VC1_SEL_E[1:0]

VC2_SEL_E[1:0]

VC1_ALT_E[1:0]

AFE_TRIM_E [15:8]

TIA_CEIL_

DETECT_EN_E

CH2_TRIM_INT_E[1:0]

CH1_TRIM_INT_E[1:0] VREF_

AFE_TRIM_

VREF_E[1:0]

PULSE_E

[7:0]

VREF_PULSE_VAL_E[1:0]

TIA_GAIN_CH2_E[2:0]

TIA_GAIN_CH1_E[2:0]

0x0185

0x0186

LED_

POW12_E

[15:8]

LED_

DRIVESIDE2_E

LED_CURRENT2_E[6:0]

LED_CURRENT1_E[6:0]

LED_CURRENT4_E[6:0]

LED_CURRENT3_E[6:0]

0x0000

0x0101

R/W

[7:0]

LED_

DRIVESIDE1_E

LED_

POW34_E

[15:8]

[7:0]

LED_

DRIVESIDE4_E

LED_

DRIVESIDE3_E

0x0187

0x0188

0x0189

0x018A

COUNTS_E

PERIOD_E

[15:8]

[7:0]

NUM_INT_E[7:0]

NUM_REPEAT_E[7:0]

MOD_TYPE_E[1:0]

R/W

[15:8]

[7:0]

Reserved

MIN_PERIOD_E[9:8] 0x0000

0x0210

MIN_PERIOD_E[7:0]

LED_WIDTH_E[7:0]

LED_OFFSET_E[7:0]

LED_PULSE_E [15:8]

[7:0]

INTEG_

SETUP_E

[15:8]

SINGLE_

INTEG_E

CH2_AMP_DISABLE_E[2:0]

AFE_INT_

C_BUF_E

INTEG_WIDTH_E[4:0]

INTEG_OFFSET_E[12:8]

INTEG_OFFSET_E[7:0]

CH1_AMP_DISABLE_E[2:0]

0x0003

[7:0]

ADC_COUNT_E[1:0]

Reserved

0x018B

0x018C

0x018D

0x018E

INTEG_OS_E [15:8]

[7:0]

0x0214

0x0001

0x0000

R/W

MOD_

PULSE_E

[15:8]

[7:0]

MOD_WIDTH_E[7:0]

MOD_OFFSET_E[7:0]

PATTERN_E [15:8]

LED_DISABLE_E[3:0]

SUBTRACT_E[3:0]

MOD_DISABLE_E[3:0]

REVERSE_INTEG_E[3:0]

[7:0]

ADC_OFF1_E [15:8]

[7:0]

Reserved

CH1_ADC_ADJUST_E[13:8]

CH1_ADC_ADJUST_E[7:0]

Rev. 0 | Page 61 of 101

ADPD4100/ADPD4101

Data Sheet

Bit 15

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 1

Bit 8

Bit 0

Reg

Name

Bits

Bit 7

Reset

R/W

0x018F

ADC_OFF2_E [15:8]

ZERO_

ADJUST_E

Reserved

CH2_ADC_ADJUST_E[13:8]

0x0000

R/W

[7:0]

CH2_ADC_ADJUST_E[7:0]

0x0190

0x0191

0x0192

0x0193

DATA_

FORMAT_E

[15:8]

[7:0]

DARK_SHIFT_E[4:0]

SIGNAL_SHIFT_E[4:0]

DARK_SIZE_E[2:0]

0x0003

0x0000

0x0026

R/W

SIGNAL_SIZE_E[2:0]

LIT_DATA_

FORMAT_E

[15:8]

[7:0]

Reserved

LIT_SHIFT_E[4:0]

Reserved

LIT_SIZE_E[2:0]

DECIMATE_FACTOR_E[6:4]

DECIMATE_TYPE_E[3:0]

DECIMATE_E [15:8]

[7:0]

DECIMATE_FACTOR_E[3:0]

DIGINT_LIT_E [15:8]

Reserved

LIT_

OFFSET_

E[8]

[7:0]

LIT_OFFSET_E[7:0]

0x0194

0x0195

DIGINT_

DARK_E

[15:8]

[7:0]

DARK2_OFFSET_E[8:1]

0x2306

0x0000

R/W

DARK2_

OFFSET_E[0]

DARK1_OFFSET_E[6:0]

THRESH_

CFG_E

[15:8]

[7:0]

Reserved

THRESH1_TYPE_E[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_E[1:0]

CHAN_E DIR_E

THRESH0_SHIFT_E[4:0]

THRESH0_VALUE_E[7:0]

THRESH1_SHIFT_E[4:0]

THRESH1_VALUE_E[7:0]

THRESH1_

CHAN_E

THRESH1_

DIR_E

0x0196

0x0197

0x01A0

THRESH0_E [15:8]

Reserved

0x0000

R/W

[7:0]

THRESH1_E [15:8]

[7:0]

Reserved

TS_CTRL_F

[15:8]

SUBSAMPLE_F CH2_EN_F

SAMPLE_TYPE_F[1:0]

INPUT_R_SELECT_F[1:0] TIMESLOT_OFFSET_ 0x0000

F[9:8]

[7:0]

TIMESLOT_OFFSET_F[7:0]

Reserved

0x01A1

TS_PATH_F [15:8]

[7:0]

PRE_WIDTH_F[3:0]

TS_GPIO_F AFE_PATH 0x40DA

_CFG_F[8]

R/W

AFE_PATH_CFG_F[7:0]

0x01A2

0x01A3

0x01A4

INPUTS_F

[15:8]

[7:0]

INP78_F[3:0]

INP34_F[3:0]

INP56_F[3:0]

INP12_F[3:0]

VC2_PULSE_F[1:0]

0x0000

0x03C0

R/W

CATHODE_F [15:8]

[7:0]

Reserved

PRECON_F[2:0]

VC1_PULSE_F[1:0]

VC2_ALT_F[1:0]

VC1_SEL_F[1:0]

VC2_SEL_F[1:0]

VC1_ALT_F[1:0]

AFE_TRIM_F [15:8]

TIA_CEIL_

DETECT_EN_F

CH2_TRIM_INT_F[1:0]

CH1_TRIM_INT_F[1:0] VREF_

AFE_TRIM_VREF_

F[1:0]

PULSE_F

[7:0]

VREF_PULSE_VAL_F[1:0]

TIA_GAIN_CH2_F[2:0]

TIA_GAIN_CH1_F[2:0]

0x01A5

0x01A6

LED_

POW12_F

[15:8]

LED_

DRIVESIDE2_F

LED_CURRENT2_F[6:0]

LED_CURRENT1_F[6:0]

LED_CURRENT4_F[6:0]

LED_CURRENT3_F[6:0]

0x0000

0x0101

R/W

[7:0]

LED_

DRIVESIDE1_F

LED_

POW34_F

[15:8]

[7:0]

LED_

DRIVESIDE4_F

LED_

DRIVESIDE3_F

0x01A7

0x01A8

0x01A9

0x01AA

COUNTS_F

PERIOD_F

[15:8]

[7:0]

NUM_INT_F[7:0]

NUM_REPEAT_F[7:0]

MOD_TYPE_F[1:0]

R/W

[15:8]

[7:0]

Reserved

MIN_PERIOD_F[9:8] 0x0000

0x0210

MIN_PERIOD_F[7:0]

LED_WIDTH_F[7:0]

LED_OFFSET_F[7:0]

LED_PULSE_F [15:8]

[7:0]

INTEG_

SETUP_F

[15:8]

SINGLE_

INTEG_F

CH2_AMP_DISABLE_F[2:0]

AFE_INT_C_

BUF_F

CH1_AMP_DISABLE_F[2:0]

0x0003

[7:0]

ADC_COUNT_F[1:0]

Reserved

INTEG_WIDTH_F[4:0]

INTEG_OFFSET_F[12:8]

0x01AB

0x01AC

INTEG_OS_F [15:8]

[7:0]

0x0214

0x0001

R/W

INTEG_OFFSET_F[7:0]

MOD_WIDTH_F[7:0]

MOD_OFFSET_F[7:0]

MOD_

PULSE_F

[15:8]

[7:0]

Rev. 0 | Page 62 of 101

Data Sheet

ADPD4100/ADPD4101

Bit 15

Bit 7

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 1

Bit 8

Bit 0

Reg

Name

Bits

Reset

R/W

0x01AD

PATTERN_F [15:8]

[7:0]

LED_DISABLE_F[3:0]

SUBTRACT_F[3:0]

MOD_DISABLE_F[3:0]

REVERSE_INTEG_F[3:0]

0x0000

R/W

0x01AE

0x01AF

ADC_OFF1_F [15:8]

[7:0]

Reserved

CH1_ADC_ADJUST_F[13:8]

CH1_ADC_ADJUST_F[7:0]

CH2_ADC_ADJUST_F[13:8]

0x0000

R/W

ADC_OFF2_F [15:8]

ZERO_

Reserved

ADJUST_F

[7:0]

CH2_ADC_ADJUST_F[7:0]

DARK_SHIFT_F[4:0]

0x01B0

0x01B1

0x01B2

0x01B3

DATA_

FORMAT_F

[15:8]

[7:0]

DARK_SIZE_F[2:0]

0x0003

0x0000

0x0026

R/W

SIGNAL_SHIFT_F[4:0]

SIGNAL_SIZE_F[2:0]

LIT_DATA_

FORMAT_F

[15:8]

[7:0]

Reserved

LIT_SHIFT_F[4:0]

Reserved

LIT_SIZE_F[2:0]

DECIMATE_FACTOR_F[6:4]

DECIMATE_TYPE_F[3:0]

DECIMATE_F [15:8]

[7:0]

DECIMATE_FACTOR_F[3:0]

DIGINT_LIT_F [15:8]

Reserved

LIT_

OFFSET_

F[8]

[7:0]

LIT_OFFSET_F[7:0]

0x01B4

0x01B5

DIGINT_

DARK_F

[15:8]

[7:0]

DARK2_OFFSET_F[8:1]

0x2306

0x0000

R/W

DARK2_

OFFSET_F[0]

DARK1_OFFSET_F[6:0]

THRESH_

CFG_F

[15:8]

[7:0]

Reserved

THRESH1_TYPE_F[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_F[1:0]

CHAN_F DIR_F

THRESH0_SHIFT_F[4:0]

THRESH0_VALUE_F[7:0]

THRESH1_SHIFT_F[4:0]

THRESH1_VALUE_F[7:0]

THRESH1_

CHAN_F

THRESH1_

DIR_F

0x01B6

0x01B7

0x01C0

THRESH0_F [15:8]

[7:0]

Reserved

0x0000

R/W

THRESH1_F [15:8]

[7:0]

Reserved

TS_CTRL_G [15:8]

SUBSAMPLE_ CH2_EN_G

G

SAMPLE_TYPE_G[1:0] INPUT_R_SELECT_G[1:0] TIMESLOT_OFFSET_ 0x0000

G[9:8]

[7:0]

TIMESLOT_OFFSET_G[7:0]

0x01C1

TS_PATH_G [15:8]

PRE_WIDTH_G[3:0]

Reserved

TS_

GPIO_G

AFE_PATH_ 0x40DA

CFG_G[8]

R/W

[7:0]

AFE_PATH_CFG_G[7:0]

0x01C2

0x01C3

0x01C4

INPUTS_G

[15:8]

[7:0]

INP78_G[3:0]

INP34_G[3:0]

INP56_G[3:0]

INP12_G[3:0]

0x0000

R/W

CATHODE_G [15:8]

[7:0]

Reserved

PRECON_G[2:0]

VC1_PULSE_G[1:0]

VC2_PULSE_G[1:0]

VC1_ALT_G[1:0]

VC2_ALT_G[1:0]

VC1_SEL_G[1:0]

0x0000

VC2_SEL_G[1:0]

AFE_TRIM_G [15:8]

TIA_CEIL_

DETECT_EN_G

CH2_TRIM_INT_G[1:0]

CH1_TRIM_INT_G[1:0] VREF_

PULSE_G

AFE_TRIM_VREF_G[1:0] 0x03C0

[7:0]

VREF_PULSE_VAL_G[1:0]

LED_

DRIVESIDE2_G

TIA_GAIN_CH2_G[2:0]

TIA_GAIN_CH1_G[2:0]

0x01C5

0x01C6

LED_

POW12_G

[15:8]

LED_CURRENT2_G[6:0]

LED_CURRENT1_G[6:0]

LED_CURRENT4_G[6:0]

LED_CURRENT3_G[6:0]

0x0000

R/W

[7:0]

LED_

DRIVESIDE1_G

LED_

POW34_G

[15:8]

[7:0]

LED_

DRIVESIDE4_G

0x0000

LED_

DRIVESIDE3_G

0x01C7

0x01C8

0x01C9

0x01CA

COUNTS_G

PERIOD_G

[15:8]

[7:0]

NUM_INT_G[7:0]

NUM_REPEAT_G[7:0]

MOD_TYPE_G[1:0]

0x0101

MIN_PERIOD_G[9:8] 0x0000

0x0210

R/W

[15:8]

[7:0]

Reserved

MIN_PERIOD_G[7:0]

LED_WIDTH_G[7:0]

LED_OFFSET_G[7:0]

LED_PULSE_G [15:8]

[7:0]

INTEG_

SETUP_G

[15:8]

SINGLE_

INTEG_G

CH2_AMP_DISABLE_G[2:0]

AFE_INT_C_

BUF_G

CH1_AMP_DISABLE_G[2:0]

0x0003

[7:0]

ADC_COUNT_G[1:0]

Reserved

INTEG_WIDTH_G[4:0]

Rev. 0 | Page 63 of 101

ADPD4100/ADPD4101

Data Sheet

Bit 15

Bit 14

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 1

Bit 8

Bit 0

Reg

Name

Bits

Bit 7

Bit 6

Reset

R/W

0x01CB

INTEG_OS_G [15:8]

[7:0]

Reserved

INTEG_OFFSET_G[12:8]

0x0214

R/W

INTEG_OFFSET_G[7:0]

MOD_WIDTH_G[7:0]

MOD_OFFSET_G[7:0]

0x01CC

0x01CD

0x01CE

0x01CF

MOD_

PULSE_G

[15:8]

[7:0]

0x0001

0x0000

R/W

PATTERN_G [15:8]

[7:0]

LED_DISABLE_G[3:0]

SUBTRACT_G[3:0]

MOD_DISABLE_G[3:0]

REVERSE_INTEG_G[3:0]

ADC_OFF1_G [15:8]

[7:0]

Reserved

CH1_ADC_ADJUST_G[13:8]

CH1_ADC_ADJUST_G[7:0]

CH2_ADC_ADJUST_G[13:8]

ADC_OFF2_G [15:8]

ZERO_

Reserved

ADJUST_G

[7:0]

CH2_ADC_ADJUST_G[7:0]

DARK_SHIFT_G[4:0]

0x01D0

0x01D1

0x01D2

0x01D3

DATA_

FORMAT_G

[15:8]

[7:0]

DARK_SIZE_G[2:0]

SIGNAL_SIZE_G[2:0]

0x0003

0x0000

0x0026

R/W

SIGNAL_SHIFT_G[4:0]

LIT_DATA_

FORMAT_G

[15:8]

[7:0]

Reserved

LIT_SHIFT_G[4:0]

Reserved

LIT_SIZE_G[2:0]

DECIMATE_FACTOR_G[6:4]

DECIMATE_TYPE_G[3:0]

DECIMATE_G [15:8]

[7:0]

DECIMATE_FACTOR_G[3:0]

DIGINT_LIT_G [15:8]

Reserved

LIT_

OFFSET_

G[8]

[7:0]

LIT_OFFSET_G[7:0]

0x01D4

0x01D5

DIGINT_

DARK_G

[15:8]

[7:0]

DARK2_OFFSET_G[8:1]

0x2306

0x0000

R/W

DARK2_

OFFSET_G[0]

DARK1_OFFSET_G[6:0]

THRESH_

CFG_G

[15:8]

[7:0]

Reserved

THRESH1_TYPE_G[1:0] THRESH0_ THRESH0_

CHAN_G DIR_G

THRESH0_SHIFT_G[4:0]

THRESH0_VALUE_G[7:0]

THRESH1_SHIFT_G[4:0]

THRESH1_VALUE_G[7:0]

THRESH1_

CHAN_G

THRESH1_

DIR_G

THRESH0_TYPE_

G[1:0]

0x01D6

0x01D7

0x01E0

THRESH0_G [15:8]

[7:0]

Reserved

0x0000

R/W

THRESH1_G [15:8]

[7:0]

Reserved

TS_CTRL_H [15:8]

SUBSAMPLE_ CH2_EN_H

H

SAMPLE_TYPE_H[1:0] INPUT_R_SELECT_H[1:0] TIMESLOT_OFFSET_ 0x0000

H[9:8]

[7:0]

TIMESLOT_OFFSET_H[7:0]

0x01E1

TS_PATH_H [15:8]

PRE_WIDTH_H[3:0]

Reserved

TS_GPIO_ AFE_PATH_ 0x40DA

R/W

H

CFG_H[8]

[7:0]

AFE_PATH_CFG_H[7:0]

0x01E2

0x01E3

0x01E4

INPUTS_H

[15:8]

[7:0]

INP78_H[3:0]

INP34_H[3:0]

INP56_H[3:0]

INP12_H[3:0]

0x0000

0x03C0

R/W

CATHODE_H [15:8]

[7:0]

Reserved

PRECON_H[2:0]

VC1_PULSE_H[1:0]

VC2_PULSE_H[1:0]

VC1_ALT_H[1:0]

VC2_ALT_H[1:0]

VC1_SEL_H[1:0]

VC2_SEL_H[1:0]

AFE_TRIM_H [15:8]

TIA_CEIL_

DETECT_EN_H

CH2_TRIM_INT_H[1:0]

CH1_TRIM_INT_H[1:0] VREF_

PULSE_H

AFE_TRIM_

VREF_H[1:0]

[7:0]

VREF_PULSE_VAL_H[1:0]

LED_

DRIVESIDE2_H

TIA_GAIN_CH2_H[2:0]

TIA_GAIN_CH1_H[2:0]

0x01E5

0x01E6

LED_

POW12_H

[15:8]

LED_CURRENT2_H[6:0]

LED_CURRENT1_H[6:0]

LED_CURRENT4_H[6:0]

LED_CURRENT3_H[6:0]

0x0000

0x0101

R/W

[7:0]

LED_

DRIVESIDE1_H

LED_

POW34_H

[15:8]

[7:0]

LED_

DRIVESIDE4_H

LED_

DRIVESIDE3_H

0x01E7

0x01E8

0x01E9

COUNTS_H

PERIOD_H

[15:8]

[7:0]

NUM_INT_H[7:0]

NUM_REPEAT_H[7:0]

MOD_TYPE_H[1:0]

R/W

[15:8]

[7:0]

Reserved

MIN_PERIOD_H[9:8] 0x0000

0x0210

MIN_PERIOD_H[7:0]

LED_WIDTH_H[7:0]

LED_OFFSET_H[7:0]

LED_PULSE_H [15:8]

[7:0]

Rev. 0 | Page 64 of 101

Data Sheet

ADPD4100/ADPD4101

Bit 15

Bit 7

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 1

Bit 8

Bit 0

Reg

Name

Bits

Reset

R/W

0x01EA

INTEG_

SETUP_H

[15:8]

SINGLE_

INTEG_H

CH2_AMP_DISABLE_H[2:0]

AFE_INT_C_

BUF_H

CH1_AMP_DISABLE_H[2:0]

0x0003

R/W

[7:0]

ADC_COUNT_H[1:0]

Reserved

INTEG_WIDTH_H[4:0]

INTEG_ OFFSET_H[12:8]

INTEG_OFFSET_H[7:0]

0x01EB

0x01EC

0x01ED

0x01EE

0x01EF

INTEG_OS_H [15:8]

[7:0]

0x0214

0x0001

0x0000

R/W

MOD_

PULSE_H

[15:8]

[7:0]

MOD_WIDTH_H[7:0]

MOD_OFFSET_H[7:0]

PATTERN_H [15:8]

[7:0]

LED_DISABLE_H[3:0]

SUBTRACT_H[3:0]

MOD_DISABLE_H[3:0]

REVERSE_INTEG_H[3:0]

ADC_OFF1_H [15:8]

[7:0]

Reserved

CH1_ADC_ADJUST_H[13:8]

CH1_ADC_ADJUST_H[7:0]

CH2_ADC_ADJUST_H[13:8]

ADC_OFF2_H [15:8]

ZERO_

Reserved

ADJUST_H

[7:0]

CH2_ADC_ADJUST_H[7:0]

DARK_SHIFT_H[4:0]

0x01F0

0x01F1

0x01F2

0x01F3

DATA_

FORMAT_H

[15:8]

[7:0]

DARK_SIZE_H[2:0]

SIGNAL_SIZE_H[2:0]

0x0003

0x0000

0x0026

R/W

SIGNAL_SHIFT_H[4:0]

LIT_DATA_

FORMAT_H

[15:8]

[7:0]

Reserved

LIT_SHIFT_H[4:0]

Reserved

LIT_SIZE_H[2:0]

DECIMATE_FACTOR_H[6:4]

DECIMATE_TYPE_H[3:0]

DECIMATE_H [15:8]

[7:0]

DECIMATE_FACTOR_H[3:0]

DIGINT_LIT_H [15:8]

Reserved

LIT_

OFFSET_

H[8]

[7:0]

LIT_OFFSET_H[7:0]

0x01F4

0x01F5

DIGINT_

DARK_H

[15:8]

[7:0]

DARK2_OFFSET_H[8:1]

0x2306

0x0000

R/W

DARK2_

OFFSET_H[0]

DARK1_OFFSET_H[6:0]

THRESH_

CFG_H

[15:8]

[7:0]

Reserved

THRESH1_TYPE_H[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_H[1:0]

CHAN_H DIR_H

THRESH0_SHIFT_H[4:0]

THRESH0_VALUE_H[7:0]

THRESH1_SHIFT_H[4:0]

THRESH1_VALUE_H[7:0]

SAMPLE_TYPE_I[1:0] INPUT_R_SELECT_I[1:0]

THRESH1_

CHAN_H

THRESH1_

DIR_H

0x01F6

0x01F7

0x0200

THRESH0_H [15:8]

Reserved

0x0000

R/W

[7:0]

THRESH1_H [15:8]

[7:0]

Reserved

TS_CTRL_I

TS_PATH_I

INPUTS_I

[15:8]

SUBSAMPLE_I CH2_EN_I

TIMESLOT_

OFFSET_I[9:8]

[7:0]

TIMESLOT_OFFSET_I[7:0]

Reserved

0x0201

[15:8]

PRE_WIDTH_I[3:0]

TS_GPIO_I AFE_PATH 0x40DA

_CFG_I[8]

R/W

[7:0]

[15:8]

[7:0]

AFE_PATH_CFG_I[7:0]

0x0202

0x0203

0x0204

INP78_I[3:0]

INP34_I[3:0]

INP56_I[3:0]

INP12_I[3:0]

0x0000

R/W

CATHODE_I [15:8]

[7:0]

Reserved

PRECON_I[2:0]

VC1_PULSE_I[1:0]

CH2_TRIM_INT_I[1:0]

VC2_PULSE_I[1:0]

VC1_ALT_I[1:0]

VC2_ALT_I[1:0]

VC1_SEL_I[1:0]

VC2_SEL_I[1:0]

AFE_TRIM_I [15:8]

TIA_CEIL_

CH1_TRIM_INT_I[1:0]

VREF_

AFE_TRIM_ VREF_I[1:0] 0x03C0

DETECT_EN_I

PULSE_I

[7:0]

VREF_PULSE_VAL_I[1:0]

LED_

TIA_GAIN_CH2_I[2:0]

LED_CURRENT2_I[6:0]

TIA_GAIN_CH1_I[2:0]

0x0205

0x0206

0x0207

LED_

POW12_I

[15:8]

0x0000

0x0101

R/W

DRIVESIDE2_I

[7:0]

LED_

DRIVESIDE1_I

LED_CURRENT1_I[6:0]

LED_CURRENT4_I[6:0]

LED_CURRENT3_I[6:0]

LED_

POW34_I

[15:8]

[7:0]

LED_

DRIVESIDE4_I

LED_

DRIVESIDE3_I

COUNTS_I

[15:8]

[7:0]

NUM_INT_I[7:0]

NUM_REPEAT_I[7:0]

Rev. 0 | Page 65 of 101

ADPD4100/ADPD4101

Data Sheet

Bit 15

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 1

Bit 8

Bit 0

Reg

Name

Bits

Bit 7

Reset

R/W

0x0208

PERIOD_I

[15:8]

[7:0]

Reserved

MOD_TYPE_I[1:0]

Reserved

MIN_PERIOD_I[9:8] 0x0000

R/W

MIN_PERIOD_I[7:0]

LED_WIDTH_I[7:0]

LED_OFFSET_I[7:0]

0x0209

0x020A

LED_PULSE_I [15:8]

[7:0]

0x0210

R/W

INTEG_

SETUP_I

[15:8]

SINGLE_

INTEG_I

CH2_AMP_DISABLE_I[2:0]

AFE_INT_

C_BUF_I

CH1_AMP_DISABLE_I[2:0]

0x0003

[7:0]

ADC_COUNT_I[1:0]

Reserved

INTEG_WIDTH_I[4:0]

INTEG_OFFSET_I[12:8]

0x020B

0x020C

0x020D

0x020E

0x020F

INTEG_OS_I [15:8]

[7:0]

0x0214

0x0001

0x0000

R/W

INTEG_OFFSET_I[7:0]

MOD_WIDTH_I[7:0]

MOD_OFFSET_I[7:0]

MOD_

PULSE_I

[15:8]

[7:0]

PATTERN_I

[15:8]

[7:0]

LED_DISABLE_I[3:0]

SUBTRACT_I[3:0]

MOD_DISABLE_I[3:0]

REVERSE_INTEG_I[3:0]

CH1_ADC_ADJUST_I[13:8]

CH1_ADC_ADJUST_I[7:0]

CH2_ADC_ADJUST_I[13:8]

ADC_OFF1_I [15:8]

[7:0]

Reserved

ADC_OFF2_I [15:8]

ZERO_

Reserved

ADJUST_I

[7:0]

CH2_ADC_ADJUST_I[7:0]

DARK_SHIFT_I[4:0]

0x0210

0x0211

0x0212

0x0213

DATA_

FORMAT_I

[15:8]

[7:0]

DARK_SIZE_I[2:0]

0x0003

0x0000

0x0026

R/W

SIGNAL_SHIFT_I[4:0]

SIGNAL_SIZE_I[2:0]

LIT_DATA_

FORMAT_I

[15:8]

[7:0]

Reserved

LIT_SHIFT_I[4:0]

Reserved

LIT_SIZE_I[2:0]

DECIMATE_FACTOR_I[6:4]

DECIMATE_TYPE_I[3:0]

DECIMATE_I [15:8]

[7:0]

DECIMATE_FACTOR_I[3:0]

DIGINT_LIT_I [15:8]

Reserved

LIT_

OFFSET_

I[8]

[7:0]

LIT_OFFSET_I[7:0]

0x0214

0x0215

DIGINT_

DARK_I

[15:8]

[7:0]

DARK2_OFFSET_I[8:1]

0x2306

0x0000

R/W

DARK2_

OFFSET_I[0]

DARK1_OFFSET_I[6:0]

THRESH_

CFG_I

[15:8]

[7:0]

Reserved

THRESH1_TYPE_I[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_I[1:0]

CHAN_I DIR_I

THRESH0_SHIFT_I[4:0]

THRESH0_VALUE_I[7:0]

THRESH1_SHIFT_I[4:0]

THRESH1_VALUE_I[7:0]

SAMPLE_TYPE_J[1:0] INPUT_R_SELECT_J[1:0]

THRESH1_

CHAN_I

THRESH1_

DIR_I

0x0216

0x0217

0x0220

THRESH0_I

THRESH1_I

TS_CTRL_J

[15:8]

[7:0]

Reserved

0x0000

R/W

[15:8]

[7:0]

Reserved

[15:8]

SUBSAMPLE_J CH2_EN_J

TIMESLOT_

OFFSET_J[9:8]

[7:0]

TIMESLOT_OFFSET_J[7:0]

Reserved

0x0221

TS_PATH_J

INPUTS_J

[15:8]

PRE_WIDTH_J[3:0]

TS_GPIO_J AFE_PATH 0x40DA

_CFG_J[8]

R/W

[7:0]

[15:8]

[7:0]

AFE_PATH_CFG_J[7:0]

0x0222

0x0223

0x0224

INP78_J[3:0]

INP34_J[3:0]

INP56_J[3:0]

INP12_J[3:0]

0x0000

0x03C0

R/W

CATHODE_J [15:8]

[7:0]

Reserved

PRECON_J[2:0]

VC1_PULSE_J[1:0]

CH2_TRIM_INT_J[1:0]

VC2_PULSE_J[1:0]

VC1_ALT_J[1:0]

VC2_ALT_J[1:0]

VC1_SEL_J[1:0]

VC2_SEL_J[1:0]

AFE_TRIM_J [15:8]

TIA_CEIL_

DETECT_EN_J

CH1_TRIM_INT_J[1:0]

VREF_

PULSE_J

AFE_TRIM_

VREF_J[1:0]

[7:0]

VREF_PULSE_VAL_J[1:0]

TIA_GAIN_CH2_J[2:0]

LED_CURRENT2_J[6:0]

TIA_GAIN_CH1_J[2:0]

0x0225

LED_

POW12_J

[15:8]

LED_

0x0000

R/W

DRIVESIDE2_J

[7:0]

LED_

LED_CURRENT1_J[6:0]

DRIVESIDE1_J

Rev. 0 | Page 66 of 101

Data Sheet

ADPD4100/ADPD4101

Bit 15

Bit 7

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 1

Bit 8

Bit 0

Reg

Name

Bits

Reset

R/W

0x0226

LED_

POW34_J

[15:8]

LED_

DRIVESIDE4_J

LED_CURRENT4_J[6:0]

0x0000

R/W

[7:0]

LED_

LED_CURRENT3_J[6:0]

DRIVESIDE3_J

0x0227

0x0228

0x0229

0x022A

COUNTS_J

PERIOD_J

[15:8]

[7:0]

NUM_INT_J[7:0]

NUM_REPEAT_J[7:0]

MOD_TYPE_J[1:0]

0x0101

R/W

[15:8]

[7:0]

Reserved

MIN_PERIOD_J[9:8] 0x0000

0x0210

MIN_PERIOD_J[7:0]

LED_WIDTH_J[7:0]

LED_OFFSET_J[7:0]

LED_PULSE_J [15:8]

[7:0]

INTEG_

SETUP_J

[15:8]

SINGLE_

INTEG_J

CH2_AMP_DISABLE_J[2:0]

AFE_INT_

C_BUF_J

INTEG_WIDTH_J[4:0]

INTEG_ OFFSET_J[12:8]

INTEG_OFFSET_J[7:0]

CH1_AMP_DISABLE_J[2:0]

0x0003

[7:0]

ADC_COUNT_J[1:0]

Reserved

0x022B

0x022C

0x022D

0x022E

0x022F

INTEG_OS_J [15:8]

[7:0]

0x0214

0x0001

0x0000

R/W

MOD_

PULSE_J

[15:8]

[7:0]

MOD_WIDTH_J[7:0]

MOD_OFFSET_J[7:0]

PATTERN_J

[15:8]

[7:0]

LED_DISABLE_J[3:0]

SUBTRACT_J[3:0]

MOD_DISABLE_J[3:0]

REVERSE_INTEG_J[3:0]

ADC_OFF1_J [15:8]

[7:0]

Reserved

CH1_ADC_ADJUST_J[13:8]

CH1_ADC_ADJUST_J[7:0]

CH2_ADC_ADJUST_J[13:8]

ADC_OFF2_J [15:8]

ZERO_

Reserved

ADJUST_J

[7:0]

CH2_ADC_ADJUST_J[7:0]

DARK_SHIFT_J[4:0]

0x0230

0x0231

0x0232

0x0233

DATA_

FORMAT_J

[15:8]

[7:0]

DARK_SIZE_J[2:0]

0x0003

0x0000

0x0026

R/W

SIGNAL_SHIFT_J[4:0]

SIGNAL_SIZE_J[2:0]

LIT_DATA_

FORMAT_J

[15:8]

[7:0]

Reserved

LIT_SHIFT_J[4:0]

Reserved

LIT_SIZE_J[2:0]

DECIMATE_FACTOR_J[6:4]

DECIMATE_TYPE_J[3:0]

DECIMATE_J [15:8]

[7:0]

DECIMATE_FACTOR_J[3:0]

DIGINT_LIT_J [15:8]

Reserved

LIT_

OFFSET_

J[8]

[7:0]

LIT_OFFSET_J[7:0]

0x0234

0x0235

DIGINT_

DARK_J

[15:8]

[7:0]

DARK2_OFFSET_J[8:1]

0x2306

0x0000

R/W

DARK2_

OFFSET_J[0]

DARK1_OFFSET_J[6:0]

THRESH_

CFG_J

[15:8]

[7:0]

Reserved

THRESH1_TYPE_J[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_J[1:0]

CHAN_J DIR_J

THRESH0_SHIFT_J[4:0]

THRESH0_VALUE_J[7:0]

THRESH1_SHIFT_J[4:0]

THRESH1_VALUE_J[7:0]

THRESH1_

CHAN_J

THRESH1_

DIR_J

0x0236

0x0237

0x0240

THRESH0_J

THRESH1_J

TS_CTRL_K

[15:8]

[7:0]

Reserved

0x0000

R/W

[15:8]

[7:0]

Reserved

[15:8]

SUBSAMPLE_K CH2_EN_K

SAMPLE_TYPE_K[1:0] INPUT_R_SELECT_K[1:0]

TIMESLOT_

OFFSET_K[9:8]

[7:0]

TIMESLOT_OFFSET_K[7:0]

0x0241

TS_PATH_K [15:8]

PRE_WIDTH_K[3:0]

Reserved

AFE_PATH_CFG_K[7:0]

TS_GPIO_K AFE_PATH 0x40DA

_CFG_K[8]

R/W

[7:0]

0x0242

0x0243

0x0244

INPUTS_K

[15:8]

[7:0]

INP78_K[3:0]

INP34_K[3:0]

PRECON_K[2:0]

VC1_PULSE_K[1:0]

INP56_K[3:0]

INP12_K[3:0]

0x0000

0x03C0

R/W

CATHODE_K [15:8]

[7:0]

Reserved

VC2_PULSE_K[1:0]

VC1_ALT_K[1:0]

VC2_ALT_K[1:0]

VC1_SEL_K[1:0]

VC2_SEL_K[1:0]

AFE_TRIM_K [15:8]

TIA_CEIL_

DETECT_EN_K

CH2_TRIM_INT_K[1:0]

CH1_TRIM_INT_K[1:0] VREF_

PULSE_K

AFE_TRIM_

VREF_K[1:0]

[7:0]

VREF_PULSE_VAL_K[1:0]

TIA_GAIN_CH2_K[2:0]

TIA_GAIN_CH1_K[2:0]

Rev. 0 | Page 67 of 101

ADPD4100/ADPD4101

Data Sheet

Bit 15

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 1

Bit 8

Bit 0

Reg

Name

Bits

Bit 7

Reset

R/W

0x0245

LED_

POW12_K

[15:8]

LED_

DRIVESIDE2_K

LED_CURRENT2_K[6:0]

LED_CURRENT1_K[6:0]

LED_CURRENT4_K[6:0]

LED_CURRENT3_K[6:0]

0x0000

R/W

[7:0]

[15:8]

[7:0]

LED_

DRIVESIDE1_K

0x0246

LED_

POW34_K

LED_

DRIVESIDE4_K

0x0000

0x0101

R/W

LED_

DRIVESIDE3_K

0x0247

0x0248

0x0249

0x024A

COUNTS_K

PERIOD_K

[15:8]

[7:0]

NUM_INT_K[7:0]

NUM_REPEAT_K[7:0]

MOD_TYPE_K[1:0]

R/W

[15:8]

[7:0]

Reserved

MIN_PERIOD_K[9:8] 0x0000

0x0210

MIN_PERIOD_K[7:0]

LED_WIDTH_K[7:0]

LED_OFFSET_K[7:0]

LED_PULSE_K [15:8]

[7:0]

INTEG_

SETUP_K

[15:8]

SINGLE_

INTEG_K

CH2_AMP_DISABLE_K[2:0]

AFE_INT_C_

BUF_K

CH1_AMP_DISABLE_K[2:0]

0x0003

[7:0]

ADC_COUNT_K[1:0]

Reserved

INTEG_WIDTH_K[4:0]

INTEG_ OFFSET_K[12:8]

INTEG_OFFSET_K[7:0]

0x024B

0x024C

0x024D

0x024E

0x024F

INTEG_OS_K [15:8]

[7:0]

0x0214

0x0001

0x0000

R/W

MOD_

PULSE_K

[15:8]

[7:0]

MOD_WIDTH_K[7:0]

MOD_OFFSET_K[7:0]

PATTERN_K [15:8]

[7:0]

LED_DISABLE_K[3:0]

SUBTRACT_K[3:0]

MOD_DISABLE_K[3:0]

REVERSE_INTEG_K[3:0]

ADC_OFF1_K [15:8]

[7:0]

Reserved

CH1_ADC_ADJUST_K[13:8]

CH1_ADC_ADJUST_K[7:0]

CH2_ADC_ADJUST_K[13:8]

ADC_OFF2_K [15:8]

ZERO_

Reserved

ADJUST_K

[7:0]

CH2_ADC_ADJUST_K[7:0]

DARK_SHIFT_K[4:0]

0x0250

0x0251

0x0252

0x0253

DATA_

FORMAT_K

[15:8]

[7:0]

DARK_SIZE_K[2:0]

0x0003

0x0000

0x0026

R/W

SIGNAL_SHIFT_K[4:0]

SIGNAL_SIZE_K[2:0]

LIT_DATA_

FORMAT_K

[15:8]

[7:0]

Reserved

LIT_SHIFT_K[4:0]

Reserved

LIT_SIZE_K[2:0]

DECIMATE_FACTOR_K[6:4]

DECIMATE_TYPE_K[3:0]

DECIMATE_K [15:8]

[7:0]

DECIMATE_FACTOR_K[3:0]

DIGINT_LIT_K [15:8]

Reserved

LIT_

OFFSET_

K[8]

[7:0]

LIT_OFFSET_K[7:0]

0x0254

0x0255

DIGINT_

DARK_K

[15:8]

[7:0]

DARK2_OFFSET_K[8:1]

0x2306

0x0000

R/W

DARK2_

OFFSET_K[0]

DARK1_OFFSET_K[6:0]

THRESH_

CFG_K

[15:8]

[7:0]

Reserved

THRESH1_TYPE_K[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_ K[1:0]

CHAN_K DIR_K

THRESH0_SHIFT_K[4:0]

THRESH0_VALUE_K[7:0]

THRESH1_SHIFT_K[4:0]

THRESH1_VALUE_K[7:0]

SAMPLE_TYPE_L[1:0] INPUT_R_SELECT_L[1:0]

THRESH1_

CHAN_K

THRESH1_

DIR_K

0x0256

0x0257

0x0260

THRESH0_K [15:8]

Reserved

0x0000

R/W

[7:0]

THRESH1_K [15:8]

[7:0]

Reserved

TS_CTRL_L

[15:8]

SUBSAMPLE_L CH2_EN_L

TIMESLOT_

OFFSET_L[9:8]

[7:0]

TIMESLOT_OFFSET_L[7:0]

Reserved

0x0261

TS_PATH_L [15:8]

[7:0]

PRE_WIDTH_L[3:0]

TS_GPIO_L AFE_PATH 0x40DA

_CFG_L[8]

R/W

AFE_PATH_CFG_L[7:0]

0x0262

0x0263

INPUTS_L

[15:8]

[7:0]

INP78_L[3:0]

INP34_L[3:0]

INP56_L[3:0]

INP12_L[3:0]

0x0000

R/W

CATHODE_L [15:8]

[7:0]

Reserved

VC2_SEL_L[1:0]

PRECON_L[2:0]

VC1_PULSE_L[1:0]

VC2_PULSE_L[1:0]

VC1_ALT_L[1:0]

VC2_ALT_L[1:0]

VC1_SEL_L[1:0]

Rev. 0 | Page 68 of 101

Data Sheet

ADPD4100/ADPD4101

Bit 15

Bit 7

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 1

Bit 8

Bit 0

Reg

Name

Bits

Reset

R/W

0x0264

AFE_TRIM_L [15:8]

TIA_CEIL_

DETECT_EN_L

CH2_TRIM_INT_L[1:0]

CH1_TRIM_INT_L[1:0] VREF_

PULSE_L

AFE_TRIM_

VREF_L[1:0]

0x03C0

R/W

[7:0]

VREF_PULSE_VAL_L[1:0]

TIA_GAIN_CH2_L[2:0]

TIA_GAIN_CH1_L[2:0]

0x0265

0x0266

LED_

POW12_L

[15:8]

[7:0]

LED_

DRIVESIDE2_L

LED_CURRENT2_L[6:0]

LED_CURRENT1_L[6:0]

LED_CURRENT4_L[6:0]

LED_CURRENT3_L[6:0]

0x0000

0x0101

R/W

LED_

DRIVESIDE1_L

LED_

POW34_L

[15:8]

[7:0]

LED_

DRIVESIDE4_L

LED_

DRIVESIDE3_L

0x0267

0x0268

0x0269

0x026A

COUNTS_L

PERIOD_L

[15:8]

[7:0]

NUM_INT_L[7:0]

NUM_REPEAT_L[7:0]

MOD_TYPE_L[1:0]

R/W

[15:8]

[7:0]

Reserved

MIN_PERIOD_L[9:8] 0x0000

0x0210

MIN_PERIOD_L[7:0]

LED_WIDTH_L[7:0]

LED_OFFSET_L[7:0]

LED_PULSE_L [15:8]

[7:0]

INTEG_

SETUP_L

[15:8]

SINGLE_

INTEG_L

CH2_AMP_DISABLE_L[2:0]

AFE_INT_C_

BUF_L

CH1_AMP_DISABLE_L[2:0]

0x0003

[7:0]

ADC_COUNT_L[1:0]

Reserved

INTEG_WIDTH_L[4:0]

0x026B

0x026C

0x026D

0x026E

0x026F

INTEG_OS_L [15:8]

[7:0]

INTEG_ OFFSET_L[12:8]

0x0214

0x0001

0x0000

R/W

INTEG_OFFSET_L[7:0]

MOD_WIDTH_L[7:0]

MOD_OFFSET_L[7:0]

MOD_

PULSE_L

[15:8]

[7:0]

PATTERN_L [15:8]

[7:0]

LED_DISABLE_L[3:0]

SUBTRACT_L[3:0]

MOD_DISABLE_L[3:0]

REVERSE_INTEG_L[3:0]

ADC_OFF1_L [15:8]

[7:0]

Reserved

CH1_ADC_ADJUST_L[13:8]

CH1_ADC_ADJUST_L[7:0]

CH2_ADC_ADJUST_L[13:8]

ADC_OFF2_L [15:8]

ZERO_

Reserved

ADJUST_L

[7:0]

CH2_ADC_ADJUST_L[7:0]

DARK_SHIFT_L[4:0]

0x0270

0x0271

0x0272

0x0273

DATA_

FORMAT_L

[15:8]

[7:0]

DARK_SIZE_L[2:0]

0x0003

0x0000

0x0026

R/W

SIGNAL_SHIFT_L[4:0]

SIGNAL_SIZE_L[2:0]

LIT_DATA_

FORMAT_L

[15:8]

[7:0]

Reserved

LIT_SHIFT_L[4:0]

Reserved

LIT_SIZE_L[2:0]

DECIMATE_FACTOR_L[6:4]

DECIMATE_TYPE_L[3:0]

DECIMATE_L [15:8]

[7:0]

DECIMATE_FACTOR_L[3:0]

DIGINT_LIT_L [15:8]

Reserved

LIT_

OFFSET_

L[8]

[7:0]

LIT_OFFSET_L[7:0]

0x0274

0x0275

DIGINT_

DARK_L

[15:8]

[7:0]

DARK2_OFFSET_L[8:1]

0x2306

0x0000

R/W

DARK2_

OFFSET_L[0]

DARK1_OFFSET_L[6:0]

THRESH_

CFG_L

[15:8]

[7:0]

Reserved

THRESH1_TYPE_L[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_L[1:0]

CHAN_L DIR_L

THRESH0_SHIFT_L[4:0]

THRESH0_VALUE_L[7:0]

THRESH1_SHIFT_L[4:0]

THRESH1_VALUE_L[7:0]

THRESH1_

CHAN_L

THRESH1_

DIR_L

0x0276

0x0277

THRESH0_L [15:8]

Reserved

0x0000

R/W

[7:0]

THRESH1_L [15:8]

[7:0]

Reserved

Rev. 0 | Page 69 of 101

ADPD4100/ADPD4101

Data Sheet

REGISTER DETAILS

GLOBAL CONFIGURATION REGISTERS

Table 30. Global Configuration Register Details

Addr

Name

Bits

Bit Name

Description

Reset Access

0x000D TS_FREQ

[15:0] TIMESLOT_PERIOD_L Lower 16 bits of time slot period in low frequency oscillator cycles. 0x2710 R/W

The time slot rate is (low frequency oscillator frequency) ÷

(TIMESLOT_PERIOD_x). The default value operates at 100 Hz when

using the 1 MHz low frequency oscillator.

0x000E TS_FREQH

[15:7] Reserved

Reserved.

0x0

R

[6:0]

TIMESLOT_PERIOD_H Upper seven bits of time slot period in low frequency oscillator

cycles. The time slot rate is (low frequency oscillator frequency) ÷

(TIMESLOT_PERIOD_x). The default value operates at 100 Hz when

using the 1 MHz low frequency oscillator.

R/W

0x000F SYS_CTL

15

SW_RESET

Software reset. Write 1 to this bit to assert a software reset, which 0x0

stops all AFE operations and resets the device to its default values.

Software reset does not reset the SPI or I²C port.

R/W

[14:10] Reserved

[9:8] ALT_CLOCKS

Reserved.

External clock select.

0x0

R

R/W

00: use internal low frequency oscillator and high frequency

oscillator.

01: use external low frequency oscillator.

02: use external high frequency oscillator and internal low

frequency oscillator.

03: use external high frequency oscillator and generate low

frequency oscillator from high frequency oscillator.

[7:6]

ALT_CLK_GPIO

Alternate clock GPIO select.

00: use GPIO0 for alternate clock.

01: use GPIO1 for alternate clock.

10: use GPIO2 for alternate clock.

11: use GPIO3 for alternate clock.

Write 0x0.

0x0

R/W

[5:3]

2

Reserved

0x0

R/W

LFOSC_SEL

Selects low frequency oscillator. This bit selects between the

32 kHz and 1 MHz low speed oscillator.

0: use the 32 kHz oscillator as the low frequency clock.

1: use the 1 MHz oscillator as the low frequency clock.

1

0

OSC_1M_EN

OSC_32K_EN

Enable 1 MHz low frequency oscillator. This bit turns on the 1 MHz 0x0

low frequency oscillator, which must be left running during all

operations while using this oscillator.

Enable 32 kHz low frequency oscillator. This bit turns on the 32 kHz 0x0

low frequency oscillator, which must be left running during all

operations while using this oscillator.

R/W

0x0010 OPMODE

[15:12] Reserved

[11:8] TIMESLOT_EN

Reserved.

Time slot enable control.

0x0

R

R/W

0000: Time Slot Sequence A only.

0001: Time Slot Sequence AB.

0010: Time Slot Sequence ABC.

0011: Time Slot Sequence ABCD.

0100: Time Slot Sequence ABCDE.

0101: Time Slot Sequence ABCDEF.

0110: Time Slot Sequence ABCDEFG.

0111: Time Slot Sequence ABCDEFGH.

1000: Time Slot Sequence ABCDEFGHI.

1001: Time Slot Sequence ABCDEFGHIJ.

1010: Time Slot Sequence ABCDEFGHIJK.

1011: Time Slot Sequence ABCDEFGHIJKL.

Rev. 0 | Page 70 of 101

Data Sheet

ADPD4100/ADPD4101

Addr

Name

Bits

[7:1]

0

Bit Name

Reserved

OP_MODE

Description

Reset Access

Reserved.

Operating mode selection.

0: standby.

0x0

R

R/W

1: go mode. Operate selected time slots.

Input pair sleep state for IN7 and IN8 inputs.

0x0: both inputs float.

0x1: floating short of IN7 to IN8. Only if PAIR78 is set to 1.

0x2: IN7 and IN8 connected to VC1. Also shorted together if PAIR78

is set to 1.

0x0020 INPUT_SLEEP [15:12] INP_SLEEP_78

0x0

R/W

0x3: IN7 and IN8 connected to VC2. Also shorted together if PAIR78

is set to 1.

0x4: IN7 connected to VC1. IN8 floating.

0x5: IN7 connected to VC1. IN8 connected to VC2.

0x6: IN7 connected to VC2. IN8 floating.

0x7: IN7 connected to VC2. IN8 connected to VC1.

0x8: IN7 floating. IN8 connected to VC1.

0x9: IN7 floating. IN8 connected to VC2.

Input pair sleep state for IN5 and IN6 inputs.

0x0: both inputs float.

0x1: floating short of IN5 to IN6. Only if PAIR56 is set to 1.

0x2: IN5 and IN6 connected to VC1. Also shorted together if PAIR56

is set to 1.

0x3: IN5 and IN6 connected to VC2. Also shorted together if PAIR56

is set to 1.

0x4: IN5 connected to VC1. IN6 floating.

0x5: IN5 connected to VC1. IN6 connected to VC2.

0x6: IN5 connected to VC2. IN6 floating.

0x7: IN5 connected to VC2. IN6 connected to VC1.

0x8: IN5 floating. IN6 connected to VC1.

0x9: IN5 floating. IN6 connected to VC2.

Input pair sleep state for IN3 and IN4 inputs.

0x0: both inputs float.

0x1: floating short of IN3 to IN4. Only if PAIR34 is set to 1.

0x2: IN3 and IN4 connected to VC1. Also shorted together if PAIR34

is set to 1.

0x3: IN3 and IN4 connected to VC2. Also shorted together if PAIR34

is set to 1.

[11:8] INP_SLEEP_56

[7:4]

INP_SLEEP_34

0x4: IN3 connected to VC1. IN4 floating.

0x5: IN3 connected to VC1. IN4 connected to VC2.

0x6: IN3 connected to VC2. IN4 floating.

0x7: IN3 connected to VC2. IN4 connected to VC1.

0x8: IN3 floating. IN4 connected to VC1.

0x9: IN3 floating. IN4 connected to VC2.

Input pair sleep state for IN1 and IN2 inputs.

0x0: both inputs float.

[3:0]

INP_SLEEP_12

0x1: floating short of IN1 to IN2. Only if PAIR12 is set to 1.

0x2: IN1 and IN2 connected to VC1. Also shorted together if PAIR12

is set to 1.

0x3: IN1 and IN2 connected to VC2. Also shorted together if PAIR12

is set to 1.

0x4: IN1 connected to VC1. IN2 floating.

0x5: IN1 connected to VC1. IN2 connected to VC2.

0x6: IN1 connected to VC2. IN2 floating.

Rev. 0 | Page 71 of 101

ADPD4100/ADPD4101

Data Sheet

Addr

Name

Bits

Bit Name

Description

Reset Access

0x7: IN1 connected to VC2. IN2 connected to VC1.

0x8: IN1 floating. IN2 connected to VC1.

0x9: IN1 floating. IN2 connected to VC2.

Reserved.

0x0021 INPUT_CFG [15:8] Reserved

0x0

R

R/W

[7:6]

VC2_SLEEP

VC2 sleep state.

0: VC2 set to AVDD during sleep.

1: VC2 set to ground during sleep.

10: VC2 floating during sleep.

[5:4]

VC1_SLEEP

VC1 sleep state.

0x0

R/W

0: VC1 set to AVDD during sleep.

1: VC1 set to ground during sleep.

10: VC1 floating during sleep.

3

2

1

0

PAIR78

PAIR56

PAIR34

PAIR12

Input pair configuration.

0x0

R/W

0: IN7 and IN8 configured as two single-ended inputs.

1: IN7 and IN8 configured as a differential pair.

Input pair configuration.

0: IN5 and IN6 configured as two single-ended inputs.

1: IN5 and IN6 configured as a differential pair.

Input pair configuration.

0: IN3 and IN4 configured as two single-ended inputs.

1: IN3 and IN4 configured as a differential pair.

Input pair configuration.

0: IN1 and IN2 configured as two single-ended inputs.

1: IN1 and IN2 configured as a differential pair.

INTERRUPT STATUS AND CONTROL REGISTERS

Table 31. Interrupt Status and Control Register Details

Addr

Name

Bits

Bit Name

Description

Reset Access¹

0x0000 FIFO_STATUS

15

CLEAR_FIFO

Clear FIFO. Write a 1 to empty the FIFO while the FIFO is 0x0

not being accessed. This resets FIFO_BYTE_COUNT and

clears the INT_FIFO_OFLOW, INT_FIFO_UFLOW, and

INT_FIFO_TH status bits.

FIFO underflow error. This bit is set when the FIFO is read 0x0

while empty. Write 1 to this bit to clear the interrupt. This

bit is also cleared if the FIFO is cleared using the

CLEAR_FIFO bit.

R/W1C

14

13

INT_FIFO_UFLOW

INT_FIFO_OFLOW

FIFO overflow error. This bit is set when data was not

written to the FIFO due to lack of space. Write 1 to this bit

to clear the interrupt. This bit is also cleared if the FIFO is

cleared with the CLEAR_FIFO bit.

0x0

[12:11] Reserved

Reserved.

0x0

R

[10:0] FIFO_BYTE_COUNT

This field indicates the number of bytes in the FIFO.

R

0x0001 INT_STATUS_DATA

15

INT_FIFO_TH

FIFO_TH interrupt status. This bit is set during a FIFO

write when the number of bytes in the FIFO exceeds the

FIFO_TH register value. Write 1 to this bit to clear this

interrupt. This bit can also be automatically cleared when

the FIFO_DATA register is read if the INT_ACLEAR_FIFO

bit is set.

R/W1C

[14:12] Reserved

11 INT_DATA_L

Reserved.

0x0

R

Time Slot L data register interrupt status. This bit is set

every time the Time Slot L data registers are updated.

Write 1 to this bit to clear the interrupt. The interrupt is

cleared automatically when the Time Slot L data registers

are read if the INT_ACLEAR_DATA_L bit is set.

R/W1C

Rev. 0 | Page 72 of 101

Data Sheet

ADPD4100/ADPD4101

Addr

Name

Bits

Bit Name

Description

Reset Access¹

10

INT_DATA_K

Time Slot K data register interrupt status. This bit is set

every time the Time Slot K data registers get updated.

Write 1 to this bit to clear the interrupt. The interrupt is

cleared automatically when the Time Slot K data registers

are read if the INT_ACLEAR_DATA_K bit is set.

Time Slot J data register interrupt status. This bit is set

every time the Time Slot J data registers are updated.

Write 1 to this bit to clear the interrupt. The interrupt is

cleared automatically when the Time Slot J data registers

are read if the INT_ACLEAR_DATA_J bit is set.

Time Slot I data register interrupt status. This bit is set

every time the Time Slot I data registers are updated.

Write 1 to this bit to clear the interrupt. The interrupt is

cleared automatically when the Time Slot I data registers

are read if the INT_ACLEAR_DATA_I bit is set.

Time Slot H data register interrupt status. This bit is set

every time the Time Slot H data registers are updated.

Write 1 to this bit to clear the interrupt. The interrupt is

cleared automatically when the Time Slot H data registers

are read if the INT_ACLEAR_DATA_H bit is set.

Time Slot G data register interrupt status. This bit is set

every time the Time Slot G data registers are updated.

Write 1 to this bit to clear the interrupt. The interrupt is

cleared automatically when the Time Slot G data registers

are read if the INT_ACLEAR_DATA_G bit is set.

Time Slot F data register interrupt status. This bit is set

every time the Time Slot F data registers are updated.

Write 1 to this bit to clear the interrupt. The interrupt is

cleared automatically when the Time Slot F data registers

are read if the INT_ACLEAR_DATA_F bit is set.

Time Slot E data register interrupt status. This bit is set

every time the Time Slot E data registers are updated.

Write 1 to this bit to clear the interrupt. The interrupt is

cleared automatically when the Time Slot E data registers

are read if the INT_ACLEAR_DATA_E bit is set.

0x0

R/W1C

9

8

7

6

5

4

3

2

1

0

INT_DATA_J

INT_DATA_I

INT_DATA_H

INT_DATA_G

INT_DATA_F

INT_DATA_E

INT_DATA_D

INT_DATA_C

INT_DATA_B

INT_DATA_A

Time Slot D data register interrupt status. This bit is set

every time the Time Slot D data registers are updated.

Write 1 to this bit to clear the interrupt. The interrupt is

cleared automatically when the Time Slot D data registers

are read if the INT_ACLEAR_DATA_D bit is set.

Time Slot C data register interrupt status. This bit is set

every time the Time Slot C data registers are updated.

Write 1 to this bit to clear the interrupt. The interrupt is

cleared automatically when the Time Slot C data registers

are read if the INT_ACLEAR_DATA_C bit is set.

Time Slot B data register interrupt status. This bit is set

every time the Time Slot B data registers are updated.

Write 1 to this bit to clear the interrupt. The interrupt is

cleared automatically when the Time Slot B data registers

are read if the INT_ACLEAR_DATA_B bit is set.

Time Slot A data register interrupt status. This bit is set

every time the Time Slot A data registers are updated.

Write 1 to this bit to clear the interrupt. The interrupt is

cleared automatically when the Time Slot A data registers

are read if the INT_ACLEAR_DATA_A bit is set.

Rev. 0 | Page 73 of 101

ADPD4100/ADPD4101

Data Sheet

Addr

Name

Bits

Bit Name

Description

Reset Access¹

0x0002 INT_STATUS_LEV0

0x0003 INT_STATUS_LEV1

0x0004 INT_STATUS_TC1

[15:12] Reserved

Reserved.

0x0

R

11

10

9

INT_LEV0_L

INT_LEV0_K

INT_LEV0_J

INT_LEV0_I

INT_LEV0_H

INT_LEV0_G

INT_LEV0_F

INT_LEV0_E

INT_LEV0_D

INT_LEV0_C

INT_LEV0_B

INT_LEV0_A

Time Slot L Level 0 interrupt status. This bit is set during a 0x0

data register update when the configured criteria is met.

Time Slot K Level 0 interrupt status. This bit is set during a 0x0

data register update when the configured criteria is met.

Time Slot J Level 0 interrupt status. This bit is set during a 0x0

data register update when the configured criteria is met.

Time Slot I Level 0 interrupt status. This bit is set during a 0x0

data register update when the configured criteria is met.

Time Slot H Level 0 interrupt status. This bit is set during 0x0

a data register update when the configured criteria is met.

Time Slot G Level 0 interrupt status. This bit is set during a 0x0

data register update when the configured criteria is met.

Time Slot F Level 0 interrupt status. This bit is set during a 0x0

data register update when the configured criteria is met.

Time Slot E Level 0 interrupt status. This bit is set during a 0x0

data register update when the configured criteria is met.

Time Slot D Level 0 interrupt status. This bit is set during a 0x0

data register update when the configured criteria is met.

Time Slot C Level 0 interrupt status. This bit is set during a 0x0

data register update when the configured criteria is met.

Time Slot B Level 0 interrupt status. This bit is set during a 0x0

data register update when the configured criteria is met.

Time Slot A Level 0 interrupt status. This bit is set during a 0x0

data register update when the configured criteria is met.

R/W1C

8

7

6

5

4

3

2

1

0

[15:12] Reserved

Reserved.

0x0

R

11

10

9

INT_LEV1_L

INT_LEV1_K

INT_LEV1_J

INT_LEV1_I

INT_LEV1_H

INT_LEV1_G

INT_LEV1_F

INT_LEV1_E

INT_LEV1_D

INT_LEV1_C

INT_LEV1_B

INT_LEV1_A

Time Slot L Level 1 interrupt status. This bit is set during a 0x0

data register update when the configured criteria is met.

Time Slot K Level 1 interrupt status. This bit is set during a 0x0

data register update when the configured criteria is met.

Time Slot J Level 1 interrupt status. This bit is set during a 0x0

data register update when the configured criteria is met.

Time Slot I Level 1 interrupt status. This bit is set during a 0x0

data register update when the configured criteria is met.

Time Slot H Level 1 interrupt status. This bit is set during 0x0

a data register update when the configured criteria is met.

Time Slot G Level 1 interrupt status. This bit is set during a 0x0

data register update when the configured criteria is met.

Time Slot F Level 1 interrupt status. This bit is set during a 0x0

data register update when the configured criteria is met.

Time Slot E Level 1 interrupt status. This bit is set during a 0x0

data register update when the configured criteria is met.

Time Slot D Level 1 interrupt status. This bit is set during a 0x0

data register update when the configured criteria is met.

Time Slot C Level 1 interrupt status. This bit is set during a 0x0

data register update when the configured criteria is met.

Time Slot B Level 1 interrupt status. This bit is set during a 0x0

data register update when the configured criteria is met.

Time Slot A Level 1 interrupt status. This bit is set during a 0x0

data register update when the configured criteria is met.

R/W1C

8

7

6

5

4

3

2

1

0

[15:12] Reserved

Reserved.

0x0

R

11

INT_TCLN1_L

Time Slot L Channel 1 ceiling detection interrupt status. 0x0

This bit is set during a data register update when

R/W1C

Channel 1 exceeds the threshold level during Time Slot L.

10

INT_TCLN1_K

Time Slot K Channel 1 ceiling detection interrupt status. 0x0

This bit is set during a data register update when

R/W1C

Channel 1 exceeds the threshold level during Time Slot K.

Rev. 0 | Page 74 of 101

Data Sheet

ADPD4100/ADPD4101

Addr

Name

Bits

Bit Name

Description

Reset Access¹

9

INT_TCLN1_J

Time Slot J Channel 1 ceiling detection interrupt status.

This bit is set during a data register update when

Channel 1 exceeds the threshold level during Time Slot J.

Time Slot I Channel 1 ceiling detection interrupt status.

This bit is set during a data register update when

Channel 1 exceeds the threshold level during Time Slot I.

Time Slot H Channel 1 ceiling detection interrupt status. 0x0

This bit is set during a data register update when

Channel 1 exceeds the threshold level during Time Slot H.

Time Slot G Channel 1 ceiling detection interrupt status. 0x0

This bit is set during a data register update when

Channel 1 exceeds the threshold level during Time Slot G.

Time Slot F Channel 1 ceiling detection interrupt status. 0x0

This bit is set during a data register update when

Channel 1 exceeds the threshold level during Time Slot F.

Time Slot E Channel 1 ceiling detection interrupt status. 0x0

This bit is set during a data register update when

Channel 1 exceeds the threshold level during Time Slot E.

Time Slot D Channel 1 ceiling detection interrupt status. 0x0

This bit is set during a data register update when

Channel 1 exceeds the threshold level during Time Slot D.

Time Slot C Channel 1 ceiling detection interrupt status. 0x0

This bit is set during a data register update when

Channel 1 exceeds the threshold level during Time Slot C.

Time Slot B Channel 1 ceiling detection interrupt status. 0x0

This bit is set during a data register update when

0x0

R/W1C

8

7

6

5

4

3

2

1

0

INT_TCLN1_I

INT_TCLN1_H

INT_TCLN1_G

INT_TCLN1_F

INT_TCLN1_E

INT_TCLN1_D

INT_TCLN1_C

INT_TCLN1_B

INT_TCLN1_A

0x0

Channel 1 exceeds the threshold level during Time Slot B.

Time Slot A Channel 1 ceiling detection interrupt status. 0x0

This bit is set during a data register update when

Channel 1 exceeds the threshold level during Time Slot A.

0x0005 INT_STATUS_TC2

[15:12] Reserved

Reserved.

0x0

R

11

10

9

INT_TCLN2_L

Time Slot L Channel 2 ceiling detection interrupt status. 0x0

This bit is set during a data register update when

Channel 2 exceeds the threshold level during Time Slot L.

Time Slot K Channel 2 ceiling detection interrupt status. 0x0

This bit is set during a data register update when

Channel 2 exceeds the threshold level during Time Slot K.

R/W1C

INT_TCLN2_K

INT_TCLN2_J

INT_TCLN2_I

INT_TCLN2_H

INT_TCLN2_G

INT_TCLN2_F

INT_TCLN2_E

INT_TCLN2_D

R/W1C

Time Slot J Channel 2 ceiling detection interrupt status.

This bit is set during a data register update when

Channel 2 exceeds the threshold level during Time Slot J.

Time Slot I Channel 2 ceiling detection interrupt status.

This bit is set during a data register update when

Channel 2 exceeds the threshold level during Time Slot I.

0x0

8

7

Time Slot H Channel 2 ceiling detection interrupt status. 0x0

This bit is set during a data register update when

Channel 2 exceeds the threshold level during Time Slot H.

Time Slot G Channel 2 ceiling detection interrupt status. 0x0

This bit is set during a data register update when

Channel 2 exceeds the threshold level during Time Slot G.

6

5

Time Slot F Channel 2 ceiling detection interrupt status. 0x0

This bit is set during a data register update when

Channel 2 exceeds the threshold level during Time Slot F.

4

Time Slot E Channel 2 ceiling detection interrupt status. 0x0

This bit is set during a data register update when

Channel 2 exceeds the threshold level during Time Slot E.

Time Slot D Channel 2 ceiling detection interrupt status. 0x0

This bit is set during a data register update when

3

Channel 2 exceeds the threshold level during Time Slot D.

Rev. 0 | Page 75 of 101

ADPD4100/ADPD4101

Data Sheet

Addr

Name

Bits

Bit Name

Description

Reset Access¹

2

INT_TCLN2_C

Time Slot C Channel 2 ceiling detection interrupt status. 0x0

This bit is set during a data register update when

Channel 2 exceeds the threshold level during Time Slot C.

Time Slot B Channel 2 ceiling detection interrupt status. 0x0

This bit is set during a data register update when

Channel 2 exceeds the threshold level during Time Slot B.

Time Slot A Channel 2 ceiling detection interrupt status. 0x0

This bit is set during a data register update when

Channel 2 exceeds the threshold level during Time Slot A.

FIFO threshold interrupt autoclear enable. Set this bit to 0x1

enable automatic clearing of the FIFO_TH interrupt each

time the FIFO is read.

R/W1C

R/W

1

INT_TCLN2_B

0

INT_TCLN2_A

0x0007 INT_ACLEAR

15

INT_ACLEAR_FIFO

[14:12] Reserved

Reserved.

0x0

0x1

R

11

10

9

INT_ACLEAR_DATA_L

Time Slot L interrupt autoclear enable. Set this bit to

enable automatic clearing of the INT_DATA_L interrupt

each time the Time Slot L data registers are read.

R/W

INT_ACLEAR_DATA_K Time Slot K interrupt autoclear enable. Set this bit to

enable automatic clearing of the INT_DATA_K interrupt

each time the Time Slot K data registers are read.

0x1

R/W

INT_ACLEAR_DATA_J

Time Slot J interrupt autoclear enable. Set this bit to

enable automatic clearing of the INT_DATA_J interrupt

each time the Time Slot J data registers are read.

Time Slot I interrupt autoclear enable. Set this bit to

enable automatic clearing of the INT_DATA_I interrupt

each time the Time Slot I data registers are read.

8

INT_ACLEAR_DATA_I

7

INT_ACLEAR_DATA_H Time Slot H interrupt autoclear enable. Set this bit to

enable automatic clearing of the INT_DATA_H interrupt

each time the Time Slot H data registers are read.

6

5

4

3

2

1

0

INT_ACLEAR_DATA_G Time Slot G interrupt autoclear enable. Set this bit to

enable automatic clearing of the INT_DATA_G interrupt

each time the Time Slot G data registers are read.

0x1

R/W

INT_ACLEAR_DATA_F

Time Slot F interrupt autoclear enable. Set this bit to

enable automatic clearing of the INT_DATA_F interrupt

each time the Time Slot F data registers are read.

INT_ACLEAR_DATA_E

Time Slot E interrupt autoclear enable. Set this bit to

enable automatic clearing of the INT_DATA_E interrupt

each time the Time Slot E data register is read.

INT_ACLEAR_DATA_D Time Slot D interrupt autoclear enable. Set this bit to

enable automatic clearing of the INT_DATA_D interrupt

each time the Time Slot D data registers are read.

INT_ACLEAR_DATA_C Time Slot C interrupt autoclear enable. Set this bit to

enable automatic clearing of the INT_DATA_C interrupt

each time the Time Slot C data registers are read.

INT_ACLEAR_DATA_B Time Slot B interrupt autoclear enable. Set this bit to

enable automatic clearing of the INT_DATA_B interrupt

each time the Time Slot B data registers are read.

INT_ACLEAR_DATA_A Time Slot A interrupt autoclear enable. Set this bit to

enable automatic clearing of the INT_DATA_A interrupt

each time the Time Slot A data registers are read.

Rev. 0 | Page 76 of 101

Data Sheet

ADPD4100/ADPD4101

Addr

Name

Bits

Bit Name

Description

Reset Access¹

0x0014 INT_ENABLE_XD

15

INTX_EN_FIFO_TH

INT_FIFO_TH interrupt enable. Write a 1 to this bit to

enable drive of the FIFO threshold status on Interrupt X.

0x0

R/W

14

13

INTX_EN_FIFO_UFLOW INT_FIFO_UFLOW interrupt enable for Interrupt X. Write a 0x0

1 to this bit to enable drive of the FIFO underflow status

on Interrupt X.

INTX_EN_FIFO_OFLOW INT_FIFO_OFLOW interrupt enable for Interrupt X. Write a 0x0

1 to this bit to enable drive of the FIFO overflow status on

Interrupt X.

R/W

12

11

Reserved

Reserved.

0x0

R

INTX_EN_DATA_L

INT_DATA_L interrupt enable. Write a 1 to this bit to

enable drive of INT_DATA_L status on Interrupt X.

R/W

10

9

INTX_EN_DATA_K

INTX_EN_DATA_J

INTX_EN_DATA_I

INTX_EN_DATA_H

INTX_EN_DATA_G

INTX_EN_DATA_F

INTX_EN_DATA_E

INTX_EN_DATA_D

INTX_EN_DATA_C

INTX_EN_DATA_B

INTX_EN_DATA_A

INTY_EN_FIFO_TH

INT_DATA_K interrupt enable. Write a 1 to this bit to

enable drive of INT_DATA_K status on Interrupt X.

INT_DATA_J interrupt enable. Write a 1 to this bit to

enable drive of INT_DATA_J status on Interrupt X.

INT_DATA_I interrupt enable. Write a 1 to this bit to

enable drive of INT_DATA_I status on Interrupt X.

INT_DATA_H interrupt enable. Write a 1 to this bit to

enable drive of INT_DATA_H status on Interrupt X.

INT_DATA_G interrupt enable. Write a 1 to this bit to

enable drive of INT_DATA_G status on Interrupt X.

INT_DATA_F interrupt enable. Write a 1 to this bit to

enable drive of INT_DATA_F status on Interrupt X.

INT_DATA_E interrupt enable. Write a 1 to this bit to

enable drive of INT_DATA_E status on Interrupt X.

0x0

R/W

8

7

6

5

4

3

INT_DATA_D interrupt enable. Write a 1 to this bit to

enable drive of INT_DATA_D status on Interrupt X.

INT_DATA_C interrupt enable. Write a 1 to this bit to

enable drive of INT_DATA_C status on Interrupt X.

INT_DATA_B interrupt enable. Write a 1 to this bit to

enable drive of INT_DATA_B status on Interrupt X.

INT_DATA_A interrupt enable. Write a 1 to this bit to

enable drive of INT_DATA_A status on Interrupt X.

2

1

0

0x0015 INT_ENABLE_YD

15

14

INT_FIFO_TH interrupt enable. Write a 1 to this bit to

enable drive of the FIFO threshold status on Interrupt Y.

INTY_EN_FIFO_UFLOW INT_FIFO_UFLOW interrupt enable for Interrupt Y. Write a 0x0

1 to this bit to enable drive of the FIFO underflow status

on Interrupt Y.

13

INTY_EN_FIFO_OFLOW INT_FIFO_OFLOW interrupt enable for Interrupt Y. Write a 0x0

1 to this bit to enable drive of the FIFO overflow status on

Interrupt Y.

R/W

12

11

Reserved

INTY_EN_DATA_L

Reserved.

0x0

R

R/W

INT_DATA_L interrupt enable. Write a 1 to this bit to

enable drive of INT_DATA_L status on Interrupt Y.

10

9

INTY_EN_DATA_K

INTY_EN_DATA_J

INTY_EN_DATA_I

INTY_EN_DATA_H

INTY_EN_DATA_G

INTY_EN_DATA_F

INTY_EN_DATA_E

INT_DATA_K interrupt enable. Write a 1 to this bit to

enable drive of INT_DATA_K status on Interrupt Y.

INT_DATA_J interrupt enable. Write a 1 to this bit to

enable drive of INT_DATA_J status on Interrupt Y.

INT_DATA_I interrupt enable. Write a 1 to this bit to

enable drive of INT_DATA_I status on Interrupt Y.

INT_DATA_H interrupt enable. Write a 1 to this bit to

enable drive of INT_DATA_H status on Interrupt Y.

INT_DATA_G interrupt enable. Write a 1 to this bit to

enable drive of INT_DATA_G status on Interrupt Y.

INT_DATA_F interrupt enable. Write a 1 to this bit to

enable drive of INT_DATA_F status on Interrupt Y.

INT_DATA_E interrupt enable. Write a 1 to this bit to

enable drive of INT_DATA_E status on Interrupt Y.

0x0

R/W

8

7

6

5

4

Rev. 0 | Page 77 of 101

ADPD4100/ADPD4101

Data Sheet

Addr

Name

Bits

Bit Name

Description

Reset Access¹

3

INTY_EN_DATA_D

INT_DATA_D interrupt enable. Write a 1 to this bit to

enable drive of INT_DATA_D status on Interrupt Y.

INT_DATA_C interrupt enable. Write a 1 to this bit to

enable drive of INT_DATA_C status on Interrupt Y.

INT_DATA_B interrupt enable. Write a 1 to this bit to

enable drive of INT_DATA_B status on Interrupt Y.

INT_DATA_A interrupt enable. Write a 1 to this bit to

enable drive of INT_DATA_A status on Interrupt Y.

0x0

R/W

2

1

0

INTY_EN_DATA_C

INTY_EN_DATA_B

INTY_EN_DATA_A

0x0016 INT_ENABLE_XL0

[15:12] Reserved

Reserved.

0x0

R

R/W

11

10

9

INTX_EN_LEV0_L

INT_LEV0_L interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV0_L status on Interrupt X.

INT_LEV0_K interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV0_K status on Interrupt X.

INT_LEV0_J interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV0_J status on Interrupt X.

INT_LEV0_I interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV0_I status on Interrupt X.

INT_LEV0_H interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV0_H status on Interrupt X.

INT_LEV0_G interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV0_G status on Interrupt X.

INT_LEV0_F interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV0_F status on Interrupt X.

INTX_EN_LEV0_K

INTX_EN_LEV0_J

INTX_EN_LEV0_I

INTX_EN_LEV0_H

INTX_EN_LEV0_G

INTX_EN_LEV0_F

INTX_EN_LEV0_E

INTX_EN_LEV0_D

INTX_EN_LEV0_C

INTX_EN_LEV0_B

INTX_EN_LEV0_A

0x0

R/W

8

7

6

5

4

INT_LEV0_E interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV0_E status on Interrupt X.

3

INT_LEV0_D interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV0_D status on Interrupt X.

INT_LEV0_C interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV0_C status on Interrupt X.

INT_LEV0_B interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV0_B status on Interrupt X.

INT_LEV0_A interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV0_A status on Interrupt X.

2

1

0

0x0017 INT_ENABLE_XL1

[15:12] Reserved

Reserved.

0x0

R

11

10

9

INTX_EN_LEV1_L

INT_LEV1_L interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV1_L status on Interrupt X.

R/W

INTX_EN_LEV1_K

INTX_EN_LEV1_J

INTX_EN_LEV1_I

INTX_EN_LEV1_H

INTX_EN_LEV1_G

INTX_EN_LEV1_F

INTX_EN_LEV1_E

INTX_EN_LEV1_D

INTX_EN_LEV1_C

INT_LEV1_K interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV1_K status on Interrupt X.

0x0

R/W

INT_LEV1_J interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV1_J status on Interrupt X.

8

INT_LEV1_I interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV1_I status on Interrupt X.

7

INT_LEV1_H interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV1_H status on Interrupt X.

6

INT_LEV1_G interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV1_G status on Interrupt X.

5

INT_LEV1_F interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV1_F status on Interrupt X.

4

INT_LEV1_E interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV1_E status on Interrupt X.

3

INT_LEV1_D interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV1_D status on Interrupt X.

2

INT_LEV1_C interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV1_C status on Interrupt X.

Rev. 0 | Page 78 of 101

Data Sheet

ADPD4100/ADPD4101

Addr

Name

Bits

Bit Name

Description

Reset Access¹

1

INTX_EN_LEV1_B

INT_LEV1_B interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV1_B status on Interrupt X.

0x0

R/W

0

INTX_EN_LEV1_A

INT_LEV1_A interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV1_A status on Interrupt X.

0x0

R/W

0x0018 INT_ENABLE_XT1

[15:12] Reserved

Reserved.

0x0

R

R/W

11

10

9

INTX_EN_TCLN1_L

INT_TCLN1_L interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN1_L status on Interrupt X.

INT_TCLN1_K interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN1_K status on Interrupt X.

INT_TCLN1_J interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN1_J status on Interrupt X.

INTX_EN_TCLN1_K

INTX_EN_TCLN1_J

INTX_EN_TCLN1_I

INTX_EN_TCLN1_H

INTX_EN_TCLN1_G

INTX_EN_TCLN1_F

INTX_EN_TCLN1_E

INTX_EN_TCLN1_D

INTX_EN_TCLN1_C

INTX_EN_TCLN1_B

INTX_EN_TCLN1_A

0x0

R/W

8

INT_TCLN1_I interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN1_I status on Interrupt X.

INT_TCLN1_H interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN1_H status on Interrupt X.

INT_TCLN1_G interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN1_G status on Interrupt X.

INT_TCLN1_F interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN1_F status on Interrupt X.

INT_TCLN1_E interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN1_E status on Interrupt X.

INT_TCLN1_D interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN1_D status on Interrupt X.

INT_TCLN1_C interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN1_C status on Interrupt X.

INT_TCLN1_B interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN1_B status on Interrupt X.

7

6

5

4

3

2

1

0

INT_TCLN1_A interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN1_A status on Interrupt X.

0x0019 INT_ENABLE_XT2

[15:12] Reserved

Reserved.

0x0

R

R/W

11

10

9

INTX_EN_TCLN2_L

INT_TCLN2_L interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN2_L status on Interrupt X.

INT_TCLN2_K interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN2_K status on Interrupt X.

INT_TCLN2_J interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN2_J status on Interrupt X.

INT_TCLN2_I interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN2_I status on Interrupt X.

INT_TCLN2_H interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN2_H status on Interrupt X.

INT_TCLN2_G interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN2_G status on Interrupt X.

INT_TCLN2_F interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN2_F status on Interrupt X.

INT_TCLN2_E interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN2_E status on Interrupt X.

INT_TCLN2_D interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN2_D status on Interrupt X.

INT_TCLN2_C interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN2_C status on Interrupt X.

INT_TCLN2_B interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN2_B status on Interrupt X.

INT_TCLN2_A interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN2_A status on Interrupt X.

INTX_EN_TCLN2_K

INTX_EN_TCLN2_J

INTX_EN_TCLN2_I

INTX_EN_TCLN2_H

INTX_EN_TCLN2_G

INTX_EN_TCLN2_F

INTX_EN_TCLN2_E

INTX_EN_TCLN2_D

INTX_EN_TCLN2_C

INTX_EN_TCLN2_B

INTX_EN_TCLN2_A

0x0

R/W

8

7

6

5

4

3

2

1

0

Rev. 0 | Page 79 of 101

ADPD4100/ADPD4101

Data Sheet

Addr

Name

Bits

Bit Name

Description

Reset Access¹

0x001A INT_ENABLE_YL0

[15:12] Reserved

Reserved.

0x0

R

R/W

11

10

9

INTY_EN_LEV0_L

INT_LEV0_L interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV0_L status on Interrupt Y.

INT_LEV0_K interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV0_K status on Interrupt Y.

INT_LEV0_J interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV0_J status on Interrupt Y.

INT_LEV0_I interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV0_I status on Interrupt Y.

INTY_EN_LEV0_K

INTY_EN_LEV0_J

INTY_EN_LEV0_I

INTY_EN_LEV0_H

INTY_EN_LEV0_G

INTY_EN_LEV0_F

INTY_EN_LEV0_E

INTY_EN_LEV0_D

INTY_EN_LEV0_C

INTY_EN_LEV0_B

INTY_EN_LEV0_A

0x0

R/W

8

7

INT_LEV0_H interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV0_H status on Interrupt Y.

6

INT_LEV0_G interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV0_G status on Interrupt Y.

INT_LEV0_F interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV0_F status on Interrupt Y.

INT_LEV0_E interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV0_E status on Interrupt Y.

INT_LEV0_D interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV0_D status on Interrupt Y.

5

4

3

2

INT_LEV0_C interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV0_C status on Interrupt Y.

INT_LEV0_B interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV0_B status on Interrupt Y.

INT_LEV0_A interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV0_A status on Interrupt Y.

1

0

0x001B INT_ENABLE_YL1

[15:12] Reserved

Reserved.

0x0

R

R/W

11

10

9

INTY_EN_LEV1_L

INT_LEV1_L interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV1_L status on Interrupt Y.

INT_LEV1_K interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV1_K status on Interrupt Y.

INT_LEV1_J interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV1_J status on Interrupt Y.

INT_LEV1_I interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV1_I status on Interrupt Y.

INT_LEV1_H interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV1_H status on Interrupt Y.

INT_LEV1_G interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV1_G status on Interrupt Y.

INT_LEV1_F interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV1_F status on Interrupt Y.

INT_LEV1_E interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV1_E status on Interrupt Y.

INT_LEV1_D interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV1_D status on Interrupt Y.

INT_LEV1_C interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV1_C status on Interrupt Y.

INT_LEV1_B interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV1_B status on Interrupt Y.

INT_LEV1_A interrupt enable. Write a 1 to this bit to

enable drive of INT_LEV1_A status on Interrupt Y.

INTY_EN_LEV1_K

INTY_EN_LEV1_J

INTY_EN_LEV1_I

INTY_EN_LEV1_H

INTY_EN_LEV1_G

INTY_EN_LEV1_F

INTY_EN_LEV1_E

INTY_EN_LEV1_D

INTY_EN_LEV1_C

INTY_EN_LEV1_B

INTY_EN_LEV1_A

0x0

R/W

8

7

6

5

4

3

2

1

0

Rev. 0 | Page 80 of 101

Data Sheet

ADPD4100/ADPD4101

Addr

Name

Bits

Bit Name

Description

Reset Access¹

0x001C INT_ENABLE_YT1

[15:12] Reserved

Reserved.

0x0

R

R/W

11

10

9

INTY_EN_TCLN1_L

INT_TCLN1_L interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN1_L status on Interrupt Y.

INT_TCLN1_K interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN1_K status on Interrupt Y.

INT_TCLN1_J interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN1_J status on Interrupt Y.

INT_TCLN1_I interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN1_I status on Interrupt Y.

INT_TCLN1_H interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN1_H status on Interrupt Y.

INT_TCLN1_G interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN1_G status on Interrupt Y.

INTY_EN_TCLN1_K

INTY_EN_TCLN1_J

INTY_EN_TCLN1_I

INTY_EN_TCLN1_H

INTY_EN_TCLN1_G

INTY_EN_TCLN1_F

INTY_EN_TCLN1_E

INTY_EN_TCLN1_D

INTY_EN_TCLN1_C

INTY_EN_TCLN1_B

INTY_EN_TCLN1_A

0x0

R/W

8

7

6

5

INT_TCLN1_F interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN1_F status on Interrupt Y.

INT_TCLN1_E interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN1_E status on Interrupt Y.

INT_TCLN1_D interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN1_D status on Interrupt Y.

INT_TCLN1_C interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN1_C status on Interrupt Y.

INT_TCLN1_B interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN1_B status on Interrupt Y.

INT_TCLN1_A interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN1_A status on Interrupt Y.

4

3

2

1

0

0x001D INT_ENABLE_YT2

[15:12] Reserved

Reserved.

0x0

R

11

10

9

INTY_EN_TCLN2_L

INT_TCLN2_L interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN2_L status on Interrupt Y.

INT_TCLN2_K interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN2_K status on Interrupt Y.

INT_TCLN2_J interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN2_J status on Interrupt Y.

INT_TCLN2_I interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN2_I status on Interrupt Y.

INT_TCLN2_H interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN2_H status on Interrupt Y.

INT_TCLN2_G interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN2_G status on Interrupt Y.

INT_TCLN2_F interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN2_F status on Interrupt Y.

INT_TCLN2_E interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN2_E status on Interrupt Y.

INT_TCLN2_D interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN2_D status on Interrupt Y.

INT_TCLN2_C interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN2_C status on Interrupt Y.

INT_TCLN2_B interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN2_B status on Interrupt Y.

INT_TCLN2_A interrupt enable. Write a 1 to this bit to

enable drive of INT_TCLN2_A status on Interrupt .

R/W

INTY_EN_TCLN2_K

INTY_EN_TCLN2_J

INTY_EN_TCLN2_I

INTY_EN_TCLN2_H

INTY_EN_TCLN2_G

INTY_EN_TCLN2_F

INTY_EN_TCLN2_E

INTY_EN_TCLN2_D

INTY_EN_TCLN2_C

INTY_EN_TCLN2_B

INTY_EN_TCLN2_A

0x0

R/W

8

7

6

5

4

3

2

1

0

Rev. 0 | Page 81 of 101

ADPD4100/ADPD4101

Data Sheet

Addr

0x001E FIFO_STATUS_BYTES [15:9] Reserved

ENA_STAT_TCX

Name

Bits

Bit Name

Description

Reserved.

Reset Access¹

0x0

R

8

7

6

5

4

3

Enable Channel 1 and Channel 2 TIA ceiling detection

interrupt status byte for Time Slot I through Time Slot L.

This byte contains the interrupt status for the Channel 1

and Channel 2 interrupts for Time Slot I through Time Slot L.

Enable Channel 2 TIA ceiling detection interrupt status

byte for Time Slot A through Time Slot H. This byte

contains the interrupt status for the Channel 2 and

Channel 2 interrupts for Time Slot A through Time Slot H.

Enable Channel 1 TIA ceiling detection interrupt status

byte for Time Slot A through Time Slot H. This byte

contains the interrupt status for the Channel 1 and

Channel 2 interrupts for Time Slot A through Time Slot H.

Enable Level 0 and Level 1 interrupt status byte for

Time Slot I through Time Slot L. This byte contains the

interrupt status for the Level 0 and Level 1 interrupts for

Time Slot I through Time Slot L.

ENA_STAT_TC2

ENA_STAT_TC1

ENA_STAT_LX

ENA_STAT_L1

ENA_STAT_L0

0x0

R

R/W

Enable Level 1 interrupt status byte for Time Slot A

through Time Slot H. This byte contains the interrupt

status for the Level 1 interrupts for Time Slot A through

Time Slot H.

Enable Level 0 interrupt status byte for Time Slot A

through Time Slot H. This byte contains the interrupt

status for Level Interrupt 0 for Time Slot A through Time

Slot H.

2

1

0

ENA_STAT_D2

ENA_STAT_D1

ENA_STAT_SUM

Enable data interrupt status byte for Time Slot I through 0x0

Time Slot L. This byte contains the data interrupt status

for Time Slot I through Time Slot L.

R/W

Enable data interrupt status byte for Time Slot A through 0x0

Time Slot H. This byte is the data interrupt status for Time

Slot A through Time Slot H.

Enable status summary byte. When enabled, write a

status byte containing the summary pattern to the FIFO

following the last enabled time slot data.

0x0

¹R/W1C means write 1 to clear.

THRESHOLD SETUP AND CONTROL REGISTERS

Table 32. Threshold Setup and Control Register Details

Addr

0x0006 FIFO_TH

Name

Bits

[15:10] Reserved

[9:0] FIFO_TH

Bit Name

Description

Reserved.

Reset Access

0x00

0x000 R/W

R

FIFO interrupt generation threshold. Generate FIFO interrupt

during a FIFO write when the number of bytes in the FIFO exceeds

this value. The FIFO is 512 bytes. Therefore, the maximum value for

FIFO_TH is 0x1FF.

0x0115 THRESH_CFG_A [15:8] Reserved

Reserved.

0x0

R

R/W

0x0135 THRESH_CFG_B 7

0x0155 THRESH_CFG_C

0x0175 THRESH_CFG_D

THRESH1_CHAN_x Select channel for Level 1 interrupt.

0: use Channel 1.

1: use Channel 2.

0x0195 THRESH_CFG_E

0x01B5 THRESH_CFG_F

0x01D5 THRESH_CFG_G

6

THRESH1_DIR_x

Direction of comparison for Level 1 interrupt.

0: set when below Level 1 interrupt threshold.

1: set when above Level 1 interrupt threshold.

0x0

R/W

0x01F5 THRESH_CFG_H [5:4]

0x0215 THRESH_CFG_I

0x0235 THRESH_CFG_J

0x0255 THRESH_CFG_K

0x0275 THRESH_CFG_L

THRESH1_TYPE_x Type of comparison for Level 1 interrupt.

0: off (no comparison).

1: compare to signal.

10: compare to dark.

11: reserved.

Rev. 0 | Page 82 of 101

Data Sheet

ADPD4100/ADPD4101

Addr

Name

Bits

Bit Name

Description

Reset Access

3

THRESH0_CHAN_x Select channel for Level 0 interrupt.

0: use Channel 1.

0x0

R/W

1: use Channel 2.

2

THRESH0_DIR_x

Direction of comparison for Level 0 interrupt.

0: set when below Level 0 interrupt threshold.

1: set when above Level 0 interrupt threshold.

[1:0]

THRESH0_TYPE_x Type of comparison for Level 0 interrupt.

0: off (no comparison).

1: compare to signal.

10: compare to dark.

11: reserved.

0x0116 THRESH0_A

0x0136 THRESH0_B

0x0156 THRESH0_C

0x0176 THRESH0_D

0x0196 THRESH0_E

0x01B6 THRESH0_F

0x01D6 THRESH0_G

0x01F6 THRESH0_H

0x0216 THRESH0_I

0x0236 THRESH0_J

0x0256 THRESH0_K

0x0276 THRESH0_L

0x0117 THRESH1_A

0x0137 THRESH1_B

0x0157 THRESH1_C

0x0177 THRESH1_D

0x0197 THRESH1_E

0x01B7 THRESH1_F

0x01D7 THRESH1_G

0x01F7 THRESH1_H

0x0217 THRESH1_I

0x0237 THRESH1_J

0x0257 THRESH1_K

0x0277 THRESH1_L

[15:13] Reserved

Reserved.

0x0

R

R/W

[12:8] THRESH0_SHIFT_x Shift for Level 0 interrupt comparison threshold. Shift

THRESH0_VALUE_x by this amount before comparing.

[7:0]

THRESH0_VALUE_x Value for Level 0 interrupt comparison threshold.

0x0

R/W

[15:13] Reserved

Reserved.

0x0

R

R/W

[12:8] THRESH1_SHIFT_x Shift for Level 1 interrupt comparison threshold. Shift

THRESH1_VALUE_x by this amount before comparing.

[7:0]

THRESH1_VALUE_x Value for Level 1 interrupt comparison threshold.

0x0

R/W

Rev. 0 | Page 83 of 101

ADPD4100/ADPD4101

Data Sheet

CLOCK AND TIMESTAMP SETUP AND CONTROL REGISTERS

Table 33. Clock and Timestamp Setup and Control Register Details

Addr

0x0009 OSC32M

Name

Bits

[15:8] Reserved

[7:0] OSC_32M_FREQ_ADJ

Bit Name

Description

Reserved.

Reset Access

0x0

R

High frequency oscillator frequency control. 0x00 is the lowest 0x80 R/W

frequency, and 0xFF is maximum frequency.

0x000A OSC32M_CAL 15

OSC_32M_CAL_START

Start high frequency oscillator calibration cycle. Writing a 1 to 0x0

this bit causes the high frequency oscillator calibration cycle to

occur. 32 MHz oscillator cycles are counted during 128 low

frequency oscillator cycles if using the 1 MHz low frequency

oscillator, or 32 low frequency oscillator cycles if using the

32 kHz low frequency oscillator. The OSC_32M_CAL_COUNT

bits are updated with the count. The calibration circuit clears

the OSC_32M_CAL_START bit when the calibration cycle is

completed.

R/W

[14:0] OSC_32M_CAL_COUNT High frequency oscillator calibration count. These bits contain 0x0

the total number of 32 MHz cycles that occurred during the

R

last high frequency oscillator calibration cycle.

0x000B OSC1M

0x000C OSC32K

[15:11] Reserved

Reserved.

0x0

R

R/W

10

CLK_CAL_ENA

Enables clock for oscillator calibration. When set to 0 (default), 0x0

the oscillator calibration circuitry is disabled. Set this bit to 1 to

turn on the oscillator calibration circuitry.

Low frequency oscillator frequency control. 0x000 is the lowest 0x2B2 R/W

frequency, and 0x3FF is maximum frequency.

Enable time stamp capture. This bit is used to activate the time 0x0

stamp capture function. When set, the next rising edge on the

time stamp input (defaults to GPIO0) causes a time stamp

capture. This bit is cleared when the time stamp occurs.

[9:0]

15

OSC_1M_FREQ_ADJ

CAPTURE_TIMESTAMP

R/W

[14:6] Reserved

Reserved.

0x0

R

[5:0]

OSC_32K_ADJUST

32 kHz oscillator trim.

0x12 R/W

00 0000: maximum frequency.

01 0010: default frequency.

11 1111: minimum frequency.

Count at last time stamp. Lower 16 bits.

Count at last time stamp. Upper 16 bits.

0x0011 STAMP_L

0x0012 STAMP_H

[15:0] TIMESTAMP_COUNT_L

[15:0] TIMESTAMP_COUNT_H

0x0

R

0x0013 STAMPDELTA [15:0] TIMESTAMP_SLOT_DELTA Count remaining until next time slot start.

SYSTEM REGISTERS

Table 34. System Register Details

Addr

0x0008 CHIP_ID

Name

Bits

[15:8] Version

[7:0] CHIP_ID

0x002E DATA_HOLD_FLAG [15:12] Reserved

Bit Name

Description

Mask version.

Chip ID.

Reset Access

0x2

0xC2

0x0

R

Reserved.

R

R/W

11

10

9

HOLD_REGS_L

Prevent update of Time Slot L data registers.

0: allow data register update.

1: hold current contents of data register.

Prevent update of time Slot K data registers.

0: allow data register update.

1: hold current contents of data register.

Prevent update of Time Slot J data registers.

0: allow data register update.

1: hold current contents of data register.

Prevent update of Time Slot I data registers.

0: allow data register update.

1: hold current contents of data register.

Rev. 0 | Page 84 of 101

HOLD_REGS_K

HOLD_REGS_J

HOLD_REGS_I

0x0

R/W

8

Data Sheet

ADPD4100/ADPD4101

Addr

Name

Bits

Bit Name

Description

Reset Access

7

HOLD_REGS_H

Prevent Update of Time Slot H data registers.

0: allow data register update.

1: hold current contents of data register.

Prevent update of Time Slot G data registers.

0: allow data register update.

1: hold current contents of data register.

Prevent update of Time Slot F data registers.

0: allow data register update.

1: hold current contents of data register.

Prevent update of Time Slot E data registers.

0: allow data register update.

1: hold current contents of data register.

Prevent update of Time Slot D data registers.

0: allow data register update.

1: hold current contents of data register.

Prevent update of Time Slot C data registers.

0: allow data register update.

1: hold current contents of data register.

Prevent update of Time Slot B data registers.

0: allow data register update.

1: hold current contents of data register.

Prevent update of Time Slot A data registers.

0: allow data register update.

0x0

R/W

6

5

4

3

2

1

0

HOLD_REGS_G

HOLD_REGS_F

HOLD_REGS_E

HOLD_REGS_D

HOLD_REGS_C

HOLD_REGS_B

HOLD_REGS_A

1: hold current contents of data register.

0x00B6 I2C_KEY

[15:12] I2C_KEY_MATCH Write the I2C_KEY_MATCH bits to specify which GPIOx pins must 0x0

be high to change the slave address. A 0 ignores that specific

GPIO input. A 1 selects which GPIOx must be high to change the

address. Any combination is allowed. Use Bit 12 for GPIO0, Bit 13

for GPIO1, Bit 14 for GPIO2, and Bit 15 for GPIO3.

[11:0] I2C_KEY

I²C address change key. Must write these bits to 0x4AD to change 0x0

address. Write these bits at the same time that the I2C_KEY_MATCH

bits are written.

R0/W

R/W

0x00B7 I2C_ADDR

[15:8] I2C_SLAVE_KEY2 I²C key, Part 2. Must be written to 0xAD immediately following the 0x0

write of the I2C_KEY bits. The GPIOx pins as selected in the

I2C_KEY_MATCH bits must also be set high at this time.

[7:1]

0

I2C_SLAVE_ADDR I²C slave address update field. Write the desired 7-bit slave

0x24 R/W

0x0

address along with proper keys to change the I²C slave address.

Reserved

Reserved.

R

Rev. 0 | Page 85 of 101

ADPD4100/ADPD4101

Data Sheet

I/O SETUP AND CONTROL REGISTERS

Table 35. I/O Setup and Control Register Details

Addr

Name

Bits

Bit Name

Description

Reset Access

0x0022 GPIO_CFG [15:14] GPIO_SLEW

Slew control for GPIOx pins.

0: slowest.

1: slow.

10: fastest.

11: fast.

Drive control for GPIOx pins.

0: medium.

1: weak.

10: strong.

11: strong.

0x0

R/W

[13:12] GPIO_DRV

[11:9] GPIO_PIN_CFG3

GPIO3 pin configuration.

000: disabled (tristate, input buffer off).

001: enabled input.

010: output—normal.

011: output—inverted.

100: pull-down only—normal.

101: pull-down only—inverted.

110: pull-up only—normal.

111: pull-up only—inverted.

GPIO2 pin configuration.

000: disabled (tristate, input buffer off).

001: enabled input.

010: output—normal.

011: output—inverted.

100: pulldown only—normal.

101: pull-down only—inverted.

110: pull-up only—normal.

111: pull-up only—inverted.

GPIO1 pin configuration.

000: disabled (tristate, input buffer off).

001: enabled input.

010: output—normal.

011: output—inverted.

100: pull-down only—normal.

101: pull-down only—inverted.

110: pull-up only—normal.

111: pull-up only—inverted.

GPIO0 pin configuration.

000: disabled (tristate, input buffer off).

001: enabled input.

[8:6]

[5:3]

[2:0]

GPIO_PIN_CFG2

GPIO_PIN_CFG1

GPIO_PIN_CFG0

0x0

R/W

010: output—normal.

011: output—inverted.

100: pull-down only—normal.

101: pull-down only—inverted.

110: pull-up only—normal.

111: pull-up only—inverted.

Rev. 0 | Page 86 of 101

Data Sheet

ADPD4100/ADPD4101

Addr

Name

Bits

Bit Name

Description

Reset Access

0x0023 GPIO01

15

Reserved

Reserved.

GPIO1 output signal select.

0x00: Output Logic 0.

0x0

R

R/W

[14:8] GPIOOUT1

0x01: Output Logic 1.

0x02: Interrupt X.

0x03: Interrupt Y.

0x08: LED1x amplifier enable

0x09: LED2x amplifier enable

0x0A: LED3x amplifier enable

0x0B: LED4x amplifier enable

0x0C: Any LED amplifier enable

0x0F: 32 MHz oscillator output divided by 64 (500 kHz).

0x10: time slot specific output pattern defined by TS_GPIO_x and

TS_GPIO_SLEEP bits.

0x11: in sleep state.

0x16: low frequency oscillator output.

0x17: 32 MHz oscillator output.

0x18: 32 MHz oscillator output divided by 32 (1 MHz).

0x20: Time Slot A active.

0x21: Time Slot B active.

0x22: Time Slot C active.

0x23: Time Slot D active.

0x24: Time Slot E active.

0x25: Time Slot F active.

0x26: Time Slot G active.

0x27: Time Slot H active.

0x28: Time Slot I active.

0x29: Time Slot J active.

0x2A: Time Slot K active.

0x2B: Time Slot L active.

0x30: Time Slot A LED pulse.

0x31: Time Slot B LED pulse.

0x32: Time Slot C LED pulse.

0x33: Time Slot D LED pulse.

0x34: Time Slot E LED pulse.

0x35: Time Slot F LED pulse.

0x36: Time Slot G LED pulse.

0x37: Time Slot H LED pulse.

0x38: Time Slot I LED pulse.

0x39: Time Slot J LED pulse.

0x3A: Time Slot K LED pulse.

0x3B: Time Slot L LED pulse.

0x3F: any time slot LED pulse.

0x40: Time Slot A modulation pulse.

0x41: Time Slot B modulation pulse.

0x42: Time Slot C modulation pulse.

0x43: Time Slot D modulation pulse.

0x44: Time Slot E modulation pulse.

0x45: Time Slot F modulation pulse.

0x46: Time Slot G modulation pulse.

0x47: Time Slot H modulation pulse.

0x48: Time Slot I modulation pulse.

0x49: Time Slot J modulation pulse.

Rev. 0 | Page 87 of 101

ADPD4100/ADPD4101

Data Sheet

Addr

Name

Bits

Bit Name

Description

Reset Access

0x4A: Time Slot K modulation pulse.

0x4B: Time Slot L modulation pulse.

0x4F: any time slot modulation pulse.

0x50: output data cycle occurred in Time Slot A, which is useful

when synchronizing an external device to a decimated data rate

from the ADPD4100/ADPD4101.

0x51: output data cycle occurred in Time Slot B.

0x52: output data cycle occurred in Time Slot C.

0x53: output data cycle occurred in Time Slot D.

0x54: output data cycle occurred in Time Slot E.

0x55: output data cycle occurred in Time Slot F.

0x56: output data cycle occurred in Time Slot G.

0x57: output data cycle occurred in Time Slot H.

0x58: output data cycle occurred in Time Slot I.

0x59: output data cycle occurred in Time Slot J.

0x5A: output data cycle occurred in Time Slot K.

0x5B: output data cycle occurred in Time Slot L.

0x5F: output data cycle occurred in any time slot.

Reserved.

7

[6:0]

Reserved

GPIOOUT0

0x0

R

R/W

GPIO0 output signal select. Options are identical to those

described in GPIOOUT1.

0x0024 GPIO23

0x0025 GPIO_IN

15

Reserved

Reserved.

0x0

R

R/W

[14:8] GPIOOUT3

GPIO3 output signal select. Options are identical to those

described in GPIOOUT1.

7

[6:0]

Reserved

GPIOOUT2

Reserved.

0x0

R

R/W

GPIO2 output signal select. Options are identical to those

described in GPIOOUT1.

[15:4] Reserved

[3:0] GPIO_INPUT

Reserved.

0x0

R

GPIO input value (if enabled). Read back the value present on any 0x0

GPIO enabled as an input. Bit 0 is GPIO1, Bit 1 is GPIO1, Bit 2 is

GPIO2, and Bit 3 is GPIO3.

0x0026 GPIO_EXT [15:9] Reserved

Reserved.

0x0

R

R/W

8

TS_GPIO_SLEEP

When GPIOOUTx is set to 0x10, the GPIO returns to the

TS_GPIO_SLEEP value at the end of the time slot and during sleep.

7

TIMESTAMP_INV

Time stamp trigger invert.

0x0

R/W

0: time stamp trigger is rising edge.

1: time stamp trigger is falling edge.

6

TIMESTAMP_ALWAYS_EN Enable time stamp always on. When set, do not automatically

clear CAPTURE_TIMESTAMP. This bit provides an always activated

time stamp.

0x0

R/W

[5:4]

TIMESTAMP_GPIO

Time stamp GPIO select.

0x0: use GPIO0 for time stamp (default).

0x1: use GPIO1 for time stamp.

0x2: use GPIO2 for time stamp.

0x3: use GPIO3 for time stamp

Reserved.

External sync enable. When enabled, use the GPIO selected by

EXT_SYNC_GPIO to trigger samples rather than the period

counter.

3

2

Reserved

EXT_SYNC_EN

0x0

R/W

[1:0]

EXT_SYNC_GPIO

External synchronization GPIO select.

0x0

R/W

00: use GPIO0 for external synchronization

01: use GPIO1 for external synchronization.

10: use GPIO2 for external synchronization.

11: use GPIO3 for external synchronization.

Rev. 0 | Page 88 of 101

Data Sheet

ADPD4100/ADPD4101

Addr

Name

Bits

Bit Name

Description

Reset Access

0x00B4 IO_ADJUST [15:7] Reserved

Reserved.

0x000 R

6

LOW_IOVDD_EN

Set to 0x0 if IOVDD of 3 V or higher is used. Default value of 0x1

used for IOVDD is lower than 3 V, because the typical value of

IOVDD is 1.8 V.

0x1

R/W

[5:4]

[3:2]

Reserved

SPI_SLEW

Set to 0x01.

Slew control for SPI pins.

0: slowest.

1: slow.

10: fastest.

0x01 R/W

0x0

R/W

11: fast.

[1:0]

SPI_DRV

Drive control for SPI pins.

0: medium.

1: weak.

10: strong.

11: strong.

TIME SLOT CONFIGURATION REGISTERS

Table 36. Time Slot Configuration Register Details

Addr

Name

Bits

Bit Name

Description

Reset Access

0x0100 TS_CTRL_A

0x0120 TS_CTRL_B

0x0140 TS_CTRL_C

0x0160 TS_CTRL_D

0x0180 TS_CTRL_E

0x01A0 TS_CTRL_F

0x01C0 TS_CTRL_G

0x01E0 TS_CTRL_H

0x0200 TS_CTRL_I

0x0220 TS_CTRL_J

0x0240 TS_CTRL_K

0x0260 TS_CTRL_L

15

SUBSAMPLE_x

Subsample using DECIMATE_FACTOR_x. When this bit is

set, operate the selected time slot only once per

(DECIMATE_FACTOR_x + 1) time slot sequences.

0x0

R/W

14

CH2_EN_x

Channel 2 enable.

0: Channel 2 disabled.

1: Channel 2 enabled.

[13:12] SAMPLE_TYPE_x

Time Slot x sampling type.

00: standard sampling modes.

01: one-region digital integration mode.

10: two-region digital integration mode.

11: impulse response mode.

[11:10] INPUT_R_SELECT_x

Input resistor (R_IN) select.

00: 500 Ω.

0x0

R/W

01: 6.5 kΩ.

10: reserved.

11: reserved.

[9:0]

TIMESLOT_OFFSET_x Time Slot x offset in 64 × the number of 1 MHz low

frequency oscillator cycles or 2 × the number of 32 kHz

low frequency oscillator cycles.

0x0

0x4

R/W

0x0101 TS_PATH_A

0x0121 TS_PATH_B

0x0141 TS_PATH_C

0x0161 TS_PATH_D

0x0181 TS_PATH_E

0x01A1 TS_PATH_F

0x01C1 TS_PATH_G

0x01E1 TS_PATH_H

0x0201 TS_PATH_I

[15:12] PRE_WIDTH_x

Preconditioning duration for Time Slot x. This value is in

2 μs increments. A value of 0 skips the preconditioning

state. Default is 8 μs.

[11:10] Reserved

Write 0x0.

0x0

R

R/W

9

TS_GPIO_x

Time slot specific value for Time Slot x. When GPIOOUTx is 0x0

set to 0x10 and TS_GPIO_x is set to 1, the GPIO selected

by GPIOOUTx outputs a 1 while the time slot selected by

TS_GPIO_x is active. The GPIO returns to the

TS_GPIO_SLEEP value at the end of the time slot.

Rev. 0 | Page 89 of 101

ADPD4100/ADPD4101

Data Sheet

Addr

Name

Bits

Bit Name

Description

Reset Access

0x0221 TS_PATH_J

0x0241 TS_PATH_K

0x0261 TS_PATH_L

[8:0]

AFE_PATH_CFG_x

Signal path selection.

0x0DA: TIA, BPF, integrator, and ADC.

0x0E6: TIA, integrator, and ADC.

0x0DA R/W

0x106: TIA and ADC.

0x101: ADC.

0x0E1: buffer and ADC.

0x0E6: TIA, integrator, and ADC.

0x0102 INPUTS_A

0x0122 INPUTS_B

0x0142 INPUTS_C

0x0162 INPUTS_D

0x0182 INPUTS_E

0x01A2 INPUTS_F

0x01C2 INPUTS_G

0x01E2 INPUTS_H

0x0202 INPUTS_I

0x0222 INPUTS_J

0x0242 INPUTS_K

0x0262 INPUTS_L

[15:12] INP78_x

IN7 and IN8 input pair enable.

0x0

R/W

0000: input pair disabled. IN7 and IN8 disconnected.

0001: IN7 connected to Channel 1. IN8 disconnected.

0010: IN7 connected to Channel 2. IN8 disconnected.

0011: IN7 disconnected. IN8 connected to Channel 1.

0100: IN7 disconnected. IN8 connected to Channel 2.

0101: IN7 connected to Channel 1. IN8 connected to

Channel 2.

0110: IN7 connected to Channel 2. IN8 connected to

Channel 1.

0111: IN7 and IN8 connected to Channel 1. Single-

ended or differential, based on PAIR78.

1000: IN7 and IN8 connected to Channel 2. Single-ended

or differential, based on PAIR78.

[11:8] INP56_x

IN5 and IN6 input pair enable.

0x0

R/W

0000: input pair disabled. IN5 and IN6 disconnected.

0001: IN5 connected to Channel 1. IN6 disconnected.

0010: IN5 connected to Channel 2. IN6 disconnected.

0011: IN5 disconnected. IN6 connected to Channel 1.

0100: IN5 disconnected. IN6 connected to Channel 2.

0101: IN5 connected to Channel 1. IN6 connected to

Channel 2.

0110: IN5 connected to Channel 2. IN6 connected to

Channel 1.

0111: IN5 and IN6 connected to Channel 1. Single-ended

or differential, based on PAIR56.

1000: IN5 and IN6 connected to Channel 2. Single-ended

or differential, based on PAIR56.

[7:4]

INP34_x

IN3 and IN4 input pair enable.

0x0

R/W

0000: input pair disabled. IN3 and IN4 disconnected.

0001: IN3 connected to Channel 1. IN4 disconnected.

0010: IN3 connected to Channel 2. IN4 disconnected.

0011: IN3 disconnected. IN4 connected to Channel 1.

0100: IN3 disconnected. IN4 connected to Channel 2.

0101: IN3 connected to Channel 1. IN4 connected to

Channel 2.

0110: IN3 connected to Channel 2. IN4 connected to

Channel 1.

0111: IN3 and IN4 connected to Channel 1. Single-ended

or differential, based on PAIR34.

1000: IN3 and IN4 connected to Channel. Single-ended or

differential, based on PAIR34.

Rev. 0 | Page 90 of 101

Data Sheet

ADPD4100/ADPD4101

Addr

Name

Bits

Bit Name

Description

Reset Access

[3:0]

INP12_x

IN1 and IN2 input pair enable.

0x0

R/W

0000: input pair disabled. IN1 and IN2 disconnected.

0001: IN1 connected to Channel 1. IN2 disconnected.

0010: IN1 connected to Channel 2. IN2 disconnected.

0011: IN1 disconnected. IN2 connected to Channel 1.

0100: IN1 disconnected. IN2 connected to Channel 2.

0101: IN1 connected to Channel 1. IN2 connected to

Channel 2.

0110: IN1 connected to Channel 2. IN2 connected to

Channel 1.

0111: IN1 and IN2 connected to Channel 1. Single-ended

or differential, based on PAIR12.

1000: IN1 and IN2 connected to Channel 2. Single-ended

or differential, based on PAIR12.

0x0103 CATHODE_A

0x0123 CATHODE_B

0x0143 CATHODE_C

0x0163 CATHODE_D

0x0183 CATHODE_E

0x01A3 CATHODE_F

0x01C3 CATHODE_G

0x01E3 CATHODE_H

0x0203 CATHODE_I

0x0223 CATHODE_J

0x0243 CATHODE_K

0x0263 CATHODE_L

15

Reserved

Reserved.

0x0

R

R/W

[14:12] PRECON_x

Precondition value for enabled inputs during Time Slot x.

000: float input(s).

001: precondition to VC1.

010: precondition to VC2.

011: precondition to V_ICM. Used when inputs are

configured differentially.

100: precondition with TIA input.

101: precondition with TIA_VREF.

110: precondition by shorting differential pair.

VC2 pulse control for Time Slot x.

00: no pulsing.

01: alternate VC2 on each subsequent Time Slot x.

10: pulse to alternate value specified in VC2_ALT_x using

modulation pulse.

VC2 alternate pulsed state for Time Slot x.

00: V_DD.

01: TIA_VREF.

10: TIA_VREF + 215 mV.

11: GND.

VC2 active state for Time Slot x.

00: V_DD.

[11:10] VC2_PULSE_x

0x0

R/W

[9:8]

[7:6]

VC2_ALT_x

VC2_SEL_x

0x0

R/W

01: TIA_VREF.

10: TIA_VREF + 215 mV.

11: GND.

[5:4]

[3:2]

VC1_PULSE_x

VC1_ALT_x

VC1 pulse control for Time Slot x.

00: no pulsing.

01: alternate VC1 on each subsequent Time Slot x.

10: pulse to alternate value specified in VC1_ALT_x using

modulation pulse.

VC1 alternate pulsed state for Time Slot x.

00: V_DD.

0x0

R/W

01: TIA_VREF.

10: TIA_VREF + 215 mV.

11: GND.

[1:0]

VC1_SEL_x

VC1 active state for Time Slot x.

00: V_DD.

0x0

R/W

01: TIA_VREF.

10: TIA_VREF + 215 mV.

11: GND.

Rev. 0 | Page 91 of 101

ADPD4100/ADPD4101

Data Sheet

Addr

Name

Bits

Bit Name

Description

Reset Access

0x0104 AFE_TRIM_A

0x0124 AFE_TRIM_B

0x0144 AFE_TRIM_C

0x0164 AFE_TRIM_D

0x0184 AFE_TRIM_E

0x01A4 AFE_TRIM_F

0x01C4 AFE_TRIM_G

0x01E4 AFE_TRIM_H

0x0204 AFE_TRIM_I

0x0224 AFE_TRIM_J

0x0244 AFE_TRIM_K

0x0264 AFE_TRIM_L

15

TIA_CEIL_DETECT_

EN_x

Set to 1 to enable TIA ceiling detection circuitry. Enables

Channel 1 TIA ceiling detection circuitry and Channel 2

TIA ceiling detection circuitry if Channel 2 is also enabled.

0x0

R/W

[14:13] CH2_TRIM_INT_x

Set the integrator input resistor when AFE_INT_C_BUF_x = 0. 0x0

Set the buffer gain when AFE_INT_C_BUF_x = 1

R/W

AFE_INT_C_BUF_x = 0

00: 400 kΩ.

AFE_INT_C_BUF_x = 1

00: gain = 1.

01: 200 kΩ.

01: gain = 1.

10: 100 kΩ.

11: 100 kΩ.

10: gain = 0.7.

11: gain = 0.7.

[12:11] CH1_TRIM_INT_x

Set the integrator input resistor when AFE_INT_C_BUF_x = 0. 0x0

Set the buffer gain when AFE_INT_C_BUF_x = 1 or in

digital integration mode.

R/W

AFE_INT_C_BUF_x = 0

00: 400 kΩ.

AFE_INT_C_BUF_x = 1

00: gain = 1.

01: 200 kΩ.

01: gain = 1.

10: 100 kΩ.

11: 100 kΩ.

10: gain = 0.7.

11: gain = 0.7.

10

VREF_PULSE_x

TIA_VREF pulse control.

0: no pulsing.

1: pulse TIA_VREF based on modulation pulse.

Voltage select for TIA_VREF.

00: TIA_VREF = 1.1385 V.

0x0

0x3

R/W

[9:8]

AFE_TRIM_VREF_x

01: TIA_VREF = 1.012 V.

10: TIA_VREF = 0.8855 V.

11: TIA_VREF = 1.265 V.

[7:6]

[5:3]

VREF_PULSE_VAL_x TIA_VREF pulse alternate value.

00: modulate TIA_VREF = 1.1385 V.

0x3

0x0

R/W

01: modulate TIA_VREF = 1.012 V.

10: modulate TIA_VREF = 0.8855 V.

11: modulate TIA_VREF = 1.265 V.

TIA_GAIN_CH2_x

TIA_GAIN_CH1_x

TIA resistor gain setting for Channel 2.

000: 200 kΩ.

001: 100 kΩ.

010: 50 kΩ.

011: 25 kΩ.

100: 12.5 kΩ.

TIA resistor gain setting for Channel 1.

000: 200 kΩ.

[2:0]

0x0

R/W

001: 100 kΩ.

010: 50 kΩ.

011: 25 kΩ.

100: 12.5 kΩ.

0x010D PATTERN_A

0x012D PATTERN_B

0x014D PATTERN_C

0x016D PATTERN_D

0x018D PATTERN_E

0x01AD PATTERN_F

0x01CD PATTERN_G

0x01ED PATTERN_H

0x020D PATTERN_I

[15:12] LED_DISABLE_x

[11:8] MOD_DISABLE_x

Four-pulse LED disable pattern. Set to 1 to disable the LED 0x0

pulse in the matching position in a group of four pulses.

The LSB maps to the first pulse.

R/W

Four-pulse modulation disable pattern. Set to 1 to disable 0x0

the modulation pulse in the matching position in a group

of four pulses. The LSB maps to the first pulse.

[7:4]

SUBTRACT_x

Four-pulse subtract pattern. Set to 1 to negate the math

operation in the matching position in a group of four

pulses. The LSB maps to the first pulse.

0x0

Rev. 0 | Page 92 of 101

Data Sheet

ADPD4100/ADPD4101

Addr

Name

Bits

Bit Name

Description

Reset Access

0x022D PATTERN_J

0x024D PATTERN_K

0x026D PATTERN_L

[3:0]

REVERSE_INTEG_x

Four-pulse integration reverse pattern. Set to 1 to reverse 0x0

the integrator positive/negative pulse order in the

matching position in a group of four pulses. The LSB maps

to the first pulse.

R/W

0x0110 DATA_FORMAT_A

0x0130 DATA_FORMAT_B

0x0150 DATA_FORMAT_C

0x0170 DATA_FORMAT_D

0x0190 DATA_FORMAT_E

0x01B0 DATA_FORMAT_F

0x01D0 DATA_FORMAT_G

0x01F0 DATA_FORMAT_H

0x0210 DATA_FORMAT_I

0x0230 DATA_FORMAT_J

0x0250 DATA_FORMAT_K

0x0270 DATA_FORMAT_L

[15:11] DARK_SHIFT_x

[10:8] DARK_SIZE_x

Number of bits to shift the dark data to the right before

writing to the FIFO for Time Slot x. Selectable between

0 bits and 32 bits.

0x0

R/W

Number of bytes of dark data to be written to the FIFO for 0x0

Time Slot x. Selectable between 0 bytes and 4 bytes.

R/W

[7:3]

[2:0]

SIGNAL_SHIFT_x

SIGNAL_SIZE_x

Number of bits to shift the signal data to the right before 0x0

writing to the FIFO for Time Slot x. Selectable between

0 bits and 32 bits.

Number of bytes of signal data to be written to the FIFO

for Time Slot x. Selectable between 0 bytes and 4 bytes.

0x3

R/W

0x0111 LIT_DATA_FORMAT_A [15:8] Reserved

Reserved

0x0

R/W

0x0131 LIT_DATA_FORMAT_B [7:3]

0x0151 LIT_DATA_FORMAT_C

0x0171 LIT_DATA_FORMAT_D

0x0191 LIT_DATA_FORMAT_E [2:0]

0x01B1 LIT_DATA_FORMAT_F

0x01D1 LIT_DATA_FORMAT_G

0x01F1 LIT_DATA_FORMAT_H

0x0211 LIT_DATA_FORMAT_I

0x0231 LIT_DATA_FORMAT_J

0x0251 LIT_DATA_FORMAT_K

0x0271 LIT_DATA_FORMAT_L

LIT_SHIFT_x

Number of bits to shift the lit data to the right before

writing to the FIFO for Time Slot x. Selectable between

0 bits and 32 bits.

LIT_SIZE_x

Number of bytes of lit data to be written to the FIFO for

Time Slot x. Selectable between 0 bytes and 4 bytes.

0x3

R/W

0x0112 DECIMATE_A

0x0132 DECIMATE_B

0x0152 DECIMATE_C

0x0172 DECIMATE_D

0x0192 DECIMATE_E

0x01B2 DECIMATE_F

0x01D2 DECIMATE_G

0x01F2 DECIMATE_H

0x0212 DECIMATE_I

0x0232 DECIMATE_J

0x0252 DECIMATE_K

0x0272 DECIMATE_L

[15:11] Reserved

Write 0x0.

0x0

R

R/W

[10:4] DECIMATE_FACTOR_x Decimate sample divider. Output data rate is sample

rate ÷ (DECIMATE_FACTOR_x + 1). Decimate by 1 to 128.

[3:0]

DECIMATE_TYPE_x

Decimation type select.

0x0

R/W

0: block sum, CIC first order.

1: signal uses CIC second order.

10: signal uses CIC third order.

11: signal uses CIC fourth order.

100: reserved.

Rev. 0 | Page 93 of 101

ADPD4100/ADPD4101

Data Sheet

AFE TIMING SETUP REGISTERS

Table 37. AFE Timing Setup Register Details

Addr

Name

Bits

Bit Name

Description

Reset Access

0x0107 COUNTS_A

0x0127 COUNTS_B

0x0147 COUNTS_C

0x0167 COUNTS_D

0x0187 COUNTS_E

0x01A7 COUNTS_F

0x01C7 COUNTS_G

0x01E7 COUNTS_H

0x0207 COUNTS_I

0x0227 COUNTS_J

0x0247 COUNTS_K

0x0267 COUNTS_L

0x0108 PERIOD_A

0x0128 PERIOD_B

0x0148 PERIOD_C

0x0168 PERIOD_D

0x0188 PERIOD_E

0x01A8 PERIOD_F

0x01C8 PERIOD_G

0x01E8 PERIOD_H

0x0208 PERIOD_I

0x0228 PERIOD_J

0x0248 PERIOD_K

0x0268 PERIOD_L

[15:8] NUM_INT_x

Number of ADC cycles or acquisition width. Number of analog 0x1

integration cycles per ADC conversion or the acquisition width

for digital integration and impulse mode. A setting of 0 is not

allowed.

R/W

[7:0]

NUM_REPEAT_x

Number of sequence repeats. Total number of pulses =

NUM_INT_x × NUM_REPEAT_x. A setting of 0 is not allowed.

0x1

[15:14] Reserved

[13:12] MOD_TYPE_x

Reserved.

Modulation connection type.

0x0

R

R/W

00: TIA is continuously connected to input after precondition.

No connection modulation.

01: float type operation. Pulse connection from input to TIA

with modulation pulse, floating between pulses.

10: nonfloat type connection modulation. Pulse connection

from input to TIA. Connect to precondition value between

pulses.

[11:10] Reserved

Reserved.

0x0

R

R/W

[9:0]

MIN_PERIOD_x

Minimum period for pulse repetition in μs. Override for the

automatically calculated period. Used in float type operations

to set the float time of second and subsequent floats using the

formula: Float Time = MIN_PERIOD_x − MOD_WIDTH_x.

0x010A INTEG_SETUP_A 15

0x012A INTEG_SETUP_B

0x014A INTEG_SETUP_C

SINGLE_INTEG_x

Use single integrator pulse.

0: use both generated integrator clocks.

1: skip the second integrator clock.

0x0

R/W

0x016A INTEG_SETUP_D [14:12] CH2_AMP_DISABLE_x Amplifier disables for power control. Set the appropriate bit to 0x0

0x018A INTEG_SETUP_E

0x01AA INTEG_SETUP_F

0x01CA INTEG_SETUP_G

0x01EA INTEG_SETUP_H

0x020A INTEG_SETUP_I 11

disable the Channel 2 amplifier in Time Slot x.

0: TIA.

1: BPF.

2: integrator.

AFE_INT_C_BUF_x

Set to 1 to configure the integrator as a buffer in Time Slot x.

0x0

R/W

0x022A INTEG_SETUP_J [10:8] CH1_AMP_DISABLE_x Amplifier disables for power control. Set the appropriate bit to 0x0

disable the Channel 1 amplifier in Time Slot x.

0x024A INTEG_SETUP_K

0x026A INTEG_SETUP_L

0: TIA.

1: BPF.

2: integrator.

[7:6]

ADC_COUNT_x

ADC conversions per pulse. Number of conversions =

ADC_COUNT + 1.

0x0

R/W

5

[4:0]

Reserved

INTEG_WIDTH_A

Reserved.

0x0

0x3

R

R/W

Integrator clock width in μs. Must be >0.

Rev. 0 | Page 94 of 101

Data Sheet

ADPD4100/ADPD4101

Addr

Name

Bits

Bit Name

Description

Reset Access

0x010B INTEG_OS_A

0x012B INTEG_OS_B

0x014B INTEG_OS_C

0x016B INTEG_OS_D

0x018B INTEG_OS_E

0x01AB INTEG_OS_F

0x01CB INTEG_OS_G

0x01EB INTEG_OS_H

0x020B INTEG_OS_I

0x022B INTEG_OS_J

0x024B INTEG_OS_K

0x026B INTEG_OS_L

[15:13] Reserved

[12:5] INTEG_OFFSET_x

Reserved.

0x0

0x10

R

R/W

Integrator clock offset for Time Slot x in 1 µs increments per LSB.

Must be >0.

0x14

[4:0]

INTEG_OFFSET_x

Integrator clock offset for Time Slot x in 31.25 ns increments

per LSB.

R/W

0x010C MOD_PULSE_A [15:8] MOD_WIDTH_x

Modulation pulse width for Time Slot x in μs. 0 = disable.

Modulation pulse offset for Time Slot x in μs. Must be >0.

0x0

0x1

R/W

0x012C MOD_PULSE_B [7:0]

0x014C MOD_PULSE_C

0x016C MOD_PULSE_D

0x018C MOD_PULSE_E

0x01AC MOD_PULSE_F

0x01CC MOD_PULSE_G

0x01EC MOD_PULSE_H

0x020C MOD_PULSE_I

0x022C MOD_PULSE_J

0x024C MOD_PULSE_K

0x026C MOD_PULSE_L

MOD_OFFSET_x

0x0113 DIGINT_LIT_A

0x0133 DIGINT_LIT_B

0x0153 DIGINT_LIT_C

0x0173 DIGINT_LIT_D

0x0193 DIGINT_LIT_E

0x01B3 DIGINT_LIT_F

0x01D3 DIGINT_LIT_G

0x01F3 DIGINT_LIT_H

0x0213 DIGINT_LIT_I

0x0233 DIGINT_LIT_J

0x0253 DIGINT_LIT_K

0x0273 DIGINT_LIT_L

[15:9] Reserved

[8:0] LIT_OFFSET_x

Reserved.

0x0

R

Digital integration mode, acquisition window lit offset in μs for 0x26 R/W

Time Slot x. Also, impulse response mode offset. Must be >0.

0x0114 DIGINT_DARK_A [15:7] DARK2_OFFSET_x

0x0134 DIGINT_DARK_B

Digital integration mode, acquisition window Dark Offset 2 for 0x046 R/W

Time Slot x in μs. Must be >0.

0x0154 DIGINT_DARK_C [6:0]

0x0174 DIGINT_DARK_D

0x0194 DIGINT_DARK_E

0x01B4 DIGINT_DARK_F

0x01D4 DIGINT_DARK_G

0x01F4 DIGINT_DARK_H

0x0214 DIGINT_DARK_I

0x0234 DIGINT_DARK_J

0x0254 DIGINT_DARK_K

0x0274 DIGINT_DARK_L

DARK1_OFFSET_x

Digital integration mode, acquisition window Dark Offset 1 for 0x6

Time Slot x in μs. Must be >0.

R/W

Rev. 0 | Page 95 of 101

ADPD4100/ADPD4101

Data Sheet

LED CONTROL AND TIMING REGISTERS

Table 38. LED Control and Timing Register Details

Addr

Name

Bits Bit Name

Description

LED_DRIVESIDE2_x LED output select for LED2x.

0: drive LED on Output LED2A.

Reset Access

0x0105 LED_POW12_A 15

0x0125 LED_POW12_B

0x0145 LED_POW12_C

0x0

0x2

R/W

1: drive LED on Output LED2B.

0x0165 LED_POW12_D [14:8] LED_CURRENT2_x LED current setting for LED2A or LED2B output. Set to 0 to disable.

Output current varies monotonically from 1.5 mA to 200 mA for

values between 0x01 and 0x7F.

0x0185 LED_POW12_E

0x01A5 LED_POW12_F

0x01C5 LED_POW12_G 7

0x01E5 LED_POW12_H

0x0205 LED_POW12_I

LED_DRIVESIDE1_x LED output select for LED1x.

0: drive LED on Output LED1A.

1: drive LED on Output LED1B.

0x0225 LED_POW12_J [6:0] LED_CURRENT1_x LED current setting for LED1A or LED1B output. Set to 0 to disable.

Output current varies monotonically from 1.5 mA to 200 mA for

values between 0x01 and 0x7F.

0x0245 LED_POW12_K

0x0265 LED_POW12_L

0x0106 LED_POW34_A 15

0x0126 LED_POW34_B

0x0146 LED_POW34_C

LED_DRIVESIDE4_x LED output select for LED4x.

0: drive LED on Output LED4A.

1: drive LED on Output LED4B.

0x0166 LED_POW34_D [14:8] LED_CURRENT4_x LED current setting for LED4A or LED4B output. Set to 0 to disable.

Output current varies monotonically from 1.5 mA to 200 mA for

values between 0x01 and 0x7F.

0x0186 LED_POW34_E

0x01A6 LED_POW34_F

0x01C6 LED_POW34_G 7

0x01E6 LED_POW34_H

0x0206 LED_POW34_I

LED_DRIVESIDE3_x LED output select for LED3x.

0: drive LED on Output LED3A.

1: drive LED on Output LED3B.

0x0226 LED_POW34_J [6:0] LED_CURRENT3_x LED current setting for LED3A or LED3B output. Set to 0 to disable.

0x0246 LED_POW34_K

0x0266 LED_POW34_L

0x0109 LED_PULSE_A [15:8] LED_WIDTH_x

0x0129 LED_PULSE_B [7:0] LED_OFFSET_x

0x0149 LED_PULSE_C

Output current varies monotonically from 1.5 mA to 200 mA for

values between 0x01 and 0x7F.

LED pulse width in μs. 0 = disable.

LED pulse offset in μs. Set to a minimum of 16 μs (0x10). Must be >0. 0x10 R/W

0x0169 LED_PULSE_D

0x0189 LED_PULSE_E

0x01A9 LED_PULSE_F

0x01C9 LED_PULSE_G

0x01E9 LED_PULSE_H

0x0209 LED_PULSE_I

0x0229 LED_PULSE_J

0x0249 LED_PULSE_K

0x0269 LED_PULSE_L

Rev. 0 | Page 96 of 101

Data Sheet

ADPD4100/ADPD4101

ADC OFFSET REGISTERS

Table 39. ADC Offset Register Details

Addr

Name

Bits

Bit Name

Description

Reset Access

0x010E ADC_OFF1_A [15:14] Reserved

0x012E ADC_OFF1_B [13:0] CH1_ADC_ADJUST_x Adjustment to ADC value. This value is subtracted from the ADC

Reserved.

0x0

R

R/W

value for Channel 1 in Time Slot x. Set to 0 for chop and float modes.

0x014E ADC_OFF1_C

0x016E ADC_OFF1_D

0x018E ADC_OFF1_E

0x01AE ADC_OFF1_F

0x01CE ADC_OFF1_G

0x01EE ADC_OFF1_H

0x020E ADC_OFF1_I

0x022E ADC_OFF1_J

0x024E ADC_OFF1_K

0x026E ADC_OFF1_L

0x010F ADC_OFF2_A 15

0x012F ADC_OFF2_B 14

ZERO_ADJUST_x

Reserved

0x0

R/W

Reserved.

0x014F ADC_OFF2_C [13:0] CH2_ADC_ADJUST_x Adjustment to ADC value. This value is subtracted from the ADC

value for Channel 2 in Time Slot x. Set to 0 for chop and float modes.

0x016F ADC_OFF2_D

0x018F ADC_OFF2_E

0x01AF ADC_OFF2_F

0x01CF ADC_OFF2_G

0x01EF ADC_OFF2_H

0x020F ADC_OFF2_I

0x022F ADC_OFF2_J

0x024F ADC_OFF2_K

0x026F ADC_OFF2_L

OUTPUT DATA REGISTERS

Table 40. Output Data Register Details

Addr

Name

Bits

Bit Name

Description

Reset

Access

0x002F

0x0030

0x0031

0x0032

0x0033

0x0034

0x0035

0x0036

0x0037

0x0038

0x0039

0x003A

0x003B

0x003C

0x003D

0x003E

0x003F

0x0040

0x0041

0x0042

0x0043

FIFO_DATA

[15:0]

FIFO_DATA

FIFO data port

0x0

R

SIGNAL1_L_A

SIGNAL1_H_A

SIGNAL2_L_A

SIGNAL2_H_A

DARK1_L_A

DARK1_H_A

DARK2_L_A

DARK2_H_A

SIGNAL1_L_B

SIGNAL1_H_B

SIGNAL2_L_B

SIGNAL2_H_B

DARK1_L_B

DARK1_H_B

DARK2_L_B

DARK2_H_B

SIGNAL1_L_C

SIGNAL1_H_C

SIGNAL2_L_C

SIGNAL2_H_C

SIGNAL1_L_A

SIGNAL1_H_A

SIGNAL2_L_A

SIGNAL2_H_A

DARK1_L_A

DARK1_H_A

DARK2_L_A

DARK2_H_A

SIGNAL1_L_B

SIGNAL1_H_B

SIGNAL2_L_B

SIGNAL2_H_B

DARK1_L_B

Signal Channel 1 lower half, Time Slot A

Signal Channel 1 upper half, Time Slot A

Signal Channel 2 lower half, Time Slot A

Signal Channel 2 upper half, Time Slot A

Dark Channel 1 value lower half, Time Slot A

Dark Channel 1 value upper half, Time Slot A

Dark Channel 2 value lower half, Time Slot A

Dark Channel 2 value upper half, Time Slot A

Signal Channel 1 lower half, Time Slot B

Signal Channel 1 upper half, Time Slot B

Signal Channel 2 lower half, Time Slot B

Signal Channel 2 upper half, Time Slot B

Dark Channel 1 value lower half, Time Slot B

Dark Channel 1 value upper half, Time Slot B

Dark Channel 2 value lower half, Time Slot B

Dark Channel 2 value upper half, Time Slot B

Signal Channel 1 lower half, Time Slot C

Signal Channel 1 upper half, Time Slot C

Signal Channel 2 lower half, Time Slot C

Signal Channel 2 upper half, Time Slot C

DARK1_H_B

DARK2_L_B

DARK2_H_B

SIGNAL1_L_C

SIGNAL1_H_C

SIGNAL2_L_C

SIGNAL2_H_C

Rev. 0 | Page 97 of 101

ADPD4100/ADPD4101

Data Sheet

Addr

Name

Bits

Bit Name

Description

Reset

0x0

Access

R

0x0044

0x0045

0x0046

0x0047

0x0048

0x0049

0x004A

0x004B

0x004C

0x004D

0x004E

0x004F

0x0050

0x0051

0x0052

0x0053

0x0054

0x0055

0x0056

0x0057

0x0058

0x0059

0x005A

0x005B

0x005C

0x005D

0x005E

0x005F

0x0060

0x0061

0x0062

0x0063

0x0064

0x0065

0x0066

0x0067

0x0068

0x0069

0x006A

0x006B

0x006C

0x006D

0x006E

0x006F

0x0070

0x0071

0x0072

0x0073

0x0074

0x0075

0x0076

0x0077

0x0078

DARK1_L_C

DARK1_H_C

DARK2_L_C

DARK2_H_C

SIGNAL1_L_D

SIGNAL1_H_D

SIGNAL2_L_D

SIGNAL2_H_D

DARK1_L_D

DARK1_H_D

DARK2_L_D

DARK2_H_D

SIGNAL1_L_E

SIGNAL1_H_E

SIGNAL2_L_E

SIGNAL2_H_E

DARK1_L_E

DARK1_H_E

DARK2_L_E

DARK2_H_E

SIGNAL1_L_F

SIGNAL1_H_F

SIGNAL2_L_F

SIGNAL2_H_F

DARK1_L_F

DARK1_H_F

DARK2_L_F

DARK2_H_F

SIGNAL1_L_G

SIGNAL1_H_G

SIGNAL2_L_G

SIGNAL2_H_G

DARK1_L_G

DARK1_H_G

DARK2_L_G

DARK2_H_G

SIGNAL1_L_H

SIGNAL1_H_H

SIGNAL2_L_H

SIGNAL2_H_H

DARK1_L_H

DARK1_H_H

DARK2_L_H

DARK2_H_H

SIGNAL1_L_I

SIGNAL1_H_I

SIGNAL2_L_I

SIGNAL2_H_I

DARK1_L_I

[15:0]

DARK1_L_C

DARK1_H_C

DARK2_L_C

DARK2_H_C

SIGNAL1_L_D

SIGNAL1_H_D

SIGNAL2_L_D

SIGNAL2_H_D

DARK1_L_D

DARK1_H_D

DARK2_L_D

DARK2_H_D

SIGNAL1_L_E

SIGNAL1_H_E

SIGNAL2_L_E

SIGNAL2_H_E

DARK1_L_E

DARK1_H_E

DARK2_L_E

DARK2_H_E

SIGNAL1_L_F

SIGNAL1_H_F

SIGNAL2_L_F

SIGNAL2_H_F

DARK1_L_F

DARK1_H_F

DARK2_L_F

DARK2_H_F

SIGNAL1_L_G

SIGNAL1_H_G

SIGNAL2_L_G

SIGNAL2_H_G

DARK1_L_G

DARK1_H_G

DARK2_L_G

DARK2_H_G

SIGNAL1_L_H

SIGNAL1_H_H

SIGNAL2_L_H

SIGNAL2_H_H

DARK1_L_H

DARK1_H_H

DARK2_L_H

DARK2_H_H

SIGNAL1_L_I

SIGNAL1_H_I

SIGNAL2_L_I

SIGNAL2_H_I

DARK1_L_I

Dark Channel 1 value lower half, Time Slot C

Dark Channel 1 value upper half, Time Slot C

Dark Channel 2 value lower half, Time Slot C

Dark Channel 2 value upper half, Time Slot C

Signal Channel 1 lower half, Time Slot D

Signal Channel 1 upper half, Time Slot D

Signal Channel 2 lower half, Time Slot D

Signal Channel 2 upper half, Time Slot D

Dark Channel 1 value lower half, Time Slot D

Dark Channel 1 value upper half, Time Slot D

Dark Channel 2 value lower half, Time Slot D

Dark Channel 2 value upper half, Time Slot D

Signal Channel 1 lower half, Time Slot E

Signal Channel 1 upper half, Time Slot E

Signal Channel 2 lower half, Time Slot E

Signal Channel 2 upper half, Time Slot E

Dark Channel 1 value lower half, Time Slot E

Dark Channel 1 value upper half, Time Slot E

Dark Channel 2 value lower half, Time Slot E

Dark Channel 2 value upper half, Time Slot E

Signal Channel 1 lower half, Time Slot F

Signal Channel 1 upper half, Time Slot F

Signal Channel 2 lower half, Time Slot F

Signal Channel 2 upper half, Time Slot F

Dark Channel 1 value lower half, Time Slot F

Dark Channel 1 value upper half, Time Slot F

Dark Channel 2 value lower half, Time Slot F

Dark Channel 2 value upper half, Time Slot F

Signal Channel 1 lower half, Time Slot G

Signal Channel 1 upper half, Time Slot G

Signal Channel 2 lower half, Time Slot G

Signal Channel 2 upper half, Time Slot G

Dark Channel 1 value lower half, Time Slot G

Dark Channel 1 value upper half, Time Slot G

Dark Channel 2 value lower half, Time Slot G

Dark Channel 2 value upper half, Time Slot G

Signal Channel 1 lower half, Time Slot H

Signal Channel 1 upper half, Time Slot H

Signal Channel 2 lower half, Time Slot H

Signal Channel 2 upper half, Time Slot H

Dark Channel 1 value lower half, Time Slot H

Dark Channel 1 value upper half, Time Slot H

Dark Channel 2 value lower half, Time Slot H

Dark Channel 2 value upper half, Time Slot H

Signal Channel 1 lower half, Time Slot I

Signal Channel 1 upper half, Time Slot I

Signal Channel 2 lower half, Time Slot I

Signal Channel 2 upper half, Time Slot I

Dark Channel 1 value lower half, Time Slot I

Dark Channel 1 value upper half, Time Slot I

Dark Channel 2 value lower half, Time Slot I

Dark Channel 2 value upper half, Time Slot I

Signal Channel 1 lower half, Time Slot J

DARK1_H_I

DARK2_L_I

DARK2_H_I

SIGNAL1_L_J

DARK1_H_I

DARK2_L_I

DARK2_H_I

SIGNAL1_L_J

Rev. 0 | Page 98 of 101

Data Sheet

ADPD4100/ADPD4101

Addr

Name

Bits

Bit Name

Description

Reset

0x0

Access

0x0079

0x007A

0x007B

0x007C

0x007D

0x007E

0x007F

0x0080

0x0081

0x0082

0x0083

0x0084

0x0085

0x0086

0x0087

0x0088

0x0089

0x008A

0x008B

0x008C

0x008D

0x008E

0x008F

SIGNAL1_H_J

SIGNAL2_L_J

SIGNAL2_H_J

DARK1_L_J

DARK1_H_J

DARK2_L_J

DARK2_H_J

SIGNAL1_L_K

SIGNAL1_H_K

SIGNAL2_L_K

SIGNAL2_H_K

DARK1_L_K

DARK1_H_K

DARK2_L_K

DARK2_H_K

SIGNAL1_L_L

SIGNAL1_H_L

SIGNAL2_L_L

SIGNAL2_H_L

DARK1_L_L

DARK1_H_L

DARK2_L_L

DARK2_H_L

[15:0]

SIGNAL1_H_J

SIGNAL2_L_J

SIGNAL2_H_J

DARK1_L_J

DARK1_H_J

DARK2_L_J

Signal Channel 1 upper half, Time Slot J

Signal Channel 2 lower half, Time Slot J

Signal Channel 2 upper half, Time Slot J

Dark Channel 1 value lower half, Time Slot J

Dark Channel 1 value upper half, Time Slot J

Dark Channel 2 value lower half, Time Slot J

Dark Channel 2 value upper half, Time Slot J

Signal Channel 1 lower half, Time Slot K

Signal Channel 1 upper half, Time Slot K

Signal Channel 2 lower half, Time Slot K

Signal Channel 2 upper half, Time Slot K

Dark Channel 1 value lower half, Time Slot K

Dark Channel 1 value upper half, Time Slot K

Dark Channel 2 value lower half, Time Slot K

Dark Channel 2 value upper half, Time Slot K

Signal Channel 1 lower half, Time Slot L

Signal Channel 1 upper half, Time Slot L

Signal Channel 2 lower half, Time Slot L

Signal Channel 2 upper half, Time Slot L

Dark Channel 1 value lower half, Time Slot L

Dark Channel 1 value upper half, Time Slot L

Dark Channel 2 value lower half, Time Slot L

Dark Channel 2 value upper half, Time Slot L

R

DARK2_H_J

SIGNAL1_L_K

SIGNAL1_H_K

SIGNAL2_L_K

SIGNAL2_H_K

DARK1_L_K

DARK1_H_K

DARK2_L_K

DARK2_H_K

SIGNAL1_L_L

SIGNAL1_H_L

SIGNAL2_L_L

SIGNAL2_H_L

DARK1_L_L

DARK1_H_L

DARK2_L_L

DARK2_H_L

Rev. 0 | Page 99 of 101

ADPD4100/ADPD4101

OUTLINE DIMENSIONS

Data Sheet

2.180

2.140

2.100

0.225

BSC

5

4

3

2

1

A

B

C

D

E

F

BALL A1

IDENTIFIER

3.150

3.110

3.070

2.40

REF

0.40

BSC

0.485

BSC

G

TOP VIEW

BOTTOM VIEW

(BALL SIDE UP)

(BALL SIDE DOWN)

0.225

BSC

0.315

BSC

1.60

REF

0.330

0.560

0.500

0.440

0.300

0.270

SIDE VIEW

COPLANARITY

0.05

0.230

0.200

0.170

SEATING

PLANE

0.300

0.260

0.220

Figure 58. 35-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-35-2)

Dimensions shown in millimeters

2.180

2.140

2.100

0.225

BSC

5

4

3

2

1

A

B

C

D

E

F

BALL A1

IDENTIFIER

3.150

3.110

3.070

2.40

REF

0.40

BSC

0.485

BSC

G

TOP VIEW

BOTTOM VIEW

(BALL SIDE UP)

(BALL SIDE DOWN)

0.225

BSC

0.315

BSC

1.60

REF

0.330

0.560

0.500

0.440

0.300

0.270

SIDE VIEW

COPLANARITY

0.05

0.230

0.200

0.170

SEATING

PLANE

0.300

0.260

0.220

Figure 59. 33-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-33-1)

Dimensions shown in millimeters

Rev. 0 | Page 100 of 101

Data Sheet

ADPD4100/ADPD4101

ORDERING GUIDE

Model^{1, 2}

Temperature Range

−40°C to +85°C

Package Description

Package Option

ADPD4100BCBZR7

ADPD4101BCBZR7

EVAL-ADPD4100Z-PPG

35-Ball Wafer Level Chip Scale Package [WLCSP]

33-Ball Wafer Level Chip Scale Package [WLCSP]

Evaluation Board

CB-35-2

CB-33-1

¹Z = RoHS Compliant Part.

²EVAL-ADPDUCZ is the microcontroller board, ordered separately, which is required to interface with the EVAL-ADPD4100Z-PPG evaluation board.

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D23297-6/20(0)

Rev. 0 | Page 101 of 101


型号：	ADPD4101BCBZR7
厂家：	ADI
描述：	Multimodal Sensor Front End
文件：	总101页 (文件大小：1988K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADPD4101BCBZR7 [ADI]

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