ADR391ART-REEL_技术文档

Precision Low Drift 2.048 V/2.500 V

SOT-23 Voltage References with Shutdown

a

ADR390/ADR391

PIN CONFIGURATION

5-Lead SOT-23

FEATURES

Initial Accuracy: ؎6 mV Max

Low TCV_O: 25 ppm/؇C Max

Load Regulation: 60 ppm/mA

Line Regulation: 25 ppm/V

Wide Operating Range:

(RT Sufﬁx)

SHDN

1

2

3

5

4

GND

V

ADR390/

ADR391

V

IN

2.4 V–18 V for ADR390

2.8 V–18 V for ADR391

V

OUT(SENSE)

OUT(FORCE)

Low Power: 120 ␮A Max

Shutdown to Less than 3 ␮A Max

High Output Current: 5 mA Min

Wide Temperature Range: ؊40؇C to +85؇C

Tiny SOT-23-5 Package

Table I.

Part Number

Nominal Output Voltage (V)

ADR390

ADR391

2.048

2.500

APPLICATIONS

Battery-Powered Instrumentation

Portable Medical Instruments

Data Acquisition Systems

Industrial and Process Control Systems

Hard Disk Drives

Automotive

GENERAL DESCRIPTION

The ADR390 and ADR391 are precision 2.048 V and 2.5 V

bandgap voltage references featuring high accuracy and stability

and low power consumption in a tiny footprint. Patented tempera-

ture drift curvature correction techniques minimize nonlinearity of

the voltage change with temperature. The wide operating range

and low power consumption with additional shutdown capability

make them ideal for 3 V to 5 V battery-powered applications. The

V_OUTSense Pin enables greater accuracy by supporting full Kelvin

operation in systems using very ﬁne or long circuit traces.

The ADR390 and ADR391 are micropower, Low Dropout Voltage

(LDV) devices that provide a stable output voltage from supplies as

low as 300 mV above the output voltage. They are speciﬁed over the

industrial (–40°C to +85°C) temperature range. Each is available

in the tiny 5-lead SOT-23 package.

The combination of V_OUTsense and shutdown functions also

enables a number of unique applications combining precision

reference/regulation with fault decision and over-current protec-

tion. Details are provided in the applications section.

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

ADR390/ADR391

ADR390 SPECIFICATIONS

ELECTRICAL CHARACTERISTICS ^{(@ V}_IN^{= 5 V, T}_A^{= 25؇C unless otherwise noted)}

Parameter

Symbol

Conditions

Min

Typ Max

Unit

Initial Accuracy

V_O

2.042

0.29

2.048 2.054

0.29

V

Initial Accuracy Error

Temperature Coefﬁcient

Minimum Supply Voltage Headroom

Line Regulation

V_OERR

TCV_O/°C

%

–40°C < T_A< +85°C

5

25

ppm/°C

V

_IN– V_O

300

mV

∆V_O/∆V_IN

V_IN= 2.5 V to 15 V

–40°C < T_A< +85°C

V_IN= 3 V,

10

25

ppm/V

Load Regulation

∆V_O/∆I_LOAD

I_LOAD= 0 mA to 5 mA

–40°C < T_A< +85°C

No Load

60

120

140

ppm/mA

µA

Quiescent Current

I_IN

100

–40°C < T_A< +85°C

µA

Voltage Noise

e_N

t_R

0.1 Hz to 10 Hz

5

µV p-p

µs

Turn-On Settling Time

Long-Term Stability¹

Output Voltage Hysteresis²

Ripple Rejection Ratio

Short Circuit to GND

Shutdown Supply Current

Shutdown Logic Input Current

Shutdown Logic Low

Shutdown Logic High

20

50

40

85

30

∆V_O

V_OHYS

RRR

I_SC

I_SHDN

I_LOGIC

V_INL

V_INH

1,000 Hours

ppm

dB

f

_IN= 60 Hz

mA

µA

3

500

0.8

nA

V

2.4

NOTES

¹Long-term stability, typical shift in value of output voltage at 25°C on a sample of parts subjected to operation life test of 1000 hours at 125°C. ∆V_O= V_O(t₀) –V_O

(t₁₀₀₀); V_O(t₀) = V_Oat 25°C at time 0; V_O(t₁₀₀₀) = V_Oat 25°C after 1000 hours at 125°C; ∆V_O= (V_O(t₀) – V_O(t₁₀₀₀))/V_O(t₀) × 10⁶(in ppm).

²Output Voltage Hysteresis, is defined as the change in 25°C output voltage before and after the device is cycled through temperature. +25°C to –40°C to +85°C to

+25°C. This is a typical value from a sample of parts put through such a cycle. Refer to Figures 11 and 12. V_OHYS= V_O–V_OTC; V_O= V_Oat 25°C at time 0; V_OTC= V_O

at 25°C after temperature cycle at +25°C to –40°C to +85°C to +25°C; V_OHYS= ((V_O–V_OTC)/V_O) × 106 (in ppm).

Speciﬁcations subject to change without notice.

ELECTRICAL CHARACTERISTICS ^{(@ V}_IN^{= 15 V, T}_A^{= 25؇C unless otherwise noted)}

Parameter

Symbol

Conditions

Min

Typ Max

Unit

Initial Accuracy

V_O

2.042

0.29

2.048 2.054

0.29

V

Initial Accuracy Error

Temperature Coefﬁcient

Minimum Supply Voltage Headroom

Line Regulation

V_OERR

TCV_O/°C

%

–40°C < T_A< +85°C

5

25

ppm/°C

V

_IN– V_O

300

mV

∆V_O/∆V_IN

V_IN= 2.5 V to 15 V

–40°C < T_A< +85°C

V_IN= 3 V,

10

25

ppm/V

Load Regulation

∆V_O/∆I_LOAD

I

_LOAD= 0 mA to 5 mA

–40°C < T_A< +85°C

60

120

140

ppm/mA

µA

Quiescent Current

I_IN

No Load

100

–40°C < T_A< +85°C

0.1 Hz to 10 Hz

µA

Voltage Noise

e_N

t_R

5

µV p-p

µs

Turn-On Settling Time

Long-Term Stability¹

Output Voltage Hysteresis²

Ripple Rejection Ratio

Short Circuit to GND

Shutdown Supply Current

Shutdown Logic Input Current

Shutdown Logic Low

Shutdown Logic High

20

50

40

85

30

∆V_O

V_OHYS

RRR

I_SC

I_SHDN

I_LOGIC

V_INL

V_INH

1,000 Hours

ppm

dB

f

_IN= 60 Hz

mA

µA

3

500

0.8

nA

V

V_IN– 1

V

NOTES

¹Long-term stability, typical shift in value of output voltage at 25°C on a sample of parts subjected to operation life test of 1000 hours at 125°C. ∆V_O= V_O(t₀) –V_O

(t₁₀₀₀); V_O(t₀) = V_Oat 25°C at time 0; V_O(t₁₀₀₀) = V_Oat 25°C after 1000 hours at 125°C; ∆V_O= (V_O(t₀) – V_O(t₁₀₀₀))/V_O(t₀) × 10⁶(in ppm).

²Output Voltage Hysteresis, is defined as the change in 25°C output voltage before and after the device is cycled through temperature. +25°C to –40°C to +85°C to

+25°C. This is a typical value from a sample of parts put through such a cycle. Refer to Figures 11 and 12. V_OHYS= V_O–V_OTC; V_O= V_Oat 25°C at time 0; V_OTC= V_O

at 25°C after temperature cycle at +25°C to –40°C to +85°C to +25°C; V_OHYS= ((V_O–V_OTC)/V_O) × 106 (in ppm).

Speciﬁcations subject to change without notice.

–2–

REV. 0

ADR390/ADR391

ADR391 SPECIFICATIONS

ELECTRICAL CHARACTERISTICS ^{(@ V}_IN^{= 5 V, T}_A^{= 25؇C unless otherwise noted)}

Parameter

Symbol

Conditions

Min

Typ Max

Unit

Initial Accuracy

V_O

2.494

0.24

2.5

2.506

0.24

25

V

Initial Accuracy Error

Temperature Coefﬁcient

Minimum Supply Voltage Headroom

Line Regulation

V_OERR

%

TCV_O/°C

V_IN– V_O

∆V_O/∆V_IN

–40°C < T_A< +85°C

5

ppm/°C

mV

300

V_IN= 2.8 V to 15 V

–40°C < T_A< +85°C

V_IN= 3.5 V,

I_LOAD= 0 mA to 5 mA

–40°C < T_A< +85°C

No Load

10

25

ppm/V

Load Regulation

∆V_O/∆I_LOAD

60

120

140

ppm/mA

µA

Quiescent Current

I_IN

100

–40°C < T_A< +85°C

0.1 Hz to 10 Hz

µA

Voltage Noise

e_N

t_R

5

µV p-p

µs

Turn-On Settling Time

Long-Term Stability¹

Output Voltage Hysteresis²

Ripple Rejection Ratio

Short Circuit to GND

Shutdown Supply Current

Shutdown Logic Input Current

Shutdown Logic Low

Shutdown Logic High

20

50

75

85

25

∆V_O

V_OHYS

RRR

I_SC

I_SHDN

I_LOGIC

V_INL

V_INH

1,000 Hours

ppm

dB

f

_IN= 60 Hz

mA

µA

nA

V

3

500

0.8

2.4

NOTES

¹Long-term stability, typical shift in value of output voltage at 25°C on a sample of parts subjected to operation life test of 1000 hours at 125°C. ∆V_O= V_O(t₀) –V_O

(t₁₀₀₀); V_O(t₀) = V_Oat 25°C at time 0; V_O(t₁₀₀₀) = V_Oat 25°C after 1000 hours at 125°C; ∆V_O= (V_O(t₀) – V_O(t₁₀₀₀))/V_O(t₀) × 10⁶(in ppm).

²Output Voltage Hysteresis, is defined as the change in 25°C output voltage before and after the device is cycled through temperature. +25°C to –40°C to +85°C to

+25°C. This is a typical value from a sample of parts put through such a cycle. Refer to Figures 11 and 12. V_OHYS= V_O–V_OTC; V_O= V_Oat 25°C at time 0; V_OTC= V_O

at 25°C after temperature cycle at +25°C to –40°C to +85°C to +25°C; V_OHYS= ((V_O–V_OTC)/V_O) × 106 (in ppm).

Speciﬁcations subject to change without notice.

ELECTRICAL CHARACTERISTICS ^{(@ V}_IN^{= 15 V, T}_A^{= 25؇C unless otherwise noted)}

Parameter

Symbol

Conditions

Min

Typ Max

Unit

Initial Accuracy

V_O

2.494

0.24

2.5

2.506

0.24

25

V

Initial Accuracy Error

Temperature Coefﬁcient

Minimum Supply Voltage Headroom

Line Regulation

V_OERR

TCV_O/°C

%

–40°C < T_A< +85°C

5

ppm/°C

V

_IN– V_O

300

mV

∆V_O/∆V_IN

V_IN= 2.8 V to 15 V

–40°C < T_A< +85°C

V_IN= 3.5 V,

10

25

ppm/V

Load Regulation

∆V_O/∆I_LOAD

I_LOAD= 0 mA to 5 mA

–40°C < T_A< +85°C

No Load

60

120

140

ppm/mA

µA

Quiescent Current

I_IN

100

–40°C < T_A< +85°C

µA

Voltage Noise

e_N

t_R

0.1 Hz to 10 Hz

5

µV p-p

µs

Turn-On Settling Time

Long-Term Stability¹

Output Voltage Hysteresis²

Ripple Rejection Ratio

Short Circuit to GND

Shutdown Supply Current

Shutdown Logic Input Current

Shutdown Logic Low

Shutdown Logic High

20

50

75

85

30

∆V_O

V_OHYS

RRR

I_SC

I_SHDN

I_LOGIC

V_INL

V_INH

1,000 Hours

ppm

dB

f

_IN= 60 Hz

mA

µA

3

500

0.8

nA

V

V_IN– 1

NOTES

¹Long-term stability, typical shift in value of output voltage at 25°C on a sample of parts subjected to operation life test of 1000 hours at 125°C. ∆V_O= V_O(t₀) –V_O

(t₁₀₀₀); V_O(t₀) = V_Oat 25°C at time 0; V_O(t₁₀₀₀) = V_Oat 25°C after 1000 hours at 125°C; ∆V_O= (V_O(t₀) – V_O(t₁₀₀₀))/V_O(t₀) × 10⁶(in ppm).

²Output Voltage Hysteresis, is defined as the change in 25°C output voltage before and after the device is cycled through temperature. +25°C to –40°C to +85°C to

+25°C. This is a typical value from a sample of parts put through such a cycle. Refer to Figures 11 and 12. V_OHYS= V_O–V_OTC; V_O= V_Oat 25°C at time 0; V_OTC= V_O

at 25°C after temperature cycle at +25°C to –40°C to +85°C to +25°C; V_OHYS= ((V_O–V_OTC)/V_O) × 106 (in ppm).

Speciﬁcations subject to change without notice.

REV. 0

–3–

ADR390/ADR391

ABSOLUTE MAXIMUM RATINGS*

Package Type

␪_JA*

␪

Unit

JC

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V

Shutdown Logic Level . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V

Or Supply Voltage, Whichever is Lower . . . . . . . . . . . . 18 V

Output Short-Circuit Duration to GND Observe Derating Curves

Storage Temperature Range

5-Lead SOT-23 (RT)

230

–

°C/W

*θ_JAis speciﬁed for worst-case conditions, i.e., θ_JAis speciﬁed for device in

socket for SOT packages.

RT Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Operating Temperature Range

ADR390/ADR391 . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Junction Temperature Range

RT Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational sections

of this speciﬁcation is not implied. Exposure to absolute maximum rating condi-

tions for extended periods may affect device reliability.

ORDERING GUIDE

Temperature

Range

Package

Description

Package

Option

Top

Mark

Output

Voltage

Number of

Parts

Model

ADR390ART–REEL7

ADR390ART–REEL

–40ЊC to +85ЊC

5-Lead SOT

RT-5

R0A

2.048

3,000

10,000

ADR391ART–REEL7

ADR391ART–REEL

–40ЊC to +85ЊC

5-Lead SOT

RT-5

R1A

2.500

3,000

10,000

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the ADR390/ADR391 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–4–

REV. 0

Typical Performance Characteristics–ADR390/ADR391

2.054

2.052

2.050

2.048

2.046

2.044

2.042

140

SAMPLE 1

120

+85؇C

100

+25؇C

SAMPLE 2

؊40؇C

80

60

SAMPLE 3

40

؊40

؊15

10

35

60

85

2.5

5.0

7.5

10.0

12.5

15.0

INPUT VOLTAGE – V

TEMPERATURE – ؇C

Figure 4. ADR391 Supply Current vs. Input Voltage

Figure 1. ADR390 Output Voltage vs. Temperature

2.506

40

I = 0mA TO 5mA

L

2.504

35

30

25

20

15

10

SAMPLE 1

2.502

V

= 3.0V

= 5.0V

IN

SAMPLE 2

2.500

V

IN

2.498

SAMPLE 3

2.496

2.494

؊40

؊15

10

35

60

85

؊40

؊15

10

35

60

85

TEMPERATURE – ؇C

Figure 2. ADR391 Output Voltage vs. Temperature

Figure 5. ADR390 Load Regulation vs. Temperature

140

40

I = 0mA TO 5mA

L

35

30

25

20

15

10

120

+85؇C

V

= 3.5V

= 5.0V

100

IN

+25؇C

؊40؇C

V

IN

80

60

40

2.5

5.0

7.5

10.0

12.5

15.0

؊40

؊15

10

35

60

85

INPUT VOLTAGE – V

TEMPERATURE – ؇C

Figure 3. ADR390 Supply Current vs. Input Voltage

Figure 6. ADR391 Load Regulation vs. Temperature

REV. 0

–5–

ADR390/ADR391

5

0.8

0.6

0.4

0.2

0

V

= 2.5V TO 15V

IN

4

3

2

+85؇C

+25؇C

؊40؇C

1

0

؊40

؊15

10

35

60

85

0

1

2

3

4

5

LOAD CURRENT – mA

TEMPERATURE – ؇C

Figure 7. ADR390 Line Regulation vs. Temperature

Figure 10. ADR391 Minimum Input-Output Voltage

Differential vs. Load Current

60

5

TEMPERATURE: +25؇C

؊40؇C

+85؇C

+25؇C

V

= 2.8V TO 15V

IN

50

40

30

20

4

3

2

1

0

10

0

؊40

؊15

10

35

60

85

؊0.24 ؊0.18 ؊0.12 ؊0.06

0

0.06 0.12 0.18 0.24 0.30

TEMPERATURE – ؇C

V

DEVIATION – mV

OUT

Figure 8. ADR391 Line Regulation vs. Temperature

Figure 11. ADR390 V_OUTHysteresis Distribution

70

0.8

TEMPERATURE: +25؇C

؊40؇C

+85؇C

+25؇C

60

50

40

30

20

10

0

0.6

؊40؇C

0.4

+85؇C

+25؇C

0.2

0

1

2

3

4

5

؊0.56

؊0.41

؊0.26

؊0.11

0.04

0.19

0.34

LOAD CURRENT – mA

V

DEVIATION – mV

OUT

Figure 12. ADR391 V_OUTHysteresis Distribution

Figure 9. ADR390 Minimum Input-Output Voltage

Differential vs. Load Current

–6–

REV. 0

ADR390/ADR391

1k

0

V

= 5V

IN

C

= 0␮F

BYPASS

LINE

0.5V/DIV

INTERRUPTION

ADR391

ADR390

V

OUT

1V/DIV

0

100

10

100

FREQUENCY – Hz

1k

10k

TIME – 10␮s/DIV

Figure 13. Voltage Noise Density vs. Frequency

Figure 16. ADR391 Line Transient Response

0

C

= 0.1␮F

BYPASS

0.5V/DIV

LINE

INTERRUPTION

V

OUT

1V/DIV

0

TIME – 10␮s/DIV

TIME – 10ms/DIV

Figure 14. ADR390 Voltage Noise 10 Hz to 10 kHz

Figure 17. ADR391 Line Transient Response

0

C

= 0nF

L

V

OUT

V

ON

LOAD OFF

LOAD

0

TIME – 10ms/DIV

TIME – 200␮s/DIV

Figure 15. ADR391 Voltage Noise 10 Hz to 10 kHz

Figure 18. ADR391 Load Transient Response

REV. 0

–7–

ADR390/ADR391

0

C

= 1nF

V

= 15V

L

IN

V

0

OUT

V

5V/DIV

2V/DIV

IN

LOAD OFF

V

OUT

V

ON

LOAD

TIME – 200␮s/DIV

TIME – 40␮s/DIV

Figure 19. ADR391 Load Transient Response

Figure 22. ADR391 Turn-Off Response at 15 V

0

C

= 100nF

C

= 0.1␮F

L

BYPASS

V

OUT

2V/DIV

5V/DIV

V

OUT

LOAD OFF

V

ON

LOAD

V

IN

TIME – 200␮s/DIV

Figure 20. ADR391 Load Transient Response

Figure 23. ADR391 Turn-On/Turn-Off Response at 5 V

0

V

= 15V

R

= 500⍀

IN

L

0

5V/DIV

2V/DIV

5V/DIV

V

OUT

V

IN

V

OUT

V

IN

TIME – 20␮s/DIV

TIME – 200␮s/DIV

Figure 21. ADR391 Turn-On Response Time at 15 V

Figure 24. ADR391 Turn-On/Turn-Off Response at 5 V

–8–

REV. 0

ADR390/ADR391

THEORY OF OPERATION

0

Bandgap references are the high-performance solution for low

supply voltage and low power voltage reference applications,

and the ADR390/ADR391 is no exception. But the uniqueness

of this product lies in its architecture. By observing Figure 28,

the zero TC bandgap voltage is referenced to the output, not to

ground. The bandgap cell consists of the pnp pair Q51 and Q52,

running at unequal current densities. The difference in V_BE

results in a voltage with a positive TC which is ampliﬁed up by

R

C

= 500⍀

= 100nF

L

2V/DIV

5V/DIV

V

OUT

V

IN

R58

R54

2 ×

the ratio of

. This PTAT voltage, combined with V_BE’s

of Q51 and Q52 produce the stable bandgap voltage.

Reduction in the bandgap curvature is performed by the ratio of

the two resistors R44 and R59. Precision laser trimming and

other patented circuit techniques are used to further enhance

the drift performance.

TIME – 200␮s/DIV

Figure 25. ADR391 Turn-On/Turn-Off Response at 5 V

V

IN

80

60

40

SHDN

FORCE

20

0

SENSE

R59 R44

R58

TESTPAD

؊20

؊40

R49

Q52

؊60

R54

Q51

R53

؊80

TESTPAD

GROUND

؊100

TESTPAD

2RS

؊120

R48

10

100

1k

10k

100k

1M

FREQUENCY – Hz

R60

R61

Figure 26. Ripple Rejection vs. Frequency

Figure 28. Simpliﬁed Schematic

Device Power Dissipation Considerations

100

The ADR390/ADR391 is capable of delivering load currents to

5 mA with an input voltage that ranges from 2.8 V (ADR391 only)

to 15 V. When this device is used in applications with large input

voltages, care should be taken to avoid exceeding the speciﬁed maxi-

mum power dissipation or junction temperature that could result in

premature device failure. The following formula should be used to

calculate a device’s maximum junction temperature or dissipation:

90

80

70

60

50

40

30

20

10

0

C

= 0␮F

L

T_J−T_A

P_D=

θ_JA

C

= 0.1␮F

L

In this equation, T_Jand T_Aare, respectively, the junction and

ambient temperatures, P_Dis the device power dissipation, and

C

= 1␮F

L

θ

_JAis the device package thermal resistance.

10

100

1k

10k

100k

1M

FREQUENCY – Hz

Shutdown Mode Operation

The ADR390/ADR391 includes a shutdown feature that is TTL/

CMOS level compatible. A logic LOW or a zero volt condition on

the SHDN pin is required to turn the device off. During shutdown,

the output of the reference becomes a high impedance state where

its potential would then be determined by external circuitry. If the

shutdown feature is not used, the SHDN pin should be connected

to V_IN(Pin 2).

Figure 27. Output Impedance vs. Frequency

REV. 0

–9–

ADR390/ADR391

APPLICATIONS

Membrane Switch Controlled Power Supply

U2, either the external load of U1 or R1 must provide a path for

this current. If the U1 minimum load is not well deﬁned, the

resistor R1 should be used, set to a value that will conservatively

pass 600 µA of current with the applicable V_OUT1across it. Note

that the two U1 and U2 reference circuits are locally treated as

macrocells, each having its own bypasses at input and output for best

stability. Both U1 and U2 in this circuit can source dc currents up to

their full rating. The minimum input voltage, V_S,is determined by

the sum of the outputs, V_OUT2, plus the dropout voltage of U2.

The ADR390/ADR391 can operate as a low dropout power

supply in hand-held instrumentation. In the following circuit, a

membrane ON/OFF switch is used to control the operation of the

reference. During an initial power-on condition, the SHDN pin is

held to GND. Recall that this condition disables the output (read:

three-state). When the membrane ON switch is pressed, the SHDN

pin assumes and remains at the same potential as V_IN, via the 10 kΩ

resistor thus enabling the output. When the membrane OFF switch

is pressed, the SHDN pin is momentarily connected to GND which

disables the ADR390/ADR391 output once again.

A related variation on stacking two three-terminal references is

shown in the following ﬁgure where U1, an ADR391, is stacked

with a two-terminal reference diode such as the AD589. Similar

to the all three-terminal stacked references mentioned earlier,

the two individual terminal voltage outputs of D1 and U1 are

1.235 V and 2.5 V, respectively. Thus V_OUT2is the sum of D1 and

U1, or 3.735 V. When using two-terminal reference diodes such

as D1, the rated minimum and maximum device currents must

be observed, and the maximum load current from V_OUT1can

V

IN

ADR39x

10k⍀

V

1␮F

TANT

OUT

ON

be no greater than the current set up by R1 and V_O(U1)

.

OFF

V

IN

2

V

IN

> V

OUT2

+0.15V

V

U1

OUT2

3.735V

5V

1

4

ADR39x

C1

0.1␮F

R1

4.99k⍀

C2

1␮F

V

(U1)

(D1)

O

Figure 29. Membrane Switch Controlled Power Supply

5

(SEE TEXT)

Stacking Reference ICs for Arbitrary Outputs

V

OUT1

Some applications may require two reference voltage sources which

are a combined sum of standard outputs. The following circuit

shows how this “stacked output” reference can be implemented:

1.235V

C3

1␮F

D1

O

AD589

V

OUT

IN

COMMON

OUTPUT TABLE

U1/U2

V

(V)

V

(V)

OUT1

OUT2

Figure 31. Stacking Voltage References with the ADR390/

ADR391

ADR390/ADR390

ADR391/ADR391

2.048

2.5

4.096

5.0

V

IN

2

V

IN

> V

+0.15V

A Negative Precision Reference without Precision Resistors

In many current-output CMOS DAC applications where the

output signal voltage must be of the same polarity as the reference

voltage, it is often required to reconﬁgure a current-switching

DAC into a voltage-switching DAC through the use of a 1.25 V

reference, an op amp, and a pair of resistors. Using a current-

switching DAC directly requires the need for an additional

operational ampliﬁer at the output to reinvert the signal. A negative

voltage reference is then desirable from the point that an additional

operational ampliﬁer is not required for either reinversion (current-

switching mode) or ampliﬁcation (voltage switching mode) of the

DAC output voltage. In general, any positive voltage reference can

be converted into a negative voltage reference through the use of an

operational ampliﬁer and a pair of matched resistors in an inverting

conﬁguration. The disadvantage to this approach is that the largest

single source of error in the circuit is the relative matching of the

resistors used.

OUT2

C1

0.1␮F

U2

1

V

4

ADR39x

OUT2

(SEE TABLE)

C2

1␮F

V

(U2)

(U1)

O

5

2

C3

0.1␮F

U1

V

4

OUT1

ADR39x

R1

3.9k⍀

(SEE TABLE)

C4

1␮F

V

O

5

(SEE TEXT)

V

IN

OUT

COMMON

Figure 30. Stacking Voltage References with the ADR390/

ADR391

Two reference ICs are used, fed from a common unregulated

input, V_IN. The outputs of the individual ICs are simply connected

in series which provides two output voltages V_OUT1and V_OUT2

.

The following circuit avoids the need for tightly matched resis-

tors with the use of an active integrator circuit. In this circuit,

the output of the voltage reference provides the input drive for

the integrator. The integrator, to maintain circuit equilibrium,

adjusts its output to establish the proper relationship between

the reference’s V_OUTand GND. Thus, any negative output

voltage desired can be chosen by simply substituting for the

appropriate reference IC. The shutdown feature is maintained

in the circuit with the simple addition of a PNP transistor and

V_OUT1is the terminal voltage of U1, while V_OUT2is the sum of this

voltage and the terminal voltage of U2. U1 and U2 are simply

chosen for the two voltages that supply the required outputs (see

Output Table). For example, if both U1 and U2 are ADR391’s,

V_OUT1is 2.5 V and V_OUT2is 5.0 V.

While this concept is simple, a precaution is in order. Since the

lower reference circuit must sink a small bias current from U2,

plus the base current from the series PNP output transistor in

–10–

REV. 0

ADR390/ADR391

a 10 kΩ resistor. A precaution should be noted with this approach:

although rail-to-rail output ampliﬁers work best in the application,

these operational ampliﬁers require a ﬁnite amount (mV) of head-

room when required to provide any load current. The choice for

the circuit’s negative supply should take this issue into account.

High-Power Performance with Current Limit

In some cases, the user may want higher output current delivered

to a load and still achieve better than 0.5% accuracy out of the

ADR390/ADR391. The accuracy for a reference is normally

speciﬁed on the data sheet with no load. However, the output

voltage changes with load current.

V

IN

The circuit below provides high current without compromising

the accuracy of the ADR390/ADR391. The series pass transis-

tor Q1 provides up to 1 A load current. The ADR390/ADR391

delivers only the base drive to Q1 through the force pin. The

sense pin of the ADR390/ADR391 is a regulated output and is

connected to the load.

10k⍀

SHDN

TTL/CMOS

2N3906

2

V

OUT

V

S

1␮F

+5V

1k⍀

1␮F

1

SHDN

4

OUT

ADR39x

GND

100⍀

A1

5

R1

؊V

REF

10k⍀

4.7k⍀

100k⍀

U1

V

IN

؊5V

GND

SHDN

A1 = 1/2 OP295,

1/2 OP291

V

IN

Figure 32. A Negative Precision Voltage Reference Uses

No Precision Resistors

V

Q1

Q2N4921

OUT (FORCE)

V

OUT (SENSE)

Q2

Q2N2222

Precision Current Source

ADR390/ADR391

R

S

Many times in low-power applications, the need arises for a preci-

sion current source that can operate on low supply voltages. As

shown in the following ﬁgure, the ADR390/ADR391 can be conﬁg-

ured as a precision current source. The circuit conﬁguration illus-

trated is a ﬂoating current source with a grounded load. The

reference’s output voltage is bootstrapped across R_SET, which sets

the output current into the load. With this conﬁguration, circuit

precision is maintained for load currents in the range from the

reference’s supply current, typically 90 µA to approximately 5 mA.

I

L

Figure 34. ADR390/ADR391 for High-Power Performance

with Current Limit

A similar circuit function can also be achieved with the Darlington

transistor conﬁguration, see Figure 35.

V

IN

R1

4.7k⍀

U1

V

IN

SHDN

GND

V

OUT

SHDN

ADR39x

V

IN

Q2N2222

V

OUT

V

S

V

Q1

OUT (FORCE)

Q2

V

OUT (SENSE)

R

1

R

Q2N4921

1

GND

ADR390/ADR391

1␮F

R

S

R

SET

I

SY

}

ADJUST

P

1

R

L

I

OUT

R

L

Figure 35. ADR390/ADR391 High Output Current with

Darlington Drive Conﬁguration

The transistor Q2 protects Q1 during short circuit limit faults by

robbing its base drive. The maximum current is I_LMAX≈ 0.6 V/R_S.

Figure 33. A Precision Current Source

REV. 0

–11–

ADR390/ADR391

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

5-Lead SOT-23

(RT Sufﬁx)

0.1181 (3.00)

0.1102 (2.80)

5

1

4

3

0.1181 (3.00)

0.1024 (2.60)

0.0669 (1.70)

0.0590 (1.50)

2

PIN 1

0.0374 (0.95) BSC

0.0748 (1.90)

BSC

0.0079 (0.20)

0.0031 (0.08)

0.0512 (1.30)

0.0354 (0.90)

0.0571 (1.45)

0.0374 (0.95)

10؇

0؇

SEATING

PLANE

0.0197 (0.50)

0.0138 (0.35)

0.0059 (0.15)

0.0019 (0.05)

0.0217 (0.55)

0.0138 (0.35)

–12–

REV. 0


型号：	ADR391ART-REEL
厂家：	ADI
描述：	IC 1-OUTPUT THREE TERM VOLTAGE REFERENCE, 2.5 V, PDSO5, SOT-23, 5 PIN, Voltage Reference 光电二极管输出元件
文件：	总12页 (文件大小：149K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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