ADR425BRZ-REEL7 [ADI]
Ultraprecision, Low Noise, 2.048 V/2.500 V/ 3.00 V/5.00 V XFET® Voltage References; 超精密，低噪声， 2.048 V / 2.500 V / 3.00 V / 5.00 V XFET®电压基准
| 型号： | ADR425BRZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | Ultraprecision, Low Noise, 2.048 V/2.500 V/ 3.00 V/5.00 V XFET® Voltage References |
| 文件： | 总24页 (文件大小：392K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultraprecision, Low Noise, 2.048 V/2.500 V/
3.00 V/5.00 V XFET® Voltage References
ADR420/ADR421/ADR423/ADR425
FEATURES
PIN CONFIGURATION
Low noise (0.1 Hz to 10 Hz)
ADR420: 1.75 μV p-p
ADR421: 1.75 μV p-p
TP
1
2
8
TP
NIC
V
ADR420/
ADR421/
ADR423/
ADR425
V
7
6
IN
NIC
3
4
OUT
TOP VIEW
(Not to Scale)
ADR423: 2.0 μV p-p
GND
5
TRIM
ADR425: 3.4 μV p-p
NIC = NO INTERNAL CONNECTION
TP = TEST PIN (DO NOT CONNECT)
Low temperature coefficient: 3 ppm/°C
Long-term stability: 50 ppm/1000 hours
Load regulation: 70 ppm/mA
Line regulation: 35 ppm/V
Low hysteresis: 40 ppm typical
Wide operating range
ADR420: 4 V to 18 V
ADR421: 4.5 V to 18 V
ADR423: 5 V to 18 V
Figure 1. 8-Lead SOIC, 8-Lead MSOP
GENERAL DESCRIPTION
The ADR42x are a series of ultraprecision, second generation
eXtra implanted junction FET (XFET) voltage references
featuring low noise, high accuracy, and excellent long-term
stability in SOIC and MSOP footprints.
Patented temperature drift curvature correction technique and
XFET technology minimize nonlinearity of the voltage change
with temperature. The XFET architecture offers superior
accuracy and thermal hysteresis to the band gap references. It
also operates at lower power and lower supply headroom than
the buried Zener references.
ADR425: 7 V to 18 V
Quiescent current: 0.5 mA maximum
High output current: 10 mA
Wide temperature range: −40°C to +125°C
APPLICATIONS
Precision data acquisition systems
High resolution converters
Battery-powered instrumentation
Portable medical instruments
Industrial process control systems
Precision instruments
The superb noise and the stable and accurate characteristics
of the ADR42x make them ideal for precision conversion
applications such as optical networks and medical equipment.
The ADR42x trim terminal can also be used to adjust the out-
put voltage over a ±±.ꢀ5 range without compromising any
other performance. The ADR42x series voltage references
offer two electrical grades and are specified over the extended
industrial temperature range of −4±°C to +12ꢀ°C. Devices have
8-lead SOIC or 3±5 smaller, 8-lead MSOP packages.
Optical network control circuits
ADR42x PRODUCTS
Table 1.
Initial Accuracy
%
Output Voltage, VOUT (V)
Model
mV
1, 3
1, 3
1.5, 4
2, 6
Temperature Coefficient (ppm/°C)
ADR420
ADR421
ADR423
ADR425
2.048
2.50
3.00
5.00
0.05, 0.15
0.04, 0.12
0.04, 0.13
0.04, 0.12
3, 10
3, 10
3, 10
3, 10
Rev. I
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2001–2011 Analog Devices, Inc. All rights reserved.
ADR420/ADR421/ADR423/ADR425
TABLE OF CONTENTS
Features .............................................................................................. 1
Device Power Dissipation Considerations.............................. 16
Basic Voltage Reference Connections ..................................... 16
Noise Performance..................................................................... 16
Turn-On Time ............................................................................ 16
Applications..................................................................................... 17
Output Adjustment .................................................................... 17
Applications....................................................................................... 1
Pin Configuration............................................................................. 1
General Description......................................................................... 1
ADR42x Products............................................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
ADR42± Electrical Specifications............................................... 3
ADR421 Electrical Specifications............................................... 4
ADR423 Electrical Specifications............................................... ꢀ
ADR42ꢀ Electrical Specifications............................................... 6
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 1ꢀ
Theory of Operation ...................................................................... 16
Reference for Converters in Optical Network Control
Circuits......................................................................................... 17
High Voltage Floating Current Source.................................... 17
Kelvin Connections.................................................................... 18
Dual-Polarity References........................................................... 18
Programmable Current Source ................................................ 19
Programmable DAC Reference Voltage .................................. 19
Precision Voltage Reference for Data Converters.................. 2±
Precision Boosted Output Regulator....................................... 2±
Outline Dimensions....................................................................... 21
Ordering Guide .......................................................................... 22
REVISION HISTORY
5/11—Rev. H to Rev. I
7/04—Rev. D to Rev. E
Added Endnote 1 in Table 2............................................................ 4
Added Endnote 1 in Table 3............................................................ ꢀ
Added Endnote 1 in Table 4............................................................ 6
Added Endnote 1 in Table ꢀ............................................................ 7
Deleted A Negative Precision Reference Without Precision
Resistors Section ............................................................................. 17
Deleted Figure 42; Renumbered Sequentially ............................ 17
Updated Outline Dimensions....................................................... 21
Changes to Ordering Guide .......................................................... 22
Changes to Ordering Guide.............................................................ꢀ
3/04—Rev. C to Rev. D
Changes to Table I .............................................................................1
Changes to Ordering Guide.............................................................4
Updated Outline Dimensions....................................................... 16
1/03—Rev. B to Rev. C
Changed Mini_SOIC to MSOP........................................Universal
Changes to Ordering Guide.............................................................4
Corrections to Y-axis labels in TPCs 21 and 24 ............................9
Enhancement to Figure 13 ............................................................ 1ꢀ
Updated Outline Dimensions....................................................... 16
6/07—Rev. G to Rev. H
Changes to Table 2............................................................................ 3
Changes to Table 3............................................................................ 4
Changes to Table 4............................................................................ ꢀ
Changes to Table ꢀ............................................................................ 6
Updated Outline Dimensions....................................................... 21
Changes to Ordering Guide .......................................................... 22
3/02—Rev. A to Rev. B
Edits to Ordering Guide ...................................................................4
Deletion of Precision Voltage Regulator section........................ 1ꢀ
Addition of Precision Boosted Output Regulator section ....... 1ꢀ
Addition of Figure 13..................................................................... 1ꢀ
6/05—Rev. F to Rev. G
Changes to Table 1............................................................................ 1
Changes to Ordering Guide .......................................................... 22
10/01—Rev. 0 to Rev. A
Addition of ADR423 and ADR42ꢀ to
ADR42±/ADR421...............................................................Universal
2/05—Rev. E to Rev. F
Updated Format..................................................................Universal
Updated Outline Dimensions....................................................... 21
Changes to Ordering Guide .......................................................... 22
5/01—Revision 0: Initial Version
Rev. I | Page 2 of 24
ADR420/ADR421/ADR423/ADR425
SPECIFICATIONS
ADR420 ELECTRICAL SPECIFICATIONS
VIN = ꢀ.± V to 1ꢀ.± V, TA = 2ꢀ°C, unless otherwise noted.
Table 2.
Parameter
OUTPUT VOLTAGE
A Grade
Symbol
Conditions
Min
Typ
Max
Unit
VOUT
2.045
2.047
2.048
2.048
2.051
2.049
V
V
B Grade
INITIAL ACCURACY1
VOUTERR
A Grade
−3
−0.15
−1
+3
+0.15
+1
mV
%
mV
%
B Grade
−0.05
+0.05
TEMPERATURE COEFFICIENT
A Grade
TCVOUT
−40°C < TA < +125°C
2
1
10
3
ppm°C
ppm/°C
V
B Grade
SUPPLY VOLTAGE HEADROOM
LINE REGULATION
VIN − VOUT
2
∆VOUT/∆VIN
VIN = 5 V to 18 V,
−40°C < TA < +125°C
10
35
70
ppm/V
LOAD REGULATION
∆VOUT/∆IL
IIN
IL = 0 mA to 10 mA,
−40°C < TA < +125°C
ppm/mA
QUIESCENT CURRENT
No load
390
500
600
μA
μA
−40°C < TA < +125°C
0.1 Hz to 10 Hz
1 kHz
VOLTAGE NOISE
eN p-p
eN
1.75
60
μV p-p
nV/√Hz
μs
VOLTAGE NOISE DENSITY
TURN-ON SETTLING TIME
LONG-TERM STABILITY
OUTPUT VOLTAGE HYSTERESIS
RIPPLE REJECTION RATIO
SHORT CIRCUIT TO GND
tR
10
∆VOUT
VOUT_HYS
RRR
ISC
1000 hours
fIN = 1 kHz
50
ppm
ppm
dB
40
−75
27
mA
1 Initial accuracy does not include shift due to solder heat effect.
Rev. I | Page 3 of 24
ADR420/ADR421/ADR423/ADR425
ADR421 ELECTRICAL SPECIFICATIONS
VIN = ꢀ.± V to 1ꢀ.± V, TA = 2ꢀ°C, unless otherwise noted.
Table 3.
Parameter
OUTPUT VOLTAGE
A Grade
Symbol
Conditions
Min
Typ
Max
Unit
VOUT
2.497
2.499
2.500
2.500
2.503
2.501
V
V
B Grade
INITIAL ACCURACY1
VOUTERR
A Grade
−3
−0.12
−1
+3
+0.12
+1
mV
%
mV
%
B Grade
−0.04
+0.04
TEMPERATURE COEFFICIENT
A Grade
B Grade
TCVOUT
−40°C < TA < +125°C
2
1
10
3
ppm/°C
ppm/°C
V
SUPPLY VOLTAGE HEADROOM
LINE REGULATION
VIN − VOUT
2
∆VOUT/∆VIN
VIN = 5 V to 18 V,
−40°C < TA < +125°C
10
35
70
ppm/V
LOAD REGULATION
∆VOUT/∆IL
IIN
IL = 0 mA to 10 mA,
−40°C < TA < +125°C
ppm/mA
QUIESCENT CURRENT
No load
390
500
600
μA
μA
−40°C < TA < +125°C
0.1 Hz to 10 Hz
1 kHz
VOLTAGE NOISE
eN p-p
eN
1.75
80
μV p-p
nV/√Hz
μs
VOLTAGE NOISE DENSITY
TURN-ON SETTLING TIME
LONG-TERM STABILITY
OUTPUT VOLTAGE HYSTERESIS
RIPPLE REJECTION RATIO
SHORT CIRCUIT TO GND
tR
10
∆VOUT
VOUT_HYS
RRR
ISC
1000 hours
fIN = 1 kHz
50
ppm
ppm
dB
40
−75
27
mA
1 Initial accuracy does not include shift due to solder heat effect.
Rev. I | Page 4 of 24
ADR420/ADR421/ADR423/ADR425
ADR423 ELECTRICAL SPECIFICATIONS
VIN = ꢀ.± V to 1ꢀ.± V, TA = 2ꢀ°C, unless otherwise noted.
Table 4.
Parameter
OUTPUT VOLTAGE
A Grade
Symbol
Conditions
Min
Typ
Max
Unit
VOUT
2.996
2.9985
3.000
3.000
3.004
3.0015
V
V
B Grade
INITIAL ACCURACY1
VOUTERR
A Grade
−4
+4
mV
%
mV
%
−0.13
−1.5
−0.04
+0.13
+1.5
+0.04
B Grade
TEMPERATURE COEFFICIENT
A Grade
TCVOUT
−40°C < TA < +125°C
2
1
10
3
ppm/°C
ppm/°C
V
B Grade
SUPPLY VOLTAGE HEADROOM
LINE REGULATION
VIN − VOUT
2
∆VOUT/∆VIN
VIN = 5 V to 18 V,
−40°C < TA < +125°C
10
35
70
ppm/V
LOAD REGULATION
∆VOUT/∆IL
IIN
IL = 0 mA to 10 mA,
−40°C < TA < +125°C
ppm/mA
QUIESCENT CURRENT
No load
390
500
600
μA
μA
−40°C < TA < +125°C
0.1 Hz to 10 Hz
1 kHz
VOLTAGE NOISE
eN p-p
eN
2
μV p-p
nV/√Hz
μs
VOLTAGE NOISE DENSITY
TURN-ON SETTLING TIME
LONG-TERM STABILITY
OUTPUT VOLTAGE HYSTERESIS
RIPPLE REJECTION RATIO
SHORT CIRCUIT TO GND
90
10
50
40
−75
27
tR
∆VOUT
VOUT_HYS
RRR
ISC
1000 hours
fIN = 1 kHz
ppm
ppm
dB
mA
1 Initial accuracy does not include shift due to solder heat effect.
Rev. I | Page 5 of 24
ADR420/ADR421/ADR423/ADR425
ADR425 ELECTRICAL SPECIFICATIONS
VIN = 7.± V to 1ꢀ.± V, TA = 2ꢀ°C, unless otherwise noted.
Table 5.
Parameter
OUTPUT VOLTAGE
A Grade
Symbol
Conditions
Min
Typ
Max
Unit
VOUT
4.994
4.998
5.000
5.000
5.006
5.002
V
V
B Grade
INITIAL ACCURACY1
VOUTERR
A Grade
−6
−0.12
−2
+6
+0.12
+2
mV
%
mV
%
B Grade
−0.04
+0.04
TEMPERATURE COEFFICIENT
A Grade
B Grade
TCVOUT
−40°C < TA < +125°C
2
1
10
3
ppm/°C
ppm/°C
V
SUPPLY VOLTAGE HEADROOM
LINE REGULATION
VIN − VO
2
∆VO/∆VIN
VIN = 7 V to 18 V,
−40°C < TA < +125°C
10
35
70
ppm/V
LOAD REGULATION
∆VO/∆IL
IIN
IL = 0 mA to 10 mA,
−40°C < TA < +125°C
ppm/mA
QUIESCENT CURRENT
No load
390
500
600
μA
μA
−40°C < TA < +125°C
0.1 Hz to 10 Hz
1 kHz
VOLTAGE NOISE
eN p-p
eN
3.4
110
10
μV p-p
nV/√Hz
μs
VOLTAGE NOISE DENSITY
TURN-ON SETTLING TIME
LONG-TERM STABILITY
OUTPUT VOLTAGE HYSTERESIS
RIPPLE REJECTION RATIO
SHORT CIRCUIT TO GND
tR
∆VO
VO_HYS
RRR
ISC
1000 hours
fIN = 1 kHz
50
ppm
ppm
dB
40
−75
27
mA
1 Initial accuracy does not include shift due to solder heat effect.
Rev. I | Page 6 of 24
ADR420/ADR421/ADR423/ADR425
ABSOLUTE MAXIMUM RATINGS
These ratings apply at 2ꢀ°C, unless otherwise noted.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for devices soldered in the circuit board for surface-
mount packages.
Table 6.
Parameter
Supply Voltage
Rating
18 V
Output Short-Circuit Duration to GND
Storage Temperature Range
Operating Temperature Range
JunctionTemperature Range
Lead Temperature (Soldering, 60 sec)
Indefinite
Table 7.
Package Type
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
θJA
Unit
°C/W
°C/W
8-Lead MSOP (RM)
8-Lead SOIC (R)
190
130
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. I | Page 7 of 24
ADR420/ADR421/ADR423/ADR425
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
TP
1
2
8
TP
NIC
V
ADR420/
ADR421/
ADR423/
ADR425
V
7
6
IN
NIC
3
4
OUT
TOP VIEW
(Not to Scale)
GND
5
TRIM
NIC = NO INTERNAL CONNECTION
TP = TEST PIN (DO NOT CONNECT)
Figure 2. 8-Lead SOIC, 8-Lead MSOP Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
1, 8
TP
Test Pin. There are actual connections in TP pins, but they are reserved for factory testing purposes. Users should not
connect anything to TP pins; otherwise, the device may not function properly.
2
VIN
Input Voltage.
3, 7
4
5
NIC
GND
TRIM
No Internal Connect. NICs have no internal connections.
Ground Pin = 0 V.
Trim Terminal. It can be used to adjust the output voltage over a 0.5% range without affecting the temperature
coefficient.
6
VOUT
Output Voltage.
Rev. I | Page 8 of 24
ADR420/ADR421/ADR423/ADR425
TYPICAL PERFORMANCE CHARACTERISTICS
5.0025
5.0023
2.0495
2.0493
2.0491
2.0489
2.0487
2.0485
2.0483
2.0481
2.0479
2.0477
2.0475
5.0021
5.0019
5.0017
5.0015
5.0013
5.0011
5.0009
5.0007
5.0005
–40
–10
20
50
80
110 125
–40
–10
20
50
80
110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 3. ADR420 Typical Output Voltage vs. Temperature
Figure 6. ADR425 Typical Output Voltage vs. Temperature
2.5015
0.55
2.5013
2.5011
2.5009
2.5007
2.5005
2.5003
2.5001
2.4999
2.4997
2.4995
0.50
0.45
0.40
0.35
0.30
0.25
+125°C
+25°C
–40°C
–40
–10
20
50
80
110 125
4
6
8
10
12
14
15
TEMPERATURE (°C)
INPUT VOLTAGE (V)
Figure 4. ADR421 Typical Output Voltage vs. Temperature
Figure 7. ADR420 Supply Current vs. Input Voltage
0.55
0.50
0.45
0.40
0.35
0.30
0.25
3.0010
3.0008
3.0006
3.0004
3.0002
3.0000
2.9998
2.9996
2.9994
2.9992
2.9990
+125°C
+25°C
–40°C
–40
–10
20
50
80
110 125
4
6
8
10
12
14
15
TEMPERATURE (°C)
INPUT VOLTAGE (V)
Figure 5. ADR423 Typical Output Voltage vs. Temperature
Figure 8. ADR421 Supply Current vs. Input Voltage
Rev. G | Page 9 of 24
ADR420/ADR421/ADR423/ADR425
0.55
70
60
50
40
30
20
10
0
I
= 0mA TO 5mA
L
0.50
+125°C
0.45
V
= 5V
IN
0.40
+25°C
V
= 6.5V
0.35
IN
–40°C
0.30
0.25
4
6
8
10
12
14 15
–40
–10
20
50
80
110 125
INPUT VOLTAGE (V)
TEMPERATURE (°C)
Figure 9. ADR423 Supply Current vs. Input Voltage
Figure 12. ADR421 Load Regulation vs. Temperature
0.55
0.50
0.45
0.40
0.35
0.30
0.25
70
60
50
40
30
20
10
0
I
= 0mA TO 10mA
L
+125°C
V
= 7V
IN
+25°C
–40°C
V
= 15V
IN
6
8
10
12
14
15
–40
–10
20
50
80
110 125
INPUT VOLTAGE (V)
TEMPERATURE (°C)
Figure 10. ADR425 Supply Current vs. Input Voltage
Figure 13. ADR423 Load Regulation vs. Temperature
70
60
50
40
30
20
10
0
35
30
25
20
15
10
5
V
= 15V
IN
= 0mA TO 10mA
I
= 0mA TO 5mA
L
I
L
V
= 4.5V
IN
V
= 6V
IN
0
–40
–40
–10
20
50
80
110 125
–10
20
50
80
110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. ADR420 Load Regulation vs. Temperature
Figure 14. ADR425 Load Regulation vs. Temperature
Rev. I | Page 10 of 24
ADR420/ADR421/ADR423/ADR425
6
5
4
3
2
1
14
12
10
8
V
= 4.5V TO 15V
V
= 7.5V TO 15V
IN
IN
6
4
2
0
–40
0
–40
–10
20
50
80
110 125
–10
20
50
80
110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15. ADR420 Line Regulation vs. Temperature
Figure 18. ADR425 Line Regulation vs. Temperature
6
5
4
3
2
1
2.5
2.0
1.5
1.0
0.5
0
V
= 5V TO 15V
IN
–40°C
+25°C
+85°C
0
–40
–10
20
50
80
110 125
0
1
2
3
4
5
TEMPERATURE (°C)
LOAD CURRENT (mA)
Figure 16. ADR421 Line Regulation vs. Temperature
Figure 19. ADR420 Minimum Input/Output Voltage
Differential vs. Load Current
9
8
7
6
5
4
3
2
1
2.5
2.0
1.5
1.0
0.5
0
V
= 5V TO 15V
IN
–40°C
+25°C
+125°C
0
–40
–10
20
50
80
110
0
1
2
3
4
5
TEMPERATURE (°C)
LOAD CURRENT (mA)
Figure 17. ADR423 Line Regulation vs. Temperature
Figure 20. ADR421 Minimum Input/Output Voltage
Differential vs. Load Current
Rev. I | Page 11 of 24
ADR420/ADR421/ADR423/ADR425
2.5
2.0
–40°C
+25°C
1.5
+125°C
1.0
0.5
0
TIME (1s/DIV)
0
1
2
3
4
5
LOAD CURRENT (mA)
Figure 21. ADR423 Minimum Input/Output Voltage
Differential vs. Load Current
Figure 24. ADR421 Typical Noise Voltage 0.1 Hz to 10 Hz
2.5
2.0
1.5
1.0
0.5
0
–40°C
+25°C
+125°C
TIME (1s/DIV)
0
1
2
3
4
5
LOAD CURRENT (mA)
Figure 22. ADR425 Minimum Input/Output Voltage
Differential vs. Load Current
Figure 25. Typical Noise Voltage 10 Hz to 10 kHz
30
25
20
15
10
5
1k
TEMPERATURE
SAMPLE SIZE – 160
+25°C
–40°C
+25°C
+125°C
ADR425
ADR420
ADR423
ADR421
100
0
10
10
100
1k
10k
FREQUENCY (Hz)
DEVIATION (ppm)
Figure 23. ADR421 Typical Hysteresis
Figure 26. Voltage Noise Density vs. Frequency
Rev. I | Page 12 of 24
ADR420/ADR421/ADR423/ADR425
C
= 100nF
1mA LOAD
1V/DIV
L
C
= 0µF
BYPASS
LINE INTERRUPTION
500mV/DIV
V
OUT
V
V
IN
LOAD OFF
OUT
500mV/DIV
2V/DIV
LOAD ON
TIME (100µs/DIV)
TIME (100µs/DIV)
Figure 27. ADR421 Line Transient Response, no CBYPASS
Figure 30. ADR421 Load Transient Response, CL = 100 nF
C
= 0.01µF
IN
NO LOAD
C
= 0.1µF
BYPASS
LINE INTERRUPTION
500mV/DIV
V
OUT
V
V
IN
2V/DIV
V
IN
OUT
500mV/DIV
2V/DIV
TIME (4µs/DIV)
TIME (100µs/DIV)
Figure 28. ADR421 Line Transient Response, CBYPASS = 0.1 μF
Figure 31. ADR421 Turn-Off Response
C
= 0.01µF
IN
NO LOAD
C
= 0µF
1mA LOAD
1V/DIV
L
2V/DIV
2V/DIV
V
OUT
V
OUT
LOAD OFF
2V/DIV
LOAD ON
V
IN
TIME (4µs/DIV)
TIME (100µs/DIV)
Figure 29. ADR421 Load Transient Response, no CL
Figure 32. ADR421 Turn-On Response
Rev. I | Page 13 of 24
ADR420/ADR421/ADR423/ADR425
50
45
40
35
30
25
20
15
10
5
C
= 0.01µF
L
NO INPUT CAP
V
OUT
2V/DIV
V
IN
ADR425
ADR423
ADR421
2V/DIV
ADR420
100k
0
10
TIME (4µs/DIV)
100
1k
10k
FREQUENCY (Hz)
Figure 33. ADR421 Turn-Off Response
Figure 36. Output Impedance vs. Frequency
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
C
= 0.01µF
L
NO INPUT CAP
2V/DIV
2V/DIV
V
OUT
V
IN
TIME (4µs/DIV)
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 37. Ripple Rejection vs. Frequency
Figure 34. ADR421 Turn-On Response
C
R
C
= 0.1µF
= 500Ω
BYPASS
L
L
= 0
V
5V/DIV
2V/DIV
OUT
V
IN
TIME (100µs/DIV)
Figure 35. ADR421 Turn-On/Turn-Off Response
Rev. I | Page 14 of 24
ADR420/ADR421/ADR423/ADR425
TERMINOLOGY
Temperature Coefficient
Thermal Hysteresis
The change of output voltage over the operating temperature
range is normalized by the output voltage at 2ꢀ°C, and
expressed in ppm/°C as
The change of output voltage after the device is cycled through
temperatures from +2ꢀ°C to −4±°C to +12ꢀ°C and back to
+2ꢀ°C. This is a typical value from a sample of parts put
through such a cycle.
VOUT
(
T2
)
− VOUT
(
T1
)
TCVOUT
(
ppm / °C
)
=
× 1±6
VOUT _ HYS = VOUT
(
25°C
)
− VOUT _ TC
25°C − VOUT _ TC
VOUT
VOUT
(
25°C
)
×
(T2 − T1
)
VOUT
(
)
where:
VOUT (25°C) = VOUT at 2ꢀ°C.
VOUT (T1) = VOUT at Temperature 1.
VOUT (T2) = VOUT at Temperature 2.
VOUT _ HYS
(
ppm
)
=
×1±6
(
25°C
)
where:
V
V
OUT (25°C) = VOUT at 2ꢀ°C.
OUT_TC = VOUT at 2ꢀ °C after temperature cycle at +2ꢀ°C to
Line Regulation
The change in output voltage due to a specified change in input
voltage. It includes the effects of self-heating. Line regulation is
expressed in either percent per volt, parts per million per volt,
or microvolts per volt change in input voltage.
−4±°C to +12ꢀ°C and back to +2ꢀ°C.
Input Capacitor
Input capacitors are not required on the ADR42x. There is
no limit for the value of the capacitor used on the input, but a
1 μF to 1± μF capacitor on the input improves transient response
in applications where the supply suddenly changes. An addi-
tional ±.1 μF capacitor in parallel also helps to reduce noise
from the supply.
Load Regulation
The change in output voltage due to a specified change in load
current. It includes the effects of self-heating. Load regulation is
expressed in either microvolts per milliampere, parts per
million per milliampere, or ohms of dc output resistance.
Output Capacitor
Long-Term Stability
Typical shift of output voltage at 2ꢀ°C on a sample of parts
subjected to operation life test of 1±±± hours at 12ꢀ°C.
The ADR42x do not need output capacitors for stability under
any load condition. An output capacitor, typically ±.1 μF, filters
out any low level noise voltage and does not affect the operation
of the part. On the other hand, the load transient response can
be improved with an additional 1 ꢁF to 1± ꢁF output capacitor
in parallel. A capacitor here acts as a source of stored energy for
sudden increase in load current. The only parameter that
degrades by adding an output capacitor is the turn-on time,
which depends on the size of the selected capacitor.
ΔVOUT = VOUT
ΔVOUT ppm
where:
(
t0
)
− VOUT
t0 − VOUT
VOUT t0
(
t1
)
VOUT
(
)
(t1 )
(
)
=
× 1±6
(
)
V
V
OUT (t0) = VOUT at 2ꢀ°C at Time ±.
OUT (t1) = VOUT at 2ꢀ°C after 1±±± hours operation at 12ꢀ°C.
Rev. I | Page 15 of 24
ADR420/ADR421/ADR423/ADR425
THEORY OF OPERATION
The ADR42x series of references uses a reference generation
technique known as XFET (eXtra implanted junction FET).
This technique yields a reference with low supply current, good
thermal hysteresis, and exceptionally low noise. The core of the
XFET reference consists of two junction field-effect transistors
(JFET), one having an extra channel implant to raise its pinch-
off voltage. By running the two JFETs at the same drain current,
the difference in pinch-off voltage can be amplified and used to
form a highly stable voltage reference.
DEVICE POWER DISSIPATION CONSIDERATIONS
The ADR42x family of references is guaranteed to deliver load
currents to 1± mA with an input voltage that ranges from 4.ꢀ V
to 18 V. When these devices are used in applications at higher
currents, the following equation should be used to account for
the temperature effects due to power dissipation increases:
TJ = PD × θJA + TA
(2)
where:
TJ and TA are the junction temperature and the ambient
temperature, respectively.
PD is the device power dissipation.
The intrinsic reference voltage is about ±.ꢀ V with a negative
temperature coefficient of about −12± ppm/°C. This slope is
essentially constant to the dielectric constant of silicon and can
be closely compensated by adding a correction term generated
in the same fashion as the proportional-to-temperature (PTAT)
term used to compensate band gap references. The primary
advantage over a band gap reference is that the intrinsic tem-
perature coefficient is approximately 3± times lower (therefore
requiring less correction). This results in much lower noise
because most of the noise of a band gap reference comes from
the temperature compensation circuitry.
θJA is the device package thermal resistance.
BASIC VOLTAGE REFERENCE CONNECTIONS
Voltage references, in general, require a bypass capacitor
connected from VOUT to GND. The circuit in Figure 39
illustrates the basic configuration for the ADR42x family of
references. Other than a ±.1 μF capacitor at the output to help
improve noise suppression, a large output capacitor at the
output is not required for circuit stability.
Figure 38 shows the basic topology of the ADR42x series. The
temperature correction term is provided by a current source
with a value designed to be proportional to absolute tempera-
ture. The general equation is
TP
1
2
8
7
6
TP
ADR420/
ADR421/
ADR423/
ADR425
V
NIC
IN
10µF
+
OUTPUT
0.1µF
NIC
3
4
0.1µF
TOP VIEW
(Not to Scale)
5
TRIM
V
OUT = G × (ΔVP − R1 × IPTAT
)
(1)
NIC = NO INTERNAL CONNECTION
TP = TEST PIN (DO NOT CONNECT)
where:
G is the gain of the reciprocal of the divider ratio.
ΔVP is the difference in pinch-off voltage between the two JFETs.
PTAT is the positive temperature coefficient correction current.
Figure 39. Basic Voltage Reference Configuration
NOISE PERFORMANCE
I
The noise generated by ADR42x references is typically less
than 2 μV p-p over the ±.1 Hz to 1± Hz band for the ADR42±,
ADR421, and ADR423. Figure 24 shows the ±.1 Hz to 1± Hz
noise of the ADR421, which is only 1.7ꢀ μV p-p. The noise
measurement is made with a band-pass filter made of a 2-pole
high-pass filter with a corner frequency at ±.1 Hz and a 2-pole
low-pass filter with a corner frequency at 1± Hz.
Each ADR42x device is created by on-chip adjustment of R2
and R3 to achieve the specified reference output.
V
IN
I
I
1
1
ADR420/ADR421/
ADR423/ADR425
I
PTAT
V
OUT
R2
R3
TURN-ON TIME
*
At power-up (cold start), the time required for the output
voltage to reach its final value within a specified error band
is defined as the turn-on settling time. Two components typi-
cally associated with this are the time for the active circuits to
settle and the time for the thermal gradients on the chip to
stabilize. Figure 31 to Figure 3ꢀ show the turn-on settling time
for the ADR421.
∆V
P
R1
*EXTRA CHANNEL IMPLANT
= G(∆V – R1 × I
V
)
PTAT
GND
OUT
P
Figure 38. Simplified Schematic
Rev. I | Page 16 of 24
ADR420/ADR421/ADR423/ADR425
APPLICATIONS
SOURCE FIBER
OUTPUT ADJUSTMENT
GIMBAL + SENSOR
DESTINATION
The ADR42x trim terminal can be used to adjust the output
voltage over a ±±.ꢀ5 range. This feature allows the system
designer to trim system errors out by setting the reference to
a voltage other than the nominal. This is also helpful if the
part is used in a system at temperature to trim out any error.
Adjustment of the output has a negligible effect on the
temperature performance of the device. To avoid degrading
temperature coefficients, both the trimming potentiometer
and the two resistors need to be low temperature coefficient
types, preferably <1±± ppm/°C.
FIBER
LASER BEAM
ACTIVATOR
RIGHT
MEMS MIRROR
PREAMP
ACTIVATOR
LEFT
AMPL
DAC
AMPL
DAC
ADR421
CONTROL
ELECTRONICS
ADR421
ADR421
ADC
DSP
INPUT
2
OUTPUT
= ±0.5%
V
6
IN
V
OUT
Figure 41. All Optical Router Network
V
OUT
ADR420/
ADR421/
ADR423/
ADR425
HIGH VOLTAGE FLOATING CURRENT SOURCE
R1
470kΩ
The circuit in Figure 42 can be used to generate a floating
current source with minimal self-heating. This particular
configuration can operate on high supply voltages determined
by the breakdown voltage of the N-channel JFET.
R
10kΩ
10kΩ (ADR420)
15kΩ (ADR421)
P
TRIM
5
GND
4
R2
Figure 40. Output Trim Adjustment
+V
S
SST111
VISHAY
REFERENCE FOR CONVERTERS IN OPTICAL
NETWORK CONTROL CIRCUITS
2
V
In the high capacity, all optical router network of Figure 41,
arrays of micromirrors direct and route optical signals from
fiber to fiber, without first converting them to electrical form,
which reduces the communication speed. The tiny micro-
mechanical mirrors are positioned so that each is illuminated
by a single wavelength that carries unique information and
can be passed to any desired input and output fiber. The mirrors
are tilted by the dual-axis actuators controlled by precision
analog-to-digital converters (ADCs) and digital-to-analog
converters (DACs) within the system. Due to the microscopic
movement of the mirrors, not only is the precision of the
converters important, but the noise associated with these
controlling converters is extremely critical, because total noise
within the system can be multiplied by the numbers of
converters used. Consequently, the exceptional low noise of the
ADR42x is necessary to maintain the stability of the control
loop for this application.
IN
ADR420/
ADR421/
ADR423/
ADR425
V
OUT
6
2N3904
OP09
GND
4
R
L
2.10kΩ
–V
S
Figure 42. High Voltage Floating Current Source
Rev. I | Page 17 of 24
ADR420/ADR421/ADR423/ADR425
KELVIN CONNECTIONS
DUAL-POLARITY REFERENCES
In many portable instrumentation applications where PC board
cost and area are important considerations, circuit intercon-
nects are often narrow. These narrow lines can cause large
voltage drops if the voltage reference is required to provide load
currents to various functions. In fact, a circuit’s interconnects
can exhibit a typical line resistance of ±.4ꢀ mΩ/square (1 oz. Cu,
for example). Force and sense connections, also referred to as
Kelvin connections, offer a convenient method of eliminating
the effects of voltage drops in circuit wires. Load currents flow-
ing through wiring resistance produce an error (VERROR = R × IL)
at the load. However, the Kelvin connection in Figure 43
overcomes the problem by including the wiring resistance
within the forcing loop of the op amp. Because the op amp
senses the load voltage, op amp loop control forces the output to
compensate for the wiring error and to produce the correct
voltage at the load.
Dual-polarity references can easily be made with an op amp and
a pair of resistors. In order not to defeat the accuracy obtained
by the ADR42x, it is imperative to match the resistance toler-
ance and the temperature coefficient of all components.
V
IN
2
1µF
0.1µF
V
V
IN
6
+5V
OUT
R1
10kΩ
R2
10kΩ
U1
ADR425
+10V
V+
TRIM
GND
4
5
U2
–5V
OP1177
V–
R3
5kΩ
–10V
Figure 44. +5 V and −5 V Reference Using ADR425
V
IN
+2.5V
+10V
2
R
LW
2
V
ADR420/
ADR421/
ADR423/
ADR425
OUT
SENSE
V
V
V
IN
6
5
OUT
IN
U1
ADR425
R
LW
V
R1
OUT
A1
5.6kΩ
FORCE
V
OUT
6
TRIM
GND
4
GND
4
R
L
R2
5.6kΩ
A1 = OP191
V+
U2
OP1177
V–
Figure 43. Advantage of Kelvin Connection
–2.5V
–10V
Figure 45. +2.5 V and −2.5 V Reference Using ADR425
Rev. I | Page 18 of 24
ADR420/ADR421/ADR423/ADR425
PROGRAMMABLE CURRENT SOURCE
PROGRAMMABLE DAC REFERENCE VOLTAGE
Together with a digital potentiometer and a Howland current
pump, the ADR42ꢀ forms the reference source for a program-
mable current as
With a multichannel DAC, such as the quad, 12-bit voltage
output AD7398, one of its internal DACs, and an ADR42x
voltage reference can be used as a common programmable
VREFx for the rest of the DACs. The circuit configuration is
shown in Figure 47. The relationship of VREFx to VREF depends
on the digital code and the ratio of R1 and R, and is given by
R2 + R2B
⎛
⎜
⎞
⎟
A
R1
⎝
⎠
IL
=
× VW
(3)
(4)
R2B
R2
R1
⎛
⎞
⎟
VREF × 1 +
⎜
and
⎝
D
⎠
VREF x =
(ꢀ)
D
2N
R2
⎛
⎜
⎞
VW =
× VREF
1 +
×
⎟
⎠
2N R1
⎝
where:
where:
D is the decimal equivalent of the input code.
N is the number of bits.
D is the decimal equivalent of input code.
N is the number of bits.
C1
10pF
V
REF is the applied external reference.
V
REFx is the reference voltage for DACs A to D.
V
R1'
R2'
DD
2
50kΩ
1kΩ
Table 9. VREFx vs. R1 and R2
R1, R2
V
DD
Digital Code
VREF
V
TRIM
U1
5
6
IN
AD5232
U2
R1 = R2
R1 = R2
R1 = R2
R1 = 3R2
R1 = 3R2
R1 = 3R2
0000 0000 0000
1000 0000 0000
1111 1111 1111
0000 0000 0000
1000 0000 0000
1111 1111 1111
2 VREF
1.3 VREF
VREF
4 VREF
1.6 VREF
VREF
V+
A2
OP2177
ADR425
DIGITAL POT
C2
10pF
V
DD
V
OUT
GND
4
V–
A
R2
10Ω
B
U2
V+
A1
OP2177
V
SS
B
W
R1
50kΩ
R2
A
1kΩ
V–
LOAD
V
SS
VL
IL
Figure 46. Programmable Current Source
R2
±0.1%
R1
±0.1%
V
A
REF
V
A
R1' and R2' must be equal to R1 and R2A + R2B, respectively.
Theoretically, R2B can be made as small as needed to achieve
OUT
V
REF
DACA
V
the current needed within A2 output current driving capability.
In the example shown in Figure 46, OP2177 is able to deliver
a maximum of 1± mA. Because the current pump uses both
positive and negative feedback, capacitors C1 and C2 are needed
to ensure that negative feedback prevails and, therefore, avoiding
oscillation. This circuit also allows bidirectional current flow if
the inputs VA and VB of the digital potentiometer are supplied
with the dual-polarity references as previously shown.
IN
ADR425
V
B
REF
V
V
V
B
C
D
OUT
OUT
OUT
V
V
V
= V
= V
= V
x (D
x (D
x (D
)
)
)
OB
OC
OD
REF
REF
REF
B
C
D
DACB
V
C
REF
DACC
V
D
REF
DACD
AD7398
Figure 47. Programmable DAC Reference
Rev. I | Page 19 of 24
ADR420/ADR421/ADR423/ADR425
PRECISION VOLTAGE REFERENCE FOR DATA
CONVERTERS
PRECISION BOOSTED OUTPUT REGULATOR
A precision voltage output with boosted current capability
can be realized with the circuit shown in Figure 49. In this
circuit, U2 forces VOUT to be equal to VREF by regulating the turn
on of N1. Therefore, the load current is furnished by VIN. In
this configuration, a ꢀ± mA load is achievable at VIN of ꢀ V.
Moderate heat is generated on the MOSFET, and higher current
can be achieved by replacing the larger device. In addition, for
a heavy capacitive load with step input, a buffer may be added
at the output to enhance the transient response.
The ADR42x family has a number of features that make it ideal
for use with ADCs and DACs. The exceptionally low noise,
tight temperature coefficient, and high accuracy characteristics
make the ADR42x ideal for low noise applications such as
cellular base station applications.
AD77±1 is an example of an ADC that is well suited for the
ADR42x. The ADR421 is used as the precision reference for
the converter in Figure 48. The AD77±1 is a 16-bit ADC with
on-chip digital filtering intended for measuring wide dynamic
range and low frequency signals, such as those representing
chemical, physical, or biological processes. It contains a charge-
balancing (Σ-Δ) ADC, calibration microcontroller with on-chip
static RAM, clock oscillator, and serial communications port.
N1
V
V
OUT
IN
R
L
25Ω
5V
2
U1
V
IN
2N7002
6
5
V
+
OUT
V+
U2
ADR421
+5V
ANALOG
SUPPLY
AD8601
TRIM
GND
4
V–
–
0.1µF
10µF
AD7701
AV
V
DV
DD
DD
Figure 49. Precision Boosted Output Regulator
SLEEP
MODE
0.1µF
V
IN
V
OUT
REF
DATA READY
DRDY
CS
0.1µF
ADR420/
ADR421/
ADR423/
ADR425
READ (TRANSMIT)
SERIAL CLOCK
SERIAL CLOCK
SCLK
SDATA
GND
CLKIN
RANGES
BP/UP
CAL
SELECT
CLKOUT
CALIBRATE
SC1
SC2
ANALOG
INPUT
A
IN
ANALOG
GROUND
DGND
AGND
0.1µF
0.1µF
10µF
DV
SS
AV
SS
–5V
ANALOG
SUPPLY
0.1µF
Figure 48. Voltage Reference for 16-Bit ADC AD7701
Rev. I | Page 20 of 24
ADR420/ADR421/ADR423/ADR425
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
45°
1.27 (0.0500)
BSC
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0099)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 50. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.15
0.05
0.23
0.09
6°
0°
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 51. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Rev. I | Page 21 of 24
ADR420/ADR421/ADR423/ADR425
ORDERING GUIDE
Initial
Accuracy
Output
Voltage,
VOUT (V)
Temperature
Coefficient
(ppm/°C)
Temperature
Range
Package
Description
Package
Option
Model1
Branding
mV
%
ADR420ARZ
2.048
2.048
2.048
2.048
2.048
2.048
2.50
2.50
2.50
2.50
2.50
2.50
2.50
2.50
2.50
3.00
3.00
3.00
3.00
3.00
3.00
5.00
5.00
5.00
5.00
5.00
5.00
5.00
5.00
3
3
3
3
1
1
3
3
3
3
3
1
1
1
1
4
4
4
4
1.5
1.5
6
6
6
6
2
2
2
2
0.15
0.15
0.15
0.15
0.05
0.05
0.12
0.12
0.12
0.12
0.12
0.04
0.04
0.04
0.04
0.13
0.13
0.13
0.13
0.04
0.04
0.12
0.12
0.12
0.12
0.04
0.04
0.04
0.04
10
10
10
10
3
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead MSOP
8-Lead MSOP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead MSOP
8-Lead MSOP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead MSOP
8-Lead MSOP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead MSOP
8-Lead MSOP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
R-8
R-8
RM-8
RM-8
R-8
ADR420ARZ-REEL7
ADR420ARMZ
ADR420ARMZ-REEL7
ADR420BRZ
ADR420BRZ-REEL7
ADR421AR
L0C
L0C
3
R-8
10
10
10
10
10
3
3
3
3
R-8
R-8
R-8
RM-8
RM-8
R-8
R-8
R-8
ADR421ARZ
ADR421ARZ-REEL7
ADR421ARMZ
ADR421ARMZ-REEL7
ADR421BR
ADR421BR-REEL7
ADR421BRZ
ADR421BRZ-REEL7
ADR423ARZ
ADR423ARZ-REEL7
ADR423ARMZ
ADR423ARMZ-REEL7
ADR423BRZ
ADR423BRZ-REEL7
ADR425ARZ
ADR425ARZ-REEL7
ADR425ARMZ
ADR425ARMZ-REEL7
ADR425BR
ADR425BR-REEL7
ADR425BRZ
ADR425BRZ-REEL7
R06
R06
R-8
10
10
10
10
3
R-8
R-8
RM-8
RM-8
R-8
R0U
R0U
3
R-8
10
10
10
10
3
3
3
3
R-8
R-8
RM-8
RM-8
R-8
R-8
R-8
R-8
R7A#
R7A#
1 Z = RoHS Compliant Part. # denotes RoHS-compliant product may be top or bottom marked.
Rev. I | Page 22 of 24
ADR420/ADR421/ADR423/ADR425
NOTES
Rev. I | Page 23 of 24
ADR420/ADR421/ADR423/ADR425
NOTES
©2001–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02432-0-5/11(I)
Rev. I | Page 24 of 24
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