ADRF5024 [ADI]
Silicon SPDT Switch, Reflective, 100 MHz to 44 GHz;
| 型号： | ADRF5024 |
| 厂家： | 
ADI |
| 描述： | Silicon SPDT Switch, Reflective, 100 MHz to 44 GHz 光电二极管 |
| 文件： | 总13页 (文件大小：432K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Silicon SPDT Switch, Reflective,
100 MHz to 44 GHz
Data Sheet
ADRF5024
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Ultrawideband frequency range: 100 MHz to 44 GHz
Reflective design
Low insertion loss with impedance match
1.0 dB typical to 18 GHz
ADRF5024
VSS
1.4 dB typical to 40 GHz
1.7 dB typical to 44 GHz
RFC
CTRL
VDD
Low insertion loss without impedance match
0.9 dB typical to 18 GHz
1.7 dB typical to 40 GHz
2.1 dB typical to 44 GHz
High input linearity
P1dB: 27.5 dBm typical
IP3: 50 dBm typical
High RF input power handling
Through path: 27 dBm
Figure 1.
Hot switching: 27 dBm
No low frequency spurious
RF settling time (50% VCTRL to 0.1 dB of final RF output): 17 ns
12-terminal, 2.25 mm × 2.25 mm LGA package
Pin compatible with the ADRF5025 low frequency cutoff
version
APPLICATIONS
Industrial scanners
Test and instrumentation
Cellular infrastructure: 5G mmWave
Military radios, radars, electronic counter measures (ECMs)
Microwave radios and very small aperture terminals (VSATs)
GENERAL DESCRIPTION
The ADRF5024 is a reflective, single-pole double-throw
(SPDT) switch manufactured in the silicon process.
The ADRF5024 is pin-compatible with the ADRF5025, low
frequency cutoff version, which operates from 9 kHz to 44 GHz.
This switch operates from 100 MHz to 44 GHz with better than
1.7 dB of insertion loss and 35 dB of isolation. The ADRF5024
has a radio frequency (RF) input power handling capability of
27 dBm for both the through path and hot switching.
The ADRF5024 RF ports are designed to match a characteristic
impedance of 50 Ω. For ultrawideband products, impedance
matching on the RF transmission lines can further optimize
high frequency insertion loss and return loss characteristics.
Refer to the Electrical Specifications section, Typical Performance
Characteristics section, and Applications Information section
for more details.
The ADRF5024 draws a low current of 14 μA on the positive
supply of +3.3 V and 120 μA on negative supply of −3.3 V. The
device employs complementary metal-oxide semiconductor
(CMOS)-/low voltage transistor to transistor logic (LVTTL)-
compatible controls.
The ADRF5024 comes in a 2.25 mm × 2.25 mm, 12-terminal,
RoHS-compliant, land grid array (LGA) package and can
operate between −40°C to +105°C.
Rev. C
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ADRF5024
Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
Interface Schematics .....................................................................6
Typical Performance Characteristics .............................................7
Insertion Loss, Return Loss, and Isolation................................7
Input Power Compression and Third-Order Intercept ..........8
Theory of Operation .........................................................................9
Applications Information ............................................................. 10
Evaluation Board........................................................................ 10
Probe Matrix Board ................................................................... 12
Outline Dimensions....................................................................... 13
Ordering Guide .......................................................................... 13
Applications ...................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications .................................................................................... 3
Electrical Specifications............................................................... 3
Absolute Maximum Ratings ........................................................... 5
Thermal Resistance...................................................................... 5
Power Derating Curves ............................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions ............................ 6
REVISION HISTORY
8/2020—Rev. B to Rev. C
5/2018—Rev. 0 to Rev. A
Changes to Figure 7 and Figure 10 ................................................ 7
Updated Outline Dimensions ..................................................... 13
Changes to Ordering Guide.......................................................... 13
5/2020—Rev. A to Rev. B
Change to Return Loss Parameter, Table 1 .................................. 3
Changes to Table 2 ........................................................................... 5
Changes to Insertion Loss, Return Loss, and Isolation Section,
Figure 7, Figure 8, Figure 10, and Figure 11................................. 7
Changes to Theory of Operation Section...................................... 9
5/2018—Revision 0: Initial Version
Rev. C | Page 2 of 13
Data Sheet
ADRF5024
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
VDD = 3.3 V, VSS = −3.3 V, VCTRL = 0 V or VDD, and case temperature (TCASE) = 25°C for 50 Ω system, unless otherwise noted.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
FREQUENCY RANGE
INSERTION LOSS
f
100
44,000
MHz
Between RFC and RF1/RF2 (On)
With Impedance Match
See Figure 24
100 MHz to 18 GHz
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
40 GHz to 44 GHz
See Figure 25
1.0
1.4
1.4
1.4
1.7
dB
dB
dB
dB
dB
Without Impedance Match
100 MHz to 18 GHz
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
40 GHz to 44 GHz
0.9
1.1
1.5
1.7
2.1
dB
dB
dB
dB
dB
RETURN LOSS
RFC and RF1/RF2 (On)
With Impedance Match
See Figure 24
100 MHz to 18 GHz
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
40 GHz to 44 GHz
See Figure 25
17
13
13
18
12
dB
dB
dB
dB
dB
Without Impedance Match
100 MHz to 18 GHz
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
40 GHz to 44 GHz
21
17
13
12
10
dB
dB
dB
dB
dB
ISOLATION
Between RFC and RF1/RF2
100 MHz to 18 GHz
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
40 GHz to 44 GHz
100 MHz to 18 GHz
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
40 GHz to 44 GHz
42
41
38
36
35
47
45
44
42
38
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Between RF1 and RF2
SWITCHING CHARACTERISTICS
Rise and Fall Time
On and Off Time
RF Settling Time
0.1 dB
tRISE, tFALL
tON, tOFF
10% to 90% of RF output
50% VCTRL to 90% of RF output
2
10
ns
ns
50% VCTRL to 0.1 dB of final RF output
50% VCTRL to 0.05 dB of final RF output
17
22
ns
ns
0.05 dB
Rev. C | Page 3 of 13
ADRF5024
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
INPUT LINEARITY1
1 dB Power Compression
Third-Order Intercept
200 MHz to 40 GHz
P1dB
IP3
27.5
50
dBm
dBm
Two tone input power = 12 dBm each tone,
Δf = 1 MHz
SUPPLY CURRENT
Positive Supply Current
Negative Supply Current
DIGITAL CONTROL INPUTS
Voltage
VDD and VSS pins
IDD
ISS
14
120
μA
μA
CTRL pin
Low
High
VINL
VINH
0
1.2
0.8
3.3
V
V
Current
Low and High
IINL, IINH
<1
μA
RECOMMENDED OPERATING CONDITONS
Supply Voltage
Positive
VDD
VSS
VCTRL
PIN
3.15
−3.45
0
3.45
−3.15
VDD
V
V
V
Negative
Digital Control Voltage
RF Input Power2
Through Path
f = 200 MHz to 40 GHz, TCASE = 85°C3
RF signal is applied to RFC or through
connected RF1/RF2
RF signal is present at RFC while switching
between RF1 and RF2
27
dBm
dBm
°C
Hot Switching
27
Case Temperature
TCASE
−40
+105
1 For input linearity performance over frequency, see Figure 13 to Figure 16.
2 For power derating over frequency, see Figure 2 and Figure 3.
3 For 105°C operation, the power handling degrades from the TCASE = 85°C specification by 3 dB.
Rev. C | Page 4 of 13
Data Sheet
ADRF5024
ABSOLUTE MAXIMUM RATINGS
For the recommended operating conditions, see Table 1.
Table 3. Thermal Resistance
Package Type
Table 2.
θJC
Unit
Parameter
Rating
CC-12-3, Through Path
352
°C/W
Positive Supply Voltage
Negative Supply Voltage
Digital Control Input Voltage
Voltage
−0.3 V to +3.6 V
−3.6 V to +0.3 V
POWER DERATING CURVES
2
0
–2
−0.3 V to VDD + 0.3 V
3 mA
Current
RF Input Power1 (f = 200 MHz to 40
GHz, TCASE = 85°C2)
–4
Through Path
Hot Switching
RF Input Power Under Unbiased
Condition1 (VDD, VSS = 0 V)
Temperature
Junction, TJ
27.5 dBm
27.5 dBm
21 dBm
–6
–8
–10
–12
–14
135°C
−65°C to +150°C
260°C
Storage Range
Reflow
10k
100k
1M
10M
100M
1G
10G
100G
FREQUENCY (Hz)
ESD Sensitivity
Figure 2. Power Derating vs. Frequency, Low Frequency Detail, TCASE = 85°C
Human Body Model (HBM)
RFC, RF1, and RF2 Pins
Digital Pins
2
500 V
2000 V
1250 V
0
–2
Charged Device Model (CDM)
1 For power derating vs. frequency, see Figure 2 and Figure 3. This power
derating is applicable for insertion loss path and hot switching power
specifications.
–4
2 For 105°C operation, the power handling degrades from the TCASE = 85°C
specification by 3 dB.
–6
–8
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
–10
–12
–14
35
38
41
44
47
50
FREQUENCY (GHz)
Figure 3. Power Derating vs. Frequency, High Frequency Detail, TCASE = 85°C
Only one absolute maximum rating can be applied at any one
time.
ESD CAUTION
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJC is the junction to case bottom (channel to package bottom)
thermal resistance.
Rev. C | Page 5 of 13
ADRF5024
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
12 11
10
9
8
7
1
2
3
VSS
GND
RFC
GND
ADRF5024
CTRL
TOP VIEW
(Not to Scale)
VDD
4
5
6
NOTES
1. EXPOSED PAD MUST BE CONNECTED
TO THE RF/DC GROUND OF THE PCB.
Figure 4. Pin Configuration (Top View)
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
Ground. These pins must be connected to the RF/dc ground of the PCB.
RF Common Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is
necessary when the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic.
1, 3, 4, 6, 10, 12
2
GND
RFC
5
RF1
RF Port 1. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is necessary when
the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic.
7
8
9
VDD
CTRL
VSS
Positive Supply Voltage.
Control Input Voltage. See Figure 6 for the interface schematic.
Negative Supply Voltage.
11
RF2
RF Port 2. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is necessary when
the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic.
EPAD
Exposed Pad. The exposed pad must be connected to the RF/dc ground of the PCB.
INTERFACE SCHEMATICS
VDD
VDD
RFC,
RF1,
RF2
CTRL
Figure 6. CTRL Interface Schematic
Figure 5. RFx Pins Interface Schematic
Rev. C | Page 6 of 13
Data Sheet
ADRF5024
TYPICAL PERFORMANCE CHARACTERISTICS
INSERTION LOSS, RETURN LOSS, AND ISOLATION
VDD = 3.3 V, VSS = −3.3 V, VCTRL = 0 V or VDD, and TCASE = 25°C for a 50 Ω system, unless otherwise noted.
Insertion loss, return loss and isolation are measured on the probe matrix board using ground-signal-ground (GSG) probes close to the
RFx pins. See the Applications Information section for details on the evaluation and probe matrix boards.
0
–0.5
–1.0
–1.5
–2.0
–2.5
-3.0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
T
T
T
T
T
= –55°C
= –40°C
= +25°C
= +85°C
= +105°C
T
T
T
T
T
= –55°C
= –40°C
= +25°C
= +85°C
= +105°C
CASE
CASE
CASE
CASE
CASE
CASE
CASE
CASE
CASE
CASE
–3.5
–4.0
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 10. Insertion Loss vs. Frequency Without Impedance Match
Figure 7. Insertion Loss vs. Frequency with Impedance Match
0
0
RFC
RF1 ON
RF2 ON
RFC
RF1 ON
–5
–10
–15
–20
–25
–30
–35
–40
–5
RF2 ON
–10
–15
–20
–25
–30
–35
–40
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 8. Return Loss vs. Frequency for RFC and RFx (On)
with Impedance Match
Figure 11. Return Loss vs. Frequency for RFC and RFx (On)
Without Impedance Match
0
–10
–20
–30
–40
–50
–60
–70
–80
0
–10
–20
–30
–40
–50
–60
–70
–80
RFC TO RFx
RFx TO RFx
RFC TO RFx
RFx TO RFx
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 9. Isolation vs. Frequency with Impedance Match
Figure 12. Isolation vs. Frequency Without Impedance Match
Rev. C | Page 7 of 13
ADRF5024
Data Sheet
INPUT POWER COMPRESSION AND THIRD-ORDER INTERCEPT
VDD = 3.3 V, VSS = −3.3 V, VCTRL = 0 V or VDD, and TCASE = 25°C for a 50 Ω system, unless otherwise noted. All of the large signal
performance parameters were measured on the evaluation board.
30
28
26
24
22
20
18
16
14
12
30
28
26
24
22
20
18
16
14
12
10
10
10k
100k
1M
10M
100M
1G
0
5
10
15
20
25
30
35
40
FREQUENCY (Hz)
FREQUENCY (GHz)
Figure 15. Input P1dB vs. Frequency (Low Frequency Detail)
Figure 13. Input P1dB vs. Frequency
60
55
50
45
40
35
30
25
20
60
55
50
45
40
35
30
25
20
0
5
10
15
20
25
30
35
40
10k
100k
1M
10M
100M
1G
FREQUENCY (GHz)
FREQUENCY (Hz)
Figure 16. Input IP3 vs. Frequency (Low Frequency Detail)
Figure 14. Input IP3 vs. Frequency
Rev. C | Page 8 of 13
Data Sheet
ADRF5024
THEORY OF OPERATION
The ADRF5024 requires a positive supply voltage applied to the
VDD pin and a negative supply voltage applied to the VSS pin.
Bypassing capacitors are recommended on the supply lines to
filter high frequency noise.
The unselected RF port of the ADRF5024 is reflective. The
isolation path provides high isolation between the unselected
port and the insertion loss path.
The ideal power-up sequence is as follows:
All of the RF ports (RFC, RF1, and RF2) are dc-coupled to 0 V,
and no dc blocking is required at the RF ports when the RF line
potential is equal to 0 V.
1. Connect GND.
2. Power up VDD and VSS. Power up VSS after VDD to
avoid current transients on VDD during ramp-up.
3. Apply the digital control inputs. The relative order of the
control inputs is not important. However, powering the
digital control inputs before the VDD supply may
inadvertently forward bias and damage the internal ESD
protection structures. To avoid this damage, use a series
1 kΩ resistor to limit the current flowing in to the control
pin. Use pull-up or pull-down resistors if the controller is
in a high impedance state after VDD is powered up and
the control pins are not driven to a valid logic state.
4. Apply an RF input signal.
The RF ports are internally matched to 50 ꢀ. Therefore,
external matching networks are not required. However,
impedance matching on transmission lines can be used to
improve insertion loss and return loss performance at high
frequencies.
The ADRF5024 integrates a driver to perform logic functions
internally and provides the user with the advantage of a
simplified CMOS/LVTTL-compatible control interface. This
driver features a single digital control input pin, CTRL. The
logic level applied to the CTRL pin determines which RF port is
in the insertion loss state and in the isolation state (see Table 5).
The ideal power-down sequence is the reverse order of the
power-up sequence.
Table 5. Control Voltage Truth Table
RF Path
Digital Control Input (VCTRL
)
RF1 to RFC
RF2 to RFC
Low
High
Isolation (off)
Insertion loss (on)
Insertion loss (on)
Isolation (off)
Rev. C | Page 9 of 13
ADRF5024
Data Sheet
APPLICATIONS INFORMATION
THRU CAL can be used to calibrate out the board loss effects
from the ADRF5024-EVALZ evaluation board measurements
to determine the device performance at the pins of the IC.
Figure 19 shows the typical board loss for the ADRF5024-
EVALZ evaluation board at room temperature, the embedded
insertion loss, and the de-embedded insertion loss for the
ADRF5024.
EVALUATION BOARD
The ADRF5024-EVALZ is a 4-layer evaluation board. The
outer copper (Cu) layers are 0.5 oz (0.7 mil) plated to 1.5 oz
(2.2 mil) and are separated by dielectric materials. Figure 17
shows the evaluation board stackup.
G = 7mil
W = 14mil
1.5oz Cu (2.2mil)
1.5oz Cu (2.2mil)
1.5oz Cu (2.2mil)
T = 2.2mil
H = 8mil
0
RO4003
–1
–2
–3
–4
–5
0.5oz Cu (0.7mil)
0.5oz Cu (0.7mil)
1.5oz Cu (2.2mil)
–6
THRU LOSS
EMBEDDED INSERTION LOSS
DEEMBEDDED INSERTION LOSS
–7
Figure 17. Evaluation Board (Cross Section View)
0
5
10
15
20
25
30
35
40
45
50
All RF and dc traces are routed on the top copper layer,
whereas the inner and bottom layers are grounded planes that
provide a solid ground for the RF transmission lines. The top
dielectric material is 8 mil Rogers RO4003, offering optimal
high frequency performance. The middle and bottom dielectric
materials provide mechanical strength. The overall board
thickness is 62 mil, which allows 2.4 mm RF launchers to
be connected at the board edges.
FREQUENCY (GHz)
Figure 19. Insertion Loss vs. Frequency
Figure 20 shows the actual ADRF5024-EVALZ with its
component placement.
Two power supply ports are connected to the VDD and VSS
test points, TP7 and TP5 (or TP3 and TP1 if using without
impedance match circuit), and the ground reference is
connected to the GND test point, TP4 or TP8. On the supply
traces, VDD and VSS, a 100 pF bypass capacitor filters high
frequency noise. Additionally, unpopulated components
positions are available for applying extra bypass capacitors.
WITHOUT
IMPEDANCE
MATCH
WITH
IMPEDANCE
MATCH
A control port is connected to the CTRL test point, TP6 (or
TP2 for without impedance match circuit). There are
provisions for the resistor capacitor (RC) filter to eliminate dc-
coupled noise, if needed, by the application. The resistor can
also improve the isolation between the RF and the control
signal.
Figure 18. Evaluation Board Layout, Top View
The RF transmission lines were designed using a coplanar
waveguide (CPWG) model, with trace width of 14 mil and
ground clearance of 7 mil to have a characteristic impedance of
50 Ω. For optimal RF and thermal grounding, as many plated
through vias as possible are arranged around transmission lines
and under the exposed pad of the package.
The RF input and output ports (RFC, RF1, and RF2) are
connected through 50 ꢀ transmission lines to the 2.4 mm
RF launchers, J10, J9, and J8 (or J2, J3, and J1 for without
impedance match circuit), respectively. These high frequency
RF launchers are by contact and are not soldered to the board.
A THRU CAL line connects the unpopulated J6 and J7
launchers (or J4 and J5 for without impedance match circuit).
This transmission line is used to estimate the loss due to the
PCB over the environmental conditions being evaluated.
The ADRF5024-EVALZ has two layouts implemented, with
and without impedance matching. By default, the impedance
matched circuit is populated. For more details on this impedance
matched circuit, refer to Impedance Matching in the Probe
Matrix Board section.
The schematic of the ADRF5024-EVALZ evaluation board
is shown in Figure 21.
Rev. C | Page 10 of 13
Data Sheet
ADRF5024
Figure 20. Evaluation Board Component Placement
RF2
EPAD
VSS
VCTRL
VDD
9
8
7
GND
RFC
GND
1
2
3
VSS
100pF
100pF
0Ω
CTRL
VDD
RFC
ADRF5024
RF1
THRU CAL
Figure 21. Simplified Evaluation Board Schematic
Table 6. Evaluation Board Components
Component
C8, C9
J8 to J10
R2
Default Value
Description
100 pF
Not applicable
0 Ω
Capacitors, C0402 package
2.4 mm end launch connectors (Southwest Microwave: 1492-04A-5)
Resistor, 0402 package
TP5 to TP8
U2
PCB
Not applicable
ADRF5024
08-046672E
Through hole mount test points
ADRF5024 SPDT switch, Analog Devices, Inc.
Evaluation PCB, Analog Devices
Rev. C | Page 11 of 13
ADRF5024
Data Sheet
Impedance Matching
PROBE MATRIX BOARD
Impedance matching at the RFx pins can improve the insertion
loss and return loss at high frequencies. Figure 24 and Figure 25
show the difference in the transmission lines at the RFC, RF1,
and RF2 pins. This same circuit is implemented on the probe
matrix boards and the evaluation boards.
The probe matrix board is a 4-layer board. Similar to the
evaluation board, this board also uses a 8 mil Rogers RO4003
dielectric. The outer copper layers are 0.5 oz (0.7 mil) copper
plated to 1.5 oz (2.2 mil). The RF transmission lines were
designed using a CPWG model with a width of 14 mil and
ground spacing of 7 mil to have a characteristic impedance of
50 Ω.
The dimensions of the 50 Ω lines are 14 mil trace width and
7 mil gap. To implement this impedance matched circuit, a
5 mil trace with a width of 5 mils was inserted between the pin
pad and the 50 Ω trace. The calibration kit reference kit does
not include the 5 mil matching line, and therefore, the measured
insertion loss includes the losses of the matching circuit.
Figure 22 and Figure 23 show the cross section and top view of
the board, respectively. Measurements are made using GSG
probes at close proximity to the RFx pins. Unlike the evaluation
board, probing reduces reflections caused by mismatch arising
from connectors, cables, and board layout, resulting in a more
accurate measurement of the device performance.
G = 7mil
W = 14mil
1.5oz Cu (2.2mil)
1.5oz Cu (2.2mil)
1.5oz Cu (2.2mil)
T = 2.2mil
H = 8mil
RO4003
0.5oz Cu (0.7mil)
0.5oz Cu (0.7mil)
1.5oz Cu (2.2mil)
Figure 22. Probe Matrix Board (Cross Section View)
Figure 24. With Impedance Match
Figure 23. Probe Board Layout (Top View)
The probe matrix board includes a through reflect line (TRL)
calibration kit allowing board loss de-embedding. The actual
board duplicates the same layout in matrix form to assemble
multiple devices at one time. All S parameters were measured
on this board.
Figure 25. Without Impedance Match
Rev. C | Page 12 of 13
Data Sheet
ADRF5024
OUTLINE DIMENSIONS
0.85
0.80
0.75
0.567
BSC
2.35
2.25
2.15
0.633
BSC
0.818
BSC
PIN 1
INDICATOR
PIN 1
INDICATOR
0.10 × 0.45°
10
12
0.40
BSC
1
9
0.75
0.70
0.65
0.80 REF
7
3
6
4
0.775
BSC
0.325
0.275
0.225
TOP VIEW
END VIEW
BOTTOM VIEW
0.250
0.200
0.150
0.125
BSC
0.85
0.75
0.65
0.53 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.26
0.22
0.18
SECTION OF THIS DATA SHEET.
Figure 26. 12-Terminal Land Grid Array [LGA]
2.25 mm × 2.25 mm Body and 0.75 mm Package Height
(CC-12-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +105°C
−40°C to +105°C
Package Description
Package Option
CC-12-3
CC-12-3
Marking Code
ADRF5024BCCZN
ADRF5024BCCZN-R7
ADRF5024-EVALZ
12-Terminal Land Grid Array [LGA]
12-Terminal Land Grid Array [LGA]
Evaluation Board
24
24
1 Z = RoHS Compliant Part.
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registered trademarks are the property of their respective owners.
D16011-8/20(C)
Rev. C | Page 13 of 13
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