ADRF6650ACPZ [ADI]
Dual Downconverter with DVGA and PLL/VCO, 450 MHz to 2700 MHz;
| 型号： | ADRF6650ACPZ |
| 厂家： | 
ADI |
| 描述： | Dual Downconverter with DVGA and PLL/VCO, 450 MHz to 2700 MHz 电信 信息通信管理 电信集成电路 |
| 文件： | 总61页 (文件大小：1124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual Downconverter with DVGA and
PLL/VCO, 450 MHz to 2700 MHz
ADRF6650
Data Sheet
The on-chip RF baluns enable the ADRF6650 to support 50 Ω
terminated RF inputs. The integrated passive mixer provides a
highly linear downconversion for a 200 MHz, sliding, intermediate
frequency (IF) window. The ADRF6650 uses broadband square
wave limiting local oscillator (LO) amplifiers to achieve an RF
bandwidth of 450 MHz to 2700 MHz. Unlike conventional
narrow-band sine wave LO amplifier solutions, this amplifier
permits the LO to be applied either above or below the RF input
over an extremely wide bandwidth.
FEATURES
Dual down-converter with integrated fractional-N PLL/VCO
RF: 450 MHz to 2700 MHz continuous
LO frequency: 450 MHz to 2900 MHz,
high-side or low-side injection
43 dB gain control range
Gain control with up/down and SPI
Integrated RF balun for single-ended 50 Ω inputs
Power supply: 3.3 and 5 V
8 mm × 8 mm, 56-lead LFCSP package
The ADRF6650 offers two alternatives for generating the differ-
ential LO input signal: internally via the on-chip fractional-N
synthesizer with low phase noise VCOs, or externally via a low
phase noise LO signal. The integrated PLL/VCO enables contin-
uous LO coverage from 450 MHz to 2900 MHz. The PLL reference
input supports a wide frequency range and includes integrated
reference dividers before the phase frequency detector (PFD).
APPLICATIONS
Multiband/multistandard cellular base station diversity
receivers
Wideband radio link diversity downconverters
Multimode cellular extenders and picocells
GENERAL DESCRIPTION
The ADRF6650 is fabricated using an advanced silicon-germa-
nium (SiGe) bipolar complementary metal-oxide semiconductor
(BiCMOS) process. It is available in a 56-lead, RoHS-compliant,
8 mm × 8 mm, lead frame chip scale package (LFCSP) package
with an exposed pad. Performance is specified over the −40°C to
+105°C maximum paddle temperature.
The ADRF6650 is a highly integrated downconverter that
integrates dual mixers, dual digital switched attenuators, dual
digital variable gain amplifiers, a phase-locked loop (PLL), and
voltage controlled oscillators (VCOs). In addition, the ADRF6650
integrates two radio frequency (RF) baluns, serial gain control
(SGC) controls, and fast enable inputs for time division duplex
(TDD) operation.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2019 Analog Devices, Inc. All rights reserved.
www.analog.com
ADRF6650
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Mixers .......................................................................................... 22
Low-Pass Filters.......................................................................... 22
IF Amplifiers............................................................................... 22
DVGA .......................................................................................... 22
TDD Operation .......................................................................... 24
LO Generation Block................................................................. 24
Serial Port Interface ................................................................... 27
Applications Information.............................................................. 28
Basic Connections...................................................................... 28
RF Frequency and IF Bandwidth Optimization .................... 31
IF DVGA vs. Load...................................................................... 31
ADC Interfacing......................................................................... 32
Power Modes............................................................................... 33
Power Supply Configuration .................................................... 34
Layout .......................................................................................... 35
Register Map ................................................................................... 37
Register Details........................................................................... 40
Outline Dimensions....................................................................... 61
Ordering Guide .......................................................................... 61
Applications....................................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
RF Input to IF Output System Specifications ........................... 5
Gain Control Specifications ........................................................ 6
PLL/VCO Specifications.............................................................. 6
Digital Logic Specifications......................................................... 8
Absolute Maximum Ratings.......................................................... 10
Thermal Resistance .................................................................... 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics ........................................... 13
Phase-Locked Loop (PLL)......................................................... 18
Spurious Performance................................................................ 21
Theory of Operation ...................................................................... 22
RF Balun ...................................................................................... 22
REVISION HISTORY
11/2019—Revision A
Rev. A | Page 2 of 61
Data Sheet
ADRF6650
FUNCTIONAL BLOCK DIAGRAM
REF_IN
45
56 55
50
49
53 52
ADRF6650
DVGA SPI
SPI
RFIN_A
TDD_A
4
2
÷R
PFD
÷N
LPF
41
30
CP
CPOUT
Σ-Δ
VTUNE
÷
32
31
EX_LO_IN–
EX_LO_IN+
13
11
TDD_B
RFIN_B
39 LO_OUT–
38
LO_OUT+
LPF
SPI
DVGA SPI
15 16
21
22
18 19
24 25 26 27
Figure 1.
Rev. A | Page 3 of 61
ADRF6650
Data Sheet
SPECIFICATIONS
VCC_DVGA_A/VCC_DVGA_B = 5 V, remaining supplies = 3.3 V, TA = 25°C, low-side LO injection, fIF = 184 MHz, internal LO, maximum
gain setting, 5 V high performance settings, unless otherwise noted. All losses from input and output traces and baluns are de-embedded
from results.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
RF INPUT INTERFACE
Return Loss
Input Impedance
RF Frequency Range
IF OUTPUT INTERFACE
Return loss
RFIN_A/RFIN_B internally matched to 50 Ω
−10
50
dB
Ω
MHz
450
2700
IF output with 100 Ω differential load (25 Ω external
resistors are required on each differential output pin)
Differential impedance
−10
10
dB
Ω
Output Impedance
LO INPUT INTERFACE
Required Input Power
Input Impedance
Return Loss
External LO operation, differential
−6
+6
dBm
Ω
dB
100
−10
Frequency Range
LO OUTPUT INTERFACE
Power1
Low-side or high-side LO
Differential
TRM_XLODRV_DRV_POUT = 01
450
2900
MHz
fLO = 900 MHz
fLO = 1800 MHz
fLO = 2700 MHz
Output Impedance
Return Loss
0
1
0
50
−10
dBm
dBm
dBm
Ω
dB
Frequency Range
Low-side or high-side LO
450
2900
MHz
POWER SUPPLY
VCC_DVGA_A and VCC_DVGA_B2
5 V mode
3.3 V mode
4.75
3.1
3.2
5.0
3.3
3.3
3.3
5.25
3.5
3.4
V
V
V
V
PLL/VCO Supplies3
RF and IF Supplies
POWER CONSUMPTION
fLO = 1050 MHz
3.1
3.5
Total
Internal LO
2.6
2.4
2.7
2.5
2.6
2.47
W
W
W
W
W
W
Internal LO, auxiliary LO output buffer disabled
Internal LO
Internal LO, auxiliary LO output buffer disabled
Internal LO
fLO = 1565 MHz
fLO = 2350 MHz
Internal LO, auxiliary LO output buffer disabled
1 For details on LO output power setting, see the LO Generation Block section.
2 For the 3.3 V DVGA supply option, see the Applications Information section.
3 Design practices for the best noise performance are discussed in the Applications Information section.
Rev. A | Page 4 of 61
Data Sheet
ADRF6650
RF INPUT TO IF OUTPUT SYSTEM SPECIFICATIONS
VCC_DVGA_A/VCC_DVGA_B = 5 V, remaining supplies = 3.3 V, TA = 25°C, low-side LO injection, fIF = 184 MHz, internal LO, maximum
gain setting, 5 V high performance settings, unless otherwise noted. All losses from input and output traces and baluns are de-embedded
from results.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE AT RF Frequency
(fRF) = 900 MHz
High-side LO
Power Gain
Output 1 dB Compression Point (OP1dB)
30
16
8
dB
Maximum gain
Gain = 1 dB
dBm
dBm
dBm
Output Third-Order Intercept Point (OIP3) Output power (POUT) = −4 dBm/tone, 1 MHz to 40 MHz
separation
44
Maximum gain minus 16 dB, POUT = −4 dBm/tone, 1 MHz to
40 MHz separation
38
dBm
Noise Figure
Maximum gain and maximum gain minus 5 dB
Internal LO, 3 MHz offset blocking, PIN = 0 dBm, POUT = 1 dBm
PIN = 0 dBm, POUT = 1 dBm
9.5
21
dB
dB
Noise Figure Under Blocker
Second Harmonic Distortion (HD2)
Third Harmonic Distortion (HD3)
LO to IF Leakage
LO to RF Leakage
RF to IF Leakage
−66.7
−58
−22.5
−54
−46
52
dBc
dBc
dBm
dBm
dBc
dBc
PIN = 0 dBm, POUT = 1 dBm
Isolation
Channel to channel
DYNAMIC PERFORMANCE AT fRF = 1800 MHz Low-side LO
Power Gain
29
16
9
43
41
dB
OP1dB
Maximum gain
dBm
dBm
dBm
dBm
Gain = 1 dB
OIP3
POUT = −4 dBm/tone, 1 MHz to 40 MHz separation
Maximum gain minus 16 dB, POUT = −4 dBm/tone, 1 MHz to
40 MHz separation
Noise Figure
Noise Figure Under Blocker
Maximum gain and maximum gain minus 5 dB
Internal LO, 3 MHz offset blocking, input power (PIN) = 0 dBm,
11
22.5
dB
dB
POUT = 1 dBm
HD2
HD3
LO to IF Leakage
LO to RF Leakage
RF to IF Leakage
Isolation
PIN = 0 dBm, POUT = 1 dBm
PIN = 0 dBm, POUT = 1 dBm
−75
−67
−37.5
−55
−68
50
dBc
dBc
dBm
dBm
dBc
dBc
Channel to channel
DYNAMIC PERFORMANCE AT fRF = 2700 MHz High-side LO
Power Gain
29
16
9
43.5
40
dB
OP1dB
Maximum gain
dBm
dBm
dBm
dBm
Gain = 1 dB
OIP3
POUT = −4 dBm/tone, 1 MHz to 40 MHz separation
Maximum gain minus 16 dB, POUT = −4 dBm/tone, 1 MHz to
40 MHz separation
Noise Figure
Noise Figure Under Blocker
HD2
Maximum gain and maximum gain minus 5 dB
Internal LO, 3 MHz offset blocking, PIN = 0 dBm, POUT = 1 dBm
PIN = 0 dBm, POUT = 1 dBm
11.5
23.5
−59
−63
−43
−46
−81
57
dB
dB
dBc
dBc
dBm
dBm
dBc
dBc
HD3
PIN = 0 dBm, POUT = 1 dBm
LO to IF Leakage
LO to RF Leakage
RF to IF Leakage
Isolation
Channel to channel
Rev. A | Page 5 of 61
ADRF6650
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
MxN SPURS
See the Spurious Performance section
RF TO IF DELAY DIFFERENCE BETWEEN
CHANNELS
Channel A = 5 dB attenuation, Channel B sweep
attenuation from 0 dB to 40 dB
1
1
ns
µs
TDD SWITCH TIME
Level sensitive, from effective level of control signal to
99%/1% of final RF signal level; the amplitude response,
phase response, and group delay must all be settled in this
time interval
2
GAIN CONTROL SPECIFICATIONS
Table 3.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
GAIN ADJUSTMENT
Range
Step
43
1
dB
dB
Gain Step Error
Cumulative Gain Error
Phase Error
Between any two adjacent steps
Error vs. line (maximum gain reference)
fRF = 200 MHz and with 20 dB gain change
At any gain settings, this specification must be met with
any gain adjustment between 1 dB to 16 dB and the
output power settled within 1 dB of the final value
0.2
dB
dB
Degrees
ns
1
10
15
Gain Adjustment Setting Time
Gain Adjustment Setting Time
At any gain settings, this specification must be met with
any gain adjustment between 1 dB to 16 dB and the
output power settled within 0.1 dB of the final value
70
ns
PLL/VCO SPECIFICATIONS
VCC_x and VCC_DVGA_A/VCC_DVGA_B = 5 V, remaining supplies = 3.3 V, TA = 25°C, fREF = 122.88 MHz, fREF power = 2.5 V p-p,
PFD frequency (fPFD) = 30.72 MHz, charge pump current setting of 7, and loop filter bandwidth = 20 kHz, unless otherwise noted.
Table 4.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
PLL REFERENCE
PLL Reference Frequency
PLL Reference Level
10
0.7
30.72
250
3.3
MHz
V p-p
For PLL lock condition, 50 Ω to ground required
close to REF_IN pin
Step Size
Lock Time
240
0.4
kHz
ms
PFD FREQUENCY
30.72
61.44
8000
MHz
MHz
INTERNAL VCO RANGE
OPEN-LOOP VCO PHASE NOISE
VCO Frequency (fVCO) = 4200 MHz
4000
10 kHz offset
100 kHz offset
1 MHz offset
10 MHz offset
10 kHz offset
100 kHz offset
1 MHz offset
10 MHz offset
10 kHz offset
100 kHz offset
1 MHz offset
10 MHz offset
−86
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−112
−133
−153
−84
−112
−134
−154
−83
fVCO = 4700 MHz
fVCO = 5440 MHz
−110
−132
−152
Rev. A | Page 6 of 61
Data Sheet
ADRF6650
Parameter
Test Conditions/Comments
10 kHz offset
100 kHz offset
1 MHz offset
10 MHz offset
10 kHz offset
100 kHz offset
1 MHz offset
Min
Typ
Max
Unit
fVCO = 6260 MHz
−82
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−108
−130
−150
−80
−106
−127
−147
fVCO = 7060 MHz
10 MHz offset
SYNTHESIZER SPECIFICATIONS
Fractional Figure of Merit (FOM)
Flicker FOM
−227
−262
dBc/Hz
dBc/Hz
fPFD Spurs1
At the input of internal mixer and daisy-chained
ADRF6650 mixer
fPFD × 1
fPFD × 2
−90
−95
−95
−70
dBc
dBc
dBc
dBc
fPFD × 3 and Higher
Unwanted Spurs (Other Than PFD and
Harmonics)1
At the input of internal mixer and daisy-chained
ADRF6650 mixer
LO Frequency (fLO) = 1050 MHz, fVCO
4200 MHz
=
Closed-Loop Phase Noise
1 kHz offset
10 kHz offset
100 kHz offset
600 kHz offset
800 kHz offset
1.6 MHz offset
3 MHz offset
10 MHz offset
−110
−107
−122
−141
−143
−149
−153
−157
−159
0.08
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
100 MHz offset
100 Hz to 10 MHz integration bandwidth
Integrated Phase Noise and Spurs
fLO = 1565 MHz, fVCO = 6260 MHz
Closed-Loop Phase Noise
1 kHz offset
10 kHz offset
100 kHz offset
600 kHz offset
800 kHz offset
1.6 MHz offset
3 MHz offset
10 MHz offset
−106
−102
−119
−137
−140
−145
−151
−156
−157
0.13
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
100 MHz offset
100 Hz to 10 MHz integration bandwidth
Integrated Phase Noise and Spurs
fLO = 1765 MHz, fVCO = 7060 MHz
Closed-Loop Phase Noise
1 kHz offset
10 kHz offset
100 kHz offset
950 kHz offset
2.1 MHz offset
3.5 MHz offset
7.5 MHz offset
10 MHz offset
−102
−97
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
−117
−138
−145
−149
−153
−156
−158
0.2
100 MHz offset
100 Hz to 10 MHz integration bandwidth
Integrated Phase Noise and Spurs
Rev. A | Page 7 of 61
ADRF6650
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
fLO = 2350 MHz, fVCO = 4700 MHz
Closed-Loop Phase Noise
1 kHz offset
10 kHz offset
100 kHz offset
950 kHz offset
2.1 MHz offset
3.5 MHz offset
7.5 MHz offset
10 MHz offset
−103
−101
−116
−140
−147
−151
−156
−156
−157
0.16
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
100 MHz offset
100 Hz to 10 MHz integration bandwidth
Integrated Phase Noise and Spurs
fLO = 2720 MHz, fVCO = 5440 MHz
Closed-Loop Phase Noise
1 kHz offset
10 kHz offset
100 kHz offset
950 kHz offset
2.1 MHz offset
3.5 MHz offset
7.5 MHz offset
10 MHz offset
−102
−99
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
−114
−137
−144
−148
−153
−155
−156
0.2
100 MHz offset
100 Hz to 10 MHz integration bandwidth
Integrated Phase Noise and Spurs
1 Auxiliary LO output measurements are performed under daisy-chain configuration with another ADRF6650 device. Measurements are taken from the auxiliary LO
output of the daisy-chained ADRF6650.
DIGITAL LOGIC SPECIFICATIONS
Table 5.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
ALL DIGITAL INPUTS/OUTPUTS
Input Voltage
Logic Low
VIL
VIH
0
1.2
0.5
3.6
V
V
Logic High
Input Current
Logic High
Logic Low
IIH
IIL
−100
−100
+100
+100
µA
µA
Output Voltage
Logic Low
Logic High
VOL
VOH
0
1.4
0.4
1.8
V
V
When driving loads with complementary metal-
oxide semiconductor (CMOS) 1.8 V interface
When driving loads with CMOS 3.3 V interface
2.4
3.3
V
Output Driving Current
Logic High
Logic Low
IOH
IOL
1
1
2
2
mA
mA
Rev. A | Page 8 of 61
Data Sheet
ADRF6650
Serial Peripheral Interface (SPI) Timing
Table 6.
Parameter
Description
Min
8
8
50
25
25
10
30
18
Typ
Max
Unit
ns
ns
ns
ns
tDS
tDH
tCLK
tHIGH
tLOW
tS
SDI to SCLK rising edge setup
SCLK rising edge to SDI hold
Period of SCLK
High width of SCLK
Low width of SCLK
CS falling edge to SCLK rising edge, setup time
SCLK rising edge to CS rising edge, hold time
SCLK falling edge to valid readback data, SDIO/SDO; not shown in Figure 2
ns
ns
tC
ns
tDV
ns
SPI Timing Diagram
tHIGH
DS
CLK
tC
tLOW
S
DH
CS
DON'T CARE
DON'T CARE
DON'T CARE
R/W
A10
A9
DON'T CARE
Figure 2. Serial Control Port Write Timing—MSB First, 16-Bit Instruction
Rev. A | Page 9 of 61
ADRF6650
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 7.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
Rating
VCC_MIX_A, VCC_LOA_S2, VCC_LOA_S1,
VCC_LOB_S1, VCC_LOB_S2, VCC_MIX_B,
MIX_PU_A+, MIX_PU_A−, MIX_PU_B+,
MIX_PU_B−
−0.3 V to +3.6 V
Typical θJA and θJC are specified vs. the number of PCB layers.
The use of appropriate thermal management techniques is
recommended to ensure that the maximum junction
temperature does not exceed the limits shown in Table 7.
VCC_DVGA_B, VCC_DVGA_A
−0.3 V to +5.4 V
VCCVCO_3V3, VCCDIV_3V3, VCCFBDIV_3V3, −0.3 V to +3.6 V
VCCLO_MIX_3V3, VCCLO_AUX_3V3,
VCCCP_3V3, VCCPFD_3V3, VCCREF_3V3,
VBAT_DIG_3V3
Table 8. Thermal Resistance
Package Type
θJA
θJC
Unit
RF Input Power (RFIN_A, RFIN_B)
External LO Input Power
VTUNE, CPOUT, REF_IN, DCL_BIAS
TDD_A, TDD_B, RXA_ATT_CLK,
RXA_ATT_DATA, RXB_ATT_CLK,
RXB_ATT_DATA
20 dBm
CP-56-161
10 dBm differential
−0.3 V to +3.6 V
−0.3 V to +3.6 V
JEDEC 1s0p Board2
Cold Plate Only, No PCB3
JEDEC 2s2p Board2
N/A4
N/A4
29.3
3.3
2.8
N/A
°C/W
°C/W
°C/W
1 The maximum junction temperature of 125°C cannot be exceeded.
2 Per JEDEC JESD51-12.
SCLK, SDIO, SDO, CS
−0.3 V to +3.6 V
125°C
−40°C to +105°C
3 For nonstandardized testing where the paddle of the device is directly
connected to a cold plate. This approach can be useful to estimate junction
temperature when the exact paddle temperature is known in the application.
4 N/A means not applicable.
Maximum Junction Temperature
Operating Temperature Range
(Measured at Pad)
Storage Temperature Range
−65°C to +150°C
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A | Page 10 of 61
Data Sheet
ADRF6650
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VCC_MIX_A
TDD_A
1
2
3
4
5
6
7
8
9
42 VCCCP_3V3
41 CPOUT
40 GND
GND
RFIN_A
39 LO_OUT–
RFBT_A
38 LO_OUT+
37 VCCLO_AUX_3V3
36 VCCLO_MIX_3V3
35 VCCFBDIV_3V3
34 VCCDIV_3V3
33 VCCVCO_3V3
32 EXT_LO_IN–
31 EXT_LO_IN+
30 VTUNE
VCC_LOA_S2
VCC_LOA_S1
VCC_LOB_S1
VCC_LOB_S2
ADRF6650
TOP VIEW
(Not to Scale)
RFBT_B 10
RFIN_B 11
GND 12
TDD_B 13
29 DCL_BIAS
VCC_MIX_B 14
NOTES
1. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO A GROUND PLANE
WITH LOW THERMAL IMPEDANCE.
Figure 3. Pin Configuration
Table 9. Pin Function Descriptions
Pin No. Mnemonic
Description
1
2
3
VCC_MIX_A
TDD_A
GND
Channel A Mixer IF Amplifier VCC
TDD Enable, Channel A.
Ground.
.
4
5
6
7
8
9
RFIN_A
RFBT_A
Channel A Single-Ended, RF, 50 Ω Input.
Channel A RF Balun Low Frequency Inductor Connection.
Channel A LO Path VCC (Stage 3 and Stage 4).
Channel A LO Path VCC (Stage 1 and Stage 2).
Channel B LO Path VCC (Stage 1 and Stage 2).
Channel B LO Path VCC (Stage 3 and Stage 4).
Channel B RF Balun Low Frequency Inductor Connection.
Channel B Single-Ended, RF, 50 Ω Input.
Ground.
TDD Enable, Channel B.
Channel B Mixer IF Amplifier VCC.
Channel B Mixer IF Amplifier Positive Output Pull-Up.
Channel B Mixer IF Amplifier Negative Output Pull-Up.
Channel B Variable Gain Amplifier (VGA) Decouple Output.
Channel B VGA Negative Output.
VCC_LOA_S2
VCC_LOA_S1
VCC_LOB_S1
VCC_LOB_S2
RFBT_B
RFIN_B
GND
TDD_B
VCC_MIX_B
MIX_PU_B+
MIX_PU_B−
VCPL_B
IFOUT_B−
IFOUT_B+
VCC_DVGA_B
RXB_ATT_DATA
RXB_ATT_CLK
LO_LCKDT
SCLK
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Channel B VGA Positive Output.
Channel B Digital Step Attenuator (DSA) and VGA VCC
Channel B VGA Serial Gain Control (Up/Down) Data.
Channel B VGA Serial Gain Control (Up/Down) Clock.
LO Lock Detect.
.
SPI Clock.
Rev. A | Page 11 of 61
ADRF6650
Data Sheet
Pin No. Mnemonic
Description
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
SDIO
SDO
CS
SPI Data Input/Output (3-Wire Mode); Input Only (4-Wire Mode).
SPI Data Output (4-Wire Mode); Not Used (3-Wire Mode).
SPI Chip Select (Active Low).
RST
Reset (Active Low).
DCL_BIAS
VTUNE
VCO Core Bias Decouple Output.
Tuning Voltage (VTUNE) Input.
External LO Positive Input.
External LO Negative Input.
VCO 3.3 V Supply.
LO Chain and Divider 3.3 V Supply.
PLL Feedback Divider 3.3 V Supply.
LO Mixer Output Buffer 3.3 V Supply.
LO External Output Buffer 3.3 V Supply.
External LO Positive Output.
External LO Negative Output.
Charge Pump GND.
Charge Pump Output.
Charge Pump 3.3 V Supply.
PFD 3.3 V Supply.
Reference Input Buffer 3.3 V Supply.
Reference Input Buffer.
SPI 1.8 V LDO External Decouple Output.
SDM 1.8 V LDO External Decouple Output.
SPI and SDM LDO 3.3 V Supply.
Channel A VGA Serial Gain Control (Up/Down) Clock.
Channel A VGA Serial Gain Control (Up/Down) Data.
EXT_LO_IN+
EXT_LO_IN−
VCCVCO_3V3
VCCDIV_3V3
VCCFBDIV_3V3
VCCLO_MIX_3V3
VCCLO_AUX_3V3
LO_OUT+
LO_OUT−
GND
CPOUT
VCCCP_3V3
VCCPFD_3V3
VCCREF_3V3
REF_IN
SPILDO_OUT_1V8
SDMLDO_OUT_1V8
VBAT_DIG_3V3
RXA_ATT_CLK
RXA_AT T_DATA
VCC_DVGA_A
IFOUT_A+
IFOUT_A−
VCPL_A
Channel A DSA and VGA VCC
.
Channel A VGA Positive Output.
Channel A VGA Negative Output.
Channel A VGA Decouple Output.
Channel A Mixer Amplifier Negative Output Pull-Up.
Channel A Mixer Amplifier Positive Output Pull-Up.
MIX_PU_A−
MIX_PU_A+
EPAD
Exposed Pad. The exposed pad must be connected to a ground plane with low thermal impedance.
Rev. A | Page 12 of 61
Data Sheet
ADRF6650
TYPICAL PERFORMANCE CHARACTERISTICS
VCC_DVGA_x = 5 V, VCCx = 3.3 V, TA = 27°C, fIF = 184 MHz, internal LO, digital variable gain amplifier (DVGA) attenuation = 0 dB,
LTUNE = 1 nH, LSHUNT = 150 nH, and 25 Ω external resistors on each differential leg, 5 V high power mode, low-pass filter setting = 7,
unless otherwise noted. The LO is high-side for RF frequencies lower than 1 GHz and higher than 2.5 GHz, and LO is low-side for the
remaining RF frequencies. For two-tone measurements, IF output power is −4 dBm/tone and 10 MHz tone spacing, unless otherwise
noted. All losses from input and output traces and baluns are de-embedded from results.
35
30
25
20
15
10
5
35
33
31
29
27
25
23
21
19
17
15
–40°C
+27°C
+105°C
LO FREQUENCY = 800MHz
LO FREQUENCY = 1800MHz
LO FREQUENCY = 2700MHz
0
500
940
1380
1820
2260
2700
50
125
200
275
350
425
500
RF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 4. Gain vs. RF Frequency
Figure 7. Gain vs. IF Frequency; RF Sweep with Fixed LO, LSHUNTx = 150 nH
20
35
LO FREQUENCY = 800MHz
LO FREQUENCY = 1800MHz
18
16
14
12
10
8
LO FREQUENCY = 2700MHz
30
25
20
15
10
5
6
4
–40°C
+27°C
+105°C
2
0
500
0
940
1380
1820
2260
2700
50
100
150
200
250
300
350
400
450
500
RF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 5. OP1dB vs. RF Frequency
Figure 8. Gain vs. IF Frequency; RF Sweep with Fixed LO, LSHUNTx = 47 nH
50
45
40
35
30
25
20
15
10
5
21
LO FREQUENCY = 800MHz
LO FREQUENCY = 1800MHz
19
17
15
13
11
9
LO FREQUENCY = 2700MHz
OIP3
GAIN
7
OP1dB
5
CHANNEL A
CHANNEL B
0
500
3
50
125
200
275
350
425
500
940
1380
1820
2260
2700
IF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 9. OP1dB vs. IF Frequency; RF Sweep with Fixed LO
Figure 6. OP1dB, Gain, and OIP3 vs. RF Frequency, Channel Comparison
Rev. A | Page 13 of 61
ADRF6650
Data Sheet
45
40
35
30
25
20
15
10
50
45
40
35
30
25
20
15
10
–40°C
+27°C
+105°C
–40°C
+27°C
+105°C
500 720 940 1160 1380 1600 1820 2040 2260 2480 2700
RF FREQUENCY (MHz)
500
940
1380
1820
2260
2700
RF FREQUENCY (MHz)
Figure 10. OIP3 vs. RF Frequency; Maximum Gain, LSHUNTx = 150 nH
Figure 13. OIP3 vs. RF Frequency; Maximum Gain − 16 dB, LSHUNTx = 47 nH,
IF = 368 MHz
50
50
45
40
35
30
25
20
LO FREQUENCY = 800MHz
LO FREQUENCY = 1800MHz
45
40
35
30
25
20
15
10
LO FREQUENCY = 2700MHz
15
–40°C
+27°C
+105°C
10
500
940
1380
1820
2260
2700
50
100
150
200
250
300
350
400
450
500
RF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 11. OIP3 vs. RF Frequency; Maximum Gain, LSHUNTx = 47 nH,
IF = 368 MHz
Figure 14. OIP3 vs. IF Frequency; RF Sweep with Fixed LO, Maximum Gain,
LSHUNTx = 150 nH
45
40
35
30
25
20
15
10
50
45
40
35
30
25
20
15
10
–40°C
5
–40°C
+27°C
+105°C
5
+27°C
+105°C
0
0
500
150
200
250
300
350
400
450
500
550
600
1000
1500
2000
2500
3000
3500
4000
IF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 12. OIP3 vs. RF Frequency; Maximum Gain − 16 dB, LSHUNTx = 150 nH
Figure 15. OIP3 vs. IF Frequency; RF Sweep with Fixed LO, Maximum Gain,
SHUNTx = 47 nH, IF = 368 MHz
L
Rev. A | Page 14 of 61
Data Sheet
ADRF6650
35
30
25
20
15
10
5
100
90
80
70
60
50
40
140
130
120
110
100
90
–40°C
+27°C
+105°C
0
80
–5
–10
–15
30
20
70
–40°C
+27°C
+105°C
60
0
4
8
12
16
20
24
28
32
36
40
500 720 940 1160 1380 1600 1820 2040 2260 2480 2700
DVGA ATTENUATION SETTING
RF FREQUENCY (MHz)
Figure 16. HD2 and HD3 vs. RF Frequency, Maximum Gain
Figure 19. Gain vs. DVGA Attenuation Setting, RF = 2700 MHz
90
80
70
60
50
40
30
20
10
0
130
18
16
14
12
10
8
120
110
100
90
80
70
6
60
4
–40°C
2
50
+27°C
+105°C
0
40
2700
450
900
1350
1800
2250
0
5
10
15
20
25
30
35
40
RF FREQUENCY (MHz)
DVGA ATTENUATION SETTING
Figure 17. HD2 and HD3 vs. RF Frequency, Gain = 1 dB
Figure 20. OP1dB vs. DVGA Attenuation Setting, RF = 2700 MHz
20
50
–40°C
+27°C
+105°C
LO FREQUENCY = 800MHz
LO FREQUENCY = 1800MHz
45
18
16
14
12
10
8
LO FREQUENCY = 2700MHz
40
35
30
25
20
15
10
5
6
4
700
0
1200
1700
2200
2700
30
26
22
18
14
10
6
2
–2
–6
RF FREQUENCY (MHz)
GAIN (dB)
Figure 18. Noise Figure vs. RF Frequency; Maximum Gain
Figure 21. OIP3 vs. Gain for Various LO Frequencies
Rev. A | Page 15 of 61
ADRF6650
Data Sheet
30
25
20
15
10
12
10
8
–40°C
+27°C
+105°C
6
4
2
0
–2
–4
5
29
24
19
14
9
4
–1
–6
0
4
8
12
16
20
24
28
32
36
40
GAIN (dB)
DVGA ATTENUATION SETTING
Figure 22. Noise Figure vs. Gain, RF = 2100 MHz
Figure 25. Cumulative Phase Error vs. DVGA Attenuation Setting,
RF = 2700 MHz
30
25
20
15
10
5
70
60
50
40
30
20
10
–40°C
RF FREQUENCY = 950MHz
RF FREQUENCY = 1850MHz
+27°C
+105°C
0
450
0
–8
–6
–4
–2
0
2
4
6
8
10
900
1350
1800
2250
2700
BLOCKER OUTPUT POWER (dBm)
RF FREQUENCY (MHz)
Figure 23. Noise Figure Under Blocker vs. Blocker Output Power,
PIN = 0 dBm, Internal LO
Figure 26. Channel to Channel Isolation vs. RF Frequency
1.5
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–40°C
+27°C
+105°C
1.0
–40°C
+27°C
+105°C
0.5
0
–0.5
–1.0
–1.5
0
4
8
12
16
20
24
28
32
36
40
500
940
1380
1820
2260
2700
DVGA ATTENUATION SETTING
RF FREQUENCY (MHz)
Figure 24. Cumulative Gain Error vs. DVGA Attenuation Setting,
RF = 2700 MHz
Figure 27. RF to IF Feedthrough vs. RF Frequency
Rev. A | Page 16 of 61
Data Sheet
ADRF6650
0
0
–2
–40°C
+27°C
+105°C
–10
–4
–20
–30
–40
–50
–60
–70
–6
–8
–10
–12
–14
–16
650
1100
1550
2000
2450
2900
2900
2900
0
100
200
300
400
500
LO FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 28. LO to IF Feedthrough vs. LO Frequency
Figure 31. IF Output Return Loss , External 25 Ω on Each Differential Leg
0
0
–5
–40°C
+27°C
+105°C
–10
–10
–15
–20
–25
–30
–35
–40
–20
–30
–40
–50
–60
–70
550
1020
1490
1960
2430
450
900
1350
1800
2250
2700
LO FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 29. LO to RF Feedthrough vs. LO Frequency
Figure 32. RF Input Return Loss
500
450
400
350
300
250
200
150
100
50
PLL/VCO 3.3V
RF/IF 3.3V
DVGA 5V
0
700
1140
1580
2020
2460
LO FREQUENCY (MHz)
Figure 30. RF/IF 3.3 V, DVGA 5 V, and PLL/VCO 3.3 V Supply Currents vs.
LO Frequency
Rev. A | Page 17 of 61
ADRF6650
Data Sheet
PHASE-LOCKED LOOP (PLL)
VCC_DVGA_x = 5 V, VCCx = 3.3 V, TA = 27°C, fPFD = 30.72 MHz, fREF = 122.88 MHz, 20 kHz loop filter, measured at the LO output,
unless otherwise noted. All losses from input and output traces and baluns are de-embedded from results.
0
–10
–60
–40°C
+27°C
+105°C
–70
–20
–30
–80
–40
–90
–50
–60
–100
–110
–120
–130
–140
–150
–160
–170
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
0.001
0.01
0.1
1
10
100
0.001
0.01
0.1
1
10
100
OFFSET FREQUENCY (MHz)
OFFSET FREQUENCY (MHz)
Figure 33. Open-Loop VCO Phase Noise vs. Offset Frequency, fLO = 2350 MHz,
VCO = 4700 MHz
Figure 36. Closed-Loop Phase Noise vs. Offset Frequency for fLO = 1765 MHz
f
–60
–70
0
–10
VCO = 4GHz
VCO = 4.7GHz
VCO = 5.6GHz
VCO = 6.8GHz
–20
–30
–80
–40
–90
–50
–60
–100
–110
–120
–130
–140
–150
–160
–170
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
0.001
0.01
0.1
1
10
100
0.001
0.01
0.1
1
10
100
OFFSET FREQUENCY (MHz)
OFFSET FREQUENCY (MHz)
Figure 34. Open-Loop VCO Phase Noise vs. Offset Frequency, for Various VCO
Frequencies, Divide by 2 Selected
Figure 37. Closed-Loop Phase Noise vs. Offset Frequency for fLO = 2350 MHz
–60
–70
–60
–70
–80
–80
–90
–90
–100
–110
–120
–130
–140
–150
–160
–170
–100
–110
–120
–130
–140
–150
–160
–170
0.001
0.01
0.1
1
10
100
0.001
0.01
0.1
1
10
100
OFFSET FREQUENCY (MHz)
OFFSET FREQUENCY (MHz)
Figure 35. Closed-Loop Phase Noise vs. Offset Frequency for fLO = 1565 MHz
Figure 38. Closed-Loop Phase Noise vs. Offset Frequency for fLO = 2720 MHz
Rev. A | Page 18 of 61
Data Sheet
ADRF6650
–170
–50
–60
–40°C
–40°C
+27°C
+105°C
+27°C
–180
+105°C
–190
–200
–210
–220
–230
–240
–250
–260
–270
–70
FRACTIONAL
–80
–90
–100
FLICKER
–110
450
940
1430
1920
2410
2900
450
940
1430
1920
2410
2900
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 39. PLL Figure of Merit (FOM) vs. LO Frequency
Figure 42. Reference Spurs vs. LO Frequency, 1 × fPFD Offset,
Daisy-Chain Measurement
–50
–60
–50
–40°C
+27°C
+105°C
–40°C
+27°C
+105°C
–70
–60
–70
–80
10kHz
–90
–100
–110
–120
–130
–140
–150
–160
–170
–80
100kHz
–90
1MHz
10MHz
–100
–110
450
940
1430
1920
2410
2900
450
940
1430
1920
2410
2900
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 40. Closed-Loop LO Phase Noise vs. LO Frequency for
Various Offset Frequencies
Figure 43. Reference Spurs vs. LO Frequency, 2 × fPFD Offset,
Daisy-Chain Measurement
–50
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
PFD × 3
PFD × 4
PFD × 5
PFD × 6
PFD × 7
–40°C
+27°C
+105°C
–60
–70
–80
–90
–100
–110
450
940
1430
1920
2410
2900
450
940
1430
1920
2410
2900
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 41. 100 Hz to 10 MHz Integrated Phase Noise vs. LO Frequency
Figure 44. Reference Spurs vs. LO Frequency, 3 and Higher × fPFD Offset,
Daisy-Chain Measurement
Rev. A | Page 19 of 61
ADRF6650
Data Sheet
0
2101.5
2101.0
2100.5
2100.0
2099.5
2099.0
2098.5
HD2
HD3
–10
–20
–30
–40
–50
–60
1000
1380
1760
2140
2520
2900
2900
2900
0
100
200
300
400
500
600
LO FREQUENCY
TIME (µs)
Figure 45. LO HD2/HD3 vs. LO Frequency
Figure 48. LO Frequency Settling Time, fLO = 2.1 GHz
10
0
–5
–40°C
EXTERNAL LO INPUTS
AUXILIARY LO OUTPUTS
+27°C
8
+105°C
6
4
–10
–15
–20
–25
–30
–35
–40
2
0
–2
–4
–6
–8
–10
450
940
1430
1920
2410
450
940
1430
1920
2410
2900
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 46. LO Output Power vs. LO Frequency
Figure 49. Auxiliary Output Return Loss, External LO Input Return Loss vs.
LO Frequency
20
16
12
8
LO OUT LEVEL = 0
LO OUT LEVEL = 1
LO OUT LEVEL = 2
LO OUT LEVEL = 3
4
0
–4
–8
–12
–16
–20
450
940
1430
1920
2410
LO FREQUENCY (MHz)
Figure 47. LO Output Power vs. LO Frequency, for Various
Output Power Level Settings
Rev. A | Page 20 of 61
Data Sheet
ADRF6650
SPURIOUS PERFORMANCE
(N × fRF) − (M × fLO) spur measurements were made using the standard evaluation board. Mixer spurious products were measured in
decibels (dB) relative to the carrier (dBc) from the IF output power level. IF = 184 MHz, and RF spur frequency is found with the formula;
fRF_SPUR = ((M × fLO) + fIF))/N. Data is shown for all spurious components greater than −115 dBc and frequencies of less than 2.7 GHz.
Table 10. 900 MHz Spurious Performance
N
1
2
3
4
5
6
M = 1
M = 2
M = 3
M = 4
M = 5
M = 6
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
−53
−84
Not applicable
Not applicable
Not applicable
Not applicable
−10.5
Not applicable
−115
Not applicable
Not applicable
Not applicable
−49
−17
Not applicable
−115
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Rev. A | Page 21 of 61
ADRF6650
Data Sheet
THEORY OF OPERATION
The ADRF6650 is a wideband, highly integrated, dual-channel
downconverter ideally suited for multiple input, multiple output
(MIMO) applications. Additionally, the ADRF6650 integrates an
LO generation block consisting of a synthesizer and a multicore
VCO with an octave range and low phase noise. The synthesizer
uses a fractional-N PLL to enable continuous LO coverage from
450 MHz to 2900 MHz. The wideband frequency response and
flexible frequency programming simplifies the receiver design,
saves on-board space, and minimizes the need for external
components.
In addition, the input side of the LPF has a series 50 Ω resistor
on each differential leg which improves the mixer termination
for low RF frequencies (<1 GHz). The resistors can be bypassed
by DPLX_EN_OVERRIDE (Register 0x0300, Bit 0).
IF AMPLIFIERS
The IF amplifier following the LPF is a fixed gain, balanced
feedback design that simultaneously provides the desired gain,
noise figure, and input impedance that is required to achieve
the overall performance. The balanced open-collector output of
the IF amplifier, with an impedance modified by the feedback
within the amplifier, connects internally to the DSA stage, but
requires external pull-up inductors of approximately 220 nH.
It is also possible to use a tuned load to improve the filtering of
unwanted mixing products but can limit the signal bandwidth
for wide bandwidth applications.
The RF subsystem of the ADRF6650 consists of an integrated,
wideband, low loss RF balun; a double balanced, passive metal-
oxide semiconductor field-effect transistor (MOSFET) mixer; a
tunable filter; a fixed gain IF amplifier; a DVGA, and fractional
synthesizer with on-chip VCO.
PULL-UP
INDUCTORS
RF BALUN
VCC_3V3
The ADRF6650 integrates a wideband balun operating over a
frequency range from 450 MHz to 2700 MHz. The RF balun
offers the benefit of ease of drivability from a single-ended 50 Ω
RF input, and the single-ended to differential conversion of the
balun optimizes common-mode rejection. The balun uses an
external compensation inductor to improve the balance for low
RF frequency. See the RF Frequency and IF Bandwidth
Optimization section for details.
VCC_3V3
BAND
OPTIMIZATION
INDUCTOR
MIX_PU_A+
MIX_PU_A–
IF AMPLIFIER
DSA
DVGA
Figure 50. External Pull-Up Inductor Connection
MIXERS
The IP3 performance can be optimized by adjusting the low-
pass filter between the mixer and the IF amplifier. Further
optimization can be made, via SPI control, by adjusting the IF
main bias current, IFMAIN_BIAS_OVERRIDE (Register 0x0301,
Bits[3:0]), and a linearizing optimization current, IFLIN_BIAS_
OVERRIDE (Register 0x0302, Bits[3:0]). The linearization current
generally maintains the same IP3 for a given IF frequency but
may need to be adjusted for different IF frequencies.
The output of the balun is applied to a passive mixer that
commutates the RF input in accordance with the output of the
LO subsystem. The passive mixer is essentially a balanced, low
loss switch that adds minimum noise to the frequency translation.
The only noise contribution from the mixer is due to the resistive
loss of the switches, which is in the order of a few ohms.
LOW-PASS FILTERS
Because the mixer is inherently broadband and bidirectional,
it is necessary to properly terminate all idler (M × N product)
frequencies generated by the mixing process. Terminating the
mixer avoids the generation of unwanted intermodulation
products and reduces the level of unwanted signals at the input
of the IF amplifier, where high peak signal levels can compromise
the compression and intermodulation performance of the
system. This termination is accomplished by the addition of a
programmable low-pass filter (LPF) network between the IF
amplifier and the mixer and in the feedback elements in the IF
amplifier. The LPF filter has programmable filter bandwidths
and is tuned by switching parallel capacitances on the primary
and secondary sides by writing to the LPF_OVERRIDE register
(Register 0x0300). Therefore, selecting the proper combination
of LPF1_OVERRIDE (Register 0x0300, Bits[3:1]) and
DVGA
The ADRF6650 integrates a differential variable gain amplifier
consisting of a differential, digitally controlled passive
attenuator (DSA) followed by a DVGA. The total attenuation
range is 43 dB, in 1 dB steps, with the first 12 dB of attenuation
provided by the DVGA and the remaining 31 dB provided by
the DSA. The 12 dB of attenuation from the DVGA has less
than 1 dB degradation of the ADRF6650 noise figure for the
entire 12 dB range. The OIP3 also remains nearly constant over
that attenuation range, as shown in Figure 21. The input
digitally controlled binary weighted attenuator has a 31 dB
range in 1 dB steps. The noise figure for this attenuator
increases 1 dB for each dB of attenuation of this 31 dB
attenuation range.
LPF2_OVERRIDE (Register 0x0300, Bits[6:4]) sets the desired
bandwidth. It is recommended to set the LPF1_OVERRIDE and
LPF2_OVERRIDE bit fields to the same value.
Rev. A | Page 22 of 61
Data Sheet
ADRF6650
Output Impedance and Matching
SPI Mode
The differential output impedance of each channel of the
ADRF6650 is 10 Ω. External series resistors are required to
increase the output impedance for matching considerations, but
reduce the maximum output power of the ADRF6650. A series
resistor of 25 Ω on each differential leg of each output provides
a −10 dB return loss for a 100 Ω differential load and the
maximum output power.
In SPI mode, the DVGA gain is controlled by DVGA_GAIN1
(Register 0x0104, Bits[5:0]) and DVGA_GAIN2 (Register 0x0104,
Bits[5:0]), as shown in Table 12.
Table 12. DVGA Attenuation Setting
DVGA_GAIN_CH1 (Register 0x0104,
Bits[5:0]) and DVGA_GAIN_CH2
(Register 0x0105, Bits[5:0])
Attenuation
Power Supply and Common Mode
000000
000001
…
101010
101011
0
1
…
42
43
The DVGA in each channel of the ADRF6650 can be powered
either at 3.3 V or 5.0 V through the VCC_DVGA_A and VCC_
DVGA_B pins. A 5.0 V supply provides increased performance,
mainly in OIP3 and in OP1dB but results in increased power
consumption. The current consumption of the DVGA is main-
tained at the same level for each power voltage (approximately
75 mA) and is controlled by DVGA_5V_SEL (Register 0x0103,
Bit 7). If desired, the current can be reduced for lower power
consumption and reduced performance. The performance mode
select is controlled by DVGA_HP_SEL (Register 0x0104, Bit 6).
Up/Down Mode
The up/down interface reuses the RXx_ATT_DATA and RXx_
ATT_CLK pins to control the gain. Gain is increased by a clock
pulse on RXx_ATT_CLK (rising edges) when RXx_ATT_DATA
is low. Gain is decreased by a clock pulse on RXx_ATT_CLK
when RXx_ATT_DATA is high. Reset is detected by a rising
edge latching data having one polarity with the falling edge
latching the opposite polarity. Reset results in minimum gain
code 111111 (binary).
TheADRF6650 is also flexible in terms of input/output
coupling. It can be ac-coupled or dc-coupled at the outputs
within the specified output common-mode levels of 1.2 V to
2.8 V, depending on the supply voltage. The output common-
mode voltage can be set by VCPL_A and VCPL_B, which allows
the driving of an analog-to-digital converter (ADC) directly
without external components. If no external output common-
mode voltage is applied, the output common mode is VCC/2.
RXx_ATT_DATA
RXx_ATTN_CLK
Gain Control Modes
UP
DOWN
RESET
The attenuation of the DVGA can be controlled by several
different modes:
Figure 51. Up/Down Data and Clock Bit Sequence
The step size is selectable via DVGA_UPDN_STEP
(Register 0x0103, Bits[4:3]), as shown in Table 13. The default
step size is 1 dB. The gain code count rails at the top and
bottom of the control range.
•
SPI mode through a dedicated register for each channel in
the main SPI.
•
Up/down mode through the serial gain control 2-wire SPI
port for each channel.
Table 13. Up/Down Step Size
DVGA_UPDN_STEP
(Register 0x0103, Bits[4:3])
The mode is set by DVGA_GAIN_MODE (Register 0x0103,
Bits[2:0]) as shown in Table 11. The attenuation setting at any
configuration can be read from the ATTEN_READBACK_CH1
register (Register 0x003C) and ATTEN_READBACK_CH2
register (Register 0x003D) for Channel A and Channel B,
respectively. When the gain control mode is changed between
different modes, a reset needs to be issued through DVGA_
CH1_RSTB (Register 0x0021, Bit 1) and DVGA_CH2_RSTB
(Register 0x0021, Bit 0) to the Channel A DVGA and
Step Size
00
01
10
11
1
2
4
8
Channel B DVGA, respectively. See the description details for
the DVGA_CH1_RSTB and DVGA_CH2_RSTB registers.
Table 11. DVGA Gain Modes
DVGA_GAIN_MODE
(Register 0x0103, Bits[2:0])
DVGA Mode
SPI
Up/down
01
11
Rev. A | Page 23 of 61
ADRF6650
Data Sheet
Internal LO Mode
TDD OPERATION
For internal LO mode, the ADRF6650 uses the on-chip PLL and
VCO to synthesize the frequency of the LO signal. The PLL,
shown in Figure 52, consists of a reference path, phase and
frequency detector (PFD), charge pump, and a programmable
integer divider with a prescaler. The reference path takes in a
reference clock and divides it down by a value calculated with
the R divider together with doubler bit and prescaler bit. Then
the divided down reference signal passes to the PFD. The PFD
compares this signal to the divided down signal from the VCO.
The PFD sends an up/down signal to the charge pump if the
VCO signal is slow/fast compared to the reference frequency.
The charge pump sends a current pulse to the off-chip loop
filter to increase or decrease the tuning voltage (VTUNE).
The ADRF6650 provides two separate pins to control the
channels (enable/disable) in TDD operation. When the TDD_A
(Pin 2) and TDD_B (Pin 13) pins are pulled low, Channel A and
Channel B are active, respectively. When TDD_A and TDD_B
are pulled high, the channels are disabled.
The ADRF6650 also provides TDD enable masks to enable/
disable certain blocks during TDD operation. The TDD enable
masks select which blocks are disabled during TDD off time.
The EN_MASK register (Register 0x0102) includes the mask
bits for the LO stages, the IF amplifiers, the DVGAs, and the
PLL. When set to 1, the bits shown in Table 14 disable the
related block during TDD off time. The enable mask bits for
the LO Stage 23, the IF amplifiers, and the DVGA disable the
related block (when set to 1) when either one of the TDD_A
and TDD_B pins is set to high. Alternatively, the LO_STG1_
ENB_MASK bit (Register 0x0102, Bit 0) disables the LO stage
amplifier only when both TDD_A and TDD_B are high. In the
same manner, the PLL_ENB_CH12_MASK bit (Register 0x0102,
Bit 7) disables the PLL/VCO only when both TDD_A and
TDD_B are high.
The ADRF6650 integrates a multicore VCO covering an octave
range of 4 GHz to 8 GHz. The suitable VCO is selected with the
autotune functionality built in the chip. After the user determines
the necessary register values, a write to the INT_L register
(Register 0x1200) initiates the autotune process.
LO Frequency and Dividers
The signal originating from the VCO or the external LO inputs
goes through a series of dividers before it is buffered to drive
the mixer. The programmable divide by two stages divide the
frequency of the incoming signal by 1, 2, 4, 8, and 16 before
reaching to the mixers. The control bits (Register 0x1414, Bits[4:0])
needed to select the different LO frequency ranges are listed in
Table 15.
Table 14. TDD Enable Mask Register (Register 0x0102)
TDD Enable Mask Bit
LO_STG1_ENB_MASK
LO_STG23_ENB_CH1_MASK
LO_STG23_ENB_CH2_MASK
IF_ENB_CH1_MASK
Default Block
0
1
1
1
1
1
1
0
LO Stage 1
Channel A LO Stage 23
Channel B LO Stage 23
Channel A IF amplifier
Channel B IF amplifier
Channel A DVGA
Channel B DVGA
PLL
IF_ENB_CH2_MASK
Table 15. Output Divide Ratio for Frequency Ranges
DVGA_ENB_CH1_MASK
DVGA_ENB_CH1_MASK
PLL_ENB_CH12_MASK
LO Frequency
(MHz)
OUT_DIVRATIO
(Register 0x1414, Bits[4:0])
VCO Frequency
(MHz)
450 to 500
10000
01000
00100
00010
LO × 16
LO × 8
LO × 4
LO × 2
500 to 1000
1000 to 2000
2000 to 2900
LO GENERATION BLOCK
The ADRF6650 supports the use of both internal and external
LO signals for the mixers. The internal LO is generated by an
on-chip VCO, which is tunable over a frequency range of
4000 MHz to 8000 MHz. The output of the VCO is phase-
locked to an external reference clock through a fractional-N
PLL that is programmable through the SPI control registers. To
produce LO signals over the 450 MHz to 2900 MHz frequency
range to drive the mixers, the VCO outputs passes through an
output divider. Alternatively, an external signal can be used to
supply the LO signals to the mixers.
Rev. A | Page 24 of 61
Data Sheet
ADRF6650
AUXILIARY
LO OUTPUT
LO OUT ENABLE
REGISTER 0x1414[6]
31
32
EXT_LO_IN+
EXT_LO_IN–
SEE PLL FREQUENCY
PROGRAMMING SECTION
REGISTER 0x1414[4:0]
REF_IN
TO MIXER
OUT
DIVIDER
EXTERNAL
LOOP FILTER
R
CPOUT
41
VTUNE
45
DIVIDER
PFD
CHARGE
PUMP
30
MIX OUT ENABLE
REGISTER 0x1414[7]
SEE PLL FREQUENCY
PROGRAMMING SECTION
SEE EXTERNAL
LO MODE
SECTION
REGISTER 0x120B[1]
PRESCALER
FRAC2
MOD2
16,777,216
FRAC1 +
N = INT +
Figure 52. PLL/VCO Block Diagram
Rev. A | Page 25 of 61
ADRF6650
Data Sheet
PLL Frequency Programming
5. Calculate FRAC2 by the following equation:
The INT, FRAC1, FRAC2, and MOD values, in conjunction
with the R counter, make it possible to generate output
frequencies that are spaced by fractions of the PFD frequency
(fPFD). Calculate the VCO frequency (VCOOUT) by
FRAC2 = (N − INT) × 224 − FRAC1)) × MOD
(5)
(6)
The FRAC2 and MOD fraction results in outputs with zero
frequency error for channel spacings when
f
PFD/GCD(fPFD/fCHSP) < 16,383
where:
PFD is the frequency of the phase frequency detector.
GCD is a greatest common denominator function.
CHSP is the desired channel spacing frequency.
VCOOUT = fPFD × N
(1)
where:
f
VCOOUT is the output frequency of the VCO (without using
the output divider).
f
f
PFD is the frequency of the phase frequency detector.
After determining the necessary register values for PLL, also set
the SD_EN_FRAC0 bit (Register 0x122A, Bit 4) to 1.
N is the desired value of the feedback counter.
Calculate fPFD by
It is recommended to set the charge pump current to be 2.4 mA
by setting the CP_CURRENT bit (Register 0x122E, Bits[3:0]) to
7. Together with a 20 kHz loop filter, the charge pump current
setting results in an optimized performance.
f
PFD = REFIN × ((1 + D)/(R × (1 + T)))
(2)
where:
REFIN is the reference input frequency.
D is the reference doubler bit (Register 0x120E, Bit 3).
R is the preset divide ratio of the binary 7-bit programmable
reference counter (1 to 255) (Register 0x120C, Bits[6:0]).
Bleed Setting
The PFD circuitry compares the PFD and divided down VCO
signals. The ADRF6650 employs a bleed circuit to put the PFD
circuit in the linear operation region. The bleed circuit introduces a
delay to the incoming PFD signal, indicated as PFD_OFFSET in
Equation 7. Calculate the bleed current, BICP (Register 0x122F,
Bits[7:0]), from the desired PFD_OFFSET, as shown in
Equation 7.
T is the reference divide by 2 bit (0 or 1) (Register 0x120E, Bit 0).
N comprises
FRAC2
MOD
FRAC1 +
N = INT +
16,777,216
(3)
BICP = integer(round(float(ICP × PFD_OFFSET ×
where:
f
PFD)/960)/255))
where:
CP is the charge pump current.
(7)
INT is the 16-bit integer value (23 to 32,767 for the 4/5
prescaler, 75 to 65,535 for the 8/9 prescaler) referenced with
Register 0x1201 and Register 0x1200.
FRAC1 is the 24-bit numerator of the primary modulus (0 to
16,777,215) with Register 0x1204, Register 0x1203, and
Register 0x1202.
FRAC2 is the numerator of the 14-bit auxiliary modulus (0 to
16,383) with Register 0x1234, Bits[5:0] and Register 0x1233.
MOD is the programmable, 14-bit auxiliary fractional modulus
(2 to 16,383), referenced with Register 0x1209, Bits[5:0] and
Register 0x1208.
I
The recommended PFD_OFFSET for the 20 kHz loop filter
is 2 ns.
PLL Lock Time
The time it takes to lock the PLL after the last register is written
breaks down into two parts: VCO band calibration and loop
settling.
After writing to the last register, the PLL automatically performs
a VCO band calibration to choose the correct VCO band. This
calibration requires approximately 200 µs. After calibration
completes, the feedback action of the PLL causes the VCO to
lock to the correct frequency eventually. The speed with which
this lock occurs depends on the small signal settling of the loop.
Settling time, after calibration, depends on the PLL loop filter
bandwidth. With a 20 kHz loop filter bandwidth, the settling
time is approximately 200 µs.
Equation 3 results in a very fine frequency resolution with no
residual frequency error. To apply this formula, take the
following steps:
1. Calculate N by VCOOUT/fPFD. The integer value of this
number forms INT.
2. Subtract the INT value from the full N value.
3. Multiply the remainder by 224. The integer value of this
number forms FRAC1.
Lock Detection Control
4. Calculate MOD based on the channel spacing (fCHSP) by
The ADRF6650 provides two ways of observing lock detection.
Lock detection can be monitored from a dedicated register,
LOCK_DETECT (Register 0x124D, Bit 0). Lock detection can
also be monitored through the dedicated LO_LCKDT pin (Pin 23).
The SD_SM_2 bit (Register 0x122A, Bit 1) must be set to 0 to
observe lock detection.
MOD = fPFD/GCD(fPFD, fCHSP
)
(4)
where:
GCD(fPFD, fCHSP) is the greatest common divider of the PFD
frequency and the channel spacing frequency.
f
CHSP is the desired channel spacing frequency.
Rev. A | Page 26 of 61
Data Sheet
ADRF6650
Required PLL/VCO Settings and Register Write Sequence
SERIAL PORT INTERFACE
Configure the PLL registers accordingly to achieve the desired
frequency, and the last write must be to Register 0x1200
(INT_L). When Register 0x1200 is programmed, an internal
VCO calibration initiates, which is the last step to locking the
PLL. After the PLL locks, enable the buffer to the mixer via the
MIX_OE bit (Register 0x1414, Bit 7) to provide the LO signal to
the mixer.
The SPI of the ADRF6650 allows the user to configure the
device for specific functions or operations through a structured
register space provided inside the chip. This interface provides
the user with added flexibility and customization. Addresses are
accessed via the serial port interface and can be written to or
read from the serial port interface.
The serial port interface consists of four control lines: SCLK, SDIO,
External LO Mode
CS
SDO, and . The SPI supports both 3-wire (default) and 4-wire
modes of operation. Enable SDOACTIVE (Register 0x0000, Bit 4)
and SDOACTIVE (Register 0x0000, Bit 3) for 4-wire mode. SCLK
(serial clock) is the serial shift clock, and it synchronizes the serial
interface reads and writes. SDIO is the serial data input or the
serial data output depending on the instruction sent and the
The external LO frequency range is 450 MHz to 2900 MHz, and
the applied LO signal is fed to the mixers after passing through
the divide by 1 block. To configure for external LO mode, write
the following register sequence Table 16 and apply the differential
LO signals to Pin 31 (EXT_LO_IN+) and Pin 32 (EXT_LO_IN−).
CS
relative position in the timing frame.
is an active low control
Table 16. Register Settings for External LO Mode
CS
that gates the read and write cycles. The falling edge of , in
conjunction with the rising edge of SCLK, determines the start
Register
0x120B
0x122D
0x1240
0x1217
0x121F
0x1021
0x1414
Required Value
Description
0x00
0x00
0x03
0x00
0x40
0xD8
0xA1
Disable feedback divider
Disable PFD and CP
Disable VCO adjust
Set VCO select to a low value
Disable calibration
Disable PLL blocks
Use external LO
CS
of the frame. When
is high, all SCLK and SDIO activity is
ignored. See Table 6 for the serial timing and its definitions.
The ADRF6650 protocol consists of a read/write followed by
16 register address bits and 8 data bits. Both the address and
data fields are organized with the MSB first and end with the
LSB.
SPI and GPIO 1.8 V/3.3 V Compatibility
The EXT_LO_IN+ and EXT_LO_IN− input pins must be ac-
coupled. When not in use, leave the EXT_LO_IN+ and
EXT_LO_IN− pins unconnected.
The SPI and general-purpose input/output (GPIO) interfaces of
the ADRF6650 provide two options for the logic voltage levels,
namely 1.8 V and 3.3 V. The interfaces use 1.8 V logic levels as
the default. Enable SPI_18_33_SEL (Register 0x0101, Bit 0) and
SPI_1P8_3P3_CTRL (Register 0x1401, Bit 4) for 3.3 V-compatible
logic levels. See Table 5 for the SPI and GPIO specifications.
In external LO mode of operation, the ADRF6650 consumes
approximately 0.5 W less of power compared to the internal LO
mode of operation.
Rev. A | Page 27 of 61
ADRF6650
Data Sheet
APPLICATIONS INFORMATION
BASIC CONNECTIONS
39Ω
35.7Ω
270nH
0.1µF
0.1µF
25Ω
25Ω
IF OUTPUT A
TC1-1-13X+
PULL-UP
INDUCTORS
VCC 3.3V
270nH
35.7Ω
39Ω
REF_IN
45
56 55
50
49
53 52
220Ω
220Ω
CPOUT
4300pF
VTUNE
4300pF
ADRF6650
DVGA
SPI
100pF
RFIN_A
TDD_A
RF
INPUT A
÷R
PFD
÷N
4
2
0.12µF
LPF
41
30
CP
CPOUT
Σ-Δ
VTUNE
EX LO
÷
100pF
INPUT
EX_LO_IN–
32
31
TCM1-83X+
EX_LO_IN+
LO_OUT–
100pF
100pF
13
11
TDD_B
RFIN_B
39
38
100pF
LO OUTPUT
TCM1-83X+
RF
INPUT B
LPF
LO_OUT+
SPI
DVGA
SPI
100pF
15 16
21
22
18 19
24 25 26 27
39Ω
270nH
0.1µF
25Ω
35.7Ω
IF OUTPUT B
TC1-1-13X+
PULL-UP
INDUCTORS
VCC 3.3V
25Ω
35.7Ω
270nH
0.1µF
BAND
OPTIMIZATION
INDUCTOR
39Ω
Figure 53. Basic Connections Diagram
Table 17. Basic Connections
Pin No.
RF Inputs
4, 11
Mnemonic
Description
Basic Connection
The single-ended RF inputs have a 50 Ω impedance.
These pins must be ac-coupled. Terminate unused RF
inputs with a dc blocking capacitor to GND to improve
isolation. See the Layout section for the recommended
PCB layout.
RFIN_A, RFIN_B
RF inputs
RF Balun Optimization
5, 10
Connect the balun tuning inductors (LTUNEx) to ground.
See the RF Frequency and IF Bandwidth Optimization
section for LTUNEx values.
RFBT_A, RFBT_B
TDD_A, TDD_B
RF balun tuning inductor
TDD enable control pins
TDD_x Pins
2, 13
Active high. 1.8 V and 3.3 V logic level compatible. See the
TDD Operation section for details about TDD pin use.
Serial VGA Control
21, 50
Follow the layout considerations given under the Layout
section.
RXB_ATT_DATA,
RXA_ATT_DATA
RXB_ATT_CLK,
RXA_ATT_CLK
DVGA data pins
DVGA clock pins
22, 49
Rev. A | Page 28 of 61
Data Sheet
ADRF6650
Pin No.
Mnemonic
Description
Basic Connection
3.3 V RF/IF Power
1, 14
Decouple all power supply pins to ground using 100 pF
and 0.1 µF capacitors. Place the decoupling capacitors
close to the pins.
VCC_MIX_A,
VCC_MIX_B
Mixer IF amplifier supply
6, 9
7, 8
VCC_LOA_S2,
VCC_LOB_S2
LO path supply for Stage 3 and Stage 4
LO path supply for Stage 1 and Stage 2
IF amplifier pull-up connections
VCC_LOA_S1,
VCC_LOB_S1
Mixer Supply Pull-Up
15, 16, 55, 56
Connect the pull-up pins to 3.3 V RF/IF power supply rail
with 270 nH pull-up inductors on each leg. Place the
decoupling capacitors of 100 pF and 0.1 µF between the
supply rail and the pull-up inductors. Place the inductor
to optimize the IF bandwidth (LSHUNTx) in between the
negative and positive pins. See the RF Frequency and IF
Bandwidth Optimization section for LSHUNTx values.
MIX_PU_B+,
MIX_PU_B−,
MIX_PU_A−,
MIX_PU_A+
DVGA Decoupling
17, 54
Decouple the DVGA decoupling pins to ground using
100 pF and 0.1 µF capacitors and connect to the DVGA
power supply rail (5 V). Place the decoupling capacitors
close to the pins. Place a resistor divider to divide the
power supply for the DVGA into two. Use 5.1 kΩ (or
similar) for resistor divider component values.
VCPL_B, VCPL_A
DVGA decoupling pins
5 V Power
20, 51
Decouple all power supply pins to ground using 100 pF
and 0.1 µF capacitors. Place the decoupling capacitors
close to the pins.
VCC_DVGA_B,
VCC_DVGA_A
DVGA power supply
IF outputs
IF Outputs
Place 25 Ω in series for each differential leg. The
differential IF output impedance, together with the series
25 Ω, becomes 60 Ω. For optimized performance, the 60 Ω
output impedance must be terminated with a 100 Ω load.
18, 19, 52, 53
IFOUT_A−,
IFOUT_B+,
IFOUT_A+,
IFOUT_A−
3.3 V PLL/VCO Power
Decouple all power supply pins to ground using 100 pF
and 0.1 µF capacitors. Place the decoupling capacitors
close to the pins. Employ ferrite beads to provide
isolation between the PLL/VCO supply pins. Beware of
the series resistance of the ferrite beads and try to
minimize the voltage drop.
33
34
VCCVCO_3V3
VCCDIV_3V3
VCO 3.3 V supply
LO chain and divider 3.3 V supply
PLL feedback divider 3.3 V supply
LO mixer output buffer 3.3 V supply
LO external output buffer 3.3 V supply
Charge pump 3.3 V supply
35
VCCFBDIV_3V3
VCCLO_MIX_3V3
VCCLO_AUX_3V3
VCCCP_3V3
36
37
42
43
VCCPFD_3V3
VCCREF_3V3
PFD 3.3 V supply
44
Reference input buffer 3.3 V supply
SPI and SDM LDO 3.3 supply V supply
48
VBAT_DIG_3V3
PLL/VCO
29
30
DCL_BIAS
VTUNE
VCO core bias decouple
VTUNE input
Decouple this pin to ground using 0.1 µF capacitor.
This pin is driven by the output of the loop filter; its
nominal input voltage range is 1.5 V to 2.5 V.
41
45
CPOUT
REF_IN
Charge pump output
Reference input buffer
Connect this pin to the VTUNE pin through the loop filter.
The nominal input level of this pin is 1 V p-p. The input
range is 10 MHz to 250 MHz. This pin is internally biased
and must be ac-coupled and terminated externally with
a 50 Ω resistor. Place the ac coupling capacitor between
the pin and the resistor.
46
47
SPILDO_OUT_
1V8
SPI 1.8 V LDO external decouple
output
Decouple the decoupling pins to ground using 100 pF
and 0.1 µF capacitors. Place the decoupling capacitors
close to the pins.
Decouple the decoupling pins to ground using 100 pF
and 0.1 µF capacitors. Place the decoupling capacitors
close to the pins.
SDMLDO_OUT_
1V8
SDM 1.8 V LDO external decouple
output
23
LO_LCKDT
LO lock detect
LO output
This pin has1.8 V/3.3 V logic levels.
Auxiliary LO Output
38, 39
The differential output impedance of the LO output
buffer is 100 Ω.
LO_OUT+,
LO_OUT−
Rev. A | Page 29 of 61
ADRF6650
Data Sheet
Pin No.
Mnemonic
Description
Basic Connection
External LO Inputs
31, 32
The differential input impedance of the external LO
input buffer is 100 Ω.
EXT_LO_IN+,
EXT_LO_IN−
External LO input
Serial Port Interface
24
25
SCLK
SDIO
SPI clock
This pin has1.8 V/3.3 V logic levels.
This pin has 1.8 V/3.3 V logic levels.
SPI data input/output (3-wire mode),
input only for 4-wire mode
26
SDO
CS
SPI data output (4-wire mode),
not used for 3-wire mode
SPI chip select
This pin has 1.8 V/3.3 V logic levels.
27
Active low. This pin has 1.8 V/3.3 V logic levels.
Reset
28
RST
Reset
Active low. This pin has 1.8 V/3.3 V logic levels.
Connect these pins to the ground of the PCB.
Do not connect this pin to the pad ground; connect this
pin to the PCB ground.
Ground
3, 12
40
GND
GND
Ground
Charge pump ground
Exposed Pad
Exposed pad
The exposed thermal pad is on the bottom of the package.
The exposed pad must be soldered to ground.
Rev. A | Page 30 of 61
Data Sheet
ADRF6650
Table 19. IF Band Optimization Inductor Values for Various
IF Center Frequencies
RF FREQUENCY AND IF BANDWIDTH
OPTIMIZATION
IF Center
Frequency (MHz)
IF Band Optimization Inductor,
LSHUNTx (nH)
The ADRF6650 incorporates a wideband balun at its RF inputs
for each channel. The wideband balun requires a tuning inductor
(LTUNEx) for optimized performance for various RF frequencies
of operation. Optimized LTUNEx provides optimized gain, noise
figure, and OIP3. Table 18 provides the LTUNEx values required
for some of the popular RF frequency points. As shown in Table 18,
the lower the RF frequency, the higher the LTUNEx inductor.
Figure 54 incorporates the ADRF6650 RF balun and the tuning
inductor.
120
180
270
360
35
Open
150
100
47
30
25
20
15
10
Table 18. LTUNEx Values for Various RF frequencies
RF Frequency (MHz)
LTUNEx (nH)
450
900
1800
2700
15
3.9
3.9
1
5
OPEN
150nH
ADRF6650
47nH
0
50
RF INPUT A
100
150
200
250
300
350
400
450
500
4
5
IF FREQUENCY (MHz)
CHANNEL A
CHANNEL B
TO MIXER A
Figure 56. Centering the IF Bandwidth with LTUNEx Gain vs. IF Frequency
L
A
TUNE
IF DVGA VS. LOAD
RF INPUT B
11
10
By design, the ADRF6650 has an output impedance of 10 Ω.
The ADRF6650 is optimized to perform with external 25 Ω in
each differential leg. External resistors are employed to increase
the output impedance. Together with the external 25 Ω, the
total differential output impedance equals 60 Ω. With a 100 Ω
differential load, the return loss is below −10 dB for a wide
range of IF frequency.
TO MIXER B
L
B
TUNE
Figure 54. Block Diagram Incorporating LTUNEx
40
36
32
28
24
20
1nH
3.9nH
8.2nH
ADRF6650
IFOUT_A–
10Ω
IF OUTPUT A
IFOUT_A+
100Ω FOR
OPTIMAL
450
750
1050
1350
1650
1950
2250
2550
PERFORMANCE
RF FREQUENCY (MHz)
Figure 57. IF Output Schematic, Channel A Output Shown
Figure 55. RF Gain Roll-Off for Various LTUNEx Values
Different application circuits may require various loading
conditions for the IF outputs. Therefore it is important to
understand the effect of IF output loading on the performance
characteristics, such as OP1dB, gain, OIP3, and OIP2.
The IF amplifier employed within the ADRF6650 requires pull-
up inductors tied to a 3.3 V power supply. In addition to these
pull-up inductors, an IF band optimization inductor (LSHUNTx) is
used for each of the channels, as shown in Figure 54. LSHUNTx
places the center of the IF with a 200 MHz bandwidth. Complete
coverage of 500 MHz IF bandwidth is achieved by shifting the
200 MHz IF window, as shown in Figure 56. The IF band
optimization inductor provides optimized gain flatness and
OIP3.
Rev. A | Page 31 of 61
ADRF6650
Data Sheet
35
ADC INTERFACING
100Ω
200Ω
30
25
20
15
10
5
The integrated IF DVGA of the ADRF6650 provides variable
and sufficient drive capability for both buffered and unbuffered
ADCs. The DVGA also provides isolation between the sampling
edges of the ADC and the mixer core. As result, only a selective
band-pass filter is required when interfacing with an ADC.
The filter resides between the ADRF6650 and the ADC. The
band-pass filter eliminates all out-of-band signals that might
degrade the performance of the ADRF6650 and ADC pair. The
band-pass filter center and bandwidth are selected for the
specific application, that is, the topology, system requirements,
signal bandwidth, ADC type, and sampling rate. The type and
the order of the filter are chosen by taking into account the
trade-off between the amount of rejection required and the
insertion loss. In this section, a filter design is explained for a
band-pass sampling use case with a step by step analysis.
0
0
100
200
300
400
500
600
IF FREQUENCY (MHz)
Figure 58. IF Gain vs. IF Frequency for Various Loads
60
50
40
30
20
10
0
100Ω
200Ω
Band-pass sampling is a popular way of reconstructing the
information from the received signals, especially for wireless
communication standards with high dynamic range requirements.
Band-pass sampling relies on the idea that the sampling rate
required to completely represent an analog signal is twice the
highest frequency of signal bandwidth of interest. With this
fact, a signal at a high IF frequency can be reconstructed by
accurately placing the signal of interest to one of the Nyquist
zones. To better illustrate the idea, a case for IF center frequency
of 187.5 MHz with a signal bandwidth of 30 MHz is considered.
To place the signal bandwidth to the first Nyquist zone, a
sampling rate of 250 MSPS is adequate, which puts the center
frequency of the retrieved signal to 62.5 MHz. One important
consideration for the band-pass sampling is that all of the
Nyquist zones fold on top of each other, which reduces the
available dynamic range. To overcome excessive noise due to
folding, employ a sharp antialiasing filter between the
ADRF6650 and the ADC.
0
50
100 150 200 250 300 350 400 450 500
IF FREQUENCY (MHz)
Figure 59. OIP3 vs. IF Frequency for Various Loads
120
100
80
60
40
20
0
100Ω
200Ω
To determine a proper candidate for the ADC, consider the signal-
to-noise ratio (SNR)/spurious-free dynamic range (SFDR) and
analog input bandwidth requirements. The SNR/SFDR require-
ments are provided for a given input power. Considering a
standard LTE uplink signal with a peak-to-average power ratio
(PAPR) of 8 dB to 10 dB, the average input signal power is backed
off at least 10 dB from the full scale. The SNR/SFDR of the
ADC at the backed off level allows a dynamic range compatible
with the system requirements. The analog input specification, alter-
natively, must be able to cope with the high IF frequency signal
(centered at 187.5 MHz). With these requirements in mind, the
AD9694 14-bit, 500 MSPS ADC or the AD6684 135 MHz quad
IF receiver are proper candidates with an SNR of 68 dBFS and
SFDR of 97 dBFS at 10 dB back-off from full scale.
HD2
HD3
56
106
156
206
256
306
356
406
456
IF FREQUENCY (MHz)
Figure 60. HD2/HD3 vs. IF Frequency for Various Loads
As mentioned previously in this section, the IF outputs are
optimized for a load of 100 Ω; however, this may not be the
most readily available load impedance. As a result, load vs.
performance trade-offs must be considered. Use Figure 58
through Figure 60 as guides only; do not interpret them in the
absolute sense. The results are obtained for one chip under
nominal voltage and supply.
The IF center frequency of the received signal (187.5 MHz) is
on the second Nyquist zone for a sampling rate of 250 MSPS.
The antialiasing filter provides enough rejection on other
Nyquist zones so that inherent folding of the zones does not
degrade the SNR and SFDR of the ADC. Considering that there
Rev. A | Page 32 of 61
Data Sheet
ADRF6650
0
–10
–20
–30
–40
–50
–60
–70
–80
are RF filters (diplexer, SAW, BAW, and others) at the front end
of the signal chain, the major spurious contents result from the
HD2 and HD3 products of the ADRF6650. As shown in Figure 17,
for an ADRF6650 gain of 1 dB, the HD2 and HD3 products are
−60 dBc. To avoid degrading the SFDR performance of the
AD9694 or AD6684, the antialiasing filter must reject the HD2
and HD3 products by 37 dB (97 dBFS − 60 dBc = 37 dB). Consi-
dering the tolerances of the filter components, a filter with a
bandwidth of 36 MHz and a rejection of at least 40 dB at second
and third harmonic zones is sufficient.
STANDALONE BPF
NORMALIZED ADRF6650 + BPF
When designing the band-pass filter, it is important to consider
the IF output impedance of the ADRF6650 and the input impe-
dance of the ADC. As mentioned in the IF DVGA vs. Load
section, the ADRF6650 IF outputs have an impedance of 60 Ω
(together with the external 25 Ω on each differential leg) and
are optimized for a 100 Ω differential load.
50
100
150
200
250
300
350
400
450
500
IF FREQUENCY (MHz)
Figure 63. Standalone BPF and Normalized ADRF6650 and Band-Pass Filter
Insertion Loss Response
POWER MODES
Figure 61 shows a band-pass filter designed around 187.5 MHz
with a bandwidth of 36 MHz. Figure 62 shows the return loss of
the filter. Figure 63 shows the performance of the filter with and
without the ADRF6650.
The ADRF6650 incorporates dual DVGAs that are compatible
with either a 5 V or 3.3 V supply. The specifications are given
under the 5 V supply condition. However, it is possible to use
the DVGA with a 3.3 V supply with decreased gain and OP1dB,
whereas a 3.3 V supply consumes the same amount of current,
which in turn saves power consumption.
IF OUTPUTS
3pF
0.1µF
0.1µF
220nH
220nH
25Ω
25Ω
The ADRF6650 allows the user to select between two power
modes for each supply voltage: high performance and low
power. The 5 V high performance mode achieves the best
linearity given in the Specifications section. Alternatively, low
power mode enables power consumption savings in return of
decreased linearity.
39pF 19nH
3pF
39pF 18nH
100Ω
100Ω
Figure 61. Antialiasing Band-Pass Filter Schematic
To summarize, the ADRF6650 has four power modes, as
outlined in Table 21.
Table 20. Component Values for Band Pass Filter Design
(Center at 184 MHz and Bandwidth 75 MHz)
Table 21. Power Mode Bit Settings
Value
39 pF
3 pF
18 nH
19 nH
220 nH
Type
Manufacturer
DVGA_5V_SEL
(Register 0x0103,
Bit 7)
DVGA_HP_SEL
(Register 0x0104,
Bit 6)
0402, NPO
0402, NPO
0402HP
0402HP
0402HP
Murata
Murata
Coilcraft
Coilcraft
Coilcraft
Power Mode
DVGA 5 V and High
Performance
DVGA 5 V and Low
Power
DVGA 3.3 V and High
Performance
DVGA 3.3 V and Low
Power
1
1
0
0
1
0
1
0
0
–5
–10
–15
–20
–25
50
100
150
200
250
300
350
400
450
500
IF FREQUENCY (MHz)
Figure 62. Standalone Return Loss Response
Rev. A | Page 33 of 61
ADRF6650
Data Sheet
To provide insight on the various power modes of the ADRF6650,
Figure 64 to Figure 66 display OP1dB, OIP3, and gain vs. IF
frequency.
POWER SUPPLY CONFIGURATION
The ADRF6650 employs high performance mixers, IF amplifiers,
DVGAs, PLL, and VCOs. To achieve the best performance,
especially in terms of spurs and phase noise, the power supply
configuration must be dealt with great care.
18
16
14
12
10
8
There are three main supply domains for the ADRF6650, namely,
DVGA (5 V), RF/IF (3.3 V), and PLL/VCO (3.3 V). For the best
performance, each of the supply domains requires specific attention
in the power supply design.
DVGA (5 V) Supply Domain
6
DVGAs on each channel are supplied thorough the same linear
regulator, taking into account the total amount of current drawn.
The linear regulator must have high power supply rejection ratio
(PSRR) and low noise to avoid spur injection from the supply
circuitry. Another consideration is the transient response, which is
important for the TDD operation. If the DVGAs are set to turn on
and off during TDD cycles, the transient response of the power
supply IC may affect the settling time of the ADRF6650. Take
care to avoid long transient times. The ADM7170/ADM7171
are ultralow noise, high PSRR, and fast transient response LDOs
that are suitable for the DVGA (5 V) supply domain. Their fast
transient response ensures that the ADRF6650 settling time is
not affected by variations in supply.
4
2
DVGA 5V
DVGA 3.3V
0
800
1800
2700
4000
LO FREQUENCY (MHz)
Figure 64. OP1dB vs. LO Frequency for Various Power Modes
50
45
40
35
30
25
20
15
10
5
ADRF6650
BEAD
VCC_DVGA_A
0.1µF
0.1µF
100pF
100pF
5V
ADM7170/
ADM7171
DVGA 5V LOW POWER
DVGA 5V HIGH PERFORMANCE
DVGA 3.3V HIGH PERFORMANCE
DVGA 3.3V LOW POWER
10µF
BEAD
0
50
VCC_DVGA_B
100
150
200
250
300
350
400
450
IF FREQUENCY (MHz)
Figure 65. OIP3 vs. IF Frequency for Various Power Modes, fLO = 1800 MHz
35
Figure 67. DVGA (5 V) Supply Domain with the ADM7170/ADM7171
30
25
20
15
10
RF/IF (3.3 V) Supply Domain
The RF/IF supply domain includes all of the supplies related to
RF and IF blocks within the ADRF6650, namely mixers, IF
amplifiers, and LO path to the mixers. All of the RF/IF supply
domain pins are supplied with the same linear regulator with
beads separating each individual pin. Each pin requires its own
decoupling capacitors, placed close to the pin.
The linear regulator must have high PSRR and low noise to avoid
spur injection from the supply circuitry. Another consideration
is the transient response, which becomes important for the
TDD operation. If the RF/IF blocks are set to turn on and off
during TDD cycles, transient response of the power supply IC
can affect the settling time of the ADRF6650. Take care to avoid
long transient times. The ADM7170/ADM7171 are ultralow
noise, high PSRR, and fast transient response LDOs that are
suitable for the RF/IF (3.3 V) supply domain. Their fast transient
response ensures that the ADRF6650 settling time is not
affected by variations in supply.
DVGA 5V LOW POWER
5
DVGA 5V HIGH PERFORMANCE
DVGA 3.3V HIGH PERFORMANCE
DVGA 3.3V LOW POWER
0
50
100
150
200
250
300
350
400
450
IF FREQUENCY (MHz)
Figure 66. Gain vs. IF Frequency for Various Power Modes, fLO = 1800 MHz
Rev. A | Page 34 of 61
Data Sheet
ADRF6650
BEAD
BEAD
0.1µF
BEAD
0.1µF
MIX_PU_A±
100pF
MIX_PU_B±
100pF
VCCVCO_3V3
10µF
0.1µF
100pF
BEAD
0.1µF
BEAD
0.1µF
VCCCP_3V3
100pF
100pF
10µF
VCCPFD_3V3
BEAD
0.1µF
BEAD
0.1µF
VCC_MIX_A
100pF
VCC_MIX_B
100pF
ADM7170
10µF
VR1
VR2
VR3
VR4
BEAD
0.1µF
BEAD
VCCREF_3V3
HMC1060
100pF
100pF
10µF
VBAT_DIG_3V3
BEAD
0.1µF
BEAD
0.1µF
VCC_LOA_S1/2
100pF
VCC_LOB_S1/2
100pF
0.1µF
BEAD
BEAD
VCCLO_AUX_3V3
VCCLO_MIX_3V3
0.1µF
100pF
10µF
VCCDIV_3V3
0.1µF
0.1µF
100pF
100pF
Figure 68. RF/IF (3.3 V) Supply Domain with the ADM7170
VCCFBDIV_3V3
Note that if the DVGA is supplied through 3.3 V, the two supply
domains can be tied together to reduce the number of power
supply ICs. Take care for the increased current drawn from the
power supply IC when the DVGA and RF/IF supply domains
are connected together.
Figure 69. PLL/VCO Domain Power Supply Circuit
LAYOUT
PLL/VCO (3.3 V) Supply Domain
Careful layout of the ADRF6650 is necessary to optimize
performance and minimize stray parasitics. Because the
ADRF6650 supports two channels, the layout of the RF section
is critical in achieving isolation between channels. Figure 70
shows the recommended layout for the RF inputs. The best
layout approach is to keep the traces short and direct. In addition,
for improved isolation, do not route the RF input traces in
parallel to each other and spread the traces immediately after
each one leaves the pins. Keep the traces as far away from each
other as possible (and at an angle, if possible) to prevent cross
coupling.
The PLL/VCO supply domain requires specific attention, which
can otherwise result in performance degradation. The ADRF6650
incorporates an ultralow noise PLL/VCO, which is sensitive to
any noise and/or frequency component at the supply pins.
These unwanted noise and frequency components degrade the
performance of the overall system. To avoid performance
degradation, the ADRF6650-EVALZ evaluation board employs
the PLL/VCO supply domain circuit given in Figure 69, which
uses the HMC1060, an ultralow noise LDO with four isolated
outputs. Noise performance and isolated outputs makes the
HMC1060 the perfect solution for the PLL/VCO supply domain.
For more configurability options, see the ADRF6650-EVALZ
evaluation board user guide.
The input impedance of the RF inputs is 50 Ω, and the traces
leading to the pin must also have a 50 Ω characteristic impedance.
Terminate the unused RF inputs with a dc blocking capacitor to
ground.
Rev. A | Page 35 of 61
ADRF6650
Data Sheet
Figure 70. Serial Gain Control Clock and Data Routing (Green is Top Layer,
Blue is Inner Layer, Yellow is Component Placement)
Figure 71. PLL/VCO Pin Connections
The ADRF6650 incorporates a very low noise PLL/VCO, and
care must be taken when designing the PCB routing around the
PLL/VCO pins. It is required to place the decoupling capacitors
for the supply pins as close as possible. If 0402 capacitors are
used, placing all of the decoupling capacitors close to the pin
becomes problematic. In such a case, place the smaller value
decoupling capacitor as close as possible to the pin. It is a good
practice to keep the first capacitor of the loop filter close to the
CPOUT pin, and the last capacitor close to the VTUNE pin, as
shown in Figure 71.
Rev. A | Page 36 of 61
Data Sheet
ADRF6650
REGISTER MAP
Table 22. Register Details
Reg
0x0000 ADI_SPI_CONFIG [7:0] SOFTRESET_ LSB_FIRST_
0x0001 SPI_CONFIG_B [7:0] SINGLE_ CSB_STALL
Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset RW
ENDIAN_
SDOACTIVE_ SDOACTIVE ENDIAN
LSB_FIRST
SOFTRESET 0x00 R/W
MASTER_SLAVE_ RESERVED
RB
SOFT_RESET
MASTER_
SLAVE_
0x00 R/W
INSTRUCTION
TRANSFER
0x0002 DEVICE_CONFIG [7:0]
0x0003 CHIP_TYPE [7:0]
RESERVED
OPERATING_MODE
POWER_MODE
0x00 R/W
CHIPTYPE
0x00
0x12
0x00
R
R
R
0x0004 PRODUCT_ID_1 [7:0]
0x0005 PRODUCT_ID_2 [7:0]
PRODUCT_ID[7:0]
PRODUCT_ID[15:8]
SCRATCHPAD
0x000A SCRATCH
[7:0]
[7:0]
[7:0]
[7:0]
0x00 R/W
0x000B SPI_REVISON
0x000C VENDOR_ID_L
0x000D VENDOR_ID_H
SPI_VER
0x00
0x56
0x04
R
R
R
VENDOR_ID[7:0]
VENDOR_ID[15:8]
0x0021 BLOCK_RESETS [7:0]
RESERVED
DVGA_CH2_
RSTB
DVGA_CH1_ 0x1F R/W
RSTB
0x003C ATTEN_
READBACK_CH1
[7:0]
[7:0]
[7:0]
[7:0]
ATTEN_READBACK_CH1
ATTEN_READBACK_CH2
0x00
0x00
0x00
0x00
R
R
R
R
0x003D ATTEN_
READBACK_CH2
0x003E DVGA_TRIM_
READBACK_CH1
DVGA_TRIM_READBACK_CH1
DVGA_TRIM_READBACK_CH2
0x003F DVGA_TRIM_
READBACK_CH2
0x0100 TDD_BYPASS
[7:0] DVGA_ENB_ DVGA_ENB_CH1 IF_ENB_CH2
CH2
IF_ENB_CH1
LO_STG23_ LO_STG23_
ENB_CH2 ENB_CH1
LO_STG1_ENB BYPASS_TD 0xFE R/W
D
0x0101 CONFIG
[7:0] Reserved
Reserved
IFLIN_BIAS_EN
IFMAIN_BIAS_
EN
RESERVED
SPI_18_33_ 0x38 R/W
SEL
0x0102 EN_MASK
[7:0] PLL_ENB_
DVGA_ENB_
DVGA_ENB_
CH1_MASK
IF_ENB_CH2_ IF_ENB_
LO_STG23_
LO_STG23_
ENB_CH1_
MASK
LO_STG1_ 0x7E R/W
ENB_MASK
CH12_MASK CH2_MASK
MASK
CH1_MASK ENB_CH2_
MASK
0x0103 DVGA_MODE
0x0104 DVGA_GAIN1
0x0105 DVGA_GAIN2
0x0300 LPF_OVERRIDE
[7:0] DVGA_5V_SEL
DVGA_FA_STEP
DVGA_HP_SEL
RESERVED
DVGA_UPDN_STEP
DVGA_GAIN_MODE
0x80 R/W
0x68 R/W
0x28 R/W
[7:0] RESERVED
[7:0]
DVGA_GAIN_CH1
DVGA_GAIN_CH2
[7:0] RESERVED
LPF2_OVERRIDE
LPF1_OVERRIDE
LPF_DPLX_ 0x7F R/W
EN_
OVERRIDE
0x0301 IFMAIN_
OVERRIDE
[7:0]
RESERVED
IFMAIN_BIAS_OVERRIDE
0x15 R/W
0x0302 IFLIN_OVERRIDE [7:0]
0x0303 VGS_OVERRIDE [7:0]
RESERVED
RESERVED
IFLIN_BIAS_OVERRIDE
VGS_OVERRIDE
0x1F R/W
0x04 R/W
0x10 R/W
0x0304 DVGA_TRIM1_
LP3V_OVERRIDE
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
RESERVED
DVGA_TRIM_LP_3V_CH1_OVERRIDE
0x0305 DVGA_TRIM1_
HP3V_OVERRIDE
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
DVGA_TRIM_HP_3V_CH1_OVERRIDE
DVGA_TRIM_LP_5V_CH1_OVERRIDE
DVGA_TRIM_HP_5V_CH1_OVERRIDE
DVGA_TRIM_LP_3V_CH2_OVERRIDE
DVGA_TRIM_HP_3V_CH2_OVERRIDE
DVGA_TRIM_LP_5V_CH2_OVERRIDE
DVGA_TRIM_HP_5V_CH2_OVERRIDE
0x10 R/W
0x10 R/W
0x10 R/W
0x10 R/W
0x10 R/W
0x10 R/W
0x10 R/W
0x0306 DVGA_TRIM1_
LP5V_OVERRIDE
0x0307 DVGA_TRIM1_
HP5V_OVERRIDE
0x0308 DVGA_TRIM2_
LP3V_OVERRIDE
0x0309 DVGA_TRIM2_
HP3V_OVERRIDE
0x030A DVGA_TRIM2_
LP5V_OVERRIDE
0x030B DVGA_TRIM2_
HP5V_OVERRIDE
Rev. A | Page 37 of 61
ADRF6650
Data Sheet
Reg
Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset RW
0x0310 OVERRIDE_
SELECT
[7:0] SPARE2_
OVERRIDE_
SEL
SPARE1_
OVERRIDE_SEL
DVGA_TRIM_
CH2_
OVERRIDE_SEL
DVGA_TRIM_ VGS_
CH1_
OVERRIDE_SEL SEL
IFLIN_TRIM_ IFMAIN_TRIM_ LPF_TRIM_ 0x00 R/W
OVERRIDE_ OVERRIDE_ OVERRIDE_SEL OVERRIDE_
SEL
SEL
0x1021 BLOCK_RESETS [7:0] RESERVED
ARSTB_BLOCK_ ARSTB_BLOCK_ ARSTB_
ARSTB_
ARSTB_
BLOCK_
DSMOSTG
ARSTB_BLOCK_ ARSTB_
0xFF R/W
0x02 R/W
LKD
AUTOCAL
BLOCK_NDIV BLOCK_
RDIV
DSMCORE
BLOCK_
DSMALL
0x1032 GPO1_CONTROL [7:0] RESERVED
GPO1_BLK_SEL
RESERVED
GPO1_
ENABLE
0x1033 GPO1_SELECT
[7:0]
[7:0]
GPO1_SGNL_SEL
0x00 R/W
0x0A R/W
0x1109 SIG_PATH_9_
NORMAL
RESERVED
TRM_MIXLODRV_DRV_
POUT
TRM_XLODRV_DRV_POUT RESERVED
0x1200 INT_L
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
INT_DIV[7:0]
INT_DIV[15:8]
FRAC[7:0]
0x89 R/W
0x01 R/W
0x00 R/W
0x00 R/W
0x00 R/W
0x00 R/W
0x00 R/W
0x00 R/W
0x00 R/W
0x00 R/W
0x01 R/W
0x03 R/W
0x1201 INT_H
0x1202 FRAC1_L
0x1203 FRAC1_M
0x1204 FRAC1_H
FRAC[15:8]
FRAC[23:16]
PHASE[7:0]
PHASE[15:8]
PHASE[23:16]
MOD2[7:0]
0x1205 SD_PHASE_L_0 [7:0]
0x1206 SD_PHASE_M_0 [7:0]
0x1207 SD_PHASE_H_0 [7:0]
0x1208 MOD_L
0x1209 MOD_H
0x120B SYNTH
0x120C R_DIV
0x120E SYNTH_0
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
RESERVED
MOD2[13:8]
RESERVED
PRE_SEL
EN_FBDIV
RESERVED
R_DIV
RESERVED
DOUBLER_
EN
RESERVED
RESERVED
RDIV2_SEL 0x04 R/W
0x1214 MULTI_FUNC_
SYNTH_CTRL_
0214
[7:0]
LD_BIAS
LDP
0x48 R/W
0x1217 SI_VCO_SEL
0x121F VCO_FSM
0x122A SD_CTRL
[7:0]
RESERVED
DISABLE_CAL
RESERVED
SI_VCO_SEL
0x00 R/W
0x00 R/W
[7:0] RESERVED
[7:0]
RESERVED
RESERVED
SD_EN_FRAC0
SD_EN_OUT_
OFF
SD_SM_2
RESERVED
CP_HIZ
0x02 R/W
0x122C MULTI_FUNC_
SYNTH_CTRL_
022C
[7:0]
RESERVED
0x03 R/W
0x122D MULTI_FUNC_
SYNTH_CTRL_
022D
[7:0] EN_PFD_CP
BLEED_POL
RESERVED
INT_ABP
RESERVED
BLEED_EN 0x81 R/W
0x122E CP_CURR
0x122F BICP
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
RESERVED
CP_CURRENT
0x0F R/W
0x08 R/W
0x00 R/W
0x00 R/W
BICP
FRAC2[7:0]
0x1233 FRAC2_L
0x1234 FRAC2_H
RESERVED
FRAC2[13:8]
RESERVED
0x1235 MULTI_FUNC_
SYNTH_CTRL_
0235
RESERVED
PHASE_ADJ_EN RESERVED
0x00 R/W
0x1240 VCO_LUT_CTRL [7:0]
RESERVED
SI_VCO_
FORCE_
CAPSVCOI
SI_VCO_
FORCE_VCO
SI_VCO_
FORCE_
CAPS
0x00 R/W
0x124D LOCK_DETECT
[7:0]
[7:0]
RESERVED
LOCK_
DETECT
0x00
R
0x1401 MULTI_FUNC_
CTRL
RESERVED
RESERVED
SPI_1P8_3P3_
CTRL
RESERVED
0x00 R/W
0x140E LO_CNTRL2
0x1414 LO_CNTRL8
[7:0] EN_BIAS_R
[7:0] MIX_OE
REFBUF_EN
USEEXT_LOI
RESERVED
OUT_DIVRATIO
0xB3 R/W
0x02 R/W
LO_OE
0x1541 FRAC2_L_SLAVE [7:0]
0x1542 FRAC2_H_SLAVE [7:0]
0x1543 FRAC_L_SLAVE [7:0]
0x1544 FRAC_M_SLAVE [7:0]
FRAC2_SLV[7:0]
0x00
0x00
0x00
0x00
R
R
R
R
RESERVED
FRAC2_SLV[13:8]
FRAC_SLV[7:0]
FRAC_SLV[15:8]
Rev. A | Page 38 of 61
Data Sheet
ADRF6650
Reg
Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset RW
0x1545 FRAC_H_SLAVE2 [7:0]
0x1546 PHASE_L_SLAVE [7:0]
FRAC_SLV[23:16]
0x00
0x00
0x00
R
R
R
PHASE_SLV[7:0]
PHASE_SLV[15:8]
0x1547 PHASE_M_
SLAVE2
[7:0]
[7:0]
[7:0]
[7:0]
0x1548 PHASE_H_
SLAVE3
PHASE_SLV[23:16]
INT_DIV_SLV[7:0]
INT_DIV_SLV[15:8]
0x00
0x89
0x01
0x03
R
R
R
0x1549 INT_DIV_L_
SLAVE
0x154A INT_DIV_H_
SLAVE
0x154B R_DIV_SLAVE
[7:0] RESERVED
[7:0]
R_DIV_SLV
R
R
0x154C RDIV2_SEL_
SLAVE
RESERVED
RDIV2_SEL_ 0x00
SLV
0x1583 DISABLE_CFG
[7:0]
RESERVED
DSM_LAUNCH_DLY
DISABLE_
FREQHOP
DISABLE_
DBLBUFFERING PHASEADJ
DISABLE_
0x00 R/W
Rev. A | Page 39 of 61
ADRF6650
Data Sheet
REGISTER DETAILS
Address: 0x0000, Reset: 0x00, Name: ADI_SPI_CONFIG
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 ] SO FT RESET _ ( R/W )
Soft Reset
[ 0 ] SO FT RESET ( R/W )
Soft Reset
[ 6 ] LSB_FIRST _ ( R/W )
LSB First
[ 1] LSB_FIRST ( R/W )
LSB First
[ 5] ENDIAN_ ( R/W )
Endian
[ 2] ENDIAN ( R/W )
Endian
[ 4 ] SDO ACT IVE_ ( R/W )
SDO Active
[ 3] SDO ACT IVE ( R/W )
SDO Active
Table 23. Bit Descriptions for ADI_SPI_CONFIG
Bits
Bit Name
Settings
Description
Soft Reset
LSB First
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
SOFTRESET_
LSB_FIRST_
ENDIAN_
SDOACTIVE_
SDOACTIVE
ENDIAN
Endian
SDO Active
SDO Active
Endian
LSB First
Soft Reset
LSB_FIRST
SOFTRESET
Address: 0x0001, Reset: 0x00, Name: SPI_CONFIG_B
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] SINGLE_INSTRUCTION (R/W)
[0] MASTER_SLAVE_TRANSFER (R/W)
Single Instruction
Master Slave Transfer
[6] CSB_STALL (R/W)
[2:1] SOFT_RESET (R/W)
CSB Stall
Soft Reset
[5] MASTER_SLAVE_RB (R/W)
[4:3] RESERVED
Master Slave RB
Table 24. Bit Descriptions for SPI_CONFIG_B
Bits
Bit Name
Settings
Description
Reset
0x0
0x0
0x0
0x0
0x0
0x0
Access
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
[4:3]
[2:1]
0
SINGLE_INSTRUCTION
CSB_STALL
MASTER_SLAVE_RB
RESERVED
SOFT_RESET
MASTER_SLAVE_TRANSFER
Single Instruction
CSB Stall
Master Slave RB
Reserved
Soft Reset
Master Slave Transfer
Address: 0x0002, Reset: 0x00, Name: DEVICE_CONFIG
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :4 ] RESERVED
[ 1:0 ] PO W ER_M O DE ( R/W )
Not employed.
[ 3:2] O PERAT ING_M O DE ( R/W )
Operation Mode - Not employed.
Table 25. Bit Descriptions for DEVICE_CONFIG
Bits
[7:4]
[3:2]
[1:0]
Bit Name
Settings
Description
Reset
0x0
0x0
Access
R
R/W
R/W
RESERVED
OPERATING_MODE
POWER_MODE
Reserved.
Operation Mode - Not employed.
Not employed.
0x0
Rev. A | Page 40 of 61
Data Sheet
ADRF6650
Address: 0x0003, Reset: 0x00, Name: CHIP_TYPE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] CHIPTYPE (R)
Chip Type, Read Only
Table 26. Bit Descriptions for CHIP_TYPE
Bits
Bit Name
Settings
Description
Chip Type, Read Only
Reset
Access
[7:0]
CHIPTYPE
0x0
R
Address: 0x0004, Reset: 0x12, Name: Product_ID_1
7
6
5
4
3
2
1
0
0
0
0
1
0
0
1
0
[7:0] PRODUCT_ID[7:0] (R)
Product ID
Table 27. Bit Descriptions for Product_ID_1
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
PRODUCT_ID[7:0]
Product ID
0x12
R
Address: 0x0005, Reset: 0x00, Name: Product_ID_2
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] PRODUCT_ID[15:8] (R)
Product ID
Table 28. Bit Descriptions for Product_ID_2
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
PRODUCT_ID[15:8]
Product ID
0x12
R
Address: 0x000A, Reset: 0x00, Name: Scratch
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :0 ] SCRAT CHPAD ( R/W )
Scratch Pad
Table 29. Bit Descriptions for Scratch
Bits
Bit Name
Settings
Description
Reset
0x0
Access
[7:0]
SCRATCHPAD
Scratch Pad
R/W
Address: 0x000B, Reset: 0x00, Name: SPI_Revision
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] SPI_VER (R)
SPI Register Map Revision
Table 30. Bit Descriptions for SPI_Revision
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
SPI_VER
SPI Register Map Revision
0x0
R
Address: 0x000C, Reset: 0x56, Name: VENDOR_ID_L
7
6
5
4
3
2
1
0
0
1
0
1
0
1
1
0
[7:0] VENDOR_ID[7:0] (R)
Vendor ID
Table 31. Bit Descriptions for VENDOR_ID_L
Bits
Bit Name
Settings
Description
Reset
0x456
Access
[7:0]
VENDOR_ID[7:0]
Vendor ID
R
Rev. A | Page 41 of 61
ADRF6650
Data Sheet
Address: 0x000D, Reset: 0x04, Name: VENDOR_ID_H
7
6
5
4
3
2
1
0
0
0
0
0
0
1
0
0
[7:0] VENDOR_ID[15:8] (R)
Vendor ID
Table 32. Bit Descriptions for VENDOR_ID_H
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
VENDOR_ID[15:8]
Vendor ID
0x456
R
Address: 0x0021, Reset: 0x1F, Name: BLOCK_RESETS
7
6
5
4
3
2
1
0
0
0
0
1
1
1
1
1
[ 7 :2] RESERVED
[ 0 ] DVGA_CH2_RST B ( R/W )
Resets the DVGA of Channel 2
[ 1] DVGA_CH1_RST B ( R/W )
Resets the DVGA of Channel 1
Table 33. Bit Descriptions for BLOCK_RESETS
Bits
[7:2]
1
Bit Name
Settings
Description
Reset
0x7
0x1
Access
R
R/W
R/W
RESERVED
DVGA_CH1_RSTB
DVGA_CH2_RSTB
Reserved.
Resets the DVGA of Channel 1
Resets the DVGA of Channel 2
0
0x1
Address: 0x003C, Reset: 0x00, Name: ATTEN_READBACK_CH1
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :0 ] AT T EN_READBACK_CH1 ( R)
Readback of the current attenuation
state from Channel 1
Table 34. Bit Descriptions for ATTEN_READBACK_CH1
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
ATTEN_READBACK_CH1
Readback of the current attenuation state from Channel 1
0x0
R
Address: 0x003D, Reset: 0x00, Name: ATTEN_READBACK_CH2
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :0 ] AT T EN_READBACK_CH2 ( R)
Readback of the current attenuation
state from Channel 2
Table 35. Bit Descriptions for ATTEN_READBACK_CH2
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
ATTEN_READBACK_CH2
Readback of the current attenuation state from Channel 2
0x0
R
Address: 0x003E, Reset: 0x00, Name: DVGA_TRIM_READBACK_CH1
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :0 ] DVGA_T RIM _READBACK_CH1 ( R)
Readback the DVGA trim that is finally
sent out to the DVGA, Channel 1 (post
3V/5V and power mode)
Table 36. Bit Descriptions for DVGA_TRIM_READBACK_CH1
Bits Bit Name
Settings Description
Reset Access
0x0
[7:0] DVGA_TRIM_READBACK_CH1
Readback the DVGA trim that is finally sent out to the DVGA,
Channel 1 (post 3 V/5 V and power mode)
R
Rev. A | Page 42 of 61
Data Sheet
ADRF6650
Address: 0x003F, Reset: 0x00, Name: DVGA_TRIM_READBACK_CH2
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :0 ] DVGA_T RIM _READBACK_CH2 ( R)
Readback the DVGA trim that is finally
sent out to the DVGA, Channel 2 (post
3V/5V and power mode)
Table 37. Bit Descriptions for DVGA_TRIM_READBACK_CH2
Bits Bit Name
Settings Description
Reset Access
[7:0] DVGA_TRIM_READBACK_CH2
Readback the DVGA trim that is finally sent out to the DVGA,
Channel 2 (post 3 V/5 V and power mode)
0x0
R
Address: 0x0100, Reset: 0xFE, Name: TDD_BYPASS
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
0
[ 7 ] DVGA_ENB_CH2 ( R/W )
Channel 2 DVGA Enable When BYPASS_TDD= 1
[ 0 ] BYPASS_T DD ( R/W )
Bypass TDD
[ 6 ] DVGA_ENB_CH1 ( R/W )
Channel 1 DVGA Enable When BYPASS_TDD= 1
[ 1 ] LO _ST G1 _EN B ( R/W )
Input LO Buffer Enable When BYPASS_TDD= 1
[ 5] IF_ENB_CH2 ( R/W )
Channel 2 Mix IF Buffer Enable When
BYPASS_TDD= 1
[ 2] LO _ST G23_ENB_CH1 ( R/W )
Channel 1 LO Buffer Enable When BYPASS_TDD= 1
[ 3] LO _ST G23_ENB_CH2 ( R/W )
Channel 2 LO Buffer Enable When BYPASS_TDD= 1
[ 4 ] IF_ENB_CH1 ( R/W )
Channel 1 Mix IF Buffer Enable When
BYPASS_TDD= 1
Table 38. Bit Descriptions for TDD_BYPASS
Bits
Bit Name
Settings
Description
Reset
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
DVGA_ENB_CH2
DVGA_ENB_CH1
IF_ENB_CH2
Channel 2 DVGA Enable When BYPASS_TDD = 1
Channel 1 DVGA Enable When BYPASS_TDD = 1
Channel 2 Mix IF Buffer Enable When BYPASS_TDD = 1
Channel 1 Mix IF Buffer Enable When BYPASS_TDD = 1
Channel 2 LO Buffer Enable When BYPASS_TDD = 1
Channel 1 LO Buffer Enable When BYPASS_TDD = 1
Input LO Buffer Enable When BYPASS_TDD = 1
Bypass TDD
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x0
IF_ENB_CH1
LO_STG23_ENB_CH2
LO_STG23_ENB_CH1
LO_STG1_ENB
BYPASS_TDD
Address: 0x0101, Reset: 0x38, Name: CONFIG
Table 39. Bit Descriptions for CONFIG
Bits
Bit Name
Settings
Description
Reset
Access
R/W
R/W
R/W
R/W
5
4
[3:1]
0
IFLIN_BIAS_EN
IFMAIN_BIAS_EN
RESERVED
Enable Internal Bias Adjustment for IF Amplifier Linearization
Enable Internal Bias Adjustment for IF Amplifier
Reserved
0x1
0x1
0x4
0x0
SPI_18_33_SEL
SPI Tristate Buffer Output Voltage Level, 0 = 1.8 V, 1 = 3.3 V
Rev. A | Page 43 of 61
ADRF6650
Data Sheet
Address: 0x0102, Reset: 0x7E, Name: EN_MASK
7
6
5
4
3
2
1
0
0
1
1
1
1
1
1
0
[ 7 ] P LL _EN B_CH 1 2 _M AS K ( R/W )
[ 0 ] LO _S T G 1 _EN B_M AS K ( R/W )
PLL Dis ab le fo r TDD O p e ratio n.
Inp ut LO Buffe r Dis ab le fo r TDD O p e ratio n.
[ 6 ] D V G A_EN B_CH 2 _M AS K ( R/W )
Channe l 2 DVGA Dis ab le fo r TDD O p e ratio n.
[ 1 ] LO _S T G 2 3 _EN B_CH 1 _M AS K ( R/W )
Channe l 1 LO Buffe r Dis ab le fo r TDD
O p e ratio n.
[ 5 ] D V G A_EN B_CH 1 _M AS K ( R/W )
Channe l 1 DVGA Dis ab le fo r TDD O p e ratio n.
[ 2 ] LO _S T G 2 3 _EN B_CH 2 _M AS K ( R/W )
Channe l 2 LO Buffe r Dis ab le fo r TDD
O p e ratio n.
[ 4 ] IF_EN B_CH 2 _M AS K ( R/W )
Channe l 2 Mix e r IF Buffe r Dis ab le fo r
TDD O p e ratio n.
[ 3 ] IF _EN B_CH 1 _M AS K ( R/W )
Channe l 1 Mix e r IF Buffe r Dis ab le fo r
TDD O p e ratio n.
Table 40. Bit Descriptions for EN_MASK
Bits Bit Name Settings Description
Reset Access
7
6
5
4
3
2
1
0
PLL_ENB_CH12_MASK
PLL Disable for TDD Operation. Pass PLL disable to PLL when TDD_A and
TDD_B are both high. PLL Blocks disable according to PLL register setting
Channel 2 DVGA Disable for TDD Operation. 1 = disable when TDD_A is
high (active low), 0 = enable.
Channel 1 DVGA Disable for TDD Operation. 1 = disable when TDD_A is
high (active low), 0 = enable.
Channel 2 Mixer IF Buffer Disable for TDD Operation. 1 = disable when
TDD_A is high (active low), 0 = enable.
Channel 1 Mixer IF Buffer Disable for TDD Operation. 1 = disable when
TDD_A is high (active low), 0 = enable.
Channel 2 LO Buffer Disable for TDD Operation. 1 = disable when TDD_A
is high (active low), 0 = enable.
Channel 1 LO Buffer Disable for TDD Operation. 1 = disable when TDD_A
is high (active low), 0 = enable.
Input LO Buffer Disable for TDD Operation. 1 = disable when TDD_A is
high (active low), 0 = enable.
0x0
0x1
0x1
0x1
0x1
0x1
0x1
0x0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DVGA_ENB_CH2_MASK
DVGA_ENB_CH1_MASK
IF_ENB_CH2_MASK
IF_ENB_CH1_MASK
LO_STG23_ENB_CH2_MASK
LO_STG23_ENB_CH1_MASK
LO_STG1_ENB_MASK
Address: 0x0103, Reset: 0x80, Name: DVGA_MODE
Table 41. Bit Descriptions for DVGA_MODE
Bits
Bit Name
Settings
Description
Reset
0x1
Access
R/W
7
DVGA_5V_SEL
DVGA_UPDN_STEP
5 V Power Supply Select for DVGA. 1 = 5 V mode.
[4:3]
VGA Up-Down Gain Step Size for Both Channels.
0x0
R/W
0
1
1 dB
2 dB
10 4 dB
11 8 dB
[2:0]
DVGA_GAIN_MODE
VGA Gain Mode for Both Channels.
SPI
11 Up/Down
0x0
R/W
1
Rev. A | Page 44 of 61
Data Sheet
ADRF6650
Address: 0x0104, Reset: 0x68, Name: DVGA_GAIN1
7
6
5
4
3
2
1
0
0
1
1
0
1
0
0
0
[7] RESERVED
[5:0] DVGA_GAIN_CH1 (R/W)
Channel 1 Gain Setting, SPI Mode
[6] DVGA_HP_SEL (R/W)
High Power Select for DVGA
0: Low Power.
1: High Performance.
Table 42. Bit Descriptions for DVGA_GAIN1
Bits
Bit Name
Settings
Description
Reset
0x0
Access
R
7
RESERVED
Reserved
6
DVGA_HP_SEL
High Power Select for DVGA
Low Power
High Performance
0x1
R/W
0
1
[5:0]
DVGA_GAIN_CH1
Channel 1 Gain Setting, SPI Mode
0x28
R/W
Address: 0x0105, Reset: 0x28, Name: DVGA_GAIN2
7
6
5
4
3
2
1
0
0
0
1
0
1
0
0
0
[7:6] RESERVED
[5:0] DVGA_GAIN_CH2 (R/W)
Channel 2 Gain Setting, SPI Mode
Table 43. Bit Descriptions for DVGA_GAIN2
Bits
[7:6]
[5:0]
Bit Name
Settings
Description
Reset
0x0
0x28
Access
R
R/W
RESERVED
DVGA_GAIN_CH2
Reserved
Channel 2 Gain Setting, SPI Mode
Address: 0x0300, Reset: 0x7F, Name: LPF_OVERRIDE
7
6
5
4
3
2
1
0
0
1
1
1
1
1
1
1
[ 7 ] RES ERV ED
[ 0 ] LP F_D P LX _EN _O V ERRID E ( R/W )
LPF Dip le x e r O v e rrid e Value
[ 6 :4 ] LP F 2 _O V ERRID E ( R/W )
LPF CDAC2 O v e rrid e Value
[ 3 :1 ] L P F1 _O V ERRID E ( R/W )
LPF CDAC1 O v e rrid e Value
Table 44. Bit Descriptions for LPF_OVERRIDE
Bits
Bit Name
Settings
Description
Reset
0x0
Access
R
7
RESERVED
Reserved
[6:4]
[3:1]
0
LPF2_OVERRIDE
LPF1_OVERRIDE
LPF_DPLX_EN_OVERRIDE
LPF CDAC2 Override Value
LPF CDAC1 Override Value
LPF Diplexer Override Value
0x7
0x7
0x1
R/W
R/W
R/W
Address: 0x0301, Reset: 0x15, Name: IFMAIN_OVERRIDE
7
6
5
4
3
2
1
0
0
0
0
1
0
1
0
1
[ 7 :4 ] RES ERV ED
[ 3 :0 ] IFM AIN _BIAS _O V ERRID E ( R/W )
Bias Ad jus tm e nt Value fo r IF Main Am p lifie r
O v e rrid e .
Table 45. Bit Descriptions for IFMAIN_OVERRIDE
Bits
[7:4]
[3:0]
Bit Name
Settings
Description
Reset
0x1
0x5
Access
R/W
R/W
RESERVED
IFMAIN_BIAS_OVERRIDE
Reserved
Bias Adjustment for IF Main Amplifier Override Value
Rev. A | Page 45 of 61
ADRF6650
Data Sheet
Address: 0x0302, Reset: 0x1F, Name: IFLIN_OVERRIDE
7
6
5
4
3
2
1
0
0
0
0
1
1
1
1
1
[ 7 :4 ] RES ERV ED
[ 3 :0 ] IFL IN _BIAS _O V ERRID E ( R/W )
Bias Ad jus tm e nt Value fo r IF Am p lifie r
Line ariz e r O v e rrid e .
Table 46. Bit Descriptions for IFLIN_OVERRIDE
Bits
[7:4]
[3:0]
Bit Name
Settings
Description
Reset
0x1
0xF
Access
R/W
R/W
RESERVED
IFLIN_BIAS_OVERRIDE
Reserved
Bias Adjustment Value for IF Amplifier Linearizer Override
Address: 0x0303, Reset: 0x04, Name: VGS_OVERRIDE
7
6
5
4
3
2
1
0
0
0
0
0
0
1
0
0
[ 7 :4 ] RES ERV ED
[ 3 :0 ] V G S _O V ERRID E ( R/W )
Mixe r Gate Vo ltag e Se tting O v e rrid e
Value
Table 47. Bit Descriptions for VGS_OVERRIDE
Bits
[7:4]
[3:0]
Bit Name
Settings Description
Reset Access
RESERVED
VGS_OVERRIDE
Reserved.
0x0
0x4
R/W
R/W
Mixer Gate Voltage Setting Override Value
Address: 0x0304, Reset: 0x10, Name: DVGA_TRIM1_LP3V_OVERRIDE
7
6
5
4
3
2
1
0
0
0
0
1
0
0
0
0
[ 7 :5 ] RES ERV ED
[ 4 :0 ] D V G A_T RIM _LP _3 V _CH 1 _O V ERRID E ( R/W )
DVGA Channe l 1 Trim O v e rrid e Bits fo r
3 .3
V Lo w Po w e r O p e ratio n.
Table 48. Bit Descriptions for DVGA_TRIM1_LP3V_OVERRIDE
Bits Bit Name
Settings Description
Reset Access
[7:5] RESERVED
Reserved.
0x0
R
[4:0] DVGA_TRIM_LP_3V_CH1_OVERRIDE
DVGA Channel 1 Trim Override Bits for 3.3 V Low Power
Operation. When DVGA_5V_SEL = 0 and DVGA_HP_SEL = 0.
0x10
R/W
Address: 0x0305, Reset: 0x10, Name: DVGA_TRIM1_HP3V_OVERRIDE
7
6
5
4
3
2
1
0
0
0
0
1
0
0
0
0
[ 7 :5 ] RES ERV ED
[ 4 :0 ] D V G A_T RIM _H P _3 V _CH 1 _O V ERRID E ( R/W )
DVGA Channe l 1 Trim O v e rrid e Bits fo r
3 .3
V Hig h Pe rfo rm anc e O p e ratio n.
Table 49. Bit Descriptions for DVGA_TRIM1_HP3V_OVERRIDE
Bits Bit Name
Settings Description
Reset Access
[7:5] RESERVED
Reserved.
0x0
R
[4:0] DVGA_TRIM_HP_3V_CH1_OVERRIDE
DVGA Channel 1 Trim Override Bits for 3.3 V High Performance 0x10
Operation. When DVGA_5V_SEL = 0 and DVGA_HP_SEL = 1.
R/W
Rev. A | Page 46 of 61
Data Sheet
ADRF6650
Address: 0x0306, Reset: 0x10, Name: DVGA_TRIM1_LP5V_OVERRIDE
7
6
5
4
3
2
1
0
0
0
0
1
0
0
0
0
[ 7 :5 ] RES ERV ED
[ 4 :0 ] D V G A_T RIM _LP _5 V _CH 1 _O V ERRID E ( R/W )
DVGA Channe l 1 Trim O v e rrid e Bits fo r
5
V Lo w Po w e r O p e ratio n.
Table 50. Bit Descriptions for DVGA_TRIM1_LP5V_OVERRIDE
Bits Bit Name
Settings Description
Reset Access
[7:5] RESERVED
Reserved.
0x0
R
[4:0] DVGA_TRIM_LP_5V_CH1_OVERRIDE
DVGA Channel 1 Trim Override Bits for 5 V Low Power
0x10
R/W
Operation. When DVGA_5V_SEL = 1 and DVGA_HP_SEL = 0.
Address: 0x0307, Reset: 0x10, Name: DVGA_TRIM1_HP5V_OVERRIDE
7
6
5
4
3
2
1
0
0
0
0
1
0
0
0
0
[ 7 :5 ] RES ERV ED
[ 4 :0 ] D V G A_T RIM _H P _5 V _CH 1 _O V ERRID E ( R/W )
DVGA Channe l 1 Trim O v e rrid e Bits fo r
5
V Hig h Pe rfo rm anc e O p e ratio n.
Table 51. Bit Descriptions for DVGA_TRIM1_HP5V_OVERRIDE
Bits Bit Name
Settings Description
Reset Access
[7:5] RESERVED
Reserved.
0x0
R
[4:0] DVGA_TRIM_HP_5V_CH1_OVERRIDE
DVGA Channel 1 Trim Override Bits for 5 V High Performance
Operation. When DVGA_5V_SEL = 1 and DVGA_HP_SEL = 1
0x10
R/W
Address: 0x0308, Reset: 0x10, Name: DVGA_TRIM2_LP3V_OVERRIDE
7
6
5
4
3
2
1
0
0
0
0
1
0
0
0
0
[ 7 :5 ] RES ERV ED
[ 4 :0 ] D V G A_T RIM _LP _3 V _CH 2 _O V ERRID E ( R/W )
DVGA Channe l 2 Trim O v e rrid e Bits fo r
3 .3
V Lo w Po w e r O p e ratio n.
Table 52. Bit Descriptions for DVGA_TRIM2_LP3V_OVERRIDE
Bits Bit Name
Settings Description
Reset Access
[7:5] RESERVED
Reserved.
0x0
R
[4:0] DVGA_TRIM_LP_3V_CH2_OVERRIDE
DVGA Channel 2 Trim Override Bits for 3.3 V Low Power
Operation. When DVGA_5V_SEL = 0 and DVGA_HP_SEL = 0.
0x10
R/W
Address: 0x0309, Reset: 0x10, Name: DVGA_TRIM2_HP3V_OVERRIDE
7
6
5
4
3
2
1
0
0
0
0
1
0
0
0
0
[ 7 :5 ] RES ERV ED
[ 4 :0 ] D V G A_T RIM _H P _3 V _CH 2 _O V ERRID E ( R/W )
DVGA Channe l 2 Trim O v e rrid e Bits fo r
3 .3
V Hig h Pe rfo rm anc e O p e ratio n.
Table 53. Bit Descriptions for DVGA_TRIM2_HP3V_OVERRIDE
Bits Bit Name
Settings Description
Reset Access
[7:5] RESERVED
Reserved.
0x0
R
[4:0] DVGA_TRIM_HP_3V_CH2_OVERRIDE
DVGA Channel 2 Trim Override Bits for 3.3 V High Performance 0x10
Operation. When DVGA_5V_SEL = 0 and DVGA_HP_SEL = 1.
R/W
Rev. A | Page 47 of 61
ADRF6650
Data Sheet
Address: 0x0310, Reset: 0x00, Name: OVERRIDE_SELECT
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :6 ] RESERVED
[ 0 ] LPF_T RIM _O VERRIDE_SEL ( R/W )
LPF Override Select Bit; 1 = SPI value
[ 5] DVGA_T RIM _CH2_O VERRIDE_SEL ( R/W )
DVGA Trim Channel 2 Override Select
Bit; 1 = SPI value
[ 1] IFM AIN_T RIM _O VERRIDE_SEL ( R/W )
IF Main Amplifier Trim Override Select
Bit; 1 = SPI value
[ 4 ] DVGA_T RIM _CH1_O VERRIDE_SEL ( R/W )
DVGA Trim Channel 1 Override Select
Bit; 1 = SPI value
[ 2] IFLIN_T RIM _O VERRIDE_SEL ( R/W )
IF Amplifier Linearizer Override Select
Bit; 1 = SPI value
[ 3] VGS_O VERRIDE_SEL ( R/W )
Mixer Gate Voltage Override Select.
Bit; 1 = SPI value
Table 56. Bit Descriptions for OVERRIDE_SELECT
Bits
Bit Name
Settings
Description
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[7:6] RESERVED
Reserved.
5
4
3
2
1
0
DVGA_TRIM_CH2_OVERRIDE_SEL
DVGA_TRIM_CH1_OVERRIDE_SEL
VGS_OVERRIDE_SEL
IFLIN_TRIM_OVERRIDE_SEL
IFMAIN_TRIM_OVERRIDE_SEL
LPF_TRIM_OVERRIDE_SEL
DVGA Trim Channel 2 Override Select Bit; 1 = SPI value
DVGA Trim Channel 1 Override Select Bit; 1 = SPI value
Mixer Gate Voltage Override Select. Bit; 1 = SPI value
IF Amplifier Linearizer Override Select Bit; 1 = SPI value
IF Main Amplifier Trim Override Select Bit; 1 = SPI value
LPF Override Select Bit; 1 = SPI value
Address: 0x1021, Reset: 0xFF, Name: BLOCK_RESETS
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
[ 7 ] RESERVED
[ 0 ] ARST B_BLO CK_DSM ALL ( R/W )
RSTB - DSM Reference Counters, Core,
Output Stage (+ NDIV)
[ 6 ] ARST B_BLO CK_LKD ( R/W )
RSTB - Lock detect
[ 1] ARST B_BLO CK_DSM CO RE ( R/W )
RSTB - DSM Core and Output Stage
(+ NDIV)
[ 5] ARST B_BLO CK_AUT O CAL ( R/W )
RSTB - Autocalibration of FSM/Counters
[ 4 ] ARST B_BLO CK_NDIV ( R/W )
RSTB - NDIV
[ 2] ARST B_BLO CK_DSM O ST G ( R/W )
RSTB - DSM Output Stage (and NDIV)
[ 3] ARST B_BLO CK_RDIV ( R/W )
RSTB - Reference Divider
Table 57. Bit Descriptions for BLOCK_RESETS
Bits
Bit Name
Settings
Description
Reset
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
RESERVED
Reserved.
RSTB - Lock detect
RSTB - Autocalibration of FSM/Counters
RSTB - NDIV
RSTB - Reference Divider
RSTB - DSM Output Stage (and NDIV)
RSTB - DSM Core and Output Stage (+NDIV)
RSTB - DSM Reference Counters, Core, Output Stage (+NDIV)
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
ARSTB_BLOCK_LKD
ARSTB_BLOCK_AUTOCAL
ARSTB_BLOCK_NDIV
ARSTB_BLOCK_RDIV
ARSTB_BLOCK_DSMOSTG
ARSTB_BLOCK_DSMCORE
ARSTB_BLOCK_DSMALL
Rev. A | Page 48 of 61
Data Sheet
ADRF6650
Address: 0x1032, Reset: 0x02, Name: GPO1_CONTROL
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
[ 7 ] RESERVED
[ 0 ] GPO 1_ENABLE ( R/W )
Enable the GPO1 Output
[ 6 :3] GPO 1_BLK_SEL ( R/W )
Select Which Block to Take the Signal
from
[ 2:1] RESERVED
Table 58. Bit Descriptions for GPO1_CONTROL
Bits
7
Bit Name
RESERVED
Settings
Description
Reserved.
Reset
0x0
Access
R/W
[6:3]
[2:1]
0
GPO1_BLK_SEL
RESERVED
GPO1_ENABLE
Select Which Block to Take the Signal from
Reserved.
Enable the GPO1 Output
0x0
0x0
0x0
R/W
R/W
R/W
Address: 0x1033, Reset: 0x00, Name: GPO1_SELECT
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :0 ] GPO 1_SGNL_SEL ( R/W )
Selection of Which Signal to Output
from the Selected Block
Table 59. Bit Descriptions for GPO1_SELECT
Bits
[7:0]
Bit Name
GPO1_SGNL_SEL
Settings
Description
Reset
0x0
Access
R/W
Selection of Which Signal to Output from the Selected Block
Address: 0x1109, Reset: 0x0A, Name: SIG_PATH_9_NORMAL
7
6
5
4
3
2
1
0
0
0
0
0
1
0
1
0
[7:5] RESERVED
[0] RESERVED
[4:3] TRM_MIXLODRV_DRV_POUT (R/W)
[2:1] TRM_XLODRV_DRV_POUT (R/W)
Table 60. Bit Descriptions for SIG_PATH_9_NORMAL
Bits
[7:5]
[4:3]
[2:1]
0
Bit Name
Settings
Description
Reset
0x0
0x1
0x1
0x0
Access
R
R/W
R/W
R
RESERVED
Reserved
TRM_MIXLODRV_DRV_POUT
TRM_XLODRV_DRV_POUT
RESERVED
LO Output to Mixer Power Level
Auxiliary LO output Power Level
Reserved
Address: 0x1200, Reset: 0x89, Name: INT_L
7
6
5
4
3
2
1
0
1
0
0
0
1
0
0
1
[ 7 :0 ] INT _DIV[ 7 :0 ] ( R/W )
Integer-N Word, Optionally Double Buffered.
Table 61. Bit Descriptions for INT_L
Bits
Bit Name
Settings
Description
Reset Access
[7:0]
INT_DIV[7:0]
Integer-N Word, Optionally Double Buffered. Writing the LSB of
the integer word normally causes an autotune event.
0x189 R/W
Rev. A | Page 49 of 61
ADRF6650
Data Sheet
Address: 0x1201, Reset: 0x01, Name: INT_H
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[ 7 :0 ] INT _DIV[ 15:8 ] ( R/W )
Integer-N Word, Optionally Double Buffered.
Table 62. Bit Descriptions for INT_H
Bits Bit Name
Settings Description
Reset Access
[7:0] INT_DIV[15:8]
Integer-N Word, Optionally Double Buffered. Writing the LSB of the integer word
normally causes an autotune event.
0x189 R/W
Address: 0x1202, Reset: 0x00, Name: FRAC1_L
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :0 ] FRAC[ 7 :0 ] ( R/W )
Fractional N Word, Optionally Double
Buffered
Table 63. Bit Descriptions for FRAC1_L
Bits
Bit Name
Settings
Description
Fractional-N Word, Optionally Double Buffered. Lower 8 bits of 24-bit FRAC value.
Reset Access
[7:0] FRAC[7:0]
0x0
R/W
Address: 0x1203, Reset: 0x00, Name: FRAC1_M
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :0 ] FRAC[ 15:8 ] ( R/W )
Fractional N Word, Optionally Double
Buffered
Table 64. Bit Descriptions for FRAC1_M
Bits Bit Name
Settings Description
Reset Access
0x0 R/W
[7:0] FRAC[15:8]
Fractional-N Word, Optionally Double Buffered. Lower 8 bits of 24-bit FRAC value.
Address: 0x1204, Reset: 0x00, Name: FRAC1_H
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :0 ] FRAC[ 23:16 ] ( R/W )
Fractional N Word, Optionally Double
Buffered
Table 65. Bit Descriptions for FRAC1_H
Bits Bit Name
Settings Description
Reset Access
0x0 R/W
[7:0] FRAC[23:16]
Fractional-N Word, Optionally Double Buffered. Lower 8 bits of 24-bit FRAC value.
Rev. A | Page 50 of 61
Data Sheet
ADRF6650
Address: 0x1205, Reset: 0x00, Name: SD_PHASE_L_0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] PHASE[7:0] (R/W)
Sigma-Delta Phase Word
Table 66. Bit Descriptions for SD_PHASE_L_0
Bits Bit Name
Settings Description
Reset Access
[7:0] PHASE[7:0]
Sigma-Delta Phase Word. Lower bits. If phase adjust mode is enabled (PHASE_ADJ_EN = 0x0
1), the phase in the DSM is incremented by this amount on each phase adjustment
trigger. The phase adjustment trigger can be caused from SPI, via a write to the LSB of
this register (provided DISABLE_PHASEADJ = 0), or from the GPI port. The value is
represented as an unsigned 24-bit fractional-Number, in units of VCO cycles. It therefore
has a resolution of 21 µ°. For example, to adjust the phase by 5° of the fundamental VCO,
program this word to (5°/360°) × 224 = 233,017. This process can be done repetitively to
effectively recede by multiple VCO cycles, or to embed the PLL itself inside phase or
frequency control loops under some other supervisory control. The phase adjust feature
must not be done any faster than once every 5 PFD cycles, and by no more than 180° on
any individual adjustment.
R/W
Address: 0x1206, Reset: 0x00, Name: SD_PHASE_M_0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] PHASE[15:8] (R/W)
Sigma-Delta Phase Word
Table 67. Bit Descriptions for SD_PHASE_M_0
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
PHASE[15:8]
Sigma-Delta Phase Word. Middle bits. See description for SD_PHASE_L_0.
0x0
R/W
Address: 0x1207, Reset: 0x00, Name: SD_PHASE_H_0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] PHASE[23:16] (R/W)
Sigma-Delta Phase Word
Table 68. Bit Descriptions for SD_PHASE_H_0
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
PHASE[23:16]
Sigma-Delta Phase Word. Upper bits. See description for SD_PHASE_L_0.
0x0
R/W
Address: 0x1208, Reset: 0x00, Name: MOD_L
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :0 ] M O D2[ 7 :0 ][ 7 :0 ] ( R/W )
MOD2 word.
Table 69. Bit Descriptions for MOD_L
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
MOD2[7:0][7:0]
MOD2 word. Upper bits.
0x0
R/W
Address: 0x1209, Reset: 0x00, Name: MOD_H
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :6 ] RESERVED
[ 5:0 ] M O D2[ 7 :0 ][ 13:8 ] ( R/W )
MOD2 word.
Table 70. Bit Descriptions for MOD_H
Bits
[7:6]
[5:0]
Bit Name
Settings
Description
Reset Access
RESERVED
MOD2[7:0][13:8]
Reserved
MOD2 word. Upper bits.
0x0
0x0
R
R/W
Rev. A | Page 51 of 61
ADRF6650
Data Sheet
Address: 0x120B, Reset: 0x01, Name: SYNTH
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[ 7 :2] RESERVED
[ 0 ] EN_FBDIV ( R/W )
Enable Feedback Divider
[ 1] PRE_SEL ( R/W )
Prescaler Select
0: Disable 2x Prescaler.
1: Enable 2x Prescaler.
Table 71. Bit Descriptions for SYNTH
Bits
[7:2]
1
Bit Name
RESERVED
PRE_SEL
Settings
Description
Reset
0x0
Access
R
Reserved.
Prescaler Select
Disable 2x Prescaler.
Enable 2x Prescaler.
0x0
R/W
0
1
0
EN_FBDIV
Enable Feedback Divider
0x1
R/W
Address: 0x120C, Reset: 0x03, Name: R_DIV
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
1
[7] RESERVED
[6:0] R_DIV (R/W)
R Divider Word
Table 72. Bit Descriptions for R_DIV
Bits
7
[6:0]
Bit Name
RESERVED
R_DIV
Settings
Description
Reserved.
R Divider Word. Lower 8 bits of 10-bit reference R divider word.
Reset
Access
R
R/W
0x0
0x3
Address: 0x120E, Reset: 0x04, Name: SYNTH_0
7
6
5
4
3
2
1
0
0
0
0
0
0
1
0
0
[7:4] RESERVED
[0] RDIV2_SEL (R/W)
Reference Divide by 2
0: Reference Divide by 2 Disabled.
1: Reference Divide by 2 Enabled.
[3] DOUBLER_EN (R/W)
Reference Doubler enable - Optionally
double-buffered
[2:1] RESERVED
Table 73. Bit Descriptions for SYNTH_0
Bits
[7:4]
3
Bit Name
Settings
Description
Reset
0x0
Access
R
RESERVED
DOUBLER_EN
RESERVED
RDIV2_SEL
Reserved
Reference Doubler Enable, Optionally Double-Buffered
Reserved
0x0
R/W
R/W
R/W
[2:1]
0
0x2
Reference Divide by 2
0x0
0
1
Reference Divide by 2 Disabled
Reference Divide by 2 Enabled
Rev. A | Page 52 of 61
Data Sheet
ADRF6650
Address: 0x1214, Reset: 0x48, Name: MULTI_FUNC_SYNTH_CTRL_0214
7
6
5
4
3
2
1
0
0
1
0
0
1
0
0
0
[7:6] LD_BIAS (R/W)
Lock Detect Bias
00: 40uA.
[2:0] RESERVED
01: 30uA.
10: 20uA.
11: 10uA.
[5:3] LDP (R/W)
Lock Detect Precision
000: Check 1024 Consecutive PFD Cycles
for Lock.
001: Check 2048 Consecutive PFD Cycles.
010: Check 4096 Consecutive PFD Cycles.
011: Check 8192 Consecutive PFD Cycles.
Table 74. Bit Descriptions for MULTI_FUNC_SYNTH_CTRL_0214
Bits
Bit Name
Settings
Description
Reset
Access
[7:6]
LD_BIAS
Lock Detect Bias
0x1
R/W
00 40 µA
01 30 µA
10 20 µA
11 10 µA
[5:3]
LDP
Lock Detect Precision
0x1
0x0
R/W
R/W
000 Check 1024 Consecutive PFD Cycles for Lock
001 Check 2048 Consecutive PFD Cycles
010 Check 4096 Consecutive PFD Cycles
011 Check 8192 Consecutive PFD Cycles
Reserved
[2:0]
RESERVED
Address: 0x1217, Reset: 0x00, Name: SI_VCO_SEL
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :4 ] RESERVED
[ 3:0 ] SI_VCO _SEL ( R/W )
Manual VCO Core Select
Table 75. Bit Descriptions for SI_VCO_SEL
Bits
[7:4]
[3:0]
Bit Name
RESERVED
SI_VCO_SEL
Settings
Description
Reset
0x0
0x0
Access
R
R/W
Reserved
Manual VCO Core Select
Address: 0x121F, Reset: 0x00, Name: VCO_FSM
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] RESERVED
[5:0] RESERVED
[6] DISABLE_CAL (R/W)
Disable VCO ALC and AFC Calibration
0: Power Down Synth.
1: Power Up Synth.
Table 76. Bit Descriptions for VCO_FSM
Bits Bit Name Settings Description
Reserved.
Reset Access
7
6
RESERVED
0x0
R
DISABLE_CAL
Disable VCO ALC and AFC Calibration. The PLL does not reset the calibration machine, 0x0
or trigger a new calibration if set to 1 on a frequency hop to maintain ALC and
capacitor positions.
R/W
0
1
Power Down Synth.
Power Up Synth.
[5:0] RESERVED
Reserved.
0x0
R/W
Rev. A | Page 53 of 61
ADRF6650
Data Sheet
Address: 0x122A, Reset: 0x02, Name: SD_CTRL
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
[7:6] RESERVED
[0] RESERVED
[5] SD_EN_FRAC0 (R/W)
[1] SD_SM_2 (R/W)
Sigma Delta Enable with FRAC = 0
Loss of Lock Enabled
[4] SD_EN_OUT_OFF (R/W)
[3:2] RESERVED
Sigma Delta Enable, Output off
Table 77. Bit Descriptions for SD_CTRL
Bits Bit Name
Settings Description
Reset Access
[7:6] RESERVED
Reserved.
0x0
0x0
R/W
R/W
5
SD_EN_FRAC0
Sigma-Delta Enable with FRAC = 0. The DSM normally recognizes a FRAC value of
all 0, and disables itself. Setting this mode can keep the DSM running even when
a zero fractional is presented.
4
SD_EN_OUT_OFF
Sigma-Delta Enable, Output Off. Keeps the DSM core enabled and clocking, but
ignores the output of the DSM and instead muxes the N divider setpoint from the
double-buffer data directly.
0x0
R/W
[3:2] RESERVED
Reserved.
0x0
0x1
0x0
R
R/W
R/W
1
0
SD_SM_2
RESERVED
Loss of Lock Enabled. Enables the CSP/LOL circuit. Recommend reserved 1.
Reserved.
Address: 0x122C, Reset: 0x03, Name: MULTI_FUNC_SYNTH_CTRL_022C
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
1
[7:2] RESERVED
[1:0] CP_HIZ (R/W)
Charge Pump Tristate
0: Charge Pump Tristate Mode 0.
1: Charge Pump Tristate Mode 1.
2: Charge Pump Tristate Mode 2.
3: Charge Pump Tristate Mode 3.
Table 78. Bit Descriptions for MULTI_FUNC_SYNTH_CTRL_022C
Bits
[7:2]
[1:0]
Bit Name
RESERVED
CP_HIZ
Settings
Description
Reset
0x0
Access
R
Reserved
Charge Pump Tristate
Charge Pump Tristate Mode 0
Charge Pump Tristate Mode 1
Charge Pump Tristate Mode 2
Charge Pump Tristate Mode 3
0x3
R/W
0
1
2
3
Address: 0x122D, Reset: 0x81, Name: MULTI_FUNC_SYNTH_CTRL_022D
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
1
[7] EN_PFD_CP (R/W)
[0] BLEED_EN (R/W)
Enable Phase Detector and Charge
Pump
Bleed Enable
[1] RESERVED
[6] BLEED_POL (R/W)
Selects the Bleed Polarity
[2] INT_ABP (R/W)
Integer-N ABP Select
[5:3] RESERVED
Table 79. Bit Descriptions for MULTI_FUNC_SYNTH_CTRL_022D
Bits
Bit Name
EN_PFD_CP
BLEED_POL
RESERVED
INT_ABP
Settings
Description
Reset
0x1
0x0
0x0
0x0
0x0
0x1
Access
R/W
R/W
R
R/W
R
7
6
[5:3]
2
1
Enable Phase Detector and Charge Pump.
Selects the Bleed Polarity.
Reserved.
Integer-N ABP Select. Shortens the reset delay of the PFD by 4 inverters.
Reserved.
RESERVED
BLEED_EN
0
Bleed Enable.
R/W
Rev. A | Page 54 of 61
Data Sheet
ADRF6650
Address: 0x122E, Reset: 0x0F, Name: CP_CURR
7
6
5
4
3
2
1
0
0
0
0
0
1
1
1
1
[7:4] RESERVED
[3:0] CP_CURRENT (R/W)
Main Charge Pump Current
Table 80. Bit Descriptions for CP_CURR
Bits
[7:4]
[3:0]
Bit Name
Settings
Description
Reset
Access
R
R/W
RESERVED
CP_CURRENT
Reserved
Main Charge Pump Current
0x0
0xF
Address: 0x122F, Reset: 0x08, Name: BICP
7
6
5
4
3
2
1
0
0
0
0
0
1
0
0
0
[7:0] BICP (R/W)
Binary Scaled Bleed Current
Table 81. Bit Descriptions for BICP
Bits
Bit Name
Settings
Description
Binary Scaled Bleed Current
Reset
Access
[7:0]
BICP
0x8
R/W
Address: 0x1233, Reset: 0x00, Name: FRAC2_L
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :0 ] FRAC2[ 7 :0 ] ( R/W )
FRAC2 Word for Exact Frequency Mode,
Optionally Double buffered
Table 82. Bit Descriptions for FRAC2_L
Bits
Bit Name
Settings Description
FRAC2 Word for Exact Frequency Mode, Optionally Double Buffered
Reset
Access
[7:0]
FRAC2[7:0]
0x0
R/W
Address: 0x1234, Reset: 0x00, Name: FRAC2_H
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :6 ] RESERVED
[ 5:0 ] FRAC2[ 13:8 ] ( R/W )
FRAC2 Word for Exact Frequency Mode,
Optionally Double buffered
Table 83. Bit Descriptions for FRAC2_H
Bits
[7:6]
[5:0]
Bit Name
Settings
Description
Reserved.
FRAC2 Word for Exact Frequency Mode, Optionally Double Buffered
Reset
0x0
0x0
Access
R
R/W
RESERVED
FRAC2[13:8]
Address: 0x1235, Reset: 0x00, Name: MULTI_FUNC_SYNTH_CTRL_0235
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:2] RESERVED
[0] RESERVED
[1] PHASE_ADJ_EN (R/W)
DSM Phase Adjust Enable
Table 84. Bit Descriptions for MULTI_FUNC_SYNTH_CTRL_0235
Bits Bit Name
Settings Description
Reset Access
[7:2] RESERVED
Reserved.
0x0
0x0
R
1
PHASE_ADJ_EN
DSM Phase Adjust Enable. If set to 1, a phase adjust trigger causes a phase shift in
the delta-sigma by the amount programmed in the phase word. The phase trigger
is either caused by a write to the LSB of the phase word or through a GPI trigger.
R/W
0
RESERVED
Reserved.
0x0
R
Rev. A | Page 55 of 61
ADRF6650
Data Sheet
Address: 0x1240, Reset: 0x00, Name: VCO_LUT_CTRL
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :5] RESERVED
[ 0 ] SI_VCO _FO RCE_CAPS ( R/W )
Force the SPI to Select the VCO Capacitor
[ 4 ] SI_VCO _FO RCE_CAPSVCO I ( R/W )
Manual VCO Capacitor Select
[ 1] SI_VCO _FO RCE_VCO ( R/W )
Force the VCO Select
[ 3:2] RESERVED
Table 85. Bit Descriptions for VCO_LUT_CTRL
Bits
[7:5]
4
[3:2]
1
Bit Name
Settings
Description
Reset
0x0
0x0
0x0
0x0
Access
R
R/W
R/W
R/W
R/W
RESERVED
SI_VCO_FORCE_CAPSVCOI
RESERVED
SI_VCO_FORCE_VCO
SI_VCO_FORCE_CAPS
Reserved
Manual VCO Capacitor Select
Reserved
Force the VCO Select
Force the SPI to Select the VCO Capacitor
0
0x0
Address: 0x124D, Reset: 0x00, Name: LOCK_DETECT
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:1] RESERVED
[0] LOCK_DETECT (R)
State of the Lock Detect Signal
Table 86. Bit Descriptions for LOCK_DETECT
Bits
[7:1]
0
Bit Name
Settings
Description
Reset
0x0
0x0
Access
RESERVED
LOCK_DETECT
Reserved
State of the Lock Detect Signal
R
R
Address: 0x1401, Reset: 0x00, Name: MULTI_FUNC_CTRL
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :5] RESERVED
[ 3:0 ] RESERVED
[ 4 ] SPI_1P8 _3P3_CT RL ( R/W )
SPI Supply Control
0: 1.8 V Read Back.
1: 3.3 V Read Back.
Table 87. Bit Descriptions for MULTI_FUNC_CTRL
Bits
[7:5]
4
Bit Name
Settings
Description
Reset
Access
R
RESERVED
Reserved
0x0
0x0
SPI_1P8_3P3_CTRL
SPI Supply Control
1.8 V Read Back
3.3 V Read Back
Reserved
R/W
0
1
[3:0]
RESERVED
0x0
R
Address: 0x140E, Reset: 0xB3, Name: LO_CNTRL2
7
6
5
4
3
2
1
0
1
0
1
1
0
0
1
1
[7] EN_BIAS_R (R/W)
[4:0] RESERVED
Enable the Resistor Bias
[5] REFBUF_EN (R/W)
[6] RESERVED
Reference Buffer Enable
Table 88. Bit Descriptions for LO_CNTRL2
Bits
Bit Name
Settings
Description
Reset
Access
7
EN_BIAS_R
Enable the Resistor Bias. Selects the resistor bias
instead of bandgap-based bias for the LO path.
0x1
R/W
6
5
[4:0]
RESERVED
REFBUF_EN
RESERVED
Reserved.
Reference Buffer Enable.
Reserved.
0x0
0x1
0x13
R/W
R/W
R/W
Rev. A | Page 56 of 61
Data Sheet
ADRF6650
Address: 0x1414, Reset: 0x02, Name: LO_CNTRL8
Recommended register for use to control the LO path from a single spot. By programming this register, all of the individual block enables
and configuration bits are set appropriately.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
[7] MIX_OE (R/W)
Mix Output Enable
[4:0] OUT_DIVRATIO (R/W)
Output Path Div Ratio
1: /1.
[6] LO_OE (R/W)
LO PAth Output Enable
10: /2.
100: /4.
1000: /8.
10000: /16.
[5] USEEXT_LOI (R/W)
Use External LO Path
Table 89. Bit Descriptions for LO_CNTRL8
Bits Bit Name Settings Description
Reset Access
7
6
5
MIX_OE
Mix Output Enable. When disabled (MIX_OE = 0), MUTE = 1, or DIVRATIO = 0, the
mute depth is selected via GEN_MUTE_DEPTH. Note that the mute depth may be
artificially restricted if the other output path is still enabled and relies on a shared
branch of the LO chain.
0x0
R/W
LO_OE
LO Path Output Enable. When disabled (LO_OE = 0), MUTE = 1, or DIVRATIO = 0, the
mute depth is selected via GEN_MUTE_DEPTH. Note that the mute depth may be
artificially restricted if the other output path is still enabled and relies on a shared
branch of the LO chain.
0x0
R/W
USEEXT_LOI
Use External LO Path.
0x0
0x2
R/W
R/W
[4:0] OUT_DIVRATIO
Output Path Divide Ratio. Sets the divide ratio from the fundamental VCOs or
external input path to the output paths. Nominally, the internal VCO range is 4 GHz
to 8 GHz. 0 = mute.
1
/1.
10 /2.
100 /4.
1000 /8.
10000 /16.
Address: 0x1541, Reset: 0x00, Name: FRAC2_L_SLAVE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :0 ] FRAC2_SLV[ 7 :0 ] ( R)
FRAC2 Word Double Buffered Value
Table 90. Bit Descriptions for FRAC2_L_SLAVE
Bits
Bit Name
Settings
Description
FRAC2 Word Double Buffered Value
Reset
Access
[7:0]
FRAC2_SLV[7:0]
0x0
R
Address: 0x1542, Reset: 0x00, Name: FRAC2_H_SLAVE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :6 ] RESERVED
[ 5:0 ] FRAC2_SLV[ 13:8 ] ( R)
FRAC2 Word Double Buffered Value
Table 91. Bit Descriptions for FRAC2_H_SLAVE
Bits
[7:6]
[5:0]
Bit Name
Settings
Description
Reset
0x0
0x0
Access
RESERVED
FRAC2_SLV[13:8]
Reserved
FRAC2 Word Double Buffered Value
R
R
Rev. A | Page 57 of 61
ADRF6650
Data Sheet
Address: 0x1543, Reset: 0x00, Name: FRAC_L_SLAVE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :0 ] FRAC_SLV[ 7 :0 ] ( R)
Fractional-N Word Double Buffered Value
Table 92. Bit Descriptions for FRAC_L_SLAVE
Bits Bit Name Settings Description
[7:0] FRAC_SLV[7:0] Fractional-N Word Double Buffered Value. Lower 8 bits of 24-bit FRAC value.
Reset Access
0x0
R
Address: 0x1544, Reset: 0x00, Name: FRAC_M_SLAVE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :0 ] FRAC_SLV[ 15:8 ] ( R)
Fractional-N Word Double Buffered Value
Table 93. Bit Descriptions for FRAC_M_SLAVE
Bits Bit Name
Settings Description
Reset Access
0x0
[7:0] FRAC_SLV[15:8]
Fractional-N Word Double Buffered Value. Middle 8 bits of 24-bit FRAC value.
R
Address: 0x1545, Reset: 0x00, Name: FRAC_H_SLAVE2
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :0 ] FRAC_SLV[ 23:16 ] ( R)
Fractional-N Word Double Buffered Value
Table 94. Bit Descriptions for FRAC_H_SLAVE2
Bits Bit Name
Settings Description
Reset Access
[7:0] FRAC_SLV[23:16]
Fractional-N Word Double Buffered Value. Higher 8 bits of 24-bit FRAC value.
0x0
R
Address: 0x1546, Reset: 0x00, Name: PHASE_L_SLAVE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] PHASE_SLV[7:0] (R)
Sigma-Delta Phase Word
Table 95. Bit Descriptions for PHASE_L_SLAVE
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
PHASE_SLV[7:0]
Sigma-Delta Phase Word. Lower 8 bits of 24-bit SD phase word.
0x0
R
Address: 0x1547, Reset: 0x00, Name: PHASE_M_SLAVE2
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] PHASE_SLV[15:8] (R)
Sigma-Delta Phase Word
Table 96. Bit Descriptions for PHASE_M_SLAVE2
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
PHASE_SLV[15:8]
Sigma-Delta Phase Word. Middle 8 bits of 24-bit SD phase word.
0x0
R
Address: 0x1548, Reset: 0x00, Name: PHASE_H_SLAVE3
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] PHASE_SLV[23:16] (R)
Sigma-Delta Phase Word
Table 97. Bit Descriptions for PHASE_H_SLAVE3
Bits Bit Name Settings Description
[7:0] PHASE_SLV[23:16]
Reset
Access
Sigma-Delta Phase Word. Lower Higher 8 bits of 24-bit SD phase word.
0x0
R
Rev. A | Page 58 of 61
Data Sheet
ADRF6650
Address: 0x1549, Reset: 0x89, Name: INT_DIV_L_SLAVE
7
6
5
4
3
2
1
0
1
0
0
0
1
0
0
1
[7:0] INT_DIV_SLV[7:0] (R)
Integer-N Word - Double Buffered
Readback Value
Table 98. Bit Descriptions for INT_DIV_L_SLAVE
Bits Bit Name Settings Description
[7:0] INT_DIV_SLV[7:0]
Reset Access
Integer-N Word, Double Buffered Readback Value. Readback data from the
N setpoint double buffer output.
0x189
R
Address: 0x154A, Reset: 0x01, Name: INT_DIV_H_SLAVE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[7:0] INT_DIV_SLV[15:8] (R)
Integer-N Word - Double Buffered
Readback Value
Table 99. Bit Descriptions for INT_DIV_H_SLAVE
Bits Bit Name
Settings Description
Reset Access
[7:0] INT_DIV_SLV[15:8]
Integer-N Word, Double Buffered Readback Value. Readback data from the
N setpoint double buffer output.
0x189
R
Address: 0x154B, Reset: 0x03, Name: R_DIV_SLAVE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
1
[7] RESERVED
[6:0] R_DIV_SLV (R)
R Divider Word
Table 100. Bit Descriptions for R_DIV_SLAVE
Bits
Bit Name
RESERVED
R_DIV_SLV
Settings
Description
Reset
Access
7
[6:0]
Reserved.
0x0
0x3
R
R
R Divider Word. Lower 8 bits of 10-bit reference R divider word.
Address: 0x154C, Reset: 0x00, Name: RDIV2_SEL_SLAVE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:1] RESERVED
[0] RDIV2_SEL_SLV (R)
Reference Divide by 2
0: Reference Divide by 2 Disabled.
1: Reference Divide by 2 Enabled.
Table 101. Bit Descriptions for RDIV2_SEL_SLAVE
Bits
[7:1]
0
Bit Name
Settings Description
Reset
Access
RESERVED
Reserved
0x0
0x0
R
R
RDIV2_SEL_SLV
Reference Divide by 2
0
1
Reference Divide by 2 Disabled
Reference Divide by 2 Enabled
Rev. A | Page 59 of 61
ADRF6650
Data Sheet
Address: 0x1583, Reset: 0x00, Name: DISABLE_CFG
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :5] RESERVED
[ 0 ] DISABLE_PHASEADJ( R/W )
Disable the Phase Adjust from the SPI
Register
[ 4 :3] DSM _LAUNCH_DLY ( R/W )
Delay the DSM Clock Launch.
[ 1] DISABLE_DBLBUFFERING ( R/W )
If Disabled, an RDIV Write Resets R Divider
[ 2] DISABLE_FREQ HO P ( R/W )
Disable the Generation of Frequency
Hop from the SPI Register
Table 102. Bit Descriptions for DISABLE_CFG
Bits Bit Name Settings
Description
Reset
0x0
Access
R
[7:5] RESERVED
Reserved.
[4:3] DSM_LAUNCH_DLY
Delay the DSM Clock Launch.
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
2
1
0
DISABLE_FREQHOP
DISABLE_DBLBUFFERING
DISABLE_PHASEADJ
Disable the Generation of Frequency Hop from the SPI Register
If Disabled, an RDIV Write Resets R Divider
Disable the Phase Adjust from the SPI Register
Rev. A | Page 60 of 61
Data Sheet
ADRF6650
OUTLINE DIMENSIONS
8.10
8.00 SQ
7.90
0.30
0.25
0.20
PIN 1
INDICATOR
PIN 1
INDICATOR
43
56
1
42
0.50
BSC
EXPOSED
PAD
*
6.80
6.70 SQ
6.60
29
14
28
15
0.45
0.40
0.35
BOTTOM VIEW
6.50 REF
0.20 MIN
TOP VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.203 REF
*
COMPLIANT TO JEDEC STANDARDS MO-220-WLLD-5
WITH EXCEPTION TO EXPOSED PAD DIMENSION.
Figure 72. 56-Lead Lead Frame Chip Scale Package [LFCSP]
8 mm × 8 mm Body and 0.75 mm Package Height
(CP-56-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
ADRF6650ACPZ
ADRF6650ACPZ-RL7
ADRF6650-EVALZ
−40°C to +105°C
−40°C to +105°C
56-Lead Lead Frame Chip Scale Package [LFCSP]
56-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
CP-56-16
CP-56-16
1 Z = RoHS Compliant Part.
©2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14813-0-11/19(A)
Rev. A | Page 61 of 61
相关型号：
ADRF6701ACPZ
RF/Microwave Modulator/Demodulator, 750 MHz - 1160 MHz RF/MICROWAVE I/Q MODULATOR, 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, LFCSP_VQ, CP-40-1, 40 PIN
ADI
©2020 ICPDF网 联系我们和版权申明