ADRF6720-EVALZ [ADI]
Wideband Quadrature Modulator with Integrated Fractional-N PLL and VCOs;
| 型号： | ADRF6720-EVALZ |
| 厂家： | 
ADI |
| 描述： | Wideband Quadrature Modulator with Integrated Fractional-N PLL and VCOs |
| 文件： | 总44页 (文件大小：3418K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Wideband Quadrature Modulator with
Integrated Fractional-N PLL and VCOs
Data Sheet
ADRF6720
FEATURES
GENERAL DESCRIPTION
I/Q modulator with integrated fractional-N PLL
RF output frequency range: 700 MHz to 3000 MHz
Internal LO frequency range: 356.25 MHz to 2855 MHz
Output P1dB: 12.2 dBm at 2140 MHz
The ADRF6720 is a wideband quadrature modulator with an
integrated synthesizer ideally suited for 3G and 4G
communication systems. The ADRF6720 consists of a high
linearity broadband modulator, an integrated fractional-N
phase-locked loop (PLL), and four low phase noise multicore
voltage controlled oscillators (VCOs).
Output IP3: 32.6 dBm at 2140 MHz
Carrier feedthrough: −40.3 dBm at 2140 MHz
Sideband suppression: −37.6 dBc at 2140 MHz
Noise floor: −157.9 dBm/Hz at 2140 MHz
Baseband 1 dB modulation bandwidth: >1000 MHz
Baseband input bias level: 0.5 V
Power supply: 3.3 V/425 mA
Integrated RF tunable balun allowing single-ended RF output
Multicore integrated VCOs
HD3/IP3 optimization
Sideband suppression and carrier feedthrough optimization
High-side/low-side LO injection
Programmable via 3-wire serial port interface (SPI)
40-lead 6 mm × 6 mm LFCSP
The ADRF6720 local oscillator (LO) signal can be generated
internally via the on-chip integer-N and fractional-N
synthesizers, or externally via a high frequency, low phase noise
LO signal. The internal integrated synthesizer enables LO
coverage from 356.25 MHz to 2855 MHz using the multicore
VCOs. In the case of internal LO generation or external LO
input, quadrature signals are generated with a divide-by-2 phase
splitter. When the ADRF6720 is operated with an external 1 ×
LO input, a polyphase filter generates the quadrature inputs to
the mixer.
The ADRF6720 offers digital programmability for carrier
feedthrough optimization, sideband suppression, HD3/IP3
optimization, and high-side or low-side LO injection.
APPLICATIONS
2G/3G/4G/LTE broadband communication systems
Microwave point-to-point radios
Satellite modems
Military/aerospace
Instrumentation
The ADRF6720 is fabricated using an advanced silicon-
germanium BiCMOS process. It is available in a 40-lead,
RoHS-compliant, 6 mm × 6 mm LFCSP package with an
exposed pad. Performance is specified over the −40°C to +85°C
temperature range.
FUNCTIONAL BLOCK DIAGRAM
VPOSx
40
35
30
26
22
17
11
6
I+
I–
3
4
27
24
ENBL
ADRF6720
V TO I
PHASE
CORRECTION
LO NULLING
DAC
RFOUT
LO NULLING
DAC
PHASE
CORRECTION
8
Q–
Q+
V TO I
PLL
18
19
LOOUT+
LOOUT–
9
39
36
REFIN
CP
QUAD
DIVIDER
32
VTUNE
LOIN–
LOIN+
33
34
15
14
13
CS
SERIAL
PORT
INTERFACE
POLYPHASE
FILTER
LDO
2.5V
LDO
VCO
SCLK
SDIO
2
5
7 10 16 20 23 25 29 37 38
12
31
28
DECL1 DECL2
DECL3
GND
Figure 1.
Rev. 0
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rightsof third parties that may result fromits use. Specifications subject to change without notice. No
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Tel: 781.329.4700
©2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADRF6720
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Baseband Inputs ......................................................................... 24
LO Input ...................................................................................... 24
Loop Filter................................................................................... 24
RF Output.................................................................................... 24
Applications Information .............................................................. 25
DAC-to-I/Q Modulator Interfacing......................................... 25
Baseband Bandwidth ................................................................. 25
Carrier Feedthrough Nulling.................................................... 26
Sideband Suppression Optimization ....................................... 26
Linearity....................................................................................... 27
LO Amplitude and Common Mode Voltage.......................... 27
Layout........................................................................................... 27
Characterization Setups................................................................. 29
Register Map ................................................................................... 31
Register Details ............................................................................... 32
Outline Dimensions ....................................................................... 42
Ordering Guide .......................................................................... 42
Applications....................................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 7
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 18
LO Generation Block.................................................................. 18
Baseband...................................................................................... 21
Active Mixers .............................................................................. 21
Serial Port Interface.................................................................... 22
Basic Connections for Operation................................................. 23
Power Supply and Grounding................................................... 23
REVISION HISTORY
4/14—Revision 0: Initial Version
Rev. 0 | Page 2 of 44
Data Sheet
ADRF6720
SPECIFICATIONS
VPOSx = 3.3 V, TA = 25°C; baseband I/Q amplitude = 1 V p-p differential sine waves in quadrature with a 500 mV dc bias, unless
otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max Unit
OPERATING FREQUENCY
RANGE
RF output range
700
3000 MHz
Internal LO range
External LO range
356.25
700
2855 MHz
3000 MHz
RF OUTPUT = 940 MHz
Output Power, POUT
Modulator Voltage Gain
Output P1dB
Carrier Feedthrough
Sideband Suppression
Quadrature Error
I/Q Amplitude Balance
Second Harmonic
Third Harmonic
Baseband VIQ = 1 V p-p differential
5.8
1.82
13.1
−44.0
−47.1
−0.15
−0.01
−66.1
−60.6
66.4
dBm
dB
dBm
dBm
dBc
Degrees
dB
dBc
dBc
dBm
POUT − P(fLO (2 × fBB))
POUT − P(fLO (3 × fBB))
f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone =
0.45 V p-p differential
Output IP2
Output IP3
Noise Floor
f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone =
0.45 V p-p differential
I/Q input with 500 mV dc bias and no RF output, 20 MHz carrier offset
36.2
dBm
−157.6
−157.3
dBm/Hz
dBm/Hz
I/Q input with 500 mV dc bias and −10 dBm RF output, 20 MHz carrier
offset
RF OUTPUT = 1900 MHz
Output Power, POUT
Modulator Voltage Gain
Output P1dB
Carrier Feedthrough
Sideband Suppression
Quadrature Error
I/Q Amplitude Balance
Second Harmonic
Third Harmonic
Baseband VIQ = 1 V p-p differential
5.6
1.62
13.1
−39.2
−41.2
1.15
−0.0175
−66.2
−57.2
62.2
dBm
dB
dBm
dBm
dBc
Degrees
dB
dBc
POUT − P(fLO (2 × fBB))
POUT − P(fLO (3 × fBB))
f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone =
0.45 V p-p differential
dBc
dBm
Output IP2
Output IP3
Noise Floor
f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone =
0.45 V p-p differential
I/Q input with 500 mV dc bias and no RF output, 20 MHz carrier offset
35.7
dBm
−158.8
−158.1
dBm/Hz
dBm/Hz
I/Q input with 500 mV dc bias and −10 dBm RF output, 20 MHz carrier
offset
RF OUTPUT = 2140 MHz
Output Power, POUT
Modulator Voltage Gain
Output P1dB
Carrier Feedthrough
Sideband Suppression
Quadrature Error
I/Q Amplitude Balance
Second Harmonic
Third Harmonic
Baseband VIQ = 1 V p-p differential
5
1.12
12.2
−40.3
−37.6
−1.15
−0.022
−57.9
−58.1
dBm
dB
dBm
dBm
dBc
Degrees
dB
dBc
POUT − P(fLO (2 × fBB))
POUT − P(fLO (3 × fBB))
dBc
Rev. 0 | Page 3 of 44
ADRF6720
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max Unit
Output IP2
f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone =
0.45 V p-p differential
57.7
dBm
Output IP3
Noise Floor
f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone =
0.45 V p-p differential
I/Q input with 500 mV dc bias and no RF output, 20 MHz carrier offset
32.6
dBm
−157.9
−156.3
dBm/Hz
dBm/Hz
I/Q input with 500 mV dc bias and −10 dBm RF output, 20 MHz carrier
offset
RF OUTPUT = 2300 MHz
Output Power, POUT
Modulator Voltage
Gain
Baseband VIQ = 1 V p-p differential
4.6
0.62
dBm
dB
Output P1dB
11.8
dBm
dBm
dBc
Degrees
dB
dBc
dBc
dBm
Carrier Feedthrough
Sideband Suppression
Quadrature Error
I/Q Amplitude Balance
Second Harmonic
Third Harmonic
−37.6
−36.6
−1.5
−0.0285
−54.8
−56.6
57.6
POUT − P(fLO (2 × fBB))
POUT − P(fLO (3 × fBB))
f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone =
0.45 V p-p differential
Output IP2
Output IP3
Noise Floor
f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone =
0.45 V p-p differential
I/Q input with 500 mV dc bias and no RF output, 20 MHz carrier offset
30.4
dBm
−159.2
−157.5
dBm/Hz
dBm/Hz
I/Q input with 500 mV dc bias and −10 dBm RF output, 20 MHz carrier
offset
RF OUTPUT = 2600 MHz
Output Power, POUT
Modulator Voltage
Gain
Baseband VIQ = 1 V p-p differential
3.9
−0.08
dBm
dB
Output P1dB
11.3
dBm
dBm
dBc
Degrees
dB
dBc
dBc
dBm
Carrier Feedthrough
Sideband Suppression
Quadrature Error
I/Q Amplitude Balance
Second Harmonic
Third Harmonic
−36.5
−42.3
−0.55
−0.021
−60.3
−54.7
56.6
POUT − P(fLO (2 × fBB))
POUT − P(fLO (3 × fBB))
f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone =
0.45 V p-p differential
Output IP2
Output IP3
Noise Floor
f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone =
0.45 V p-p differential
I/Q input with 500 mV dc bias and no RF output, 20 MHz carrier offset
29.9
dBm
−159.2
−157.3
dBm/Hz
dBm/Hz
I/Q input with 500 mV dc bias and −10 dBm RF output, 20 MHz carrier
offset
SYNTHESIZER
Synthesizer specifications referenced to the modulator output
SPECIFICATIONS
Figure of Merit (FOM)1
−218.5
dBc/Hz/Hz
REFERENCE
REFIN, MUXOUT pins
CHARACTERISTICS
REFIN Input
Frequency
REFIN Input
Amplitude
Phase Detector
Frequency
5.7
320
40
MHz
dBm
MHz
4
11.4
Rev. 0 | Page 4 of 44
Data Sheet
ADRF6720
Parameter
Test Conditions/Comments
Min
Typ
0.25
2.7
Max Unit
MUXOUT Output Level Low (lock detect output selected)
High (lock detect output selected)
MUXOUT Duty Cycle
V
V
%
50
CHARGE PUMP
Charge Pump Current
Programmable to 250 μA, 500 μA, 750 μA, or 1000 μA
1000
μA
Output Compliance
Range
1
2.8
V
PHASE NOISE,
FREQUENCY =
940 MHz,
Closed-loop operation (20 kHz loop filter, see Figure 44 for loop filter
design)
fPFD = 38.4 MHz
10 kHz offset
100 kHz offset
1 MHz offset
5 MHz offset
−97.8
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
° rms
−120.8
−144.4
−154.4
−154.9
−155.3
0.175
10 MHz offset
20 MHz offset
1 kHz to 40 MHz integration bandwidth, with spurs
Integrated Phase
Noise
Reference Spurs
fPFD
−104.8
−97.8
−98.8
−103
dBc
dBc
dBc
dBc
fPFD × 2
fPFD × 3
fPFD × 4
PHASE NOISE,
FREQUENCY =
1900 MHz,
Closed-loop operation (20 kHz loop filter, see Figure 44 for loop filter
design)
f
PFD = 38.4 MHz
10 kHz offset
100 kHz offset
1 MHz offset
5 MHz offset
−91.5
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
° rms
−114.5
−139.9
−151.4
−153
10 MHz offset
20 MHz offset
1 kHz to 40 MHz integration bandwidth, with spurs
−153.5
0.332
Integrated Phase
Noise
Reference Spurs
fPFD
−102
dBc
dBc
dBc
dBc
fPFD × 2
fPFD × 3
fPFD × 4
−90.8
−93.6
−100.5
PHASE NOISE,
FREQUENCY =
2140 MHz,
Closed-loop operation (20 kHz loop filter, see Figure 44 for loop filter
design)
fPFD = 38.4 MHz
10 kHz offset
100 kHz offset
1 MHz offset
5 MHz offset
10 MHz offset
20 MHz offset
1 kHz to 40 MHz integration bandwidth, with spurs
−92
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
° rms
−115.7
−140.3
−151.3
−152.1
−152.9
0.305
Integrated Phase
Noise
Reference Spurs
fPFD
−95.9
−93.1
−87.4
−91.5
dBc
dBc
dBc
dBc
fPFD × 2
fPFD × 3
fPFD × 4
Rev. 0 | Page 5 of 44
ADRF6720
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max Unit
PHASE NOISE,
FREQUENCY =
2300 MHz,
Closed-loop operation (20 kHz loop filter, see Figure 44 for loop filter
design)
fPFD = 38.4 MHz
10 kHz offset
100 kHz offset
1 MHz offset
5 MHz offset
10 MHz offset
20 MHz offset
1 kHz to 40 MHz integration bandwidth, with spurs
−94.1
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
° rms
−114.6
−138.7
−150.1
−151.4
−152.6
0.270
Integrated Phase
Noise
Reference Spurs
fPFD
−100.8
−95.6
−89.4
−93.1
dBc
dBc
dBc
dBc
fPFD × 2
fPFD × 3
fPFD × 4
PHASE NOISE,
FREQUENCY =
2600 MHz,
Closed-loop operation (20 kHz loop filter, see Figure 44 for loop filter
design)
f
PFD = 38.4 MHz
10 kHz offset
100 kHz offset
1 MHz offset
5 MHz offset
10 MHz offset
20 MHz offset
1 kHz to 40 MHz integration bandwidth, with spurs
−91.5
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
−111.3
−136.8
−148.3
−150
−150.7
0.378
Integrated Phase
Noise
Reference Spurs
fPFD
−97.4
−89.3
−95.2
−91.4
dBc
dBc
dBc
dBc
fPFD × 2
fPFD × 3
fPFD × 4
LO INPUT/OUTPUT
LO Output Frequency
Range
LO Output Level
LO output
700
−6
2855 MHz
2 × LO or 1 × LO mode, into a 50 Ω load, LO buffer enabled at 2140 MHz
LO_DRV_LVL = 0
LO_DRV_LVL = 1
−5.1
−0.5
3
0
50
dBm
dBm
dBm
LO_DRV_LVL = 2
LO Input Level
LO Input Impedance
BASEBAND INPUTS
Externally applied LO, PLL disabled
Externally applied LO, PLL disabled
I and Q pins
+6
dBm
Ω
I and Q Input DC Bias
Level
0.5
V
Bandwidth
Differential Input
Impedance
Differential Input
Capacitance
1 dB
>1000
465
MHz
Ω
Frequency = 10 MHz2
Frequency = 10 MHz2
1.84
pF
OUT ENABLE
ENBL pin
Turn-On Settling Time
ENBL high to low (90% of envelope), when Register 0x01[10] = 1,
Register 0x10[10] = 1
190
20
ns
ns
Turn-Off Settling Time ENBL low to high (10% of envelope), when Register 0x01[10] = 1,
Register 0x10[10] = 1
Rev. 0 | Page 6 of 44
Data Sheet
ADRF6720
Parameter
Test Conditions/Comments
Min
Typ
Max Unit
DIGITAL LOGIC
SCLK, SDIO, CS, and ENBL
Input Voltage High (VIH)
Input Voltage Low (VIL)
Input Current (IIH/IIL)
Input Capacitance
(CIN)
1.4
−1
V
V
µA
pF
0.7
1
5
Output Voltage High
(VOH)
Output Voltage Low
(VOL)
IOH = −100 uA
IOL = 100 uA
2.3
V
V
0.2
POWER SUPPLIES
Voltage Range
Supply Current
VPOSx
3.3
425
V
mA
Tx mode at internal LO mode (PLL, internal VCO , and modulator
enabled, LO output driver disabled)
Tx mode at external 1× LO mode (PLL, internal VCO disabled,
modulator enabled, LO output driver disabled)
228
mA
LO output driver; LO_DRV_LVL bits (Register 0x22[7:6]) = 10
Power-down mode
50
14.5
mA
mA
1 The figure of merit (FOM) is computed as phase noise (dBc/Hz) – 10log10(fPFD) − 20log10(fLO/fPFD). The FOM was measured across the full LO range, with fREF
153.6 MHz, fREF power = 4 dBm with a 38.4 MHz fPFD. The FOM was computed at a 50 kHz offset.
=
2 Refer to Figure 47 for a plot of input impedance over frequency.
TIMING CHARACTERISTICS
Table 2.
Parameter Description
tSCLK Serial clock period
tDS
Min Typ Max Units
38
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
Setup time between data and rising edge of SCLK
tDH
Hold time between data and rising edge of SCLK
8
tS
Setup time between falling edge of CS and SCLK
10
10
10
10
tH
Hold time between rising edge of CS and SCLK
tHIGH
tLOW
tACCESS
tz
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Maximum time delay between falling edge of SCLK and output data valid for a read operation
Maximum time delay between CS deactivation and SDIO bus return to high impedance
231
5
tHIGH
tH
tDS
tSCLK
tS
tDH
tLOW
tACCESS
CS
DON'T CARE
tZ
DON'T CARE
DON'T CARE
SCLK
SDIO
A6
A5
A4
A3
A2
A1
A0
R/W
D15
D14
D13
D3
D2
D1
D0
DON'T CARE
Figure 2. Serial Port Timing Diagram
Rev. 0 | Page 7 of 44
ADRF6720
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
θJA is thermal resistance, junction to ambient (°C/W), and θJC is
thermal resistance, junction to case (°C/W).
Parameter
Rating
Supply Voltage
I+, I−, Q+, Q−
LOIN+, LOIN−
REFIN
ENBL
−0.3 V to +3.6 V
−0.5 V to +1.5 V
16 dBm differential
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
150°C
Table 4. Thermal Resistance
1
1
Package Type
θJA
θJC
0.44
Unit
40-Lead LFCSP
30.23
°C/W
VTUNE
1 See JEDEC standard JESD51-2 for information on optimizing thermal
impedance.
CS, SCLK, SDIO
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
−40°C to +85°C
−65°C to +150°C
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. 0 | Page 8 of 44
Data Sheet
ADRF6720
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
MUXOUT
GND
I+
1
2
3
4
5
6
7
8
9
30 VPOS6
29 GND
28 DECL2
I–
ENBL
27
26
ADRF6720
GND
VPOS1
GND
Q–
Q+
GND 10
VPOS5
TOP VIEW
25 GND
RFOUT
(Not to Scale)
24
23 GND
22 VPOS4
21 NIC
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
2. SOLDER THE EXPOSED PAD TO A LOW IMPEDANCE
GROUND PLANE.
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
MUXOUT
Multiplexer Output. This output allows a digital lock detect signal, a voltage
proportional to absolute temperature ( VPTAT ), or a buffered, frequency-scaled
reference signal to be accessed externally. The output is selected by programming
Bits[6:4] in Register 0x21.
2, 10
3, 4
5, 7
6
GND
I+, I−
GND
Baseband Ground.
Differential In-Phase Baseband Inputs.
Mixer Core (I and Q) Ground.
3.3 V Supply Voltage for Baseband. Decouple VPOS1 with 100 pF and 0.1 µF
capacitors located close to the pin.
VPOS1
8, 9
11
Q−, Q+
VPOS2
Differential Quadrature Baseband Inputs.
3.3 V Supply Voltage for 2.5 V LDO. Decouple VPOS2 with 100 pF and 0.1 µF
capacitors located close to the pin.
12
DECL1
Decoupling Pin for 2.5 V LDO. Connect 100 pF, 0.1 µF, and 10 µF capacitors between
this pin and ground.
13
14
15
16
17
SDIO
SCLK
CS
Serial Data Input/Output for SPI.
Serial Clock Input/Output for SPI.
Chip Select Input/Output for SPI.
Digital Ground.
3.3 V Supply Voltage for LO. Decouple VPOS3 with 100 pF and 0.1 µF capacitors
located close to the pin.
GND
VPOS3
18, 19
LOOUT+, LOOUT−
Differential LO Outputs. Either the internally generated LO or external 1 × LO/2 × LO
is available at 1 × LO or 2 × LO on these pins.
20
21
22
GND
NIC
VPOS4
LO Ground.
Not Internally Connected. This pin can be left open or tied to RF ground.
3.3 V Supply Voltage for RF. Decouple VPOS4 with 100 pF and 0.1 µF capacitors
located close to the pin.
23, 25
24
26
GND
RFOUT
VPOS5
RF Ground.
Single-Ended 0 V DC RF Output.
3.3 V Supply Voltage for RF. Decouple VPOS5 with 100 pF and 0.1 µF capacitors
located close to the pin.
27
28
29
ENBL
DECL2
GND
Enables/Disables the Circuit Blocks. References the settings at Register 0x01 and
Register 0x10. Refer to the ENBL section for more information.
Decoupling Pin for VCO LDO. Connect 100 pF, 0.1 µF, and 10 µF capacitors between
this pin and ground.
VCO Ground.
Rev. 0 | Page 9 of 44
ADRF6720
Data Sheet
Pin No.
Mnemonic
Description
30
VPOS6
3.3 V Supply Voltage for VCO LDO. Decouple VPOS6 with 100 pF and 0.1 µF
capacitors located close to the pin.
31
DECL3
Decoupling Pin for VCO LDO. Connect 100 pF, 0.1 µF, and 10 µF capacitors between
this pin and ground.
32
VTUNE
VCO Tuning Voltage.
33, 34
35
LOIN−, LOIN+
VPOS7
Differential External LO Inputs.
3.3 V Supply Voltage for Charge Pump. Decouple VPOS7 with 100 pF and 0.1 µF
capacitors located close to the pin.
36
37
38
39
40
CP
Charge Pump Output.
Charge Pump Ground.
PLL Reference Ground.
PLL Reference Input.
3.3 V Supply Voltage for PLL Reference. Decouple VPOS8 with 100 pF and 0.1 µF
capacitors located close to the pin.
GND
GND
REFIN
VPOS8
EP
Exposed Pad. Solder the exposed pad to a low impedance ground plane.
Rev. 0 | Page 10 of 44
Data Sheet
ADRF6720
TYPICAL PERFORMANCE CHARACTERISTICS
VPOSx = 3.3 V; TA = 25°C; baseband I/Q amplitude = 1 V p-p differential sine waves in quadrature with a 500 mV dc bias; baseband I/Q
frequency (fBB) = 1 MHz; fPFD = 38.4 MHz; fREF = 153.6 MHz at 4 dBm referred to 50 Ω (1 V p-p); 20 kHz loop filter, unless otherwise
noted.
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
T
T
T
= –40°C
= +25°C
= +85°C
3.15V
3.3V
3.45V
A
A
A
700
1200
1700
2200
2700
700
1200
1700
2200
2700
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 4. Single Sideband (SSB) Output Power (POUT) vs. LO Frequency (fLO
)
Figure 7. SSB Output Power (POUT) vs. LO Frequency (fLO) and Supply
and Temperature; Multiple Devices Shown
16
16
T
T
T
= –40°C
= +25°C
= +85°C
3.15V
3.3V
3.45V
A
A
A
14
12
10
8
14
12
10
8
6
6
4
4
2
2
0
700
0
700
1200
1700
2200
2700
1200
1700
2200
2700
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 5. SSB 1 dB Output Compression Point (OP1dB) vs. LO Frequency (fLO
)
Figure 8. SSB 1 dB Output Compression Point (OP1dB) vs. LO Frequency (fLO)
and Temperature; Multiple Devices Shown
and Supply
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
T
T
T
= –40°C
= +25°C
= +85°C
T
A
= –40°C
= +25°C
= +85°C
A
A
A
T
A
T
A
700
1200
1700
2200
2700
700
1200
1700
2200
2700
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 6. Carrier Feedthrough vs. LO Frequency (fLO) and Temperature Before
Nulling; Multiple Devices Shown
Figure 9. Carrier Feedthrough vs. LO Frequency (fLO) and Temperature After
Nulling Using DCOFF_I and DCOFF_Q at 25°C; Multiple Devices Shown
Rev. 0 | Page 11 of 44
ADRF6720
Data Sheet
0
–10
–20
–30
–40
–50
–60
–70
–80
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
T
T
T
= –40°C
= +25°C
= +85°C
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
A
A
A
–90
700
1200
1700
2200
2700
700
1200
1700
2200
2700
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 10. Sideband Suppression vs. LO Frequency (fLO) and Temperature
Before Nulling; Multiple Devices Shown
Figure 13. Sideband Suppression vs. LO Frequency (fLO) and Temperature
After Nulling Using I_LO and Q_LO at 25°C; Multiple Devices Shown
80
–20
T
T
T
= –40°C
= +25°C
= +85°C
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
A
A
A
SECOND-ORDER
THIRD-ORDER
70
60
50
40
30
20
10
0
OIP2
–30
–40
–50
–60
–70
–80
–90
OIP3
700
1200
1700
2200
2700
700
1200
1700
2200
2700
LO FEQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 11. OIP3 and OIP2 vs. LO Frequency (fLO) and Temperature (POUT
−5 dBm per Tone); Multiple Devices Shown
≈
Figure 14. Second- and Third-Order Harmonics vs. LO Frequency (fLO) and
Temperature (POUT ≈ 5 dBm)
0
–10
–20
–30
–40
–50
–60
–70
–80
20
0
–10
–20
–30
–40
–50
–60
–70
–80
20
15
10
5
THIRD-ORDER
THIRD-ORDER
HARMONIC (dBc)
HARMONIC (dBC)
15
SSB OUTPUT
POWER (dBm)
SSB OUTPUT
POWER (dBm)
10
5
SIDEBAND
SUPPRESSION (dBC)
SIDEBAND
SUPPRESSION (dBc)
0
0
CARRIER
FEEDTHROUGH (dBm)
–5
–10
–15
–20
–5
–10
–15
–20
CARRIER
SECOND-ORDER
HARMONIC (dBC)
FEEDTHROUGH (dBm)
SECOND-ORDER
HARMONIC (dBc)
0.1
1
10
0.1
1
10
BASEBAND INPUT VOLTAGE (V p-p Differential)
BASEBAND INPUT VOLTAGE (V p-p Differential)
Figure 15. SSB Output Power, Second- and Third-Order Harmonics, Carrier
Feedthrough, and Sideband Suppression vs. Baseband Differential Input
Voltage (fOUT = 2140 MHz)
Figure 12. SSB Output Power, Second- and Third-Order Harmonics, Carrier
Feedthrough, and Sideband Suppression vs. Baseband Differential Input
Voltage (fOUT = 940 MHz)
Rev. 0 | Page 12 of 44
Data Sheet
ADRF6720
0
–20
0
–10
–20
20
15
10
5
T
T
T
= –40°C
= +25°C
= +85°C
THIRD-ORDER
A
A
A
HARMONIC (dBC)
SSB OUTPUT
POWER (dBm)
–40
CARRIER
FEEDTHROUGH (dBm)
–60
–30
–40
–50
–60
–70
–80
–80
0
–100
–120
–140
–160
–180
–5
–10
–15
–20
SECOND-ORDER
HARMONIC (dBC)
SIDEBAND
SUPPRESSION (dBC)
1k
10k
100k
1M
10M
0.1
1
10
OFFSET FREQUENCY (Hz)
BASEBAND INPUT VOLTAGE (V p-p Differential)
Figure 16. SSB Output Power, Second- and Third-Order Harmonics, Carrier
Feedthrough, and Sideband Suppression vs. Baseband Differential Input
Voltage (fOUT = 2600 MHz)
Figure 19. Closed-Loop Phase Noise vs. Offset Frequency and Temperature,
LO = 940 MHz; 20 kHz Loop Filter
f
0
–20
0
T
T
T
= –40°C
= +25°C
= +85°C
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
A
A
A
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (Hz)
Figure 20. Closed-Loop Phase Noise vs. Offset Frequency and Temperature,
LO = 2140 MHz; 20 kHz Loop Filter
Figure 17. Closed-Loop Phase Noise vs. Offset Frequency and Temperature,
LO = 1900 MHz; 20 kHz Loop Filter
f
f
0
–20
0
–20
T
T
T
= –40°C
= +25°C
= +85°C
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
A
A
A
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (Hz)
Figure 21. Closed-Loop Phase Noise vs. Offset Frequency and Temperature,
LO = 2600 MHz; 20 kHz Loop Filter
Figure 18. Closed-Loop Phase Noise vs. Offset Frequency and Temperature,
LO = 2300 MHz; 20 kHz Loop Filter
f
f
Rev. 0 | Page 13 of 44
ADRF6720
Data Sheet
–80
–80
–90
T
T
T
= –40°C
= +25°C
= +85°C
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
A
A
A
OFFSET = 10kHz
OFFSET = 1kHz
–90
–100
–110
–120
–130
–140
–150
–160
–170
–100
–110
–120
–130
–140
–150
–160
–170
OFFSET = 100kHz
OFFSET = 1MHz
OFFSET = 10MHz
OFFSET = 5MHz
700
1200
1700
2200
2700
700
1200
1700
2200
2700
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 22. Closed-Loop Phase Noise vs. LO Frequency at 1 kHz, 100 kHz, and
5 MHz Offsets
Figure 25. Closed-Loop Phase Noise vs. LO Frequency at 10 kHz, 1 MHz, and
10 MHz Offsets
–70
–70
–75
1 × PFD FREQUENCY
3 × PFD FREQUENCY
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
–75
–80
–80
–85
–85
–90
–90
–95
–95
–100
–105
–110
–115
–120
–100
–105
–110
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
–115
1 × PFD FREQUENCY
3 × PFD FREQUENCY
–120
700
1200
1700
2200
2700
700
1200
1700
2200
2700
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 23. PLL Reference Spurs vs. LO Frequency (1 × PFD and 3 × PFD) at
Modulator Output
Figure 26. PLL Reference Spurs vs. LO Frequency (1 × PFD and 3 × PFD) at LO
Output
–70
–70
–75
2 × PFD FREQUENCY
4 × PFD FREQUENCY
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
–75
–80
–80
–85
–85
–90
–90
–95
–95
–100
–105
–110
–115
–120
–100
–105
–110
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
–115
–120
2 × PFD FREQUENCY
4 × PFD FREQUENCY
700
1200
1700
2200
2700
700
1200
1700
2200
2700
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 24. PLL Reference Spurs vs. LO Frequency (2 × PFD and 4 × PFD) at
Modulator Output
Figure 27. PLL Reference Spurs vs. LO Frequency (2 × PFD and 4 × PFD) at LO
Output
Rev. 0 | Page 14 of 44
Data Sheet
ADRF6720
1.0
2.8
2.6
2.4
2.2
2
T
T
T
= –40°C
= +25°C
= +85°C
T
T
T
= –40°C
A
A
A
A
A
A
= +25°C
= +85°C
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.8
1.6
1.4
1.2
1.0
0.8
700
1200
1700
2200
2700
2800
3300
3800
4300
4800
5300
5800
LO FREQUENCY (MHz)
VCO FREQUENCY (MHz)
Figure 28. Integrated Phase Noise with Spurs vs. LO Frequency and
Temperature
Figure 31. VTUNE vs. VCO Frequency and Temperature
–40
–60
–40
2860.8MHz
2579.83MHz
2300.22MHz
2300.78MHz
2156.06MHz
2009.22MHz
–60
–80
–80
–100
–120
–140
–160
–100
–120
–140
–160
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 32. Open-Loop VCO Phase Noise for VCO 1 Measured at 2009.22 MHz,
2156.06 MHz, and 2300.78 MHz (VCO ÷ 2)
Figure 29. Open-Loop VCO Phase Noise for VCO 0 Measured at 2300.22 MHz,
2579.83 MHz, and 2860.8 MHz (VCO ÷ 2)
–40
–40
1751.47MHz
1587.28MHz
1425.29MHz
–60
2010.75MHz
1882.97MHz
1750.48MHz
–60
–80
–100
–120
–140
–160
–80
–100
–120
–140
–160
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 33. Open-Loop VCO Phase Noise for VCO 3 Measured at 1425.29 MHz,
1587.28 MHz, and 1751.47 MHz (VCO ÷ 2)
Figure 30. Open-Loop VCO Phase Noise for VCO 2 Measured at 1750.48 MHz,
1882.97 MHz, and 2010.75 MHz (VCO ÷ 2)
Rev. 0 | Page 15 of 44
ADRF6720
Data Sheet
100
5
4
T
T
T
= –40°C
= +25°C
= +85°C
940MHz
A
A
A
1900MHz
90
2140MHz
2300MHz
2600MHz
3
80
70
60
50
40
30
20
10
0
2
1
LO_DRV_LVL = 1
LO_DRV_LVL = 2
0
–1
–2
–3
–4
–5
–6
–7
–8
LO_DRV_LVL = 0
–163 –162 –161 –160 –159 –158 –157 –156 –155 –154 –153
700
1200
1700
2200
2700
NOISE FLOOR (dBm/Hz)
LO FREQUENCY (MHz)
Figure 34. Noise Floor Cumulative Distribution at Various LO Frequencies
Using Internal LO; I/Q Input with 500 mV DC Bias and No RF Output
Figure 37. LO Output Power vs. LO Frequency at Various LO_DRV_LVL
Settings
100
520
T
T
T
= –40°C
= +25°C
= +85°C
940MHz
A
A
A
1900MHz
90
500
480
460
440
420
400
380
360
340
320
2140MHz
2300MHz
2600MHz
80
70
60
50
40
30
20
10
0
–163 –162 –161 –160 –159 –158 –157 –156 –155 –154 –153
700
1200
1700
2200
2700
NOISE FLOOR (dBm/Hz)
LO FREQUENCY (MHz)
Figure 35. Noise Floor Cumulative Distribution at Various LO Frequencies
Using Internal LO; I/Q Input with 500 mV DC Bias and RF Output = −10 dBm
Figure 38. Supply Current vs. LO Frequency and Temperature (PLL and
I/Q Modulator Enabled, LO Buffer Disabled)
20
0
15
–5
10
–10
5
BAL_CIN = 0, BAL_COUT = 0
BAL_CIN = 1, BAL_COUT = 0
0
–15
–20
–25
–30
BAL_CIN = 2, BAL_COUT = 0
BAL_CIN = 3, BAL_COUT = 0
BAL_CIN = 4, BAL_COUT = 0
BAL_CIN = 8, BAL_COUT = 0
BAL_CIN = 9, BAL_COUT = 0
BAL_CIN = 10, BAL_COUT = 0
BAL_CIN = 11, BAL_COUT = 0
BAL_CIN = 12, BAL_COUT = 0
BAL_CIN = 13, BAL_COUT = 0
BAL_CIN = 14, BAL_COUT = 0
BAL_CIN = 15, BAL_COUT = 0
BAL_CIN = 15, BAL_COUT = 3
–5
–10
–15
–20
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.7
1.2
1.7
2.2
2.7
LO FREQUENCY (GHz)
TIME (ms)
Figure 36. Frequency Deviation from LO Frequency at LO = 1.91 GHz to
1.9 GHz vs. Lock Time
Figure 39. RF Output Return Loss vs. LO Frequency (fLO) for Multiple BAL_CIN
and BAL_COUT Combinations
Rev. 0 | Page 16 of 44
Data Sheet
ADRF6720
0
–5
0
–2
–4
–10
–15
–20
–25
–30
–35
–6
–8
–10
–12
–14
–16
–18
–20
0.3
1.3
2.3
3.3
4.3
5.3
6.3
0.3
1.3
2.3
3.3
4.3
5.3
6.3
LO FREQUENCY (GHz)
LO FREQUENCY (GHz)
Figure 40. LO Input Return Loss vs. LO Frequency (fLO
)
Figure 41. LO Output Return Loss vs. LO Frequency (fLO)
Rev. 0 | Page 17 of 44
ADRF6720
Data Sheet
THEORY OF OPERATION
The ADRF6720 integrates a high performance broadband I/Q
modulator with a fractional-N PLL and low noise multicore
VCOs. The baseband inputs mix with the LO generated
internally or provided externally, and convert it to a single-
ended RF using an integrated RF balun. A block diagram of the
device is shown in Figure 1. The ADRF6720 is programmed via
an SPI.
Internal LO Mode
For internal LO mode, the ADRF6720 uses the on-chip PLL and
VCO to synthesize the frequency of the LO signal. The PLL,
shown in Figure 42, consists of a reference path, phase and
frequency detector (PFD), charge pump, and a programmable
integer divider with prescaler. The reference path takes in a
reference clock and divides it down by a factor of 2, 4, or 8, or
multiplies it by a factor of 1 or 2, and then passes it to the PFD.
The PFD compares this signal to the divided down signal from
the VCO. Depending on the PFD polarity selected, the PFD
sends either an up or down signal to the charge pump if the
VCO signal is either slow or fast compared to the reference
frequency. The charge pump sends a current pulse to the off-
chip loop filter to increase or decrease the tuning voltage
(VTUNE).
LO GENERATION BLOCK
The ADRF6720 supports the use of both internal and external
LO signals for the mixers. The internal LO is generated by an
on-chip VCO, which is tunable over an octave frequency range
of 2850 MHz to 5710 MHz. The output of the VCO is phase-
locked to an external reference clock through a fractional-N
PLL that is programmable through the SPI control registers. To
produce in-phase and quadrature phase LO signals over the
356.25 MHz to 2855 MHz frequency range to drive the mixers,
steer the VCO outputs through a combination of frequency
dividers, as shown in Figure 42.
The ADRF6720 integrates four VCO cores, covering an octave
range of 2850 MHz to 5710 MHz.
Table 6 lists the frequency range covered by each VCO. The
desired VCO can be selected by addressing the VCO_SEL bits at
Register 0x22[2:0].
Alternatively, an external signal can be used with the dividers or
a polyphase phase splitter to generate the LO signals in
quadrature to the mixers. In demanding applications that
require the lowest possible phase noise performance, it may be
necessary to source the LO signal externally. The different
methods of quadrature LO generation and the control register
programming needed are listed in Table 6.
The LO source and quadrature generation path can be selected
by setting the QUAD_DIV_EN bit (Register 0x01[9]) and the
LO_1XVCO_EN bit (Register 0x01[11]). The mode of the VCO
signal through a polyphase filter is intended to extend the
operating frequency with an internal VCO and is only useful for
baseband input frequencies high enough to prevent the RF
output from pulling the VCO.
POLYPHASE
FILTER
34
33
LOIN+
LOIN–
I+
I–
REF_SEL
REG 0x21[2:0]
QUAD_DIV_EN
REG 0x01[9]
TO MIXER
LO_1XVCO_EN
REG 0x01[11]
Q+
Q–
EXTERNAL
LOOP
PFD_POLARITY
÷8
÷4
÷2
×1
×2
FILTER
REG 0x21[3]
QUAD
DIVIDER
÷1, ÷2,
÷4
CP
36
VTUNE
32
PFD
CHARGE
PUMP
39
REFIN
+
LPF
CP_CTL
REG 0x20[14:0]
DIV8 _EN/
DIV4_EN
REG 0x22[4:3]
÷1,÷2
FRAC
MOD
÷2
N = INT +
DRVDIV2_EN
REG 0x22[5]
LOOUT+
LOOUT–
MUXOUT
1
VCO_SEL
REG 0x22[2:0]
DIV_MODE: REG 0x02[11]
INT_DIV: REG 0x02[10:0]
FRAC_DIV: REG 0x03[15:0]
MOD_DIV: REG 0x04[15:0]
LOCK_DET
VPTAT
LO_DRV2X_EN
REG 0x01[8]
LO_DRV1X_EN REG 0x01[7]
REF_MUX_SEL
REG 0x21[6:4]
Figure 42. LO Block Diagram
Rev. 0 | Page 18 of 44
Data Sheet
ADRF6720
Table 6. LO Mode Selection
QUAD_DIV_EN
(Register
0x01[9])
LO_1XVCO_EN
(Register
0x1 [11])
Enables
(Register
0x01[6:0])
VCO_SEL
(Register
0x22[2:0])
Quadrature
fVCO or fEXT (MHz) Generation
LO Selection
Internal (VCO)
2850 to 3500
3500 to 4020
4020 to 4600
4600 to 5710
2855 to 3000
700 to 6000
700 to 3000
Divide by 2
Divide by 2
Divide by 2
Divide by 2
Polyphase
Divide by 2
Polyphase
1
1
1
1
0
1
0
0
0
0
0
0
0
0
111 111X1
111 111X1
111 111X1
111 111X1
111 111X1
101 000X1
000 000X1
011
010
001
000
011
1XX1
XXX1
External
1 X = don’t care.
LO Frequency and Dividers
locked.
LO_DIVIDER is the final frequency divider ratio that divides
the frequency of the VCO or the external LO signal down by 2,
4, or 8 before it reaches the mixer, as shown in Table 7.
The signal coming from the VCO or the external LO inputs
goes through a series of dividers before it is buffered to drive
the active mixers. Two programmable divide-by-2 stages divide
the frequency of the incoming signal by 1, 2, or 4 before
reaching the quadrature divider that further divides the signal
frequency by 2 to generate the in-phase and quadrature phase
LO signals for the mixers. The control bits (Register 0x22[4:3])
needed to select the different LO frequency ranges are listed in
Table 7.
Loop Filter
The loop filter is connected between the CP and VTUNE pins.
The recommended components for 20 kHz filter designs are
shown in Table 8 and referenced in Figure 44.
The ADRF6720 closed-loop phase noise is characterized using a
20 kHz loop filter. Operation with an external VCO is possible.
In this case, the output of the loop filter is connected to the
tuning pin of the external VCO. The output of the VCO is
brought back into the device on the LOIN+ and LOIN− pins.
For assistance in designing loop filters with other characteristics,
download the most recent revision of ADIsimPLL™ from
http://www.analog.com/adisimpll.
Table 7. LO Frequency and Dividers
DIV8_EN
DIV4_EN
(Register
0x22[3])
LO Frequency fVCO/fLO or (Register
Range (MHz)
1425 to 2855
712.5 to 1425
356.25 to 712.5
fEXT LO/fLO
0x22[4])
2
4
8
0
0
1
0
1
1
Table 8. Recommended Loop Filter Components
PLL Frequency Programming
Component
20 kHz Loop Filter
2700 pF
300 Ω
The N divider with divide-by-2 divides down the VCO signal to
the PFD frequency. The N divider can be configured for
fractional or integer mode by addressing the DIV_MODE bit
(Register 0x02[11]). The default configuration is set for
fractional mode. Use the following equations to determine the
N value and PLL frequency:
C57
R12
C58
100 nF
R23
5.6 Ω
C59
R26
2700 pF
820 Ω
fVCO
2×N
C60
1500 pF
fPFD
=
PLL Lock Time
FRAC
MOD
fvco
It takes time to lock the PLL after the last register is written.
VCO band calibration time and loop settling time are used to
determine the PLL lock time.
N = INT +
fLO
where:
f
PFD ×2× N
=
=
LO _ DIVIDER LO_DIVIDER
After writing to the last register, the PLL automatically performs
a VCO band calibration to choose the correct VCO band. This
calibration takes approximately 94,208 PFD cycles. For a
40 MHz fPFD, this corresponds to 2.36 ms. After a band
calibration completes, the feedback action of the PLL results in
the VCO locking to the correct frequency. The speed to be
locked depends on the nonlinear cycle slipping behavior, as well
as the small signal settling of the loop. For an accurate
f
f
PFD is the phase frequency detector frequency.
VCO is the VCO frequency.
N is the fractional divide ratio (INT + FRAC/MOD).
INT is the integer divide ratio programmed in Register 0x02.
FRAC is the fractional divider programmed in Register 0x03.
MOD is the modulus divide ratio programmed in Register 0x04.
estimation of the lock time, download the ADIsimPLL tool to
f
LO is the LO frequency going to the mixer core when the loop is
Rev. 0 | Page 19 of 44
ADRF6720
Data Sheet
capture these effects correctly. In general, higher bandwidth
loops tend to lock more quickly than lower bandwidth loops.
(fRF < fLO) when Q leads I and places the RF frequency above the
LO (fRF > fLO) when I leads Q.
The lock detect signal is available as one of the selectable
outputs through the MUXOUT pin, with a logic high signifying
that the loop is locked. The control bits for the MUXOUT pin
are the REF_MUX_SEL bits (Register 0x21[6:4]), and the
default configuration is for PLL lock detect.
Table 10. LO Polarity Setting
Bit
Address
Name
Settings Description
Quadrature polarity
0x32[11:10]
POL_Q
switch, Q channel
01
10
Inverted Q channel
polarity
Normal polarity
Required PLL/VCO Settings and Register Write Sequence
In addition to writing to the necessary registers to configure the
PLL and VCO for the desired LO frequency and phase noise
performance, the registers listed in Table 9 are the required
registers to write.
0x32[9:8]
POL_I
Quadrature polarity
switch, I channel.
Normal polarity
Inverted I channel
polarity
01
10
To ensure that the PLL locks to the desired frequency, follow the
proper write sequence of the PLL registers. Configure the PLL
registers accordingly to achieve the desired frequency, and the
last writes must be to Register 0x02 (INT_DIV), Register 0x03
(FRAC_DIV), or Register 0x04 (MOD_DIV). When Register 0x02,
Register 0x03, and Register 0x04 are programmed, an internal
VCO calibration initiates, which is the last step to locking the
PLL.
LO Outputs
The ADRF6720 can provide either a differential 1 × or 2 × LO
output signal at the LOOUT+ and LOOUT− pins (Pin 18 and
Pin 19, respectively). The availability of the LO signal makes it
possible to daisy-chain many devices. One ADRF6720 device
can serve as the master where the LO signal is sourced, and the
subsequent slave devices can share the same LO output signal
from the master.
Table 9. Required PLL/VCO Register Writes
Address
Bit Name
Setting Description
When the quadrature LO signals are generated using the
quadrature divider, the output signal is available at either 2× or
1× the frequency of the LO signal at the mixer by setting
LO_DRV2X_EN bit(Register 0x1[8]) and DRVDIV2_EN bit
(Register 0x22[5]). However, 1× the frequency of the LO signal
in this case has a phase ambiguity of 180° relative to the LO
signal that drives the mixer core. Because of this phase
ambiguity, the utility of this 1 × LO output signal as a system
daisy-chained LO signal is compromised. To avoid this
ambiguity, a second 1× the frequency of the LO signal output is
made available after the quadrature divider. This second 1 × LO
output path is enabled by setting the LO_DRV1X_EN bit
(Register 0x01[7]) high.
0x21[3]
0x49[13:0]
PFD_POLARITY 0x01
Negative polarity
Internal settings
SET_1[13:9],
SET_0[8:0]
0x14B4
External LO Mode
Use the VCO_SEL bits (Register 0x22[2:0]) to select external or
internal LO mode. To configure for external LO mode, set
Register 0x22[2:0] to 4 decimal and apply the differential LO
signals to Pin 33 (LOIN−) and Pin 34 (LOIN+). The external
LO frequency range is 700 MHz to 3 GHz. When the polyphase
phase splitter is selected, a 1 × LO signal is required for the
active mixer, or a 2 × LO can be used with the internal
quadrature divider, as shown in Table 6.
There is also the option of using an external VCO with the
internal PLL. In this case, the PLL is enabled, but the VCO
blocks are turned off.
When the quadrature LO signals are generated using the
polyphase phase splitter, the output signal is also available at 1×
the frequency of the LO signal by setting LO_DRV1X_EN bit
(Register 0x10[7]) high.
The LOIN+ and LOIN− input pins must be ac-coupled. When
not in use, leave the LOIN+ and LOIN− pins unconnected.
Set the output to different drive levels by accessing the
LO_DRV_LVL bits (Register 0x22[7:6]), as shown in Table 11.
LO Polarity
The ADRF6720 offers the flexibility of specifying the
quadrature polarity on LO to the I channel or Q channel
mixers. This specification determines whether the LO is
injected above or below the RF frequency. RF frequency can
place either above or below the LO depending on the
Register 0x32[11:8] setting as well as the phase relationship
between the baseband I and Q. For normal operation and
characterization, the Register 0x32 settings are 2 decimal for POL_I
(Register 0x32[9:8]) and 1 decimal for POL_Q (Register 0x32,
Bits[11:10]). Setting Register 0x32 as such places the RF
frequency below the LO
Table 11. LO Output Level at 2140 MHz
LO_DRV_LVL (Register 0x22[7:6])
Amplitude (dBm)
00
01
10
−5.1
−0.5
3
Rev. 0 | Page 20 of 44
Data Sheet
ADRF6720
Table 12. Optimum Balun Setting For Desired Frequency Range
BASEBAND
BAL_CIN
BAL_COUT
Frequency Range (MHz)
The input impedance of the baseband inputs is a 500 Ω
differential. These inputs are designed to work with a 0.5 V
common-mode voltage. To match the 100 Ω impedance of the
DAC, place a shunt 125 Ω external resistor across the I and Q
inputs.
0
1
2
3
4
8
9
10
11
12
13
14
15
15
0
0
0
0
0
0
0
0
0
0
0
0
0
3
fRF > 1730
1550 < fRF < 1730
1380 < fRF < 1550
1250 < fRF < 1380
1170 < fRF < 1250
1100 < fRF < 1170
1020 < fRF < 1100
970 < fRF < 1020
930 < fRF < 970
890 < fRF < 930
840 < fRF < 890
820 < fRF < 840
740 < fRF < 820
The voltages applied to the differential baseband inputs (I+, I−,
Q+, and Q−) drive the V-to-I stage that converts baseband
voltages into currents. The converted modulated signal current
feeds the modulator mixer core.
A programmable dc current can be added to both the I and Q
channels to null any carrier feedthrough at the RF output. Refer
to the Carrier Feedthrough Nulling section for more
information
680 < fRF < 740
The linearity can be optimized by adding the amplitude and
phase correction signals to the current output via the MOD_RSEL
(Register 0x31[12:6]) and MOD_CSEL (Register 0x31[5:0])
adjustment. Refer to the Linearity section for more information.
ENBL
The ENBL pin quickly enables/disables the RF output. The
circuit blocks that are enabled/disabled with the ENBL pin can
be programmed by setting the appropriate bits in the enables
register (Register 0x01) and the ENBL_MASK register
(Register 0x10). When the bits in the enables and the
ENBL_MASK register are 1, pulling the ENBL pin low disables
and pulling high enables the internal blocks more quickly than
possible with an SPI write operation.
ACTIVE MIXERS
The ADRF6720 has two double balanced mixers: one for the
in-phase channel (I channel) and the other for the quadrature
channel (Q channel). They upconvert the modulated baseband
signal currents by the LO signals to the RF.
Tunable RFOUT Balun
Table 13. Enable/Disable Settings
The ADRF6720 integrates a programmable balun operating
over a frequency range from 700 MHz to 3000 MHz. It offers
single-ended-to-differential conversion and provides additional
common-mode noise rejection.
Register
0x01
Register 0x10
ENBL_MASK
Bit1
Enables
ENBL Pin
Voltage
X2
Bit1
State
X2
Block controlled
by Register 0x01,
enables bit [A]
disabled. No effect
by ENBL.
Block controlled
by Register 0x01,
enables bit [A]
disabled. No effect
by ENBL.
Block controlled
by Register 0x01,
enables bit [A]
enabled.
Block controlled
by Register 0x01,
enables bit [A]
disabled
The capacitors at the input and output of the balun in parallel
with the inductive windings of the balun change the resonant
frequency of the inductor capacitor (LC) tank. Therefore,
selecting the proper combination of BAL_CIN (Register 0x30[3:0])
and BAL_COUT (Register 0x30[7:4]) sets the desired frequency
and optimizes gain. Under most circumstances, it is suggested to
set BAL_CIN and BAL_COUT over the frequency profile given
in Table 12. However, for matching reasons, it is advantageous to
tune the registers independently.
0
1
0
X2
1
1
1
1
>1.8 V
<0.5 V
RFOUT
BAL_COUT
BAL_CIN
REG 0x30[3:0]
REG 0x30[7:4]
Figure 43. Integrated Tunable Balun
1 This bit refers to any of the 11 bits in the register.
2 X = don’t care.
Rev. 0 | Page 21 of 44
ADRF6720
Data Sheet
On a write cycle, up to 16 bits of serial write data are shifted in,
SERIAL PORT INTERFACE
CS
MSB to LSB. If the rising edge of
occurs before the LSB of
The SPI of the ADRF6720 allows the user to configure the
device for specific functions or operations via a 3-pin SPI port.
This interface provides users with added flexibility and
customization. The SPI consists of three control lines: SCLK,
the serial data is latched, only the bits that were latched are
written to the device. If more than 16 data bits are shifted in, the
16 most recent bits are written to the device. The ADRF6720
input logic level for the write cycle supports an interface as low
as 1.4 V.
CS
SDIO, and . The timing requirements for the SPI port are
shown in Table 2.
On a read cycle, up to 16 bits of serial read data are shifted out,
MSB first. Data shifted out beyond 16 bits is undefined.
Readback content at a given register address does not
necessarily correspond with the write data of the same address.
The output logic level for a read cycle is 2.3 V.
The ADRF6720 protocol consists of seven register address bits,
followed by a read/write and 16 data bits. Both the address and
data fields are organized with the most significant bit (MSB)
first, and end with the least significant bit (LSB).
Rev. 0 | Page 22 of 44
Data Sheet
ADRF6720
BASIC CONNECTIONS FOR OPERATION
Figure 44 shows the basic connections for operating the ADRF6720 as they are implemented on the evaluation board of the device.
+3.3V
RED
10µF
(0805)
0.1µF
(0402)
0.1µF
(0402)
0.1µF
(0402)
0.1µF
(0402)
0.1µF
(0402)
0.1µF
(0402)
0.1µF
(0402)
0.1µF
(0402)
100pF
(0402)
100pF
(0402)
100pF
(0402)
100pF
(0402)
100pF
(0402)
100pF
(0402)
100pF
(0402)
100pF
(0402)
3.3V
10kΩ
VPOS8
VPOS6
VPOS5
VPOS4
VPOS3
VPOS2
VPOS1
VPOS7
40
35
30
26
22
17
11
6
(0402)
I+
ENBL
3
4
I+
I–
27
24
S1
ADRF6720
125Ω
(0402)
V TO I
49.9Ω
I–
PHASE
CORRECTION
(0402)
LO NULLING
DAC
RFOUT
LO NULLING
DAC
PHASE
CORRECTION
Q–
Q+
8
9
Q–
Q+
125Ω
(0402)
V TO I
LOOUT+
LOOUT–
LOOUT
18
19
3
1
4
100pF
(0402)
LOCK_DET
VPTAT
6
100pF
(0402)
MUXOUT
÷2
1
0Ω
(0402)
CS
CS
15
14
13
SCLK
POLYPHASE
FILTER
0°
SERIAL PORT
INTERFACE
SCLK
90°
SDIO
SDIO
DECL3
÷1, ÷2,
÷4
REFIN
31
28
12
÷8
÷4
÷2
×1
×2
LDO
2.5V
100pF
(0402)
100pF
(0402)
0.1µF
(0402)
10µF
(0603)
REF_IN
REFIN
NIC
PFD
FRAC
MOD
÷2
N = INT +
39
21
DECL2
DECL1
49.9Ω
(0402)
LDO
VCO
100pF
(0402)
0.1µF
(0402)
10µF
(0603)
CHARGE
PUMP
2
5
7
10 16 20 23 25 29 37 38
36
32
33 34
100pF
(0402)
0.1µF
(0402)
10µF
(0603)
VTUNE
EXT LO
CP
3
4
6
R23
5.6Ω
(0402)
R26
820Ω
(0402)
100pF
(0402)
GND
1
R12
100pF
(0402)
300Ω
C57
2700pF
(0402)
C59
2700pF
(0402)
C60
1500pF
(0402)
(0402)
C58
100nF
(0603)
NOTES
1. NIC = NO INTERNAL CONNECTION.
Figure 44. Basic Connections for Operation (Loop Filter Set to 20 kHz)
ground plane spans multiple layers on the circuit board, stitch
them together under the exposed pad. The AN-772 Application
Note discusses the thermal and electrical grounding of the
LFCSP package in detail.
POWER SUPPLY AND GROUNDING
Connect the power supply pins to a 3.3 V source; the pins can
range between 3.15 V and 3.45 V. Individually decouple the pins
using 100 pF and 0.1 µF capacitors located as close as possible
to the pins. Individually decouple the three internal decoupling
nodes (labeled DECL3, DECL2, and DECL1) with capacitors as
shown in Figure 44.
Tie the 11 GND pins to the same ground plane through low
impedance paths.
Solder the exposed pad on the underside of the package to a
ground plane with low thermal and electrical impedance. If the
Rev. 0 | Page 23 of 44
ADRF6720
Data Sheet
BASEBAND INPUTS
LO INPUT
Drive the four I and Q inputs with an external bias level of 500 mV.
These inputs are generally dc-coupled to the outputs of a dual
DAC. The nominal drive level used in the characterization of
the ADRF6720 is 1 V p-p differential (or 500 mV p-p on each
pin).
The external LO input is designed to be driven differentially.
AC couple both sides of the differential LO source through a
pair of series capacitors to the LOIN+ and LOIN− pins.
The typical LO drive level, used for the characterization of the
ADRF6720, is 0 dBm.
The I and Q input resistances are 500 Ω, differential. As a result,
the external shunt resistors at the I and Q inputs may be
required to interface a DAC or a filter. The effective value of the
resistance is 500 Ω in parallel with the shunt resistor (see the
DAC to I/Q Modulator Interfacing section for more
information).
Apply the reference frequency for the PLL (between 5.7 MHz
and 320 MHz) to the REFIN pin, which is ac-coupled. If the
REFIN pin is being driven from a 50 Ω source, terminate the
pin with 50 Ω as shown in Figure 44. Apply a drive level of
about 4 dBm to 14 dBm; 4 dBm is used at characterization.
LOOP FILTER
The loop filter in Figure 44 is connected between the CP and
VTUNE pins. The recommended components for 20 kHz filter
designs are shown in Table 8.
RF OUTPUT
The RF output is available at the RFOUT pin (Pin 24), which can
drive a 50 Ω load.
Rev. 0 | Page 24 of 44
Data Sheet
ADRF6720
APPLICATIONS INFORMATION
resulting in a value for RLI and RLQ of 125 Ω.
DAC TO I/Q MODULATOR INTERFACING
Figure 47 shows the differential input resistance and
capacitance over baseband input frequencies.
The ADRF6720 is designed to interface with minimal
components to members of the Analog Devices, Inc., family of
TxDAC® converters. These dual-channel differential current
output DACs provide an output current swing from 0 mA to
20 mA. The interface described in this section can be used with
any DAC that has a similar output.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
An example of an interface using the AD9142A TxDAC is shown
in Figure 45. The baseband inputs of the ADRF6720 require a dc
bias of 500 m V. The nominal midscale output current on each of
the outputs of the AD9142A is 10 mA. Therefore, an average
current of 10 mA flowing through a single 50 Ω resistor to
ground from each of the DAC outputs produces the desired
500 mV dc bias for the inputs to the ADRF6720. Place a shunt
125 Ω external resistor across the I and Q inputs to match the
100 Ω impedance of the DAC. The external resistor reduces the
voltage swing for a given DAC output current. The AD9142A
output currents have a swing ranging from 0 mA to 20 mA.
With the 50 Ω termination resistors to ground in the DAC
outputs and the 125 Ω shunt resistors in place, the resulting
drive signal from each differential pair is 1 V p-p differential
(with the DAC running at 0 dBFS) with a 500 mV dc bias.
10
100
1k
10k
EFFECTIVE AC SWING LIMITING RESISTANCE (Ω)
Figure 46. Relationship Between the Effective AC Swing Limiting Resistance
and the Peak-to-Peak Voltage Swing with 50 Ω Bias Setting Resistors
500
450
400
350
300
250
200
150
100
50
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
RESISTANCE
AD9142A
IOUT1P
ADRF6720
I+
67
3
R
50Ω
BI+
R
125Ω
LI
500Ω
R
BI–
CAPACITANCE
66
57
4
8
I–
50Ω
IOUT1N
IOUT2N
Q–
R
BQ+
50Ω
R
125Ω
LQ
500Ω
0
0
100 200 300 400 500 600 700 800 900 1000
R
BQ–
56
Q+
50Ω
9
FREQUENCY (MHz)
IOUT2P
Figure 47. Differential Baseband Input Resistance and Input Capacitance
Equivalents (Shunt R, Shunt C)
Figure 45. Interface Between the AD9142A and ADRF6720 with 50 Ω
Resistors to Ground to Establish the 500 mV DC Bias for the ADRF6720
Baseband Inputs
I/Q Filtering
An antialiasing filter between the DAC and modulator is
necessary to filter out Nyquist images, common-mode noise,
and broadband DAC noise. The interface for setting up the
biasing and ac swing described in the DAC to I/Q Modulator
Interfacing section lends itself well to the introduction of such a
filter. The filter can be inserted between the dc bias setting
resistors and the ac swing limiting resistor. With this
configuration, the dc bias setting resistors set the source
impedance, and the ac swing limiting resistor sets the load
impedance with a 500 Ω differential I and Q input impedance
in parallel for the filter.
Adjust the voltage swing for a given DAC output current by
placing a different resistance value on RLI and RLQ to the interface
(see Figure 45). This adjustment has the effect of varying the ac
swing without changing the dc bias already established by the
50 Ω resistors. A higher resistance value increases the output
power of the ADRF6720 and signal-to-noise ratio (SNR) at the
cost of higher intermodulation distortion.
When setting the size of resistor to adjust swing level, take the input
impedance of the I and Q inputs into account. The I and Q inputs
have a differential input resistance of 500 Ω. As a result, the
effective value of the resistance is 500 Ω in parallel with the
chosen shunt resistor. For example, if a 100 Ω resistance is desired
(based on Figure 45), the value of RLI or RLQ must be set such that
BASEBAND BANDWIDTH
The ADRF6720 can be used with a DAC generating a complex
IF (CIF), as well as a zero IF signal (ZIF). The 1 dB bandwidth
of the ADRF6720 is more than 1000 MHz. Figure 48 shows the
100 Ω = (500 × RLI)/(500 + RLI)
100 Ω = (500 × RLQ)/(500 + RLQ
)
Rev. 0 | Page 25 of 44
ADRF6720
Data Sheet
baseband frequency response of ADRF6720, facilitating high
CIF and providing sufficient flat bandwidth for digital
predistortion (DPD) algorithms. Any flatness variations across
frequency at the ADRF6720 RF output have been calibrated out
of this measurement.
SIDEBAND SUPPRESSION OPTIMIZATION
Sideband suppression results from gain and phase imperfection
between the I and Q channels. Sideband suppression also results
from the quadrature error in generating quadrature LO signals.
The net unwanted sideband signal at the RF output is the vector
combination of the signals as a result of these effects.
1
0
–1
–2
–3
–4
–5
–6
The ADRF6720 offers quadrature phase adjustment through the
I_LO (Register 0x32[3:0]) and Q_LO (Register 0x32[7:4])
parameters to reject unwanted sideband signal.
Figure 50 shows the level of unwanted sideband signal
achievable from the ADRF6720 across the I_LO and Q_LO
parameters
If further optimization is required, the amplitude and phase
adjustments can be made externally by a TxDAC. The result of
this type of adjustment is shown in Figure 51.
0
200
400
600
800
1000
–30
–35
BB FREQUENCY (MHz)
Figure 48. ADRF6720 Baseband Frequency Response
–30
–35
–40
–45
–50
–55
–60
–65
–70
–40
–45
–50
–55
–60
–65
CARRIER FEEDTHROUGH NULLING
Carrier feedthrough results from minute dc offsets that occur
on the differential baseband inputs. In an I/Q modulator,
nonzero differential offsets mix with the LO and result in
carrier feedthrough to the RF output. In addition to this effect,
some of the signal power at the LO input couples directly to the
RF output (this may be as a result of bond wire to bond wire
coupling or coupling through the silicon substrate). The net
carrier feedthrough at the RF output is the vector combination
of the signals that appear at the output as a result of these two
effects.
–70
15
10
5
15
0
10
5
0
Figure 50. Sideband Suppression Optimization Through I_LO and Q_LO
Adjustment ; LO = 2140 MHz
0
The ADRF6720 has a feature to add dc current, positive or
negative, to both the I and Q channels for carrier feedthrough
nulling. Figure 49 shows carrier feedthrough vs. DCOFF_I
(Register 0x33[15:8]) and DCOFF_Q (Register 0x33[7:0]).
BEFORE NULLING
AFTER NULLING BY I_LO, Q_LO INADRF6720
–10
AFTER NULLING EXTERNALLY
–20
–30
–40
–50
–60
–70
–80
–90
The carrier feedthrough nulling can also be accomplished
externally by a TxDAC.
–20
–20
–30
–40
–50
–60
–70
–30
–40
–50
–60
700
1200
1700
2200
2700
LO FREQUENCY (MHz)
Figure 51. Sideband Suppression Before and After Nulling Using I_LO and
Q_LO Through External Adjustment; LO = 2140 MHz
–70
300
300
200
250
200
100
150
100
50
0
0
Figure 49. Carrier Feedthrough Optimization Through DCOFF_I and
DCOFF_Q Adjustment
Rev. 0 | Page 26 of 44
Data Sheet
ADRF6720
LINEARITY
LO AMPLITUDE AND COMMON-MODE VOLTAGE
The linearity in ADRF6720 can be optimized through the
MOD_RSEL (Register 0x31[12:6]) and MOD_CSEL
(Register 0x31[5:0]) settings. The resistance and capacitance
curves as a function of the MOD_RSEL and MOD_CSEL
settings. These settings control the amount of antiphase
distortion to the baseband input stages to correct for distortion.
The typical External LO driving level of the ADRF6720 is
0 dBm differential. All the baseband inputs must be externally
dc biased to 500 mV. Figure 54 and Figure 55 show the
performance variation vs. the external LO amplitude and
baseband common-mode voltage, respectively.
10
70
60
50
40
30
20
10
0
SSB OUTPUT POWER(dBm)
The top two bits (Register 0x31[12:11]) of MOD_RSEL and the
MSB (Register 0x31[5]) of MOD_CSEL are used as a range
setting. Figure 52 and Figure 53 show the output IP3 and
output IP2 that are achievable across the MOD_RSEL and
MOD_CSEL settings.
0
OUTPUT IP2 (dBm)
–10
–20
–30
–40
–50
–60
–70
OUTPUT IP3 (dBm)
Figure 52 and Figure 53 show both a surface and a contour plot in
one figure. The contour plot is located directly underneath the
surface plot. The peaks on the surface plot indicate the maximum
output IP3 and maximum output IP2, and the same color pattern
on the contour plot determines the optimized MOD_RSEL and
MOD_CSEL values. The overall shape of the output IP3 plot varies
with the MOD_RSEL setting more than the MOD_CSEL setting.
CARRIER FEEDTHROUGH (dBm)
SIDEBAND SUPPRESSION (dBc)
THIRD HARMONIC (dBc)
10
SECOND HARMONIC (dBc)
–
10
10
–
–
5
0
5
EXTERNAL LO AMPLITUDE (dBm)
36
Figure 54. SSB Output Power, Second- and Third-Order Harmonics, Carrier
Feedthrough, Sideband Suppression, OIP2, and OIP3 vs. External LO
Amplitude; Baseband I/Q Amplitude = 1 V p-p Differential, fOUT = 2140 MHz
34
36
34
32
30
28
26
32
30
28
10
0
70
60
50
40
30
20
10
0
SSB OUTPUT POWER(dBm)
OUTPUT IP2 (dBm)
–10
–20
–30
–40
–50
–60
–70
26
30
20
OUTPUT IP3 (dBm)
SIDEBAND SUPPRESSION (dBc)
10
30
0
25
20
15
D_RS
10
5
0
EL
MO
CARRIER FEEDTHROUGH (dBm)
THIRD HARMONIC (dBc)
Figure 52. OIP3 vs. MOD_CSEL and MOD_RSEL at fRF = 2140 MHz, I/Q
Amplitude Per Tone = 0.5 V p-p Differential
SECOND HARMONIC (dBc)
–10
0.2
0.3
0.4
0.5
0.6
0.7
0.8
60
59
58
57
56
BASEBAND COMMON-MODE VOLTAGE (V)
60
59
58
57
56
Figure 55. SSB Output Power, Second- and Third-Order Harmonics, Carrier
Feedthrough, Sideband Suppression, OIP2, and OIP3 vs. Baseband Common-
Mode Voltage; Baseband I/Q Amplitude = 1 V p-p Differential, fOUT = 2140 MHz
LAYOUT
Solder the exposed pad on the underside of the ADRF6720 to a
low thermal and electrical impedance ground plane. This pad is
typically soldered to an exposed opening in the solder mask on
the evaluation board. Notice the use of 25 via holes on the
exposed pad of the ADRF6720 evaluation board. Connect these
ground vias to all other ground layers on the evaluation board
to maximize heat dissipation from the device package.
55
55
30
30
20
25
20
15
10
10
5
0
0
Figure 53. OIP2 vs. MOD_CSEL and MOD_RSEL at fRF = 2140 MHz, I/Q
Amplitude per Tone = 0.5 V p-p Differential
Rev. 0 | Page 27 of 44
ADRF6720
Data Sheet
Figure 56. Evaluation Board Layout for the ADRF6720 Package
Rev. 0 | Page 28 of 44
Data Sheet
ADRF6720
CHARACTERIZATION SETUPS
The primary setup used to characterize the ADRF6720 is shown
in Figure 57. This setup was used to evaluate the product as a
single-sideband modulator. An automated software program
(VEE) was used to control equipment over the IEEE bus. The
setup was used to measure SSB, OIP2, OIP3, output P1 dB
(OP1dB), LO, and USB null.
For phase noise and reference spur measurements, see the phase
noise setup shown in Figure 58. Phase noise was measured on
an LO and modulator output.
ADRF6720 TEST RACK ASSEMBLY (INTERNAL VCO CONFIGURATION)
ALL INSTRUMENTS ARE CONNECTED IN DAISY-CHAIN
FASHION VIA GBIP CABLE UNLESS OTHERWISE NOTED.
E3631A POWER SUPPLY
(+6V ADJUSTED TO 5V)
+3.3V FOR
VPOS TO 34950
MODULE
34401A DMM (FOR SUPPLY
CURRENT MEASUREMENT)
PROGRAMMING
AND DC CABLE
(×4 FOR MULTISITE)
34980A
WITH 34950 AND (×3) 34921 MODULES
INPUT
(RFOUT)
AGILENT MXA N9020A SPECTRUM ANALYZER
12-PIN
CONNECTOR
(REGISTER
PROGRAMMING)
20-PIN CONNECTOR
DC HEADER
REFIN
KEITHLEY S46 SWITCH SYSTEM
(FOR RFOUT AND REFIN ON 4 SITES)
ADRF6720
EVALUATION BOARD
RFOUT
6dB
OUTPUT (REF)
KEITHLEY S46 SWITCH SYSTEM
(FOR BASEBAND INPUTS ON 4 SITES)
Rohde & Schwarz SMT 06 SIGNAL GENERATOR
(REFIN)
BASEBAND INPUTS AT 1MHz
BASEB AND OUTPUTS
(I–, I+, Q–, Q+)
AEROFLEX IFR 3416 FREQUENCY GENERATOR
(WITH BASEBAND OUTPUTS AT 1MHz)
PC CONTROL
CONNECTED TO SYSTEM VIA USB TO GPIB ADAPTER
Figure 57. General Characterization Setup
Rev. 0 | Page 29 of 44
ADRF6720
Data Sheet
ADRF6720 PHASE NOISE STAND SETUP
ALL INSTRUMENTS ARE CONNECTED IN DAISY-CHAIN FASHION
VIA GBIP CABLE UNLESS OTHERWISE NOTED.
Rohde & Schwarz
SMA 100A SIGNAL GENERATOR
REFIN
AGILENT MXA N9020A
SPECTRUM ANALYZER
AGILENT E5052A SIGNAL SOURCE
ANALYZER
IF OUT
KEITHLEY S46 SWITCH SYSTEM 2
(FOR RFOUT AND REFIN ON 4 SITES)
REFIN
LOOUT±
BASEBAND INPUTS
(I–, I+, Q–, Q+)
IFR 3416 SIGNAL GENERATOR
(BASEBAND SOURCE)
KEITHLEY S46 SWITCH SYSTEM 1
(FOR BASEBAND INPUTS ON 4 SITES)
20-PIN CONNECTOR
(DC MEASUREMENT, +3.3V POS)
AND 12-PIN
CONNECTOR (VCO AND PLL
PROGRAMMING)
ADRF6720
EVALUATION BOARD
34980A MULTIFUNCTION SWITCH
(WITH 34950 AND 34921 MODULES)
AGILENT E3631A POWER
SUPPLY
INPUT DC
AGILENT 34401A DMM
(IN DC I MODE, SUPPLY CURRENT
MEASUREMENT)
PC CONTROL
CONNECTED TO SYSTEM VIA USB TO GPIB ADAPTER
Figure 58. Characterization Setup for Phase Noise and Reference Spur Measurements
Rev. 0 | Page 30 of 44
Data Sheet
ADRF6720
REGISTER MAP
Table 14. ADRF6720 Register Map
Bit 15
Bit 14
Bit 6
Bit 13
Bit 5
Bit 12
Bit 4
Bit 11
Bit 3
Bit 10
Bit 2
Bit 9
Bit 1
Bit 8
Bit 0
Reg Name
Bits Bit 7
Reset RW
0x00 SOFT_RESET [15:8]
[7:0]
RESERVED
0x0000 W
RESERVED
VCO_EN
SOFT_RESET
0x01
ENABLES
[15:8]
RESERVED
VCO_MUX_EN
LO_1XVCO_EN
DIV_EN
MOD_EN
CP_EN
QUAD_DIV_EN
LO_DRV2X_EN 0xF67F RW
RESERVED
[7:0] LO_DRV1X_EN
REF_BUF_EN
VCO_LDO_EN
INT_DIV[10:8]
0x02
INT_DIV
[15:8]
[7:0]
RESERVED
DIV_MODE
0x002C RW
INT_DIV[7:0]
0x03 FRAC_DIV [15:8]
[7:0]
FRAC_DIV[15:8]
FRAC_DIV[7:0]
MOD_DIV[15:8]
MOD_DIV[7:0]
0x0128 RW
0x0600 RW
0x04 MOD_DIV [15:8]
[7:0]
0x10 ENBL_MASK [15:8]
RESERVED
LO_1XVCO_MASK MOD_MASK QUAD_DIV_MASK LO_DRV2X_MASK 0xF67F RW
DIV_MASK CP_MASK VCO_LDO_MASK RESERVED
CP_CSCALE RESERVED
[7:0] LO_DRV1X_MASK VCO_MUX_MASK REF_BUF_MASK VCO_MASK
0x20
0x21
0x22
CP_CTL
PFD_CTL
VCO_CTL
[15:8]
[7:0]
RESERVED
RESERVED
CP_SEL
0x0C26 RW
0x000B RW
0x2A03 RW
0x0000 RW
0x1101 RW
0x0900 RW
0x0000 RW
0x0010 RW
0x000E RW
0x0000 RW
0x0000 RW
0x16BD RW
CP_BLEED
[15:8]
[7:0]
RESERVED
PFD_POLARITY
RESERVED
REF_MUX_SEL
VCO_LDO_R4SEL
LO_DRV_LVL DRVDIV2_EN
REF_SEL
VCO_LDO_R2SEL
VCO_SEL
[15:8]
[7:0]
DIV8_EN
DIV4_EN
0x30 BALUN_CTL [15:8]
RESERVED
[7:0]
BAL_COUT
RESERVED
MOD_RSEL[1:0]
RESERVED
BAL_CIN
MOD_RSEL[6:2]
MOD_CSEL
POL_Q
0x31 MOD_LIN_CTL [15:8]
[7:0]
0x32 MOD_CTL0 [15:8]
[7:0]
MOD_BLEED
POL_I
Q_LO
I_LO
0x33 MOD_CTL1 [15:8]
[7:0]
DCOFF_I
DCOFF_Q
RESERVED
0x40 PFD_CP_CTL [15:8]
[7:0]
RESERVED
ABLDLY
CP_CTRL
RESERVED
DITH_EN
PFD_CLK_EDGE
0x42 DITH_CTL1 [15:8]
[7:0]
RESERVED
DITH_MAG
DITH_VAL
0x43 DITH_CTL2 [15:8]
[7:0]
DITH_VAL[15:8]
DITH_VAL[7:0]
0x45 VCO_CTL2 [15:8]
RESERVED
VTUNE_CTRL
[7:0] VCO_BAND_SRC
0x49 VCO_CTL3 [15:8] RESERVED
[7:0]
BAND
SET_1
SET_0[8]
SET_0[7:0]
Rev. 0 | Page 31 of 44
ADRF6720
Data Sheet
REGISTER DETAILS
Address: 0x00, Reset: 0x0000, Name: SOFT_RESET
Table 15. Bit Descriptions for SOFT_RESET
Bits
Bit Name
Settings
Description
Reset
Access
0
SOFT_RESET
Soft Reset.
0x0
W
Address: 0x01, Reset: 0xF67F, Name: ENABLES
Table 16. Bit Descriptions for ENABLES
Bits
11
10
9
8
7
6
5
4
3
Bit Name
Settings
Description
Reset
0x0
0x1
0x1
0x0
0x0
0x1
0x1
0x1
0x1
0x1
0x1
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
LO_1XVCO_EN
MOD_EN
Enables 1 × LO with Internal VCO.
Enables MOD/LO Drive Chain.
Enables Quad Divider for 2 × LO Operation.
Enables External 2 × LO Driver—Before Quad Divider.
Enables External 1 × LO Driver—After Quad Divider.
Enables VCO Mux.
Enables Reference Buffer.
Enables VCOs.
Enables VCO Dividers.
Enables Charge Pump.
QUAD_DIV_EN
LO_DRV2X_EN
LO_DRV1X_EN
VCO_MUX_EN
REF_BUF_EN
VCO_EN
DIV_EN
CP_EN
VCO_LDO_EN
2
1
Enables VCO LDO.
Rev. 0 | Page 32 of 44
Data Sheet
ADRF6720
Address: 0x02, Reset: 0x002C, Name: INT_DIV
Table 17. Bit Descriptions for INT_DIV
Bits
Bit Name
Settings
Description
Divide Mode.
Fractional
Reset
Access
11
DIV_MODE
0x0
RW
0
1
Integer
[10:0]
INT_DIV
Divider INT Value.
0x2C
RW
Address: 0x03, Reset: 0x0128, Name: FRAC_DIV
Table 18. Bit Descriptions for FRAC_DIV
Bits
Bit Name
Settings
Description
Reset
Access
[15:0]
FRAC_DIV
Divider FRAC Value.
0x128
RW
Address: 0x04, Reset: 0x0600, Name: MOD_DIV
Table 19. Bit Descriptions for MOD_DIV
Bits
Bit Name
Settings
Description
Reset
Access
[15:0]
MOD_DIV
Divider Modulus Value.
0x600
RW
Rev. 0 | Page 33 of 44
ADRF6720
Data Sheet
Address: 0x10, Reset: 0xF67F, Name: ENBL_MASK
Table 20. Bit Descriptions for ENBL_MASK
Bits
11
10
9
8
7
6
5
4
3
Bit Name
Settings
Description
Reset
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
LO_1XVCO_MASK
MOD_MASK
Enable 1 × LO with internal VCO.
MOD Enable.
Quadrature Divide Path Enable (2 ×/4 ×/8 × LO).
External 2 × LO Driver Enable—Before Quad Divider.
External 1 × LO Driver Enable—After Quad Divider.
VCO_Mux_Enable.
Reference Buffer Enable.
Power Up VCOs.
Power Up Dividers.
Power Up Charge Pump.
0x0
0x1
0x1
0x0
0x0
0x1
0x1
0x1
0x1
0x1
0x1
QUAD_DIV_MASK
LO_DRV2X_MASK
LO_DRV1X_MASK
VCO_MUX_MASK
REF_BUF_MASK
VCO_MASK
DIV_MASK
CP_MASK
VCO_LDO_MASK
2
1
Power Up VCO LDO.
Address: 0x20, Reset: 0x0C26, Name: CP_CTL
Rev. 0 | Page 34 of 44
Data Sheet
ADRF6720
Table 21. Bit Descriptions for CP_CTL
Bits
Bit Name
Settings
Description
Reset
Access
14
CP_SEL
Charge Pump Reference Current Select.
Internal Charge Pump.
External Charge Pump.
0x0
RW
0
1
[13:10] CP_CSCALE
Charge Pump Coarse Scale Current.
0x3
RW
RW
0001 250 μA.
0011 500 μA.
0111 750 μA.
1111 1000 μA.
[5:0]
CP_BLEED
Charge Pump Bleed.
0x26
000000 0 μA
000001 15.625 μA Sink.
000010 31.25 μA Sink.
000011 46.875 μA Sink.
…
011111 484.375 μA Sink.
100000 0 μA.
100001 15.625 μA Source.
100010 31.25 μA Source.
100011 46.875 μA Source.
…
111111 484.375 μA Source.
Address: 0x21, Reset: 0x000B, Name: PFD_CTL
Table 22. Bit Descriptions for PFD_CTL
Bits
Bit Name
Settings
Description
Reset
Access
[6:4]
REF_MUX_SEL
Reference (REF) Output Mux Select.
0x0
RW
000 LOCK_DET.
001 VPTAT.
010 REFCLK.
011 REFCLK/2.
100 REFCLK × 2.
101 REFCLK/8.
110 REFCLK/4.
3
PFD_POLARITY
Set PFD Polarity.
Positive.
Negative.
0x1
RW
0
1
Rev. 0 | Page 35 of 44
ADRF6720
Data Sheet
Bits
Bit Name
REF_SEL
Settings
Description
Reset
Access
[2:0]
Set REF Input Multiply/Divide Ratio.
0x3
RW
000 ×2.
001 ×1.
010 Divide by 2.
011 Divide by 4.
100 Divide by 8.
Address: 0x22, Reset: 0x2A03, Name: VCO_CTL
Table 23. Bit Descriptions for VCO_CTL
Bits Bit Name Settings
[15:12] VCO_LDO_R4SEL
Description
Reset
0x2
Access
RW
VCO LDO Resistor 4 Selections.
VCO LDO Resistor 2 Selections.
Set External LO Output Amplitude.
[11:8]
[7:6]
VCO_LDO_R2SEL
LO_DRV_LVL
0xA
RW
0x0
RW
00 −5.1 dBm.
01 −0.5 dBm.
10 3 dBm.
5
4
3
DRVDIV2_EN
DIV8_EN
Divide by 2 for External LO Driver Enable.
Disable.
Enable.
0x0
0x0
0x0
RW
RW
RW
0
1
Divide by 2 in LO Path for Total of Division of 8.
Disable.
Enable.
0
1
DIV4_EN
Divide by 2 in LO Path for Total of Division of 4.
0
1
Disable.
Enable.
Rev. 0 | Page 36 of 44
Data Sheet
ADRF6720
Bits
Bit Name
Settings
Description
Reset
Access
[2:0]
VCO_SEL
Select VCO Core/External LO.
0x3
RW
000 4.6 GHz to 5.71 GHz.
001 4.02 GHz to 4.6 GHz.
010 3.5 GHz to 4.02 GHz.
011 2.85 GHz to 3.5 GHz.
100 External LO/VCO.
Address: 0x30, Reset: 0x0000, Name: BALUN_CTL
Table 24. Bit Descriptions for BALUN_CTL
Bits
Bit Name
Settings
Description
Reset
Access
[7:4]
BAL_COUT
Set Balun Output Capacitance.
0x0
RW
0000 Minimum Capacitance Value.
1111 Maximum Capacitance Value.
Set Balun Input Capacitance.
[3:0]
BAL_CIN
0x0
RW
0000 Minimum Capacitance Value.
1111 Maximum Capacitance Value.
Address: 0x31, Reset: 0x1101, Name: MOD_LIN_CTL
Table 25. Bit Descriptions for MOD_LIN_CTL
Bits
Bit Name
Settings
Description
Reset
0x44
0x01
Access
RW
[12:6]
[5:0]
MOD_RSEL
MOD_CSEL
Modulator Linearizer RSEL Value.
Modulator Linearizer CSEL Value.
RW
Rev. 0 | Page 37 of 44
ADRF6720
Data Sheet
Address: 0x32, Reset: 0x0900, Name: MOD_CTL0
Table 26. Bit Descriptions for MOD_CTL0
Bits
Bit Name
Settings
Description
Reset
0x0
Access
RW
[14:12] MOD_BLEED
[11:10] POL_Q
Modulator Bleed Current.
Quadrature Polarity Switch, Q Channel.
01 Inverted Q Channel Polarity.
10 Normal Polarity.
0x2
RW
[9:8]
POL_I
Quadrature Polarity Switch, I Channel.
01 Normal Polarity.
0x1
RW
10 Inverted I Channel Polarity.
Unwanted Sideband Nulling, Q Channel.
Unwanted Sideband Nulling, I Channel.
[7:4]
[3:0]
Q_LO
I_LO
0x0
0x0
RW
RW
Address: 0x33, Reset: 0x0000, Name: MOD_CTL1
Rev. 0 | Page 38 of 44
Data Sheet
ADRF6720
Table 27. Bit Descriptions for MOD_CTL1
Bits
Bit Name
Settings
Description
Reset
Access
[15:8]
DCOFF_I
LO Nulling, I Channel.
0x0
RW
00000000 0 μA.
00000001 +5 μA.
00000010 +10 μA.
00000011 +15 μA.
…
…
01111110 +630 μA.
01111111 +635 μA.
10000000 0 μA.
10000001 −5 μA.
10000010 −10 μA.
10000011 −15 μA.
…
…
11111110 −630 μA.
11111111 −635 μA.
[7:0]
DCOFF_Q
LO Nulling, Q Channel.
0x0
RW
00000000 0 μA.
00000001 +5 μA.
00000010 +10 μA.
00000011 +15 μA.
…
…
01111110 +630 μA.
01111111 +635 μA.
10000000 0 μA.
10000001 −5 μA.
10000010 −10 μA.
10000011 −15 μA.
…
…
11111110 −630 μA.
11111111 −635 μA.
Address: 0x40, Reset: 0x0010, Name: PFD_CP_CTL
Rev. 0 | Page 39 of 44
ADRF6720
Data Sheet
Table 28. Bit Descriptions for PFD_CP_CTL
Bits
Bit Name
Settings
Description
Reset
Access
[6:5]
ABLDLY
Set Antibacklash Delay.
0x0
RW
00 0 ns.
01 0.5 ns.
10 0.75 ns.
11 0.9 ns.
[4:2]
[1:0]
CP_CTRL
Set Charge Pump Control.
0x4
0x0
RW
RW
000 Both On.
001 Pump Down.
010 Pump Up.
011 Tristate.
100 PFD.
PFD_CLK_EDGE
Set PFD Clock Edge Trigger.
00 Divide and Reference Down Edge.
01 Divide Down Edge, Reference Up Edge.
10 Divide Up Edge, Reference Down Edge.
11 Divide and Reference Up Edge.
Address: 0x42, Reset: 0x000E, Name: DITH_CTL1
Table 29. Bit Descriptions for DITH_CTL1
Bits
Bit Name
Settings
Description
Reset
Access
3
DITH_EN
Set Dither Enable.
Disable.
Enable.
0x1
RW
0
1
[2:1]
0
DITH_MAG
DITH_VAL
Set Dither Magnitude.
Set Dither Value.
0x3
0x0
RW
RW
Address: 0x43, Reset: 0x0000, Name: DITH_CTL2
Table 30. Bit Descriptions for DITH_CTL2
Bits
Bit Name
Settings
Description
Reset
Access
[15:0]
DITH_VAL
Set Dither Value.
0x0
RW
Rev. 0 | Page 40 of 44
Data Sheet
ADRF6720
Address: 0x45, Reset: 0x0000, Name: VCO_CTL2
Table 31. Bit Descriptions for VCO_CTL2
Bits
Bit Name
Settings
Description
Reset
Access
[9:8]
VTUNE_CTRL
Source for VCO VTUNE Pin.
00 Band Calibration Routine.
01 SPI.
0x0
RW
7
VCO_BAND_SRC
BAND
VCO Band Source
Band Calibration Routine.
SPI.
0x0
RW
RW
0
1
[6:0]
VCO Band Selection.
0x00
Address: 0x49, Reset: 0x16BD, Name: VCO_CTL3
Table 32. Bit Descriptions for VCO_CTL3
Bits
Bit Name
Settings
Description
Reset
Access
[13:9]
SET_1
Internal Settings. Refer to the Required PLL/VCO Settings and Register
Write Sequence section.
0x0B
RW
[8:0]
SET_0
Internal Settings. Refer to the Required PLL/VCO Settings and Register
Write Sequence section.
0x0BD
RW
Rev. 0 | Page 41 of 44
ADRF6720
Data Sheet
OUTLINE DIMENSIONS
6.10
6.00 SQ
5.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
31
40
1
30
0.50
BSC
4.55
4.40 SQ
4.25
EXPOSED
PAD
10
21
11
20
0.45
0.40
0.35
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD.
Figure 60. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
6 mm × 6 mm Body, Very Very Thin Quad
(CP-40-11)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +85°C
Package Description
Package Option
ADRF6720ACPZ-R7
ADRF6720-EVALZ
40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Evaluation Board
CP-40-11
1 Z = RoHS Compliant Part.
Rev. 0 | Page 42 of 44
Data Sheet
NOTES
ADRF6720
Rev. 0 | Page 43 of 44
ADRF6720
NOTES
Data Sheet
©2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12134-0-4/14(0)
Rev. 0 | Page 44 of 44
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