ADSP-1981BL [ADI]
AC 97 SoundMAX Codec; AC 97的SoundMAX编解码器
| 型号： | ADSP-1981BL |
| 厂家： | 
ADI |
| 描述： | AC 97 SoundMAX Codec |
| 文件： | 总32页 (文件大小：1238K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AC ’97 SoundMAX® Codec
AD1981BL
AC ’97 2.3 COMPATIBLE FEATURES
S/PDIF output, 20-bit data format, supporting
48 kHz and 44.1 kHz sample rates
Integrated stereo headphone amplifier
Variable sample rate audio
External audio power-down control
>90 dB dynamic range
Stereo full-duplex codec
ENHANCED FEATURES
Stereo MIC preamplifier support
Built-in digital equalizer function for optimized
speaker sound
Full-duplex variable sample rates from 7040 Hz to
48 kHz with 1 Hz resolution
Jack sense pins for automatic output switching
Software-programmed VREFOUT output for biasing
microphone and external power amplifier
Low power 3.3 V operation for analog and digital supplies
Multiple codec configuration options
20-bit PCM DAC
3 analog line-level stereo inputs for line-in, AUX, and CD
Mono line-level phone input
Dual MIC input with built-in programmable preamplifier
High quality CD input with ground sense
Mono output for speakerphone or internal speaker
power management support
48-lead LQFP package, Pb-free available
FUNCTIONAL BLOCK DIAGRAM
V
V
REF
XTL_OUT XTL_IN SPDIF
REFOUT
AD1981BL
VOLTAGE
REFERENCE
G
MIC PREAMP
CODEC CORE
SPDIF
TX
MIC1
G
G
MIC2
PHONE_IN
CD_L
PCM L/R
ADC RATE
PLL
ID0
16-BIT
G
G
M
M
CD
DIFF AMP
Σ-∆ ADC
CD_GND
CD_R
16-BIT
ID1
AUX_L
Σ-∆ ADC
AUX_R
LINE_IN_L
LINE_IN_R
ADC
RESET
SYNC
AND
DAC
SLOT
LOGIC
16-BIT
G
G
M
M
Σ-∆ADC
16-BIT
Σ-∆ ADC
BIT_CLK
SDATA_OUT
SDATA_IN
A
MONO_OUT
M
20-BIT
GA
GA
M
M
Σ-∆ DAC
EQ
HP
A
A
A
A
HP_OUT_L
LINE_OUT_L
LINE_OUT_R
HP_OUT_R
M
20-BIT
Σ-∆ DAC
GA
M
GA
M
EQ
PCM FRONT
DAC RATE
G = GAIN
GA
M
GA
M
MZ
A = ATTENUATION
M = MUTE
GA
M
GA
M
Z = HIGH Z
GA
M
GA
M
AC '97
MZ
CONTROL
REGISTERS
M
HP
M
ANALOG MIXING
CONTROL LOGIC
EAPD
EAPD
M
JS0
JS1
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
AD1981BL
TABLE OF CONTENTS
Specifications..................................................................................... 3
PCM-Out Volume Register....................................................... 18
Record Select Control Register................................................. 19
Record Gain Register................................................................. 19
General-Purpose Register ......................................................... 20
Power-Down Control/Status Register ..................................... 21
Extended Audio ID Register..................................................... 22
Extended Audio Status and Control Register......................... 22
PCM Front DAC Rate Register................................................. 23
PCM ADC Rate Register........................................................... 23
SPDIF Control Register............................................................. 24
EQ Control Register................................................................... 24
EQ Data Register........................................................................ 26
Mixer ADC, Input Gain Register ............................................. 26
Jack Sense/Audio Interrupt/Status Register............................ 27
Serial Configuration Register ................................................... 29
Miscellaneous Control Bit Register ......................................... 29
Vendor ID Registers................................................................... 31
Outline Dimensions....................................................................... 32
Ordering Guide .......................................................................... 32
Test Conditions............................................................................. 3
General Specifications ................................................................. 3
Power-Down States ...................................................................... 5
Timing Parameters....................................................................... 5
Absolute Maximum Ratings............................................................ 9
Environmental Conditions.......................................................... 9
Pin Configuration and Function Descriptions........................... 10
Indexed Control Registers............................................................. 12
Control Register Details ................................................................ 13
Reset Register.............................................................................. 13
Master Volume Register............................................................. 13
Headphone Volume Register .................................................... 14
Mono Volume Register .............................................................. 15
Phone Volume Register.............................................................. 15
MIC Volume Register................................................................. 16
Line-In Volume Register............................................................ 16
CD Volume Register................................................................... 17
AUX Volume Register ................................................................ 17
REVISION HISTORY
1/05—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to Ordering Guide .......................................................... 32
1/04—Revision 0: Initial Version
Rev. A | Page 2 of 32
AD1981BL
SPECIFICATIONS
TEST CONDITIONS
Standard test conditions, unless otherwise noted.
Table 1.
Parameter
Test Condition
Temperature
25°C
Digital Supply (DVDD)
Analog Supply (AVDD)
Sample Rate (fS)
Input Signal
3.3 V
3.3 V
48 kHz
1008 Hz
Analog Output Pass Band
DAC
20 Hz to 20 kHz
Calibrated
−3 dB Attenuation Relative to Full Scale
0 dB Input
10 kΩ Output Load (LINE_OUT)
32 Ω Output Load (HP_OUT)
Calibrated
ADC
0 dB Gain
Input −3.0 dB Relative to Full Scale
GENERAL SPECIFICATIONS
Table 2.
Parameter
Min
Typ
Max
Unit
ANALOG INPUT
Input Voltage (RMS Values Assume Sine Wave Input)
LINE_IN, AUX, CD, PHONE_IN
0.707
2.0
0.0707
0.2
1.707
2.0
20
V rms
V p-p
V rms
V p-p
V rms
V p-p
kΩ
MIC_IN with 20 dB Gain
MIC_IN with 0 dB Gain
Input Impedance1
Input Capacitance1
5
7.5
pF
MASTER VOLUME
Step Size (0 dB to −46.5 dB): LINE_OUT_L, LINE_OUT_R
Output Attenuation Range1
Step Size (0 dB to −46.5 dB): MONO_OUT
Output Attenuation Range1
Step Size (0 dB to −46.5 dB): HP_OUT_R, HP_OUT_L
Output Attenuation Range Span1
Mute Attenuation of 0 dB Fundamental1
PROGRAMMABLE GAIN AMPLIFIER—ADC
Step Size (0 dB to 22.5 dB)
1.5
46.5
1.5
46.5
1.5
46.5
dB
dB
dB
dB
dB
dB
dB
80
1.5
22.5
dB
dB
PGA Gain Range
ANALOG MIXER—INPUT GAIN/AMPLIFIERS/ATTENUATORS
Signal-to-Noise Ratio (SNR)
CD to LINE_OUT
Other to LINE_OUT1
90
90
dB
dB
Rev. A | Page 3 of 32
AD1981BL
Parameter
Min
Typ
1.5
Max
Unit
dB
Step Size (+12 dB to −34.5 dB) (All Steps Tested):
MIC_IN, LINE_IN, CD, AUX, PHONE_IN, DAC
Input Gain/Attenuation Range:
MIC_IN, LINE_IN, CD, AUX, PHONE_IN, DAC
DIGITAL DECIMATION AND INTERPOLATION FILTERS1
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
46.5
dB
0
0.4 × fS
0.09
0.6 × fS
∞
Hz
dB
Hz
Hz
0.4 × fS
0.6 × fS
Stop-Band Rejection
Group Delay
Group Delay Variation over Pass Band
ANALOG-TO-DIGITAL CONVERTERS
−74
dB
sec
µs
16/fS
0
Resolution
Total Harmonic Distortion (THD)
Dynamic Range (−60 dB Input THD + N Referenced to Full Scale, A-Weighted)
Signal-to-Intermodulation Distortion1CCIF Method)
ADC Crosstalk1
16
−87
83
Bits
dB
dB
dB
78
85
Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L)
Line_In to Other
Gain Error2 (Full-Scale Span Relative to Nominal Input Voltage)
Interchannel Gain Mismatch (Difference of Gain Errors)
ADC Offset Error1
−80
−100
dB
dB
%
dB
mV
−80
10
0.5
5
DIGITAL-TO-ANALOG CONVERTERS
Resolution
20
Bits
dB
dB
dB
dB
%
Total Harmonic Distortion (THD) LINE_OUT
Total Harmonic Distortion (THD) HP_OUT
Dynamic Range (−60 dB Input THD + N Referenced to Full Scale, A-Weighted)
Signal-to-Intermodulation Distortion1 (CCIF Method)
Gain Error2 (Output FS Voltage Relative to Nominal Output FS Voltage)
Interchannel Gain Mismatch (Difference of Gain Errors)
−88
−81
87.5
−100
82
10
0.7
−80
dB
dB
DAC Crosstalk1 (Input L, Zero R, Measure R_OUT; Input R, Zero L, Measure
L_OUT)
ANALOG OUTPUT
Full-Scale Output Voltage; LINE_OUT and MONO_OUT
0.707
2.0
V rms
V p-p
Ω
kΩ
pF
pF
V rms
Ω
V
V
Output Impedance1
800
100
External Load Impedance1
10
Output Capacitance1
15
1
External Load Capacitance1
Full-Scale Output Voltage; HP_OUT (0 dB Gain)
External Load Impedance1
32
1
VREF
VREFOUT
VREFOUT Current Drive
Mute Click (Muted Output Minus Unmuted Midscale DAC Output)
STATIC DIGITAL SPECIFICATIONS
High Level Input Voltage (VIH): Digital Inputs
Low Level Input Voltage (VIL)
High Level Output Voltage (VOH), IOH = 2 mA
1.12
2.25
1.225
5
mA
mV
5
0.65 × DVDD
0.9 × DVDD
V
V
V
0.35 × DVDD
Rev. A | Page 4 of 32
AD1981BL
Parameter
Min
Typ
Max
Unit
Low Level Output Voltage (VOL), IOL = 2 mA
Input Leakage Current
Output Leakage Current
0.1 × DVDD
+10
+10
V
µA
µA
−10
−10
POWER SUPPLY
Power Supply Range (AVDD and DVDD)
Power Dissipation
Analog Supply Current—3.3 V (AVDD)
Digital Supply Current—3.3 V (DVDD)
Power Supply Rejection (100 mV p-p Signal at 1 kHz)1
3.0
3.47
V
2.87
39
48
mW
mA
mA
dB
40
(At Both Analog and Digital Supply Pins, Both ADCs and DACs)
CLOCK SPECIFICATIONS1
Input Clock Frequency
Recommended Clock Duty Cycle
24.576
50
MHz
%
40
60
1 Guaranteed but not tested.
2 Measurements reflect main ADC.
POWER-DOWN STATES
Values presented with VREFOUT not loaded.
Table 3.
Parameter
Fully Active
ADC
DAC
ADC + DAC
Mixer
ADC + Mixer
DAC + Mixer
ADC + DAC + Mixer
Standby
Set Bits
DVDD Typ
AVDD Typ
Unit
No Bits Value
PR0
PR1
PR1, PR0
PR2
PR2, PR0
PR2, PR1
PR2, PR1, PR0
47.76
40.1
32.8
13.2
47.7
40
32.77
13.9
0
38.9
34.39
26.3
20.55
19.39
14.86
6.39
1.15
0
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
PR5, PR4, PR3, PR2, PR1, PR0
PR6
Headphone Standby
47.7
32
TIMING PARAMETERS
Guaranteed over operating temperature range.
Table 4.
Parameter
Symbol
tRST_LOW
tRST2CLK
Min
Typ
Max
Unit
RESET Active Low Pulse Width
RESET Inactive to BIT_CLK Start-Up Delay
SYNC Active High Pulse Width
SYNC Low Pulse Width
SYNC Inactive to BIT_CLK Start-Up Delay
BIT_CLK Frequency
BIT_CLK Frequency Accuracy
BIT_CLK Period
BIT_CLK Output Jitter1, 2, 3
BIT_CLK High Pulse Width
BIT_CLK Low Pulse Width
SYNC Frequency
1.0
ms
ns
162.8
tSYNC_HIGH
tSYNC_LOW
tSYNC2CLK
1.3
19.5
µs
µs
ns
MHz
ppm
ns
ps
ns
162.8
12.288
1
tCLK_PERIOD
81.4
750
42
38
48.0
2000
48.84
tCLK_HIGH
tCLK_LOW
32.56
32.56
ns
kHz
Rev. A | Page 5 of 32
AD1981BL
Parameter
Symbol
tSYNC_PERIOD
tSETUP
tHOLD
tRISECLK
tFALLCLK
tRISESYNC
tFALLSYNC
tRISEDIN
tFALLDIN
tRISEDOUT
tFALLDOUT
tS2_PDOWN
tSETUP2RST
tOFF
Min
Typ
20.8
2.5
Max
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
SYNC Period
Setup to Falling Edge of BIT_CLK
Hold from Falling Edge of BIT_CLK
BIT_CLK Rise Time
BIT_CLK Fall Time
SYNC Rise Time
SYNC Fall Time
SDATA_IN Rise Time
SDATA_IN Fall Time
SDATA_OUT Rise Time
5
5
2
2
2
2
2
2
2
2
0
15
4
4
4
4
4
4
4
4
6
6
6
6
6
6
6
6
SDATA_OUT Fall Time
End of Slot 2 to BIT_CLK, SDATA_IN Low
Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT)
Rising Edge of RESET to High Z Delay
Propagation Delay
1.0
25
15
50
15
RESET Rise Time
Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid
1 Guaranteed but not tested.
2 Output jitter is directly dependent on crystal input jitter.
3 Maximum jitter specification is for noncrystal operation only. Crystal operation maximum is much lower.
tRST2CLK
tRST_LOW
RESET
tTRI2ACTV
BIT_CLK
tTRI2ACTV
SDATA_IN
Figure 2. Cold Reset Timing (Codec is Supplying the BIT_CLK Signal)
tSYNC_HIGH
tSYNC2CLK
SYNC
BIT_CLK
Figure 3. Warm Reset Timing
Rev. A | Page 6 of 32
AD1981BL
tCLK_LOW
BIT_CLK
tCLK_HIGH
tCLK_PERIOD
tSYNC_LOW
SYNC
tSYNC_HIGH
tSYNC_PERIOD
Figure 4. Clock Timing
BIT_CLK
tRISECLK
tFALLCLK
SYNC
tRISESYNC
tFALLSYNC
SDATA_IN
tRISEDIN
tFALLDIN
SDATA_OUT
tRISEDOUT
Figure 5. Signal Rise and Fall Times
tFALLDOUT
SLOT 1
SLOT 2
SYNC
BIT_CLK
WRITE TO
0x20
DATA
PR4
SDATA_OUT
SDATA_IN
tS2_PDOWN
BIT_CLK NOT TO SCALE
Figure 6. AC-Link Low Power Mode Timing
Rev. A | Page 7 of 32
AD1981BL
tCO
tSETUP
V
V
IL
BIT_CLK
IH
SDATA_OUT
SDATA_IN
SYNC
V
V
OH
OL
tHOLD
Figure 7. AC-Link Low Power Mode Timing, SYNC and BIT_CLK Chopped
RESET
SDATA_OUT
tSETUP2RST
SDATA_IN, BIT_CLK,
EAPD, SPDIF_OUT
AND DIGITAL I/O
HIGH Z
tOFF
Figure 8. ATE Test Mode
Rev. A | Page 8 of 32
AD1981BL
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Stresses greater than those listed under Absolute Maximum
Parameter
Rating
Ratings may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Power Supplies
Digital (DVDD)
−0.3 V to +3.6 V
−0.3 V to +6.0 V
10 mA
Analog (AVDD)
Input Current (Except Supply Pins)
Signals Pins
Digital Input Voltage
Analog Input Voltage
−0.3 V to DVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
0°C to 70°C
ENVIRONMENTAL CONDITIONS
Ambient Temperature Range
(Operating)
Ambient Temperature Rating (LQFP Package)
TCASE = Case Temperature in °C
PD = Power Dissipation in W
θJA Thermal Resistance (Junction to Ambient)
θJC Thermal Resistance (Junction to Case)
Table 6. Thermal Resistance
Package
θJA
θJC
LQFP
50.1°C/W
17.8°C/W
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degrada-
tion or loss of functionality.
Rev. A | Page 9 of 32
AD1981BL
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
DV
1
1
2
3
4
5
6
7
8
9
36 LINE_OUT_R
35 LINE_OUT_L
DD
XTL_IN
XTL_OUT
34 AV
33 AV
4
DD
DV
1
4
SS
SS
SDATA_OUT
BIT_CLK
32 AFILT4
31 AFILT3
30 AFILT2
29 AFILT1
AD1981BL
TOP VIEW
(Not to Scale)
DV
2
SS
SDATA_IN
DV
2
28
27
V
V
DD
REFOUT
REF
SYNC 10
RESET 11
NC 12
26 AV
25 AV
1
SS
DD
1
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
Figure 9. 48-Lead LQFP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
I/O Description
DIGITAL I/O
2
3
5
6
XTL_IN
I
O
I
Crystal Input (24.576 MHz) or External Clock Input.
Crystal Output.
AC-Link Serial Data Output, AD1981BL Data Input Stream.
XTL_OUT
SDATA_OUT
BIT_CLK
O/I AC-Link Bit Clock Output (12.288 MHz) or Bit Clock Input, if Secondary Mode
Selected.
8
10
SDATA_IN
SYNC
O
I
AC-Link Serial Data Input, AD1981BL Data Output Stream.
AC-Link Frame Sync.
11
RESET
I
AC-Link Reset, AD1981BL Master Hardware Reset.
S/PDIF Output.
48
SPDIF
O
CHIP SELECTS1
45
ID0
ID1
I
I
Chip Select Input 0 (Active Low). This pin can also be used as the chain input from a
secondary codec.
Chip Select Input 1 (Active Low).
46
JACK SENSE AND EAPD
17
JS0
I
Jack Sense 0 Input.
16
JS1
I
Jack Sense 1 Input.
47
EAPD
O
External Amp Power-Down Control.
ANALOG I/O
13
14
15
18
19
20
21
PHONE_IN
AUX_L
AUX_R
CD_L
CD_GND_REF
CD_ R
I
I
I
I
I
I
I
Phone Input. Mono input from telephony subsystem speaker phone or handset.
Auxiliary Input Left Channel.
Auxiliary Input Right Channel.
CD Audio Left Channel.
CD Audio Analog Ground Reference for Differential CD Input.
CD Audio Right Channel.
MIC1
Microphone 1 Input (Mono) or Left Channel when 2-Channel Mode Selected
(Stereo MIC).
Rev. A | Page 10 of 32
AD1981BL
Pin No.
Mnemonic
I/O Description
22
MIC2
I
Microphone 2 Input (Mono) or Right Channel when 2-Channel Mode Selected
(Stereo MIC).
23
LINE_IN_L
I
Line-In Left Channel.
24
LINE_IN_R
I
Line-In Right Channel.
35
36
37
39
LINE_OUT_L
LINE_OUT_R
MONO_OUT
HP_OUT_L
HP_OUT_R
O
O
O
O
O
Line-Out (Front) Left Channel.
Line-Out (Front) Right Channel.
Monaural Output to Telephony Subsystem Speaker Phone.
Headphone Left-Channel Output.
Headphone Right-Channel Output.
41
FILTER/REFERENCE2
27
28
29
30
31
32
VREF
O
O
O
O
O
O
Voltage Reference Filter.
Voltage Reference Output 5 mA Drive (Intended for MIC Bias and Power Amp Bias).
Antialiasing Filter Capacitor—ADC Right Channel.
Antialiasing Filter Capacitor—ADC Left Channel.
Antialiasing Filter Capacitor—Mixer ADC Right Channel.
Antialiasing Filter Capacitor—Mixer ADC Left Channel.
VREFOUT
AFILT1
AFILT2
AFILT3
AFILT4
POWER AND GROUND
SIGNALS
1
4
7
9
25
26
38
40
43
44
34
33
DVDD1
DVSS1
DVSS2
DVDD2
AVDD1
AVSS1
AVDD2
AVSS2
AVDD3
AVSS3
AVDD4
AVSS4
I
I
I
I
I
I
I
I
I
I
I
I
Digital VDD, 3.3 V.
Digital GND.
Digital GND.
Digital VDD, 3.3 V.
Analog VDD, 3.3 V.
Analog GND.
Analog VDD, 3.3 V.
Analog GND.
Analog VDD, 3.3 V.
Analog GND.
Analog VDD, 3.3 V.
Analog GND.
NO CONNECTS
12
42
NC
NC
No Connect.
No Connect.
1 These pins can also be used to select an external clock. See Table 44.
2 These signals are connected to resistors, capacitors, or specific voltages.
Rev. A | Page 11 of 32
AD1981BL
INDEXED CONTROL REGISTERS
Table 8.
Reg
Name
D15
X
D14
SE4
X
D13
SE3
X
D12
SE2
D11
SE1
D10
SE0
D9
D8
D7
D6
ID6
X
D5
ID5
X
D4
D3
D2
D1
D0
Default
0x0090
0x8000
0x00
0x02
Reset
ID9
ID8
ID7
RM1
ID4
ID3
ID2
ID1
ID0
Master
MM
LMV4
LMV3
LMV2
LMV1
LMV0
RMV4
RMV3
RMV2
RMV1
RMV0
Volume
0x04
0x06
0x0C
Headphone
Volume
HPM
MVM
PHM
X
X
X
X
X
X
LHV4
LHV3
LHV2
LHV1
LHV0
RM1
X
X
X
X
X
X
X
RHV4
MV4
RHV3
MV3
RHV2
MV2
RHV1
MV1
RHV0
MV0
0x8000
0x8000
0x8008
Mono
Volume
X
X
X
X
X
X
X
X
X
X
Phone
Volume
X
PHV4
PHV3
PHV2
PHV1
PHV0
0x0E
0x10
MIC Volume
MCM
LVM
X
X
X
X
X
X
X
X
X
X
RM1
M20
X
X
X
MCV4
RLV4
MCV3
RLV3
MCV2
RLV2
MCV1
RLV1
MCV0
RLV0
0x8008
0x8808
Line-In
Volume
LLV4
LLV3
LLV2
LLV1
LLV0
0x12
0x16
0x18
CD Volume
CVM
AM
X
X
X
X
X
X
LCV4
LAV4
LOV4
LCV3
LAV3
LOV3
LCV2
LAV2
LOV2
LCV1
LAV1
LOV1
LCV0
LAV0
LOV0
RM1
RM1
RM1
X
X
X
X
X
X
RCV4
RAV4
ROV4
RCV3
RAV3
ROV3
RCV2
RAV2
ROV2
RCV1
RAV1
ROV1
RCV0
RAV0
ROV0
0x8808
0x8808
0x8808
AUX Volume
PCM-Out
Volume
OM
0x1A
Record
Select
X
X
X
X
X
LS2
LS1
LS0
X
X
X
X
X
RS2
RS1
RS0
0x0000
0x1C
0x20
Record Gain
IM
X
X
X
X
X
X
X
LIM3
X
LIM2
X
LIM1
MIX
LIM0
MS
RM1
X
X
X
X
X
X
RIM3
X
RIM2
X
RIM1
X
RIM0
X
0x8000
0x0000
General-
Purpose
LPBK
0x26
0x28
0x2A
0x2C
0x32
0x3A
0x60
Power-Down
Ctrl/Stat
EAPD
IDC1
VFORCE
SRF15
SRA15
V
PR6
IDC0
X
PR5
X
PR4
X
PR3
REVC1
X
PR2
PR1
AMAP
X
PR0
X
X
X
X
X
REF
X
ANL
DAC
X
ADC
VRAS
VRA
0x000X
0xX605
0x0000
0xBB80
0xBB80
0x2000
0x8080
Ext’d Audio
ID
REVC0
SPCV
SRF10
SRA10
CC6
X
X
DSA1
SPSA1
SRF5
SRA5
CC1
DSA0
SPSA0
SRF4
SRA4
CC0
SPDIF
SPDIF
SRF2
SRA2
COPY
BCA2
Ext’d Audio
Stat/Ctrl
X
X
X
X
X
X
X
PCM Front
DAC Rate
SRF14
SRA14
X
SRF13
SRA13
SPSR1
X
SRF12
SRA12
SPSR0
X
SRF11
SRA11
L
SRF9
SRA9
CC5
X
SRF8
SRA8
CC4
X
SRF7
SRA7
CC3
SYM
SRF6
SRA6
CC2
CHS
SRF3
SRA3
PRE
BCA3
SRF1
SRA1
/AUD
BCA1
SRF0
SRA0
PRO
PCM L/R
ADC Rate
SPDIF
Control
EQ Ctrl
EQM
MAD
LBEN
X
X
BCA5
BCA4
BCA0
0x62
0x64
EQ Data
CFD15
MXM
CFD14
X
CFD13
X
CFD12
X
CFD11
LMG3
CFD10
LMG2
CFD9
LMG1
CFD8
LMG0
CFD7
RM1
CFD6
X
CFD5
X
CFD4
X
CFD3
CFD2
CFD1
CFD0
0x0000
0x8000
Mixer ADC,
Volume
RMG3
RMG2
RMG1
RMG0
0x72
Jack Sense
X
X
X
JS MT2
JS
MT1
JS
MT0
JS1
EQB
JS0
EQB
JS1
TMR
JS0
TMR
JS1
MD
JS0
MD
JS1
ST
JS0 ST
JS1
INT
JS0
INT
0x0000
0x74
0x76
Serial Config
SLOT 16
DACZ
REGM 2
X
REGM 1
MSPLT
REGM 0
LODIS
X
X
X
X
CHEN
X
X
X
X
X
INTS
X
SPAL
SPDZ
SPLNK
MBG0
0x7001
0x0000
Misc Control
Bit
DAM
FMXE
MAD
PD
2CMIC
MAD
ST
VREFH
VREFD
MBG1
0x7C
0x7E
Vendor ID1
Vendor ID2
F7
T7
F6
T6
F5
T5
F4
T4
F3
T3
F2
T2
F1
T1
F0
T0
S7
S6
S5
S4
S3
S2
S1
S0
0x4144
0x5374
REV7
REV6
REV5
REV4
REV3
REV2
REV1
REV0
All registers are not shown. Bits containing an X are assumed to be reserved.
Odd register addresses are aliased to the next lower even address.
Reserved registers should not be written.
Zeros should be written to reserved bits.
1 For AC ‘97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, the RM bit has no effect.
Rev. A | Page 12 of 32
AD1981BL
CONTROL REGISTER DETAILS
RESET REGISTER
Index 0x00
Reg No.
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
Reset
X
SE4
SE3
SE2
SE1
SE0
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
0x0090
X is a wild card, and has no effect on the value.
Writing any value to this register performs a register reset that causes all registers to revert to their default values (except 0x74, which forces the serial configuration).
Reading this register returns the ID code of the part and a code for the type of 3D stereo enhancement.
ID[9:0] Identify Capability. The ID decodes the capabilities of AD1981BL based on the functions listed in Table 9.
Table 9. ID Bits
Bit
Function
AD1981B
ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7
ID8
ID9
Dedicated MIC PCM in Channel
Modem Line Codec Support
Bass and Treble Control
Simulated Stereo (Mono to Stereo)
Headphone Out Support
Loudness (Bass Boost) Support
18-Bit DAC Resolution
20-Bit DAC Resolution
18-Bit ADC Resolution
20-Bit ADC Resolution
0
0
0
0
1
0
0
1
0
0
MASTER VOLUME REGISTER
Index 0x02
This register controls the Line_Out volume controls for both stereo channels and the mute bit. Each volume subregister contains five bits,
generating 32 volume levels with 31 steps of 1.5 dB each. Because AC ’97 defines 6-bit volume registers, to maintain compatibility
whenever the D5 or D13 bits are set to 1, their respective lower five volume bits are automatically set to 1 by the codec logic. On readback,
all lower five bits read 1s whenever these bits are set to 1. Refer to Table 12 for examples.
Reg No.
Name
D15 D14 D13 D12
D11
D10
D9
D8
D7
D6 D5 D4
D3
D2
D1
D0
Default
0x02
Master
MM
X
X
LMV4 LMV3 LMV2 LMV1 LMV0 RM1
X
X
RMV4 RMV3 RMV2 RMV1 RMV0 0x8000
Volume
1 For AC ‘97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, the RM bit has no effect.
All registers are not shown, and bits containing an X are assumed to be reserved.
Table 10.
Bit
Mnemonic
Function
RMV [4:0]
Right Master Volume The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum
Control
attenuation of 46.5 dB.
RM
Right-Channel Mute
Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately from the
MM bit. Otherwise, this bit always reads 0 and has no effect when set to 1.
LMV [4:0]
MM
Left Master Volume
Control
The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum
attenuation of 46.5 dB.
Master Volume Mute When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in
Register 0x76 is set to 1, in which case this mute bit affects only the left channel.
Rev. A | Page 13 of 32
AD1981BL
HEADPHONE VOLUME REGISTER
Index 0x04
This register controls the headphone volume controls for both stereo channels and the mute bit. Each volume subregister contains five
bits, generating 32 volume levels with 31 steps of 1.5 dB each. Because AC ’97 defines 6-bit volume registers, to maintain compatibility,
whenever the D5 or D13 bits are set to 1, their respective lower five volume bits are automatically set to 1 by the codec logic. On readback,
all lower five bits read 1s whenever these bits are set to 1. Refer to Table 12 for examples.
Reg
No.
Name
D15
D14 D13
D12
D11
D10
D9
D8
D7
RM1
D6 D5 D4
RHV4
D3
D2
D1
D0
Default
0x04 Headphone
Volume
HPM
X
X
LHV4
LHV3
LHV2
LHV1
LHV0
X
X
RHV3
RHV2
RHV1
RHV0 0x8000
1 For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, the RM bit has no effect.
All registers are not shown, and bits containing an X are assumed to be reserved.
Table 11.
Bit
Mnemonic
Function
RHV [4:0]
Right Headphone
Volume Control
The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum
attenuation of 46.5 dB.
RM
Right-Channel Mute Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately from the
HPM bit. Otherwise, this bit always reads 0 and has no effect when set to 1.
LHV [4:0]
HPM
Left Headphone
Volume Control
The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum
attenuation of 46.5 dB.
Headphone Volume When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in
Mute Register 0x76 is set to 1, in which case this mute bit affects only the left channel.
Table 12. Volume Settings for Master and Headphone
Reg. 0x76
Control Bits Master Volume (0x02) and Headphone Volume (0x04)
Left-Channel Volume D [13:8] Right-Channel Volume D [5:0]
MSPLT1
D71
X
D15
Write
Readback
Function
Write
Readback
Function
0
0
0
0
0
1
1
1
0
0
0
0
1
0
1
1
00 0000
00 1111
01 1111
1X XXXX
XX XXXX
1X XXXX
XX XXXX
XX XXXX
00 0000
00 1111
01 1111
01 1111
XX XXXX
01 1111
XX XXXX
XX XXXX
0 dB Gain
00 0000
00 1111
01 1111
00 0000
00 1111
01 1111
0 dB Gain
−22.5 dB Gain
X
−22.5 dB Gain
−46.5 dB Gain
X
−46.5 dB Gain
−46.5 dB Gain
X
1X XXXX 01 1111
XX XXXX XX XXXX
XX XXXX XX XXXX
XX XXXX XX XXXX
XX XXXX XX XXXX
−46.5 dB Gain
−∞ dB Gain, Muted
−46.5 dB Gain
X
−∞ dB Gain, Muted
−∞ dB Gain, Right Only Muted
−46.5 dB Gain
1
−∞ dB Gain, Left Only Muted
−∞ dB Gain, Left Muted
0
1
−∞ dB Gain, Right Muted
1 For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, the RM bit has no effect.
X is a wild card, and has no effect on the value.
Rev. A | Page 14 of 32
AD1981BL
MONO VOLUME REGISTER
Index 0x06
This register controls the mono output volume and mute bit. The volume register contains five bits, generating 32 volume levels with
31 steps of 1.5 dB each. Because AC ’97 defines 6-bit volume registers, to maintain compatibility, whenever the D5 bit is set to 1, their
respective lower five volume bits are automatically set to 1 by the codec logic. On readback, all lower five bits read 1s whenever this bit is
set to 1. Refer to Table 14 for examples.
Reg No.
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x06
Mono Volume
MVM
X
X
X
X
X
X
X
X
X
X
MV4
MV3
MV2
MV1
MV0
0x8000
All registers are not shown, and bits containing an X are assumed to be reserved.
Table 13.
Bit
Mnemonic
Function
MV [4:0]
Mono Volume Control The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum
attenuation of 46.5 dB.
MVM
Mono Volume Mute
When this bit is set to 1, the channel is muted.
Table 14. Volume Settings for Mono
Control Bits D [4:0] for Mono (0x06)
D15
Function
Write
Readback
0 0000
0 1111
1 1111
X XXXX
0
0
0
1
0 0000
0 1111
1 1111
X XXXX
0 dB Gain
−22.5 dB Gain
−46.5 dB Gain
−∞ dB Gain, Muted
An X is a wild card, and has no effect on the value.
PHONE VOLUME REGISTER
Index 0x0C
Reg No.
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x0C
Phone Volume
PHM
X
X
X
X
X
X
X
X
X
X
PHV4
PHV3
PHV2
PHV1
PHV0
0x8008
All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 17 for examples.
Table 15.
Bit
Mnemonic
Function
PHV [4:0]
Phone Volume
Allows setting the phone volume attenuator in 32 volume levels with 31 steps of 1.5 dB each. The
LSB represents 1.5 dB, and the gain range is +12 dB to −34.5 dB. The default value is 0 dB, with the
mute bit enabled.
PHM
Phone Mute
When this bit is set to 1, the phone channel is muted.
All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 17 for examples.
Rev. A | Page 15 of 32
AD1981BL
MIC VOLUME REGISTER
Index 0x0E
Reg No.
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x0E
MIC Volume
MCM
X
X
X
X
X
X
X
X
M20
X
MCV4
MCV3
MCV2
MCV1
MCV0
0x8008
All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 17 for examples.
Table 16.
Bit
Mnemonic
Function
MCV [4:0]
MIC Volume Gain
Allows setting the phone volume attenuator in 32 volume levels with 31 steps of 1.5 dB each. The LSB
represents 1.5 dB, and the gain range is +12 dB to −34.5 dB. The default value is 0 dB, with the mute bit
enabled.
M20
MIC Gain Boost
This bit allows setting additional MIC gain to increase the microphone sensitivity. The nominal gain
boost by default is 20 dB; however, Bits D0 and D1 (MBG [1:0]) on the miscellaneous control bits register
(0x76) allow changing the gain boost to 10 dB or 30 dB, if necessary.
0 = Disabled; Gain = 0 dB
1 = Enabled; Default Gain = 20 dB (see Register 0x76, Bits D0, D1)
MCM
MIC Mute
When this bit is set to 1, the MIC channel is muted.
Table 17. Volume Settings for Phone and MIC
Control Bits D [4:0] Phone (0x0C) and MIC (0x0E)
D15
Function
Write
Readback
0 0000
0 1000
1 1111
X XXXX
0
0
0
1
0 0000
0 1000
1 1111
X XXXX
12 dB Gain
0 dB Gain
−34.5 dB Gain
−∞ db Gain, Muted
X is a wild card, and has no effect on the value.
LINE-IN VOLUME REGISTER
Index 0x10
Reg No. Name
D15 D14 D13 D12
D11
D10
D9
D8
D7
D6 D5 D4
D3
D2
D1
D0
Default
0x10 Line-In Volume LVM
X
X
LLV4 LLV3 LLV2 LLV1 LLV0 RM1
X
X
RLV4 RLV3 RLV2 RLV1 RLV0 0x8808
1For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, the RM bit has no effect.
All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 22 for examples.
Table 18.
Bit
Mnemonic
Function
RLV [4:0]
Line-In Volume Right Allows setting the line-in right-channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and
the range is +12 dB to −34.5 dB. The default value is 0 dB, mute enabled.
RM
Right-Channel Mute
Line-In Volume Left
Line-In Mute
Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately from the
LM bit. Otherwise, this bit always reads 0 and has no effect when set to 1.
Allows setting the line-in left-channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and
the range is +12 dB to −34.5 dB. The default value is 0 dB, mute enabled.
When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in
Register 0x76 is set to 1, in which case this mute bit affects only the left channel.
LLV [4:0]
LVM
Rev. A | Page 16 of 32
AD1981BL
CD VOLUME REGISTER
Index 0x12
Reg No.
Name
D15
D14 D13 D12
D11
D10
D9
D8
D7
D6 D5 D4
D3
D2
D1
D0
Default
0x12
CD Volume
CVM
X
X
LCV4 LCV3 LCV2 LCV1 LCV0 RM1
X
X
RCV4 RCV3 RCV2 RCV1 RCV0 0x8808
1 For AC ‘97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, the RM bit has no effect.
All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 22 for examples.
Table 19.
Bit
Mnemonic
Function
RCV [4:0]
Right CD Volume
Allows setting the CD right-channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the
gain range is +12 dB to −34.5 dB. The default value is 0 dB, mute enabled.
RM
Right-Channel Mute
Left CD Volume
Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately from the
CVM bit. Otherwise, this bit always reads 0 and has no affect when set to 1.
Allows setting the CD left-channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the
gain range is +12 dB to −34.5 dB. The default value is 0 dB, mute enabled.
When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in
Register 0x76 is set to 1, in which case this mute bit affects only the left channel.
LCV [4:0]
CVM
CD Volume Mute
AUX VOLUME REGISTER
Index 0x16
Reg No. Name
D15 D14 D13 D12
D11
D1
D9
D8
D7
D6 D5 D4
D3
D2
D1
D0
Default
0x16 AUX Volume AM
X
X
LAV4 LAV3 LAV2 LAV1 LAV0 RM1
X
X
RAV4 RAV3 RAV2 RAV1 RAV0 0x8808
1 For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, the RM bit has no effect.
All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 22 for examples.
Table 20.
Bit
Mnemonic
Function
RAV [4:0]
Right AUX Volume
Allows setting the AUX right-channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and
the gain range is +12 dB to −34.5 dB. The default value is 0 dB, mute enabled.
RM
Right-Channel Mute
Left AUX Volume
AUX Volume Mute
Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately from the
AM bit. Otherwise, this bit always reads 0 and has no affect when set to 1.
Allows setting the AUX left-channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and
the gain range is +12 dB to −34.5 dB. The default value is 0 dB, mute enabled.
When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in
Register 0x76 is set to 1, in which case this mute bit affects only the left channel.
LAV [4:0]
AM
Rev. A | Page 17 of 32
AD1981BL
PCM-OUT VOLUME REGISTER
Index 0x18
Reg
No.
Name
D15 D14 D13 D12
D11
D10
D9
D8
D7
D6 D5 D4
D3
D2
D1
D0
Default
0x18
PCM-Out
Volume
OM
X
X
LOV4 LOV3 LOV2 LOV1 LOV0 RM1
X
X
ROV4 ROV3 ROV2 ROV1 ROV0 0x8808
1 For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, the RM bit has no effect.
All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 22 for examples.
Table 21.
Bit
Mnemonic
Function
ROV [4:0]
Right PCM-Out Volume
Allows setting the PCM right-channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and
the range is +12 dB to −34.5 dB. The default value is 0 dB, mute enabled.
RM
Right-Channel Mute
Left PCM-Out Volume
PCM-Out Volume Mute
Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately from
the OM bit. Otherwise, this bit always reads 0 and has no effect when set to 1.
Allows setting the PCM left-channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and
the range is +12 dB to −34.5 dB. The default value is 0 dB, mute enabled.
When this bit is set to 1, both the left and right channels are muted unless the MSPLT bit in
Register 0x76 is set to 1, in which case this mute bit affects only the left channel.
LOV [4:0]
OM
Table 22. Volume Settings for Line-In, CD Volume, AUX, and PCM-Out
Control Bits
Line-In (0x10), CD (0x12), AUX (0x16), and PCM-Out (0x18)
Left-Channel Volume D [12:8] Right-Channel Volume D [4:0]
Reg. 0x76
MSPLT1
D15
Write
Readback
0 0000
0 1000
Function
12 dB Gain
0 dB Gain
+34.5 dB
Gain
D71
Write
Readback
0 0000
0 1000
Function
12 dB Gain
0 dB Gain
−34.5 dB
Gain
0
0
0
0
0
0
0 0000
0 1000
1 1111
X
X
X
0 0000
0 1000
1 1111
1 1111
1 1111
0
1
1
0
X XXXX
1 1111
X XXXX
1 1111
−∞ dB Gain,
Muted
−34.5 dB
Gain
X
1
X XXXX
X XXXX
X XXXX
X XXXX
−∞ dB Gain,
Muted
−∞ dB Gain,
Right Only
Muted
1
1
1
1
X XXXX
X XXXX
X XXXX
X XXXX
−∞ dB Gain,
Left Only
Muted
−∞ dB Gain,
Left Muted
0
1
1 1111
1 1111
−34.5 dB
Gain
X XXXX
X XXXX
−∞ dB Gain,
Right Muted
1 For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, the RM bit has no effect.
X is a wild card, and has no effect on the value.
Rev. A | Page 18 of 32
AD1981BL
RECORD SELECT CONTROL REGISTER
Index 0x1A
Reg No.
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x1A
Record Select
X
X
X
X
X
LS2
LS1
LS0
X
X
X
X
X
RS2
RS1
RS0
0x0000
Used to select the record source independently for right and left. The default value is 0x0000, which corresponds to MIC In. Refer to Table 24 for examples.
All registers are not shown, and bits containing an X are assumed to be reserved.
Table 23.
Bit
Function
RS [2:0]
LS [2:0]
Right Record Select
Left Record Select
Table 24. Settings for Record Select Control
LS [10:8]
Left Record Source
RS [2:0]
000
Right Record Source
MIC
000
MIC
001
CD_L
001
CD_R
010
Muted
010
Muted
011
AUX_L
011
AUX_R
100
101
110
111
LINE_IN_L
Stereo Mix (L)
Mono Mix
PHONE_IN
100
101
110
111
LINE_IN_R
Stereo Mix (R)
Mono Mix
PHONE_IN
RECORD GAIN REGISTER
Index 0x1C
Reg No.
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
RM1
D6
D5
D4
D3
D2
D1
D0
Default
0x1C
Record Gain
IM
X
X
X
LIM3
LIM2
LIM1
LIM0
X
X
X
RIM3
RIM2
RIM1
RIM0
0x8000
1 For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, the RM bit has no effect.
All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 24 for examples.
Table 25.
Bit
Mnemonic
Function
RIM [3:0] Right Input Mixer Gain Each LSB represents 1.5 dB, 0000 = 0 dB, and the gain range is 0 dB to 22.5 dB.
Control
RM
Right-Channel Mute
Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately from the
IM bit. Otherwise, this bit always reads 0 and has no affect when set to 1.
LIM [3:0] Left Input Mixer Gain
Control
Each LSB represents 1.5 dB, 0000 = 0 dB, and the gain range is 0 dB to 22.5 dB.
IM
Input Mute
When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in
Register 0x76 is set to 1, in which case this mute bit affects only the left channel.
Rev. A | Page 19 of 32
AD1981BL
Table 26. Settings for Record Gain Register
Reg. 0x76
Control Bits Record Gain (1Channel)
Left-Channel Input Mixer D [11:8] Right-Channel Input Mixer D [3:0]
MSPLT1
D15
Write
1111
0000
XXXX
Readback
1111
0000
Function
D71
X
X
X
Write
1111
0000
XXXX
Readback
1111
0000
Function
0
0
0
0
0
1
22.5 dB Gain
0 dB Gain
−∞ dB Gain,
Muted
22.5 dB Gain
0 dB Gain
−∞ dB Gain,
Muted
XXXX
XXXX
1
1
1
0
1
1
1111
XXXX
XXXX
1111
XXXX
XXXX
22.5 dB Gain
1
0
1
XXXX
1111
XXXX
XXXX
1111
XXXX
−∞ dB Gain,
Right Only
Muted
−∞ dB Gain,
Left Only
Muted
−∞ dB Gain,
Left Muted
22.5 dB Gain
−∞ dB Gain,
Right Muted
1 For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, the RM bit has no effect.
X is a wild card, and has no effect on the value.
GENERAL-PURPOSE REGISTER
Index 0x20
Reg No.
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x20
General-Purpose
X
X
X
X
X
X
MIX
MS
LPBK
X
X
X
X
X
X
X
0x0000
This register should be read before writing to generate a mask for only the bit(s) that need to be changed.
All registers are not shown, and bits containing an X are assumed to be reserved.
Table 27.
Bit
Mnemonic
Function
LPBK
Loopback Control
ADC/DAC Digital Loopback Mode.
0 = No Loopback (default).
1 = Loopback PCM Digital Data from ADC Output to DAC.
MS
MIC Select
Selects mono MIC input.
0 = Select MIC1.
1 = Select MIC2.
See the 2CMIC bit in Register 0x76 to enable stereo microphone recording.
Selects mono output audio source.
MIX
Mono Output Select
0 = Mixer Mono Output (reset default).
1 = MIC1 Channel.
Rev. A | Page 20 of 32
AD1981BL
POWER-DOWN CONTROL/STATUS REGISTER
Index 0x26
Reg No.
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7 D6 D5 D4 D3
D2
D1
D0
Default
0x26
Power-Down Ctrl/Stat
EAPD
PR6
PR5
PR4
PR3
PR2
PR1 PR0
X
X
X
X
REF ANL DAC
ADC 0x000X
The ready bits are read-only; writing to REF, ANL, DAC, ADC has no effect. These bits indicate the status for the AD1981BL subsections. If the bit is a 1, that subsection
is ready. Ready is defined as the subsection able to perform in its nominal state.
All registers are not shown, and bits containing an X are assumed to be reserved.
Table 28.
Bit
Mnemonic
Function
ADC
DAC
ANL
REF
ADC Sections Ready to Transmit Data.
DAC Sections Ready to Accept Data.
Analog Amplifiers, Attenuators, and Mixers Ready.
Voltage References, VREF and VREFOUT, Up to Nominal Level.
PR [6:0]
Codec Power-
Down Modes
The first three bits are to be used individually rather than in combination with each other. PR3 can be
used in combination with PR2 or by itself. The mixer and reference cannot be powered down via PR3
unless the ADCs and DACs are also powered down.
Nothing else can be powered up until the reference is powered up. PR5 has no effect unless all ADCs,
DACs, and the ac-link are powered down. The reference and the mixer can be either powered up or
powered down, but all power-up sequences must be allowed to run to completion before PR5 and PR4
are both set.
In multiple codec systems, the master codec’s PR5 and PR4 bits control the slave codec. PR5 is also
effective in the slave codec, if the master’s PR5 bit is clear, but the PR4 bit has no effect except to enable or
disable PR5.
EAPD
External Audio
Power-Down
Control
Controls the state of the EAPD pin.
EAPD = 0 sets the EAPD pin low, enabling an external power amplifier (reset default).
EAPD = 1 sets the EAPD pin high, shutting the external power amplifier off.
Table 29.
Power-Down State
Set Bits
PR [6:0]
ADCs and Input MUX Power-Down
DACs Power-Down
Analog Mixer Power-Down (VREF and VREFOUT On)
Analog Mixer Power-Down (VREF and VREFOUT Off)
AC-Link Interface Power-Down
Internal Clocks Disabled
ADC and DAC Power-Down
VREF Standby Mode
Total Power-Down
PR0
PR1
PR1, PR2
PR0, PR1, PR3
[000 0001]
[000 0010]
[000 0101]
[000 1011]
[001 0000]
[011 0011]
[000 0011]
[011 0111]
[111 1111]
[100 0000]
PR4
PR0, PR1, PR4, PR5
PR0, PR1
PR0, PR1, PR2, PR4, PR5
PR0, PR1, PR2, PR3, PR4, PR5, PR6
PR6
Headphone Amp Power-In Standby
Rev. A | Page 21 of 32
AD1981BL
EXTENDED AUDIO ID REGISTER
Index 0x28
Reg No. Name
D15
D14
D13 D12 D11
D10
D9
D8 D7 D6 D5
D4
D3 D2
SPDIF
D1 D0
Default
0x28 Ext’d Audio ID IDC1 IDC0
X
X
REVC1 REVC0 AMAP
X
X
X
DSA1 DSA0
X
X VRAS 0xX605
The extended audio ID register identifies which extended audio features are supported. A nonzero extended audio ID value indicates that one or more of the
extended audio features are supported.
All registers are not shown, and bits containing an X are assumed to be reserved.
Table 30.
Bit
Mnemonic
Function
VRAS
Variable Rate PCM Audio
Support (Read-Only)
This bit returns a 1 when Read To indicates that the variable rate PCM audio is supported.
SPDIF
SPDIF Support (Read-Only)
This bit returns a 1 when Read To indicates that the SPDIF transmitter is supported (IEC958).
This bit is also used to validate that the SPDIF transmitter output is enabled. The SPDIF bit can
be set high only if the SPDIF pin (Pin 48) is pulled down at power-up, enabling the codec
transmitter logic. If the SPDIF pin is floating or pulled high at power-up, the transmitter logic
is disabled; therefore, this bit returns a low, indicating that the SPDIF transmitter is not
available. This bit must always be read back to verify that the SPDIF transmitter is actually
enabled.
DSA [1:0]
AMAP
DAC Slot Assignments
(Read/Write)
Reset default = 00.
00 DACs 1, 2 = 3 and 4.
01 DACs 1, 2 = 7 and 8.
10 DACs 1, 2 = 6 and 9.
11 Reserved.
Slot DAC Mappings Based
on Codec ID (Read-Only)
This bit returns a 1 when read to indicate that slot/DAC mappings based on the codec ID are
supported.
REVC [1:0]
IDC [1:0]
AC ’97 Revision Compliance
Indicates Codec
REVC [1:0] = 01 indicates that the codec is AC ’97 revision 2.2-compliant (read-only).
00 = Primary.
Configuration (Read-Only)
01, 10, 11 = Secondary.
EXTENDED AUDIO STATUS AND CONTROL REGISTER
Index 0x2A
Reg
No.
Name
D15
D14 D13 D12 D11 D10
SPCV
D9 D8 D7 D6 D5
D4
D3 D2
SPDIF
D1 D0
Default
0x2A
Ext’d Audio
Stat/Ctrl
VFORCE
X
X
X
X
X
X
X
X
SPSA1 SPSA0
X
X VRA 0x0000
The extended audio status and control register is a read/write register that provides status and control of the extended audio features.
All registers are not shown, and bits containing an X are assumed to be reserved.
Table 31.
Bit
Mnemonic
Function
VRA
Variable Rate Audio
(Read/Write)
VRA = 0 sets the fixed sample rate audio to 48 kHz (reset default).
VRA = 1 enables variable rate audio mode (enables sample rate registers and SLOTREQ
signaling).
SPDIF
SPDIF Transmitter
SPDIF = 1 enables the SPDIF transmitter.
Subsystem Enable/Disable
Bit (Read/Write)
SPDIF = 0 disables the SPDIF transmitter (default).
This bit is also used to validate that the SPDIF transmitter output is enabled. The SPDIF bit can
be set high only if the SPDIF pin (Pin 48) is pulled down at power-up, enabling the codec
transmitter logic. If the SPDIF pin is floating or pulled high at power-up, the transmitter logic is
disabled and this bit returns a low, indicating that the SPDIF transmitter is not available. This bit
must always be read back to verify that the SPDIF transmitter is enabled.
SPSA [1:0]
SPDIF Slot Assignment Bits These bits control the SPDIF slot assignment and respective defaults, depending on the codec
(Read/Write) ID configuration.
Rev. A | Page 22 of 32
AD1981BL
Bit
Mnemonic
Function
SPCV
SPDIF Configuration Valid
(Read-Only)
This bit indicates the status of the SPDIF transmitter subsystem, enabling the driver to
determine if the currently programmed SPDIF configuration is supported. SPCV is always valid,
independent of the SPDIF enable bit status.
SPCV = 0 indicates that the current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is not
valid (not supported).
SPCV = 1 indicates that the current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is valid
(supported).
VFORCE
Validity Force Bit
(Reset Default = 0)
When asserted, this bit forces the SPDIF stream validity flag (Bit 28 within each SPDIF L/R
subframe) to be controlled by the V bit (D15) in Register 0x3A (SPDIF control register).
VFORCE = 0 and V = 0; the validity bit is managed by the codec error detection logic.
VFORCE = 0 and V = 1; the validity bit is forced high, indicating the subframe data is invalid.
VFORCE = 1 and V = 0; the validity bit is forced low, indicating the subframe data is valid.
VFORCE = 1 and V = 1; the validity bit is forced high, indicating the subframe data is invalid.
Table 32. AC ’97 2.2 AMAP-Compliant Default SPDIF Slot Assignments
Codec ID
Function
SPSA = 00
3 and 4
3 and 4
3 and 4
3 and 4
3 and 4
3 and 4
3 and 4
3 and 4
SPSA = 01
7 and 8 (default)
7 and 8
7 and 8
7 and 8
7 and 8
7 and 8
7 and 8
7 and 8
SPSA = 10
6 and 9
6 and 9 (default)
6 and 9
6 and 9 (default)
6 and 9
6 and 9 (default)
6 and 9
SPSA = 11
00
00
00
01
01
10
10
11
2-Channel Primary w/SPDIF
4-Channel Primary w/SPDIF
6-Channel Primary w/SPDIF
+2-Channel Secondary w/SPDIF
+4-Channel Secondary w/SPDIF
+2-Channel Secondary w/SPDIF
+4-Channel Secondary w/SPDIF
+2-Channel Secondary w/SPDIF
10 and 11
10 and 11
10 and 11 (default)
10 and 11 (default)
10 and 11 (default)
10 and 11 (default)
6 and 9
PCM FRONT DAC RATE REGISTER
Index 0x2C
Reg
No.
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x2C PCM
Front
SRF15 SRF14 SRF13 SRF12 SRF11 SRF10 SRF9 SRF8 SRF7 SRF6 SRF5 SRF4 SRF3 SRF2 SRF1 SRF0 0xBB80
DAC
Rate
This read/write sample rate control register contains a 16-bit unsigned value, representing the rate of operation in Hz.
Table 33.
Bit
Mnemonic
Function
SRF [15:0]
Sample Rate
The sampling frequency range is from 7 kHz (0x1B58) to 48 kHz (0xBB80) in 1 Hz increments. If 0 is written to
VRA, the sample rate is reset to 48 kHz.
PCM ADC RATE REGISTER
Index 0x32
Reg
No.
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x32
PCM L/R
ADC
SRA15
SRA14
SRA13
SRA12
SRA11
SRA10
SRA9
SRA8
SRA7
SRA6
SRA5
SRA4
SRA3
SRA2
SRA1
SRA0
0xBB80
Rate
This read/write sample rate control register contains a 16-bit unsigned value, representing the rate of operation in Hz.
Table 34.
Bit
Mnemonic
Function
SRA [15:0]
Sample Rate
The sampling frequency range is from 7 kHz (0x1B58) to 48 kHz (0xBB80) in 1 Hz increments. If 0 is written to
VRA, the sample rate is reset to 48 kHz.
Rev. A | Page 23 of 32
AD1981BL
SPDIF CONTROL REGISTER
Index 0x3A
Reg No.
Name
D15 D14 D13
D12
D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x3A
SPDIF Control
V
X
SPSR1 SPSR0
L CC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE COPY AUD
PRO 0x2000
Register 0x3A is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or subframe in the V case). With the
exception of V, this register should be written to only when the SPDIF transmitter is disabled (SPDIF bit in Register 0x2A is 0). This ensures that control and status
information start up correctly at the beginning of SPDIF transmission.
Table 35.
Bit
Mnemonic
Function
PRO
Professional
1 = Professional use of channel status.
0 = Consumer.
AUD
COPY
PRE
Nonaudio
1 = Data is non-PCM format.
0 = Data is PCM format.
1 = Copyright is asserted.
0 = Copyright is not asserted.
1 = Filter pre-emphasis is 50 µs/15 µs.
0 = Pre-emphasis is none.
Copyright
Pre-emphasis
CC [6:0]
L
SPSR [1:0]
Category Code
Generation Level
SPDIF Transmit
Sample Rate
Programmed according to IEC standards, or as appropriate.
Programmed according to IEC standards, or as appropriate.
SPSR [1:0] = 00: Transmit sample rate is 44.1 kHz.
SPSR [1:0] = 01: Reserved.
SPSR [1:0] = 10: Transmit sample rate is 48 kHz (reset default).
SPSR [1:0] = 11: Not supported.
V
Validity
This bit affects the validity flag (Bit 28 transmitted in each SPDIF L/R subframe) and enables the SPDIF
transmitter to maintain connection during error or mute conditions.
V = 1: Each SPDIF subframe (L + R) has Bit 28 set to 1. This tags both samples as invalid.
V = 0: Each SPDIF subframe (L + R) has Bit 28 set to 0 for valid data and 1 for invalid data (error
condition).
When V = 0, asserting the VFORCE bit (D15) in Register 0x2A (Ext’d Audio Stat/Ctrl) forces the validity
flag low, marking both samples as valid.
EQ CONTROL REGISTER
Index 0x60
Reg No. Name
0x60 EQ Ctrl
D15
D14
D13 D12 D11 D10 D9 D8 D7
D6
D5
D4
D3
D2
D1
D0
Default
EQM MAD LBEN
X
X
X
X
X
X
SYM CHS BCA5 BCA4 BCA3 BCA2 BCA1 BCA0 0x8080
Register 0x60 is a read/write register that controls the equalizer functionality and data setup. This register contains the biquad and coefficient address pointer, which
is used in conjunction with the EQ data register (0x78) to set up the equalizer coefficients. The reset default disables the equalizer function until the coefficients can be
properly set up by the software and sets the symmetry bit to allow equal coefficients for left and right channels.
All registers are not shown, and bits containing an X are assumed to be reserved.
Table 36.
Bit
Mnemonic
Function
BCA [5:0]
Biquad and Coefficient
Address Pointer
biquad 0 coef a0 BCA[5:0] = 011011
biquad 0 coef a1 BCA[5:0] = 011010
biquad 0 coef a2 BCA[5:0] = 011001
biquad 0 coef b1 BCA[5:0] = 011101
biquad 0 coef b2 BCA[5:0] = 011100
biquad 1 coef a0 BCA[5:0] = 100000
biquad 1 coef a1 BCA[5:0] = 011111
Rev. A | Page 24 of 32
AD1981BL
Bit
Mnemonic
Function
biquad 1 coef a2 BCA[5:0] = 011110
biquad 1 coef b1 BCA[5:0] = 100010
biquad 1 coef b2 BCA[5:0] = 100001
biquad 2 coef a0 BCA[5:0] = 100101
biquad 2 coef a1 BCA[5:0] = 100100
biquad 2 coef a2 BCA[5:0] = 100011
biquad 2 coef b1 BCA[5:0] = 100111
biquad 2 coef b2 BCA[5:0] = 100110
biquad 3 coef a0 BCA[5:0] = 101010
biquad 3 coef a1 BCA[5:0] = 101001
biquad 3 coef a2 BCA[5:0] = 101000
biquad 3 coef b1 BCA[5:0] = 101100
biquad 3 coef b2 BCA[5:0] = 101011
biquad 4 coef a0 BCA[5:0] = 101111
biquad 4 coef a1 BCA[5:0] = 101110
biquad 4 coef a2 BCA[5:0] = 101101
biquad 4 coef b1 BCA[5:0] = 110001
biquad 4 coef b2 BCA[5:0] = 110000
biquad 5 coef a0 BCA[5:0] = 110100
biquad 5 coef a1 BCA[5:0] = 110011
biquad 5 coef a2 BCA[5:0] = 110010
biquad 5 coef b1 BCA[5:0] = 110110
biquad 5 coef b2 BCA[5:0] = 110101
biquad 6 coef a0 BCA[5:0] = 111001
biquad 6 coef a1 BCA[5:0] = 111000
biquad 6 coef a2 BCA[5:0] = 110111
biquad 6 coef b1 BCA[5:0] = 111011
biquad 6 coef b2 BCA[5:0] = 111010
CHS
SYM
Channel Select
Symmetry
CHS = 0 selects the left-channel coefficient’s data block.
CHS = 1 selects the right-channel coefficient’s data block.
When set to 1, this bit indicates that the left- and right-channel coefficients are equal. This
shortens the coefficients’ setup sequence, because only the left-channel coefficients need to be
addressed and set up. The right-channel coefficients are fetched from the left-channel memory.
MAD
LBEN
Mixer ADC Loopback
Enable
Enables mixer ADC data to be summed into the PCM stream.
0 = No loopback allowed (default).
1 = Enable loopback.
EQM
Equalizer Mute
When set to 1, this bit disables the equalizer function (allows all data to pass through). The reset
default sets this bit to 1, disabling the equalizer function until the biquad coefficients can be
properly set.
Rev. A | Page 25 of 32
AD1981BL
EQ DATA REGISTER
Index 0x62
Reg
No.
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x62
EQ
Data
CFD15
CFD14
CFD13
CFD12
CFD11
CFD10
CFD9
CFD8
CFD7
CFD6
CFD5
CFD4
CFD3
CFD2
CFD1
CFD0
0x0000
This read/write register is used to transfer EQ biquad coefficients into memory. The register data is transferred to, or retrieved from, the address pointed to by the BCA
bits in the EQ Cntrl Register (0x60). Data is written to memory only if the EQM bit (Register 0x60, Bit 15) is asserted.
Table 37.
Bit
Mnemonic
Function
CFD [15:0]
Coefficient Data
The biquad coefficients are fixed-point format values with 16 bits of resolution. The CFD15 bit is
the MSB, and the CFD0 bit is the LSB.
MIXER ADC, INPUT GAIN REGISTER
Index 0x64
Reg
No.
Name
D15
D14 D13 D12 D11
D10
D9
D8
D7
D6 D5 D4 D3
D2
D1
D0
Default
0x64
Mixer ADC,
Volume
MXM
X
X
X
LMG3 LMG2 LMG1 LMG0 RM1
X
X
X
RMG3 RMG2 RMG1 RMG0 0x8000
1 For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, the RM bit has no effect.
All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 39 for examples.
Table 38.
Bit
Mnemonic
Function
RMG [3:0]
Right Mixer Gain
Control
This register controls the gain into the mixer ADC from 0 dB to a maximum gain of 22.5 dB. The
least significant bit represents 1.5 dB.
RM
Right-Channel Mute
Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately from
the MXM bit. Otherwise, this bit always reads 0 and has no affect when set to 1.
LMG [3:0]
MXM
Left Mixer Gain Control
This register controls the gain into the mixer ADC, from 0 dB to a maximum gain of 22.5 dB. The
least significant bit represents 1.5 dB.
0 = Unmuted.
Mixer Gain Register
Mute
1 = Muted (reset default).
Table 39. Settings for Mixer ADC, Input Gain
Reg. 0x76
Control Bits Mixer ADC, Input Gain (0x64)
Left-Channel Mixer Gain D [11:8] Right-Channel Mixer Gain D [3:0]
MSPLT1
D15 Write
Readback
1111
Function
D71 Write
Readback
1111
Function
0
0
0
1
1
1
0
0
1
0
1
1
1111
0000
XXXX
1111
XXXX
XXXX
22.5 dB Gain
X
X
X
1
0
1
1111
0000
XXXX
XXXX
1111
XXXX
22.5 dB Gain
0000
0 dB Gain
0000
0 dB Gain
XXXX
1111
XXXX
XXXX
−∞ dB Gain, Muted
22.5 dB Gain
−∞ dB Gain, Left Only Muted
−∞ dB Gain, Left Muted
XXXX
XXXX
1111
−∞ dB Gain, Muted
−∞ dB Gain, Right Only Muted
22.5 dB Gain
XXXX
−∞ dB Gain, Right Muted
1 For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, the RM bit has no effect.
X is a wild card, and has no effect on the value.
Rev. A | Page 26 of 32
AD1981BL
JACK SENSE/AUDIO INTERRUPT/STATUS REGISTER
Index 0x72
Reg
No.
Name
D15 D14 D13 D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x72
Jack
Sense
X
X
X
JS
MT2
JS
MT1
JS
MT0
JS1
EQB
JS0
EQB
JS1
TMR
JS0
TMR
JS1
MD
JS0
MD
JS1
ST
JS0
ST
JS1
INT
JS0
INT
0x0000
All register bits are read/write except for JS0ST and JS1ST, which are read-only.
All registers are not shown, and bits containing an X are assumed to be reserved.
Table 40.
Bit
Mnemonic
Function
JS0INT
JS0 Interrupt
This bit indicates that Pin JS0 has generated an interrupt. This bit remains set until the software
services the JS0 interrupt, that is, JS0 ISR should clear this bit by writing a 0 to it.
The interrupt to the system is an OR combination of this bit and JS1INT.
The actual interrupt implementation is selected by the INTS bit (Register 0x76). It is also possible to
generate a software system interrupt by writing a 1 to this bit.
JS1INT
JS1 Interrupt
This bit indicates that Pin JS1 has generated an interrupt. This bit remains set until the software
services the JS1 interrupt, that is, JS1 ISR should clear this bit by writing a 0 to it. See the JS0INT
description for details.
JS0ST
JS1ST
JS0MD
JS0 State
JS1 State
JS0 Mode
This bit always reports the logic state of the JS0 pin.
This bit always reports the logic state of the JS1 pin.
This bit selects the operation mode for the JS0 pin.
0 = Jack sense mode (default).
1 = Interrupt mode.
JS1MD
JS1 Mode
This bit selects the operation mode for the JS1 pin.
0 = Jack sense mode (default).
1 = Interrupt mode.
JS0TMR
JS1TMR
JS0EQB
JS0 Timer Enable
JS1 Timer Enable
JS0 EQ Bypass Enable
If this bit is set to 1, JS0 must be high for >278 ms to be recognized.
If this bit is set to 1, JS1 must be high for >278 ms to be recognized.
This bit enables JS0 to control the EQ bypass. When this bit is set to 1, JS0 = 1 causes the EQ to be
bypassed.
JS1EQB
JS1 EQ Bypass Enable
This bit enables JS1 to control the EQ bypass. When this bit is set to 1, JS1 = 1 causes the EQ to be
bypassed.
JSMT [2:0]
JS Mute Enable
Selector
These three bits select and enable the jack sense muting action (see Table 41).
Rev. A | Page 27 of 32
AD1981BL
Table 41. Jack Sense Mute Select—JSMT [2:0]
JS1
JS0
Ref Headphone
LINE_OUT JSMT2 JSMT1 JSMT0 HP_OUT
LINE_OUT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FMUTE
MONO_OUT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Notes
0
1
2
3
4
OUT (0)
OUT (0)
IN (1)
OUT (0)
IN (1)
OUT (0)
IN (1)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FMUTE
JS0 and JS1 ignored.
IN (1)
OUT (0)
OUT (0)
ACTIVE
JS0 no mute action;
JS1 mutes Line_Out.
5
6
7
8
OUT (0)
IN (1)
IN (1)
IN (1)
OUT (0)
IN (1)
0
0
0
0
0
0
0
1
1
1
1
0
FMUTE
ACTIVE
ACTIVE
FMUTE
ACTIVE
FMUTE
FMUTE
FMUTE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
OUT (0)
OUT (0)
JS0 no mute action;
JS1 mutes Mono and
Line-Out.
9
OUT (0)
IN (1)
IN (1)
IN (1)
OUT (0)
IN (1)
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
FMUTE
ACTIVE
ACTIVE
**
**
**
ACTIVE
FMUTE
FMUTE
**
**
**
ACTIVE
FMUTE
FMUTE
**
**
**
10
11
12
13
14
15
16
OUT (0)
OUT (0)
IN (1)
OUT (0)
IN (1)
OUT (0)
IN (1)
** Reserved.
IN (1)
**
**
**
OUT (0)
OUT (0)
FMUTE
FMUTE
ACTIVE
JS0 mutes Mono;
JS1 no mute action.
17
18
19
20
OUT (0)
IN (1)
IN (1)
IN (1)
OUT (0)
IN (1)
1
1
1
1
0
0
0
0
0
0
0
1
FMUTE
ACTIVE
ACTIVE
FMUTE
ACTIVE
FMUTE
ACTIVE
FMUTE
FMUTE
ACTIVE
FMUTE
ACTIVE
OUT (0)
OUT (0)
JS0 mutes Mono;
JS1 mutes Line-Out.
21
22
23
24
OUT (0)
IN (1)
IN (1)
IN (1)
OUT (0)
IN (1)
1
1
1
1
0
0
0
1
1
1
1
0
FMUTE
ACTIVE
ACTIVE
FMUTE
ACTIVE
FMUTE
FMUTE
FMUTE
FMUTE
ACTIVE
FMUTE
ACTIVE
OUT (0)
OUT (0)
JS0 mutes Mono;
JS1 mutes Mono and
Line-Out.
25
26
27
28
29
30
31
OUT (0)
IN (1)
IN (1)
IN (1)
OUT (0)
IN (1)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
FMUTE
ACTIVE
ACTIVE
**
**
**
ACTIVE
FMUTE
FMUTE
**
**
**
FMUTE
FMUTE
FMUTE
**
**
**
OUT (0)
OUT (0)
IN (1)
OUT (0)
IN (1)
OUT (0)
IN (1)
** Reserved.
IN (1)
**
**
**
FMUTE = Output is forced to mute independent of the respective volume register setting.
ACTIVE = Output is not muted, and its status is dependent on the respective volume register setting.
OUT = Nothing plugged into the jack and, therefore, the JS status is low (via the load resistor pull-down).
IN = Jack has plug inserted and, therefore, the JS status is high (via the codec JS internal pull-up).
Rev. A | Page 28 of 32
AD1981BL
SERIAL CONFIGURATION REGISTER
Index 0x74
Reg No. Name
D15
D14
D13
D12
D11 D10 D9 D8
CHEN
D7 D6 D5 D4
INTS
D3 D2
D1
D0
Default
0x74
Serial
SLOT16 REGM2 REGM1 REGM0
X
X
X
X
X
X
X
SPAL SPDZ SPLNK 0x7001
Config
This register is not reset when the reset register (Register 0x00) is written.
All registers are not shown, and bits containing an X are assumed to be reserved.
Table 42.
Bit
Mnemonic
Function
SPLNK
SPDIF Link
This bit enables the SPDIF to link with the DAC for data requests.
0 = SPDIF and DAC are not linked.
1 = SPDIF and DAC are linked and receive the same data requests (reset default).
0 = Repeat last sample out of the SPDIF stream if FIFO underruns (reset default).
1 = Forces midscale sample out the SPDIF stream if FIFO underruns.
0 = SPDIF transmitter is connected to the ac-link stream (reset default).
1 = SPDIF transmitter is connected to the digital ADC stream, not the ac-link.
This bit selects the JS interrupt implementation path.
SPDZ
SPAL
INTS
SPDIF DACZ
SPDIF ADC Loop-
Around
Interrupt Mode Select
0 = Bit 0 Slot 12 (modem interrupt).
1 = Slot 6 valid bit (MIC ADC interrupt).
CHEN
Chain Enable
This bit enables chaining of a slave codec SDATA_IN stream into the ID0 pin (Pin 45).
0 = Disable chaining (reset default).
1 = Enable chaining into ID0 pin.
REGM0
REGM1
REGM2
SLOT16
Master Codec Register
Mask
Slave 1 Codec Register
Mask
Slave 2 Codec Register
Mask
Enable 16-Bit Slot Mode
Slot 16 makes all ac-link slots 16 bits in length, formatted into 16 slots. This is a preferred mode for
DSP serial port interfacing.
MISCELLANEOUS CONTROL BIT REGISTER
Index 0x76
Reg
No.
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x76
Misc
Control
Bit
DACZ
X
MSPLT
LODIS
DAM
X
FMXE
X
MADPD
2CMIC
X
MADST
VREFH
VREFD
MBG1
MBG0
0x0000
All registers are not shown, and bits containing an X are assumed to be reserved.
Table 43.
Bit
Mnemonic
Function
These two bits allow changing the MIC preamp gain from the nominal 20 dB gain.
This gain setting takes effect only while Bit D6 (M20) on the MIC volume register (0x0E) is set to 1;
otherwise, the MIC boost block has a gain of 0 dB.
MBG [1:0]
MIC Boost Gain Change
Register
00 = 20 dB gain (reset default).
01 = 10 dB gain.
10 = 30 dB gain.
11 = Reserved.
Rev. A | Page 29 of 32
AD1981BL
Bit
Mnemonic
Function
VREFD
VREFOUT Disable
This bit disables VREFOUT, placing it into high Z out mode. This bit overrides the VREFH bit selection.
0 = VREFOUT pin is driven by the internal reference (reset default).
1 = VREFOUT pin is placed into high Z out mode.
VREFH
VREFOUT High
0 = VREFOUT pin is set to 2.25 V output (reset default).
1 = VREFOUT pin is set to 2.25 V output (is set to 3.7 V only if AVDD = 5 V).
This bit indicates status of the mixer digitizing ADC (left and right channels).
0 = Mixer ADC not ready.
MADST
Mixer ADC Status Bit
1 = Mixer ADC ready.
2CMIC
2-Channel MIC Select
This bit enables simultaneous recording from MIC1 and MIC2 inputs for applications that use a
stereo microphone array. This register works in conjunction with the MS bit in Register 0x20.
0 = MIC1 or MIC2 (determined by the MS bit) is routed to the record selector’s left and right MIC
channels, as well as to the mixer (reset default).
1 = MIC1 is routed to the record selector’s left MIC channel and MIC2 is routed to the record
selector’s right MIC channel. In this mode, the MS bit should be set low, and MIC1 can still be
enabled into the mixer.
MADPD
FMXE
Mixer ADC Power-Down This bit controls power-down for mixer digitizing ADC.
0 = Mixer ADC is powered on (default).
1 = Mixer ADC is powered down.
Front DAC into Mixer
Enable
This bit controls the front (main) DAC to mixer mute switches.
0 = Front DAC outputs are allowed to sum into the mixer (reset default).
1 = Front DAC outputs are muted into the mixer (blocked).
DAM
LODIS
Digital Audio Mode
LINE_OUT Disable
PCM DAC outputs bypass the analog mixer and are sent directly to the codec output.
This bit disables the LINE_OUT pins (L/R), placing them into high Z mode so that the assigned
output audio jack can be shared for the input function (or other function).
0 = LINE_OUT pins have normal audio drive capability (reset default).
1 = LINE_OUT pins are placed into high Z mode.
MSPLT
DACZ
Mute Split
This bit allows separate mute control bits for the master, headphone, LINE_IN, CD, AUX, and PCM
volume control registers as well as for the record gain register.
0 = Both left- and right-channel mutes are controlled by Bit 15 in the respective registers (reset
default).
1 = Bit 15 affects only the left-channel mute, and Bit 7 affects only the right-channel mute.
This bit determines DAC data fill under starved conditions.
DAC Zero-Fill
0 = DAC data is repeated when DACs are starved for data (reset default).
1 = DAC is zero-filled when DACs are starved for data.
Rev. A | Page 30 of 32
AD1981BL
VENDOR ID REGISTERS
Index 0x7C–0x7E
Reg No.
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x7C
Vendor ID1
F7
F6
F5
F4
F3
F2
F1
F0
S7
S6
S5
S4
S3
S2
S1
S0
0x4144
S[7:0] This register is ASCII encoded to A.
F[7:0] This register is ASCII encoded to D.
Reg No.
Name
D15
D14
D13
D12
D11
T3
D10
T2
D9
D8
T0
D7
REV7
D6
REV6
D5
D4
REV4
D3
REV3
D2
REV2
D1
REV1
D0
Default
0x7E
Vendor ID2
T7
T6
T5
T4
T1
REV5
REV0
0x5374
T[7:0] This register is ASCII encoded to S.
REV[7:0] Vendor-specific revision number: The AD1981BL assigns 0x74 to this field.
Table 44. Codec ID and External Clock Selection
ID1
ID0
Codec ID
Codec Clocking Source
1
1
0
0
1
0
1
0
(00) Primary
(01) Secondary
(00) Primary
(00) Primary
24.576 MHz
12.288 MHz
48.000 MHz
14.31818 MHz
Local crystal or external into XTL_IN.
External into BIT_CLK.
External into XTL_IN.
External into XTL_IN.
Internally, the pins have weak pull-ups and are inverted.
ID
Rev. A | Page 31 of 32
AD1981BL
OUTLINE DIMENSIONS
0.75
0.60
0.45
9.00 BSC
SQ
1.60
MAX
37
48
36
1
PIN 1
7.00
BSC SQ
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
25
12
0.15
0.05
13
24
SEATING
PLANE
0.08 MAX
COPLANARITY
0.27
0.22
0.17
VIEW A
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026BBC
Figure 10. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD1981BLJST
AD1981BLJST-REEL
AD1981BLJSTZ1
AD1981BLJSTZ-REEL1
Temperature Range
Package Description
Package Option
ST-48
ST-48
ST-48
ST-48
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
1Z = Pb-free part. The AD1981BLJSTZ is a lead-free environmentally friendly product. It is manufactured using the most up-to-date materials and processes. The coating
on the leads of each device is 100% pure tin electroplate. The device is suitable for lead-free applications and can withstand surface-mount soldering at up to 255°C
( 5°C). In addition, it is backward compatible with conventional tin-lead soldering processes. This means that the electroplated tin coating can be soldered with tin-
lead solder pastes at reflow temperatures of 220°C to 235°C.
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04321–0–1/05(A)
Rev. A | Page 32 of 32
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