ADSP-2104_15 [ADI]
Low Cost DSP Microcomputers;
| 型号： | ADSP-2104_15 |
| 厂家： | 
ADI |
| 描述： | Low Cost DSP Microcomputers |
| 文件： | 总36页 (文件大小：335K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
a
Low Cost DSP Microcomputers
ADSP-2104/ADSP-2109
FUNCTIO NAL BLO CK D IAGRAM
SUMMARY
16-Bit Fixed-Point DSP Microprocessors w ith
On-Chip Mem ory
Enhanced Harvard Architecture for Three-Bus
Perform ance: Instruction Bus & Dual Data Buses
Independent Com putation Units: ALU, Multiplier/
Accum ulator, and Shifter
MEMORY
DATA ADDRESS
GENERATORS
PROGRAM
SEQUENCER
PROGRAM
MEMORY
DATA
MEMORY
DAG 2
DAG 1
EXTERNAL
ADDRESS
BUS
PROGRAM MEMORY ADDRESS
Single-Cycle Instruction Execution & Multifunction
Instructions
DATA MEMORY ADDRESS
On-Chip Program Mem ory RAM or ROM
& Data Mem ory RAM
Integrated I/ O Peripherals: Serial Ports and Tim er
PROGRAM MEMORY DATA
DATA MEMORY DATA
EXTERNAL
DATA
BUS
FEATURES
20 MIPS, 50 ns Maxim um Instruction Rate
Separate On-Chip Buses for Program and Data Mem ory
Program Mem ory Stores Both Instructions and Data
(Three-Bus Perform ance)
TIMER
ARITHMETIC UNITS
MAC SHIFTER
SERIAL PORTS
SPORT 0 SPORT 1
ALU
ADSP-2100 CORE
Dual Data Address Generators w ith Modulo and
Bit-Reverse Addressing
Efficient Program Sequencing w ith Zero-Overhead
Looping: Single-Cycle Loop Setup
Autom atic Booting of On-Chip Program Mem ory from
Byte-Wide External Mem ory (e.g., EPROM )
Double-Buffered Serial Ports w ith Com panding Hardw are,
Autom atic Data Buffering, and Multichannel Operation
Three Edge- or Level-Sensitive Interrupts
Low Pow er IDLE Instruction
T he ADSP-2100 Family’s flexible architecture and compre-
hensive instruction set support a high degree of parallelism.
In one cycle the ADSP-2104/ADSP-2109 can perform all
of the following operations:
•
•
•
•
•
•
Generate the next program address
Fetch the next instruction
Perform one or two data moves
Update one or two data address pointers
Perform a computation
Receive and transmit data via one or two serial ports
PLCC Package
GENERAL D ESCRIP TIO N
T he ADSP-2104 and ADSP-2109 processors are single-chip
microcomputers optimized for digital signal processing (DSP)
and other high speed numeric processing applications. T he
ADSP-2104/ADSP-2109 processors are built upon a common
core. Each processor combines the core DSP architecture—
computation units, data address generators, and program
sequencer—with differentiating features such as on-chip
program and data memory RAM (ADSP-2109 contains 4K
words of program ROM), a programmable timer, and two
serial ports.
T he ADSP-2104 contains 512 words of program RAM, 256
words of data RAM, an interval timer, and two serial ports.
T he ADSP-2104L is a 3.3 volt power supply version of the
ADSP-2104; it is identical to the ADSP-2104 in all other
characteristics.
T he ADSP-2109 contains 4K words of program ROM and
256 words of data RAM, an interval timer, and two serial ports.
T he ADSP-2109L is a 3.3 volt power supply version of the
ADSP-2109; it is identical to the ADSP-2109 in all other
characteristics.
Fabricated in a high speed, submicron, double-layer metal
CMOS process, the ADSP-2104/ADSP-2109 operates at
20 MIPS with a 50 ns instruction cycle time. T he ADSP-2104L
and ADSP-2109L are 3.3 volt versions which operate at
13.824 MIPS with a 72.3 ns instruction cycle time. Every
instruction can execute in a single cycle. Fabrication in CMOS
results in low power dissipation.
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
ADSP-2104/ADSP-2109
T he ADSP-2109 is a memory-variant version of the ADSP-
2104 and contains factory-programmed on-chip ROM program
memory.
windowed user interface. A PROM splitter utility generates
PROM programmer compatible files.
EZ-ICE® in-circuit emulators allow debugging of ADSP-2104
systems by providing a full range of emulation functions such as
modification of memory and register values and execution
breakpoints. EZ-LAB® demonstration boards are complete DSP
systems that execute EPROM-based programs.
The ADSP-2109 eliminates the need for an external boot EPROM
in your system, and can also eliminate the need for any external
program memory by fitting the entire application program in
on-chip ROM. T his device provides an excellent option for
volume applications where board space and system cost constraints
are of critical concern.
T he EZ-Kit Lite is a very low cost evaluation/development
platform that contains both the hardware and software needed
to evaluate the ADSP-21xx architecture.
D evelopm ent Tools
T he ADSP-2104/ADSP-2109 processors are supported by a
complete set of tools for system development. T he ADSP-2100
Family Development Software includes C and assembly
language tools that allow programmers to write code for any
ADSP-21xx processor. T he ANSI C compiler generates ADSP-
21xx assembly source code, while the runtime C library provides
ANSI-standard and custom DSP library routines. T he ADSP-
21xx assembler produces object code modules which the linker
combines into an executable file. The processor simulators provide
an interactive instruction-level simulation with a reconfigurable,
Additional details and ordering information is available in the
ADSP-2100 Family Software & Hardware Development Tools data
sheet (ADDS-21xx-T OOLS). T his data sheet can be requested
from any Analog Devices sales office or distributor.
Additional Infor m ation
T his data sheet provides a general overview of ADSP-2104/
ADSP-2109 processor functionality. For detailed design
information on the architecture and instruction set, refer to the
ADSP-2100 Family User’s Manual, available from Analog
Devices.
EZ-ICE and EZ-LAB are registered trademarks of Analog Devices, Inc.
TABLE O F CO NTENTS
SPECIFICAT IONS (ADSP-2104L/ADSP-2109L) . . . . . . 16
Recommended Operating Conditions . . . . . . . . . . . . . . . . 16
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Supply Current & Power . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Power Dissipation Example . . . . . . . . . . . . . . . . . . . . . . . . 18
Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 18
Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
T est Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
GENERAL DESCRIPT ION . . . . . . . . . . . . . . . . . . . . . . . . 1
Development T ools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
ARCHIT ECT URE OVERVIEW . . . . . . . . . . . . . . . . . . . . 3
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
TIMING PARAMETERS (ADSP-2104/ADSP-2109) . . . . . 20
SYST EM INT ERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Interrupts & Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Bus Request–Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Program Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . 6
Program Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Boot Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Low Power IDLE Instruction . . . . . . . . . . . . . . . . . . . . . . . 8
ADSP-2109 Prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ordering Procedure for ADSP-2109 ROM Processors . . . . 9
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
T IMING PARAMETERS (ADSP-2104L/ADSP-2109L) . . 27
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Interrupts & Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Bus Request–Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
SPECIFICAT IONS (ADSP-2104/ADSP-2109) . . . . . . . . 12
PIN CONFIGURAT IONS
68-Lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PACKAGE OUT LINE DIMENSIONS
68-Lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Recommended Operating Conditions . . . . . . . . . . . . . . . . 12
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Supply Current & Power . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power Dissipation Example . . . . . . . . . . . . . . . . . . . . . . . . 14
Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 14
Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
T est Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
–2–
REV. 0
ADSP-2104/ADSP-2109
INSTRUCTION
REGISTER
PROGRAM
MEMORY
DATA
MEMORY
BOOT
ADDRESS
GENERATOR
SRAM
or ROM
SRAM
DATA
ADDRESS
GENERATOR
#2
DATA
ADDRESS
GENERATOR
#1
TIMER
PROGRAM
SEQUENCER
24
16
PMA BUS
DMA BUS
14
PMA BUS
DMA BUS
EXTERNAL
ADDRESS
BUS
14
MUX
MUX
14
PMD BUS
DMD BUS
24
16
PMD BUS
24
EXTERNAL
DATA
BUS
BUS
EXCHANGE
DMD BUS
COMPANDING
CIRCUITRY
INPUT REGS
INPUT REGS
ALU
INPUT REGS
MAC
SHIFTER
TRANSMIT REG
RECEIVE REG
TRANSMIT REG
RECEIVE REG
OUTPUT REGS
OUTPUT REGS
OUTPUT REGS
16
SERIAL
PORT 0
SERIAL
PORT 1
R Bus
5
5
Figure 1. ADSP-2104/ADSP-2109 Block Diagram
ARCH ITECTURE O VERVIEW
circular buffers. T he circular buffering feature is also used by
the serial ports for automatic data transfers to (and from) on-
chip memory.
Figure 1 shows a block diagram of the ADSP-2104/ADSP-2109
architecture. T he processor contains three independent compu-
tational units: the ALU, the multiplier/accumulator (MAC), and
the shifter. T he computational units process 16-bit data directly
and have provisions to support multiprecision computations.
T he ALU performs a standard set of arithmetic and logic
operations; division primitives are also supported. T he MAC
performs single-cycle multiply, multiply/add, and multiply/
subtract operations. T he shifter performs logical and arithmetic
shifts, normalization, denormalization, and derive exponent
operations. The shifter can be used to efficiently implement
numeric format control including multiword floating-point
representations.
Efficient data transfer is achieved with the use of five internal
buses:
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus
T he two address buses (PMA, DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD, DMD) share a single external data bus.
T he BMS, DMS, and PMS signals indicate which memory
space is using the external buses.
T he internal result (R) bus directly connects the computational
units so that the output of any unit may be used as the input of
any unit on the next cycle.
Program memory can store both instructions and data, permit-
ting the ADSP-2104/ADSP-2109 to fetch two operands in a
single cycle, one from program memory and one from data
memory. T he processor can fetch an operand from on-chip
program memory and the next instruction in the same cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient use of these computational units.
T he sequencer supports conditional jumps, subroutine calls,
and returns in a single cycle. With internal loop counters and
loop stacks, the ADSP-2104/ADSP-2109 executes looped code
with zero overhead—no explicit jump instructions are required
to maintain the loop. Nested loops are also supported.
T he memory interface supports slow memories and memory-
mapped peripherals with programmable wait state generation.
External devices can gain control of the processor’s buses with
the use of the bus request/grant signals (BR, BG).
T wo data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for
One bus grant execution mode (GO Mode) allows the ADSP-
2104/ADSP-2109 to continue running from internal memory.
A second execution mode requires the processor to halt while
buses are granted.
REV. 0
–3–
ADSP-2104/ADSP-2109
T he ADSP-2104/ADSP-2109 can respond to several different
interrupts. T here can be up to three external interrupts,
configured as edge- or level-sensitive. Internal interrupts can be
generated by the timer and serial ports. T here is also a master
RESET signal.
Flexible Inter r upt Schem e—Receive and transmit functions
can generate a unique interrupt upon completion of a data word
transfer.
Autobuffer ing with Single-Cycle O ver head—Each SPORT
can automatically receive or transmit the contents of an entire
circular data buffer with only one overhead cycle per data word;
an interrupt is generated after the transfer of the entire buffer is
completed.
Booting circuitry provides for loading on-chip program memory
automatically from byte-wide external memory. After reset,
three wait states are automatically generated. T his allows, for
example, the ADSP-2104 to use a 150 ns EPROM as external
boot memory. Multiple programs can be selected and loaded
from the EPROM with no additional hardware.
Multichannel Capability (SP O RT0 O nly)—SPORT 0
provides a multichannel interface to selectively receive or
transmit a 24-word or 32-word, time-division multiplexed serial
bit stream; this feature is especially useful for T 1 or CEPT
interfaces, or as a network communication scheme for multiple
processors.
T he data receive and transmit pins on SPORT 1 (Serial Port 1)
can be alternatively configured as a general-purpose input flag
and output flag. You can use these pins for event signalling to
and from an external device.
Alter nate Configur ation—SPORT 1 can be alternatively
configured as two external interrupt inputs (IRQ0, IRQ1) and
the Flag In and Flag Out signals (FI, FO).
A programmable interval timer can generate periodic interrupts.
A 16-bit count register (T COUNT ) is decremented every n
cycles, where n–1 is a scaling value stored in an 8-bit register
(T SCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (T PERIOD).
Inter r upts
T he interrupt controller lets the processor respond to interrupts
with a minimum of overhead. Up to three external interrupt
input pins, IRQ0, IRQ1, and IRQ2, are provided. IRQ2 is
always available as a dedicated pin; IRQ1 and IRQ0 may be
alternately configured as part of Serial Port 1. T he ADSP-2104/
ADSP-2109 also supports internal interrupts from the timer,
and serial ports. T he interrupts are internally prioritized and
individually maskable (except for RESET which is nonmaskable).
The IRQx input pins can be programmed for either level- or
edge-sensitivity. T he interrupt priorities are shown in T able I.
Ser ial P or ts
T he ADSP-2104/ADSP-2109 processor includes two synchro-
nous serial ports (“SPORT s”) for serial communications and
multiprocessor communication.
T he serial ports provide a complete synchronous serial interface
with optional companding in hardware. A wide variety of
framed or frameless data transmit and receive modes of opera-
tion are available. Each SPORT can generate an internal
programmable serial clock or accept an external serial clock.
Table I. Interrupt Vector Addresses & P riority
AD SP -2104/AD SP -2109
Each serial port has a 5-pin interface consisting of the following
signals:
Interrupt
Source
Interrupt
Vector Address
Signal Nam e
Function
RESET Startup
IRQ2
0x0000
0x0004 (High Priority)
0x0008
0x000C
0x0010
SCLK
RFS
T FS
DR
Serial Clock (I/O)
Receive Frame Synchronization (I/O)
T ransmit Frame Synchronization (I/O)
Serial Data Receive
SPORT 0 T ransmit
SPORT 0 Receive
SPORT 1 T ransmit or IRQ1
SPORT 1 Receive or IRQ0
T imer
DT
Serial Data T ransmit
0x0014
0x0018 (Low Priority)
T he serial ports offer the following capabilities:
Bidir ectional—Each SPORT has a separate, double-buffered
transmit and receive function.
T he ADSP-2104/ADSP-2109 uses a vectored interrupt scheme:
when an interrupt is acknowledged, the processor shifts program
control to the interrupt vector address corresponding to the
interrupt received. Interrupts can be optionally nested so that a
higher priority interrupt can preempt the currently executing
interrupt service routine. Each interrupt vector location is four
instructions in length so that simple service routines can be
coded entirely in this space. Longer service routines require an
additional JUMP or CALL instruction.
Flexible Clocking—Each SPORT can use an external serial
clock or generate its own clock internally.
Flexible Fr am ing—T he SPORT s have independent framing
for the transmit and receive functions; each function can run in
a frameless mode or with frame synchronization signals inter-
nally generated or externally generated; frame sync signals may
be active high or inverted, with either of two pulse widths and
timings.
Individual interrupt requests are logically ANDed with the bits
in the IMASK register; the highest-priority unmasked interrupt
is then selected.
D iffer ent Wor d Lengths—Each SPORT supports serial data
word lengths from 3 to 16 bits.
Com panding in H ar dwar e—Each SPORT provides optional
A-law and µ-law companding according to CCIT T recommen-
dation G.711.
–4–
REV. 0
ADSP-2104/ADSP-2109
T he interrupt control register, ICNT L, allows the external
interrupts to be set as either edge- or level-sensitive. Depending
on bit 4 in ICNT L, interrupt service routines can either be
nested (with higher priority interrupts taking precedence) or be
processed sequentially (with only one interrupt service active at
a time).
Programmable wait-state generation allows the processors to
easily interface to slow external memories.
T he ADSP-2104/ADSP-2109 also provides either: one external
interrupt (IRQ2) and two serial ports (SPORT 0, SPORT 1), or
three external interrupts (IRQ2, IRQ1, IRQ0) and one serial
port (SPORT 0).
The interrupt force and clear register, IFC, is a write-only register
that contains a force bit and a clear bit for each interrupt.
Clock Signals
T he ADSP-2104/ADSP-2109’s CLKIN input may be driven by
a crystal or by a T T L-compatible external clock signal. T he
CLKIN input may not be halted or changed in frequency during
operation, nor operated below the specified low frequency limit.
When responding to an interrupt, the AST AT , MST AT , and
IMASK status registers are pushed onto the status stack and
the PC counter is loaded with the appropriate vector address.
T he status stack is seven levels deep to allow interrupt nesting.
T he stack is automatically popped when a return from the
interrupt instruction is executed.
If an external clock is used, it should be a T T L-compatible
signal running at the instruction rate. T he signal should be
connected to the processor’s CLKIN input; in this case, the
XT AL input must be left unconnected.
P in D efinitions
T able II shows pin definitions for the ADSP-2104/ADSP-2109
Because the processor includes an on-chip oscillator circuit, an
external crystal may also be used. T he crystal should be con-
nected across the CLKIN and XT AL pins, with two capacitors
connected as shown in Figure 2. A parallel-resonant, fundamen-
tal frequency, microprocessor-grade crystal should be used.
processors. Any inputs not used must be tied to VDD
.
SYSTEM INTERFACE
Figure 3 shows a typical system for the ADSP-2104/ADSP-2109,
with two serial I/O devices, a boot EPROM, and optional external
program and data memory. A total of 14.25K words of data
memory and 14.5K words of program memory is addressable.
Table II. AD SP -2104/AD SP -2109 P in D efinitions
P in
Nam e(s)
# of
P ins
Input /
O utput
Function
Address
Data1
14
24
O
I/O
Address outputs for program, data and boot memory.
Data I/O pins for program and data memories. Input only for
boot memory, with two MSBs used for boot memory addresses.
Unused data lines may be left floating.
Processor Reset Input
External Interrupt Request # 2
External Bus Request Input
External Bus Grant Output
External Program Memory Select
External Data Memory Select
Boot Memory Select
External Memory Read Enable
External Memory Write Enable
Memory Map Select Input
External Clock or Quartz Crystal Input
Processor Clock Output
Power Supply Pins
RESET
IRQ2
1
1
1
1
1
1
1
1
1
1
2
1
I
I
I
O
O
O
O
O
O
I
BR2
BG
PMS
DMS
BMS
RD
WR
MMAP
CLKIN, XT AL
CLKOUT
VDD
I
O
GND
Ground Pins
SPORT 0
SPORT 1
or Interrupts & Flags:
IRQ0 (RFS1)
IRQ1 (TFS1)
FI (DR1)
FO (DT1)
5
5
I/O
I/O
Serial Port 0 Pins (TFS0, RFS0, DT0, DR0, SCLK0)
Serial Port 1 Pins (TFS1, RFS1, DT1, DR1, SCLK1)
1
1
1
1
I
I
I
O
External Interrupt Request # 0
External Interrupt Request # 1
Flag Input Pin
Flag Output Pin
NOT ES
1Unused data bus lines may be left floating.
2BR must be tied high (to VDD) if not used.
REV. 0
–5–
ADSP-2104/ADSP-2109
T he RESET input resets all internal stack pointers to the empty
stack condition, masks all interrupts, and clears the MST AT
register. When RESET is released, the boot loading sequence is
performed (provided there is no pending bus request and the
chip is configured for booting, with MMAP = 0). T he first
instruction is then fetched from internal program memory
location 0x0000.
CLKIN
XTAL
CLKOUT
ADSP-2104/
ADSP-2109
P r ogr am Mem or y Inter face
T he on-chip program memory address bus (PMA) and on-chip
program memory data bus (PMD) are multiplexed with the on-
chip data memory buses (DMA, DMD), creating a single
external data bus and a single external address bus. T he external
data bus is bidirectional and is 24 bits wide to allow instruction
fetches from external program memory. Program memory may
contain code and data.
Figure 2. External Crystal Connections
A clock output signal (CLKOUT ) is generated by the processor,
synchronized to the processor’s internal cycles.
Reset
The RESET signal initiates a complete reset of the processor.
T he RESET signal must be asserted when the chip is powered
up to assure proper initialization. If the RESET signal is applied
during initial power-up, it must be held long enough to allow
the processor’s internal clock to stabilize. If RESET is activated
at any time after power-up and the input clock frequency does
not change, the processor’s internal clock continues and does
not require this stabilization time.
T he external address bus is 14 bits wide.
T he data lines are bidirectional. T he program memory select
(PMS) signal indicates accesses to program memory and can be
used as a chip select signal. T he write (WR) signal indicates a
write operation and is used as a write strobe. T he read (RD)
signal indicates a read operation and is used as a read strobe or
output enable signal.
T he power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is
applied to the processor and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 tCK cycles will ensure that the PLL has locked (this does
not, however, include the crystal oscillator start-up time).
During this power-up sequence the RESET signal should be
held low. On any subsequent resets, the RESET signal must
T he processor writes data from the 16-bit registers to 24-bit
program memory using the PX register to provide the lower
eight bits. When the processor reads 16-bit data from 24-bit
program memory to a 16-bit data register, the lower eight bits
are placed in the PX register.
T he program memory interface can generate 0 to 7 wait states
for external memory devices; default is to 7 wait states after
RESET.
meet the minimum pulse width specification, tRSP
.
T o generate the RESET signal, use either an RC circuit with an
external Schmidt trigger or a commercially available reset IC.
(Do not use only an RC circuit.)
ADSP-2104
or ADSP-2109
A
13-0
14
ADDR
13-0
BOOT
MEMORY
1x CLOCK
or
CRYSTAL
CLKIN
XTAL
D
23-22
ADDR
e.g. EPROM
D
24
15-8
2764
27128
27256
27512
CLKOUT
RESET
IRQ2
DATA
DATA
OE
23-0
BMS
CS
BR
A
D
13-0
BG
ADDR
DATA
23-0
MMAP
PROGRAM
MEMORY
RD
OE
WE
CS
SPORT 1
SCLK1
WR
(OPTIONAL)
SERIAL
DEVICE
RFS1 or IRQ0
TFS1 or IRQ1
DT1 or FO
DR1 or FI
A
13-0
(OPTIONAL)
ADDR
DATA
DATA
MEMORY
&
D
23-8
SPORT 0
SCLK0
RFS0
TFS0
DT0
PMS
DMS
PERIPHERALS
OE
WE
CS
SERIAL
DEVICE
(OPTIONAL)
(OPTIONAL)
DR0
THE TWO MSBs OF THE DATA BUS (D
) ARE USED TO SUPPLY THE TWO MSBs OF THE
23-22
BOOT MEMORY EPROM ADDRESS. THIS IS ONLY REQUIRED FOR THE 27256 AND 27512.
Figure 3. ADSP-2104/ADSP-2109 System
–6–
REV. 0
ADSP-2104/ADSP-2109
P r ogr am Mem or y Maps
D ata Mem or y Inter face
Program memory can be mapped in two ways, depending on
the state of the MMAP pin. Figure 4 shows the ADSP-2104
program memory maps. Figure 5 shows the program memory
maps for the ADSP-2109.
T he data memory address bus (DMA) is 14 bits wide. T he
bidirectional external data bus is 24 bits wide, with the upper 16
bits used for data memory data (DMD) transfers.
T he data memory select (DMS) signal indicates access to data
memory and can be used as a chip select signal. T he write (WR)
signal indicates a write operation and can be used as a write
strobe. T he read (RD) signal indicates a read operation and can
be used as a read strobe or output enable signal.
0x0000
0x0000
INTERNAL RAM
512 WORDS
LOADED FROM
EXTERNAL
BOOT MEMORY
0x01FF
0x0200
T he ADSP-2104/ADSP-2109 processors support memory-
mapped I/O, with the peripherals memory-mapped into the data
memory address space and accessed by the processor in the
same manner as data memory.
EXTERNAL
14K
RESERVED
1.5K
0x07FF
0x0800
D ata Mem or y Map
AD SP -2104
0x37FF
0x3800
On-chip data memory RAM resides in the 256 words beginning
at address 0x3800, also shown in Figure 6. Data memory
locations from 0x3900 to the end of data memory at 0x3FFF
are reserved. Control and status registers for the system, timer,
wait-state configuration, and serial port operations are located in
this region of memory.
INTERNAL RAM
512 WORDS
EXTERNAL
14K
0x39FF
0x3A00
RESERVED
1.5K
0x3FFF
0x3FFF
MMAP=0
MMAP=1
0x0000
No Booting
1K EXTERNAL
DWAIT0
0x0400
Figure 4. ADSP-2104 Program Mem ory Maps
1K EXTERNAL
DWAIT1
0x0000
0x0000
0x0800
2K
EXTERNAL
4K
INTERNAL
ROM
0x07FF
0x0800
EXTERNAL
10K EXTERNAL
2K
INTERNAL
ROM
RAM
DWAIT2
0x0FF0
0x0FF0
0x3000
0x3400
RESERVED
RESERVED
1K EXTERNAL
DWAIT3
0x0FFF
0x1000
0x0FFF
0x1000
1K EXTERNAL
DWAIT4
10K
EXTERNAL
12K
EXTERNAL
0x3800
0x3900
0x3C00
256 WORDS
0x37FF
0x3800
2K
INTERNAL
ROM
INTERNAL
RAM
0x3FFF
0x3FFF
MEMORY-MAPPED
CONTROL REGISTERS
& RESERVED
MMAP=0
MMAP=1
0x3FFF
Figure 5. ADSP-2109 Program Mem ory Maps
AD SP -2104
Figure 6. Data Mem ory Map
When MMAP = 0, on-chip program memory RAM occupies
512 words beginning at address 0x0000. Off-chip program
memory uses the remaining 14K words beginning at address
0x0800. In this configuration–when MMAP = 0–the boot
loading sequence (described below in “Boot Memory Inter-
face”) is automatically initiated when RESET is released.
T he remaining 14K of data memory is located off-chip. T his
external data memory is divided into five zones, each associated
with its own wait-state generator. T his allows slower peripherals
to be memory-mapped into data memory for which wait states
are specified. By mapping peripherals into different zones, you
can accommodate peripherals with different wait-state require-
ments. All zones default to seven wait states after RESET.
When MMAP = 1, 14K words of off-chip program memory
begin at address 0x0000 and on-chip program memory RAM is
located in the 512 words between addresses 0x3800–0x39FF. In
this configuration, program memory is not booted although it
can be written to and read under program control.
REV. 0
–7–
ADSP-2104/ADSP-2109
Boot Mem or y Inter face
the number of wait states). T he instruction does not need to be
completed when the bus is granted; the processor will grant the
bus in between two memory accesses if an instruction requires
more than one external memory access.
Boot memory is an external 16K by 8 space, divided into eight
separate 2K by 8 pages. T he 8-bit bytes are automatically
packed into 24-bit instruction words by the processor, for
loading into on-chip program memory.
When the BR signal is released, the processor releases the BG
signal, re-enables the output drivers and continues program
execution from the point where it stopped.
T hree bits in the processors’ System Control Register select
which page is loaded by the boot memory interface. Another bit
in the System Control Register allows the forcing of a boot
loading sequence under software control. Boot loading from
Page 0 after RESET is initiated automatically if MMAP = 0.
T he bus request feature operates at all times, including when
the processor is booting and when RESET is active. If this
feature is not used, the BR input should be tied high (to VDD).
T he boot memory interface can generate zero to seven wait
states; it defaults to three wait states after RESET. T his allows
the ADSP-2104 to boot from a single low cost EPROM such as
a 27C256. Program memory is booted one byte at a time and
converted to 24-bit program memory words.
Low P ower ID LE Instr uction
T he IDLE instruction places the processor in low power state in
which it waits for an interrupt. When an interrupt occurs, it is
serviced and execution continues with instruction following
IDLE. T ypically this next instruction will be a JUMP back to
the IDLE instruction. T his implements a low-power standby
loop.
T he BMS and RD signals are used to select and to strobe the
boot memory interface. Only 8-bit data is read over the data
bus, on pins D8-D15. T o accommodate up to eight pages of
boot memory, the two MSBs of the data bus are used in the
boot memory interface as the two MSBs of the boot memory
address: D23, D22, and A13 supply the boot page number.
T he IDLE n instruction is a special version of IDLE that slows
the processor’s internal clock signal to further reduce power
consumption. T he reduced clock frequency, a programmable
fraction of the normal clock rate, is specified by a selectable
divisor, n, given in the IDLE instruction. T he syntax of the
instruction is:
T he ADSP-2100 Family Assembler and Linker allow the
creation of programs and data structures requiring multiple boot
pages during execution.
IDLE n;
T he BR signal is recognized during the booting sequence. T he
bus is granted after loading the current byte is completed. BR
during booting may be used to implement booting under control
of a host processor.
where n = 16, 32, 64, or 128.
T he instruction leaves the chip in an idle state, operating at the
slower rate. While it is in this state, the processor’s other
internal clock signals, such as SCLK, CLKOUT , and the timer
clock, are reduced by the same ratio. Upon receipt of an
enabled interrupt, the processor will stay in the IDLE state for
up to a maximum of n CLKIN cycles, where n is the divisor
specified in the instruction, before resuming normal operation.
Bus Inter face
T he ADSP-2104/ADSP-2109 can relinquish control of their
data and address buses to an external device. When the external
device requires control of the buses, it asserts the bus request
signal (BR). If the processor is not performing an external
memory access, it responds to the active BR input in the next
cycle by:
When the IDLE n instruction is used, it slows the processor’s
internal clock and thus its response time to incoming interrupts–
the 1-cycle response time of the standard IDLE state is in-
creased by n, the clock divisor. When an enabled interrupt is
received, the ADSP-21xx will remain in the IDLE state for up
to a maximum of n CLKIN cycles (where n = 16, 32, 64, or
128) before resuming normal operation.
•
T hree-stating the data and address buses and the PMS,
DMS, BMS, RD, WR output drivers,
•
•
Asserting the bus grant (BG) signal,
and halting program execution.
If the Go mode is set, however, the ADSP-2104/ADSP-2109
will not halt program execution until it encounters an instruc-
tion that requires an external memory access.
When the IDLE n instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the IDLE state (a maximum of n
CLKIN cycles).
If the processor is performing an external memory access when
the external device asserts the BR signal, it will not three-state
the memory interfaces or assert the BG signal until the cycle
after the access completes (up to eight cycles later depending on
–8–
REV. 0
ADSP-2104/ADSP-2109
AD SP -2109 P r ototyping
After this information is received, it is entered into Analog
Devices’ ROM Manager System which assigns a custom ROM
model number to the product. T his model number will be
branded on all prototype and production units manufactured to
these specifications.
You can prototype your ADSP-2109 system with the ADSP-
2104 RAM-based processor. When code is fully developed and
debugged, it can be submitted to Analog Devices for conversion
into a ADSP-2109 ROM product.
T he ADSP-2101 EZ-ICE emulator can be used for develop-
ment of ADSP-2109 systems. For the 3.3 V ADSP-2109, a
voltage converter interface board provides 3.3 V emulation.
T o minimize the risk of code being altered during this process,
Analog Devices verifies that the .EXE files on both floppy disks
are identical, and recalculates the checksums for the .EXE file
entered into the ROM Manager System. T he checksum data, in
the form of a ROM Memory Map, a hard copy of the .EXE file,
and a ROM Data Verification form are returned to you for
inspection.
Additional overlay memory is used for emulation of ADSP-2109
systems. It should be noted that due to the use of off-chip
overlay memory to emulate the ADSP-2109, a performance loss
may be experienced when both executing instructions and
fetching program memory data from the off-chip overlay
memory in the same cycle. T his can be overcome by locating
program memory data in on-chip memory.
A signed ROM Verification Form and a purchase order for
production units are required prior to any product being
manufactured. Prototype units may be applied toward the
minimum order quantity.
O r der ing P r ocedur e for AD SP -2109 RO M P r ocessor
T o place an order for a custom ROM-coded ADSP-2109, you
must:
Upon completion of prototype manufacture, Analog Devices
will ship prototype units and a delivery schedule update for
production units. An invoice against your purchase order for the
NRE charges is issued at this time.
1. Complete the following forms contained in the ADSP ROM
Ordering Package, available from your Analog Devices sales
representative:
T here is a charge for each ROM mask generated and a mini-
mum order quantity. Consult your sales representative for
details. A separate order must be placed for parts of a specific
package type, temperature range, and speed grade.
ADSP-2109 ROM Specification Form
ROM Release Agreement
ROM NRE Agreement & Minimum Quantity Order (MQO)
Acceptance Agreement for Pre-Production ROM Products
2. Return the forms to Analog Devices along with two copies of
the Memory Image File (.EXE file) of your ROM code. T he
files must be supplied on two 3.5" or 5.25" floppy disks for
the IBM PC (DOS 2.01 or higher).
3. Place a purchase order with Analog Devices for nonrecurring
engineering changes (NRE) associated with ROM product
development.
REV. 0
–9–
ADSP-2104/ADSP-2109
Instr uction Set
operational parallelism. T here are five basic categories of
instructions: data move instructions, computational instruc-
tions, multifunction instructions, program flow control instruc-
tions and miscellaneous instructions. Multifunction instructions
perform one or two data moves and a computation.
The ADSP-2104/ADSP-2109 assembly language uses an algebraic
syntax for ease of coding and readability. T he sources and
destinations of computations and data movements are written
explicitly in each assembly statement, eliminating cryptic
assembler mnemonics.
T he instruction set is summarized below. T he ADSP-2100
Family Users Manual contains a complete reference to the
instruction set.
Every instruction assembles into a single 24-bit word and
executes in a single cycle. T he instructions encompass a wide
variety of instruction types along with a high degree of
ALU Instructions
[IF cond] AR| AF
=
=
=
=
=
=
=
=
=
=
=
=
=
=
xop + yop [+ C] ;
xop – yop [+ C– 1] ;
yop – xop [+ C– 1] ;
xop AND yop ;
xop OR yop ;
xop XOR yop ;
PASS xop ;
– xop ;
NOT xop ;
ABS xop ;
yop + 1 ;
Add/Add with Carry
Subtract X – Y/Subtract X – Y with Borrow
Subtract Y – X/Subtract Y – X with Borrow
AND
OR
XOR
Pass, Clear
Negate
NOT
Absolute Value
Increment
Decrement
Divide
yop – 1 ;
DIVS yop, xop ;
DIVQ xop ;
MAC Instructions
[IF cond] MR| MF
=
=
=
=
=
xop yop ;
*
Multiply
MR + xop yop ;
*
Multiply/Accumulate
Multiply/Subtract
Transfer MR
MR – xop yop ;
*
MR ;
0 ;
Clear
IF MV SAT MR ;
Conditional MR Saturation
Shifter Instructions
[IF cond] SR = [SR OR] ASHIFT xop ;
[IF cond] SR = [SR OR] LSHIFT xop ;
SR = [SR OR] ASHIFT xop BY <exp>;
SR = [SR OR] LSHIFT xop BY <exp>;
[IF cond] SE = EXP xop ;
Arithmetic Shift
Logical Shift
Arithmetic Shift Immediate
Logical Shift Immediate
Derive Exponent
[IF cond] SB = EXPADJ xop
;
Block Exponent Adjust
[IF cond] SR = [SR OR] NORM xop ;
Normalize
D ata Move Instructions
reg = reg ;
reg = <data> ;
Register-to-Register Move
Load Register Immediate
reg = DM (<addr>) ;
dreg = DM (Ix , My) ;
dreg = PM (Ix , My) ;
DM (<addr>) = reg ;
DM (Ix , My) = dreg ;
PM (Ix , My) = dreg ;
Data Memory Read (Direct Address)
Data Memory Read (Indirect Address)
Program Memory Read (Indirect Address)
Data Memory Write (Direct Address)
Data Memory Write (Indirect Address)
Program Memory Write (Indirect Address)
Multifunction Instructions
<ALU>| <MAC>| <SHIFT > , dreg = dreg ;
Computation with Register-to-Register Move
<ALU>| <MAC>| <SHIFT > , dreg = DM (Ix , My) ;
<ALU>| <MAC>| <SHIFT > , dreg = PM (Ix , My) ;
DM (Ix , My) = dreg , <ALU>| <MAC>| <SHIFT > ;
PM (Ix , My) = dreg , <ALU>| <MAC>| <SHIFT > ;
dreg = DM (Ix , My) , dreg = PM (Ix , My) ;
Computation with Memory Read
Computation with Memory Read
Computation with Memory Write
Computation with Memory Write
Data & Program Memory Read
<ALU>| <MAC> , dreg = DM (Ix , My) , dreg = PM (Ix , My) ;
ALU/MAC with Data & Program Memory Read
–10–
REV. 0
ADSP-2104/ADSP-2109
P rogram Flow Instructions
DO <addr> [UNT IL term] ;
[IF cond] JUMP (Ix) ;
Do Until Loop
Jump
[IF cond] JUMP <addr>;
[IF cond] CALL (Ix) ;
Call Subroutine
[IF cond] CALL <addr>;
IF [NOT ] FLAG_IN
IF [NOT ] FLAG_IN
[IF cond] SET | RESET | T OGGLE
JUMP <addr>;
CALL <addr>;
Jump/Call on Flag In Pin
FLAG_OUT [, ...] ;
Modify Flag Out Pin
[IF cond] RT S ;
[IF cond] RT I ;
IDLE [(n)] ;
Return from Subroutine
Return from Interrupt Service Routine
Idle
Miscellaneous Instructions
NOP ;
No Operation
MODIFY (Ix , My);
[PUSH ST S] [, POP CNT R] [, POP PC] [, POP LOOP] ;
Modify Address Register
Stack Control
ENA| DIS
SEC_REG [, ...] ;
Mode Control
BIT _REV
AV_LAT CH
AR_SAT
M_MODE
T IMER
G_MODE
Notation Conventions
Ix
Index registers for indirect addressing
My
Modify registers for indirect addressing
Immediate data value
Immediate address value
Exponent (shift value) in shift immediate instructions (8-bit signed number)
Any ALU instruction (except divide)
Any multiply-accumulate instruction
Any shift instruction (except shift immediate)
Condition code for conditional instruction
T ermination code for DO UNT IL loop
Data register (of ALU, MAC, or Shifter)
Any register (including dregs)
<data>
<addr>
<exp>
<ALU>
<MAC>
<SHIFT >
cond
term
dreg
reg
;
,
[
A semicolon terminates the instruction
Commas separate multiple operations of a single instruction
Optional part of instruction
]
[, ...]
option1 | option2
Optional, multiple operations of an instruction
List of options; choose one.
Assem bly Code Exam ple
T he following example is a code fragment that performs the filter tap update for an adaptive filter based on a least-mean-squared
algorithm. Notice that the computations in the instructions are written like algebraic equations.
MF=MX0 MY1(RND), MX0=DM(I2,M1);
{MF=error beta}
*
*
MR=MX0 MF(RND), AY0=PM(I6,M5);
*
DO adapt UNTIL CE;
AR=MR1+AY0, MX0=DM(I2,M1), AY0=PM(I6,M7);
adapt:
PM(I6,M6)=AR, MR=MX0 MF(RND);
*
MODIFY(I2,M3);
MODIFY(I6,M7);
{Point to oldest data}
{Point to start of data}
REV. 0
–11–
ADSP-2104/ADSP-2109–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
K Grade
P aram eter
Min
Max
Unit
VDD
T AMB
Supply Voltage
Ambient Operating T emperature
4.50
0
5.50
+70
V
°C
See “Environmental Conditions” for information on thermal specifications.
ELECTRICAL CHARACTERISTICS
P aram eter
Test Conditions
Min
Max
Unit
VIH
VIH
VIL
VOH
Hi-Level Input Voltage3, 5
Hi-Level CLKIN Voltage
Lo-Level Input Voltage1, 3
Hi-Level Output Voltage2, 3, 7
@ VDD = max
@ VDD = max
@ VDD = min
@ VDD = min, IOH = –0.5 mA
@ VDD = min, IOH = –100 µA8
@ VDD = min, IOL = 2 mA
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max6
@ VDD = max, VIN = 0 V6
2.0
2.2
V
V
V
V
V
V
µA
µA
µA
µA
pF
pF
0.8
2.4
VDD – 0.3
VOL
IIH
IIL
IOZH
IOZL
CI
Lo-Level Output Voltage2, 3, 7
Hi-Level Input Current1
0.4
10
10
10
10
8
Lo-Level Input Current1
T hree-State Leakage Current4
T hree-State Leakage Current4
Input Pin Capacitance1, 8, 9
Output Pin Capacitance4, 8, 9, 10
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C
CO
8
NOT ES
1Input-only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR1, DR0.
2Output pins: BG, PMS, DMS, BMS, RD, WR, A0–A13, CLKOUT , DT 1, DT 0.
3Bidirectional pins: D0–D23, SCLK1, RFS1, T FS1, SCLK0, RFS0, T FS0.
4T hree-state pins: A0–A13, D0–D23, PMS, DMS, BMS, RD, WR, DT 1, SCLK1, RSF1, T FS1, DT 0, SCLK0, RFS0, T FS0.
5Input-only pins: RESET, IRQ2, BR, MMAP, DR1, DR0.
60 V on BR, CLKIN Active (to force three-state condition).
7Although specified for T T L outputs, all ADSP-2104/ADSP-2109 outputs are CMOS-compatible and will drive to V DD and GND, assuming no dc loads.
8Guaranteed but not tested.
9Applies to PGA, PLCC, PQFP package types.
10Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
ABSO LUTE MAXIMUM RATINGS
*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating T emperature Range (Ambient) . . . –55ºC to +125°C
Storage T emperature Range . . . . . . . . . . . . . –65°C to +125°C
Lead T emperature (10 sec) PGA . . . . . . . . . . . . . . . . . +300°C
Lead T emperature (5 sec) PLCC, PQFP, T QFP . . . . +280°C
*Stresses greater than those listed above may cause permanent damage to the
device. T hese are stress ratings only, and functional operation of the device at these
or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-2104/ADSP-2109 processor features proprietary ESD protection circuitry to dissipate
high energy electrostatic discharges (H uman Body Model), permanent damage may occur to devices
subjected to such discharges. T herefore, proper ESD precautions are recommended to avoid
performance degradation or loss of functionality. Unused devices must be stored in conductive foam
or shunts, and the foam should be discharged to the destination socket before the devices are
removed. Per method 3015 of MIL-ST D-883, the ADSP-2104/ADSP-2109 processor has been
classified as Class 1 device.
WARNING!
ESD SENSITIVE DEVICE
–12–
REV. 0
ADSP-2104/ADSP-2109
SPECIFICATIONS (ADSP-2104/ADSP-2109)
SUPPLY CURRENT & POWER
P aram eter
IDD
Supply Current (Dynamic)1
Supply Current (Idle)1, 3
Test Conditions
Min
Max
Unit
@ VDD = max, tCK = 50 ns2
@ VDD = max, tCK = 72.3 ns2
@ VDD = max, tCK = 50 ns
@ VDD = max, tCK = 72.3 ns
31
24
11
10
mA
mA
mA
mA
IDD
NOT ES
1Current reflects device operating with no output loads.
2VIN = 0.4 V and 2.4 V.
3Idle refers to ADSP-2104/ADSP-2109 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND.
For typical supply current (internal power dissipation) figures, see Figure 7.
1
IDD DYNAMIC
220
200
180
170mW
= 5.5V
160
V
V
DD
128mW
140
129mW
120
100
80
= 5.0V
95mW
= 4.5V
DD
100mW
74mW
V
DD
60
10.00
13.83
20.00
25.00
30.00
FREQUENCY – MHz
1, 2
3
IDD IDLE
IDD IDLE n MODES
70
60
65
60
60mW
= 5.5V
60mW
55mW
V
IDD IDLE
DD
50
40
55
55mW
42mW
= 5.0V
50
V
V
DD
31mW
= 4.5V
38mW
28mW
IDLE 16
30
20
10
0
45
40
35
30
42mW
41mW
DD
41mW
40mW
IDLE 128
10.00
13.83
20.00
25.00 30.00
10.00
13.83
20.00
25.00 30.00
FREQUENCY – MHz
FREQUENCY – MHz
1
2
POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
IDLE REFERS TO ADSP-2104/ADSP-2109 OPERATION DURING EXECUTION OF IDLE INSTRUCTION.
DEASSERTED PINS ARE DRIVEN TO EITHER V OR GND.
DD
MAXIMUM POWER DISSIPATION AT V = 5.5V DURING EXECUTION OF IDLE n INSTRUCTION.
3
DD
Figure 7. ADSP-2104/ADSP-2109 Power (Typical) vs. Frequency
REV. 0
–13–
ADSP-2104/ADSP-2109
CAP ACITIVE LO AD ING
Figures 8 and 9 show capacitive loading characteristics.
SPECIFICATIONS (ADSP-2104/ADSP-2109)
P O WER D ISSIP ATIO N EXAMP LE
T o determine total power dissipation in a specific application,
the following equation should be applied for each output:
8
7
2
C × VDD × f
V
= 4.5V
DD
6
5
4
C = load capacitance, f = output switching frequency.
Exam ple:
In an ADSP-2104 application where external data memory is
used and no other outputs are active, power dissipation is
calculated as follows:
3
2
1
Assumptions:
•
•
External data memory is accessed every cycle with 50% of the
address pins switching.
0
0
25
50
75
100 125 150 175
– pF
C
L
External data memory writes occur every other cycle with
50% of the data pins switching.
Figure 8. Typical Output Rise Tim e vs. Load Capacitance, CL
(at Maxim um Am bient Operating Tem perature)
•
•
Each address and data pin has a 10 pF total load at the pin.
T he application operates at VDD = 5.0 V and tCK = 50 ns.
2
Total Power Dissipation = PINT + (C × VDD × f )
PINT = internal power dissipation (from Figure 7).
5
4
2
(C × VDD × f ) is calculated for each output:
V
= 4.5V
DD
3
2
# of
P ins
؋
C 2
O utput
؋
VD D × f 1
0
Address, DMS 8
Data, WR
RD
× 10 pF × 52 V × 20 MHz = 40.0 mW
× 10 pF × 52 V × 10 MHz = 22.5 mW
× 10 pF × 52 V × 10 MHz = 2.5 mW
× 10 pF × 52 V × 20 MHz = 5.0 mW
9
1
1
–1
–2
CLKOUT
70.0 mW
–3
0
25
50
75 100 125
– pF
150 175
T otal power dissipation for this example = PINT + 70.0 mW.
C
L
ENVIRO NMENTAL CO ND ITIO NS
Ambient T emperature Rating:
Figure 9. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maxim um Am bient Operating Tem perature)
TAMB = T CASE – (PD × θC A
)
TCASE = Case T emperature in °C
PD = Power Dissipation in W
θC A = T hermal Resistance (Case-to-Ambient)
θJA = T hermal Resistance (Junction-to-Ambient)
θJC = T hermal Resistance (Junction-to-Case)
P ackage
JC
CA
JA
PLCC
27°C/W
16°C/W
11°C/W
–14–
REV. 0
ADSP-2104/ADSP-2109
T he decay time, tDECAY, is dependent on the capacitative load,
CL , and the current load, iL , on the output pin. It can be
approximated by the following equation:
SPECIFICATIONS (ADSP-2104/ADSP-2109)
TEST CO ND ITIO NS
Figure 10 shows voltage reference levels for ac measurements.
CL × 0.5 V
tDECAY
=
3.0V
iL
INPUT
1.5V
0.0V
from which
tDIS = tMEASURED – tDECAY
2.0V
1.5V
0.8V
OUTPUT
is calculated. If multiple pins (such as the data bus) are dis-
abled, the measurement value is that of the last pin to stop
driving.
Figure 10. Voltage Reference Levels for AC Measurem ents
(Except Output Enable/Disable)
O utput Enable Tim e
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. T he output enable time (t E NA) is the interval from
when a reference signal reaches a high or low voltage level to
when the output has reached a specified high or low trip point,
as shown in Figure 11. If multiple pins (such as the data bus)
are enabled, the measurement value is that of the first pin to
start driving.
O utput D isable Tim e
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. T he
output disable time (tDIS) is the difference of tMEASURED and
t
DECAY, as shown in Figure 11. T he time tMEASURED is the
interval from when a reference signal reaches a high or low
voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage.
REFERENCE
SIGNAL
tMEASURED
tDIS
tENA
V
V
(MEASURED)
(MEASURED)
V
V
(MEASURED)
(MEASURED)
OH
OH
2.0V
1.0V
V
(MEASURED) – 0.5V
(MEASURED) +0.5V
OH
OUTPUT
V
OL
OL
OL
tDECAY
OUTPUT STARTS
DRIVING
OUTPUT STOPS
DRIVING
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE
APPROXIMATELY 1.5V.
Figure 11. Output Enable/Disable
I
OL
TO
OUTPUT
PIN
+1.5V
50pF
I
OH
Figure 12. Equivalent Device Loading for AC Measurem ents
(Except Output Enable/Disable)
REV. 0
–15–
ADSP-2104L/ADSP-2109L–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
K Grade
P aram eter
Min
Max
Unit
VDD
T AMB
Supply Voltage
Ambient Operating T emperature
3.00
0
3.60
+70
V
°C
See “Environmental Conditions” for information on thermal specifications.
ELECTRICAL CHARACTERISTICS
P aram eter
Test Conditions
Min
Max
Unit
VIH
VIL
VOH
VOL
IIH
Hi-Level Input Voltage1, 3
@ VDD = max
@ VDD = min
2.0
2.4
V
V
V
V
µA
µA
µA
µA
pF
pF
Lo-Level Input Voltage1, 3
Hi-Level Output Voltage2, 3, 6
Lo-Level Output Voltage2, 3, 6
Hi-Level Input Current1
0.4
@ VDD = min, IOH = –0.5 mA6
@ VDD = min, IOL = 2 mA6
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max5
@ VDD = max, VIN = 0 V5
0.4
10
10
10
10
8
IIL
Lo-Level Input Current1
IOZH
IOZL
CI
T hree-State Leakage Current4
T hree-State Leakage Current4
Input Pin Capacitance1, 7, 8
Output Pin Capacitance4, 7, 8, 9
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C
CO
8
NOT ES
1Input-only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR1, DR0.
2
Output pins: BG, PMS, DMS, BMS, RD, WR, A0–A13, CLKOUT, DT1, DT0.
Bidirectional pins: D0–D23, SCLK1, RFS1, TFS1, SCLK0, RFS0, TFS0.
3
4
Three-stateable pins: A0–A13, D0–D23, PMS, DMS, BMS, RD, WR, DT1, SCLK1, RSF1, TFS1, DT0, SCLK0, RFS0, TFS0.
0 V on BR, CLKIN Active (to force three-state condition).
All outputs are CMOS and will drive to VDD and GND with no dc loads.
Guaranteed but not tested.
5
6
7
8
Applies to PLCC package type.
9Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
ABSO LUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.5 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating T emperature Range (Ambient) . . . . –40°C to +85°C
Storage T emperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead T emperature (5 sec) PLCC . . . . . . . . . . . . . . . . +280°C
*Stresses greater than those listed above may cause permanent damage to the
device. T hese are stress ratings only, and functional operation of the device at these
or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
REV. 0
–16–
ADSP-2104/ADSP-2109
SPECIFICATIONS (ADSP-2104L/ADSP-2109L)
SUPPLY CURRENT & POWER (ADSP-2104L/ADSP-2109L)
P aram eter
Test Conditions
Min
Max
Unit
IDD
IDD
Supply Current (Dynamic)1
Supply Current (Idle)1, 3
@ VDD = max, tCK = 72.3 ns2
@ VDD = max, tCK = 72.3 ns
14
4
mA
mA
NOT ES
1Current reflects device operating with no output loads.
2VIN = 0.4 V and 2.4 V.
3Idle refers to ADSP-2104L/ADSP-2109L state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND.
For typical supply current (internal power dissipation) figures, see Figure 13.
1,2
IDLE DYNAMIC
50
48mW
45
V
= 3.30V
37mW
40
35
30
25
20
DD
V
= 3.6V
DD
29mW
24mW
19mW
15mW
V
= 3.0V
DD
15
10
5
0
5.00
7.00
10.00
13.83
15.00
FREQUENCY – MHz
3
1
IDD IDLE n MODES
IDD IDLE
14
14
12
10
13mW
13mW
10mW
12
10
IDD IDLE
V
= 3.6V
DD
9mW
= 3.30V
9mW
8
8
6
V
DD
8mW
7mW
6mW
IDLE 16
6mW
5mW
6
4
V
= 3.0V
5mW
4mW
DD
IDLE 128
4
2
0
2
0
5.00
7.00
10.00
13.83
15.00
5.00
7.00
10.00
13.83
15.00
FREQUENCY – MHz
FREQUENCY – MHz
1
2
POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
IDLE REFERS TO ADSP-2104L/ADSP-2109L OPERATION DURING EXECUTION OF IDLE INSTRUCTION.
DEASSERTED PINS ARE DRIVEN TO EITHER V OR GND.
DD
MAXIMUM POWER DISSIPATION AT V = 3.6V DURING EXECUTION OF IDLE n INSTRUCTION.
3
DD
Figure 13. ADSP-2104L/ADSP-2109L Power (Typical) vs. Frequency
REV. 0
–17–
ADSP-2104/ADSP-2109
SPECIFICATIONS (ADSP-2104L/ADSP-2109L)
P O WER D ISSIP ATIO N EXAMP LE
CAP ACITIVE LO AD ING
T o determine total power dissipation in a specific application,
the following equation should be applied for each output:
Figures 14 and 15 show capacitive loading characteristics.
2
C × VDD × f
30
25
C = load capacitance, f = output switching frequency.
Exam ple:
V
DD
= 3.0V
20
15
In an ADSP-2104L application where external data memory is
used and no other outputs are active, power dissipation is
calculated as follows:
10
5
Assumptions:
•
•
External data memory is accessed every cycle with 50% of the
address pins switching.
25
50
75
100 125 150
– pF
C
L
External data memory writes occur every other cycle with
50% of the data pins switching.
•
•
Each address and data pin has a 10 pF total load at the pin.
T he application operates at VDD = 3.3 V and tCK = 100 ns.
Figure 14. Typical Output Rise Tim e vs. Load Capacitance, CL
(at Maxim um Am bient Operating Tem perature)
2
Total Power Dissipation = PINT + (C × VDD × f )
PINT = internal power dissipation (from Figure 13).
+8
+6
2
(C × VDD × f ) is calculated for each output:
+4
# of
P ins × C
V
DD
= 3.0V
2
O utput
؋
VD D ؋
f +2
× 10 pF × 3.32 V × 10 MHz = 8.71 mW
× 10 pF × 3.32 V × 5 MHz = 4.90 mW
× 10 pF × 3.32 V × 5 MHz = 0.55 mW
× 10 pF × 3.32 V × 10 MHz = 1.09 mW
NOMINAL
–2
Address, DMS 8
Data, WR
RD
9
1
1
25
50
75
C
100 125 150
– pF
CLKOUT
L
15.25 mW
T otal power dissipation for this example = PINT + 15.25 mW.
Figure 15. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maxim um Am bient Operating Tem perature)
ENVIRO NMENTAL CO ND ITIO NS
Ambient T emperature Rating:
TAMB = T CASE – (PD × θC A
)
TCASE = Case T emperature in °C
PD = Power Dissipation in W
θC A = T hermal Resistance (Case-to-Ambient)
θJA = T hermal Resistance (Junction-to-Ambient)
θJC = T hermal Resistance (Junction-to-Case)
P ackage
JC
CA
JA
PLCC
27°C/W
16°C/W
11°C/W
–18–
REV. 0
ADSP-2104/ADSP-2109
SPECIFICATIONS (ADSP-2104L/ADSP-2109L)
TEST CO ND ITIO NS
Figure 16 shows voltage reference levels for ac measurements.
The decay time, tDECAY, is dependent on the capacitative load,
CL, and the current load, iL, on the output pin. It can be
approximated by the following equation:
V
DD
2
INPUT
CL × 0.5 V
tDECAY
=
iL
from which
V
DD
OUTPUT
2
tDIS = tMEASURED – tDECAY
is calculated. If multiple pins (such as the data bus) are dis-
abled, the measurement value is that of the last pin to stop
driving.
Figure 16. Voltage Reference Levels for AC Measurem ents
(Except Output Enable/Disable)
O utput D isable Tim e
O utput Enable Tim e
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. T he
output disable time (tDIS) is the difference of tMEASURED and
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. T he output enable time (t E NA) is the interval from
when a reference signal reaches a high or low voltage level to
when the output has reached a specified high or low trip point,
as shown in Figure 17. If multiple pins (such as the data bus)
are enabled, the measurement value is that of the first pin to
start driving.
t
DECAY, as shown in Figure 17. T he time tMEASURED is the
interval from when a reference signal reaches a high or low
voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage.
REFERENCE
SIGNAL
tMEASURED
tDIS
tENA
V
V
(MEASURED)
(MEASURED)
V
V
(MEASURED)
(MEASURED)
OH
OH
2.0V
1.0V
V
(MEASURED) – 0.5V
(MEASURED) +0.5V
OH
OUTPUT
V
OL
OL
OL
tDECAY
OUTPUT STARTS
DRIVING
OUTPUT STOPS
DRIVING
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE
APPROXIMATELY 1.5V.
Figure 17. Output Enable/Disable
I
OL
TO
OUTPUT
PIN
V
DD
2
50pF
I
OH
Figure 18. Equivalent Device Loading for AC Measurem ents
(Except Output Enable/Disable)
REV. 0
–19–
ADSP-2104/ADSP-2109
TIMING PARAMETERS (ADSP-2104/ADSP-2109)
GENERAL NO TES
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add parameters to derive longer times.
Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. T iming requirements guarantee that the
processor operates correctly with other devices.
TIMING NO TES
MEMO RY REQ UIREMENTS
Switching characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
T he table below shows common memory device specifications
and the corresponding ADSP-2104/ADSP-2109 timing
parameters, for your convenience.
Mem ory
AD SP -2104/AD SP -2109
Tim ing
D evice
Specification
Tim ing
P aram eter
P aram eter
D efinition
Address Setup to Write Start
Address Setup to Write End
Address Hold Time
Data Setup Time
tASW
tAW
tWRA
tDW
tDH
A0–A13, DMS, PMS Setup before WR Low
A0–A13, DMS, PMS Setup before WR Deasserted
A0–A13, DMS, PMS Hold after WR Deasserted
Data Setup before WR High
Data Hold Time
Data Hold after WR High
OE to Data Valid
Address Access Time
tRDD
tAA
RD Low to Data Valid
A0–A13, DMS, PMS, BMS to Data Valid
–20–
REV. 0
ADSP-2104/ADSP-2109
TIMING PARAMETERS (ADSP-2104/ADSP-2109)
CLO CK SIGNALS & RESET
Frequency
20 MH z
D ependency
P aram eter
Min
Max
Min
Max
Unit
Timing Requirement:
tCK
CLKIN Period
50
20
20
250
150
ns
ns
ns
ns
tCKL
tCKH
tRSP
CLKIN Width Low
CLKIN Width High
RESET Width Low
20
20
5tCK
1
Switching Characteristic:
tCPL
tCPH
tCKOH
CLKOUT Width Low
CLKOUT Width High
CLKIN High to CLKOUT High
15
15
0
0.5tCK – 10
0.5tCK – 10
ns
ns
ns
20
NOT E
1Applies after powerup sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles, assuming stable CLKIN (not including crystal
oscillator startup time).
tCK
tCKH
CLKIN
tCKL
tCKOH
tCPH
CLKOUT
tCPL
Figure 19. Clock Signals
REV. 0
–21–
ADSP-2104/ADSP-2109
TIMING PARAMETERS (ADSP-2104/ADSP-2109)
INTERRUP TS & FLAGS
Frequency
20 MH z
D ependency
P aram eter
Min
Max
Min
Max
Unit
Timing Requirement:
tIFS
IRQx1 or FI Setup before
27.5
0.25tCK + 15
0.25tCK
ns
ns
CLKOUT Low2, 3
IRQx1 or FI Hold after CLKOUT
High2, 3
tIFH
12.5
Switching Characteristic:
tFOH FO Hold after CLKOUT High
tFOD FO Delay from CLKOUT High
0
0
ns
ns
15
NOTES
1IRQx=IRQ0, IRQ1, and IRQ2.
2If IRQx and FI inputs meet tIFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise they will be recognized
during the following cycle. (Refer to the “Interrupt Controller” section in Chapter 3, Program Control, of the ADSP-2100 Family User’s Manual for further
information on interrupt servicing.)
3Edge-sensitive interrupts require pulse widths greater than 10 ns. Level-sensitive interrupts must be held low until serviced.
CLKOUT
tFOD
tFOH
FLAG
OUTPUT(S)
tIFH
IRQx
FI
tIFS
Figure 20. Interrupts & Flags
–22–
REV. 0
ADSP-2104/ADSP-2109
TIMING PARAMETERS (ADSP-2104/ADSP-2109)
BUS REQ UEST/GRANT
Frequency
20 MH z
D ependency
P aram eter
Min
Max
Min
Max
Unit
Timing Requirement:
tBH
tBS
BR Hold after CLKOUT High1
17.5
32.5
0.25tCK + 5
0.25tCK + 20
ns
ns
BR Setup before CLKOUT Low1
Switching Characteristic:
tSD
CLKOUT High to DMS,
32.5
0.25tCK + 20 ns
PMS, BMS, RD, WR Disable
DMS, PMS, BMS, RD, WR
Disable to BG Low
BG High to DMS, PMS,
BMS, RD, WR Enable
tSDB
tSE
0
0
ns
ns
ns
0
0
tSEC
DMS, PMS, BMS, RD, WR
Enable to CLKOUT High
2.5
0.25tCK – 10
NOTES
1If BR meets the tBS and tBH setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle. BR requires
a pulse width greater than 10 ns.
Note: BG is asserted in the cycle after BR is recognized. No external synchronization circuit is needed when BR is generated as an asynchronous signal.
tBH
CLKOUT
BR
tBS
CLKOUT
PMS, DMS
BMS, RD
tSD
tSEC
WR
BG
tSDB
tSE
Figure 21. Bus Request/Grant
REV. 0
–23–
ADSP-2104/ADSP-2109
TIMING PARAMETERS (ADSP-2104/ADSP-2109)
MEMO RY READ
20 MH z
P aram eter
Min
Max
Unit
Timing Requirement:
tRDD
tAA
tRDH
RD Low to Data Valid
A0–A13, PMS, DMS, BMS to Data Valid
Data Hold from RD High
12
19.5
ns
ns
0
Switching Characteristic:
tRP
tCRD
tASR
RD Pulse Width
17
7.5
2.5
ns
ns
ns
CLKOUT High to RD Low
A0–A13, PMS, DMS, BMS Setup before
RD Low
22.5
tRDA
tRWR
A0–A13, PMS, DMS, BMS Hold after RD
Deasserted
RD High to RD or WR Low
3.5
20
ns
ns
Frequency D ependency
(CLKIN ≤ 20 MH z)
P aram eter
Min
Max
Unit
Timing Requirement:
tRDD RD Low to Data Valid
0.5tCK – 13 + w
0.75tCK – 18 + w
ns
ns
tAA
A0–A13, PMS, DMS, BMS to Data Valid
tRDH Data Hold from RD High
0
Switching Characteristic:
tRP
RD Pulse Width
0.5tCK – 8 + w
0.25tCK – 5
ns
ns
tCRD CLKOUT High to RD Low
tASR A0–A13, PMS, DMS, BMS Setup before
RD Low
0.25tCK + 10
0.25tCK – 10
ns
tRDA A0–A13, PMS, DMS, BMS Hold after RD
Deasserted
tRWR RD High to RD or WR Low
0.25tCK – 9
0.5tCK – 5
ns
ns
NOT E
w = wait states × tCK.
CLKOUT
A0 – A13
DMS, PMS
BMS
tRDA
RD
D
tASR
tCRD
tRP
tRWR
tRDD
tRDH
tAA
WR
Figure 22. Mem ory Read
–24–
REV. 0
ADSP-2104/ADSP-2109
TIMING PARAMETERS (ADSP-2104/ADSP-2109)
MEMO RY WRITE
20 MH z
P aram eter
Min
Max
Unit
Switching Characteristic:
tDW
tDH
tWP
tWDE
tASW
Data Setup before WR High
Data Hold after WR High
WR Pulse Width
WR Low to Data Enabled
A0–A13, DMS, PMS Setup before
WR Low
12
2.5
17
0
ns
ns
ns
ns
ns
2.5
tDDR
tCWR
tAW
Data Disable before WR or RD Low
CLKOUT High to WR Low
A0–A13, DMS, PMS, Setup before WR
Deasserted
2.5
7.5
15.5
ns
ns
ns
22.5
tWRA
A0–A13, DMS, PMS Hold after WR
Deasserted
WR High to RD or WR Low
3.5
20
ns
ns
tWWR
Frequency D ependency
(CLKIN ≤ 20 MH z)
P aram eter
Min
Max
Unit
Switching Characteristic:
tDW Data Setup before WR High
0.5tCK – 13 + w
0.25tCK – 10
0.5tCK – 8 + w
0
ns
ns
ns
tDH
tWP
Data Hold after WR High
WR Pulse Width
tWDE WR Low to Data Enabled
tASW A0–A13, DMS, PMS Setup before WR Low
tDDR Data Disable before WR or RD Low
tCWR CLKOUT High to WR Low
0.25tCK – 10
0.25tCK – 10
0.25tCK – 5
ns
ns
ns
0.25tCK + 10
tAW
A0–A13, DMS, PMS, Setup before WR
Deasserted
0.75tCK – 22 + w
ns
tWRA A0–A13, DMS, PMS Hold after WR
Deasserted
tWWR WR High to RD or WR Low
0.25tCK – 9
0.5tCK – 5
ns
ns
CLKOUT
A0 – A13
DMS, PMS
tWRA
WR
tASW
tCWR
tWP
tWWR
tAW
tDH
tDDR
D
tDW
tWDE
RD
Figure 23. Mem ory Write
–25–
REV. 0
ADSP-2104/ADSP-2109
TIMING PARAMETERS (ADSP-2104/ADSP-2109)
SERIAL P O RTS
Frequency
13.824 MH z*
D ependency
P aram eter
Min
Max
Min
Max
Unit
Timing Requirement:
tSCK
tSCS
tSCH
tSCP
SCLK Period
72.3
8
10
28
ns
ns
ns
ns
DR/T FS/RFS Setup before SCLK Low
DR/T FS/RFS Hold after SCLK Low
SCLKIN Width
Switching Characteristic:
tCC
CLKOUT High to SCLKOUT
18.1
0
33.1
20
0.25tCK
0.25tCK + 15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCDE SCLK High to DT Enable
tSCDV SCLK High to DT Valid
tRH
tRD
tSCDH DT Hold after SCLK High
tT DE T FS (Alt) to DT Enable
tT DV T FS (Alt) to DT Valid
tSCDD SCLK High to DT Disable
tRDV RFS (Multichannel, Frame Delay Zero)
to DT Valid
T FS/RFSOUT Hold after SCLK High
T FS/RFSOUT Delay from SCLK High
20
18
25
20
*Maximum serial port operating frequency is 13.824 MHz.
CLKOUT
SCLK
tCC
tCC
tSCK
tSCP
tSCS tSCH
tSCP
DR
RFSIN
TFSIN
tRD
tRH
RFSOUT
TFSOUT
tSCDD
tSCDV
tSCDE
tSCDH
DT
tTDE
tTDV
TFS
( ALTERNATE
FRAME MODE )
tRDV
RFS
( MULTICHANNEL MODE,
FRAME DELAY 0 {MFD = 0} )
Figure 24. Serial Ports
–26–
REV. 0
ADSP-2104/ADSP-2109
Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. T iming requirements guarantee that the
processor operates correctly with other devices.
TIMING PARAMETERS (ADSP-2104L/ADSP-2109L)
GENERAL NO TES
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add parameters to derive longer times.
MEMO RY REQ UIREMENTS
T he table below shows common memory device specifications
and the corresponding ADSP-2104L/ADSP-2109L timing
parameters, for your convenience.
TIMING NO TES
Switching characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
AD SP -2104L/AD SP -2109L
Mem ory Specification
Tim ing P aram eter
Tim ing P aram eter D efinition
Address Setup to Write Start
Address Setup to Write End
Address Hold Time
Data Setup Time
tASW
tAW
tWRA
tDW
tDH
A0–A13, DMS, PMS Setup before WR Low
A0–A13, DMS, PMS Setup before WR Deasserted
A0–A13, DMS, PMS Hold after WR Deasserted
Data Setup before WR High
Data Hold Time
Data Hold after WR High
OE to Data Valid
Address Access Time
tRDD
tAA
RD Low to Data Valid
A0–A13, DMS, PMS, BMS to Data Valid
REV. 0
–27–
ADSP-2104/ADSP-2109
TIMING PARAMETERS (ADSP-2104L/ADSP-2109L)
CLO CK SIGNALS & RESET
Frequency
13.824 MH z
Min Max
D ependency
P aram eter
Min
Max
Unit
Timing Requirement:
tCK
CLKIN Period
72.3
20
20
361.5
150
ns
ns
ns
ns
tCKL
tCKH
tRSP
CLKIN Width Low
CLKIN Width High
RESET Width Low
20
20
5tCK
1
Switching Characteristic:
tCPL
tCPH
tCKOH
CLKOUT Width Low
CLKOUT Width High
CLKIN High to CLKOUT High
26.2
26.2
0
0.5tCK – 10
0.5tCK – 10
ns
ns
ns
20
NOTE
1Applies after powerup sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator startup time).
tCK
tCKH
CLKIN
tCKL
tCKOH
tCPH
CLKOUT
tCPL
Figure 25. Clock Signals
–28–
REV. 0
ADSP-2104/ADSP-2109
TIMING PARAMETERS (ADSP-2104L/ADSP-2109L)
INTERRUP TS & FLAGS
Frequency
13.824 MH z
D ependency
P aram eter
Min
Max
Min
Max
Unit
Timing Requirement:
tIFS
tIFH
IRQx1 or FI Setup before CLKOUT Low2, 3
33.1
18.1
0.25tCK + 15
0.25tCK
ns
ns
IRQx1 or FI Hold after CLKOUT High2, 3
Switching Characteristic:
tFOH FO Hold after CLKOUT High
tFOD FO Delay from CLKOUT High
0
ns
ns
15
NOTES
1IRQx=IRQ0, IRQ1, and IRQ2.
2If IRQx and FI inputs meet tIFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise they will be recognized during the
following cycle. (Refer to the “Interrupt Controller” section in Chapter 3, Program Control, of the ADSP-2100 Family User’s Manual for further information on
interrupt servicing.)
3Edge-sensitive interrupts require pulse widths greater than 10 ns. Level-sensitive interrupts must be held low until serviced.
CLKOUT
tFOD
tFOH
FLAG
OUTPUT(S)
tIFH
IRQx
FI
tIFS
Figure 26. Interrupts & Flags
REV. 0
–29–
ADSP-2104/ADSP-2109
TIMING PARAMETERS (ADSP-2104L/ADSP-2109L)
BUS REQ UEST/GRANT
Frequency
13.824 MH z
D ependency
P aram eter
Min
Max
Min
Max
Unit
Timing Requirement:
tBH
tBS
BR Hold after CLKOUT High1
23.1
38.1
0.25tCK + 5
0.25tCK + 20
ns
ns
BR Setup before CLKOUT Low1
Switching Characteristic:
tSD
tSDB
tSE
CLKOUT High to DMS, PMS, BMS, RD, WR Disable
DMS, PMS, BMS, RD, WR Disable to BG Low
BG High to DMS, PMS, BMS, RD, WR Enable
38.1
0.25tCK + 20
ns
ns
ns
ns
0
0
0
0
tSEC
DMS, PMS, BMS, RD, WR Enable to CLKOUT High 8.1
0.25tCK – 10
NOTES
1If BR meets the tBS and tBH setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle. BR
requires a pulse width greater than 10 ns.
Note: BG is asserted in the cycle after BR is recognized. No external synchronization circuit is needed when BR is generated as an asynchronous signal.
tBH
CLKOUT
BR
tBS
CLKOUT
PMS, DMS
BMS, RD
tSD
tSEC
WR
BG
tSDB
tSE
Figure 27. Bus Request/Grant
–30–
REV. 0
ADSP-2104/ADSP-2109
TIMING PARAMETERS (ADSP-2104L/ADSP-2109L)
MEMO RY READ
Frequency
13.824 MH z
D ependency
P aram eter
Min
Max
Min
Max
Unit
Timing Requirement:
tRDD
tAA
tRDH
RD Low to Data Valid
A0–A13, PMS, DMS, BMS to Data Valid
Data Hold from RD High
23.2
36.2
0.5tCK – 13 + w
0.75tCK – 18 + w
ns
ns
ns
0
0
Switching Characteristic:
tRP
RD Pulse Width
CLKOUT High to RD Low
A0–A13, PMS, DMS, BMS Setup before RD Low
A0–A13, PMS, DMS, BMS Hold after RD Deasserted
RD High to RD or WR Low
28.2
13.1
8.1
9.1
31.2
0.5tCK – 8 + w
0.25tCK – 5
0.25tCK – 10
0.25tCK – 9
0.5tCK – 5
ns
ns
ns
ns
ns
tCRD
tASR
tRDA
tRWR
28.1
0.25tCK + 10
w = wait states × tCK.
CLKOUT
A0 – A13
DMS, PMS
BMS
tRDA
RD
D
tASR
tCRD
tRP
tRWR
tRDD
tRDH
tAA
WR
Figure 28. Mem ory Read
REV. 0
–31–
ADSP-2104/ADSP-2109
TIMING PARAMETERS (ADSP-2104L/ADSP-2109L)
MEMO RY WRITE
Frequency
13.824 MH z
D ependency
P aram eter
Min
Max
Min
Max
Unit
Switching Characteristic:
tDW
tDH
tWP
tWDE
tASW
tDDR
tCWR
tAW
Data Setup before WR High
Data Hold after WR High
WR Pulse Width
WR Low to Data Enabled
A0–A13, DMS, PMS Setup before WR Low
Data Disable before WR or RD Low
CLKOUT High to WR Low
A0–A13, DMS, PMS, Setup before WR Deasserted
A0–A13, DMS, PMS Hold After WR Deasserted
WR High to RD or WR Low
23.2
8.1
28.2
0
8.1
8.1
13.1
32.2
9.1
0.5tCK – 13 + w
0.25tCK – 10
0.5tCK – 8 + w
ns
ns
ns
0.25tCK – 10
0.25tCK – 10
0.25tCK – 5
0.75tCK – 22 + w
0.25tCK – 9
ns
ns
ns
ns
ns
ns
28.1
0.25tCK + 10
tWRA
tWWR
31.2
0.5tCK – 5
w = wait states × tCK.
CLKOUT
A0 – A13
DMS, PMS
tWRA
WR
tASW
tCWR
tWP
tWWR
tAW
tDH
tDDR
D
tDW
tWDE
RD
Figure 29. Mem ory Write
–32–
REV. 0
ADSP-2104/ADSP-2109
TIMING PARAMETERS (ADSP-2104L/ADSP-2109L)
SERIAL P O RTS
Frequency
13.824 MH z
D ependency
P aram eter
Min
Max
Min
Max
Unit
Timing Requirement:
tSCK
tSCS
tSCH
tSCP
SCLK Period
72.3
8
10
28
ns
ns
ns
ns
DR/T FS/RFS Setup before SCLK Low
DR/T FS/RFS Hold after SCLK Low
SCLKin Width
Switching Characteristic:
tCC
CLKOUT High to SCLKout
SCLK High to DT Enable
SCLK High to DT Valid
T FS/RFSout Hold after SCLK High
T FS/RFSout Delay from SCLK High
DT Hold after SCLK High
T FS (alt) to DT Enable
18.1
0
33.1
20
0.25tCK
0.25tCK + 15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCDE
tSCDV
tRH
0
tRD
20
tSCDH
tT DE
tT DV
tSCDD
tRDV
0
0
T FS (alt) to DT Valid
18
25
20
SCLK High to DT Disable
RFS (Multichannel, Frame Delay Zero)
to DT Valid
CLKOUT
SCLK
tCC
tCC
tSCK
tSCP
tSCS tSCH
tSCP
DR
RFSIN
TFSIN
tRD
tRH
RFSOUT
TFSOUT
tSCDD
tSCDV
tSCDE
tSCDH
DT
tTDE
tTDV
TFS
( ALTERNATE
FRAME MODE )
tRDV
RFS
( MULTICHANNEL MODE,
FRAME DELAY 0 {MFD = 0} )
Figure 30. Serial Ports
REV. 0
–33–
ADSP-2104/ADSP-2109
P IN CO NFIGURATIO NS
68-Lead P LCC
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
GND
D19
D20
D21
D22
D23
PIN 1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
D2
D1
D0
IDENTIFIER
V
DD
SCLK1
FI (DR1)
IRQ0 (RFS1)
IRQ1 (TFS1)
FO (DT1)
SCLK0
DR0
ADSP-2104
ADSP-2104L
ADSP-2109
ADSP-2109L
V
DD
MMAP
BR
TOP VIEW
(PINS DOWN)
IRQ2
RESET
A0
GND
A1
RFS0
A2
TFS0
A3
DT0
A4
RD
V
WR
DD
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
P LCC
P in
P LCC
P in
P LCC
P in
P LCC
P in
Num ber Nam e
Num ber Nam e
Num ber Nam e
Num ber Nam e
1
2
3
4
5
6
7
8
D11
GND
D12
D13
D14
D15
D16
D17
D18
GND
D19
D20
D21
D22
D23
VDD
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
BR
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
FO
(DT1)
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
A12
A13
IRQ2
RESET
A0
A1
A2
A3
A4
VDD
A5
A6
GND
A7
A8
A9
A10
A11
IRQ1 (TFS1)
IRQ0 (RFS1)
FI
SCLK1
VDD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
PMS
DMS
BMS
BG
XT AL
CLKIN
CLKOUT
WR
RD
(DR1)
9
10
11
12
13
14
15
16
17
DT 0
T FS0
RFS0
GND
DR0
MMAP
SCLK0
–34–
REV. 0
ADSP-2104/ADSP-2109
O UTLINE D IMENSIO NS
AD SP -2104/AD SP -2109
68-Lead P lastic Leaded Chip Car r ier (P LCC)
9
61
e
PIN 1 IDENTIFIER
D
2
b
BOTTOM VIEW
(PINS UP)
TOP VIEW
(PINS DOWN)
b
1
D
1
A
1
D
A
INCHES
TYP
MILLIMETERS
SYMBOL MIN
MAX
MIN
TYP
MAX
A
0.169 0.172 0.175
0.104
4.29 14.37
12.64
4.45
A1
b
0.017 0.018 0.019
0.027 0.028 0.029
0.985 0.990 0.995
0.950 0.952 0.954
0.895 0.910 0.925
0.050
0.43 10.46
0.69 10.71
0.48
0.74
b1
D
25.02 25.15 25.27
24.13 24.18 24.23
22.73 23.11 23.50
11.27
D1
D2
e
0.004
10.10
REV. 0
–35–
ADSP-2104/ADSP-2109
O RD ERING GUID E
Am bient
Tem perature
Range
Instruction
Rate
P ackage
D escription
P ackage
O ption
P art Num ber*
ADSP-2104KP-80
ADSP-2109KP-80
0°C to +70°C
0°C to +70°C
20.0 MHz
20.0 MHz
68-Lead PLCC
68-Lead PLCC
P-68A
P-68A
ADSP-2104LKP-55
ADSP-2109LKP-55
0°C to +70°C
0°C to +70°C
13.824 MHz
13.824 MHz
68-Lead PLCC
68-Lead PLCC
P-68A
P-68A
*K = Commercial T emperature Range (0°C to +70°C).
*P = PLCC (Plastic Leaded Chip Carrier).
–36–
REV. 0
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