ADSP-21061_技术文档

®

ADSP-2106x SHARC

a

DSP Microcomputer Family

ADSP-21061/ADSP-21061L

Pin-Compatible with ADSP-21060 (4 Mbit) and

ADSP-21062 (2 Mbit)

SUMMARY

High Performance Signal Computer for Speech, Sound,

Graphics and Imaging Applications

Super Harvard Architecture Computer (SHARC)—

Four Independent Buses for Dual Data, Instructions,

and I/O

32-Bit IEEE Floating-Point Computation Units—

Multiplier, ALU and Shifter

1 Megabit On-Chip SRAM Memory and Integrated I/O

Peripherals—A Complete System-On-A-Chip

Integrated Multiprocessing Features

Flexible Data Formats and 40-Bit Extended Precision

32-Bit Single-Precision and 40-Bit Extended-Precision

IEEE Floating-Point Data Formats

32-Bit Fixed-Point Data Format, Integer and Fractional,

with 80-Bit Accumulators

Parallel Computations

Single-Cycle Multiply and ALU Operations in Parallel with

Dual Memory Read/Writes and Instruction Fetch

Multiply with Add and Subtract for Accelerated FFT

Butterfly Computation

KEY FEATURES

50 MIPS, 20 ns Instruction Rate, Single-Cycle Instruction

Execution

120 MFLOPS Peak, 80 MFLOPS Sustained Performance

Dual Data Address Generators with Modulo and Bit-

Reverse Addressing

Efficient Program Sequencing with Zero-Overhead

Looping: Single-Cycle Loop Setup

IEEE JTAG Standard 1149.1 Test Access Port and

On-Chip Emulation

1024-Point Complex FFT Benchmark: 0.37 ms (18,221 Cycles)

1 Megabit Configurable On-Chip SRAM

Dual-Ported for Independent Access by Core Processor

and DMA

Configurable as 32K Words Data Memory (32-Bit), 16K

Words Program Memory (48-Bit) or Combinations of

Both Up to 1 Mbit

Off-Chip Memory Interfacing

4-Gigawords Addressable (32-Bit Address)

Programmable Wait State Generation, Page-Mode DRAM

Support

240-Lead MQFP Package

225-Ball Plastic Ball Grid Array (PBGA)

DUAL-PORTED SRAM

CORE PROCESSOR

INSTRUCTION

TIMER

JTAG

TWO INDEPENDENT

7

CACHE

DUAL-PORTED BLOCKS

32 x 48-BIT

TEST &

EMULATION

PROCESSOR PORT

ADDR DATA

I/O PORT

DATA ADDR

ADDR

DATA

ADDR

DAG1

DAG2

PROGRAM

SEQUENCER

8 x 4 x 32

8 x 4 x 24

EXTERNAL

PORT

IOD

48

IOA

17

24

32

PM ADDRESS BUS

32

48

ADDR BUS

MUX

DM ADDRESS BUS

MULTIPROCESSOR

INTERFACE

PM DATA BUS

DM DATA BUS

48

BUS

CONNECT

(PX)

DATA BUS

MUX

40/32

HOST PORT

DATA

REGISTER

FILE

4

DMA

IOP

REGISTERS

(MEMORY MAPPED)

CONTROLLER

6

16 x 40-BIT

BARREL

SHIFTER

MULTIPLIER

ALU

SERIAL PORTS

(2)

CONTROL,

STATUS &

DATA BUFFERS

I/O PROCESSOR

Figure 1. ADSP-21061/ADSP-21061L Block Diagram

SHARC is a registered trademark of Analog Devices, Inc.

REV. B

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

ADSP-21061/ADSP-21061L

DMA Controller

6 DMA Channels

Multiprocessing

Glueless Connection for Scalable DSP Multiprocessing

Architecture

Distributed On-Chip Bus Arbitration for Parallel Bus

Connect of Up To Six ADSP-21061s Plus Host

300 Mbytes/s Transfer Rate Over Parallel Bus

Background DMA Transfers at 50 MHz, in Parallel with

Full-Speed Processor Execution

Performs Transfers Between ADSP-21061 Internal Memory

and External Memory, External Peripherals, Host

Processor, or Serial Ports

Serial Ports

Host Processor Interface

Efficient Interface to 16- and 32-Bit Microprocessors

Host can Directly Read/Write ADSP-21061 Internal Memory

Two 40 Mbit/s Synchronous Serial Ports

Independent Transmit and Receive Functions

3- to 32-Bit Data Word Width

␮-Law/A-Law Hardware Companding

TDM Multichannel Mode

Multichannel Signaling Protocol

TABLE OF CONTENTS

ADSP-21061L EZ-ICE Emulator (Jumpers in Place) . . . 12

Figure 6. JTAG Scan Path Connections for Multiple

ADSP-21061/ADSP-21061L Systems . . . . . . . . . . . . . . . 12

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 3

ADSP-21000 FAMILY CORE ARCHITECTURE . . . . . . . 4

ADSP-21061 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . 4

DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . 8

ADDITIONAL INFORMATION . . . . . . . . . . . . . . . . . . . . . 8

PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

TARGET BOARD CONNECTOR FOR EZ-ICE^®

PROBE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

RECOMMENDED OPERATING CONDITIONS (5V) . 14

ELECTRICAL CHARACTERISTICS (5 V) . . . . . . . . . . . 14

POWER DISSIPATION ADSP-21061 (5 V) . . . . . . . . . . . . 15

RECOMMENDED OPERATING CONDITIONS (3.3V) 16

ELECTRICAL CHARACTERISTICS (3.3 V) . . . . . . . . . . 16

POWER DISSIPATION ADSP-21061L (3.3 V) . . . . . . . . . 17

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 18

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 18

Memory Read—Bus Master . . . . . . . . . . . . . . . . . . . . . . . 21

Memory Write—Bus Master . . . . . . . . . . . . . . . . . . . . . . 22

Synchronous Read/Write—Bus Master . . . . . . . . . . . . . . 23

Synchronous Read/Write—Bus Slave . . . . . . . . . . . . . . . . 25

Multiprocessor Bus Request and Host Bus Request . . . . . 26

Asynchronous Read/Write—Host to ADSP-21061 . . . . . . 28

Three-State Timing—Bus Master, Bus Slave,

HBR, SBTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

DMA Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

JTAG Test Access Port and Emulation . . . . . . . . . . . . . . . 37

OUTPUT DRIVE CURRENTS . . . . . . . . . . . . . . . . . . . . . 38

POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . . 41

240-LEAD METRIC MQFP PIN CONFIGURATIONS . . 42

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . 43, 44

ADSP-21061L 225-Ball Plastic Ball Grid Array (PBGA)

Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

225-Ball Plastic Ball Grid Array (PBGA) Package Pinout . . . . . 46

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 47

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 7. JTAG Clocktree for Multiple ADSP-21061/

ADSP-21061L Systems . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 8. Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 9. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 10. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 11. Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 12. Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 13. Memory Read—Bus Master . . . . . . . . . . . . . . . . 21

Figure 14. Memory Write—Bus Master . . . . . . . . . . . . . . . 22

Figure 15. Synchronous Read/Write—Bus Master . . . . . . . 24

Figure 16. Synchronous Read/Write—Bus Slave . . . . . . . . . 25

Figure 17. Multiprocessor Bus Request and Host Bus

Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 18a. Synchronous REDY Timing . . . . . . . . . . . . . . 28

Figure 18b. Asynchronous Read/Write—Host to

ADSP-21061/ADSP-21061L . . . . . . . . . . . . . . . . . . . . . . 29

Figure 19a. Three-State Timing (Bus Transition Cycle,

SBTS Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 19b. Three-State Timing (Host Transition Cycle) . . 31

Figure 20. DMA Handshake Timing . . . . . . . . . . . . . . . . . 33

Figure 21. Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 22. External Late Frame Sync . . . . . . . . . . . . . . . . . 36

Figure 23. JTAG Test Access Port and Emulation . . . . . . . 37

Figure 24. Output Enable/Disable . . . . . . . . . . . . . . . . . . . 39

Figure 25. Equivalent Device Loading for AC Measurements

(Includes All Fixtures) . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 26. Voltage Reference Levels for AC Measurements

(Except Output Enable/Disable) . . . . . . . . . . . . . . . . . . . . 39

Figure 27. ADSP-2106x Typical Drive Currents

(V_DD= 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 28. Typical Output Rise Time (10%–90% V_DD) vs.

Load Capacitance (V_DD= 5 V) . . . . . . . . . . . . . . . . . . . . 40

Figure 29. Typical Output Rise Time (0.8 V–2.0 V) vs. Load

Capacitance (V_DD= 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 30. Typical Output Delay or Hold vs. Load Capacitance

(at Maximum Case Temperature) (V_DD= 5 V) . . . . . . . . 40

Figure 31. ADSP-2106x Typical Drive Currents

FIGURES

(V_DD= 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 32. Typical Output Rise Time (10%–90% V_DD) vs.

Load Capacitance (V_DD= 3.3 V) . . . . . . . . . . . . . . . . . . . 40

Figure 33. Typical Output Rise Time (0.8 V–2.0 V) vs. Load

Capacitance (V_DD= 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 34. Typical Output Delay or Hold vs. Load Capacitance

(at Maximum Case Temperature) (V_DD= 3.3 V) . . . . . . . 41

Figure 1. ADSP-21061/ADSP-21061L Block Diagram . . . . 1

Figure 2. ADSP-21061/ADSP-21061L System . . . . . . . . . . . 4

Figure 3. Multiprocessing System . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. ADSP-21061/ADSP-21061L Memory Map . . . . . 7

Figure 5. Target Board Connector For ADSP-21061/

EZ-ICE is a registered trademark of Analog Devices, Inc.

REV. B

–2–

ADSP-21061/ADSP-21061L

S^®

GENERAL NOTE

Figure 1 shows a block diagram of the ADSP-21061/ADSP-

21061L, illustrating the following architectural features:

This data sheet represents production released specifications

for the ADSP-21061 5 V and ADSP-21061L 3.3 V proces-

sors. ADSP-21061 is used throughout this data sheet to refer to

both devices unless expressly noted.

Computation Units (ALU, Multiplier and Shifter) with a

Shared Data Register File

Data Address Generators (DAG1, DAG2)

Program Sequencer with Instruction Cache

Interval Timer

GENERAL DESCRIPTION

The ADSP-21061 is a member of the powerful SHARC family

of floating point processors. The SHARC—Super Harvard

Architecture Computer—are signal processing microcomputers

that offer new capabilities and levels of integration and perfor-

mance. The ADSP-21061 is a 32-bit processor optimized for

high performance DSP applications. The ADSP-21061 com-

bines the ADSP-21000 DSP core with a dual-ported on-chip

SRAM and an I/O processor with a dedicated I/O bus to form a

complete system-in-a-chip.

1 Mbit On-Chip SRAM

External Port for Interfacing to Off-Chip Memory and

Peripherals

Host Port & Multiprocessor Interface

DMA Controller

Serial Ports

JTAG Test Access Port

Figure 2 shows a typical single-processor system. A multi-

processing system is shown in Figure 3.

Fabricated in a high-speed, low-power CMOS process, the

ADSP-21061 has a 20 ns instruction cycle time operating at up

to 50 MIPS. With its on-chip instruction cache, the processor can

execute every instruction in a single cycle. Table I shows perfor-

mance benchmarks for the ADSP-21061/ADSP-21061L.

Table I. ADSP-21061/ADSP-21061L Benchmarks (@ 50 MHz)

1024-Pt. Complex FFT

(Radix 4, with Digit Reverse)

FIR Filter (per Tap)

IIR Filter (per Biquad)

Divide (y/x)

0.37 ms

18,221 Cycles

The ADSP-21061 SHARC combines a high-performance float-

ing-point DSP core with integrated, on-chip system features,

including a 1 Mbit SRAM memory, host processor interface,

DMA controller, serial ports and parallel bus connectivity for

glueless DSP multiprocessing.

20 ns

80 ns

120 ns

180 ns

1 Cycle

4 Cycles

6 Cycles

9 Cycles

Inverse Square Root (1/√x)

DMA Transfer Rate

300 Mbytes/s

REV. B

–3–

ADSP-21061/ADSP-21061L

ADSP-21000 FAMILY CORE ARCHITECTURE

The ADSP-21061 includes the following architectural features

of the ADSP-21000 family core. The ADSP-21061 is code and

function compatible with the ADSP-21060/ADSP-21062 and

the ADSP-21020.

Instruction Cache

The ADSP-21061 includes an on-chip instruction cache that

enables three-bus operation for fetching an instruction and two

data values. The cache is selective—only the instructions whose

fetches conflict with PM bus data accesses are cached. This

allows full-speed execution of core, looped operations such as

digital filter multiply-accumulates and FFT butterfly processing.

Independent, Parallel Computation Units

The arithmetic/logic unit (ALU), multiplier and shifter all per-

form single-cycle instructions. The three units are arranged in

parallel, maximizing computational throughput. Single multi-

function instructions execute parallel ALU and multiplier op-

erations. These computation units support IEEE 32-bit single-

precision floating-point, extended precision 40-bit floating-

point and 32-bit fixed-point data formats.

Data Address Generators with Hardware Circular Buffers

The ADSP-21061’s two data address generators (DAGs) imple-

ment circular data buffers in hardware. Circular buffers allow

efficient programming of delay lines and other data structures

required in digital signal processing, and are commonly used in

digital filters and Fourier transforms. The ADSP-21061 two

DAGs contain sufficient registers to allow the creation of up to

32 circular buffers (16 primary register sets, 16 secondary). The

DAGs automatically handle address pointer wraparound, reduc-

ing overhead, increasing performance and simplifying imple-

mentation. Circular buffers can start and end at any memory

location.

ADSP-21061/

ADSP-21061L

CS

1x CLOCK

TO GND

CLKIN

EBOOT

LBOOT

BMS

BOOT

EPROM

(OPTIONAL)

ADDR

DATA

3

IRQ

2-0

Flexible Instruction Set

4

ADDR

FLAG

31-0

ADDR

DATA

OE

WE

ACK

CS

3-0

The 48-bit instruction word accommodates a variety of parallel

operations, for concise programming. For example, the ADSP-

21061 can conditionally execute a multiply, an add, a subtract

and a branch, all in a single instruction.

TIMEXP

MEMORY

AND

PERIPHERALS

DATA

47-0

RD

WR

TCLK0

RCLK0

TFS0

RSF0

DT0

(OPTIONAL)

SERIAL

DEVICE

(OPTIONAL)

ACK

MS

3-0

ADSP-21061 FEATURES

Augmenting the ADSP-21000 family core, the ADSP-21061

adds the following architectural features:

PAGE

SBTS

SW

DR0

DMA DEVICE

(OPTIONAL)

DATA

ADRCLK

TCLK1

RCLK1

TFS1

RSF1

DT1

DMAR

Dual-Ported On-Chip Memory

1-2

SERIAL

DEVICE

(OPTIONAL)

DMAG

1-2

The ADSP-21061 contains 1 megabit of on-chip SRAM, orga-

nized as two banks of 0.5 Mbits each. Each bank has eight 16-

bit columns with 4K 16-bit words per column. Each memory

block is dual-ported for single-cycle, independent accesses by

the core processor and I/O processor or DMA controller. The

dual-ported memory and separate on-chip buses allow two data

transfers from the core and one from I/O, all in a single cycle

(see Figure 4 for the ADSP-21061 Memory Map).

CS

HBR

HOST

PROCESSOR

INTERFACE

(OPTIONAL)

DR1

HBG

REDY

RPBA

BR

ADDR

DATA

1-6

ID

2-0

CPA

RESET JTAG

7

On the ADSP-21061, the memory can be configured as a maxi-

mum of 32K words of 32-bit data, 64K words for 16-bit data,

16K words of 48-bit instructions (and 40-bit data) or combina-

tions of different word sizes up to 1 megabit. All the memory

can be accessed as 16-bit, 32-bit or 48-bit.

Figure 2. ADSP-21061/ADSP-21061L System

Data Register File

A general purpose data register file is used for transferring data

between the computation units and the data buses, and for

storing intermediate results. This 10-port, 32-register (16 pri-

mary, 16 secondary) register file, combined with the ADSP-

21000 Harvard architecture, allows unconstrained data flow

between computation units and internal memory.

A 16-bit floating-point storage format is supported that effec-

tively doubles the amount of data that may be stored on chip.

Conversion between the 32-bit floating-point and 16-bit floating-

point formats is done in a single instruction.

While each memory block can store combinations of code and

data, accesses are most efficient when one block stores data,

using the DM bus for transfers, and the other block stores in-

structions and data, using the PM bus for transfers. Using the

DM and PM buses in this way, with one dedicated to each

memory block, assures single-cycle execution with two data

transfers. In this case, the instruction must be available in the

cache. Single-cycle execution is also maintained when one of the

data operands is transferred to or from off-chip, via the ADSP-

21061’s external port.

Single-Cycle Fetch of Instruction and Two Operands

The ADSP-21061 features an enhanced Harvard architecture in

which the data memory (DM) bus transfers data and the pro-

gram memory (PM) bus transfers both instructions and data

(see Figure 1). With its separate program and data memory

buses and on-chip instruction cache, the processor can simulta-

neously fetch two operands and an instruction (from the cache),

all in a single cycle.

REV. B

–4–

ADSP-21061/ADSP-21061L

Off-Chip Memory and Peripherals Interface

Six channels of DMA are available on the ADSP-21061—four

via the serial ports, and two via the processor’s external port (for

either host processor, other ADSP-21061s, memory or I/O

transfers). Programs can be downloaded to the ADSP-21061

using DMA transfers. Asynchronous off-chip peripherals can

control two DMA channels using DMA Request/Grant lines

(DMAR_1-2, DMAG_1-2). Other DMA features include interrupt

generation upon completion of DMA transfers and DMA chain-

ing for automatic linked DMA transfers.

The ADSP-21061’s external port provides the processor’s inter-

face to off-chip memory and peripherals. The 4-gigaword off-

chip address space is included in the ADSP-21061’s unified

address space. The separate on-chip buses—for program

memory, data memory and I/O—are multiplexed at the external

port to create an external system bus with a single 32-bit address

bus and a single 48-bit (or 32-bit) data bus. The on-chip

Super Harvard Architecture provides three-bus performance,

while the off-chip unified address space gives flexibility to the

designer.

Serial Ports

The ADSP-21061 features two synchronous serial ports that

provide an inexpensive interface to a wide variety of digital and

mixed-signal peripheral devices. The serial ports can operate at

the full clock rate of the processor, providing each with a maxi-

mum data rate of 40 Mbit/s. Independent transmit and receive

functions provide greater flexibility for serial communications.

Serial port data can be automatically transferred to and from

on-chip memory via DMA. Each of the serial ports offers TDM

multichannel mode.

Addressing of external memory devices is facilitated by on-chip

decoding of high order address lines to generate memory bank

select signals. Separate control lines are also generated for sim-

plified addressing of page-mode DRAM. The ADSP-21061

provides programmable memory wait states and external memory

acknowledge controls to allow interfacing to DRAM and peripher-

als with variable access, hold and disable time requirements.

Host Processor Interface

The ADSP-21061’s host interface allows easy connection to

standard microprocessor buses, both 16-bit and 32-bit, with

little additional hardware required. Asynchronous transfers at

speeds up to the full clock rate of the processor are supported.

The host interface is accessed through the ADSP-21061’s exter-

nal port and is memory-mapped into the unified address space.

Two channels of DMA are available for the host interface; code

and data transfers are accomplished with low software overhead.

The serial ports can operate with little-endian or big-endian

transmission formats, with word lengths selectable from three

bits to 32 bits. They offer selectable synchronization and trans-

mit modes as well as optional µ-law or A-law companding.

Serial port clocks and frame syncs can be internally or externally

generated. The serial ports also include keyword and keymask

features to enhance interprocessor communication.

Multiprocessing

The host processor requests the ADSP-21061’s external bus

with the host bus request (HBR), host bus grant (HBG) and

ready (REDY) signals. The host can directly read and write the

internal memory of the ADSP-21061, and can access the

DMA channel setup and mailbox registers. Vector interrupt

support is provided for efficient execution of host commands.

The ADSP-21061 offers powerful features tailored to multipro-

cessing DSP systems. The unified address space allows direct

interprocessor accesses of each ADSP-21061’s internal memory.

Distributed bus arbitration logic is included on-chip for simple,

glueless connection of systems containing up to six ADSP-21061s

and a host processor. Master processor changeover incurs only

one cycle of overhead. Bus arbitration is selectable as either

fixed or rotating priority. Bus lock allows indivisible read-modify-

write sequences for semaphores. A vector interrupt is provided

for interprocessor commands. Maximum throughput for inter-

processor data transfer is 500 Mbytes/sec over the external port.

Broadcast writes allow simultaneous transmission of data to

all ADSP-21061s and can be used to implement reflective

semaphores.

DMA Controller

The ADSP-21061’s on-chip DMA controller allows zero-

overhead, nonintrusive data transfers without processor inter-

vention. The DMA controller operates independently and

invisibly to the processor core, allowing DMA operations to

occur while the core is simultaneously executing its program

instructions.

DMA transfers can occur between the ADSP-21061’s internal

memory and either external memory, external peripherals, or a

host processor. DMA transfers can also occur between the

ADSP-21061’s internal memory and its serial ports. DMA

transfers between external memory and external peripheral

devices are another option. External bus packing to 16-, 32-

or 48-bit words is performed during DMA transfers.

Program Booting

The internal memory of the ADSP-21061 can be booted at

system power-up from either an 8-bit EPROM or a host proces-

sor. Selection of the boot source is controlled by the BMS (Boot

Memory Select), EBOOT (EPROM Boot), and LBOOT (Host

Boot) pins. 32-bit and 16-bit host processors can be used for

booting. See the BMS pin in the Pin Function Descriptions

section of this data sheet.

REV. B

–5–

ADSP-21061/ADSP-21061L

ADSP-2106x #6

ADSP-2106x #5

ADSP-2106x #4

ADSP-2106x #3

ADDR

CLKIN

RESET

RPBA

31-0

DATA

47-0

3

011

ID

2-0

CONTROL

CPA

BR , BR

5

1-2

4-6

BR

3

ADSP-2106x #2

ADDR

CLKIN

31-0

DATA

47-0

RESET

RPBA

3

010

ID

2-0

CONTROL

CPA

BR , BR

5

1

3-6

BR

2

ADSP-2106x #1

1x

CLOCK

CLKIN

ADDR

DATA

ADDR

DATA

31-0

GLOBAL

MEMORY

RESET

47-0

AND

PERIPHERALS

(OPTIONAL)

OE

RD

WR

ACK

RPBA

WE

ACK

CS

3

001

ID

MS

2-0

3-0

CS

BMS

PAGE

SBTS

SW

BOOT

EPROM

(OPTIONAL)

ADDR

CONTROL

DATA

ADRCLK

CS

HBR

HBG

REDY

HOST

PROCESSOR

INTERFACE

(OPTIONAL)

ADDR

DATA

CPA

5

BR

2-6

BR

1

Figure 3. Multiprocessing System

REV. B

–6–

ADSP-21061/ADSP-21061L

0x0000 0000

0x0002 0000

0x0040 0000

IOP REGISTERS

BANK 0

INTERNAL

MEMORY

SPACE

MS

0

NORMAL WORD ADDRESSING

SHORT WORD ADDRESSING

DRAM

(OPTIONAL)

0x0004 0000

0x0008 0000

INTERNAL MEMORY SPACE

OF ADSP-2106x

BANK 1

BANK 2

MS

1

WITH ID=001

0x0010 0000

0x0018 0000

0x0020 0000

0x0028 0000

0x0030 0000

0x0038 0000

0x003F FFFF

INTERNAL MEMORY SPACE

OF ADSP-2106x

WITH ID=010

INTERNAL MEMORY SPACE

OF ADSP-2106x

MS

2

WITH ID=011

EXTERNAL

MEMORY

SPACE

MULTIPROCESSOR

MEMORY SPACE

INTERNAL MEMORY SPACE

OF ADSP-2106x

WITH ID=100

BANK 3

3

INTERNAL MEMORY SPACE

OF ADSP-2106x

WITH ID=101

BANK SIZE IS

SELECTED BY

MSIZE BIT FIELD OF

SYSCON

INTERNAL MEMORY SPACE

OF ADSP-2106x

WITH ID=110

REGISTER.

BROADCAST WRITE

TO ALL

NONBANKED

ADSP-2106xs

NORMAL WORD ADDRESSING: 32-BIT DATA WORDS

48-BIT INSTRUCTION WORDS

SHORT WORD ADDRESSING: 16-BIT DATA WORDS

0xFFFF FFFF

Figure 4. ADSP-21061/ADSP-21061L Memory Map

REV. B

–7–

ADSP-21061/ADSP-21061L

Porting Code from ADSP-21060 or ADSP-21062 to the

ADSP-21061

The ADSP-21061 is pin compatible with the ADSP-21060/

ADSP-21061/ADSP-21062 processors. The ADSP-21061 pins

that correspond to the Link Port pins of the ADSP-21060/

ADSP-21062 are no-connects.

The same EZ-ICE hardware can be used for the ADSP-21060/

ADSP-21062, to fully emulate the ADSP-21061, with the excep-

tion of displaying and modifying the two new SPORTS

registers. The emulator will not display these two registers,

but your code can use them.

Analog Devices ADSP-21000 Family Development Software

includes an easy to use Assembler based on an algebraic syntax,

Assembly Library/Librarian, Linker, instruction-level Simulator,

an ANSI C optimizing Compiler, the CBUG™ C Source—

Level Debugger and a C Runtime Library including DSP and

mathematical functions. The Optimizing Compiler includes

Numerical C extensions based on the work of the ANSI Nu-

merical C Extensions Group. Numerical C provides extensions

to the C language for array selections, vector math operations,

complex data types, circular pointers and variably dimensioned

arrays. The ADSP-21000 Family Development Software is

available for both the PC and Sun platforms.

The ADSP-21061 is object code compatible with the ADSP-

21060/ADSP-21062 except for the following functional

changes:

The ADSP-21061 memory is organized into two blocks

with eight columns that are 4K deep per block. The

ADSP-21060/ADSP-21062 memory has 16 columns per block.

Link port functions are not available.

Handshake external port DMA pins DMAR2 and DMAG2

are assigned to external port DMA Channel 6 instead of

Channel 8.

2-D DMA capability of the SPORT is not available.

The modify registers in SPORT DMA are not programmable.

The EZ-ICE Emulator uses the IEEE 1149.1 JTAG test access

port of the ADSP-21061 processor to monitor and control the

target board processor during emulation. The EZ-ICE provides

full-speed emulation, allowing inspection and modification of

memory, registers, and processor stacks. Nonintrusive in-circuit

emulation is assured by the use of the processor’s JTAG inter-

face—the emulator does not affect target system loading or

timing.

On the ADSP-21061, Block 0 starts at the beginning of internal

memory, normal word address 0x0002 0000. Block 1 starts at

the end of Block 0, with contiguous addresses. The remaining

addresses in internal memory are divided into blocks that alias

into Block 1. This allows any code or data stored in Block 1 on

the ADSP-21062 to retain the same addresses on the ADSP-

21061—these addresses will alias into the actual Block 1 of each

processor.

Further details and ordering information are available in the

ADSP-21000 Family Hardware and Software Development Tools

data sheet (ADDS-210xx-TOOLS). This data sheet can be

requested from any Analog Devices sales office or distributor.

If you develop your application using the ADSP-21062, but will

migrate to the ADSP-21061, use only the first eight columns of

each memory bank. Limit your application to 8K of instructions

or up to 16K of data in each bank of the ADSP-21062, or any

combinations of instructions or data that does not exceed the

memory bank.

In addition to the software and hardware development tools

available from Analog Devices, third parties provide a wide

range of tools supporting the SHARC processor family. Hard-

ware tools include SHARC PC plug-in cards multiprocessor

SHARC VME boards, and daughter and modules with multiple

SHARCs and additional memory. These modules are based on

the SHARCPAC™ module specification. Third Party software

tools include an Ada compiler, DSP libraries, operating systems

and block diagram design tools.

DEVELOPMENT TOOLS

The ADSP-21061 is supported with a complete set of software

and hardware development tools, including an EZ-ICE In-

Circuit Emulator, EZ-Kit Lite, and development software. The

SHARC EZ-Kit Lite (ADDS-2106x-EZ-Lite) is a complete low

cost package for DSP evaluation and prototyping. The EZ-Kit

Lite contains an evaluation board with an ADSP-21061 (5 V)

processor and provides a serial connection to your PC. The EZ-

Kit Lite also includes an optimizing compiler, assembler, in-

struction level simulator, run-time libraries, diagnostic utilities

and a complete set of example programs.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSP-21061

architecture and functionality. For detailed information on the

ADSP-21000 Family core architecture and instruction set, refer to

the ADSP-2106x SHARC User’s Manual, Second Edition.

CBUG and SHARCPAC are trademarks of Analog Devices, Inc.

REV. B

–8–

ADSP-21061/ADSP-21061L

PIN DESCRIPTIONS

DRx, TCLKx, RCLKx, TMS and TDI)—these pins can be left

floating. These pins have a logic-level hold circuit that prevents

the input from floating internally.

ADSP-21061 pin definitions are listed below. Inputs identified

as synchronous (S) must meet timing requirements with respect

to CLKIN (or with respect to TCK for TMS, TDI). Inputs

identified as asynchronous (A) can be asserted asynchronously

to CLKIN (or to TCK for TRST).

I = Input

(O/D) = Open Drain O = Output

G = Ground (A/D) = Active Drive

S = Synchronous

P = Power Supply

A = Asynchronous

Unused inputs should be tied or pulled to IVDD or IGND,

except for ADDR_31-0, DATA_47-0, FLAG_3-0, SW and inputs that

have internal pull-up or pull-down resistors (CPA, ACK, DTx,

T = Three-State (when SBTS is asserted, or when the

ADSP-2106x is a bus slave)

PIN FUNCTION DESCRIPTIONS

Type

Function

ADDR_31-0

I/O/T

External Bus Address. The ADSP-21061 outputs addresses for external memory and peripherals

on these pins. In a multiprocessor system the bus master outputs addresses for read/writes of the

internal memory or IOP registers of other ADSP-2106xs. The ADSP-21061 inputs addresses when a

host processor or multiprocessing bus master is reading or writing its internal memory or IOP registers.

DATA_47-0

I/O/T

O/T

External Bus Data. The ADSP-21061 inputs and outputs data and instructions on these pins.

The external data bus transfers 32-bit single-precision floating-point data and 32-bit fixed-point

data over Bits 47-16. 40-bit extended-precision floating-point data is transferred over Bits 47-8 of

the bus. 16-bit short word data is transferred over Bits 31-16 of the bus. Pull-up resistors on un-

used DATA pins are not necessary.

Memory Select Lines. These lines are asserted (low) as chip selects for the corresponding banks

of external memory. Memory bank size must be defined in the ADSP-21061’s system control regis-

ter (SYSCON). The MS_3-0lines are decoded memory address lines that change at the same time as

the other address lines. When no external memory access is occurring the MS_3-0lines are inactive;

they are active, however, when a conditional memory access instruction is executed, whether or not the

condition is true. MS₀can be used with the PAGE signal to implement a bank of DRAM memory

(Bank 0). In a multiprocessor system the MS_3-0lines are output by the bus master.

MS_3-0

RD

I/O/T

O/T

Memory Read Strobe. This pin is asserted (low) when the ADSP-21061 reads from external

memory devices or from the internal memory of other ADSP-21061s. External devices (including

other ADSP-21061s) must assert RD to read from the ADSP-21061’s internal memory. In a multi-

processor system RD is output by the bus master and is input by all other ADSP-21061s.

Memory Write Strobe. This pin is asserted (low) when the ADSP-21061 writes to external memory

devices or to the internal memory of other ADSP-21061s. External devices must assert WR to write to

the ADSP-21061’s internal memory. In a multiprocessor system WR is output by the bus master and is

input by all other ADSP-21061s.

DRAM Page Boundary. The ADSP-21061 asserts this pin to signal that an external DRAM page

boundary has been crossed. DRAM page size must be defined in the ADSP-21061’s memory con-

trol register (WAIT). DRAM can only be implemented in external memory Bank 0; the PAGE

signal can only be activated for Bank 0 accesses. In a multiprocessor system PAGE is output by the

bus master.

WR

PAGE

ADRCLK

O/T

Address Clock for synchronous external memories. Addresses on ADDR_31-0are valid before the

rising edge of ADRCLK. In a multiprocessing system ADRCLK is output by the bus master.

SW

I/O/T

Synchronous Write Select. This signal is used to interface the ADSP-2106x to synchronous memory

devices (including other ADSP-21061s). The ADSP-21061 asserts SW (low) to provide an early indica-

tion of an impending write cycle, which can be aborted if WR is not later asserted (e.g. in a conditional

write instruction). In a multiprocessor system, SW is output by the bus master and is input by all other

ADSP-21061s to determine if the multiprocessor memory access is a read or write. SW is asserted at the

same time as the address output. A host processor using synchronous writes must assert this pin when

writing to the ADSP-21061(s).

ACK

I/O/S

Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external

memory access. ACK is used by I/O devices, memory controllers or other peripherals to hold off

completion of an external memory access. The ADSP-21061 deasserts ACK as an output to add

wait states to a synchronous access of its internal memory. In a multiprocessor system, a slave

ADSP-21061 deasserts the bus master’s ACK input to add wait state(s) to an access of its internal

memory. The bus master has a keeper latch on its ACK pin that maintains the input at the level it

was last driven to.

REV. B

–9–

ADSP-21061/ADSP-21061L

Type

Function

SBTS

I/S

Suspend Bus Three-State. External devices can assert SBTS (low) to place the external bus address,

data, selects, and strobes in a high impedance state for the following cycle. If the ADSP-21061

attempts to access external memory while SBTS is asserted, the processor will halt and the memory

access will not be completed until SBTS is deasserted. SBTS should only be used to recover from

PAGE faults or host processor/ADSP-21061 deadlock.

IRQ_2-0

I/A

Interrupt Request Lines. May be either edge-triggered or level-sensitive.

FLAG_3-0

I/O/A

Flag Pins. Each is configured via control bits as either an input or an output. As an input, it can be

tested as a condition. As an output, it can be used to signal external peripherals.

TIMEXP

O

Timer Expired. Asserted for four cycles when the timer is enabled and TCOUNT decrements to

zero.

HBR

I/A

Host Bus Request. Must be asserted by a host processor to request control of the ADSP-21061’s

external bus. When HBR is asserted in a multiprocessing system, the ADSP-21061 that is bus master

will relinquish the bus and assert HBG. To relinquish the bus, the ADSP-21061 places the address,

data, select, and strobe lines in a high impedance state. HBR has priority over all ADSP-21061 bus

requests (BR_6-1) in a multiprocessing system.

HBG

I/O

Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor may take

control of the external bus. HBG is asserted (held low) by the ADSP-21061 until HBR is released. In a

multiprocessing system, HBG is output by the ADSP-21061 bus master and is monitored by all others.

CS

I/A

O

Chip Select. Asserted by host processor to select the ADSP-21061.

REDY (O/D)

Host Bus Acknowledge. The ADSP-2106x deasserts REDY (low) to add wait states to an asynchro-

nous access of its internal memory or IOP registers by a host. Open drain output (O/D) by default; can

be programmed in ADREDY bit of SYSCON register to be active drive (A/D). REDY will only be

output if the CS and HBR inputs are asserted.

DMAR1

DMAR2

DMAG1

DMAG2

BR_6-1

I/A

O/T

I/O/S

DMA Request 1 (DMA Channel 7).

DMA Request 2 (DMA Channel 6).

DMA Grant 1 (DMA Channel 7).

DMA Grant 2 (DMA Channel 6).

Multiprocessing Bus Requests. Used by multiprocessing ADSP-21061s to arbitrate for bus master-

ship. An ADSP-21061 only drives its own BRx line (corresponding to the value of its ID_2-0inputs) and

monitors all others. In a multiprocessor system with less than six ADSP-21061s, the unused BRx pins

should be tied high; the processor’s own BRx line must not be tied high or low because it is an output.

ID_2-0

I

Multiprocessing ID. Determines which multiprocessing bus request (BR1–BR6) is used by ADSP-

21061. ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, etc. ID = 000 in single-processor

systems. These lines are a system configuration selection which should be hardwired or only changed at

reset.

RPBA

I/S

I/O

Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor

bus arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system con-

figuration selection which must be set to the same value on every ADSP-21061. If the value of RPBA is

changed during system operation, it must be changed in the same CLKIN cycle on every ADSP-21061.

Core Priority Access. Asserting its CPA pin allows the core processor of an ADSP-21061 bus slave

to interrupt background DMA transfers and gain access to the external bus. CPA is an open drain

output that is connected to all ADSP-2106Ls in the system. The CPA pin has an internal 5 kΩ pull-up

resistor. If core access priority is not required in a system, the CPA pin should be left unconnected.

CPA (O/D)

DTx

DRx

TCLKx

O

I

I/O

Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 kΩ internal pull-up resistor.

Data Receive (Serial Ports 0, 1). Each DR pin has a 50 kΩ internal pull-up resistor.

Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 kΩ internal pull-up resistor.

RCLKx

I/O

Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 kΩ internal pull-up resistor.

REV. B

–10–

ADSP-21061/ADSP-21061L

Type

Function

TFSx

RFSx

EBOOT

I/O

I

Transmit Frame Sync (Serial Ports 0, 1).

Receive Frame Sync (Serial Ports 0, 1).

EPROM Boot Select. When EBOOT is high, the ADSP-21061 is configured for booting from an 8-

bit EPROM. When EBOOT is low, the LBOOT and BMS inputs determine booting mode. See table

below. This signal is a system configuration selection which should be hardwired.

LBOOT

I

Link Boot—Must be tied to GND.

BMS

I/O/T*

Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOT = 1,

LBOOT = 0). In a multiprocessor system, BMS is output by the bus master. Input: When low, indi-

cates that no booting will occur and that ADSP-21061 will begin executing instructions from external

memory. See table below. This input is a system configuration selection which should be hardwired.

*Three-statable only in EPROM boot mode (when BMS is an output).

EBOOT

LBOOT

BMS

Booting Mode

1

0

Output

1 (Input)

0 (Input)

EPROM (Connect BMS to EPROM chip select.)

Host Processor

No Booting. Processor executes from external memory.

CLKIN

I

Clock In. External clock input to the ADSP-21061. The instruction cycle rate is equal to CLKIN.

CLKIN may not be halted, changed, or operated below the specified frequency.

RESET

I/A

Processor Reset. Resets the ADSP-21061 to a known state and begins execution at the program

memory location specified by the hardware reset vector address. This input must be asserted (low) at

power-up.

TCK

TMS

I

I/S

Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan.

Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kΩ internal pull-up

resistor.

TDI

I/S

Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 kΩ internal

pull-up resistor.

TDO

O

Test Data Output (JTAG). Serial scan output of the boundary scan path.

TRST

I/A

Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-

up or held low for proper operation of the ADSP-21061. TRST has a 20 kΩ internal pull-up resistor.

EMU

ICSA

VDD

GND

NC

O

P

Emulation Status. Must be connected to the ADSP-21061 EZ-ICEtarget board connector only.

Reserved, leave unconnected.

Power Supply; nominally +3.3 V dc for ADSP-21061L, +5.0 V dc for ADSP-21061.

Power Supply Return.

Do Not Connect. Reserved pins which must be left open and unconnected.

G

REV. B

–11–

ADSP-21061/ADSP-21061L

TARGET BOARD CONNECTOR FOR EZ-ICE PROBE

The ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1

JTAG test access port of the ADSP-2106x to monitor and control

the target board processor during emulation. The EZ-ICE

probe requires the ADSP-2106x’s CLKIN, TMS, TCK,

TRST, TDI, TDO, EMU, and GND signals be made acces-

sible on the target system via a 14-pin connector (a 2 row × 7

pin strip header) such as that shown in Figure 5. The EZ-ICE

probe plugs directly onto this connector for chip-on-board

emulation. You must add this connector to your target board

design if you intend to use the ADSP-2106x EZ-ICE. The total

trace length between the EZ-ICE connector and the furthest

device sharing the EZ-ICE JTAG pins should be limited to 15

inches maximum for guaranteed operation. This length restric-

tion must include EZ-ICE JTAG signals that are routed to one

or more ADSP-2106x devices, or a combination of ADSP-

2106x devices and other JTAG devices on the chain.

The 14-pin, 2-row pin strip header is keyed at the Pin 3 location —

Pin 3 must be removed from the header. The pins must be

0.025 inch square and at least 0.20 inch in length. Pin spacing

should be 0.1 × 0.1 inches. Pin strip headers are available from

vendors such as 3M, McKenzie and Samtec.

The BTMS, BTCK, BTRST and BTDI signals are provided so

the test access port can also be used for board-level testing.

When the connector is not being used for emulation, place

jumpers between the Bxxx pins and the xxx pins. If the test

access port will not be used for board testing, tie BTRST to GND

and tie or pull BTCK up to VDD. The TRST pin must be

asserted after power-up (through BTRST on the connector) or

held low for proper operation of the ADSP-2106x. None of the

Bxxx pins (Pins 5, 7, 9, 11) are connected on the EZ-ICEprobe.

The JTAG signals are terminated on the EZ-ICE probe as

follows:

Signal Termination

1

3

5

2

4

6

GND

EMU

TMS

TCK

Driven through 22 Ω Resistor (16 mA Driver)

Driven at 10 MHz through 22 Ω Resistor (16 mA

Driver)

KEY (NO PIN)

CLKIN (OPTIONAL)

TRST* Active Low Driven through 22 Ω Resistor (16 mA

BTMS

BTCK

BTRST

BTDI

TMS

TCK

TRST

TDI

Driver) (Pulled Up by On-Chip 20 kΩ Resistor)

TDI

TDO

Driven by 22 Ω Resistor (16 mA Driver)

7

9

8

One TTL Load, Split Termination (160/220)

CLKIN One TTL Load, Split Termination (160/220)

10

12

EMU

Active Low 4.7 kΩ Pull-Up Resistor, One TTL Load

(Open-Drain Output from the DSP)

9

11

*TRST is driven low until the EZ-ICE probe is turned on by the emulator at

software start-up. After software start-up, TRST is driven high.

13

14

GND

TDO

Figure 6 shows JTAG scan path connections for systems that

contain multiple ADSP-2106x processors.

TOP VIEW

Figure 5. Target Board Connector For ADSP-21061/ADSP-

21061L EZ-ICE Emulator (Jumpers in Place)

JTAG

ADSP-2106x

#1

ADSP-2106x

#n

DEVICE

(OPTIONAL)

TDO

TDI

TDO

TDI

EZ-ICE

JTAG

CONNECTOR

OTHER

JTAG

CONTROLLER

TCK

TMS

EMU

TRST

TDO

CLKIN

OPTIONAL

Figure 6. JTAG Scan Path Connections for Multiple ADSP-21061/ADSP-21061L Systems

REV. B

–12–

ADSP-21061/ADSP-21061L

Connecting CLKIN to Pin 4 of the EZ-ICEheader is optional.

The emulator only uses CLKIN when directed to perform op-

erations such as starting, stopping and single-stepping multiple

ADSP-2106x in a synchronous manner. If you do not need these

operations to occur synchronously on the multiple processors,

simply tie Pin 4 of the EZ-ICE header to ground.

should be laid out as short as possible on your board. If TCK,

TMS and CLKIN are driving a large number of ADSP-2106x

(more than eight) in your system, then treat them as a clock tree

using multiple drivers to minimize skew. (See Figure 7, JTAG

Clock Tree, and Clock Distribution in the High Frequency

Design Considerations section of the ADSP-2106x User’s

Manual, Second Edition.)

If synchronous multiprocessor operations are needed and

CLKIN is connected, clock skew between the multiple ADSP-

21061x processors and the CLKIN pin on the EZ-ICEheader

must be minimal. If the skew is too large, synchronous operations

may be off by one or more cycles between processors. For syn-

chronous multiprocessor operation TCK, TMS, CLKIN and

EMU should be treated as critical signals in terms of skew, and

If synchronous multiprocessor operations are not needed (i.e.,

CLKIN is not connected), just use appropriate parallel termina-

tion on TCK and TMS. TDI, TDO, EMU and TRST are not

critical signals in terms of skew.

For complete information on the SHARC EZ-ICE, see the ADSP-

21000 Family JTAG EZ-ICE User’s Guide and Reference.

TDI

TDO

TDI

TDO

TDI

TDO

5k⍀

*

TDI

TDO

TDI

TDO

TDI

TDO

TDI

EMU

5k⍀

*

TCK

TMS

TRST

TDO

SYSTEM

CLKIN

EMU

*

OPEN DRAIN DRIVER OR EQUIVALENT, i.e.,

Figure 7. JTAG Clocktree for Multiple ADSP-21061/ADSP-21061L Systems

REV. B

–13–

ADSP-21061/ADSP-21061L

ADSP-21061–SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS (5 V)

K Grade

Max

Parameter

Test Conditions

Min

Unit

V_DD

T_CASE

V_IH1

V_IH2

V_IL

Supply Voltage

4.75

0

2.0

2.2

–0.5

5.25

+85

V_DD+ 0.5

0.8

V

°C

V

Case Operating Temperature

High Level Input Voltage¹

High Level Input Voltage²

Low Level Input Voltage^{1, 2}

@ V_DD= max

@ V_DD= min

NOTES

¹Applies to input and bidirectional pins: DATA_47-0, ADDR_31-0, RD, WR, SW, ACK, SBTS, IRQ_2-0, FLAG_3-0, HBG, CS, DMAR1, DMAR2, BR_6-1, ID_2-0, RPBA,

CPA, TFS0, TFS1, RFS0, RFS1, LxDAT_3-0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1.

²Applies to input pins: CLKIN, RESET, TRST.

ELECTRICAL CHARACTERISTICS (5 V)

Parameter

Test Conditions

Min

Max

Unit

V_OH

V_OL

I_IH

I_IL

I_ILP

I_OZH

I_OZL

I_OZHP

I_OZLC

I_OZLA

I_OZLAR

I_OZLS

C_IN

High Level Output Voltage¹

Low Level Output Voltage¹

High Level Input Current^{3, 4}

Low Level Input Current³

@ V_DD= min, I_OH= –2.0 mA²

@ V_DD= min, I_OL= 4.0 mA²

@ V_DD= max, V_IN= V_DDmax

@ V_DD= max, V_IN= 0 V

@ V_DD= max, V_IN= V_DDmax

@ V_DD= max, V_IN= 0 V

@ V_DD= max, V_IN= V_DDmax

@ V_DD= max, V_IN= 0 V

@ V_DD= max, V_IN= 1.5 V

@ V_DD= max, V_IN= 0 V

4.1

V

0.4

10

150

10

350

1.5

350

4.2

150

4.7

µA

mA

µA

mA

µA

pF

Low Level Input Current⁴

Three-State Leakage Current^{5, 6, 7, 8}

Three-State Leakage Current^{5, 9}

Three-State Leakage Current⁹

Three-State Leakage Current⁷

Three-State Leakage Current¹⁰

Three-State Leakage Current⁸

Three-State Leakage Current⁶

Input Capacitance^{11, 12}

f_IN= 1 MHz, T_CASE= 25°C, V_IN= 2.5 V

NOTES

¹¹Applies to output and bidirectional pins: DATA_47-0, ADDR_31-0, MS_3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG_3-0, TIMEXP, HBG, REDY, DMAG1,

DMAG2, BR_6-1, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT_3-0, LxCLK, LxACK, BMS, TDO, EMU, ICSA.

¹²See Output Drive Currents section for typical drive current capabilities.

¹³Applies to input pins: ACK SBTS, IRQ_2-0, HBR, CS, DMAR1, DMAR2, ID_2-0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK. Note that ACK is pulled up

internally with 2 kΩ during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106x is not requesting bus mastership.)

¹⁴Applies to input pins with internal pull-ups: DR0, DR1, TRST, TMS, TDI.

¹⁵Applies to three-statable pins: DATA_47-0, ADDR_31-0, MS_3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG_3-0, REDY, HBG, DMAG1, DMAG2, BMS, BR_6–1

,

TFS_X, RFS_X, TDO, EMU. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID_2-0= 001 and another ADSP-2106x is

not requesting bus mastership.)

¹⁶Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.

¹⁷Applies to CPA pin.

¹⁸Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID_2-0= 001 and another

ADSP-21061x is not requesting bus mastership).

¹⁹Applies to three-statable pins with internal pull-downs: LxDAT_3-0, LxCLK, LxACK.

¹⁰Applies to ACK pin when keeper latch enabled.

¹¹Applies to all signal pins.

¹²Guaranteed but not tested.

Specifications subject to change without notice.

–14–

REV. B

ADSP-21061/ADSP-21061L

POWER DISSIPATION ADSP-21061 (5 V)

These specifications apply to the internal power portion of V_DDonly. See the Power Dissipation section of this data sheet for calcula-

tion of external supply current and total supply current. For a complete discussion of the code used to measure power dissipation, see

the technical note “SHARC Power Dissipation Measurements.”

Specifications are based on the following operating scenarios:

Operation

Peak Activity (I_DDINPEAK

Multifunction

)

High Activity (I_DDINHIGH

Multifunction

)

Low Activity (I_DDINLOW

Single Function

Internal Memory

None

)

Instruction Type

Instruction Fetch

Core Memory Access

Internal Memory DMA

Cache

Internal Memory

1 per Cycle (DM)

1 per 2 Cycles

2 per Cycle (DM and PM)

1 per Cycle

1 per 2 Cycles

To estimate power consumption for a specific application, use the following equation where % is the amount of time your program

spends in that state:

%PEAK × I_DDINPEAK+ %HIGH × I_DDINHIGH+ %LOW × I_DDINLOW+ %IDLE × I_DDIDLE+ %IDLE16 × I_DDIDLE16= power consumption

Parameter

Test Conditions

Max

Unit

I_DDINPEAK

Supply Current (Internal)¹

Supply Current (Internal)²

Supply Current (Internal)³

t_CK= 30 ns, V_DD= max

595

680

850

460

540

670

270

320

390

200

55

mA

t

_CK= 25 ns, V_DD= max

t_CK= 20 ns, V_DD= max

t_CK= 30 ns, V_DD= max

I_DDINHIGH

t

_CK= 25 ns, V_DD= max

t_CK= 20 ns, V_DD= max

t_CK= 30 ns, V_DD= max

I_DDINLOW

t

_CK= 25 ns, V_DD= max

t_CK= 20 ns, V_DD= max

V_DD= max

I_DDIDLE

I_DDIDLE16

Supply Current (Idle)⁴

Supply Current (Idle16)⁵

NOTES

¹The test program used to measure I_DDINPEAKrepresents worst case processor operation and is not sustainable under normal application conditions. Actual internal

power measurements made using typical applications are less than specified.

²I_DDINHIGHis a composite average based on a range of high activity code.

³I_DDINLOWis a composite average based on a range of low activity code.

⁴Idle denotes ADSP-21061 state during execution of IDLE instruction.

⁵Idle16 denotes ADSP-21061 state during execution of IDLE16 instruction.

REV. B

–15–

ADSP-21061/ADSP-21061L

ADSP-21061L–SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS (3.3 V)

A Grade

Min

K Grade

Parameter

Test Conditions

Max

Min

Max

Unit

V_DD

T_CASE

V_IH1

V_IH2

V_IL

Supply Voltage

3.15

–40

2.0

2.2

–0.5

3.45

+85

V_DD+ 0.5

0.8

3.15

0

2.0

2.2

–0.5

3.45

+85

V_DD+ 0.5

0.8

V

°C

V

Case Operating Temperature

High Level Input Voltage¹

High Level Input Voltage²

Low Level Input Voltage^{1, 2}

@ V_DD= max

@ V_DD= min

NOTES

¹Applies to input and bidirectional pins: DATA_47-0, ADDR_31-0, RD, WR, SW, ACK, SBTS, IRQ_2-0, FLAG_3-0, HBG, CS, DMAR1, DMAR2, BR_6-1, ID_2-0, RPBA,

CPA, TFS0, TFS1, RFS0, RFS1, LxDAT_3-0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1.

²Applies to input pins: CLKIN, RESET, TRST.

ELECTRICAL CHARACTERISTICS (3.3 V)

Parameter

Test Conditions

Min

Max

Unit

V_OH

V_OL

I_IH

I_IL

I_ILP

I_OZH

I_OZL

I_OZHP

I_OZLC

I_OZLA

I_OZLAR

I_OZLS

C_IN

High Level Output Voltage¹

Low Level Output Voltage¹

High Level Input Current^{3, 4}

Low Level Input Current³

@ V_DD= min, I_OH= –2.0 mA²

@ V_DD= min, I_OL= 4.0 mA²

@ V_DD= max, V_IN= V_DDmax

@ V_DD= max, V_IN= 0 V

@ V_DD= max, V_IN= V_DDmax

@ V_DD= max, V_IN= 0 V

@ V_DD= max, V_IN= V_DDmax

@ V_DD= max, V_IN= 0 V

@ V_DD= max, V_IN= 1.5 V

@ V_DD= max, V_IN= 0 V

2.4

V

0.4

10

150

10

350

1.5

350

4.2

150

4.7

µA

mA

µA

mA

µA

pF

Low Level Input Current⁴

Three-State Leakage Current^{5, 6, 7, 8}

Three-State Leakage Current^{5, 9}

Three-State Leakage Current⁹

Three-State Leakage Current⁷

Three-State Leakage Current¹⁰

Three-State Leakage Current⁸

Three-State Leakage Current⁶

Input Capacitance^{11, 12}

f_IN= 1 MHz, T_CASE= 25°C, V_IN= 2.5 V

NOTES

¹¹Applies to output and bidirectional pins: DATA_47-0, ADDR_31-0, MS_3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG_3-0, TIMEXP, HBG, REDY, DMAG1,

DMAG2, BR_6-1, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT_3-0, LxCLK, LxACK, BMS, TDO, EMU, ICSA.

¹²See “Output Drive Currents” for typical drive current capabilities.

¹³Applies to input pins: ACK SBTS, IRQ_2-0, HBR, CS, DMAR1, DMAR2, ID_2-0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK. Note that ACK is pulled up

internally with 2 kΩ during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106x is not requesting bus mastership.)

¹⁴Applies to input pins with internal pull-ups: DR0, DR1, TRST, TMS, TDI.

¹⁵Applies to three-statable pins: DATA_47-0, ADDR_31-0, MS_3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG_3-0, REDY, HBG, DMAG1, DMAG2, BMS, BR_6–1

,

TFS_X, RFS_X, TDO, EMU. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID_2-0= 001 and another ADSP-2106x is

not requesting bus mastership.)

¹⁶Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.

¹⁷Applies to CPA pin.

¹⁸Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID_2-0= 001 and another

ADSP-21061L is not requesting bus mastership).

¹⁹Applies to three-statable pins with internal pull-downs: LxDAT_3-0, LxCLK, LxACK.

¹⁰Applies to ACK pin when keeper latch enabled.

¹¹Applies to all signal pins.

¹²Guaranteed but not tested.

Specifications subject to change without notice.

–16–

REV. B

ADSP-21061/ADSP-21061L

POWER DISSIPATION ADSP-21061L (3.3 V)

These specifications apply to the internal power portion of V_DDonly. See the Power Dissipation section of this data sheet for calcula-

tion of external supply current and total supply current. For a complete discussion of the code used to measure power dissipation,

see the technical note “SHARC Power Dissipation Measurements.”

Specifications are based on the following operating scenarios:

Operation

Peak Activity (I_DDINPEAK

Multifunction

)

High Activity (I_DDINHIGH

Multifunction

)

Low Activity (I_DDINLOW

Single Function

Internal Memory

None

)

Instruction Type

Instruction Fetch

Core Memory Access

Internal Memory DMA

Cache

Internal Memory

1 per Cycle (DM)

1 per 2 Cycles

2 per Cycle (DM and PM)

1 per Cycle

1 per 2 Cycles

To estimate power consumption for a specific application, use the following equation where % is the amount of time your program

spends in that state:

%PEAK × I_DDINPEAK+ %HIGH × I_DDINHIGH+ %LOW × I_DDINLOW+ %IDLE × I_DDIDLE+ %IDLE16 × I_DDIDLE16= power consumption

Parameter

Test Conditions

Max

Unit

I_DDINPEAK

Supply Current (Internal)¹

Supply Current (Internal)²

Supply Current (Internal)³

t_CK= 25 ns, V_DD= max

480

535

380

425

220

245

180

50

mA

t

_CK= 22.5 ns, V_DD= max

t_CK= 25 ns, V_DD= max

_CK= 22.5 ns, V_DD= max

I_DDINHIGH

I_DDINLOW

t

t_CK= 25 ns, V_DD= max

t_CK= 22.5 ns, V_DD= max

V_DD= max

I_DDIDLE

I_DDIDLE16

Supply Current (Idle)⁴

Supply Current (Idle16)⁵

V_DD= max

NOTES

¹The test program used to measure I_DDINPEAKrepresents worst case processor operation and is not sustainable under normal application conditions. Actual internal

power measurements made using typical applications are less than specified.

²I_DDINHIGHis a composite average based on a range of high activity code.

³I_DDINLOWis a composite average based on a range of low activity code.

⁴Idle denotes ADSP-21061L state during execution of IDLE instruction.

⁵Idle16 denotes ADSP-21061L state during execution of IDLE16 instruction.

REV. B

–17–

ADSP-21061/ADSP-21061L

ABSOLUTE MAXIMUM RATINGS (5 V DEVICE)*

ABSOLUTE MAXIMUM RATINGS (3.3 V DEVICE)*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Input Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to V_DD+ 0.5 V

Output Voltage Swing . . . . . . . . . . . . . –0.5 V to V_DD+ 0.5 V

Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF

Junction Temperature Under Bias . . . . . . . . . . . . . . . . 130°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (5 seconds) . . . . . . . . . . . . . . . . . +280°C

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V

Input Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to V_DD+ 0.5 V

Output Voltage Swing . . . . . . . . . . . . . –0.5 V to V_DD+ 0.5 V

Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF

Junction Temperature Under Bias . . . . . . . . . . . . . . . . 130°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (5 seconds) . . . . . . . . . . . . . . . . . +280°C

*Stresses greater than those listed above may cause permanent damage to the

device. These are stress ratings only; functional operation of the device at these or

any other conditions greater than those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

*Stresses greater than those listed above may cause permanent damage to the

device. These are stress ratings only; functional operation of the device at these or

any other conditions greater than those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

ESD SENSITIVITY

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the ADSP-2106x features proprietary ESD protection circuitry, permanent damage may occur on

devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

Switching Characteristics specify how the processor changes its

signals. You have no control over this timing—circuitry external

to the processor must be designed for compatibility with these

signal characteristics. Switching characteristics tell you what the

processor will do in a given circumstance. You can also use switch-

ing characteristics to ensure that any timing requirement of a de-

vice connected to the processor (such as memory) is satisfied.

TIMING SPECIFICATIONS

GENERAL NOTES

The following timing specifications are target specifications and

are based on device simulation only.

The timing specifications shown are based on a CLKIN frequency

of 40 MHz (t_CK= 25 ns). The DT derating allows specifications

at other CLKIN frequencies (within the min–max range of the

t_CKspecification; see Clock Input below). DT is the differ-

ence between the actual CLKIN period and a CLKIN period

of 25 ns:

Timing Requirements apply to signals that are controlled by

circuitry external to the processor, such as the data input for a

read operation. Timing requirements guarantee that the proces-

sor operates correctly with other devices.

DT = t_CK– 25 ns

(O/D) = Open Drain

(A/D) = Active Drive

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results for

an individual device, the values given in this data sheet reflect

statistical variations and worst cases. Consequently, you cannot

meaningfully add parameters to derive longer times.

See Figure 26 under Test Conditions for voltage reference

levels.

REV. B

–18–

ADSP-21061/ADSP-21061L

ADSP-21061 (5 V)

40 MHz

Min

33 MHz

Max

50 MHz

Min

Parameter

Min

Max

Unit

Clock Input

Timing Requirements:

t_CK

CLKIN Period

30

7

5

100

3

25

7

5

100

3

20

7

5

100

3

ns

t_CKL

t_CKH

t_CKRF

CLKIN Width Low

CLKIN Width High

CLKIN Rise/Fall (0.4 V–2.0 V)

ADSP-21061L (3.3 V)

40 MHz

44 MHz

Parameter

Min

Max

Min

Max

Unit

Clock Input

Timing Requirements:

t_CK

CLKIN Period

25

7

5

100

3

22.5

7

5

100

3

ns

t_CKL

t_CKH

t_CKRF

CLKIN Width Low

CLKIN Width High

CLKIN Rise/Fall (0.4 V–2.0 V)

t_CK

CLKIN

t_CKH

t_CKL

Figure 8. Clock Input

ADSP-21061 (5 V)

ADSP-21061L (3.3 V)

Parameter

Reset

Min

Max

Min

Max

Unit

Timing Requirements:

t_WRST

RESET Pulsewidth Low¹

t_SRST

RESET Setup before CLKIN High²

4t_CK

14 + DT/2

4t_CK

14 + DT/2

ns

t_CK

NOTES

¹Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles while RESET is

low, assuming stable V_DDand CLKIN (not including start-up time of external clock oscillator).

²Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required

for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset.

CLKIN

t_SRST

t_WRST

RESET

Figure 9. Reset

ADSP-21061 (5 V)

ADSP-21061L (3.3 V)

Parameter

Min

Max

Min

Max

Unit

Interrupts

Timing Requirements:

t_SIR

t_HIR

t_IPW

IRQ2-0 Setup before CLKIN High¹

18 + 3DT/4

2 + t_CK

18 + 3DT/4

2 + t_CK

ns

IRQ2-0 Hold before CLKIN High¹

IRQ2-0 Pulsewidth²

12 + 3DT/4

NOTES

¹Only required for IRQx recognition in the following cycle.

²Applies only if t_SIRand t_HIRrequirements are not met.

REV. B

–19–

ADSP-21061/ADSP-21061L

CLKIN

t_SIR

t_HIR

IRQ2-0

t_IPW

Figure 10. Interrupts

ADSP-21061 (5 V)

ADSP-21061L (3.3 V)

Parameter

Min

Max

Min

Max

Unit

Timer

Switching Characteristics:

t_DTEX

CLKIN High to TIMEXP

15

ns

CLKIN

t_DTEX

TIMEXP

Figure 11. Timer

ADSP-21061 (5 V)

ADSP-21061L (3.3 V)

Parameter

Min

Max

Min

Max

Unit

Timing Requirements:

t_SFI

FLAG3-0_INSetup before CLKIN High¹

8 + 5DT/16

0 – 5DT/16

8 + 5DT/16

0 – 5DT/16

ns

t_HFI

FLAG3-0_INHold after CLKIN High¹

FLAG3-0_INDelay after RD/WR Low¹

FLAG3-0_INHold after RD/WR Deasserted¹

t_DWRFI

5 + 7DT/16

t_HFIWR

0

Switching Characteristics:

t_DFO

FLAG3-0_OUTDelay after CLKIN High

16

14

16

14

ns

t_HFO

t_DFOE

t_DFOD

FLAG3-0_OUTHold after CLKIN High

CLKIN High to FLAG3-0_OUTEnable

CLKIN High to FLAG3-0_OUTDisable

4

3

4

3

NOTE

¹Flag inputs meeting these setup and hold times will affect conditional instructions in the following instruction cycle.

CLKIN

t_DFOE

t_DFO

t_DFOD

t_HFO

FLAG3-0

OUT

FLAG OUTPUT

CLKIN

t_HFI

t_SFI

FLAG3-0

IN

t_HFIWR

t_DWRFI

RD, WR

FLAG INPUT

Figure 12. Flags

–20–

REV. B

ADSP-21061/ADSP-21061L

Memory Read—Bus Master

characteristics also apply for bus master synchronous read/write

timing (see Synchronous Read/Write—Bus Master). If these

timing requirements are met, the synchronous read/write timing

can be ignored (and vice versa).

Use these specifications for asynchronous interfacing to memo-

ries (and memory-mapped peripherals) without reference to

CLKIN. These specifications apply when the ADSP-21061 is

the bus master accessing external memory space. These switching

ADSP-21061 (5 V)

ADSP-21061L (3.3 V)

Max

Parameter

Min

Max

Min

Unit

Timing Requirements:

t_DAD

t_DRLD

t_HDA

t_HDRH

t_DAAK

t_DSAK

Address, Selects Delay to Data Valid^{1, 2}

18 + DT + W

12 + 5DT/8 + W

18 + DT + W

12 + 5DT/8 + W

ns

RD Low to Data Valid¹

Data Hold from Address, Selects³

Data Hold from RD High³

0.5

2.0

0.5

2.0

ACK Delay from Address, Selects^{2, 4}

ACK Delay from RD Low⁴

15 + 7DT/8 + W

8 + DT/2 + W

15 + 7DT/8 + W

8 + DT/2 + W

Switching Characteristics:

t_DRHA

t_DARL

t_RW

Address, Selects Hold after RD High

0 + H

2 + 3DT/8

12.5 + 5DT/8 + W

8 + 3DT/8 + HI

0 + H

2 + 3DT/8

12.5 + 5DT/8 + W

8 + 3DT/8 + HI

ns

Address, Selects to RD Low²

RD Pulsewidth

t_RWR

RD High to WR, RD, DMAGx Low

t_SADADCAddress, Selects Setup before

ADRCLK High²

0 + DT/4

.

0 + DT/4

ns

W = (number of wait states specified in WAIT register) × t_CK

HI = t_CK(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

H = t_CK(if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).

NOTES

¹Data Delay/Setup: User must meet t_DADor t_DRLDor synchronous specification t_SSDATI

.

²The falling edge of MSx, SW, and BMS is referenced.

³Data Hold: User must meet t_HDAor t_HDRHor synchronous specification t_HSDATI. See System Hold Time Calculation under Test Conditions for the calculation of hold

times given capacitive and dc loads.

⁴ACK Delay/Setup: User must meet t_DAAKor t_DSAKor synchronous specification t_SACKCfor deassertion of ACK (Low), all three specifications must be met for asser-

tion of ACK (High).

ADDRESS

MSx, SW

BMS

t_DARL

t_DRHA

t_RW

RD

t_HDA

t_HDRH

t_DRLD

t_DAD

DATA

t_DSAK

t_RWR

t_DAAK

ACK

WR, DMAG

t_SADADC

ADRCLK

(OUT)

Figure 13. Memory Read—Bus Master

REV. B

–21–

ADSP-21061/ADSP-21061L

Memory Write—Bus Master

characteristics also apply for bus master synchronous read/write

timing (see Synchronous Read/Write—Bus Master). If these

timing requirements are met, the synchronous read/write timing

can be ignored (and vice versa).

Use these specifications for asynchronous interfacing to memo-

ries (and memory-mapped peripherals) without reference to

CLKIN. These specifications apply when the ADSP-21061 is

the bus master accessing external memory space. These switching

ADSP-21061 (5 V)

ADSP-21061L (3.3 V)

Max

Parameter

Min

Max

Min

Unit

Timing Requirements:

t_DAAK

t_DSAK

ACK Delay from Address, Selects^{1, 2}

15 + 7DT/8 + W

8 + DT/2 + W

15 + 7DT/8 + W

8 + DT/2 + W

ns

ACK Delay from WR Low¹

Switching Characteristics:

t_DAWH

t_DAWL

t_WW

t_DDWH

t_DWHA

Address, Selects to WR Deasserted²

17 + 15DT/16 + W

3 + 3DT/8

17 + 15DT/16 + W

3 + 3DT/8

ns

Address, Selects to WR Low²

WR Pulsewidth

13 + 9DT/16 + W

7 + DT/2 + W

1 + DT/16 + H

8 + 7DT/16 + H

5 + 3DT/8 + I

–1 + DT/16

13 + 9DT/16 + W

7 + DT/2 + W

0.5 + DT/16 + H

1 + DT/16 + H

8 + 7DT/16 + H

5 + 3DT/8 + I

–1 + DT/16

Data Setup before WR High

Address Hold after WR Deasserted

t_DATRWHData Disable after WR Deasserted³

6 + DT/16 + H

t_WWR

t_DDWR

t_WDE

WR High to WR, RD, DMAGx Low

Data Disable before WR or RD Low

WR Low to Data Enabled

t_SADADCAddress, Selects to ADRCLK High²

0 + DT/4

W = (number of wait states specified in WAIT register) × t_CK

.

H = t_CK(if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).

I = t_CK(if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).

NOTES

¹ACK Delay/Setup: User must meet t_DAAKor t_DSAKor synchronous specification t_SACKCfor deassertion of ACK (Low), all three specifications must be met for asser-

tion of ACK (High)

²The falling edge of MSx, SW, and BMS is referenced.

³See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.

ADDRESS

MSx , SW

BMS

t_DWHA

t_DAWH

t_WW

t_DAWL

WR

t_WWR

t_DDWR

t_DDWH

t_WDE

t_DATRWH

DATA

t_DSAK

t_DAAK

ACK

RD, DMAG

t_SADADC

ADRCLK

(OUT)

Figure 14. Memory Write—Bus Master

REV. B

–22–

ADSP-21061/ADSP-21061L

Synchronous Read/Write—Bus Master

When accessing a slave ADSP-2106x, these switching character-

istics must meet the slave’s timing requirements for synchronous

read/writes (see Synchronous Read/Write—Bus Slave). The

slave ADSP-21061 must also meet these (bus master) timing

requirements for data and acknowledge setup and hold times.

Use these specifications for interfacing to external memory

systems that require CLKIN—relative timing or for accessing a

slave ADSP-21061 (in multiprocessor memory space). These

synchronous switching characteristics are also valid during

asynchronous memory reads and writes (see Memory Read—

Bus Master and Memory Write—Bus Master).

ADSP-21061 (5 V)

ADSP-21061L (3.3 V)

Max

Parameter

Min

Max

Min

Unit

Timing Requirements:

t_SSDATI

Data Setup before CLKIN

2 + DT/8

ns

t_SSDATI(50 MHz) Data Setup before CLKIN,

t_CK= 20 ns¹

1.5 + DT/8

3.5 – DT/8

ns

t_HSDATI

t_DAAK

Data Hold after CLKIN

ACK Delay after Address, MSx,

SW, BMS^{2, 3}

3.5 – DT/8

15 + 7 DT/8 + W

6.5 – DT/8

15 + 7 DT/8 + W

6.5 – DT/8

ns

t_SACKC

t_HACK

ACK Setup before CLKIN²

ACK Hold after CLKIN

6.5 + DT/4

–1 – DT/4

6.5 + DT/4

–1 – DT/4

Switching Characteristics:

t_DADRO

Address, MSx, BMS, SW Delay

after CLKIN²

ns

t_HADRO

Address, MSx, BMS, SW Hold

after CLKIN

–1 – DT/8

9 + DT/8

–1.5 – DT/8

–2.5 – 3DT/16

–1 – DT/8

9 + DT/8

–1.5 – DT/8

–2.5 – 3DT/16

ns

t_DPGC

t_DRDO

t_DWRO

PAGE Delay after CLKIN

RD High Delay after CLKIN

WR High Delay after CLKIN

16 + DT/8

4 – DT/8

4 – 3DT/16

16 + DT/8

4 – DT/8

4 – 3DT/16

t_DWRO(50 MHz) WR High Delay after CLKIN,

t_CK= 20 ns¹

RD/WR Low Delay after CLKIN 8 + DT/4

Data Delay after CLKIN

Data Disable after CLKIN⁴

ADRCLK Delay after CLKIN

ADRCLK Period

–1.5 – 3DT/16

4 – 3DT/16

12 + DT/4

19 + 5DT/16

7 – DT/8

ns

t_DRWL

8 + DT/4

12 + DT/4

19 + 5DT/16

7 – DT/8

t_SDDATO

t_DATTR

t_DADCCK

t_ADRCK

t_ADRCKH

t_ADRCKL

0 – DT/8

4 + DT/8

t_CK

(t_CK/2 – 2)

0 – DT/8

4 + DT/8

t_CK

(t_CK/2 – 2)

10 + DT/8

ADRCLK Width High

ADRCLK Width Low

W = (number of Wait states specified in WAIT register) × t_CK

.

NOTES

¹This specification applies to the ADSP-21061KS-200 (5 V, 50 MHz) operating at t_CK< 25 ns. For all other devices, use the preceding timing specification of the

same name.

²ACK Delay/Setup: User must meet t_DAAKor t_DSAKor synchronous specification t_SACKCfor deassertion of ACK (Low), all three specifications must be met for assertion

of ACK (High).

³Data Hold: User must meet t_HDAor t_HDRHor synchronous specification t_HDATI. See System Hold Time Calculation under Test Conditions for the calculation of hold

times given capacitive and dc loads.

⁴See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.

REV. B

–23–

ADSP-21061/ADSP-21061L

CLKIN

t_ADRCK

t_ADRCKL

t_ADRCKH

t_DADCCK

ADRCLK

t_HADRO

t_DAAK

t_DADRO

ADDRESS

SW

t_DPGC

PAGE

t_HACK

t_SACKC

ACK

(IN)

READ CYCLE

t_DRWL

t_DRDO

RD

t_HSDATI

t_SSDATI

DATA

(IN)

WRITE CYCLE

t_DWRO

t_DRWL

WR

t_DATTR

t_SDDATO

DATA

(OUT)

Figure 15. Synchronous Read/Write—Bus Master

REV. B

–24–

ADSP-21061/ADSP-21061L

Synchronous Read/Write—Bus Slave

Use these specifications for ADSP-21061 bus master accesses of

a slave’s IOP registers or internal memory (in multiprocessor

memory space). The bus master must meet these (bus slave)

timing requirements.

ADSP-21061 (5 V)

ADSP-21061L (3.3 V)

Parameter

Min

Max

Min

Max

Unit

Timing Requirements:

t_SADRI

t_HADRI

t_SRWLI

t_HRWLI

Address, SW Setup before CLKIN

14 + DT/2

ns

Address, SW Hold before CLKIN

RD/WR Low Setup before CLKIN¹

RD/WR Low Hold after CLKIN

44 MHz/50 MHz²

RD/WR Pulse High

Data Setup before WR High

Data Hold after WR High

5 + DT/2

8.5 + 5DT/16

–4 – 5DT/16

8.5 + 5DT/16

–4 – 5DT/16

8 + 7DT/16

–3.5 – 5DT/16

ns

t_RWHPI

t_SDATWH

t_HDATWH

3

1

3

1

Switching Characteristics:

t_SDDATO

t_DATTR

t_DACKAD

t_ACKTR

Data Delay after CLKIN

19 + 5DT/16

7 – DT/8

8

19 + 5DT/16

7 – DT/8

8

ns

Data Disable after CLKIN³

ACK Delay after Address, SW⁴

ACK Disable after CLKIN⁴

0 – DT/8

–1 – DT/8

6 – DT/8

–1 – DT/8

6 – DT/8

NOTES

¹t_SRWLI(min) = 9.5 + 5DT/16 when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, t _SRWLI(min)

= 4 + DT/8.

²This specification applies to the ADSP-21061LKS-176 (3.3 V, 44 MHz) and the ADSP-21061KS-200 (5 V, 50 MHz), o perating at t_CK<25 ns. For all other devices,

use the preceding timing specification of the same name.

³See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.

⁴t_DACKADis true only if the address and SW inputs have setup times (before CLKIN) greater than 10 + DT/8 and less than 19 + 3DT/4. If the address and SW inputs have

setup times greater than 19 + 3DT/4, then ACK is valid 15.5 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match will respond with ACK

regardless of the state of MMSWS or strobes. A slave will three-state ACK every cycle with t_ACKTR

.

CLKIN

t_SADRI

t_HADRI

ADDRESS

SW

t_DACKAD

t_ACKTR

ACK

READ ACCESS

t_SRWLI

t_HRWLI

t_RWHPI

RD

t_SDDATO

t_DATTR

DATA

(OUT)

WRITE ACCESS

t_RWHPI

t_SRWLI

t_HRWLI

WR

t_HDATWH

t_SDATWH

DATA

(IN)

REV. B

–25–

ADSP-21061/ADSP-21061L

Multiprocessor Bus Request and Host Bus Request

Use these specifications for passing of bus mastership between

multiprocessing ADSP-21061s (BRx) or a host processor

(HBR, HBG).

ADSP-21061 (5 V)

Max

ADSP-21061L (3.3 V)

Parameter

Min

Max

Unit

Timing Requirements:

t_HBGRCSV

t_SHBRI

t_HHBRI

t_SHBGI

t_HHBGI

t_SBRI

t_HBRI

t_SRPBAI

t_HRPBAI

HBG Low to RD/WR/CS Valid¹

20+ 5DT/4

14 + 3DT/4

6 + DT/2

20 + 5DT/4

14 + 3DT/4

6 + DT/2

ns

HBR Setup before CLKIN²

HBR Hold before CLKIN²

20 + 3DT/4

13 + DT/2

20 + 3DT/4

13 + DT/2

20 + 3DT/4

HBG Setup before CLKIN

HBG Hold before CLKIN High

BRx, CPA Setup before CLKIN³

BRx, CPA Hold before CLKIN High

RPBA Setup before CLKIN

RPBA Hold before CLKIN

6 + DT/2

12 + 3DT/4

Switching Characteristics:

t_DHBGO

t_HHBGO

t_DBRO

HBG Delay after CLKIN

7 – DT/8

ns

HBG Hold after CLKIN

BRx Delay after CLKIN

BRx Hold after CLKIN

CPA Low Delay after CLKIN

CPA Disable after CLKIN

REDY (O/D) or (A/D) Low from

CS and HBR Low⁴

–2 – DT/8

5.5 – DT/8

t_HBRO

t_DCPAO

t_TRCPA

t_DRDYCS

6.5 – DT/8

4.5 – DT/8

8.5 – DT/8

4.5 – DT/8

8

12

ns

t_TRDYHG

t_ARDYTR

REDY (O/D) Disable or REDY (A/D)

High from HBG⁴

44 + 27DT/16

40 + 27DT/16

REDY (A/D) Disable from CS or

HBR High⁴

10

NOTES

¹For first asynchronous access after HBR and CS asserted, ADDR_31-0must be a non-MMS value 1/2 t_CKbefore RD or WR goes low or by t_HBGRCSVafter HBG goes

low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the Host Processor Control of the ADSP-2106x section in the

ADSP-2106x SHARC User’s Manual, Second Edition.

²Only required for recognition in the current cycle.

³CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN.

⁴(O/D) = open drain, (A/D) = active drive.

REV. B

–26–

ADSP-21061/ADSP-21061L

CLKIN

t_SHBRI

t_HHBRI

HBR

t_DHBGO

t_HHBGO

HBG

(OUT)

t_DBRO

t_HBRO

BRx

(OUT)

t_DCPAO

t_TRCPA

CPA (OUT)

(O/D)

t_SHBGI

t_HHBGI

HBG (IN)

t_SBRI

t_HBRI

BRx (IN)

CPA (IN) (O/D)

t_SRPBAI

t_HRPBAI

RPBA

HBR

CS

t_TRDYHG

t_DRDYCS

REDY (O/D)

REDY (A/D)

HBG (OUT)

t_ARDYTR

t_HBGRCSV

RD

WR

CS

O/D = OPEN DRAIN, A/D = ACTIVE DRIVE

Figure 17. Multiprocessor Bus Request and Host Bus Request

REV. B

–27–

ADSP-21061/ADSP-21061L

Asynchronous Read/Write—Host to ADSP-21061

drive the RD and WR pins to access the ADSP-21061’s internal

memory or IOP registers. HBR and HBG are assumed low for

this timing.

Use these specifications for asynchronous host processor accesses

of an ADSP-21061, after the host has asserted CS and HBR

(low). After HBG is returned by the ADSP-21061, the host can

ADSP-21061 (5 V)

Max

ADSP-21061L (3.3 V)

Parameter

Min

Max

Unit

Read Cycle

Timing Requirements:

t_SADRDL

t_HADRDH

t_WRWH

Address Setup/CS Low before RD Low¹

Address Hold/CS Hold Low after RD

RD/WR High Width

0

6

0

6

0

ns

t_DRDHRDY

RD High Delay after REDY (O/D) Disable

RD High Delay after REDY (A/D) Disable

Switching Characteristics:

t_SDATRDY

t_DRDYRDL

t_RDYPRD

Data Valid before REDY Disable from Low

2

ns

REDY (O/D) or (A/D) Low Delay after RD Low

REDY (O/D) or (A/D) Low Pulsewidth for Read

Data Disable after RD High

10

13.5

8

45 + DT

2

45 + DT

2

t_HDARWH

8

Write Cycle

Timing Requirements:

t_SCSWRL

t_HCSWRH

t_SADWRH

t_HADWRH

t_WWRL

t_WRWH

t_DWRHRDY

CS Low Setup before WR Low

CS Low Hold after WR High

Address Setup before WR High

Address Hold after WR High

WR Low Width

RD/WR High Width

WR High Delay after REDY (O/D) or (A/D) Disable

Data Setup before WR High

0

5

2

8

6

0

3

0

5

2

8

6

0

3

ns

t_SDATWH

t_SDATWH(50 MHz) Data Setup before WR High, t_CK= 20 ns²

2.5

1

t_HDATWH

Data Hold after WR High

1

Switching Characteristics:

t_DRDYWRL

t_RDYPWR

t_SRDYCK

REDY (O/D) or (A/D) Low Delay after WR/CS Low

REDY (O/D) or (A/D) Low Pulsewidth for Write

REDY (O/D) or (A/D) Disable to CLKIN

11

13.5

ns

15

1 + 7DT/16

8 + 7DT/16 1 + 7DT/16

8 + 7DT/16 ns

NOTES

¹Not required if RD and address are valid t_HBGRCSVafter HBG goes low. For first access after HBR asserted, ADDR_31-0must be a non-MMS value 1/2 t_CLKbefore RD

or WR goes low or by t_HBGRCSVafter HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the Host Proces-

sor Control of the ADSP-2106x section in the ADSP-2106x SHARC User’s Manual, Second Edition.

²This specification applies to the ADSP-21061KS-200 (5 V, 50 MHz) operating at t_CK< 25 ns. For all other devices, use the preceding timing specification of the

same name.

CLKIN

t_SRDYCK

REDY (O/D)

REDY (A/D)

O/D = OPEN DRAIN, A/D = ACTIVE DRIVE

Figure 18a. Synchronous REDY Timing

REV. B

–28–

ADSP-21061/ADSP-21061L

READ CYCLE

ADDRESS/CS

t_HADRDH

t_SADRDL

t_WRWH

RD

t_HDARWH

DATA (OUT)

t_DRDHRDY

t_SDATRDY

t_RDYPRD

t_DRDYRDL

REDY (O/D)

REDY (A/D)

WRITE CYCLE

ADDRESS

t_HADWRH

t_SADWRH

t_HCSWRH

t_SCSWRL

CS

t_WWRL

t_WRWH

WR

t_HDATWH

t_SDATWH

DATA (IN)

t_DWRHRDY

t_DRDYWRL

t_RDYPWR

REDY (O/D)

REDY (A/D)

O/D = OPEN DRAIN, A/D = ACTIVE DRIVE

Figure 18b. Asynchronous Read/Write—Host to ADSP-2106x

REV. B

–29–

ADSP-21061/ADSP-21061L

Three-State Timing—Bus Master, Bus Slave, HBR, SBTS

These specifications show how the memory interface is disabled

(stops driving) or enabled (resumes driving) relative to CLKIN

and the SBTS pin. This timing is applicable to bus master tran-

sition cycles (BTC) and host transition cycles (HTC) as well as

the SBTS pin.

ADSP-21061 (5 V)

ADSP-21061L (3.3 V)

Parameter

Min

Max

Min

Max

Unit

Timing Requirements:

t_STSCK

t_HTSCK

SBTS Setup before CLKIN

SBTS Hold before CLKIN

12 + DT/2

ns

6 + DT/2

Switching Characteristics:

t_MIENA

t_MIENS

t_MIENHG

t_MITRA

Address/Select Enable after CLKIN

–1 – DT/8

–1.5 – DT/8

–1 – DT/8

–1.5 – DT/8

ns

Strobes Enable after CLKIN¹

HBG Enable after CLKIN

Address/Select Disable after CLKIN

Strobes Disable after CLKIN¹

HBG Disable after CLKIN

0 – DT/4

1.5 – DT/4

2 – DT/4

0 – DT/4

1.5 – DT/4

2 – DT/4

t_MITRS

t_MITRHG

t_DATEN

t_DATTR

t_ACKEN

t_ACKTR

t_ADCEN

t_ADCTR

t_MTRHBG

t_MENHBG

Data Enable after CLKIN²

9 + 5DT/16

0 – DT/8

7.5 + DT/4

–1 – DT/8

–2 – DT/8

9 + 5DT/16

0 – DT/8

7.5 + DT/4

–1 – DT/8

–2 – DT/8

Data Disable after CLKIN²

7 – DT/8

6 – DT/8

8 – DT/4

7 – DT/8

6 – DT/8

8 – DT/4

ACK Enable after CLKIN²

ACK Disable after CLKIN²

ADRCLK Enable after CLKIN

ADRCLK Disable after CLKIN

Memory Interface Disable before HBG Low³

Memory Interface Enable after HBG High³

0 + DT/8

19 + DT

0 + DT/8

19 + DT

NOTES

¹Strobes = RD, WR, MSx, SW, PAGE, DMAG, BMS.

²In addition to bus master transition cycles, these specifications also apply to bus master and bus slave synchronous read/write.

³Memory Interface = Address, RD, WR, MSx, SW, HBG, PAGE, DMAGx, BMS (in EPROM boot mode).

REV. B

–30–

ADSP-21061/ADSP-21061L

CLKIN

SBTS

t_STSCK

t_HTSCK

t_MITRA,t_MITRS,t_MITRHG

t_MIEN

MEMORY

INTERFACE

t_DATTR

t_DATEN

DATA

t_ACKTR

t_ACKEN

ACK

t_ADCEN

t_ADCTR

ADRCLK

Figure 19a. Three-State Timing (Bus Transition Cycle, SBTS Assertion)

HBG

t_MTRHBG

t_MENHBG

MEMORY

INTERFACE

MEMORY INTERFACE = ADDRESS, RD, WR, MSx, SW, PAGE, DMAGx. BMS (IN EPROM BOOT MODE)

Figure 19b. Three-State Timing (Host Transition Cycle)

REV. B

–31–

ADSP-21061/ADSP-21061L

DMA Handshake

transfer is controlled by ADDR_31-0, RD, WR, MS_3-0and ACK

(not DMAG). For Paced Master mode, the Memory Read–Bus

Master, Memory Write–Bus Master, and Synchronous Read/

Write–Bus Master timing specifications for ADDR_31-0, RD,

WR, MS_3-0, SW, PAGE, DATA_47-0and ACK also apply.

These specifications describe the three DMA handshake modes.

In all three modes DMAR is used to initiate transfers. For hand-

shake mode, DMAG controls the latching or enabling of data

externally. For external handshake mode, the data transfer is

controlled by the ADDR_31-0, RD, WR, SW, PAGE, MS_3-0

,

ACK and DMAG signals. For Paced Master mode, the data

ADSP-21061 (5 V)

ADSP-21061L (3.3 V)

Parameter

Min

Max

Min

Max

Unit

Timing Requirements:

t_SDRLC

t_SDRHC

t_WDR

DMARx Low Setup before CLKIN¹

5

6

5

6

ns

DMARx High Setup before CLKIN¹

DMARx Width Low (Nonsynchronous)

t_SDATDGLData Setup after DMAGx Low²

t_HDATIDGData Hold after DMAGx High

10 + 5DT/8

16 + 7DT/8

10 + 5DT/8

16 + 7DT/8

2

t_DATDRH

t_DMARLL

t_DMARH

Data Valid after DMARx High²

DMAGx Low Edge to Low Edge

DMAGx Width High

23 + 7DT/8

6

23.5 + 7DT/8

6

Switching Characteristics:

t_DDGL

DMAGx Low Delay after CLKIN

DMAGx High Width

DMAGx Low Width

DMAGx High Delay after CLKIN

Address Select Valid to DMAGx High

Address Select Hold to DMAGx High

9 + DT/4

6 + 3DT/8

12 + 5DT/8

–2 – DT/8

17 + DT

–0.5

8 + 9DT/16

0

10 + 5DT/8 + W

1 + DT/16

0

11 + 9DT/16 + W

0

15 + DT/4

6 – DT/8

9 + DT/4

6 + 3DT/8

12 + 5DT/8

–2 – DT/8

17 + DT

–1.0

8 + 9DT/16

0

10 + 5DT/8 + W

1 + DT/16

0

11 + 9DT/16 + W

0

15 + DT/4

6 – DT/8

ns

t_WDGH

t_WDGL

t_HDGC

t_DADGH

t_DDGHA

t_VDATDGHData Valid before DMAGx High³

t_DATRDGHData Disable after DMAGx High⁴

7

2

7

2

t_DGWRL

t_DGWRH

t_DGWRR

t_DGRDL

t_DRDGH

t_DGRDR

t_DGWR

WR Low before DMAGx Low

DMAGx Low before WR High

WR High before DMAGx High

RD Low before DMAGx Low

RD Low before DMAGx High

RD High before DMAGx High

DMAGx High to WR, RD, DMAGx Low

3 + DT/16

2

3 + DT/16

2

3

5 + 3DT/8 + HI

W = (number of wait states specified in WAIT register) × t_CK

.

HI = t_CK(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

NOTES

¹Only required for recognition in the current cycle.

²t_SDATDGLis the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the

data can be driven t_DATDRHafter DMARx is brought high.

³t_VDATDGHis valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then t_VDATDGH= 8 + 9DT/16 + (n × t_CK) where

n equals the number of extra cycles that the access is prolonged.

⁴See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.

REV. B

–32–

ADSP-21061/ADSP-21061L

CLKIN

t_SDRLC

t_DMARLL

t_SDRHC

t_WDR

t_DMARH

DMARx

DMAGx

t_HDGC

t_DDGL

t_WDGL

t_WDGH

TRANSFERS BETWEEN ADSP-2106x INTERNAL MEMORY AND EXTERNAL DEVICE

t_DATRDGH

t_VDATDGH

DATA (FROM

ADSP-2106x TO

EXTERNAL DRIVE)

t_DATDRH

t_HDATIDG

t_SDATDGL

DATA (FROM

EXTERNAL DRIVE

TO ADSP-2106x)

TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE)

t_DGWRL

t_DGWRH

t_DGWRR

WR

(EXTERNAL DEVICE

TO EXTERNAL

MEMORY)

t_DGRDR

t_DGRDL

RD

(EXTERNAL

MEMORY TO

EXTERNAL DEVICE)

t_DRDGH

t_DDGHA

t_DADGH

ADDRESS

SW, MSx

*

“MEMORY READ – BUS MASTER,” “MEMORY WRITE – BUS MASTER” AND “SYNCHRONOUS READ/WRITE – BUS MASTER”

TIMING SPECIFICATIONS FOR ADDR , RD, WR, SW, MS AND ACK ALSO APPLY HERE.

31-0 3-0

Figure 20. DMA Handshake Timing

REV. B

–33–

ADSP-21061/ADSP-21061L

Serial Ports

ADSP-21061 (5 V)

Max

ADSP-21061L (3.3 V)

Parameter

Min

Max

Unit

External Clock

Timing Requirements:

t_SFSE

TFS/RFS Setup before TCLK/RCLK¹

TFS/RFS Hold after TCLK/RCLK^{1, 2}

Receive Data Setup before RCLK¹

Receive Data Hold after RCLK¹

TCLK/RCLK Width

3.5

4

1.5

4

9

3.5

4

1.5

4

9

ns

t_HFSE

t_SDRE

t_HDRE

t_SCLKW

t_SCLK

TCLK/RCLK Period

t_CK

Internal Clock

Timing Requirements:

t_SFSI

TFS Setup before TCLK¹; RFS Setup before RCLK¹

8

1

3

8

1

3

ns

t_HFSI

t_SDRI

t_HDRI

TFS/RFS Hold after TCLK/RCLK^{1, 2}

Receive Data Setup before RCLK¹

Receive Data Hold after RCLK¹

External or Internal Clock

Switching Characteristics:

t_DFSE

t_HOFSE

RFS Delay after RCLK (Internally Generated RFS)³

13

ns

RFS Hold after RCLK (Internally Generated RFS)³

3

External Clock

Switching Characteristics:

t_DFSE

TFS Delay after TCLK (Internally Generated TFS)³

13

16

13

16

ns

t_HOFSE

t_DDTE

t_HODTE

TFS Hold after TCLK (Internally Generated TFS)³

Transmit Data Delay after TCLK³

3

5

3

5

Transmit Data Hold after TCLK³

Internal Clock

Switching Characteristics:

t_DFSI

TFS Delay after TCLK (Internally Generated TFS)³

4.5

7.5

4.5

ns

t_HOFSI

t_DDTI

t_HDTI

TFS Hold after TCLK (Internally Generated TFS)³

Transmit Data Delay after TCLK³

–1.5

0

–1.5

7.5

Transmit Data Hold after TCLK³

0

t_SCLKIWTCLK/RCLK Width

(t_SCLK/2) – 2.5

(t_SCLK/2) + 2.5

(t_SCLK/2) – 2.5

(t_SCLK/2) + 2.5

Enable and Three-State

Switching Characteristics:

t_DDTEN

t_DDTTE

t_DDTIN

t_DDTTI

t_DCLK

Data Enable from External TCLK³

4.5

0

3.5

ns

Data Disable from External TCLK³

Data Enable from Internal TCLK³

Data Disable from Internal TCLK³

TCLK/RCLK Delay from CLKIN

SPORT Disable after CLKIN

10.5

–0.5

3

22 + 3DT/8

17

22 + 3DT/8

17

t_DPTR

External Late Frame Sync

Switching Characteristics:

t_DDTLFSEData Delay from Late External TFS or

External RFS with MCE = 1, MFD = 0⁴

t_DDTENFSData Enable from late FS or MCE = 1, MFD = 0⁴

12

ns

3.5

To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame

sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width.

NOTES

¹Referenced to sample edge.

²RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external. TFS is 0 ns minimum from drive edge.

³Referenced to drive edge.

⁴MCE = 1, TFS enable and TFS valid follow t_DDTLFSEand t_DDTENFS

.

REV. B

–34–

ADSP-21061/ADSP-21061L

DATA RECEIVE– INTERNAL CLOCK

DATA RECEIVE– EXTERNAL CLOCK

SAMPLE

EDGE

DRIVE

EDGE

DRIVE

EDGE

SAMPLE

EDGE

t_SCLKIW

t_SCLKW

RCLK

t_DFSE

t_HOFSE

t_DFSE

t_HOFSE

t_HFSE

t_SFSI

t_HFSI

t_SFSE

RFS

DR

RFS

DR

t_SDRE

t_HDRE

t_SDRI

t_HDRI

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DATA TRANSMIT– INTERNAL CLOCK

DATA TRANSMIT– EXTERNAL CLOCK

SAMPLE

EDGE

DRIVE

EDGE

DRIVE

EDGE

SAMPLE

EDGE

t_SCLKIW

t_SCLKW

TCLK

t_DFSI

t_HOFSI

t_DFSE

t_HOFSE

t_SFSI

t_HFSI

t_HFSE

t_SFSE

TFS

t_DDTI

t_DDTE

t_HDTI

t_HDTE

DT

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DRIVE

EDGE

DRIVE

EDGE

TCLK (EXT)

TFS ("LATE" EXT)

TCLK / RCLK

t_DDTEN

t_DDTTE

DT

DRIVE

EDGE

DRIVE

EDGE

TCLK (INT)

TFS ("LATE", INT)

TCLK / RCLK

t_DDTIN

t_DDTTI

DT

CLKIN

t_DPTR

SPORT ENABLE AND

THREE-STATE

LATENCY

TCLK, RCLK

TFS, RFS, DT

SPORT DISABLE DELAY

FROM INSTRUCTION

IS TWO CYCLES

t_DCLK

TCLK (INT)

RCLK (INT)

LOW TO HIGH ONLY

Figure 21. Serial Ports

REV. B

–35–

ADSP-21061/ADSP-21061L

EXTERNAL RFS WITH MCE = 1, MFD = 0

DRIVE

SAMPLE

DRIVE

RCLK

RFS

t_SFSE/I

t_HFSE/I

*

t_DDTE/I

t_HDTE/I

t_DDTENFS

DT

1ST BIT

2ND BIT

t_DDTLFSE

LATE EXTERNAL TFS

SAMPLE

DRIVE

TCLK

t_SFSE/I

*

t_HFSE/I

TFS

t_DDTE/I

t_HDTE/I

t_DDTENFS

DT

1ST BIT

2ND BIT

t_DDTLFSE

*RFS HOLD AFTER RCK WHEN MCE = 1, MFD = 0 IS 0ns MINIMUM FROM DRIVE EDGE.

TFS HOLD AFTER TCK FOR LATE EXTERNAL. TFS IS 0ns MINIMUM FROM DRIVE EDGE.

Figure 22. External Late Frame Sync

REV. B

–36–

ADSP-21061/ADSP-21061L

JTAG Test Access Port and Emulation

ADSP-21061 (5 V)

ADSP-21061L (3.3 V)

Parameter

Min

Max

Min

Max

Unit

Timing Requirements:

t_TCK

TCK Period

t_CK

6

7

18

t_CK

6

7

18

ns

t_STAP

t_HTAP

t_SSYS

t_HSYS

TDI, TMS Setup before TCK High

TDI, TMS Hold after TCK High

System Inputs Setup before TCK Low¹

System Inputs Hold after TCK Low¹

t_TRSTWTRST Pulsewidth

4t_CK

Switching Characteristics:

t_DTDO

t_DSYS

TDO Delay from TCK Low

13

18.5

13

18.5

ns

System Outputs Delay after TCK Low²

NOTES

¹System Inputs = DATA_47-0, ADDR_31-0, RD, WR, ACK, SBTS, SW, HBR, HBG, CS, DMAR1, DMAR2, BR_6-1, ID_2-0, RPBA, IRQ_2-0, FLAG_3-0, DR0, DR1,

TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, EBOOT, LBOOT, BMS, CLKIN, RESET.

²System Outputs = DATA_47-0, ADDR_31-0, MS_3-0, RD, WR, ACK, PAGE, ADRCLK, SW, HBG, REDY, DMAG1, DMAG2, BR_6-1, CPA, FLAG_3-0, TIMEXP, DT0,

DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, BMS.

t_TCK

TCK

t_STAP

t_HTAP

TMS

TDI

t_DTDO

TDO

t_SSYS

t_HSYS

SYSTEM

INPUTS

t_DSYS

SYSTEM

OUTPUTS

Figure 23. JTAG Test Access Port and Emulation

REV. B

–37–

ADSP-21061/ADSP-21061L

OUTPUT DRIVE CURRENTS

Table III. External Power Calculations (3.3 V Device)

Figure 27 shows typical I-V characteristics for the output drivers

of the ADSP-2106x. The curves represent the current drive

capability of the output drivers as a function of output voltage.

Type

# of

%

2

Pins Switching

؋

C

؋

f

؋

V_DD= P_EXT

Address

MS0

WR

Data

ADDRCLK

15

1

32

1

50

0

–

50

–

× 44.7 pF × 10 MHz × 10.9 V = 0.037 W

× 44.7 pF × 10 MHz × 10.9 V = 0.000 W

× 44.7 pF × 20 MHz × 10.9 V = 0.010 W

× 14.7 pF × 10 MHz × 10.9 V = 0.026 W

× 4.7 pF × 20 MHz × 10.9 V = 0.001 W

POWER DISSIPATION

Total power dissipation has two components, one due to inter-

nal circuitry and one due to the switching of external output

drivers. Internal power dissipation is dependent on the instruc-

tion execution sequence and the data operands involved. Inter-

nal power dissipation is calculated in the following way:

P_EXT= 0.074 W

A typical power consumption can now be calculated for these

conditions by adding a typical internal power dissipation:

P_INT= I_DDIN× V_DD

The external component of total power dissipation is caused by

the switching of output pins. Its magnitude depends on:

P

_TOTAL= P_EXT+ (I_DDIN2× 5.0 V )

Note that the conditions causing a worst-case P_EXTare different

from those causing a worst-case P_INT. Maximum P_INTcannot

occur while 100% of the output pins are switching from all ones

to all zeros. Note also that it is not common for an application to

have 100% or even 50% of the outputs switching simultaneously.

– the number of output pins that switch during each cycle (O)

– the maximum frequency at which they can switch (f)

– their load capacitance (C)

– their voltage swing (V_DD

)

and is calculated by:

TEST CONDITIONS

Output Disable Time

P

_EXT= O × C × V_DD²× f

Output pins are considered to be disabled when they stop driv-

ing, go into a high impedance state, and start to decay from

their output high or low voltage. The time for the voltage on the

bus to decay by ∆V is dependent on the capacitive load, C_Land

the load current, I_L. This decay time can be approximated by

the following equation:

The load capacitance should include the processor’s package

capacitance (C_IN). The switching frequency includes driving the

load high and then back low. Address and data pins can drive

high and low at a maximum rate of 1/(2t_CK). The write strobe

can switch every cycle at a frequency of 1/t_CK. Select pins switch

at 1/(2t_CK), but selects can switch on each cycle.

C

∆V

Example:

L

t

=

DECAY

I

L

Estimate P_EXTwith the following assumptions:

The output disable time t_DISis the difference between t_MEASURED

and t_DECAYas shown in Figure 24. The time t_MEASUREDis the

interval from when the reference signal switches to when the

output voltage decays ∆V from the measured output high or

output low voltage. t_DECAYis calculated with test loads C_Land

I_L, and with ∆V equal to 0.5 V.

–A system with one bank of external data memory RAM (32-bit)

–Four 128K × 8 RAM chips are used, each with a load of 10 pF

–External data memory writes occur every other cycle, a rate

of 1/(4t_CK), with 50% of the pins switching

–The instruction cycle rate is 40 MHz (t_CK= 25 ns).

The P_EXTequation is calculated for each class of pins that can

drive:

Output Enable Time

Output pins are considered to be enabled when they have made

a transition from a high impedance state to when they start

driving. The output enable time t_ENAis the interval from when a

reference signal reaches a high or low voltage level to when the

output has reached a specified high or low trip point, as shown

in the Output Enable/Disable diagram (Figure 24). If multiple

pins (such as the data bus) are enabled, the measurement value

is that of the first pin to start driving.

Table II. External Power Calculations (5 V Device)

Type

# of

%

2

Pins Switching

؋

C

؋

f

؋

V_DD= P_EXT

Address

MS0

15

1

32

1

50

0

–

50

–

× 44.7 pF × 10 MHz × 25 V = 0.084 W

× 44.7 pF × 10 MHz × 25 V = 0.000 W

× 44.7 pF × 20 MHz × 25 V = 0.022 W

× 14.7 pF × 10 MHz × 25 V = 0.059 W

× 4.7 pF × 20 MHz × 25 V = 0.002 W

WR

Data

ADDRCLK

P

_EXT= 0.167 W

REV. B

–38–

ADSP-21061/ADSP-21061L

Capacitive Loading

Example System Hold Time Calculation

Output delays and holds are based on standard capacitive loads:

50 pF on all pins (see Figure 25). The delay and hold specifica-

tions given should be derated by a factor of 1.5 ns/50 pF for

loads other than the nominal value of 50 pF. Figures 28–29,

32–33 show how output rise time varies with capacitance. Fig-

ures 30, 34 show graphically how output delays and holds vary

with load capacitance. (Note that this graph or derating does

not apply to output disable delays; see the previous section

Output Disable Time under Test Conditions.) The graphs of

Figures 28, 29 and 30 may not be linear outside the ranges

shown.

To determine the data output hold time in a particular system,

first calculate t_DECAYusing the equation given above. Choose ∆V

to be the difference between the ADSP-2106x’s output voltage

and the input threshold for the device requiring the hold time. A

typical ∆V will be 0.4 V. C_Lis the total bus capacitance (per

data line), and I_Lis the total leakage or three-state current (per

data line). The hold time will be t_DECAYplus the minimum

disable time (i.e., t_DATRWHfor the write cycle).

REFERENCE

SIGNAL

INPUT OR

OUTPUT

t_MEASURED

1.5V

t_ENA

t_DIS

V

Figure 26. Voltage Reference Levels for AC Measure-

ments (Except Output Enable/Disable)

OH (MEASURED)

V

OH (MEASURED)

V

– ⌬V

+ ⌬V

2.0V

1.0V

OH (MEASURED)

OUTPUT

OL (MEASURED)

V

OL (MEASURED)

t_DECAY

OUTPUT STARTS

DRIVING

OUTPUT STOPS

DRIVING

HIGH-IMPEDANCE STATE.

TEST CONDITIONS CAUSE

THIS VOLTAGE TO BE

APPROXIMATELY 1.5V

Figure 24. Output Enable/Disable

I

OL

TO

OUTPUT

+1.5V

50pF

I

OH

Figure 25. Equivalent Device Loading for AC Measure-

ments (Includes All Fixtures)

REV. B

–39–

ADSP-21061/ADSP-21061L

100

5

4

3

2

1

75

50

25

5.25V, –40؇C

0

5.0V, +25؇C

Y = 0.03X –1.45

4.75V, +85؇C

–25

–50

4.75V, +85

؇C

–75

–100

–125

5.0V, +25

؇

C

5.25V, –40؇C

–150

–175

–200

NOMINAL

–1

0

0.75

1.50

2.25

3.00

3.75

4.50

5.25

25

50

75

100

125

150

175

200

SOURCE VOLTAGE – V

LOAD CAPACITANCE – pF

Figure 27. ADSP-2106x Typical Drive Currents (V_DD= 5 V)

Figure 30. Typical Output Delay or Hold vs. Load Capaci-

tance (at Maximum Case Temperature) (V_DD= 5 V)

16.0

14.0

12.0

120

100

80

3.6V –40؇C

3.3V +25؇C

3.0V +85؇C

60

40

RISE TIME

10.0

V

20

OH

Y = 0.005X + 3.7

8.0

0

FALL TIME

–20

–40

–60

–80

–100

–120

6.0

3.0V +85؇C

4.0

3.3V +25؇C

3.6V –40؇C

2.0

0

Y = 0.0031X + 1.1

V

OL

0

20

40

60

80

100 120 140 160 180 200

0

0.5

1

1.5

2

2.5

3

3.6

LOAD CAPACITANCE – pF

SOURCE VOLTAGE – Volts

Figure 28. Typical Output Rise Time (10%–90% V_DD) vs.

Load Capacitance (V_DD= 5 V)

Figure 31. ADSP-2106x Typical Drive Currents (V_DD= 3.3 V)

18

16

3.5

3.0

2.5

14

Y = 0.0796X + 1.17

12

RISE TIME

10

2.0

Y = 0.009X + 1.1

RISE TIME

8

1.5

6

4

2

0

Y = 0.0467X + 0.55

FALL TIME

1.0

FALL TIME

Y = 0.005X + 0.6

0.5

0

20

40

60

80 100 120 140 160 180 200

0

20

40

60

80

100 120 140 160 180 200

LOAD CAPACITANCE – pF

Figure 29. Typical Output Rise Time (0.8 V–2.0 V) vs.

Load Capacitance (V_DD= 5 V)

Figure 32. Typical Output Rise Time (10%–90% V_DD) vs.

Load Capacitance (V_DD= 3.3 V)

REV. B

–40–

ADSP-21061/ADSP-21061L

ENVIRONMENTAL CONDITIONS

9

8

Thermal Characteristics

The ADSP-21061KS (5 V) device is packaged in a 240-lead

thermally enhanced MQFP. The top surface of the package

contains a copper slug from which most of the die heat is dissi-

pated. The slug is flush with the top surface of the package.

Note that the copper slug is internally connected to GND

through the device substrate. The ADSP-21061LKS is packaged

in a 240-lead MQFP without a copper heat slug. The ADSP-

21061L is also available in a 225-Ball PBGA package. The

PBGA has a θ_JCof 1.7°C/W. The ADSP-2106x is specified for a

case temperature (T_CASE). To ensure that the T_CASEdata sheet

specification is not exceeded, a heatsink and/or an air flow

source may be used. A heatsink should be attached with a ther-

mal adhesive.

7

6

Y = 0.0391X + 0.36

5

4

RISE TIME

Y = 0.0305X + 0.24

3

2

1

0

FALL TIME

0

20

40

60

80 100 120 140 160 180 200

LOAD CAPACITANCE – pF

T_{CASE =}T_AMB+ ( PD × θ_CA

)

Figure 33. Typical Output Rise Time (0.8 V–2.0 V) vs.

Load Capacitance (V_DD= 3.3 V)

T

PD =

_CASE= Case temperature (measured on top surface of package)

Power dissipation in W (this value depends upon the

specific application; a method for calculating PD is

shown under Power Dissipation).

5

θ_CA

=

Value from tables below.

4

3

2

1

Y = 0.0329X –1.65

ADSP-21061 (5 V MQFP Package)

␪

_JC= 0.3؇C/W

Airflow

(Linear Ft./Min.)

0

100

200

400

600

θ_CA(°C/W)

10

9

8

7

6

NOTES

This represents thermal resistance at total power of 5 W.

NOMINAL

With air flow, no variance is seen in θ_CAwith power.

θ_CAat 0 LFM varies with power: at 2W, θ_CA= 14°C/W, at 3W θ_CA= 11°C/W.

–1

25

50

75

100

125

150

175

200

ADSP-21061L (3.3 V MQFP Package)

LOAD CAPACITANCE – pF

Figure 34. Typical Output Delay or Hold vs. Load Capaci-

tance (at Maximum Case Temperature) (V_DD= 3.3 V)

␪

_JC= 6.3؇C/W

Airflow

(Linear Ft./Min.)

0

100

200

400

600

θ_CA(°C/W)

19.6

17.6

15.6

13.9

12.2

NOTE

With air flow, no variance is seen in θ_CAwith power.

ADSP-21061L (3.3 V PBGA Package)

␪

_JC= 1.7؇C/W

Airflow

(Linear Ft./Min.)

0

200

400

11.2

θ_CA(°C/W)

19.0

13.6

NOTE

With air flow, no variance is seen in θ_CAwith power.

REV. B

–41–

ADSP-21061/ADSP-21061L

240-LEAD METRIC MQFP PIN CONFIGURATIONS

240

181

1

180

TOP VIEW

60

121

61

120

Pin Pin

No. Name

Pin Pin

No. Name

Pin Pin

No. Name

Pin Pin

No. Name

Pin Pin

No. Name

1

2

3

4

5

6

7

8

TDI

TRST

VDD

TDO

TIMEXP

EMU

ICSA

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

ADDR20

ADDR21

GND

ADDR22

ADDR23

ADDR24

VDD

GND

VDD

ADDR25

ADDR26

ADDR27

GND

MS3

MS2

MS1

MS0

SW

BMS

ADDR28

GND

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

TCLK0

TFS0

DR0

201 NC

202 NC

203 NC

204 NC

205 VDD

206 NC

207 NC

208 NC

209 NC

210 NC

211 NC

212 GND

213 NC

214 NC

215 NC

216 NC

217 NC

218 NC

219 VDD

220 GND

221 VDD

222 NC

223 NC

224 NC

225 NC

226 NC

227 NC

228 GND

229 ID2

230 ID1

231 ID0

232 LBOOT

233 RPBA

234 RESET

235 EBOOT

236 IRQ2

237 IRQ1

238 IRQ0

239 TCK

240 TMS

161 DATA14

162 DATA13

163 DATA12

164 GND

165 DATA11

166 DATA10

167 DATA9

168 VDD

169 DATA8

170 DATA7

171 DATA6

172 GND

173 DATA5

174 DATA4

175 DATA3

176 VDD

177 DATA2

178 DATA1

179 DATA0

180 GND

181 GND

182 NC

183 NC

184 NC

185 NC

186 NC

187 NC

188 VDD

189 NC

190 NC

191 NC

121 DATA41

122 DATA40

123 DATA39

124 VDD

125 DATA38

126 DATA37

127 DATA36

128 GND

RCLK0

RFS0

VDD

GND

ADRCLK

REDY

HBG

CS

FLAG3

FLAG2

FLAG1

FLAG0

GND

ADDR0

ADDR1

VDD

ADDR2

ADDR3

ADDR4

GND

ADDR5

ADDR6

ADDR7

VDD

ADDR8

ADDR9

ADDR10

GND

ADDR11

ADDR12

ADDR13

VDD

ADDR14

ADDR15

GND

ADDR16

ADDR17

ADDR18

VDD

9

129 NC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

130 DATA35

131 DATA34

132 DATA33

133 VDD

134 VDD

135 GND

136 DATA32

137 DATA31

138 DATA30

139 GND

140 DATA29

141 DATA28

142 DATA27

143 VDD

RD

WR

GND

VDD

GND

CLKIN

ACK

100 DMAG2

101 DMAG1

102 PAGE

103 VDD

104 BR6

105 BR5

106 BR4

107 BR3

108 BR2

109 BR1

110 GND

111 VDD

112 GND

113 DATA47

114 DATA46

115 DATA45

116 VDD

117 DATA44

118 DATA43

119 DATA42

120 GND

VDD

ADDR29

ADDR30

ADDR31

GND

144 VDD

145 DATA26

146 DATA25

147 DATA24

148 GND

149 DATA23

150 DATA22

151 DATA21

152 VDD

153 DATA20

154 DATA19

155 DATA18

156 GND

157 DATA17

158 DATA16

159 DATA15

160 VDD

SBTS

DMAR2

DMAR1

HBR

DT1

TCLK1

TFS1

DR1

RCLK1

RFS1

GND

CPA

192 NC

193 NC

194 NC

195 GND

196 GND

197 VDD

198 NC

199 NC

200 NC

VDD

ADDR19

DT0

REV. B

–42–

ADSP-21061/ADSP-21061L

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

240-Lead Metric Thermally Enhanced MQFP (5 V Device Only)

1.372 (34.85)

1.362 (34.60) TYP SQ

1.352 (34.35)

1.264 (32.10)

1.260 (32.00) TYP SQ

0.161 (4.10)

MAX

1.256 (31.90)

1.161 (29.50) BSC SQ

0.030 (0.75)

0.024 (0.60) TYP

0.020 (0.50)

240

181

180

1

240 LEAD METRIC MQFP

TOP VIEW (PINS DOWN)

SEATING

PLANE

LEAD PITCH

0.01969 (0.50)

TYP

HEAT

SLUG

LEAD WIDTH

0.011 (0.27)

0.009 (0.22) TYP

0.007 (0.17)

GND

INCHES (MILLIMETERS)

60

121

120

0.003 (0.08)

MAX

61

0.010 (0.25)

MIN

THE THERMALLY ENHANCED MQFP PACKAGE CONTAINS A

COPPER HEAT SLUG FLUSH WITH ITS TOP SURFACE; THE

SLUG IS EITHER CONNECTED TO GROUND OR FLOATING.

0.138 (3.50)

0.134 (3.40) TYP THE HEAT SLUG DIAMETER IS 24.1 (0.949) mm.

0.130 (3.30)

NOTE:

THE ACTUAL POSITION OF EACH LEAD IS WITHIN (0.08)

0.0032 FROM ITS IDEAL POSITION WHEN MEASURED IN THE

LATERAL DIRECTION.

CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.

REV. B

–43–

ADSP-21061/ADSP-21061L

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

240-Lead Metric MQFP (3.3 V Device Only)

1.372 (34.85)

1.362 (34.60) TYP SQ

1.352 (34.35)

1.264 (32.10)

1.260 (32.00) TYP SQ

0.161 (4.10)

MAX

1.256 (31.90)

1.161 (29.50) BSC SQ

0.030 (0.75)

0.024 (0.60) TYP

0.020 (0.50)

240

181

180

1

240 LEAD METRIC MQFP

TOP VIEW (PINS DOWN)

SEATING

PLANE

LEAD PITCH

0.01969 (0.50)

TYP

LEAD WIDTH

0.011 (0.27)

0.009 (0.22) TYP

0.007 (0.17)

INCHES (MILLIMETERS)

60

121

120

0.003 (0.08)

MAX

61

0.010 (0.25)

MIN

NOTE:

THE ACTUAL POSITION OF EACH LEAD IS WITHIN (0.08)

0.0032 FROM ITS IDEAL POSITION WHEN MEASURED IN THE

LATERAL DIRECTION.

0.138 (3.50)

0.134 (3.40) TYP

0.130 (3.30)

CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.

REV. B

–44–

ADSP-21061/ADSP-21061L

ADSP-21061L 225-Ball Plastic Ball Grid Array (PBGA) Package Pinout

Ball #

Name

Ball #

Name

Ball #

Name

Ball #

Name

Ball #

Name

A01

A02

A03

A04

A05

A06

A07

A08

A09

A10

A11

A12

A13

A14

A15

BMS

D01

D02

D03

D04

D05

D06

D07

D08

D09

D10

D11

D12

D13

D14

D15

ADDR25

ADDR26

MS2

ADDR29

DMAR1

TFS1

CPA

HBG

DMAG2

BR5

BR1

G01

G02

G03

G04

G05

G06

G07

G08

G09

G10

G11

G12

G13

G14

G15

ADDR14

ADDR15

ADDR16

ADDR19

GND

VDD

GND

DATA22

DATA25

DATA24

DATA23

K01

K02

K03

K04

K05

K06

K07

K08

K09

K10

K11

K12

K13

K14

K15

ADDR6

ADDR5

ADDR3

ADDR0

ICSA

GND

VDD

GND

DATA8

DATA11

DATA13

DATA14

N01

N02

N03

N04

N05

N06

N07

N08

N09

N10

N11

N12

N13

N14

N15

EMU

TDO

IRQ0

IRQ1

ID2

NC

DATA1

DATA3

ADDR30

DMAR2

DT1

RCLK1

TCLK0

RCLK0

ADRCLK

CS

CLKIN

PAGE

BR3

DATA47

DATA44

DATA42

DATA40

DATA37

DATA35

DATA34

B01

B02

B03

B04

B05

B06

B07

B08

B09

B10

B11

B12

B13

B14

B15

MS0

SW

ADDR31

HBR

DR1

DT0

DR0

REDY

RD

ACK

BR6

BR2

DATA45

DATA43

DATA39

E01

E02

E03

E04

E05

E06

E07

E08

E09

E10

E11

E12

E13

E14

E15

ADDR21

ADDR22

ADDR24

ADDR27

GND

NC

H01

H02

H03

H04

H05

H06

H07

H08

H09

H10

H11

H12

H13

H14

H15

ADDR12

ADDR11

ADDR13

ADDR10

GND

VDD

GND

L01

L02

L03

L04

L05

L06

L07

L08

L09

L10

L11

L12

L13

L14

L15

ADDR2

ADDR1

FLAG0

FLAG3

RPBA

GND

NC

P01

P02

P03

P04

P05

P06

P07

P08

P09

P10

P11

P12

P13

P14

P15

TRST

TMS

EBOOT

ID0

NC

DATA33

DATA30

DATA32

DATA31

DATA18

DATA19

DATA21

DATA20

DATA4

DATA7

DATA9

DATA10

DATA0

C01

C02

C03

C04

C05

C06

C07

C08

C09

C10

C11

C12

C13

C14

C15

MS3

MS1

ADDR28

SBTS

TCLK1

RFS1

TFS0

RFS0

WR

DMAG1

BR4

F01

F02

F03

F04

F05

F06

F07

F08

F09

F10

F11

F12

F13

F14

F15

ADDR17

ADDR18

ADDR20

ADDR23

GND

VDD

GND

DATA29

DATA26

DATA28

DATA27

J01

J02

J03

J04

J05

J06

J07

J08

J09

J10

J11

J12

J13

J14

J15

ADDR9

ADDR8

ADDR7

ADDR4

GND

VDD

GND

DATA12

DATA15

DATA16

DATA17

M01

M02

M03

M04

M05

M06

M07

M08

M09

M10

M11

M12

M13

M14

M15

FLAG1

FLAG2

TIMEXP

TDI

GND

NC

DATA2

DATA5

DATA6

R01

R02

R03

R04

R05

R06

R07

R08

R09

R10

R11

R12

R13

R14

R15

TCK

IRQ2

RESET

ID1

NC

DATA46

DATA41

DATA38

DATA36

REV. B

–45–

ADSP-21061/ADSP-21061L

225-Ball Plastic Ball Grid Array (PBGA) Package Pinout

Bottom View

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

A

B

C

D

E

F

DATA42 DATA44 DATA47

BR3

PAGE

CLKIN

CS

ADRCLK RCLK0

TCLK0

RCLK1

DT1

DMAR2 ADDR30

BMS

DATA39 DATA43 DATA45

BR2

BR6

BR4

BR1

NC

ACK

DMAG1

BR5

RD

WR

REDY

RFS0

HBG

DR0

TFS0

CPA

GND

DT0

RFS1

TFS1

GND

DR1

HBR

ADDR31

ADDR28

MS2

SW

MS0

MS3

DATA36 DATA38 DATA41 DATA46

DATA34 DATA35 DATA37 DATA40

DATA31 DATA32 DATA30 DATA33

TCLK1

SBTS

MS1

DMAG2

GND

DMAR1 ADDR29

ADDR26 ADDR25

GND

ADDR27 ADDR24 ADDR22 ADDR21

DATA27 DATA28 DATA26 DATA29

DATA23 DATA24 DATA25 DATA22

GND

VDD

GND

VDD

GND

ADDR23 ADDR20 ADDR18 ADDR17

ADDR19 ADDR16 ADDR15 ADDR14

G

H

J

DATA20 DATA21 DATA19 DATA18

DATA17 DATA16 DATA15 DATA12

GND

VDD

GND

ADDR10 ADDR13 ADDR11 ADDR12

GND

NC

VDD

GND

VDD

GND

VDD

GND

VDD

GND

VDD

GND

ICSA

RPBA

ADDR4

ADDR0

FLAG3

ADDR7

ADDR3

FLAG0

ADDR8

ADDR5

ADDR1

ADDR9

ADDR6

ADDR2

DATA14 DATA13 DATA11

DATA8

DATA4

K

L

DATA10

DATA6

DATA9

DATA5

DATA7

DATA2

NC

GND

TDI

TIMEXP

FLAG2

FLAG1

M

N

P

R

DATA3

DATA0

NC

DATA1

NC

ID2

NC

IRQ1

ID0

IRQ0

TDO

TMS

IRQ2

EMU

TRST

TCK

EBOOT

RESET

NC

ID1

NC = NO CONNECT

REV. B

–46–

ADSP-21061/ADSP-21061L

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

Plastic Ball Grid Array (PBGA)

0.913 (23.20)

0.906 (23.00)

0.898 (22.80)

15141312 1110 9

8 7 6 5 4 3 2 1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

0.700

(17.78)

0.791 (20.10)

0.787 (20.00)

0.783 (19.90)

0.913 (23.20)

0.906 (23.00)

0.898 (22.80)

BSC

TOP VIEW

0.050

(1.27)

BSC

0.791 (20.10)

0.787 (20.00)

0.783 (19.90)

0.050 (1.27) BSC

0.700 (17.78) BSC

DETAIL A

0.051 (1.30)

0.047 (1.20)

0.043 (1.10)

0.101 (2.57)

0.091 (2.32)

0.081 (2.06)

0.026 (0.65)

0.024 (0.61)

0.022 (0.57)

0.006 (0.15) MAX

SEATING

PLANE

0.035 (0.90)

0.030 (0.75)

NOTE

THE ACTUAL POSITION OF THE BALL GRID IS WITHIN

0.012 (0.30) OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE

EDGES. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.004 (0.10)

OF ITS IDEAL POSITION RELATIVE TO THE BALL GRID.

0.024 (0.60)

BALL DIAMETER

ORDERING GUIDE

Case Temperature

On-Chip

SRAM

Operating

Voltage

Package

Option

Part Number

Range

Instruction Rate

ADSP-21061KS-133

ADSP-21061KS-160

ADSP-21061KS-200

ADSP-21061LKS-160

ADSP-21061LKS-176

ADSP-21061LAS-160

ADSP-21061LAS-176

ADSP-21061LKB-160

ADSP-21061LKB-176

0°C to +85°C

33 MHz

40 MHz

50 MHz

40 MHz

44 MHz

40 MHz

44 MHz

40 MHz

44 MHz

1 Mbit

5 V

3.3 V

MQFP

PBGA

0°C to +85°C

–40°C Case to +85°C Case

0°C to +85°C

The package options are as follows: the ADSP-21061 (5 V) is available in the 240-lead thermally enhanced package and the ADSP-21061L (3.3 V) is available in the

240-lead standard (no heat slug) package, and 225-Ball PBGA.

REV. B

–47–


型号：	ADSP-21061
厂家：	ADI
描述：	ADSP-2106x SHARC DSP Microcomputer Family ADSP- 2106x SHARC DSP单片机系列
文件：	总47页 (文件大小：366K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-21061 [ADI]

相关型号：

ADSP-21061KS-133

ADSP-21061KS-160

ADSP-21061KS-200

ADSP-21061KS-200X

ADSP-21061KSZ-133

ADSP-21061KSZ-160

ADSP-21061KSZ-200

ADSP-21061L

ADSP-21061LAS-160

ADSP-21061LAS-176

ADSP-21061LASZ-176

ADSP-21061LKB-160