ADSP-21065LCS-240 [ADI]
DSP Microcomputer; 微电脑DSP型号: | ADSP-21065LCS-240 |
厂家: | ADI |
描述: | DSP Microcomputer |
文件: | 总44页 (文件大小:329K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
a
DSP Microcomputer
ADSP-21065L
SUMMARY
SDRAM Controller for Glueless Interface to Low Cost
External Memory (@ 66 MHz)
High Performance Signal Computer for Communica-
tions, Audio, Automotive, Instrumentation and
Industrial Applications
64M Words External Address Range
12 Programmable I/O Pins and Two Timers with Event
Capture Options
Code-Compatible with ADSP-2106x Family
208-Lead MQFP or 196-Ball Mini-BGA Package
3.3 Volt Operation
Super Harvard Architecture Computer (SHARC®)
Four Independent Buses for Dual Data, Instruction,
and I/O Fetch on a Single Cycle
32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit Floating-
Point Arithmetic
Flexible Data Formats and 40-Bit Extended Precision
32-Bit Single-Precision and 40-Bit Extended-Precision IEEE
Floating-Point Data Formats
32-Bit Fixed-Point Data Format, Integer and Fractional,
with Dual 80-Bit Accumulators
544 Kbits On-Chip SRAM Memory and Integrated I/O
Peripheral
I2S Support, for Eight Simultaneous Receive and Trans-
mit Channels
KEY FEATURES
66 MIPS, 198 MFLOPS Peak, 132 MFLOPS Sustained
Performance
User-Configurable 544 Kbits On-Chip SRAM Memory
Two External Port, DMA Channels and Eight Serial
Port, DMA Channels
Parallel Computations
Single-Cycle Multiply and ALU Operations in Parallel with
Dual Memory Read/Writes and Instruction Fetch
Multiply with Add and Subtract for Accelerated FFT But-
terfly Computation
1024-Point Complex FFT Benchmark: 0.274 ms (18,221
Cycles)
DUAL-PORTED SRAM
CORE PROCESSOR
JTAG
7
INSTRUCTION
CACHE
32
؋
48 BIT TWO INDEPENDENT
DUAL-PORTED BLOCKS
TEST &
EMULATION
PROCESSOR PORT
ADDR DATA
ADDR DATA
I/O PORT
DATA ADDR
ADDR
DATA
EXTERNAL
PORT
DAG1
8
؋
4 ؋
32 DAG2
8
؋
4 ؋
24 PROGRAM
SEQUENCER
SDRAM
INTERFACE
IOD
48
IOA
17
PM ADDRESS BUS
DM ADDRESS BUS
24
32
24
32
ADDR BUS
MUX
MULTIPROCESSOR
INTERFACE
PM DATA BUS
48
BUS
CONNECT
(PX)
DATA BUS
MUX
40 DM DATA BUS
HOST PORT
4
DMA
DATA
IOP
REGISTERS
(MEMORY MAPPED)
CONTROLLER
REGISTER
FILE
(2 Rx, 2Tx)
16
؋
40 BIT BARREL
SHIFTER
SPORT 0
MULTIPLIER
ALU
CONTROL,
STATUS, TIMER
&
2
(I S)
(2 Rx, 2Tx)
DATA BUFFERS
SPORT 1
2
(I S)
I/O PROCESSOR
Figure 1. Functional Block Diagram
SHARC is a registered trademark of Analog Devices, Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
ADSP-21065L
544 Kbits Configurable On-Chip SRAM
Dual-Ported for Independent Access by Core Processor
and DMA
Host Processor Interface
Efficient Interface to 8-, 16-, and 32-Bit Microprocessors
Host Can Directly Read/Write ADSP-21065L IOP Registers
Configurable in Combinations of 16-, 32-, 48-Bit Data and
Program Words in Block 0 and Block 1
Multiprocessing
Distributed On-Chip Bus Arbitration for Glueless, Parallel
Bus Connect Between Two ADSP-21065Ls Plus Host
132 Mbytes/s Transfer Rate Over Parallel Bus
DMA Controller
Ten DMA Channels—Two Dedicated to the External Port
and Eight Dedicated to the Serial Ports
Background DMA Transfers at up to 66 MHz, in Parallel
with Full Speed Processor Execution
Performs Transfers Between:
Internal RAM and Host
Internal RAM and Serial Ports
Internal RAM and Master or Slave SHARC
Internal RAM and External Memory or I/O Devices
External Memory and External Devices
Serial Ports
Independent Transmit and Receive Functions
Programmable 3-Bit to 32-Bit Serial Word Width
I2S Support Allowing Eight Transmit and Eight Receive
Channels
Glueless Interface to Industry Standard Codecs
TDM Multichannel Mode with -Law/A-Law Hardware
Companding
Multichannel Signaling Protocol
–2–
REV. B
ADSP-21065L
GENERAL DESCRIPTION
ADSP-21065L
The ADSP-21065L is a powerful member of the SHARC
family of 32-bit processors optimized for cost sensitive appli-
cations. The SHARC—Super Harvard Architecture—offers the
highest levels of performance and memory integration of any
32-bit DSP in the industry—they are also the only DSP in the
industry that offer both fixed and floating-point capabilities,
without compromising precision or performance.
#1
CS
CLOCK
CLKIN
BOOT
EPROM
(OPTIONAL)
ADDR
DATA
RESET
RESET
01
ID
ADDR
DATA
1-0
23-0
HOST
PROCESSOR
(OPTIONAL)
31-0
SPORT0
TX0_A
TX0_B
RX0_A
RX0_B
RD
WR
CS
ADDR
DATA
Fabricated in a high speed, low power CMOS process, 0.35 µm
technology, the ADSP-21065L offers the highest performance
by a 32-bit DSP—66 MIPS (198 MFLOPS). With its on-chip
instruction cache, the processor can execute every instruction in
a single cycle. Table I lists the performance benchmarks for the
ADSP-21065L.
ACK
MS
3-0
BMS
ADDR
DATA
SPORT1
SBTS
SW
CS
TX1_A
TX1_B
RX1_A
RX1_B
HBR
HBG
CS
SDRAM
The ADSP-21065L SHARC combines a floating-point DSP
core with integrated, on-chip system features, including a
544 Kbit SRAM memory, host processor interface, DMA con-
troller, SDRAM controller, and enhanced serial ports.
(OPTIONAL)
REDY
CONTROL
RAS
RAS
CAS
CAS
DQM
WE
DQM
SDWE
CLK
CKE
A10
SDCLK
SDCKE
SDA10
Figure 1 shows a block diagram of the ADSP-21065L, illustrat-
ing the following architectural features:
1-0
Computation Units (ALU, Multiplier, and Shifter) with a
Shared Data Register File
Data Address Generators (DAG1, DAG2)
Program Sequencer with Instruction Cache
Timers with Event Capture Modes
On-Chip, dual-ported SRAM
External Port for Interfacing to Off-Chip Memory and
Peripherals
Host Port and SDRAM Interface
DMA Controller
CPA
BR
2
1
BR
Figure 2. ADSP-21065L Single-Processor System
Independent, Parallel Computation Units
The arithmetic/logic unit (ALU), multiplier, and shifter all
perform single-cycle instructions. The three units are arranged
in parallel, maximizing computational throughput. Single multi-
function instructions execute parallel ALU and multiplier
operations. These computation units support IEEE 32-bit
single-precision floating-point, extended precision 40-bit floating-
point, and 32-bit fixed-point data formats.
Enhanced Serial Ports
JTAG Test Access Port
Table I. Performance Benchmarks
Data Register File
A general-purpose data register file is used for transferring data
between the computation units and the data buses, and for
storing intermediate results. This 10-port, 32-register (16 pri-
mary, 16 secondary) register file, combined with the ADSP-
21000 Harvard architecture, allows unconstrained data flow
between computation units and internal memory.
Benchmark
Timing
Cycles
Cycle Time
1024-Pt. Complex FFT
(Radix 4, with Digit Reverse)
15.00 ns
1
0.274 ns
18221
Matrix Multiply (Pipelined)
[3 × 3] × [3 × 1]
[4 × 4] × [4 × 1]
FIR Filter (per Tap)
IIR Filter (per Biquad)
Divide Y/X
Inverse Square Root (1/√x)
DMA Transfers
135 ns
240 ns
15 ns
60 ns
90 ns
9
16
1
4
6
9
Single-Cycle Fetch of Instruction and Two Operands
The ADSP-21065L features an enhanced Super Harvard Archi-
tecture in which the data memory (DM) bus transfers data and
the program memory (PM) bus transfers both instructions and
data (see Figure 1). With its separate program and data memory
buses, and on-chip instruction cache, the processor can simulta-
neously fetch two operands and an instruction (from the cache),
all in a single cycle.
135 ns
264 Mbytes/sec.
Instruction Cache
ADSP-21000 FAMILY CORE ARCHITECTURE
The ADSP-21065L includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and two
data values. The cache is selective—only the instructions that
fetches conflict with PM bus data accesses are cached. This
allows full-speed execution of core, looped operations such as
digital filter multiply-accumulates and FFT butterfly processing.
The ADSP-21065L is code and function compatible with the
ADSP-21060/ADSP-21061/ADSP-21062. The ADSP-21065L
includes the following architectural features of the SHARC
family core.
Data Address Generators with Hardware Circular Buffers
The ADSP-21065L’s two data address generators (DAGs)
implement circular data buffers in hardware. Circular buffers
allow efficient programming of delay lines and other data
REV. B
–3–
ADSP-21065L
structures required in digital signal processing, and are com-
monly used in digital filters and Fourier transforms. The
ADSP-21065L’s two DAGs contain sufficient registers to allow
the creation of up to 32 circular buffers (16 primary register
sets, 16 secondary). The DAGs automatically handle address
pointer wraparound, reducing overhead, increasing perfor-
mance, and simplifying implementation. Circular buffers can
start and end at any memory location.
Off-Chip Memory and Peripherals Interface
The ADSP-21065L’s external port provides the processor’s
interface to off-chip memory and peripherals. The 64M words,
off-chip address space is included in the ADSP-21065L’s uni-
fied address space. The separate on-chip buses—for program
memory, data memory and I/O—are multiplexed at the external
port to create an external system bus with a single 24-bit ad-
dress bus, four memory selects, and a single 32-bit data bus.
The on-chip Super Harvard Architecture provides three bus
performance, while the off-chip unified address space gives
flexibility to the designer.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the ADSP-
21065L can conditionally execute a multiply, an add, a subtract
and a branch, all in a single instruction.
SDRAM Interface
The SDRAM interface enables the ADSP-21065L to transfer
data to and from synchronous DRAM (SDRAM) at 2x clock
frequency. The synchronous approach coupled with 2x clock
frequency supports data transfer at a high throughput—up to
220 Mbytes/sec.
ADSP-21065L FEATURES
The ADSP-21065L is designed to achieve the highest system
throughput to enable maximum system performance. It can be
clocked by either a crystal or a TTL-compatible clock signal.
The ADSP-21065L uses an input clock with a frequency equal
to half the instruction rate—a 33 MHz input clock yields a
15 ns processor cycle (which is equivalent to 66 MHz). Inter-
faces on the ADSP-21065L operate as shown below. Hereafter
in this document, 1x = input clock frequency, and 2x = processor’s
instruction rate.
The SDRAM interface provides a glueless interface with stan-
dard SDRAMs—16 Mb, 64 Mb, and 128 Mb—and includes
options to support additional buffers between the ADSP-21065L
and SDRAM. The SDRAM interface is extremely flexible and
provides capability for connecting SDRAMs to any one of the
ADSP-21065L’s four external memory banks.
Systems with several SDRAM devices connected in parallel may
require buffering to meet overall system timing requirements.
The ADSP-21065L supports pipelining of the address and
control signals to enable such buffering between itself and mul-
tiple SDRAM devices.
The following clock operation ratings are based on 1x = 33 MHz
(instruction rate/core = 66 MHz):
SDRAM
External SRAM
Serial Ports
Multiprocessing
Host (Asynchronous)
66 MHz
33 MHz
33 MHz
33 MHz
33 MHz
Host Processor Interface
The ADSP-21065L’s host interface provides easy connection to
standard microprocessor buses—8-, 16-, and 32-bit—requiring
little additional hardware. Supporting asynchronous transfers at
speeds up to 1x clock frequency, the host interface is accessed
through the ADSP-21065L’s external port. Two channels of
DMA are available for the host interface; code and data trans-
fers are accomplished with low software overhead.
Augmenting the ADSP-21000 family core, the ADSP-21065L
adds the following architectural features:
Dual-Ported On-Chip Memory
The ADSP-21065L contains 544 Kbits of on-chip SRAM,
organized into two banks: Bank 0 has 288 Kbits, and Bank 1 has
256 Kbits. Bank 0 is configured with 9 columns of 2K × 16 bits,
and Bank 1 is configured with 8 columns of 2K × 16 bits. Each
memory block is dual-ported for single-cycle, independent ac-
cesses by the core processor and I/O processor or DMA control-
ler. The dual-ported memory and separate on-chip buses allow
two data transfers from the core and one from I/O, all in a
single cycle (see Figure 4 for the ADSP-21065L Memory Map).
The host processor requests the ADSP-21065L’s external bus
with the host bus request (HBR), host bus grant (HBG), and
ready (REDY) signals. The host can directly read and write the
IOP registers of the ADSP-21065L and can access the DMA
channel setup and mailbox registers. Vector interrupt support
enables efficient execution of host commands.
DMA Controller
On the ADSP-21065L, the memory can be configured as a
maximum of 16K words of 32-bit data, 34K words for 16-bit
data, 10K words of 48-bit instructions (and 40-bit data) or
combinations of different word sizes up to 544 Kbits. All the
memory can be accessed as 16-bit, 32-bit or 48-bit.
The ADSP-21065L’s on-chip DMA controller allows zero-
overhead, nonintrusive data transfers without processor inter-
vention. The DMA controller operates independently and
invisibly to the processor core, allowing DMA operations to
occur while the core is simultaneously executing its program
instructions.
While each memory block can store combinations of code and
data, accesses are most efficient when one block stores data,
using the DM bus for transfers, and the other block stores in-
structions and data, using the PM bus for transfers. Using the
DM and PM busses in this way, with one dedicated to each
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache. Single-cycle execution is also maintained when one of the
data operands is transferred to or from off-chip, via the ADSP-
21065L’s external port.
DMA transfers can occur between the ADSP-21065L’s internal
memory and either external memory, external peripherals, or a
host processor. DMA transfers can also occur between the
ADSP-21065L’s internal memory and its serial ports. DMA
transfers between external memory and external peripheral
devices are another option. External bus packing to 16-, 32-, or
48-bit internal words is performed during DMA transfers.
Ten channels of DMA are available on the ADSP-21065L—
eight via the serial ports, and two via the processor’s external
port (for either host processor, other ADSP-21065L, memory or
–4–
REV. B
ADSP-21065L
I/O transfers). Programs can be downloaded to the ADSP-
21065L using DMA transfers. Asynchronous off-chip peripher-
als can control two DMA channels using DMA Request/Grant
lines (DMAR1-2, DMAG1-2). Other DMA features include inter-
rupt generation on completion of DMA transfers and DMA
chaining for automatically linked DMA transfers.
DEVELOPMENT TOOLS
The ADSP-21065L is supported with a complete set of software
and hardware development tools, including the EZ-ICE® In-
Circuit Emulator and development software.
The same EZ-ICE hardware that you use for the ADSP-21060/
ADSP-21062 also fully emulates the ADSP-21065L.
Serial Ports
Both the SHARC Development Tools family and the VisualDSP®
integrated project management and debugging environment
support the ADSP-21065L. The VisualDSP project manage-
ment environment enables you to develop and debug an appli-
cation from within a single integrated program.
The ADSP-21065L features two synchronous serial ports that
provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices. The serial ports can operate at
1x clock frequency, providing each with a maximum data rate of
33 Mbit/s. Each serial port has a primary and a secondary set of
transmit and receive channels. Independent transmit and receive
functions provide greater flexibility for serial communications.
Serial port data can be automatically transferred to and from
on-chip memory via DMA. Each of the serial ports supports
three operation modes: DSP serial port mode, I2S mode (an
interface commonly used by audio codecs), and TDM (Time
Division Multiplex) multichannel mode.
The SHARC Development Tools include an easy to use Assem-
bler that is based on an algebraic syntax; an Assembly library/
librarian; a linker; a loader; a cycle-accurate, instruction-level
simulator; a C compiler; and a C run-time library that includes
DSP and mathematical functions.
Debugging both C and Assembly programs with the Visual DSP
debugger, you can:
The serial ports can operate with little-endian or big-endian
transmission formats, with selectable word lengths of 3 bits to
32 bits. They offer selectable synchronization and transmit
modes and optional µ-law or A-law companding. Serial port
clocks and frame syncs can be internally or externally generated.
The serial ports also include keyword and keymask features to
enhance interprocessor communication.
•
•
•
•
•
•
•
View Mixed C and Assembly Code
Insert Break Points
Set Watch Points
Trace Bus Activity
Profile Program Execution
Fill and Dump Memory
Create Custom Debugger Windows
Programmable Timers and General Purpose I/O Ports
The ADSP-21065L has two independent timer blocks, each of
which performs two functions—Pulsewidth Generation and
Pulse Count and Capture.
The Visual IDE enables you to define and manage multiuser
projects. Its dialog boxes and property pages enable you to
configure and manage all of the SHARC Development Tools.
This capability enables you to:
In Pulsewidth Generation mode, the ADSP-21065L can gener-
ate a modulated waveform with an arbitrary pulsewidth within
a maximum period of 71.5 secs.
•
Control how the development tools process inputs and gen-
erate outputs.
Maintain a one-to-one correspondence with the tool’s com-
mand line switches.
•
In Pulse Counter mode, the ADSP-21065L can measure either
the high or low pulsewidth and the period of an input waveform.
The EZ-ICE Emulator uses the IEEE 1149.1 JTAG test access
port of the ADSP-21065L processor to monitor and control the
target board processor during emulation. The EZ-ICE provides
full-speed emulation, allowing inspection and modification of
memory, registers, and processor stacks. Nonintrusive in-circuit
emulation is assured by the use of the processor’s JTAG inter-
face—the emulator does not affect target system loading or
timing.
The ADSP-21065L also contains twelve programmable, general
purpose I/O pins that can function as either input or output. As
output, these pins can signal peripheral devices; as input, these
pins can provide the test for conditional branching.
Program Booting
The internal memory of the ADSP-21065L can be booted at
system power-up from an 8-bit EPROM, a host processor, or
external memory. Selection of the boot source is controlled by
the BMS (Boot Memory Select) and BSEL (EPROM Boot)
pins. Either 8-, 16-, or 32-bit host processors can be used for
booting. For details, see the descriptions of the BMS and BSEL
pins in the Pin Descriptions section of this data sheet.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC processor family. Hard-
ware tools include SHARC PC plug-in cards multiprocessor
SHARC VME boards, and daughter and modules with multiple
SHARCs and additional memory. These modules are based on
the SHARCPAC™ module specification. Third Party software
tools include an Ada compiler, DSP libraries, operating systems,
and block diagram design tools.
Multiprocessing
The ADSP-21065L offers powerful features tailored to multi-
processing DSP systems. The unified address space allows
direct interprocessor accesses of both ADSP-21065L’s IOP
registers. Distributed bus arbitration logic is included on-chip
for simple, glueless connection of systems containing a maxi-
mum of two ADSP-21065Ls and a host processor. Master pro-
cessor changeover incurs only one cycle of overhead. Bus lock
allows indivisible read-modify-write sequences for semaphores.
A vector interrupt is provided for interprocessor commands.
Maximum throughput for interprocessor data transfer is
132 Mbytes/sec over the external port.
Additional Information
For detailed information on the ADSP-21065L instruction set
and architecture, see the ADSP-21065L SHARC User’s Manual,
Third Edition, and the ADSP-21065L SHARC Technical Reference.
EZ-ICE and VisualDSP are registered trademarks of Analog Devices, Inc.
SHARCPAC is a trademark of Analog Devices Inc.
REV. B
–5–
ADSP-21065L
ADSP-21065L
#2
CLKIN
ADDR
23-0
DATA
31-0
RESET
10
ID
1-0
CONTROL
SPORT0
SPORT1
CPA
BR
2
1
BR
ADSP-21065L
#1
CS
ADDR
DATA
CLOCK
CLKIN
BOOT
EPROM
(OPTIONAL)
RESET
RESET
01
ID
1-0
ADDR
23-0
HOST
PROCESSOR
(OPTIONAL)
DATA
31-0
SPORT0
RD
CS
WR
ADDR
DATA
ACK
MS
3-0
BMS
ADDR
DATA
SPORT1
SBTS
SW
CS
HBR
HBG
REDY
CS
SDRAM
(OPTIONAL)
CONTROL
RAS
RAS
CAS
DQM
CAS
DQM
WE
SDWE
SDCLK
1-0
SDCKE
SDA10
CLK
CKE
A10
CPA
BR
BR
2
1
Figure 3. Multiprocessing System
–6–
REV. B
ADSP-21065L
PIN DESCRIPTIONS
ADSP-21065L pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to
CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN
(or to TCK for TRST).
Unused inputs should be tied or pulled to VDD or GND, except for ADDR23-0, DATA31-0, FLAG11-0, SW, and inputs that have
internal pull-up or pull-down resistors (CPA, ACK, DTxX, DRxX, TCLKx, RCLKx, TMS, and TDI)—these pins can be left float-
ing. These pins have a logic-level hold circuit that prevents the input from floating internally.
I = Input
O = Output
S = Synchronous
A = Asynchronous
P = Power Supply
G = Ground
(O/D) = Open Drain
(A/D) = Active Drive
T = Three-state (when SBTS is asserted, or when the ADSP-2106x is a bus slave)
Pin
Type
Function
ADDR23-0
I/O/T
External Bus Address. The ADSP-21065L outputs addresses for external memory and pe-
ripherals on these pins. In a multiprocessor system the bus master outputs addresses for read/
writes of the IOP registers of the other ADSP-21065L. The ADSP-21065L inputs addresses
when a host processor or multiprocessing bus master is reading or writing its IOP registers.
DATA31-0
I/O/T
I/O/T
External Bus Data. The ADSP-21065L inputs and outputs data and instructions on these
pins. The external data bus transfers 32-bit single-precision floating-point data and 32-bit fixed-
point data over bits 31-0. 16-bit short word data is transferred over bits 15-0 of the bus. Pull-up
resistors on unused DATA pins are not necessary.
MS3-0
Memory Select Lines. These lines are asserted as chip selects for the corresponding banks of
external memory. Internal ADDR25-24 are decoded into MS3-0. The MS3-0 lines are decoded
memory address lines that change at the same time as the other address lines. When no external
memory access is occurring the MS3-0 lines are inactive; they are active, however, when a condi-
tional memory access instruction is executed, whether or not the condition is true. Additionally,
an MS3-0 line which is mapped to SDRAM may be asserted even when no SDRAM access is
active. In a multiprocessor system, the MS3-0 lines are output by the bus master.
RD
WR
SW
I/O/T
I/O/T
I/O/T
Memory Read Strobe. This pin is asserted when the ADSP-21065L reads from external memory
devices or from the IOP register of another ADSP-21065L. External devices (including another
ADSP-21065L) must assert RD to read from the ADSP-21065L’s IOP registers. In a multipro-
cessor system, RD is output by the bus master and is input by another ADSP-21065L.
Memory Write Strobe. This pin is asserted when the ADSP-21065L writes to external memory
devices or to the IOP register of another ADSP-21065L. External devices must assert WR to
write to the ADSP-21065L’s IOP registers. In a multiprocessor system, WR is output by the bus
master and is input by the other ADSP-21065L.
Synchronous Write Select. This signal interfaces the ADSP-21065L to synchronous memory
devices (including another ADSP-21065L). The ADSP-21065L asserts SW to provide an early
indication of an impending write cycle, which can be aborted if WR is not later asserted (e.g., in
a conditional write instruction). In a multiprocessor system, SW is output by the bus master and
is input by the other ADSP-21065L to determine if the multiprocessor access is a read or write.
SW is asserted at the same time as the address output.
ACK
I/O/S
Memory Acknowledge. External devices can deassert ACK to add wait states to an external
memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold
off completion of an external memory access. The ADSP-21065L deasserts ACK as an output
to add wait states to a synchronous access of its IOP registers. In a multiprocessor system, a
slave ADSP-21065L deasserts the bus master’s ACK input to add wait state(s) to an access of
its IOP registers. The bus master has a keeper latch on its ACK pin that maintains the input at
the level to which it was last driven.
SBTS
I/S
Suspend Bus Three-State. External devices can assert SBTS to place the external bus ad-
dress, data, selects, and strobes—but not SDRAM control pins—in a high impedance state for
the following cycle. If the ADSP-21065L attempts to access external memory while SBTS is
asserted, the processor will halt and the memory access will not finish until SBTS is deasserted.
SBTS should only be used to recover from host processor/ADSP-21065L deadlock.
IRQ2-0
I/A
Interrupt Request Lines. May be either edge-triggered or level-sensitive.
FLAG11-0
I/O/A
Flag Pins. Each is configured via control bits as either an input or an output. As an input, it can
be tested as a condition. As an output, it can be used to signal external peripherals.
REV. B
–7–
ADSP-21065L
Pin
Type
Function
HBR
I/A
Host Bus Request. Must be asserted by a host processor to request control of the ADSP-
21065L’s external bus. When HBR is asserted in a multiprocessing system, the ADSP-21065L
that is bus master will relinquish the bus and assert HBG. To relinquish the bus, the ADSP-
21065L places the address, data, select, and strobe lines in a high impedance state. It does,
however, continue to drive the SDRAM control pins. HBR has priority over all ADSP-21065L
bus requests (BR2-1) in a multiprocessor system.
HBG
I/O
Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor may
take control of the external bus. HBG is asserted by the ADSP-21065L until HBR is released.
In a multiprocessor system, HBG is output by the ADSP-21065L bus master.
CS
I/A
O
Chip Select. Asserted by host processor to select the ADSP-21065L.
REDY (O/D)
Host Bus Acknowledge. The ADSP-21065L deasserts REDY to add wait states to an asyn-
chronous access of its internal memory or IOP registers by a host. Open drain output (O/D) by
default; can be programmed in ADREDY bit of SYSCON register to be active drive (A/D).
REDY will only be output if the CS and HBR inputs are asserted.
DMAR1
DMAR2
DMAG1
DMAG2
BR2-1
I/A
DMA Request 1 (DMA Channel 9).
DMA Request 2 (DMA Channel 8).
DMA Grant 1 (DMA Channel 9).
DMA Grant 2 (DMA Channel 8).
I/A
O/T
O/T
I/O/S
Multiprocessing Bus Requests. Used by multiprocessing ADSP-21065Ls to arbitrate for bus
mastership. An ADSP-21065L drives its own BRx line (corresponding to the value of its ID2-0
inputs) only and monitors all others. In a uniprocessor system, tie both BRx pins to VDD.
ID1-0
I
Multiprocessing ID. Determines which multiprocessor bus request (BR1–BR2) is used by
ADSP-21065L. ID = 01 corresponds to BR1, ID = 10 corresponds to BR2. ID = 00 in single-
processor systems. These lines are a system configuration selection which should be hard-wired
or changed only at reset.
CPA (O/D)
I/O
Core Priority Access. Asserting its CPA pin allows the core processor of an ADSP-21065L
bus slave to interrupt background DMA transfers and gain access to the external bus. CPA is an
open drain output that is connected to both ADSP-21065Ls in the system. The CPA pin has an
internal 5 kΩ pull-up resistor. If core access priority is not required in a system, leave the CPA
pin unconnected.
DTxX
DRxX
O
I
Data Transmit (Serial Ports 0, 1; Channels A, B). Each DTxX pin has a 50 kΩ internal pull-
up resistor.
Data Receive (Serial Ports 0, 1; Channels A, B). Each DRxX pin has a 50 kΩ internal pull-up
resistor.
TCLKx
RCLKx
TFSx
I/O
I/O
I/O
I/O
I
Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 kΩ internal pull-up resistor.
Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 kΩ internal pull-up resistor.
Transmit Frame Sync (Serial Ports 0, 1).
RFSx
Receive Frame Sync (Serial Ports 0, 1).
BSEL
EPROM Boot Select. When BSEL is high, the ADSP-21065L is configured for booting from
an 8-bit EPROM. When BSEL is low, the BSEL and BMS inputs determine booting mode. See
BMS for details. This signal is a system configuration selection which should be hard-wired.
–8–
REV. B
ADSP-21065L
Pin
Type
Function
BMS
I/O/T*
Boot Memory Select. Output: used as chip select for boot EPROM devices (when BSEL = 1).
In a multiprocessor system, BMS is output by the bus master. Input: When low, indicates that
no booting will occur and that the ADSP-21065L will begin executing instructions from exter-
nal memory. See following table. This input is a system configuration selection which should be
hard-wired.
*Three-statable only in EPROM boot mode (when BMS is an output).
BSEL
BMS
Booting Mode
1
0
0
Output
1 (Input)
0 (Input)
EPROM (connect BMS to EPROM chip select).
Host processor (HBW [SYSCON] bit selects host bus width).
No booting. Processor executes from external memory.
CLKIN
I
Clock In. Used in conjunction with XTAL, configures the ADSP-21065L to use either its
internal clock generator or an external clock source. The external crystal should be rated at 1x
frequency.
Connecting the necessary components to CLKIN and XTAL enables the internal clock genera-
tor. The ADSP-21065L’s internal clock generator multiplies the 1x clock to generate 2x clock
for its core and SDRAM. It drives 2x clock out on the SDCLKx pins for the SDRAM interface
to use. See also SDCLKx.
Connecting the 1x external clock to CLKIN while leaving XTAL unconnected configures the
ADSP-21065L to use the external clock source. The instruction cycle rate is equal to 2x CLKIN.
CLKIN may not be halted, changed, or operated below the specified frequency.
RESET
I/A
Processor Reset. Resets the ADSP-21065L to a known state and begins execution at the
program memory location specified by the hardware reset vector address. This input must be
asserted at power-up.
TCK
TMS
I
Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan.
I/S
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kΩ internal
pull-up resistor.
TDI
I/S
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 kΩ
internal pull-up resistor.
TDO
O
Test Data Output (JTAG). Serial scan output of the boundary scan path.
TRST
I/A
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after
power-up or held low for proper operation of the ADSP-21065L. TRST has a 20 kΩ internal
pull-up resistor.
EMU (O/D)
O
O
Emulation Status. Must be connected to the ADSP-21065L EZ-ICE target board connector
only.
BMSTR
Bus Master Output. In a multiprocessor system, indicates whether the ADSP-21065L is cur-
rent bus master of the shared external bus. The ADSP-21065L drives BMSTR high only while
it is the bus master. In a single-processor system (ID = 00), the processor drives this pin high.
CAS
I/O/T
SDRAM Column Access Strobe. Provides the column address. In conjunction with RAS,
MSx, SDWE, SDCLKx, and sometimes SDA10, defines the operation for the SDRAM to per-
form.
RAS
I/O/T
I/O/T
O/T
SDRAM Row Access Strobe. Provides the row address. In conjunction with CAS, MSx,
SDWE, SDCLKx, and sometimes SDA10, defines the operation for the SDRAM to perform.
SDWE
DQM
SDRAM Write Enable. In conjunction with CAS, RAS, MSx, SDCLKx, and sometimes
SDA10, defines the operation for the SDRAM to perform.
SDRAM Data Mask. In write mode, DQM has a latency of zero and is used to block write
operations.
SDCLK1-0
I/O/S/T
SDRAM 2x Clock Output. In systems with multiple SDRAM devices connected in parallel,
supports the corresponding increased clock load requirements, eliminating need of off-chip
clock buffers. Either SDCLK1 or both SDCLKx pins can be three-stated.
SDCKE
I/O/T
SDRAM Clock Enable. Enables and disables the CLK signal. For details, see the data sheet
supplied with your SDRAM device.
REV. B
–9–
ADSP-21065L
Pin
Type
Function
SDA10
O/T
O
SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with a host access.
XTAL
Crystal Oscillator Terminal. Used in conjunction with CLKIN to enable the ADSP-21065L’s
internal clock generator or to disable it to use an external clock source. See CLKIN.
PWM_EVENT1-0
I/O/A
PWM Output/Event Capture. In PWMOUT mode, is an output pin and functions as a timer
counter. In WIDTH_CNT mode, is an input pin and functions as a pulse counter/event capture.
VDD
GND
NC
P
Power Supply; nominally +3.3 V dc. (33 pins)
G
Power Supply Return. (37 pins)
Do Not Connect. Reserved pins that must be left open and unconnected. (7)
CLOCK SIGNALS
TARGET BOARD CONNECTOR FOR EZ-ICE PROBE
The ADSP-21065L can use an external clock or a crystal. See
CLKIN pin description. You can configure the ADSP-21065L
to use its internal clock generator by connecting the necessary
components to CLKIN and XTAL. You can use either a crystal
operating in the fundamental mode or a crystal operating at an
overtone. Figure 4 shows the component connections used for a
crystal operating in fundamental mode, and Figure 5 shows
the component connections used for a crystal operating at an
overtone.
The ADSP-2106x EZ-ICE emulator uses the IEEE 1149.1
JTAG test access port of the ADSP-2106x to monitor and con-
trol the target board processor during emulation. The EZ-ICE
probe requires the ADSP-2106x’s CLKIN, TMS, TCK, TRST,
TDI, TDO, EMU and GND signals be made accessible on the
target system via a 14-pin connector (a 2 row x 7 pin strip header)
such as that shown in Figure 6. The EZ-ICE probe plugs di-
rectly onto this connector for chip-on-board emulation. You
must add this connector to your target board design if you,
intend to use the ADSP-2106x EZ-ICE.
CLKIN
XTAL
The total trace length between the EZ-ICE connector and the
furthest device sharing the EZ-ICE JTAG pins should be lim-
ited to 15 inches maximum for guaranteed operation. This
restriction on length must include EZ-ICE JTAG signals, which
are routed to one or more 2106x devices or to a combination of
2106xs and other JTAG devices on the chain.
X1
C2
C1
SUGGESTED COMPONENTS FOR 30 MHz OPERATION:
ECLIPTEK EC2SM-33-30.000M (SURFACE MOUNT PACKAGE)
ECLIPTEK EC-33-30.000M (THRU-HOLE PACKAGE)
C1 = 33pF
The 14-pin, 2-row pin strip header is keyed at the Pin 3 loca-
tion—you must remove Pin 3 from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spac-
ing should be 0.1 × 0.1 inches. Pin strip headers are available
from vendors such as 3M, McKenzie and Samtec.
C2 = 27pF
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS.
Figure 4. 30 MHz Operation (Fundamental Mode Crystal)
1
3
5
2
4
6
CLKIN
XTAL
R
GND
EMU
S
X1
KEY (NO PIN)
CLKIN (OPTIONAL)
C3
C1
C2
L1
BTMS
BTCK
TMS
TCK
7
9
8
SUGGESTED COMPONENTS FOR 30MHz OPERATION:
ECLIPTEK EC2SM-T-30.000M (SURFACE MOUNT PACKAGE)
10
12
ECLIPTEK ECT-30.000M (THRU-HOLE PACKAGE)
C1 = 18pF
C2 = 27pF
C3 = 75pF
BTRST
TRST
11
L
= 3300nH
= SEE NOTE.
1
S
R
BTDI
TDI
NOTE: C1, C2, C3, R AND L ARE SPECIFIC TO CRYSTAL SPECIFIED
S
1
FOR X1. CONTACT MANUFACTURER FOR DETAILS.
13
14
GND
TDO
Figure 5. 30 MHz Operation (3rd Overtone Crystal)
TOP VIEW
Figure 6. Target Board Connector for ADSP-2106x EZ-ICE
(JTAG Header)
–10–
REV. B
ADSP-21065L
The BTMS, BTCK, BTRST and BTDI signals are provided so
that the test access port can also be used for board-level testing.
When the connector is not being used for emulation, place
jumpers between the Bxxx pins and the xxx pins. If you are not
going to use the test access port for board testing, tie BTRST
to GND and tie or pull-up BTCK to VDD. The TRST pin must
be asserted after power-up (through BTRST on the connector)
or held low for proper operation of the ADSP-2106x. None of
the Bxxx pins (Pins 5, 7, 9, 11) are connected on the EZ-ICE
probe.
Connecting CLKIN to Pin 4 of the EZ-ICE header is optional.
The emulator only uses CLKIN when directed to perform op-
erations such as starting, stopping, and single-stepping two
ADSP-21065Ls in a synchronous manner. If you do not need
these operations to occur synchronously on the two processors,
simply tie Pin 4 of the EZ-ICE header to ground.
For systems which use the internal clock generator and an exter-
nal discrete crystal, do not directly connect the CLKIN pin to
the JTAG probe. This will load the oscillator circuit and possi-
bly cause it to fail to oscillate. Instead the JTAG probe’s
CLKIN can be driven by the XTAL pin through a high imped-
ance buffer.
The JTAG signals are terminated on the EZ-ICE probe as follows:
Signal
Termination
If synchronous multiprocessor operations are needed and CLKIN
is connected, clock skew between multiple ADSP-2106x proces-
sors and the CLKIN pin on the EZ-ICE header must be mini-
mal. If the skew is too large, synchronous operations may be off
by one cycle between processors. For synchronous multiproces-
sor operation TCK, TMS, CLKIN and EMU should be treated
as critical signals in terms of skew, and should be laid out as
short as possible on your board.
TMS
TCK
Driven through 22 Ω resistor (16 mA driver)
Driven at 10 MHz through 22 Ω resistor
(16 mA driver)
Driven through 22 Ω resistor (16 mA driver)
(pulled up by on-chip 20 kΩ resistor)
Driven by 22 Ω resistor (16 mA driver)
One TTL load, Split Termination (160/220)
One TTL load, Split Termination (160/220).
(Caution: Do not connect to CLKIN if
internal XTAL oscillator is used.)
TRST*
TDI
TDO
CLKIN
If synchronous multiprocessor operations are not needed (i.e.,
CLKIN is not connected), just use appropriate parallel termina-
tion on TCK and TMS. TDI, TDO, EMU and TRST are not
critical signals in terms of skew.
EMU
Active Low 4.7 kΩ pull-up resistor, one TTL
load (open-drain output from ADSP-2106xs)
For Complete information on the SHARC EZ-ICE, see the
ADSP-21000 Family JTAG EZ-ICE User’s Guide and Reference.
*TRST is driven low until the EZ-ICE probe is turned on by the emulator at
software start-up. After software start-up, TRST is driven high.
REV. B
–11–
ADSP-21065L–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Test
C Grade
Max
K Grade
Parameter
Conditions
Min
Min
Max
Units
VDD
TCASE
Supply Voltage
Case Operating Temperature
3.13
–40
3.60
+100
3.13
0
3.60
+85
V
°C
VIH
VIL1
VIL2
High Level Input Voltage
Low Level Input Voltage1
Low Level Input Voltage2
@ VDD = max
@ VDD = min
@ VDD = min
2.0
–0.5
–0.5
VDD + 0.5
0.8
0.7
2.0
–0.5
–0.5
VDD + 0.5
0.8
0.7
V
V
V
NOTE
See Environmental Conditions for information on thermal specifications.
ELECTRICAL CHARACTERISTICS
C & K Grades
Parameter
Test Conditions
Min
Max
Units
VOH
VOL
IIH
IIL
IILP
IOZH
IOZL
IOZLS
IOZLA
High Level Output Voltage3
@ VDD = min, IOH = –2.0 mA4
@ VDD = min, IOL = 4.0 mA4
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 1.5 V
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
2.4
V
V
Low Level Output Voltage3
High Level Input Current5
Low Level Input Current5
0.4
10
10
150
10
8
150
350
4
µA
µA
µA
µA
µA
µA
µA
mA
mA
pF
Low Level Input Current6
Three-State Leakage Current7, 8, 9, 10
Three-State Leakage Current7
Three-State Leakage Current8
Three-State Leakage Current11
IOZLAR Three-State Leakage Current10
IOZLC
CIN
Three-State Leakage Current9
Input Capacitance12, 13
1.5
8
fIN = 1 MHz, TCASE = 25°C, VIN = 2.5 V
NOTES
1 Applies to input and bidirectional pins: DATA31-0, ADDR23-0, BSEL, RD, WR, SW, ACK, SBTS, IRQ2-0, FLAG11-0, HBG, CS, DMAR1, DMAR2, BR2-1, ID2-0
RPBA, CPA, TFS0, TFS1, RFS0, RFS1, BMS, TMS, TDI, TCK, HBR, DR0A, DR1A, DR0B, DR1B, TCLK0, TCLK1, RCLK0, RCLK1, RESET, TRST,
PWM_EVENT0, PWM_EVENT1, RAS, CAS, SDWE, SDCKE.
,
2 Applies to input pin CLKIN.
3 Applies to output and bidirectional pins: DATA31-0, ADDR23-0, MS3-0, RD, WR, SW, ACK, FLAG11-0, HBG, REDY, DMAG1, DMAG2, BR2-1, CPA, TCLK0,
TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, DT0A, DT1A, DT0B, DT1B, XTAL, BMS, TDO, EMU, BMSTR, PWM_EVENT0, PWM_EVENT1,
RAS, CAS, DQM, SDWE, SDCLK0, SDCLK1, SDCKE, SDA10.
4 See Output Drive Currents for typical drive current capabilities.
5 Applies to input pins: ACK, SBTS, IRQ2-0, HBR, CS, DMAR1, DMAR2, ID1-0, BSEL, CLKIN, RESET, TCK (Note that ACK is pulled up internally with 2 kΩ
during reset in a multiprocessor system, when ID1-0 = 01 and another ADSP-21065L is not requesting bus mastership.)
6Applies to input pins with internal pull-ups: DR0A, DR1A, DR0B, DR1B, TRST, TMS, TDI.
7Applies to three-statable pins: DATA31-0, ADDR23-0, MS3-0, RD, WR, SW, ACK, FLAG11-0, REDY, HBG, DMAG1, DMAG2, BMS, TDO, RAS, CAS, DQM,
SDWE, SDCLK0, SDCLK1, SDCKE, SDA10 and EMU (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID1-0
=
01 and another ADSP-21065L is not requesting bus mastership).
8 Applies to three-statable pins with internal pull-ups: DT0A, DT1A, DT0B, DT1B, TCLK0, TCLK1, RCLK0, RCLK1.
9Applies to CPA pin.
10Applies to ACK pin when pulled up.
11 Applies to ACK pin when keeper latch enabled.
12 Guaranteed but not tested.
13 Applies to all signal pins.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Output Voltage Swing . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Junction Temperature Under Bias . . . . . . . . . . . . . . . . . 130°C
Lead Temperature (5 seconds) . . . . . . . . . . . . . . . . . . +280°C
*Stresses greater than those listed above may cause permanent damage to the device.
These are stress ratings only; functional operation of the device at these or any other
conditions greater than those indicated in the operational sections of this specifica-
tion is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-21065L features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–12–
REV. B
ADSP-21065L
POWER DISSIPATION ADSP-21065L
These specifications apply to the internal power portion of VDD only. See the Power Dissipation section of this data sheet for calcula-
tion of external supply current and total supply current. For a complete discussion of the code used to measure power dissipation, see
the technical note SHARC Power Dissipation Measurements.
Specifications are based on the following operating scenarios:
Table II. Internal Current Measurements
Peak Activity
(IDDINPEAK
High Activity
(IDDINHIGH
Operation
)
)
Low Activity (IDDINLOW)
Instruction Type
Instruction Fetch
Core Memory Access
Internal Memory DMA
Multifunction
Cache
2 per Cycle (DM and PM)
Multifunction
Single Function
Internal Memory
None
Internal Memory
1 per Cycle (DM)
1 per 2 Cycles
1 per Cycle
1 per 2 Cycles
To estimate power consumption for a specific application, use the following equation where % is the amount of time your program
spends in that state:
%PEAK × IDDINPEAK + %HIGH × IDDINHIGH + %LOW × IDDINLOW + %IDLE16 × IDDIDLE16 = POWER CONSUMPTION
Table III. Internal Current Measurement Scenarios
Parameter
Test Conditions
Max
Units
IDDINPEAK
Supply Current (Internal)1
Supply Current (Internal)2
Supply Current (Internal)3
Supply Current (IDLE)4
Supply Current (IDLE16)5
tCK = 33 ns, VDD = max
470
510
275
300
240
260
150
155
50
mA
mA
mA
mA
mA
mA
mA
mA
mA
t
CK = 30 ns, VDD = max
IDDINHIGH
IDDINLOW
IDDIDLE
tCK = 33 ns, VDD = max
tCK = 30 ns, VDD = max
tCK = 33 ns, VDD = max
t
CK = 30 ns, VDD = max
tCK = 33 ns, VDD = max
CK = 30 ns, VDD = max
VDD = max
t
IDDIDLE16
NOTES
1The test program used to measure IDDINPEAK represents worst case processor operation and is not sustainable under normal application conditions. Actual internal
power measurements made using typical applications are less than specified.
2IDDINHIGH is a composite average based on a range of high activity code.
3IDDINLOW is a composite average based on a range of low activity code.
4IDLE denotes ADSP-21065L state during execution of IDLE instruction.
5IDLE16 denotes ADSP-21065L state during execution of IDLE16 instruction.
TIMING SPECIFICATIONS
General Notes
Two speed grades of the ADSP-21065L are offered, 60 MHz and 66 MHz instruction rates. The specifications shown are based on a
CLKIN frequency of 30 MHz (tCK = 33.3 ns). The DT derating allows specifications at other CLKIN frequencies (within the min–
max range of the tCK specification; see Clock Input below). DT is the difference between the actual CLKIN period and a CLKIN
period of 33.3 ns:
DT = (tCK – 33.3)/32
Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addi-
tion or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical varia-
tions and worst cases. Consequently, you cannot meaningfully add parameters to derive longer times.
See Figure 27 in Equivalent Device Loading for AC Measurements (Includes All Fixtures) for voltage reference levels.
REV. B
–13–
ADSP-21065L
Switching Characteristics specify how the processor changes its signals. You have no control over this timing—circuitry external to the
processor must be designed for compatibility with these signal characteristics. Switching characteristics tell you what the processor
will do in a given circumstance. You can also use switching characteristics to ensure that any timing requirement of a device con-
nected to the processor (such as memory) is satisfied.
Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read opera-
tion. Timing requirements guarantee that the processor operates correctly with other devices.
(O/D) = Open Drain
(A/D) = Active Drive
66 MHz
60 MHz
Parameter
Min
Max
Min
Max
Units
Clock Input
Timing Requirements:
tCK
CLKIN Period
CLKIN Width Low
30.00
7.0
5.0
100
3.0
33.33
7.0
5.0
100
3.0
ns
ns
ns
ns
tCKL
tCKH
tCKRF
CLKIN Width High
CLKIN Rise/Fall (0.4 V–2.0 V)
tCK
CLKIN
tCKH
tCKL
Figure 7. Clock Input
Parameter
Reset
Min
Max
Units
Timing Requirements:
tWRST
RESET Pulsewidth Low1
tSRST
RESET Setup Before CLKIN High2
2 tCK
23.5 + 24 DT tCK
ns
ns
NOTES
1Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 3000 CLKIN cycles while RESET is
low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator).
2Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required
for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic synchronizes itself automatically after
reset.
CLKIN
tSRST
tWRST
RESET
Figure 8. Reset
Parameter
Min
Max
Units
Interrupts
Timing Requirements:
tSIR
tHIR
tIPW
IRQ2-0 Setup Before CLKIN High or Low1
11.0 + 12 DT
2.0 + tCK/2
ns
ns
ns
IRQ2-0 Hold Before CLKIN High or Low1
IRQ2-0 Pulsewidth2
0.0 + 12 DT
NOTES
1Only required for IRQx recognition in the following cycle.
2Applies only if tSIR and tHIR requirements are not met.
–14–
REV. B
ADSP-21065L
CLKIN
tSIR
tHIR
IRQ
2-0
tIPW
Figure 9. Interrupts
Parameter
Min
Max
Units
Timer
Timing Requirements:
tSTI
Timer Setup Before SDCLK High
Timer Hold After SDCLK High
0.0
6.0
ns
ns
tHTI
Switching Characteristics:
tDTEX Timer Delay After SDCLK High
tHTEX Timer Hold After SDCLK High
1.0
ns
ns
–5.0
Parameter
Flags
Min
Max
Units
Timing Requirements:
tSFI
tHFI
FLAG11-0IN Setup Before SDCLK High1
FLAG11-0IN Hold After SDCLK High1
–2.0
6.0
ns
ns
Switching Characteristics:
tDFO
FLAG11-0OUT Delay After SDCLK High
1.0
ns
ns
ns
ns
tHFO
tDFOE
tDFOD
FLAG11-0OUT Hold After SDCLK High
SDCLK High to FLAG11-0OUT Enable
SDCLK High to FLAG11-0OUT Disable
–4.0
–4.0
–1.75
NOTE
1Flag inputs meeting these setup and hold times will affect conditional instructions in the following instruction cycle.
SDCLK
tDFOE
tDFO
tDFO
tDFOD
tHFO
FLAG
OUT
11–0
FLAG OUTPUT
SDCLK
tHFI
tSFI
FLAG
IN
11–0
Figure 10. Flags
REV. B
–15–
ADSP-21065L
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN.
These specifications apply when the ADSP-21065L is the bus master when accessing external memory space. These switching char-
acteristics also apply for bus master synchronous read/write timing (see Synchronous Read/Write—Bus Master below). If these tim-
ing requirements are met, the synchronous read/write timing can be ignored (and vice versa). An exception to this is the ACK pin
timing requirements as described in the note below.
Parameter
Min
Max
Units
Timing Requirements:
tDAD
tDRLD
tHDA
Address, Selects Delay to Data Valid1, 2
28.0 + 32 DT + W
24.0 + 26 DT + W
ns
ns
ns
ns
ns
ns
RD Low to Data Valid1
Data Hold from Address Selects3
Data Hold from RD High3
0.0
0.0
tHDRH
tDAAK
tDSAK
ACK Delay from Address, Selects2, 3
ACK Delay from RD Low3
24.0 + 30 DT + W
19.5 + 24 DT + W
Switching Characteristics:
tDRHA
tDARL
tRW
Address, Selects Hold After RD High
–1.0 + H
3.0 + 6 DT
25.0 + 26 DT + W
4.5 + 6 DT + HI
11.0 +12 DT + HI
ns
ns
ns
ns
ns
Address, Selects to RD Low2
RD Pulsewidth
tRWR
tRDGL
RD High to WR, RD Low
RD High to DMAGx Low
W = (number of wait states specified in WAIT register) × tCK
.
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = tCK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
NOTES
1Data Delay/Setup: User must meet tDAD or to tDRLD or synchronous specification tSSDATI
.
2The falling edge of MSx, SW, BMS, are referenced.
3ACK is not sampled on external memory accesses that use the Internal wait state mode. For the first CLKIN cycle of a new external memory access, ACK must be
valid by tDAAK or tDSAK or synchronous specification tSACKC for wait state modes External, Either, or Both (Both, if the internal wait state is zero). For the second and
subsequent cycles of a wait stated external memory access, synchronous specifications tSACKC and tHACKC must be met for wait state modes External, Either, or Both
(Both, after internal wait states have completed).
ADDRESS
MSx , SW
BMS
tDRHA
tRW
tDARL
RD
tHDA
tHDRH
tDRLD
tDAD
DATA
tDSAK
tRWR
tDAAK
ACK
WR
DMAG
tRDGL
Figure 11. Memory Read—Bus Master
–16–
REV. B
ADSP-21065L
Memory Write—Bus Master
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN.
These specifications apply when the ADSP-21065L is the bus master when accessing external memory space. These switching char-
acteristics also apply for bus master synchronous read/write timing (see Synchronous Read/Write—Bus Master below). If these tim-
ing requirements are met, the synchronous read/write timing can be ignored (and vice versa). An exception to this is the ACK pin
timing requirements as described in the note below.
Parameter
Min
Max
Units
Timing Requirements:
tDAAK
tDSAK
ACK Delay from Address1, 2
24.0 + 30 DT + W
19.5 + 24 DT + W
ns
ns
ACK Delay from WR Low1
Switching Characteristics:
tDAWH
tDAWL
tWW
Address, Selects to WR Deasserted2
29.0 + 31 DT + W
3.5 + 6 DT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address, Selects to WR Low2
WR Pulsewidth
24.5 + 25 DT + W
15.5 + 19 DT + W
0.0 + 1 DT + H
1.0 + 1 DT + H
4.5 + 7 DT + H
11.0 + 13 DT + H
3.5 + 6 DT + I
4.5 + 6 DT
tDDWH
tDWHA
tDATRWH
tWWR
Data Setup Before WR High
Address Hold After WR Deasserted
Data Disable After WR Deasserted3
WR High to WR, RD Low
WR High to DMAGx Low
Data Disable Before WR or RD Low
WR Low to Data Enabled
4.0 + 1 DT + H
tWRDGL
tDDWR
tWDE
W = (number of wait states specified in WAIT register) × tCK
.
H = tCK (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
I = tCK (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
NOTES
1ACK is not sampled on external memory accesses that use the Internal wait state mode. For the first CLKIN cycle of a new external memory access, ACK must be
valid by tDAAK or tDSAK or synchronous specification tSACKC for wait state modes External, Either, or Both (Both, if the internal wait state is zero). For the second and
subsequent cycles of a wait stated external memory access, synchronous specifications tSACKC and tHACKC must be met for wait state modes External, Either, or Both
(Both, after internal wait states have completed).
2The falling edge of MSx, SW, and BMS is referenced.
3See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
ADDRESS
MSx , SW
BMS
tDWHA
tDAWH
tWW
tDAWL
WR
tWWR
tDDWR
tDDWH
tWDE
tDATRWH
DATA
tDSAK
tDAAK
ACK
RD
DMAG
tWRDGL
Figure 12. Memory Write—Bus Master
REV. B
–17–
ADSP-21065L
Synchronous Read/Write—Bus Master
Use these specifications for interfacing to external memory systems that require CLKIN-relative timing or for accessing a slave
ADSP-21065L (in multiprocessor memory space). These synchronous switching characteristics are also valid during asynchronous
memory reads and writes (see Memory Read—Bus Master and Memory Write—Bus Master).
When accessing a slave ADSP-21065L, these switching characteristics must meet the slave’s timing requirements for synchronous
read/writes (see Synchronous Read/Write—Bus Slave). The slave ADSP-21065L must also meet these (bus master) timing require-
ments for data and acknowledge setup and hold times.
Parameter
Min
Max
Units
Timing Requirements:
tSSDATI
tHSDATI
tDAAK
tSACKC
tHACK
Data Setup Before CLKIN
0.25 + 2 DT
4.0 – 2 DT
ns
ns
ns
ns
ns
Data Hold After CLKIN
ACK Delay After Address, MSx, SW, BMS1, 2
ACK Setup Before CLKIN1
24.0 + 30 DT + W
2.75 + 4 DT
2.0 – 4 DT
ACK Hold After CLKIN
Switching Characteristics:
tDADRO
tHADRO
tDRDO
tDWRO
tDRWL
tDDATO
tDATTR
tDBM
Address, MSx, BMS, SW Delay After CLKIN1
7.0 – 2 DT
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address, MSx, BMS, SW Hold After CLKIN
RD High Delay After CLKIN
WR High Delay After CLKIN
RD/WR Low Delay After CLKIN
Data Delay After CLKIN
0.5 – 2 DT
0.5 – 2 DT
0.0 – 3 DT
7.5 + 4 DT
6.0 – 2 DT
6.0 – 3 DT
11.75 + 4 DT
22.0 + 10 DT
7.0 – 2 DT
3.0
Data Disable After CLKIN3
1.0 – 2 DT
–4.0
BMSTR Delay After CLKIN
BMSTR Hold After CLKIN
tHBM
W = (number of wait states specified in WAIT register) × tCK
.
NOTES
1Data Hold: User must meet tHDA or tHDRH or synchronous specification tHDATI. See system hold time calculation under test conditions for the calculation of hold
times given capacitive and dc loads.
2ACK is not sampled on external memory accesses that use the Internal wait state mode. For the first CLKIN cycle of a new external memory access, ACK must be
valid by tDAAK or tDSAK or synchronous specification tSACKC for wait state modes External, Either, or Both (Both, if the internal wait state is zero). For the second and
subsequent cycles of a wait stated external memory access, synchronous specifications tSACKC and tHACKC must be met for wait state modes External, Either, or Both
(Both, after internal wait states have completed).
3See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
–18–
REV. B
ADSP-21065L
CLKIN
tHADRO
tDAAK
tDADRO
ADDRESS
SW
tHACKC
tSACKC
ACK
(IN)
READ CYCLE
tDRWL
tDRDO
RD
tHSDATI
tSSDATI
DATA
(IN)
WRITE CYCLE
tDWRO
tDRWL
WR
tDATTR
tDDATO
DATA
(OUT)
Figure 13. Synchronous Read/Write—Bus Master
REV. B
–19–
ADSP-21065L
Synchronous Read/Write—Bus Slave
Use these specifications for ADSP-21065L bus master accesses of a slave’s IOP registers or internal memory (in multiprocessor
memory space). The bus master must meet these (bus slave) timing requirements.
Parameter
Min
Max
Units
Timing Requirements:
tSADRI
Address, SW Setup Before CLKIN
24.5 + 25 DT
ns
ns
ns
ns
ns
ns
ns
tHADRI
tSRWLI
tHRWLI
tRWHPI
tSDATWH
tHDATWH
Address, SW Hold Before CLKIN
RD/WR Low Setup Before CLKIN1
RD/WR Low Hold After CLKIN
RD/WR Pulse High
Data Setup Before WR High
Data Hold After WR High
4.0 + 8 DT
7.5 + 7 DT
21.0 + 21 DT
–2.50 – 5 DT
2.5
4.5
0.0
Switching Characteristics:
tSDDATO
tDATTR
tDACK
Data Delay After CLKIN
31.75 + 21 DT
7.0 – 2 DT
29.5 + 20 DT
6.0 – 2 DT
ns
ns
ns
ns
Data Disable After CLKIN2
ACK Delay After CLKIN
ACK Disable After CLKIN2
1.0 – 2 DT
1.0 – 2 DT
tACKTR
NOTES
1tSRWLI is specified when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, tSRWLI (min) = 17.5 + 18 DT.
2See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
For two ADSP-21065Ls to communicate synchronously as master and slave, certain master and slave specification combinations
must be satisfied. Do not compare specification values directly to calculate master/slave clock skew margins for those specifications
listed below. The following table shows the appropriate clock skew margin.
Table IV. Bus Master to Slave Skew Margins
Master Specification
Slave Specification
Skew Margin
tSSDATI
tSDDATO
tCK = 33.3 ns + 2.25 ns
t
CK = 30.0 ns + 1.50 ns
tSACKC
tDACK
tCK = 33.3 ns + 3.00 ns
tCK = 30.0 ns + 2.25 ns
tCK = 33.3 ns N/A
tDADRO
tSADRI
t
CK = 30.0 ns + 2.75 ns
tCK = 33.3 ns + 1.50 ns
CK = 30.0 ns + 1.25 ns
tDRWL (Max)
tSRWLI
t
t
DRDO (Max)
tHRWLI (Max)
tHRWLI (Max)
tCK = 33.3 ns N/A
tCK = 30.0 ns 3.00 ns
tCK = 33.3 ns N/A
tCK = 30.0 ns 3.75 ns
tDWRO (Max)
–20–
REV. B
ADSP-21065L
CLKIN
tSADRI
tHADRI
ADDRESS
SW
tDACK
tACKTR
ACK
READ ACCESS
tSRWLI
tHRWLI
tRWHPI
RD
tSDDATO
tDATTR
DATA
(OUT)
WRITE ACCESS
tRWHPI
tSRWLI
tHRWLI
WR
tHDATWH
tSDATWH
DATA
(IN)
Figure 14. Synchronous Read/Write—Bus Slave
REV. B
–21–
ADSP-21065L
Multiprocessor Bus Request and Host Bus Request
Use these specifications for passing of bus mastership between multiprocessing ADSP-21065Ls (BRx) or a host processor (HBR,
HBG).
Parameter
Min
Max
Units
Timing Requirements:
tHBGRCSV
tSHBRI
tHHBRI
tSHBGI
tHHBGI
tSBRI
HBG Low to RD/WR/CS Valid1
20.0 + 36 DT
6.0 + 12 DT
1.0 + 8 DT
1.0 + 8 DT
ns
ns
ns
ns
ns
ns
ns
HBR Setup Before CLKIN2
12.0 + 12 DT
6.0 + 8 DT
7.0 + 8 DT
HBR Hold Before CLKIN2
HBG Setup Before CLKIN
HBG Hold Before CLKIN High
BRx, CPA Setup Before CLKIN3
BRx, CPA Hold Before CLKIN High
tHBRI
Switching Characteristics:
tDHBGO
tHHBGO
tDBRO
HBG Delay After CLKIN
HBG Hold After CLKIN
BRx Delay After CLKIN
8.0 – 2 DT
7.0 – 2 DT
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.0 – 2 DT
1.0 – 2 DT
1.0 – 2 DT
44.0 + 43 DT
tHBRO
BRx Hold After CLKIN
CPA Low Delay After CLKIN
tDCPAO
tTRCPA
tDRDYCS
tTRDYHG
tARDYTR
11.5 – 2 DT
5.5 – 2 DT
13.0
CPA Disable After CLKIN
REDY (O/D) or (A/D) Low from CS and HBR Low4
REDY (O/D) Disable or REDY (A/D) High from HBG4
REDY (A/D) Disable from CS or HBR High4
10.0
NOTES
1For first asynchronous access after HBR and CS asserted, ADDR23-0 must be a nonMMS value 1/2 tCK before RD or WR goes low or by tHBGRCSV after HBG goes
low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the Host Processor Control of the ADSP-21065L section of the
ADSP-21065L SHARC User’s Manual, Second Edition.
2Only required for recognition in the current cycle.
3CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN.
4(O/D) = open drain, (A/D) = active drive.
–22–
REV. B
ADSP-21065L
CLKIN
tSHBRI
tHHBRI
HBR
tDHBGO
tHHBGO
HBG
(OUT)
tDBRO
tHBRO
BRx
(OUT)
tDCPAO
tTRCPA
CPA (OUT)
(O/D)
tSHBGI
tHHBGI
HBG (IN)
tSBRI
tHBRI
BRx (IN)
CPA (IN) (O/D)
HBR
CS
tTRDYHG
tDRDYCS
REDY (O/D)
REDY (A/D)
tARDYTR
tHBGRCSV
HBG (OUT)
RD
WR
CS
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 15. Multiprocessor Bus Request and Host Bus Request
REV. B
–23–
ADSP-21065L
Asynchronous Read/Write—Host to ADSP-21065L
Use these specifications for asynchronous host processor accesses of an ADSP-21065L, after the host has asserted CS and HBR
(low). After the ADSP-21065L returns HBG, the host can drive the RD and WR pins to access the ADSP-21065L’s IOP registers.
HBR and HBG are assumed low for this timing. Writes can occur at a minimum interval of (1/2) tCK
.
Parameter
Min
Max
Units
Read Cycle
Timing Requirements:
tSADRDL
tHADRDH
tWRWH
Address Setup/CS Low Before RD Low*
Address Hold/CS Hold Low After RD High
RD/WR High Width
0.0
0.0
6.0
0.0
0.0
ns
ns
ns
ns
ns
tDRDHRDY
tDRDHRDY
RD High Delay After REDY (O/D) Disable
RD High Delay After REDY (A/D) Disable
Switching Characteristics:
tSDATRDY
tDRDYRDL
tRDYPRD
Data Valid Before REDY Disable from Low
1.5
ns
ns
ns
ns
REDY (O/D) or (A/D) Low Delay After RD Low
REDY (O/D) or (A/D) Low Pulsewidth for Read
Data Disable After RD High
13.5
10.0
28.0 + DT
2.0
tHDARWH
Write Cycle
Timing Requirements:
tSCSWRL
tHCSWRH
tSADWRH
tHADWRH
tWWRL
CS Low Setup Before WR Low
0.0
0.0
5.0
2.0
7.0
6.0
0.0
5.0
1.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS Low Hold After WR High
Address Setup Before WR High
Address Hold After WR High
WR Low Width
tWRWH
RD/WR High Width
tDWRHRDY
tSDATWH
tHDATWH
WR High Delay After REDY (O/D) or (A/D) Disable
Data Setup Before WR High
Data Hold After WR High
Switching Characteristics:
tDRDYWRL REDY (O/D) or (A/D) Low Delay After WR/CS Low
tRDYPWR REDY (O/D) or (A/D) Low Pulsewidth for Write
13.5
ns
ns
7.75
NOTE
*Not required if RD and address are valid tHBGRCSV after HBG goes low. For first access after HBR asserted, ADDR23-0 must be a nonMMS value 1/2 tCLK before RD
or WR goes low or by tHBGRCSV after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See Host Interface, in
the ADSP-21065L SHARC User’s Manual, Second Edition.
–24–
REV. B
ADSP-21065L
READ CYCLE
ADDRESS/CS
tHADRDH
tSADRDL
tWRWH
RD
tHDARWH
DATA (OUT)
tDRDHRDY
tSDATRDY
tRDYPRD
tDRDYRDL
REDY (O/D)
REDY (A/D)
WRITE CYCLE
ADDRESS
tHADWRH
tSADWRH
tHCSWRH
tSCSWRL
CS
tWWRL
tWRWH
WR
tHDATWH
tSDATWH
DATA (IN)
tDWRHRDY
tDRDYWRL
tRDYPWR
REDY (O/D)
REDY (A/D)
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 16. Asynchronous Read/Write—Host to ADSP-21065L
REV. B
–25–
ADSP-21065L
Three-State Timing—Bus Master, Bus Slave, HBR, SBTS
These specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to CLKIN and
the SBTS pin. This timing is applicable to bus master transition cycles (BTC) and host transition cycles (HTC) as well as the SBTS
pin.
Parameter
Min
Max
Units
Timing Requirements:
tSTSCK
tHTSCK
SBTS Setup Before CLKIN
SBTS Hold Before CLKIN
7.0 + 8 DT
ns
ns
1.0 + 8 DT
Switching Characteristics:
tMIENA
tMIENS
tMIENHG
tMITRA
Address/Select Enable After CLKIN
1.0 – 2 DT
–0.5 – 2 DT
2.0 – 2 DT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Strobes Enable After CLKIN1
HBG Enable After CLKIN
Address/Select Disable After CLKIN
Strobes Disable After CLKIN1
HBG Disable After CLKIN
3.0 – 4 DT
4.0 – 4 DT
5.5 – 4 DT
tMITRS
tMITRHG
tDATEN
tDATTR
tACKEN
tACKTR
tMTRHBG
tMENHBG
Data Enable After CLKIN2
10.0 + 5 DT
1.0 – 2 DT
7.5 + 4 DT
1.0 – 2 DT
2.0 + 2 DT
15.75 + DT
Data Disable After CLKIN2
7.0 – 2 DT
6.0 – 2 DT
ACK Enable After CLKIN2
ACK Disable After CLKIN2
Memory Interface Disable Before HBG Low3
Memory Interface Enable After HBG High3
NOTES
1Strobes = RD, WR, SW, DMAG.
2In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
3Memory Interface = Address, RD, WR, MSx, SW, DMAGx, BMS (in EPROM boot mode).
–26–
REV. B
ADSP-21065L
CLKIN
tSTSCK
tHTSCK
SBTS
tMITRA, tMITRS, tMITRHG
tMIENA, tMIENS, tMIENHG
MEMORY
INTERFACE
tDATTR
tDATEN
DATA
ACK
tACKTR
tACKEN
HBG
tMTRHBG
tMENHBG
MEMORY
INTERFACE
MEMORY INTERFACE = ADDRESS, RD, WR, MSx, SW, DMAGx. BMS (IN EPROM BOOT MODE)
Figure 17. Three-State Timing
REV. B
–27–
ADSP-21065L
DMA Handshake
These specifications describe the three DMA handshake modes. In all three modes DMAR is used to initiate transfers. For hand-
shake mode, DMAG controls the latching or enabling of data externally. For external handshake mode, the data transfer is controlled
by the ADDR23-0, RD, WR, SW, MS3-0, ACK, and DMAG signals. Extern mode cannot be used for transfers with SDRAM. For
Paced Master mode, the data transfer is controlled by ADDR23-0, RD, WR, MS3-0, and ACK (not DMAG). For Paced Master mode,
the Memory Read-Bus Master, Memory Write-Bus Master, and Synchronous Read/Write-Bus Master timing specifications for
ADDR23-0, RD, WR, MS3-0, SW, DATA31-0, and ACK also apply.
Parameter
Min
Max
Units
Timing Requirements:
tSDRLC
DMARx Low Setup Before CLKIN1
5.0
5.0
6.0
ns
ns
ns
ns
ns
ns
ns
ns
tSDRHC
tWDR
DMARx High Setup Before CLKIN1
DMARx Width Low (Nonsynchronous)
Data Setup After DMAGx Low2
Data Hold After DMAGx High
Data Valid After DMARx High2
DMARx Low Edge to Low Edge
DMARx Width High
tSDATDGL
tHDATIDG
tDATDRH
tDMARLL
tDMARH
15.0 + 20 DT
25.0 + 14 DT
0.0
18.0 + 14 DT
6.0
Switching Characteristics:
tDDGL
DMAGx Low Delay After CLKIN
14.0 + 10 DT
10.0 + 12 DT + HI
16.0 + 20 DT
0.0 – 2 DT
28.0 + 16 DT
–1.0
16.0 + 20 DT
0.0
5.0 + 6 DT
18.0 + 19 DT + W
0.75 + 1 DT
5.0
20.0 + 10 DT
6.0 – 2 DT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWDGH
DMAGx High Width
tWDGL
tHDGC
DMAGx Low Width
DMAGx High Delay After CLKIN
Address Select Valid to DMAGx High
Address Select Hold After DMAGx High
Data Valid Before DMAGx High3
Data Disable After DMAGx High4
WR Low Before DMAGx Low
DMAGx Low Before WR High
WR High Before DMAGx High
RD Low Before DMAGx Low
RD Low Before DMAGx High
RD High Before DMAGx High
DMAGx High to WR, RD Low
tDADGH
tDDGHA
tVDATDGH
tDATRDGH
tDGWRL
tDGWRH
tDGWRR
tDGRDL
tDRDGH
tDGRDR
tDGWR
4.0
8.0 + 6 DT
3.0 + 1 DT
8.0
24.0 + 26 DT + W
0.0
5.0 + 6 DT + HI
2.0
W = (number of wait states specified in WAIT register) × tCK
.
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
NOTES
1Only required for recognition in the current cycle.
2tSDATDGL is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the
data can be driven tDATDRH after DMARx is brought high.
3tVDATDGH is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then tVDATDGH = 8 + 9 DT + (n × tCK) where n
equals the number of extra cycles that the access is prolonged.
4See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
–28–
REV. B
ADSP-21065L
CLKIN
tSDRLC
tDMARLL
tSDRHC
tWDR
tDMARH
DMARx
DMAGx
tHDGC
tDDGL
tWDGL
tWDGH
TRANSFERS BETWEEN ADSP-2106x INTERNAL MEMORY AND EXTERNAL DEVICE
tDATRDGH
tVDATDGH
DATA (FROM
ADSP-2106x TO
EXTERNAL DEVICE)
tDATDRH
tHDATIDG
tSDATDGL
DATA (FROM
EXTERNAL DEVICE
TO ADSP-2106x)
TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE)
tDGWRL
tDGWRH
tDGWRR
WR
(EXTERNAL DEVICE
TO EXTERNAL
MEMORY)
tDGRDR
tDGRDL
RD
(EXTERNAL
MEMORY TO
EXTERNAL DEVICE)
tDRDGH
tDDGHA
tDADGH
ADDRESS
SW, MSx
*“MEMORY READ – BUS MASTER,” “MEMORY WRITE – BUS MASTER” AND “SYNCHRONOUS READ/WRITE – BUS MASTER”
TIMING SPECIFICATIONS FOR ADDR RD WR SW MS AND ACK ALSO APPLY HERE.
,
,
,
,
23–0
3–0
Figure 18. DMA Handshake Timing
REV. B
–29–
ADSP-21065L
SDRAM Interface—Bus Master
Use these specifications for ADSP-21065L bus master accesses of SDRAM.
Parameter
Min
Max
Units
Timing Requirements:
tSDSDK
tHDSDK
Data Setup Before SDCLK
Data Hold After SDCLK
2.0
1.25
ns
ns
Switching Characteristics:
tDSDK1
tDSDK2
tSDK
First SDCLK Rise Delay After CLKIN
Second SDCLK Rise Delay After CLKIN
SDCLK Period
9.0 + 6 DT
25.5 + 22 DT
16.67
7.5 + 8 DT
6.5 + 8 DT
12.75 + 6 DT
29.25 + 22 DT
tCK/2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSDKH
tSDKL
SDCLK Width High
SDCLK Width Low
tDCADSDK
tHCADSDK
tSDTRSDK
tSDENSDK
tSDCTR
tSDCEN
tSDATR
tSDAEN
Command, Address, Data, Delay After SDCLK1
Command, Address, Data, Hold After SDCLK1
Data Three-State After SDCLK
Data Enable After SDCLK2
10.0 + 5 DT
9.5 + 5 DT
4.5 + 5 DT
6.0 + 5 DT
5.0 + 3 DT
5.0 + 2 DT
–1.0 – 4 DT
1.0 – 2 DT
SDCLK, Command Three-State After CLKIN1
SDCLK, Command Enable After CLKIN1
Address Three-State After CLKIN
Address Enable After CLKIN
9.75 + 3 DT
10.0 + 2 DT
3.0 – 4 DT
7.0 – 2 DT
NOTES
1Command = SDCKE, MSx, RAS, CAS, SDWE, DQM, and SDA10.
2SDRAM controller adds one SDRAM CLK three-stated cycle delay (tCK/2) on a Read followed by a Write.
SDRAM Interface—Bus Slave
These timing requirements allow a bus slave to sample the bus master’s SDRAM command and detect when a refresh occurs.
Parameter
Min
Max
Units
Timing Requirements:
tSSDKC1
tSSDKC2
tSCSDK
tHCSDK
First SDCLK Rise After CLKIN
6.50 + 16 DT
23.25
0.0
17.5 + 16 DT
34.25
ns
ns
ns
ns
Second SDCLK Rise After CLKIN
Command Setup Before SDCLK1
Command Hold After SDCLK1
2.0
NOTE
1Command = SDCKE, RAS, CAS, and SDWE.
–30–
REV. B
ADSP-21065L
CLKIN
tDSDK2
tSDK
tDSDK1
tSDKH
SDCLK
tSDSDK
tSDKL
tHDSDK
DATA
(IN)
tSDTRSDK
tHCADSDK
tDCADSDK
tSDENSDK
DATA
(OUT)
tDCADSDK
1
CMND
ADDR
(OUT)
tHCADSDK
tSDCEN
tSDCTR
1
CMND
(OUT)
ADDR
(OUT)
tSDAEN
tSDATR
CLKIN
tSSDKC2
tSSDKC1
SDCLK
(IN)
tSCSDK
2
CMND
(IN)
tHCSDK
NOTES
1
COMMAND = SDCKE, MS , RAS, CAS, SDWE, DQM AND SDA10.
X
2
SDRAM CONTROLLER ADDS ONE SDRAM CLK THREE-STATED CYCLE DELAY (tCK/2) ON A READ FOLLOWED BY A WRITE.
Figure 19. SDRAM Interface
REV. B
–31–
ADSP-21065L
Serial Ports
Parameter
Min
Max
Units
External Clock
Timing Requirements:
tSFSE
TFS/RFS Setup Before TCLK/RCLK1
4.0
4.0
1.5
4.0
9.0
tCK
ns
ns
ns
ns
ns
ns
tHFSE
tSDRE
tHDRE
tSCLKW
tSCLK
TFS/RFS Hold After TCLK/RCLK1
Receive Data Setup Before RCLK1
Receive Data Hold After RCLK1
TCLK/RCLK Width
TCLK/RCLK Period
Internal Clock
Timing Requirements:
tSFSI
TFS Setup Before TCLK2; RFS Setup Before RCLK1
8.0
1.0
3.0
3.0
ns
ns
ns
ns
tHFSI
tSDRI
tHDRI
TFS/RFS Hold After TCLK/RCLK1
Receive Data Setup Before RCLK1
Receive Data Hold After RCLK1
External or Internal Clock
Switching Characteristics:
tDFSE
RFS Delay After RCLK (Internally Generated RFS)2
13.0
ns
ns
tHOFSE
RFS Hold After RCLK (Internally Generated RFS)2
3.0
External Clock
Switching Characteristics:
tDFSE
TFS Delay After TCLK (Internally Generated TFS)2
13.0
12.5
ns
ns
ns
ns
tHOFSE
tDDTE
tHDTE
TFS Hold After TCLK (Internally Generated TFS)2
Transmit Data Delay After TCLK2
3.0
4.0
Transmit Data Hold After TCLK2
Internal Clock
Switching Characteristics:
tDFSI
TFS Delay After TCLK (Internally Generated TFS)2
4.5
ns
ns
ns
ns
ns
tHOFSI
tDDTI
tHDTI
tSCLKIW
TFS Hold After TCLK (Internally Generated TFS)2
Transmit Data Delay After TCLK2
Transmit Data Hold After TCLK2
TCLK/RCLK Width
–1.5
7.5
0.0
(tSCLK/2) – 2.5
(tSCLK/2) + 2.5
Enable and Three-State
Switching Characteristics:
tDTENE
tDDTTE
tDTENI
tDDTTI
tDCLK
Data Enable from External TCLK2
5.0
0.0
ns
ns
ns
ns
ns
ns
Data Disable from External RCLK2
Data Enable from Internal TCLK2
Data Disable from Internal TCLK2
TCLK/RCLK Delay from CLKIN
SPORT Disable After CLKIN
10.0
3.0
18.0 + 6 DT
14.0
tDPTR
External Late Frame Sync
tDDTLFSE
Data Delay from Late External TFS or External RFS
with MCE = 1, MFD = 03, 4
10.5
12.0
ns
ns
tDTENLFSE
tDDTLSCK
Data Enable from late FS or MCE = 1, MFD = 03, 4
Data Delay from TCLK/RCLK for Late External
TFS or External RFS with MCE = 1, MFD = 03, 4
Data Enable from RCLK/TCLK for Late External FS or
MCE = 1, MFD = 03, 4
3.5
4.5
ns
ns
tDTENLSCK
NOTES
To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame
sync setup-and-hold, 2) data delay and data setup-and-hold, and 3) SCLK width.
1Referenced to sample edge.
2Referenced to drive edge.
3MCE = 1, TFS enable and TFS valid follow tDDTENFS and tDDTLFSE.
4If external RFS/TFS setup to RCLK/TCLK > tSCLK/2 then tDDTLSCK and tDTENLSCK apply; otherwise tDDTLFSE and tDTENLFS apply.
*Word selected timing for I2S mode is the same as TFS/RFS timing (normal framing only).
–32–
REV. B
ADSP-21065L
DATA RECEIVE– INTERNAL CLOCK
DATA RECEIVE– EXTERNAL CLOCK
SAMPLE
EDGE
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKW
RCLK
RCLK
tDFSE
tHOFSE
tDFSE
tHOFSE
tHFSE
tSFSI
tHFSI
tSFSE
RFS
DR
RFS
DR
tSDRE
tHDRE
tSDRI
tHDRI
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT– INTERNAL CLOCK
DATA TRANSMIT– EXTERNAL CLOCK
SAMPLE
EDGE
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKW
TCLK
TCLK
tDFSI
tHOFSI
tDFSE
tHOFSE
tSFSI
tHFSI
tHFSE
tSFSE
TFS
TFS
tDDTI
tDDTE
tHDTI
tHDTE
DT
DT
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE
EDGE
DRIVE
EDGE
TCLK (EXT)
TFS ("LATE", EXT.)
TCLK / RCLK
tDDTEN
tDDTTE
DT
DRIVE
EDGE
DRIVE
EDGE
TCLK (INT)
TFS ("LATE", INT.)
TCLK / RCLK
tDDTIN
tDDTTI
DT
CLKIN
tDPTR
SPORT ENABLE AND
THREE-STATE
LATENCY
TCLK, RCLK
TFS, RFS, DT
SPORT DISABLE DELAY
FROM INSTRUCTION
IS TWO CYCLES
tDCLK
TCLK (INT)
RCLK (INT)
LOW TO HIGH ONLY
Figure 20. Serial Ports
REV. B
–33–
ADSP-21065L
EXTERNAL RFS with MCE = 1, MFD = 0
DRIVE
DRIVE
SAMPLE
RCLK
tHOFSE/I
tSFSE/I
RFS
tDDTE/I
tHDTE/I
tDTENLFSE
1ST BIT
2ND BIT
DT
tDDTLFSE
LATE EXTERNAL TFS
DRIVE
DRIVE
SAMPLE
TCLK
tHOFSE/I
tSFSE/I
TFS
DT
tDDTE/I
tHDTE/I
tDTENLFSE
1ST BIT
2ND BIT
tDDTLFSE
Figure 21. External Late Frame Sync (Frame Sync Setup < tSCLK/2)
EXTERNAL RFS with MCE = 1, MFD = 0
DRIVE
SAMPLE
DRIVE
RCLK
RFS
tHOFSE/I
tSFSE/I
tDDTE/I
tHDTE/I
tDTENLSCK
DT
1ST BIT
2ND BIT
tDDTLSCK
LATE EXTERNAL TFS
DRIVE
SAMPLE
DRIVE
TCLK
TFS
tHOFSE/I
tSFSE/I
tDDTE/I
tHDTE/I
tDTENLSCK
DT
1ST BIT
2ND BIT
tDDTLSCK
Figure 22. External Late Frame Sync (Frame Sync Setup > tSCLK/2)
–34–
REV. B
ADSP-21065L
JTAG Test Access Port and Emulation
Parameter
Min
Max
Units
Timing Requirements:
tTCK
TCK Period
tCK
3.0
3.0
7.0
12.0
4 tCK
ns
ns
ns
ns
ns
ns
tSTAP
tHTAP
tSSYS
tHSYS
tTRSTW
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK Low1
System Inputs Hold After TCK Low1
TRST Pulsewidth
Switching Characteristics:
tDTDO TDO Delay from TCK Low
tDSYS
System Outputs Delay After TCK Low2
11.0
15.0
ns
ns
NOTES
1System Inputs = DATA31-0, ADDR23-0, RD, WR, ACK, SBTS, SW, HBR, HBG, CS, DMAR1, DMAR2, BR2-1, ID1-0, IRQ2-0, FLAG11-0, DR0x, DR1x, TCLK0,
TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, BSEL, BMS, CLKIN, RESET, SDCLK0, RAS, CAS, SDWE, SDCKE, PWM_EVENTx.
2System Outputs = DATA31-0, ADDR23-0, MS3-0, RD, WR, ACK, SW, HBG, REDY, DMAG1, DMAG2, BR2-1, CPA, FLAG11-0, PWM_EVENTx, DT0x, DT1x,
TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, BMS, SDCLK0, SDCLK1, DQM, SDA10, RAS, CAS, SDWE, SDCKE, BM, XTAL.
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 23. JTAG Test Access Port and Emulation
REV. B
–35–
ADSP-21065L
OUTPUT DRIVE CURRENT
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose ∆V
to be the difference between the ADSP-21065L’s output voltage
and the input threshold for the device requiring the hold time. A
typical ∆V will be 0.4 V. CL is the total bus capacitance (per
data line), and IL is the total leakage or three-state current (per
data line). The hold time will be tDECAY plus the minimum
disable time (i.e., tDATRWH for the write cycle).
80
V
OH
3.1V, +85؇C
3.6V, –40
؇C
60
40
20
3.3V, +25
؇
C
3.1V, +100؇C
0
–20
3.1V, +100؇C
–40
–60
–80
3.3V, +25؇C
3.6V, –40؇C
REFERENCE
SIGNAL
3.1V, +85؇C
V
OL
tMEASURED
tENA
–100
–120
tDIS
V
V
0.50
1.00
1.50
2.00
2.50
3.00
3.50
0
OH (MEASURED)
V
V
OH (MEASURED)
SOURCE VOLTAGE – V
V
– ⌬V
+ ⌬V
2.0V
1.0V
OH (MEASURED)
OUTPUT
V
OL (MEASURED)
Figure 24. Typical Drive Currents
OL (MEASURED)
OL (MEASURED)
tDECAY
TEST CONDITIONS
Output Disable Time
OUTPUT STARTS
DRIVING
OUTPUT STOPS
DRIVING
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from
their output high or low voltage. The time for the voltage on the
bus to decay by ∆V is dependent on the capacitive load, CL and
the load current, IL. This decay time can be approximated by
the following equation:
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE TO BE
APPROXIMATELY 1.5V
Figure 25. Output Enable
I
OL
CL × ∆V
tDECAY
=
IL
The output disable time tDIS is the difference between tMEASURED
and tDECAY as shown in Figure 26. The time tMEASURED is the
interval from when the reference signal switches to when the
output voltage decays ∆V from the measured output high or
output low voltage. tDECAY is calculated with test loads CL and
IL, and with ∆V equal to 0.5 V.
TO
OUTPUT
PIN
+1.5V
50pF
Output Enable Time
I
OH
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start
driving. The output enable time tENA is the interval from when a
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram. If multiple pins (such as
the data bus) are enabled, the measurement value is that of the
first pin to start driving.
Figure 26. Equivalent Device Loading for AC Measure-
ments (Includes All Fixtures)
INPUT OR
OUTPUT
1.5V
1.5V
Figure 27. Voltage Reference Levels for AC Measure-
ments (Except Output Enable/Disable)
–36–
REV. B
ADSP-21065L
Capacitive Loading
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
Output delays and holds are based on standard capacitive loads:
50 pF on all pins. The delay and hold specifications given
should be derated by a factor of l.8 ns/50 pF for loads other
than the nominal value of 50 pF. Figure 28 and Figure 29 show
how output rise time varies with capacitance. Figure 30 shows
graphically how output delays and hold vary with load capaci-
tance. (Note that this graph or derating does not apply to output
disable delays; see the previous section Output Disable time
under Test Conditions.) The graphs of Figure 28, Figure 29
and Figure 30 may not be linear outside the ranges shown.
RISE TIME
FALL TIME
18
16
14
12
0
0
20
40
60
80
100 120 140 160 180 200
LOAD CAPACITANCE – pF
Figure 29. Typical Rise and Fall Time (0.8 V–2.0 V)
RISE TIME
10
6
5
4
8
FALL TIME
6
4
2
0
3
2
0
20
40
60
80
100 120 140 160 180 200
LOAD CAPACITANCE – pF
1
Figure 28. Typical Rise and Fall Time (10%–90% VDD
)
0
–1
–2
0
20
40
60
80
100 120 140 160 180 200
LOAD CAPACITANCE – pF
Figure 30. Typical Output Delay or Hold
REV. B
–37–
ADSP-21065L
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation. (IDDIN
see calculation in Electrical Characteristics section):
POWER DISSIPATION
Total power dissipation has two components: one due to inter-
nal circuitry and one due to the switching of external output
drivers. Internal power dissipation depends on the sequence in
which instructions execute and the data operands involved. See
IDDIN calculation in Electrical Characteristics section. Internal
power dissipation is calculated this way:
P
TOTAL = PEXT + (IDDIN × VDD)
Note that the conditions causing a worst-case PEXT differ from
those causing a worst-case PINT. Maximum PINT cannot occur
while 100% of the output pins are switching from all ones (1s)
to all zeros (0s). Note also that it is not common for an appli-
cation to have 100% or even 50% of the outputs switching
simultaneously.
PINT = IDDIN × VDD
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
– the number of output pins that switch during each cycle (O)
– the maximum frequency at which the pins can switch (f)
– the load capacitance of the pins (C)
ENVIRONMENTAL CONDITIONS
Thermal Characteristics
The ADSP-21065L is offered in a 208-lead MQFP and a 196-
ball Mini-BGA package.
– the voltage swing of the pins (VDD).
The external component is calculated using:
The ADSP-21065L is specified for a case temperature (TCASE
To ensure that TCASE is not exceeded, an air flow source may be
used.
)
.
2
P
EXT = O × C × VDD × f
The load capacitance should include the processor’s package
capacitance (CIN). The frequency f includes driving the load
high and then back low. Address and data pins can drive high
and low at a maximum rate of 1/tCK while in SDRAM burst
mode.
TCASE = TAMB + (PD × θCA
)
TCASE = Case temperature (measured on top surface of package)
PD = Power Dissipation in W (this value depends upon the
specific application; a method for calculating PD is
shown under Power Dissipation)
Example:
Estimate PEXT with the following assumptions:
θJC
θJC
=
=
7.1°C/W for 208-lead MQFP
5.1°C/W for 196-ball Mini-BGA
– a system with one bank of external memory (32-bit)
– two 1M × 16 SDRAM chips, each with a control signal load
of 3 pF and a data signal load of 4 pF
Airflow
Table VI. Thermal Characteristics (208-Lead MQFP)
– external data writes occur in burst mode, two every 1/tCK
cycles, a potential frequency of 1/tCK cycles/s. Assume 50%
pin switching
– the external SDRAM clock rate is 60 MHz (2/tCK).
(Linear Ft./Min.)
CA (°C/W)
0
100
200
400
600
The PEXT equation is calculated for each class of pins that can
drive:
θ
24
20
19
17
13
Table VII. 196-Ball Mini-BGA
Table V. External Power Calculations
(Linear Ft./Min.)
CA (°C/W)
0
200
400
Pin
Type
# of
%
2
θ
38
29
23
Pins Switching
؋
C ؋
f ؋
VDD = PEXT
Address
MS0
SDWE
Data
11
1
1
50
0
0
× 10.7 × 30 MHz × 10.9 V = 0.019 W
× 10.7
× 10.7
× 7.7
—
—
× 10.9 V = 0.000 W
× 10.9 V = 0.000 W
32
50
× 30 MHz × 10.9 V = 0.042 W
SDRAM CLK 1
–
× 10.7 × 30 MHz × 10.9 V = 0.007 W
P
EXT = 0.068 W
–38–
REV. B
ADSP-21065L
208-LEAD MQFP PIN CONFIGURATION
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin
No.
Pin
Name
1
2
3
4
5
6
7
8
VDD
RFS0
GND
RCLK0
DR0A
DR0B
TFS0
TCLK0
VDD
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
CAS
SDWE
VDD
DQM
SDCKE
SDA10
GND
DMAG1
DMAG2
HBG
BMSTR
VDD
CS
SBTS
GND
WR
RD
GND
VDD
GND
REDY
SW
CPA
VDD
VDD
GND
ACK
MS0
MS1
GND
GND
MS2
MS3
FLAG11
VDD
FLAG10
FLAG9
FLAG8
GND
DATA0
DATA1
DATA2
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
VDD
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
DATA28
DATA29
GND
VDD
VDD
DATA30
DATA31
FLAG7
GND
FLAG6
FLAG5
FLAG4
GND
VDD
VDD
NC
ID1
ID0
EMU
TDO
TRST
TDI
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
ADDR17
ADDR16
ADDR15
VDD
ADDR14
ADDR13
ADDR12
VDD
DATA3
DATA4
DATA5
GND
DATA6
DATA7
DATA8
VDD
9
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
GND
GND
VDD
ADDR11
ADDR10
ADDR9
GND
DT0A
DT0B
RFS1
DATA9
DATA10
DATA11
GND
DATA12
DATA13
NC
NC
DATA14
VDD
GND
VDD
RCLK1
DR1A
DR1B
TFS1
TCLK1
VDD
ADDR8
ADDR7
ADDR6
GND
GND
ADDR5
ADDR4
ADDR3
VDD
VDD
DT1A
DT1B
PWM_EVENT1
GND
PWM_EVENT0
BR1
BR2
VDD
CLKIN
XTAL
VDD
GND
DATA15
DATA16
DATA17
VDD
DATA18
DATA19
DATA20
GND
TMS
GND
TCK
BSEL
BMS
GND
GND
VDD
VDD
ADDR2
ADDR1
ADDR0
GND
FLAG0
FLAG1
FLAG2
VDD
FLAG3
NC
NC
GND
IRQ0
NC
RESET
VDD
GND
DATA21
DATA22
DATA23
GND
GND
SDCLK1
GND
ADDR23
ADDR22
ADDR21
VDD
ADDR20
ADDR19
ADDR18
GND
VDD
VDD
SDCLK0
DMAR1
DMAR2
HBR
GND
RAS
DATA24
DATA25
DATA26
VDD
GND
DATA27
IRQ1
IRQ2
NC
GND
REV. B
–39–
ADSP-21065L
208-LEAD MQFP PIN
VDD
RSF0
GND
RCLK0
DR0A
DR0B
TFS0
TCLK0
VDD
1
2
3
4
5
6
7
8
9
VDD
GND
GND
156
155
154
153
152
151
PIN 1
IDENTIFIER
BMS
BSEL
TCK
150 GND
149 TMS
148
TDI
GND
DT0A 11
10
147
TRST
146 TDO
145
DT0B
RFS1
12
13
EMU
ID0
144
GND 14
RCLK1 15
143 ID1
142 NC
141
16
17
18
19
DR1A
DR1B
TFS1
VDD
140
139
138
137
136
135
134
133
132
131
VDD
GND
FLAG4
FLAG5
FLAG6
GND
FLAG7
DATA31
DATA30
VDD
TCLK1
VDD 20
VDD
DT1A
21
22
DT1B 23
PWM EVENT1 24
GND 25
ADSP-21065L
TOP VIEW
PWM EVENT0
26
27
28
29
130 VDD
129 GND
128
BR1
BR2
VDD
(Not to Scale)
DATA29
CLKIN 30
127 DATA28
126
31
XTAL
VDD 32
DATA27
125 GND
33
34
35
124
123
122
121
GND
SDCLK1
GND
VDD
DATA26
DATA25
DATA24
VDD 36
SDCLK0 37
120 VDD
GND
119
118
117
116
115
114
113
112
111
110
109
108
38
DMAR1
DMAR2
HBR
39
40
DATA23
DATA22
DATA21
NC
GND
DATA20
DATA19
DATA18
VDD
DATA17
DATA16
GND 41
42
RAS
CAS
SDWE
VDD
43
44
45
DQM 46
SDCKE 47
SDA10
48
GND 49
50
51
52
107 DATA15
DMAG1
DMAG2
HBG
GND
VDD
106
105
NC = NO CONNECT
–40–
REV. B
ADSP-21065L
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
208-Lead Plastic Quad Flatpack (MQFP)
1.213 (30.80)
1.205 (30.60) SQ
1.197 (30.40)
0.161 (4.10)
MAX
0.030 (0.75)
0.024 (0.60)
0.020 (0.50)
208
157
156
10
TYP
1
SEATING
PLANE
1.106 (28.10)
1.102 (28.00) SQ
1.098 (27.90)
TOP VIEW
(PINS DOWN)
0.003 (0.08)
MAX LEAD
105
104
52
COPLANARITY
53
0
MIN
0.007 (0.17) MAX
0.020 (0.50)
0.011 (0.27)
0.020 (0.50)
BSC
0.009 (0.22)
0.007 (0.17)
LEAD WIDTH
0.010 (0.25)
LEAD PITCH
0.141 (3.59)
0.137 (3.49)
0.133 (3.39)
NOTES
1. THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.003 (0.08) FROM ITS IDEAL
POSITION WHEN MEASURED IN THE LATERAL DIRECTION.
2. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.
3. THE 208 LEAD MQFP IS A METRIC PACKAGE. ENGLISH DIMENSIONS PROVIDED
ARE APPROXIMATE AND MUST NOT BE USED FOR BOARD DESIGN PURPOSES.
REV. B
–41–
ADSP-21065L
196-BALL MINI-BGA PIN CONFIGURATION
Ball #
Name
Ball #
Name
Ball #
Name
Ball #
Name
Ball #
Name
A1
A2
A3
A4
A5
A6
A7
A8
NC1
NC2
B1
B2
B3
B4
B5
B6
B7
B8
DR0A
RFS0
IRQ0
C1
C2
C3
C4
C5
C6
C7
C8
TCLK0
RCLK0
IRQ2
D1
D2
D3
D4
D5
D6
D7
D8
RCLK1
TFS0
DR0B
IRQ1
FLAG1
VDD
VDD
VDD
VDD
VDD
BMS
E1
E2
E3
E4
E5
E6
E7
E8
TFS1
DT0B
DT0A
RFS1
VDD
GND
GND
GND
GND
VDD
ID0
FLAG2
ADDR0
ADDR3
ADDR6
ADDR7
ADDR8
ADDR11
ADDR14
ADDR17
ADDR18
NC8
FLAG0
ADDR2
ADDR5
ADDR9
ADDR12
ADDR15
ADDR19
ADDR21
ADDR23
GND
FLAG3
ADDR1
ADDR4
ADDR10
ADDR13
ADDR16
ADDR20
ADDR22
RESET
BSEL
A9
B9
C9
D9
E9
A10
A11
A12
A13
A14
B10
B11
B12
B13
B14
C10
C11
C12
C13
C14
D10
D11
D12
D13
D14
E10
E11
E12
E13
E14
TMS
TRST
EMU
TDI
ID1
FLAG4
NC7
TCK
TDO
F1
TCLK1
G1
PWM_
EVENT1
DT1B
DT1A
VDD
GND
GND
GND
GND
GND
GND
VDD
DATA31
DATA30
DATA29
H1
PWM_
EVENT0
BR1
BR2
VDD
GND
GND
GND
GND
GND
GND
VDD
DATA28
DATA27
DATA26
J1
CLKIN
K1
DMAR1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
DR1B
DR1A
VDD
GND
GND
GND
GND
GND
GND
VDD
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
XTAL
SDCLK1
VDD
GND
GND
GND
GND
GND
GND
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
K13
K14
SDCLK0
HBR
SDWE
VDD
GND
GND
GND
GND
VDD
DATA19
DATA21
DATA20
DATA22
VDD
FLAG6
FLAG5
FLAG7
DATA24
DATA25
DATA23
L1
L2
L3
L4
L5
L6
DMAR2
CAS
SDA10
DMAG2
VDD
M1
M2
M3
M4
M5
M6
RAS
N1
N2
N3
N4
N5
N6
DQM
HBG
BMSTR
SBTS
REDY
GND
P1
P2
P3
P4
P5
P6
NC3
NC4
GND
WR
SW
SDCKE
DMAG1
CS
RD
CPA
VDD
MS0
L7
VDD
M7
ACK
N7
MS1
P7
MS2
L8
L9
VDD
VDD
M8
M9
FLAG10
DATA2
DATA5
DATA9
DATA12
DATA14
DATA15
N8
N9
FLAG11
DATA1
DATA4
DATA7
DATA10
DATA11
NC6
P8
P9
MS3
FLAG9
FLAG8
DATA0
DATA3
DATA6
NC5
L10
L11
L12
L13
L14
DATA8
DATA13
DATA16
DATA17
DATA18
M10
M11
M12
M13
M14
N10
N11
N12
N13
N14
P10
P11
P12
P13
P14
–42–
REV. B
ADSP-21065L
196-BALL MINI-BGA PIN CONFIGURATION
14
13
12
11
10
9
8
7
6
5
4
3
2
1
NC7
NC8
ADDR18 ADDR17 ADDR14 ADDR11 ADDR8
ADDR7
ADDR6
ADDR3
ADDR0
FLAG2
NC2
RFS0
RCLK0
TFS0
NC1
A
B
C
D
E
F
TCK
TDO
GND
ADDR23 ADDR21 ADDR19 ADDR15 ADDR12 ADDR9
ADDR5
ADDR2
ADDR1
FLAG1
VDD
FLAG0
FLAG3
DR0A
TCLK0
RCLK1
TFS1
IRQ0
IRQ2
BSEL
ADDR22 ADDR20 ADDR16 ADDR13 ADDR10 ADDR4
RESET
TMS
VDD
VDD
GND
GND
GND
GND
VDD
VDD
GND
GND
GND
GND
GND
GND
VDD
VDD
GND
GND
GND
GND
GND
GND
VDD
VDD
GND
GND
GND
GND
GND
GND
VDD
ACK
VDD
GND
GND
GND
GND
GND
GND
VDD
DR0B
DT0A
DR1A
DT1A
EMU
TRST
ID1
BMS
ID0
IRQ1
RFS1
VDD
FLAG4
FLAG7
TDI
DT0B
DR1B
DT1B
FLAG5
FLAG6
VDD
VDD
VDD
VDD
GND
TCLK1
PWM_
EVENT1
DATA29 DATA30 DATA31
DATA26 DATA27 DATA28
DATA23 DATA25 DATA24
GND
VDD
G
H
PWM_
EVENT0
GND
VDD
BR2
BR1
XTAL
GND
VDD
SDCLK1
CLKIN
DMAR1
DMAR2
RAS
J
DATA22 DATA20 DATA21 DATA19
VDD
SDCLK0
SDWE
DMAG2
CS
HBR
K
L
DATA18 DATA17 DATA16 DATA13 DATA8
VDD
SDA10
CAS
DATA15 DATA14 DATA12 DATA9
DATA5
DATA4
FLAG8
DATA2 FLAG10
DATA1 FLAG11
SDCKE
CPA
RD
DMAG1
BMSTR
GND
M
N
P
NC6
NC5
DATA11 DATA10 DATA7
GND
REDY
DQM
MS1
MS2
SBTS
WR
HBG
DATA6
DATA3
DATA0
FLAG9
NC4
NC3
MS3
MS0
SW
REV. B
–43–
ADSP-21065L
ORDERING GUIDE
Part
Number
Case Temperature
Range
Instruction
Rate
On-Chip
SRAM
Operating
Voltage
Package
Options
ADSP-21065LKS-240
ADSP-21065LCS-240
ADSP-21065LKCA-240
ADSP-21065LKS-264
ADSP-21065LKCA-264
0°C to +85°C
–40°C to +100°C
0°C to +85°C
0°C to +85°C
0°C to +85°C
60 MHz
60 MHz
60 MHz
66 MHz
66 MHz
544 Kbit
544 Kbit
544 Kbit
544 Kbit
544 Kbit
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
MQFP
MQFP
Mini-BGA
MQFP
Mini-BGA
OUTLINE DIMENSIONS
Dimensions shown in mm.
196-Ball Mini-BGA
15.20
15.00 SQ
14.80
DETAIL B
14 13 12 1110 9
8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
13.00
BSC
15.20
15.00 SQ
14.80
TOP VIEW
1.00
BSC
K
L
M
N
P
DETAIL A
1.00 BSC
1.90
1.75
1.60
13.00 BSC
DETAIL A
DETAIL B
CCC = 0.25
(TOP PLANARITY)
0.75
0.70
0.65
1.10
1.00
0.90
0.55
NOM
0.60
0.50
0.40
1.10
1.00
0.90
0.20
MAX BALL
COPLANARITY
0.70
0.60
0.50
BALL
SEATING
PLANE
1.00
BSC
DIAMETER
NOTES
1. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.30 OF ITS IDEAL POSITION RELATIVE TO THE
PACKAGE EDGES. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.10 OF ITS IDEAL POSITION
RELATIVE TO THE BALL GRID.
2. ALL MEASUREMENTS ARE PROVIDED IN METRIC UNITS BECAUSE THIS IS A METRIC PACKAGE.
ANALOG DEVICES STRONGLY RECOMMENDS THAT YOU DESIGN WITH THE METRIC MEASUREMENTS
ONLY.
3. BALL DIAMETER HAS BEEN CHANGED FROM 0.50mm NOMINAL TO 0.60mm NOMINAL TO COMPLY
WITH JEDEC STANDARD PUBLICATION 95 CASE OUTLINE DRAWING MO–151. 0.60 NOMINAL BALL
DIAMETER PRODUCT WILL BE AVAILABLE IN JULY, 2000.
–44–
REV. B
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