ADSP-21160N_技术文档

PRELIMINARY TECHNICAL DATA

a

DSP Microcomputer

ADSP-21160N

Preliminary Technical Data

SUMMARY

KEY FEATURES

High-Performance 32-Bit DSP—Applications in Audio,

Medical, Military, Graphics, Imaging, and

Communication

Super Harvard Architecture—Four Independent Buses

for Dual Data Fetch, Instruction Fetch, and

Nonintrusive, Zero-Overhead I/O

Backwards-Compatible—Assembly Source Level

Compatible with Code for ADSP-2106x DSPs

Single-Instruction-Multiple-Data (SIMD) Computational

Architecture—Two 32-Bit IEEE Floating-Point

Computation Units, Each with a Multiplier, ALU,

Shifter, and Register File

95 MHz (10.5 ns) Core Instruction Rate

Single-Cycle Instruction Execution, Including SIMD

Operations in Both Computational Units

570 MFLOPS Peak and 380 MFLOPS Sustained

Performance (Based on FIR)

Dual Data Address Generators (DAGs) with Modulo and

Bit-Reverse Addressing

Zero-Overhead Looping and Single-Cycle Loop Setup,

Providing Efficient Program Sequencing

IEEE 1149.1 JTAG Standard Test Access Port and

On-Chip Emulation

400-Ball 27

؋

27 mm Metric PBGA Package

Integrated Peripherals—Integrated I/O Processor,

4M Bits On-Chip Dual-Ported SRAM, Glueless

Multiprocessing Features, and Ports (Serial, Link,

External Bus, and JTAG)

FUNCTIONAL BLOCK DIAGRAM

CORE PROCESSOR

TIMER

DUAL-PORTED SRAM

JTAG

INSTRUCTION

CACHE

32 X 48-BIT

TWO INDEPENDENT

DUAL-PORTED BLOCKS

6

TEST AND

EMULATION

PROCESSOR PORT

ADDR DATA

ADDR

I/O PORT

DATA ADDR

DATA

ADDR

DATA

DAG2

8X4X32

DAG1

8X4X32

PROGRAM

SEQUENCER

EXTERNAL

PORT

IOD

64

IOA

18

PM ADDRESS BUS

32

64

ADDR BUS

MUX

DM ADDRESS BUS

MULTIPROCESSOR

INTERFACE

PM DATA BUS

DM DATA BUS

16/32/40/48/64

32/40/64

BUS

CONNECT

(PX)

DATA BUS

MUX

HOST PORT

DATA

REGISTER

FILE

(PEX)

16 X 40-BIT

FILE

(PEY)

16 X 40-BIT

4

DMA

CONTROLLER

IOP

BARREL

SHIFTER

BARREL

SHIFTER

MULT

REGISTERS

(MEMORY

MAPPED)

6

SERIAL PORTS

(2)

CONTROL,

STATUS, AND

DATA BUFFERS

60

LINK PORTS

(6)

ALU

I/O PROCESSOR

REV. PrB

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fications are subject to change without notice. Analog Devices

Tel:781/329-4700

www.analog.com

©Analog Devices,Inc., 2002

assumes no obligation regarding future manufacturing unless otherwise agreed to in Fax:781/326-8703

writing.

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

GENERAL DESCRIPTION

April 2002

FEATURES (CONTINUED)

ADSP-21160N

The ADSP-21160N SHARC DSP is the second iteration

of the ADSP-21160. Built in a 0.18 micron CMOS process,

it offers higher performance and lower power consumption

than its predecessor, the ADSP-21160M. Easing portabil-

ity, the ADSP-21160N is application source code

compatible with first generation ADSP-2106x SHARC

DSPs in SISD (Single Instruction, Single Data) mode. To

takeadvantageoftheprocessor’sSIMD(SingleInstruction,

Multiple Data) capability, some code changes are needed.

Like other SHARCs, the ADSP-21160N is a 32-bit

processor that is optimized for high performance DSP appli-

cations. The ADSP-21160N includes an 95 MHz core, a

dual-ported on-chip SRAM, an integrated I/O processor

with multiprocessing support, and multiple internal buses

to eliminate I/O bottlenecks.

Single Instruction Multiple Data (SIMD)

Architecture Provides:

Two Computational Processing Elements

Concurrent Execution—Each Processing Element

Executes the Same Instruction, but Operates on

Different Data

Code Compatibility—at Assembly Level, Uses the

Same Instruction Set as the ADSP-2106x

SHARC DSPs

Parallelism in Buses and Computational Units Allows:

Single-cycle Execution (with or without SIMD) of: A

Multiply Operation, An ALU Operation, A Dual

Memory Read or Write, and An Instruction Fetch

Transfers Between Memory and Core at up to Four

32-Bit Floating- or Fixed-Point Words per Cycle

Accelerated FFT Butterfly Computation Through a

Multiply with Add and Subtract

4M Bits On-Chip Dual-Ported SRAM for Independent

Access by Core Processor, Host, and DMA

DMA Controller supports:

14 Zero-Overhead DMA Channels for Transfers Between

ADSP-21160N Internal Memory and External Memory,

External Peripherals, Host Processor, Serial Ports, or

Link Ports

The ADSP-21160N introduces Single-Instruction,

Multiple-Data (SIMD) processing. Using two computa-

tional units (ADSP-2106x SHARC DSPs have one), the

ADSP-21160N can double performance versus the

ADSP-2106x on a range of DSP algorithms.

Fabricated in a state of the art, high speed, low power

CMOS process, the ADSP-21160N has a 10.5 ns instruc-

tion cycle time. With its SIMD computational hardware

running at 95 MHz, the ADSP-21160N can perform 570

million math operations per second.

64-Bit Background DMA Transfers at Core Clock Speed,

in Parallel with Full-Speed Processor Execution

665M Bytes/s Transfer Rate Over IOP Bus

Host Processor Interface to 16- and 32-Bit

Microprocessors

Table 1 shows performance benchmarks for the

ADSP-21160N.

4G Word Address Range for Off-Chip Memory

Memory Interface Supports Programmable Wait State

Generation and Page-Mode for Off-Chip Memory

Multiprocessing Support Provides:

Table 1. ADSP-21160N Benchmarks

Benchmark Algorithm

Speed

Glueless Connection for Scalable DSP Multiprocessing

Architecture

Distributed On-Chip Bus Arbitration for Parallel Bus

Connect of up to Six ADSP-21160Ns plus Host

Six Link Ports for Point-To-Point Connectivity and Array

Multiprocessing

Serial Ports Provide:

Two 47.5M Bits/s Synchronous Serial Ports with

Companding Hardware

Independent Transmit and Receive Functions

TDM Support for T1 and E1 Interfaces

64-Bit Wide Synchronous External Port Provides:

Glueless Connection to Asynchronous and SBSRAM

External Memories

1024 Point Complex FFT (Radix 4, with 96 µs

reversal)

FIR Filter (per tap)

IIR Filter (per biquad)

Matrix Multiply (pipelined)

[3

؋

3]

؋

[3

؋

1]

5.25 ns

21 ns

47.25 ns

Matrix Multiply (pipelined)

[4

؋

4]

؋

[4

؋

1]

84 ns

Divide (y/x)

31.5 ns

Inverse Square Root

DMA Transfer Rate

47.25 ns

665M Bytes/s

Thesebenchmarks provide single-channelextrapolationsof

measured dual-channel processing performance. For more

information onbenchmarking andoptimizingDSP codefor

single- and dual-channel processing, see Analog Devices’s

website.

Up to 47.5 MHz Operation

The ADSP-21160N continues SHARC’s industry-leading

standards of integration for DSPs, combining a

high-performance32-bitDSPcorewithintegrated, on-chip

system features. These features include a 4M-bit dual

ported SRAM memory, host processor interface, I/O

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrB

2

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

April 2002

ADSP-21160N

ADSP-21160N Family Core Architecture

processor that supports 14 DMA channels, two serial ports,

six link ports, external parallel bus, and glueless

multiprocessing.

The ADSP-21160N includes the following archi-

tectural features of the ADSP-2116x family core. The

ADSP-21160N is code compatible at the assembly level

with the ADSP-2106x and ADSP-21161.

The functional block diagram on page 1 shows a block

diagram of the ADSP-21160N, illustrating the following

architectural features:

SIMD Computational Engine

The ADSP-21160N contains two computational process-

ing elements that operate as a Single Instruction Multiple

Data (SIMD) engine. The processing elements are referred

to as PEX and PEY, and each contains an ALU, multiplier,

shifter, and register file. PEX is always active, and PEY may

be enabled by setting the PEYEN mode bit in the MODE1

register. When this mode is enabled, the same instruction

isexecutedinbothprocessingelements, buteachprocessing

element operates on different data. This architecture is

efficient at executing math-intensive DSP algorithms.

• Two processing elements, each made up of an ALU, Mul-

tiplier, Shifter, and Data Register File

• Data Address Generators (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting four 32-bit data

transfers between memory and the core every core

processor cycle

• Interval timer

• On-Chip SRAM (4M bits)

• External port that supports:

• Interfacing to off-chip memory peripherals

Entering SIMD mode also has an effect on the way data is

transferred between memory and the processing elements.

When in SIMD mode, twice the data bandwidth is required

to sustain computational operation in the processing

elements. Because of this requirement, entering SIMD

mode also doubles the bandwidth between memory and the

processing elements. When using the DAGs to transfer data

in SIMD mode, two data values are transferred with each

access of memory or the register file.

• Glueless multiprocessing support for six

ADSP-21160N SHARCs

• Host port

• DMA controller

• Serial ports and link ports

• JTAG test access port

Independent, Parallel Computation Units

Figure 1 shows a typical single-processor system. A multi-

processing system appears in Figure 4.

Within each processing element is a set of computational

units. The computational units consist of an arith-

metic/logic unit (ALU), multiplier, and shifter. These units

perform single-cycle instructions. The three units within

each processing element are arranged in parallel, maximiz-

ing computational throughput. Single multifunction

instructions execute parallel ALU and multiplier opera-

tions. In SIMD mode, the parallel ALU and multiplier

operations occur in both processing elements. These com-

putation units support IEEE 32-bit single-precision

floating-point, 40-bit extended precision floating-point,

and 32-bit fixed-point data formats.

ADSP-21160

CLOCK

CLKIN

CS

BMS

BOOT

EPROM

(OPTIONAL)

4

CLK_CFG3–0

EBOOT

ADDR

DATA

CIF

LBOOT

BRST

3

IRQ2–0

ADDR31–0

ADDR

4

FLAG3–0

TIMEXP

MEMORY/

MAPPED

DEVICES

DATA63–0

DATA

OE

RDx

LINK

DEVICES

(6 MAX)

LXCLK

WE

WRx

ACK

(OPTIONAL)

LXACK

ACK

CS

(OPTIONAL)

LXDAT7–0

MS3–0

Data Register File

TCLK0

RCLK0

TFS0

RSF0

DT0

PAGE

SERIAL

DEVICE

(OPTIONAL)

DMA DEVICE

(OPTIONAL)

A general-purpose data register file is contained in each

processing element. The register files transfer data between

the computation units and the data buses, and store inter-

mediate results. These 10-port, 32-register (16 primary, 16

secondary) register files, combined with the ADSP-2116x

enhanced Harvard architecture, allow unconstrained data

flow between computation units and internal memory. The

registers in PEX are referred to as R0–R15 and in PEY

as S0–S15.

SBTS

DATA

CLKOUT

DMAR1–2

DMAG1–2

DR0

TCLK1

RCLK1

TFS1

RSF1

DT1

CS

SERIAL

DEVICE

(OPTIONAL)

HOST

HBR

HBG

PROCESSOR

INTERFACE

(OPTIONAL)

DR1

REDY

BR1–6

PA

RPBA

ID2–0

ADDR

DATA

RESET JTAG

Single-Cycle Fetch of Instruction and Four Operands

The ADSP-21160N features an enhanced Harvard archi-

tecture in which the data memory (DM) bus transfers data,

and the program memory (PM) bus transfers both instruc-

tions and data (seethe functionalblock diagram on page 1).

6

Figure 1. Single-Processor System

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrB

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PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

April 2002

ADSP-21160N

With the ADSP-21160N’s separate program and data

memory buses and on-chip instruction cache, the processor

can simultaneously fetch four operands and an instruction

(from the cache), all in a single cycle.

between the 32-bit floating-point and 16-bit floating-point

formats is done in a single instruction. While each memory

block can store combinations of code and data, accesses are

most efficient when one block stores data, using the DM

bus for transfers, and the other block stores instructions and

data, using the PM bus for transfers. Using the DM bus and

PM bus in this way, with one dedicated to each memory

block, assures single-cycle execution with two data trans-

fers. In this case, the instruction must be available in

the cache.

Instruction Cache

The ADSP-21160N includes an on-chip instruction cache

that enables three-bus operation for fetching an instruction

and four data values. The cache is selective—only the

instructions whose fetches conflict with PM bus data

accesses are cached. This cache allows full-speed execution

of core, providing looped operations such as digital filter

multiply- accumulates and FFT butterfly processing.

Off-Chip Memory and Peripherals Interface

TheADSP-21160N’sexternalportprovidestheprocessor’s

interface to off-chip memory and peripherals. The 4G word

off-chip address space is included in the ADSP-21160N’s

unified address space. The separate on-chip buses—for PM

addresses, PM data, DM addresses, DM data, I/O

addresses, and I/O data—are multiplexed at the external

port to create an external system bus with a single 32-bit

address bus and a single 64-bit data bus. The lower 32 bits

of the external data bus connect to even addresses and the

upper 32 bits of the 64 connect to odd addresses. Every

access to external memory is based on an address that

fetches a 32-bit word, and with the 64-bit bus, two address

locations can be accessed at once. When fetching an instruc-

tion from external memory, two 32-bit data locations are

being accessed (16 bits are unused). Figure 3 shows the

alignment of various accesses to external memory.

Data Address Generators with Hardware

Circular Buffers

The ADSP-21160N’s two data address generators (DAGs)

are used for indirect addressing and provide for implement-

ing circular data buffers in hardware. Circular buffers allow

efficient programming of delay lines and other data struc-

tures required in digital signal processing, and are

commonly used in digital filters and Fourier transforms.

The two DAGs of the ADSP-21160N contain sufficient

registers to allow the creation of up to 32 circular buffers

(16 primary register sets, 16 secondary). The DAGs auto-

matically handle address pointer wraparound, reducing

overhead, increasing performance, and simplifying imple-

mentation. Circular buffers can start and end at any

memory location.

The external port supports asynchronous, synchronous,

and synchronous burst accesses. ZBT synchronous burst

SRAM can be interfaced gluelessly. Addressing of external

memory devices is facilitated by on-chip decoding of

high-order address lines to generate memory bank select

signals. Separate control lines are also generated for simpli-

fied addressing of page-mode DRAM. The ADSP-21160N

provides programmable memory wait states and external

memory acknowledge controls to allow interfacing to

DRAM and peripherals with variable access, hold, and

disable time requirements.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of

parallel operations, for concise programming. For example,

the ADSP-21160N can conditionally execute a multiply, an

add, and subtract, in both processing elements, while

branching, all in a single instruction.

ADSP-21160N Memory and I/O Interface Features

Augmenting the ADSP-2116x family core, the

ADSP-21160N adds the following architectural features:

Dual-Ported On-Chip Memory

DMA Controller

The ADSP-21160N contains four megabits of on-chip

SRAM, organized as two blocks of 2M bits each, which can

be configured for different combinations of code and data

storage. Each memory block is dual-ported for single-cycle,

independent accesses by the core processor and I/O proces-

sor. The dual-ported memory in combination with three

separate on-chip buses allows two data transfers from the

core and one from I/O processor, in a single cycle. On the

ADSP-21160N, the memory can be configured as a

maximum of 128K words of 32-bit data, 256K words of

16-bit data, 85K words of 48-bit instructions (or 40-bit

data), or combinations of different word sizes up to four

megabits. All of the memory can be accessed as 16-bit,

32-bit, 48-bit, or 64-bit words. A 16-bit floating-point

storage format is supported that effectively doubles the

amount of data that may be stored on-chip. Conversion

The ADSP-21160N’s on-chip DMA controller allows

zero-overhead data transfers without processor interven-

tion. The DMA controller operates independently and

invisibly to the processor core, allowing DMA operations to

occurwhilethecoreissimultaneouslyexecutingitsprogram

instructions. DMA transfers can occur between the

ADSP-21160N’s internal memory and external memory,

externalperipherals,orahostprocessor.DMAtransferscan

also occur between the ADSP-21160N’s internal memory

and its serial ports or link ports. External bus packing to

16-, 32-, 48-, or 64-bit words is performed during DMA

transfers. Fourteen channels of DMA are available on the

ADSP-21160N—six via the link ports, four via the serial

ports, and four via the processor’s external port (for either

host processor, other ADSP-21160Ns, memory or I/O

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrB

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PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

April 2002

ADSP-21160N

0x00 0000

0x02 0000

0x04 0000

0x80 0000

IOP Reg’s

DATA63–0

31

Long Word

Internal

Memory

Space

MS₀

63

55

BYTE 7

47

39

23

15

7

0

Normal Word

Bank 0

BYTE 0

0x08 0000

0x10 0000

Short Word

RDL/WRL

RDH/WRH

Internal

64-BIT LONG WORD, SIMD, DMA, IOP REGISTER TRANSFERS

Memory

Space

Bank 1

Bank 2

Bank 3

MS₁

MS₂

MS₃

64-BIT TRANSFER FOR 48-BIT INSTRUCTION FETCH

64-BIT TRANSFER FOR 40-BIT EXTENDED PRECISION

(ID = 001)

0x20 0000

0x30 0000

0x40 0000

0x50 0000

0x60 0000

Internal

Memory

Space

32-BIT NORMAL WORD (EVEN ADDRESS)

32-BIT NORMAL WORD (ODD ADDRESS)

(ID = 010)

RESTRICTED DMA, HOST, EPROM DATA ALIGNMENTS:

Internal

Memory

Space

32-BIT PACKED

16-BIT PACKED

EPROM

(ID = 011)

Multiprocessor

Memory

Space

Internal

Memory

Space

Figure 3. ADSP-21160N External Data Alignment

Options

External

Memory

Space

(ID = 100)

Internal

Memory

ify-write sequences for semaphores. A vector interrupt is

provided for interprocessor commands. Maximum

throughput for interprocessor data transfer is 380M bytes/s

over the external port. Broadcast writes allow simultaneous

transmission of data to all ADSP-21160Ns and can be used

to implement reflective semaphores.

Space

(ID = 101)

Nonbanked

Internal

Memory

Space

(ID = 110)

Six link ports provide for a second method of multiprocess-

ing communications. Each link port can support

communications to another ADSP-21160N. Using the

links, a large multiprocessor system can be constructed in a

2D or 3D fashion. Systems can use the link ports and cluster

multiprocessing concurrently or independently.

0x70 0000

0x7F FFFF

Broadcast

Write to

All DSPs

(ID = 111)

0xFFFF FFFF

Figure 2. ADSP-21160N Memory Map

Link Ports

TheADSP-21160Nfeaturessix8-bitlinkportsthatprovide

additional I/O capabilities. With the capability of running

at 95 MHz rates, each link port can support 95M bytes/s.

Link port I/O is especially useful for point-to-point inter-

processor communication in multiprocessing systems. The

link ports can operate independently and simultaneously.

Link port data is packed into 48- or 32-bit words, and can

be directly read by the core processor or DMA-transferred

to on-chip memory. Each link port has its own double-buff-

ered input and output registers. Clock/acknowledge

handshaking controls link port transfers. Transfers are pro-

grammable as either transmit or receive.

transfers). Programs can be downloaded to the

ADSP-21160N using DMA transfers. Asynchronous

off-chip peripherals can control two DMA channels using

DMA Request/Grant lines (DMAR1–2, DMAG1–2).

Other DMA features include interrupt generation upon

completion of DMA transfers, two-dimensional DMA, and

DMA chaining for automatic linked DMA transfers.

Multiprocessing

The ADSP-21160N offers powerful features tailored to

multiprocessing DSP systems as shown in Figure 4. The

external port and link ports provide integrated glueless mul-

tiprocessing support.

Serial Ports

The external port supports a unified address space (see

Figure 2) that allows direct interprocessor accesses of each

ADSP-21160N’s internal memory. Distributed bus arbitra-

tionlogicisincludedon-chipforsimple,gluelessconnection

of systems containing up to six ADSP-21160Ns and a host

processor. Master processor changeover incurs only one

cycleofoverhead. Busarbitrationisselectableaseitherfixed

or rotating priority. Bus lock allows indivisible read-mod-

The ADSP-21160N features two synchronous serial ports

that provide an inexpensive interface to a wide variety of

digital and mixed-signal peripheral devices. The serial ports

can operate up to half the clock rate of the core, providing

each witha maximum data rate of 47.5M bit/s. Independent

transmit and receive functions provide greater flexibility for

serial communications. Serial port data can be automati-

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrB

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PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

April 2002

ADSP-21160N

synchronization and transmit modes as well as optional

µ-law or A-law companding. Serial port clocks and frame

syncs can be internally or externally generated.

ADSP-21160 #6

ADSP-21160 #5

ADSP-21160 #4

ADSP-21160 #3

ADDR31–0

Host Processor Interface

CLKIN

The ADSP-21160N host interface allows easy connection

to standard microprocessor buses, both 16-bit and 32-bit,

with little additional hardware required. The host interface

is accessed through the ADSP-21160N’s external port and

is memory-mapped into the unified address space. Four

channels of DMA are available for the host interface; code

and data transfers are accomplished with low software

overhead. The host processor communicates with the

ADSP-21160M’s external bus with host bus request

(HBR),hostbutgrant(HBG),ready(REDY),acknowledge

(ACK), and chip select (CS) signals. The host can directly

read and write the internal memory of the ADSP-21160N,

and can access the DMA channel setup and mailbox regis-

ters. Vector interrupt support provides efficient execution

of host commands.

DATA63–0

RESET

RPBA

3

ID2–0

CONTROL

011

PA

5

BR1–2,BR4–6

BR3

ADSP-21160 #2

ADDR31–0

DATA63–0

CLKIN

RESET

RPBA

Program Booting

The internal memory of the ADSP-21160N can be booted

at system power-up from an 8-bit EPROM, a host proces-

sor, or through one of the link ports. Selection of the boot

source is controlled by the BMS (Boot Memory Select),

EBOOT (EPROM Boot), and LBOOT (Link/Host Boot)

pins. 32-bit and 16-bit host processors can be used

for booting.

3

ID2–0

CONTROL

010

PA

BR1,BR3–6

BR2

5

Phased Locked Loop

The ADSP-21160N uses an on-chip PLL to generate the

internal clock for the core. Ratios of 2:1, 3:1, and 4:1

between the core and CLKIN are supported. The

CLK_CFG pins are used to select the ratio. The CLKIN

rate is the rate at which the synchronous external

port operates.

ADSP-21160 #1

CLKIN

ADDR31–0

ADDR

DATA

RESET

GLOBAL MEMORY

AND

PERIPHERAL (OPTIONAL)

DATA63–0

RPBA

RDx

WRx

OE

WE

ACK

CS

3

ACK

MS3–0

Power Supplies

ID2–0

The ADSP-21160N has separate power supply connections

for the internal (V_DDINT), external (V_DDEXT), and analog

(AV_DD/AGND) power supplies. The internal and analog

supplies must meet the 1.9 V requirement. The external

supplymustmeetthe3.3 Vrequirement.Allexternalsupply

pins must be connected to the same supply.

BMS

PAGE

CS

001

BOOT EPROM(OPTIONAL)

ADDR

SBTS

DATA

CLKOUT

CS

HBR

RESET

CLOCK

HBG

HOST PROCESSOR

INTERFACE (OPTIONAL)

The PLL Filter Figure 5 on page 7 must be added for each

ADSP-21160N in the system. VDDint is the digital core

supply. It is recommended that the capacitors be connected

directly to AGND using short thick trace. It is recom-

mended that the capacitors be placed as close to AVDD and

AGND as possible. The connection from AGND to the

(digital) ground plane should be made after the capacitors.

The use of a thick trace for AGND is reasonable only

because the PLL is a relatively low power circuit - it does

not apply to any other ADSP-21160N GND connection.

REDY

ADDR

DATA

PA

BR2–6

BR1

5

Figure 4. Shared Memory Multiprocessing System

cally transferred to and from on-chip memory via a

dedicated DMA. Each of the serial ports offers a TDM

multichannel mode. The serial ports can operate with lit-

tle-endian or big-endian transmission formats, with word

lengthsselectablefrom3bitsto32bits.Theyofferselectable

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrB

6

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

April 2002

ADSP-21160N

oftheADSP-2116xdevelopmenttools,includingthesyntax

highlighting in the VisualDSP++ editor. This capability

permits:

10⍀

V_DDINT

AV_DD

0.1␮F

0.01␮F

• Control how the development tools process inputs and

generate outputs.

AGND

• Maintain a one-to-one correspondence with the tool’s

command line switches.

Figure 5. Analog Power (AV_DD) Filter Circuit

Development Tools

AnalogDevices’DSPemulatorsusetheIEEE1149.1JTAG

test access port of the ADSP-21160N processor to monitor

and control the target board processor during emulation.

The emulator provides full-speed emulation, allowing

inspection and modification of memory, registers, and

processor stacks. Nonintrusive in-circuit emulation is

assured by the use of the processor’s JTAG interface—the

emulator does not affect target system loading or timing.

The ADSP-21160N is supported with a complete set of

softwareandhardwaredevelopmenttools,includingAnalog

Devices’ emulators and VisualDSP++¹development envi-

ronment. The same emulator hardware that supports other

ADSP-2116x DSPs, also fully emulates the

ADSP-21160N.

The VisualDSP++ project management environment lets

programmers develop and debug an application. This envi-

ronment includes an easy-to-use assembler that is based on

an algebraic syntax; an archiver (librarian/library builder),

a linker, a loader, a cycle-accurate instruction-level simula-

tor, a C/C++ compiler, and a C/C++ run-time library that

includes DSP and mathematical functions. Two key points

for these tools are:

In addition to the software and hardware development tools

available from Analog Devices, third parties provide a wide

range of tools supporting the ADSP-2116x processor

family. Hardware tools include ADSP-2116x PC plug-in

cards. Third Party software tools include DSP libraries,

real-time operating systems, and block diagram

design tools.

• Compiled ADSP-2116x C/C++ code efficiency—the

compiler has been developed for efficient translation of

C/C++ code to ADSP-2116x assembly. The DSP has

architectural features that improve the efficiency of

compiled C/C++ code.

Designing an Emulator-Compatible DSP Board

(Target)

The White Mountain DSP (Product Line of Analog

Devices, Inc.) family of emulators are tools that every DSP

developer needs to test and debug hardware and software

systems. Analog Devices has supplied an IEEE 1149.1

JTAG Test Access Port (TAP) on each JTAG DSP. The

emulator uses the TAP to access the internal features of the

DSP, allowing the developer to load code, set breakpoints,

observe variables, observe memory, and examine registers.

The DSP must be halted to send data and commands, but

once an operation has been completed by the emulator, the

DSP system is set running at full speed with no impact on

system timing.

• ADSP-2106x family code compatibility—The assembler

has legacy features to ease the conversion of existing

ADSP-2106x applications to the ADSP-2116x.

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved

source and object information)

• Insert break points

• Set conditional breakpoints on registers, memory, and

stacks

To use these emulators, the target’s design must include the

interface between an Analog Devices’ JTAG DSP and the

emulation header on a custom DSP target board.

• Trace instruction execution

• Perform linear or statistical profiling of program

execution

Target Board Header

The emulator interface to an Analog Devices’ JTAG DSP

isa14-pinheader, asshowninFigure 6. Thecustomermust

supply this header on the target board in order to commu-

nicate with the emulator. The interface consists of a

standard dual row 0.025" square post header, set on

0.1"

؋

0.1" spacing, with a minimum post length of 0.235".

Pin 3 is the key position used to prevent the pod from being

inserted backwards. This pin must be clipped on the

target board.

• Fill, dump, and graphically plot the contents of memory

• Source level debugging

• Create custom debugger windows

The VisualDSP++ IDE lets programmers define and

manage DSP software development. Its dialog boxes and

property pages let programmers configure and manage all

¹VisualDSP++ is a registered trademark of Analog Devices, Inc.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrB

7

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

April 2002

ADSP-21160N

Also, the clearance (length, width, and height) around the

header must be considered. Leave a clearance of at least

0.15" and 0.10" around the length and width of the header,

and reserve a height clearance to attach and detach the pod

connector.

1

3

5

2

4

6

EMU

GND

TMS

GND

KEY (NO PIN)

BTMS

7

9

8

1

3

5

2

4

6

EMU

BTCK

TCK

GND

10

12

BTRST

TRST

KEY (NO PIN)

GND

TMS

9

11

BTDI

GND

TDI

BTMS

7

9

8

13

14

TDO

BTCK

TCK

10

12

BTRST

TRST

TOP VIEW

9

11

Figure 7. JTAG Target Board Connector with No Local

Boundary Scan

BTDI

GND

TDI

13

14

TDO

TOP VIEW

Figure 6. JTAG Target Board Connector for JTAG

Equipped Analog Devices DSP (Jumpers in

Place)

0.64"

As can be seen in Figure 6, there are two sets of signals on

the header. There are the standard JTAG signals TMS,

TCK, TDI, TDO, TRST, and EMU used for emulation

purposes (via an emulator). There are also secondary JTAG

signals BTMS, BTCK, BTDI, and BTRST that are option-

ally used for board-level (boundary scan) testing.

0.24"

0.88"

Figure 8. JTAG Pod Connector Dimensions

When the emulator is not connected to this header, place

jumpers across BTMS, BTCK, BTRST, and BTDI as

shown in Figure 7. This holds the JTAG signals in the

correct state to allow the DSP to run free. Remove all the

jumpers when connecting the emulator to the JTAG header.

0.10"

0.15"

JTAG Emulator Pod Connector

Figure 8 details the dimensions of the JTAG pod connector

at the 14-pin target end. Figure 9 displays the keep-out area

for a target board header. The keep-out area allows the pod

connector to properly seat onto the target board header.

This board area should contain no components (chips,

resistors, capacitors, etc.). The dimensions are referenced

to the center of the 0.25" square post pin.

Figure 9. JTAG Pod Connector Keep-Out Area

“EE-68” (www.analog.com). This document is updated

regularly to keep pace with improvements to emulator

support.

Additional Information

This data sheet provides a general overview of the

ADSP-21160N architecture and functionality. For detailed

information on the ADSP-2116x Family core architecture

and instruction set, refer to the ADSP-2116x SHARC DSP

Hardware Reference.

Design-for-Emulation Circuit Information

For details on target board design issues including: single

processor connections, multiprocessor scan chains, signal

buffering, signal termination, and emulator pod logic, see

the EE-68: Analog Devices JTAG Emulation Technical

Reference on the Analog Devices website—use site search on

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrB

8

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

April 2002

ADSP-21160N

PIN FUNCTION DESCRIPTIONS

• LxCLK, LxACK, LxDAT7–0 (LxPDRDE = 0) (NOTE:

See Link Port Buffer Control Register Bit definitions in

the ADSP-21160 DSP Hardware Reference).

ADSP-21160N pin definitions are listed below. Inputs iden-

tified as synchronous (S) must meet timing requirements

with respect to CLKIN (or with respect to TCK for TMS,

TDI). Inputsidentifiedasasynchronous(A)canbeasserted

asynchronously to CLKIN (or to TCK for TRST).

• DTx, DRx, TCLKx, RCLKx, EMU, TMS, TRST, TDI

(NOTE: These pins have a pull-up.)

The following symbols appear in the Type column of

Table 2: A = Asynchronous, G = Ground, I = Input,

O = Output, P = Power Supply, S = Synchronous,

(A/D) = Active Drive, (O/D) = Open Drain, and

T = Three-State (when SBTS is asserted, or when the

ADSP-21160N is a bus slave).

Tie or pull unused inputs to VDD or GND, except for the

following:

• ADDR31–0, DATA63–0, PAGE, BRST, CLKOUT

(ID2–0=00x)(NOTE:Thesepinshavealogic-levelhold

circuit enabled on the ADSP-21160N DSP with ID2–0

= 00x)

• PA, ACK, MS3–0, RDx, WRx, CIF, DMARx, DMAGx

(ID2–0 = 00x) (NOTE: These pins have a pull-up

enabled on the ADSP-21160N DSP with ID2–0 = 00x)

Table 2. Pin Function Descriptions

Type

Function

ADDR31–0

I/O/T

External Bus Address. The ADSP-21160N outputs addresses for external memory and

peripherals on these pins. In a multiprocessor system, the bus master outputs addresses

for read/writes of the internal memory or IOP registers of other ADSP-21160Ns. The

ADSP-21160N inputs addresses when a host processor or multiprocessing bus master

is reading or writing its internal memory or IOP registers. A keeper latch on the DSP’s

ADDR31–0 pins maintains the input at the level it was last driven (only enabled on the

ADSP-21160N with ID2–0 = 00x).

DATA63–0

I/O/T

O/T

External Bus Data. The ADSP-21160N inputs and outputs data and instructions on

these pins. Pull-up resistors on unused DATA pins are not necessary. A keeper latch on

theDSP’s DATA63-0 pinsmaintainstheinputatthelevelitwaslastdriven(onlyenabled

on the ADSP-21160N with ID2–0 = 00x).

Memory Select Lines. These outputs are asserted (low) as chip selects for the corre-

sponding banks of external memory. Memory bank size must be defined in the SYSCON

control register. The MS3–0 outputs are decoded memory address lines. In asyn-

chronous access mode, the MS3–0 outputs transition with the other address outputs.

In synchronous access modes, the MS3–0 outputs assert with the other address lines;

however, they de-assert after the first CLKIN cycle in which ACK is sampled asserted.

MS3–0 has a 20kΩ internal pull-up resistor that is enabled on the ADSP-21160N with

ID2–0 = 00x.

MS3–0

RDL

RDH

WRL

I/O/T

Memory Read Low Strobe. RDL is asserted whenever ADSP-21160N reads from the

low word of external memory or from the internal memory of other ADSP-21160Ns.

External devices, including other ADSP-21160Ns, must assert RDL for reading from

the low word of ADSP-21160N internal memory. In a multiprocessing system, RDL is

driven by the bus master. RDL has a 20kΩ internal pull-up resistor that is enabled on

the ADSP-21160N with ID2–0 = 00x.

Memory Read High Strobe. RDH is asserted whenever ADSP-21160N reads from the

high word of external memory or from the internal memory of other ADSP-21160Ns.

External devices, including other ADSP-21160Ns, must assert RDH for reading from

the high word of ADSP-21160N internal memory. In a multiprocessing system, RDH

is driven by the bus master. RDH has a 20kΩ internal pull-up resistor that is enabled

on the ADSP-21160N with ID2–0 = 00x.

Memory Write Low Strobe. WRL is asserted when ADSP-21160N writes to the low

wordofexternalmemoryorinternalmemoryofotherADSP-21160Ns. Externaldevices

must assert WRL for writing to ADSP-21160N’s low word of internal memory. In a

multiprocessing system, WRL is driven by the bus master. WRL has a 20kΩ internal

pull-up resistor that is enabled on the ADSP-21160N with ID2–0 = 00x.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrB

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PRELIMINARY TECHNICAL DATA

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ADSP-21160N

Table 2. Pin Function Descriptions (Continued)

Type

Function

WRH

I/O/T

Memory Write High Strobe. WRH is asserted when ADSP-21160N writes to the high

wordofexternalmemoryorinternalmemoryofotherADSP-21160Ns. Externaldevices

must assert WRH for writing to ADSP-21160N’s high word of internal memory. In a

multiprocessing system, WRH is driven by the bus master. WRH has a 20kΩ internal

pull-up resistor that is enabled on the ADSP-21160N with ID2–0 = 00x.

PAGE

BRST

O/T

DRAM Page Boundary. The ADSP-21160N asserts this pin to signal that an external

DRAM page boundary has been crossed. DRAM page size must be defined in the

ADSP-21160N’s memory control register (WAIT). DRAM can only be implemented

in external memory Bank 0; the PAGE signal can only be activated for Bank 0 accesses.

In a multiprocessing system PAGE is output by the bus master. A keeper latch on the

DSP’s PAGE pin maintains the output at the level it was last driven (only enabled on

the ADSP-21160N with ID2–0 = 00x).

I/O/T

Sequential Burst Access. BRST is asserted by ADSP-21160N or a host to indicate that

data associated with consecutive addresses is being read or written. A slave device

samples the initial address and increments an internal address counter after each

transfer. The incremented address is not pipelined on the bus. If the burst access is a

read from host to ADSP-21160N, ADSP-21160N automaticallyincrements the address

as long as BRST is asserted. BRST is asserted after the initial access of a burst transfer.

It is asserted for every cycle after that, except for the last data request cycle (denoted by

RDx or WRx asserted and BRST negated). A keeper latch on the DSP’s BRST pin

maintains the input at the level it was last driven (only enabled on the ADSP-21160N

with ID2–0 = 00x).

ACK

I/O/S

I/S

Memory Acknowledge. External devices can de-assert ACK (low) to add wait states to

an external memory access. ACK is used by I/O devices, memory controllers, or other

peripherals to hold off completion of an external memory access. The ADSP-21160N

deasserts ACK as an output to add wait states to a synchronous access of its internal

memory. ACK has a 2kΩ internal pull-up resistor that is enabled on the ADSP-21160N

with ID2–0 = 00x.

Suspend Bus and Three-State. External devices can assert SBTS (low) to place the

externalbusaddress, data, selects, andstrobesinahighimpedancestateforthefollowing

cycle. If the ADSP-21160N attempts to access external memory while SBTS is asserted,

the processor will halt and the memory access will not be completed until SBTS is

deasserted. SBTS should only be used to recover from host processor and/or

ADSP-21160N deadlock or used with a DRAM controller.

SBTS

IRQ2–0

FLAG3–0

TIMEXP

HBR

I/A

I/O/A

O

Interrupt Request Lines. These are sampled on the rising edge of CLKIN and may be

either edge-triggered or level-sensitive.

Flag Pins. Each is configured via control bits as either an input or output. As an input,

it can be tested as a condition. As an output, it can be used to signal external peripherals.

Timer Expired. Asserted for four Core Clock cycles when the timer is enabled and

TCOUNT decrements to zero.

Host Bus Request. Must be asserted by a host processor to request control of the

ADSP-21160N’s external bus. When HBR is asserted in a multiprocessing system, the

ADSP-21160N that is bus master will relinquish the bus and assert HBG. To relinquish

the bus, the ADSP-21160N places the address, data, select, and strobe lines in a high

impedance state. HBR has priority over all ADSP-21160N bus requests (BR6–1) in a

multiprocessing system.

I/A

HBG

I/O

I/A

Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor

may take control of the external bus. HBG is asserted (held low) by the ADSP-21160N

until HBR is released. In a multiprocessing system, HBG is output by the

ADSP-21160N bus master and is monitored by all others. After HBR is asserted, and

before HBG is given, HBG will float for 1 tCLK (1 CLKIN cycle). To avoid erroneous

grants, HBG should be pulled up with a 20k to 50k ohm external resistor.

Chip Select. Asserted by host processor to select the ADSP-21160N.

CS

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrB

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PRELIMINARY TECHNICAL DATA

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ADSP-21160N

Table 2. Pin Function Descriptions (Continued)

Type

Function

REDY

O (O/D)

Host Bus Acknowledge. The ADSP-21160N deasserts REDY (low) to add waitstates

to a host access when CS and HBR inputs are asserted.

DMAR1

DMAR2

I/A

DMA Request 1 (DMA Channel 11). Asserted by external port devices to request DMA

services. DMAR1 has a 20kΩ internal pull-up resistor that is enabled on the

ADSP-21160N with ID2–0 = 00x.

DMA Request 2 (DMA Channel 12). Asserted by external port devices to request DMA

services. DMAR2 has a 20kΩ internal pull-up resistor that is enabled on the

ADSP-21160N with ID2–0 = 00x.

ID2–0

I

Multiprocessing ID. Determines which multiprocessing bus request (BR1–BR6) is used

by ADSP-21160N. ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, and

so on. Use ID = 000 or ID = 001 in single-processor systems. These lines are a system

configuration selection which should be hardwired or only changed at reset.

DMAG1

O/T

DMA Grant 1 (DMA Channel 11). Asserted by ADSP-21160N to indicate that the

requested DMA starts on the next cycle. Driven by bus master only. DMAG1 has a

20kΩ internal pull-up resistor that is enabled on the ADSP-21160N with ID2–0 = 00x.

DMAG2

BR6–1

O/T

DMA Grant 2 (DMA Channel 12). Asserted by ADSP-21160N to indicate that the

requested DMA starts on the next cycle. Driven by bus master only. DMAG2 has a

20kΩ internal pull-up resistor that is enabled on the ADSP-21160N with ID2–0 = 00x.

Multiprocessing Bus Requests. Used by multiprocessing ADSP-21160Ns to arbitrate

for bus mastership. An ADSP-21160N only drives its own BRx line (corresponding to

the value of its ID2–0 inputs) and monitors all others. In a multiprocessor system with

lessthansixADSP-21160Ns,theunusedBRx pinsshouldbepulledhigh;theprocessor’s

own BRx line must not be pulled high or low because it is an output.

I/O/S

RPBA

I/S

Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for

multiprocessor bus arbitration is selected. When RPBA is low, fixed priority is selected.

This signal is a system configuration selection which must be set to the same value on

every ADSP-21160N. If the value of RPBA is changed during system operation, it must

be changed in the same CLKIN cycle on every ADSP-21160N.

PA

I/O/T

Priority Access. Asserting its PA pin allows an ADSP-21160N bus slave to interrupt

background DMA transfers and gain access to the external bus. PA is connected to all

ADSP-21160Ns in the system. If access priority is not required in a system, the PA pin

should be left unconnected. PA has a 20kΩ internal pull-up resistor that is enabled on

the ADSP-21160N with ID2–0 = 00x.

DTx

DRx

TCLKx

RCLKx

TFSx

O

I

Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 kΩ internal pull-up resistor.

Data Receive (Serial Ports 0, 1). Each DR pin has a 50 kΩ internal pull-up resistor.

Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 kΩ internalpull-up resistor.

Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 kΩ internal pull-up resistor.

Transmit Frame Sync (Serial Ports 0, 1).

I/O

RFSx

LxDAT7–0

Receive Frame Sync (Serial Ports 0, 1).

Link Port Data (Link Ports 0–5). Each LxDAT pin has a 50 kΩ internal pull-down

resistor that is enabled or disabled by the LPDRD bit of the LCTL0–1 register.

Link Port Clock (Link Ports 0–5). Each LxCLK pin has a 50 kΩ internal pull-down

resistor that is enabled or disabled by the LPDRD bit of the LCTL0–1 register.

Link Port Acknowledge (Link Ports 0–5). Each LxACK pin has a 50 kΩ internal

pull-down resistor that is enabled or disabled by the LPDRD bit of the LCOM register.

EPROM Boot Select. For a description of how this pin operates, see Table 3. This signal

is a system configuration selection that should be hardwired.

Link Boot. For a description of how this pin operates, see Table 3. This signal is a system

configuration selection that should be hardwired.

Boot Memory Select. Serves as an output or input as selected with the EBOOT and

LBOOT pins; see Table 3. This input is a system configuration selection that should be

hardwired.

LxCLK

LxACK

EBOOT

LBOOT

BMS

I/O

I

I/O/T

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrB

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ADSP-21160N

Table 2. Pin Function Descriptions (Continued)

Type

Function

CLKIN

I

Local ClockIn. CLKIN isthe ADSP-21160N clockinput. The ADSP-21160N external

port cycles at the frequency of CLKIN. The instruction cycle rate is a multiple of the

CLKIN frequency; it is programmable at power-up. CLKIN may not be halted,

changed, or operated below the specified frequency.

CLK_CFG3–0

I

Core/CLKIN Ratio Control. ADSP-21160N core clock (instruction cycle) rate is equal

to n

؋

CLKIN where n is user-selectable to 2, 3, or 4, using the CLK_CFG3–0 inputs.

For clock configuration definitions, see the RESET & CLKIN section of the System

Design chapter of the ADSP-21160 SHARC DSP Hardware Reference manual.

CLKOUT

O/T

I/A

CLKOUT is driven at the CLKIN frequency by the ADSP-21160N. This output can

be three-stated by setting the COD bit in the SYSCON register. A keeper latch on the

DSP’s CLKOUT pin maintains the output at the level it was last driven (only enabled

on the ADSP-21160N with ID2-0 = 00x).

Processor Reset. Resets the ADSP-21160N to a known state and begins execution at

the program memory location specified by the hardware reset vector address. The

RESET input must be asserted (low) at power-up.

RESET

TCK

TMS

I

I/S

Test Clock (JTAG). Provides a clock for JTAG boundary scan.

Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kΩ

internal pull-up resistor.

TDI

I/S

Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a

20 kΩ internal pull-up resistor.

TDO

TRST

O

I/A

Test Data Output (JTAG). Serial scan output of the boundary scan path.

Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)

after power-up or held low for proper operation of the ADSP-21160N. TRST has a

20 kΩ internal pull-up resistor.

EMU

CIF

O (O/D)

O/T

Emulation Status. Must be connected to the ADSP-21160N emulator target board

connector only. EMU has a 50 kΩ internal pull-up resistor.

Core Instruction Fetch. Signal is active low when an external instruction fetch is

performed. Driven by bus master only. Three-state when host is bus master. CIF has a

20kΩ internal pull-up resistor that is enabled on the ADSP-21160N with ID2–0 = 00x.

Core Power Supply. Nominally 1.9 V dc and supplies the DSP’s core processor

(40 pins).

V_DDINT

P

V_DDEXT

AV_DD

P

I/O Power Supply. Nominally 3.3 V dc (43 pins).

Analog Power Supply. Nominally 1.9 V dc and supplies the DSP’s internal PLL (clock

generator). This pin has the same specifications as V_DDINT, except that added filtering

circuitry is required. For more information, see Power Supplies on page 6.

Analog Power Supply Return.

Power Supply Return. (82 pins)

Do Not Connect. Reserved pins that must be left open and unconnected (9 pins).

AGND

GND

NC

G

Table 3. Boot Mode Selection

EBOOT LBOOT BMS

Booting Mode

1

0

1

0

1

0

1

Output

EPROM (Connect BMS to EPROM chip select.)

Host Processor

Link Port

No Booting. Processor executes from external memory.

Reserved

1 (Input)

0 (Input)

x (Input)

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrB

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PRELIMINARY TECHNICAL DATA

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ADSP-21160N

ADSP-21160N SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

C Grade

K Grade

Signal

Parameter¹

Min

Max

Min

Max

Unit

V_DDINT

AV_DD

V_DDEXT

T_CASE

V_IH1

Internal (Core) Supply Voltage

Analog (PLL) Supply Voltage

1.8

3.13

–40

2.2

2.0

3.47

+100

V_DDEXT+0.5

0.8

1.8

3.13 3.47

2.0

V

ºC

V

External (I/O) Supply Voltage

Case Operating Temperature²

0

85

High Level Input Voltage³, @ V_DDEXT=Max

High Level Input Voltage⁴, @ V_DDEXT=Max

Low Level Input Voltage^3,4, @ V_DDEXT=Min

2.2

2.3

–0.5

V_DDEXT+0.5

0.8

V_IH2

V_IL

2.3

–0.5

1

Specifications subject to change without notice.

²See Environmental Conditions on page 48 for information on thermal specifications.

³Applies to input and bidirectional pins: DATA63–0, ADDR31–0, RDx, WRx, ACK, SBTS, IRQ2–0, FLAG3–0, HBG, CS, DMAR1, DMAR2, BR6–1,

ID2–0, RPBA, PA, BRST, TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1,

TCLK0, TCLK1, RCLK0, RCLK1.

⁴Applies to input pins: CLKIN, RESET, TRST.

ELECTRICAL CHARACTERISTICS

C and K Grades

Parameter¹

Test Conditions

Min

Max

Unit

V_OH

V_OL

I_IH

High Level Output Voltage²

Low Level Output Voltage²

High Level Input Current^4,5,6

Low Level Input Current⁴

@ V_DDEXT=Min, I_OH=–2.0 mA³

@ V_DDEXT=Min, I_OL=4.0 mA³

@ V_DDEXT=Max, V_IN=V_DDMax

@ V_DDEXT=Max, V_IN=0 V

2.4

V

0.4

10

250

500

10

µA

I_IL

I_ILPU1

I_ILPU2

I_OZH

I_OZL

I_OZHPD

Low Level Input Current Pull-Up1⁵@ V_DDEXT=Max, V_IN=0 V

Low Level Input Current Pull-Up2⁶@ V_DDEXT=Max, V_IN=0 V

Three-State Leakage Current^7,8,9,10@ V_DDEXT=Max, V_IN=V_DDMax

Three-State Leakage Current⁷

Three-State Leakage Current

Pull-Down¹⁰

@ V_DDEXT=Max, V_IN=0 V

@ V_DDEXT=Max, V_IN=V_DDMax

10

250

I_OZLPU1

I_OZLPU2

Three-State Leakage Current

@ V_DDEXT=Max, V_IN=0 V

250

500

µA

Pull-Up1⁸

Three-State Leakage Current

Pull-Up2⁹

I_OZHA

I_OZLA

Three-State Leakage Current¹¹

Supply Current (Internal)¹²

Supply Current (Internal)¹³

Supply Current (Internal)¹⁴

Supply Current (Idle)¹⁵

Supply Current (Analog)¹⁶

Input Capacitance^17,18

@ V_DDEXT=Max, V_IN=V_DDMax

@ V_DDEXT=Max, V_IN=0 V

t_CCLK=10.5 ns, V_DDINT=Max

@AV_DD=Max

25

4

µA

mA

pF

I_DD-INPEAK

I_DD-INHIGH

I_DD-INLOW

I_DD-IDLE

AI_DD

1400

875

625

400

10

C_IN

f_IN=1 MHz, T_CASE=25°C,

V_IN=2.5 V

4.7

1

Specifications subject to change without notice.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

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ADSP-21160N

²Applies to output and bidirectional pins: DATA63–0, ADDR31–0, MS3–0, RDx, WRx, PAGE, CLKOUT, ACK, FLAG3–0, TIMEXP, HBG, REDY,

DMAG1, DMAG2, BR6–1, PA, BRST, CIF, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK,

LxACK, BMS, TDO, EMU.

³See Output Drive Currents on page 46 for typical drive current capabilities.

⁴Applies to input pins: SBTS, IRQ2–0, HBR, CS, ID2–0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK, CLK_CFG3-0.

⁵Applies to input pins with internal pull-ups: DR0, DR1.

⁶Applies to input pins with internal pull-ups: DMARx, TMS, TDI, TRST.

⁷Applies to three-statable pins: DATA63–0, ADDR31–0, PAGE, CLKOUT, ACK, FLAG3–0, REDY, HBG, BMS, BR6–1, TFSx, RFSx, TDO.

⁸Applies to three-statable pins with internal pull-ups: DTx, TCLKx, RCLKx, EMU.

⁹Applies to three-statable pins with internal pull-ups: MS3–0, RDx, WRx, DMAGx, PA, CIF.

¹⁰Applies to three-statable pins with internal pull-downs: LxDAT7–0, LxCLK, LxACK.

¹¹Applies to ACK pulled up internally with 2 kΩ during reset or ID2–0 = 00x.

¹²The test program used to measure I_DD-INPEAKrepresents worst case processor operation and is not sustainable under normal application conditions. Actual

internal power measurements made using typical applications are less than specified. For more information, see Power Dissipation on page 46.

13

I

is a composite average based on a range of high activity code. For more information, see Power Dissipation on page 46.

is a composite average based on a range of low activity code. For more information, see Power Dissipation on page 46.

DDINHIGH

14

DDINLOW

¹⁵Idle denotes ADSP-21160N state during execution of IDLE instruction. For more information, see Power Dissipation on page 46.

¹⁶Characterized, but not tested.

¹⁷Applies to all signal pins.

¹⁸Guaranteed, but not tested.

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PRELIMINARY TECHNICAL DATA

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ADSP-21160N

ABSOLUTE MAXIMUM RATINGS

1

Internal (Core) Supply Voltage (V_DDINT

) . . –0.3 V to +2.3 V

Analog (PLL) Supply Voltage (A_VDD) . . . . . –0.3 V to +2.3 V

External (I/O) Supply Voltage (V_DDEXT). . . . –0.3 V to +4.6 V

Input Voltage . . . . . . . . . . . . . . . . . –0.5 V to V_DDEXT+0.5 V

Output Voltage Swing . . . . . . . . . . . –0.5 V to V_DDEXT+0.5 V

Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF

Junction Temperature under Bias . . . . . . . . . . . . . . .130ºC

Storage Temperature Range. . . . . . . . . . . –65ºC to +150ºC

¹Stresses greater than those listed above may cause permanent damage to the device.

These are stress ratings only. Functional operation of the device at these or any

other conditions greater than those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

ESD SENSITIVITY

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V

readily accumulate on the human body and test equipment and can discharge without

detection. Although the ADSP-21160N features proprietary ESD protection circuitry,

permanent damage may occur on devices subjected to high-energy electrostatic

discharges. Therefore, proper ESD precautions are recommended to avoid perfor-

mance degradation or loss of functionality.

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ADSP-21160N

Switching Characteristics specify how the processor

Timing Specifications

changes its signals. Circuitry external to the processor must

be designed for compatibility with these signal characteris-

tics. Switching characteristics describe what the processor

will do in a given circumstance. Use switching characteris-

tics to ensure that any timing requirement of a device

connected to the processor (such as memory) is satisfied.

The ADSP-21160N’s internal clock switches at higher fre-

quenciesthanthesysteminputclock(CLKIN). Togenerate

the internal clock, the DSP uses an internal phase-locked

loop (PLL). This PLL-based clocking minimizes the skew

between the system clock (CLKIN) signal and the DSP’s

internal clock (the clock source for the external port logic

and I/O pads).

Timing Requirements apply to signals that are controlled

by circuitry external to the processor, such as the data input

for a read operation. Timing requirements guarantee that

the processor operates correctly with other devices.

The ADSP-21160N’s internal clock (a multiple of CLKIN)

provides the clock signal for timing internal memory,

processor core, link ports, serial ports, and external port (as

required for read/write strobes in asynchronous access

mode). During reset, program the ratio between the DSP’s

internal clock frequency and external (CLKIN) clock

frequency with the CLK_CFG3–0 pins. Even though the

internal clock is the clock source for the external port, the

external port clock always switches at the CLKIN fre-

quency. To determine switching frequencies for the serial

and link ports, divide down the internal clock, using the

programmable divider control of each port (TDIVx/RDIVx

for the serial ports and LxCLKD1–0 for the link ports).

During processor reset (RESET pin low) or software reset

(SRST bit in SYSCON register = 1), de-assertion (MS3-0,

HBG, DMAGx, RDx, WRx, CIF, PAGE, BRST) and

three-state (FLAG3-0, LxCLK, LxACK, LxDAT7-0,

ACK, REDY, PA, TFSx, RFSx, TCLKx, RCLKx, DTx,

BMS, TDO, EMU, DATA) timings differ. These occur

asynchronously to CLKIN, and may not meet the specifi-

cations published in the Timing Requirements and

Switching Characteristics tables. The maximum delay for

de-assertion and three-state is one t_CKfrom RESET pin

assertion low or setting the SRST bit in SYSCON. During

reset the DSP will not respond to SBTS, HBR and MMS

accesses. HBR asserted before reset will be recognized, but

a HBG will not be returned by the DSP until after reset is

de-asserted and the DSP has completed bus

Note the following definitions of various clock periods that

are a function of CLKIN and the appropriate ratio control:

• t_CCLK= (t_CK) / CR

• t_LCLK= (t_CCLK)

؋

LR

synchronization.

• t_SCLK= (t_CCLK)

؋

SR

Where:

• LCLK = Link Port Clock

• SCLK = Serial Port Clock

• t_CK= CLKIN Clock Period

• t_CCLK= (Processor) Core Clock Period

• t_LCLK= Link Port Clock Period

• t_SCLK= Serial Port Clock Period

• CR = Core/CLKIN Ratio (2, 3, or 4:1,

determined by CLK_CFG3–0 at reset)

• LR = Link Port/Core Clock Ratio (1, 2, 3, or 4:1,

determined by LxCLKD)

• SR = Serial Port/Core Clock Ratio (wide range,

determined by

؋

CLKDIV)

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of

others. While addition or subtraction would yield meaning-

ful results for an individual device, the values given in this

data sheet reflect statistical variations and worst cases. Con-

sequently, it is not meaningful to add parameters to derive

longer times.

See Figure 34 under Test Conditions for voltage reference

levels.

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ADSP-21160N

3.3V power supplies protects the ADSP-21160N from

partially powering the 3.3V supply. Including a Schottky

diode will shorten the delay between the supply ramps and

thus prevent damage to the ESD diode protection circuitry.

With this technique, if the 1.9V rail rises ahead of the 3.3V

rail, the Schottky diode pulls the 3.3V rail along with the

1.9V rail.

Power-up Sequencing

During the power up sequence of the DSP, differences in

therampupratesandactivationtimebetweenthetwopower

supplies can cause current toflow in the I/O ESDprotection

circuitry. To prevent this damage to the ESD diode protec-

tion circuitry, Analog Devices, Inc. recommends including

a bootstrap Schottky diode (see Figure 11 on page 18. The

bootstrap Schottky diode connected between the 1.9V and

Table 4. Power-up Sequencing

Parameter

Min

Max

Unit

Timing Requirements:

t_RSTVDD

t_IVDDEVDD

t_CLKVDD

t_CLKRST

t_PLLRST

RESET low before V_DDINT/V_DDEXTon

V_DDINTon before V_DDEXT

CLKIN running after valid V_DDINT/V_DDEXT

CLKIN valid before RESET de-asserted

PLL control setup before RESET de-asserted

0

ns

-50

0

200

ms

µs

1

200²

10³

TBD⁴

ms

Switching Characteristics:

t_CORERSTDSP core reset de-asserted after RESET de-asserted

4,5

4096*t_CK

ms

¹Valid V_DDINT/V_DDEXTassumes that the supplies are fully ramped to their 1.9 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds

of milliseconds, depending on the design of the power supply subsystem.

²CLKIN should be driven coincident with power-up to avoid an undefined state in internal gates, which may cause excess current flow.

³Assumes a stable CLKIN signal after meeting worst case start up timing of oscillators. Refer to your oscillator manufacturer’s data sheet for start up time.

⁴Based on CLKIN cycles.

⁵CORERST is an internal signal only. The 4096 cycle count is dependent on t_SRSTspecification. If setup time is not met, one additional CLKIN cycle may

be added to the core reset time, resulting in 4097 cycles maximum.

RESET

t_RSTVDD

VDDINT

t_IVDDEVDD

VDDEXT

t_CLKVDD

CLKIN

t_CLKRST

CLK_CFG3-0

t_PLLRST

t_CORERST

CORERST

Figure 10. Power-up Sequencing

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ADSP-21160N

3.3V I/O

VOLTAGE REGULATOR

V

DDEXT

ADSP-21160

1.9V CORE

VOLTAGE REGULATOR

V

DDINT

Figure 11. Dual Voltage Schottky Diode

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ADSP-21160N

Clock Input

Table 5. Clock Input

95 MHz

Parameter

Min

Max

Unit

Timing Requirements:

t_CK

CLKIN Period

CLKIN Width Low

CLKIN Width High

21

9.5

80

40

3

ns

t_CKL

t_CKH

t_CKRF

CLKIN Rise/Fall (0.4 V–2.0 V)

t_CK

CLKIN

t_CKH

t_CKL

Figure 12. Clock Input

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ADSP-21160N

Reset

Table 6. Reset

Parameter

Min

Max

Unit

Timing Requirements:

t_WRST

t_SRST

RESET Pulsewidth Low¹

RESET Setup Before CLKIN High²

4t_CK

8

ns

¹Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 µs while RESET is

low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator).

²Only required if multiple ADSP-21160Ns must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple

ADSP-21160Ns communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself

after reset.

CLKIN

t_SRST

t_WRST

RESET

Figure 13. Reset

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ADSP-21160N

Interrupts

Table 7. Interrupts

Parameter

Min

Max

Unit

Timing Requirements:

t_SIR

t_HIR

t_IPW

IRQ2–0 Setup Before CLKIN High¹

6

0

ns

IRQ2–0 Hold After CLKIN High¹

IRQ2–0 Pulsewidth²

2+t_CK

¹Only required for IRQx recognition in the following cycle.

²Applies only if t_SIRand t_HIRrequirements are not met.

CLKIN

t_SIR

t_HIR

IRQ2–0

t_IPW

Figure 14. Interrupts

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ADSP-21160N

Timer

Table 8. Timer

Parameter

Min

Max

Unit

Switching Characteristic:

t_DTEX

CLKIN High to TIMEXP

1

9

ns

CLKIN

t_DTEX

TIMEXP

Figure 15. Timer

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ADSP-21160N

Flags

Table 9. Flags

Parameter

Min

Max

Unit

Timing Requirements:

t_SFI

t_HFI

FLAG3–0 IN Setup Before CLKIN High¹

4

1

ns

FLAG3–0 IN Hold After CLKIN High¹

FLAG3–0 IN Delay After RDx/WRx Low¹

FLAG3–0 IN Hold After RDx/WRx Deasserted¹

t_DWRFI

t_HFIWR

Switching Characteristics:

12

0

t_DFO

FLAG3–0 OUT Delay After CLKIN High

9

ns

t_HFO

t_DFOE

t_DFOD

FLAG3–0 OUT Hold After CLKIN High

CLKIN High to FLAG3–0 OUT Enable

CLKIN High to FLAG3–0 OUT Disable

1

ns

t_CK– t_CCLK+5

¹Flag inputs meeting these setup and hold times for instruction cycle N will affect conditional instructions in instruction cycle N+2.

CLKIN

t_DFO

t_DFOE

t_DFO

t_DFOD

t_HFO

FLAG3–0 _OUT

FLAG OUTPUT

CLKIN

t_SFI

t_HFI

FLAG3–0 _IN

t_DWRFI

t_HFIWR

RDX

WRX

FLAG INPUT

Figure 16. Flags

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ADSP-21160N

Memory Read—Bus Master

Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to

CLKIN. These specifications apply when the ADSP-21160N is the bus master accessing external memory space in asyn-

chronous access mode. Note that timing for ACK, DATA, RDx, WRx, and DMAG strobe timing parameters only applies

to asynchronous access mode.

Table 10. Memory Read—Bus Master

Parameter

Min

Max

Unit

Timing Requirements:

t_DAD

Address, CIF, Selects Delay to Data

t_CK– 0.25t_CCLK– 11+W

t_CK– 0.5t_CCLK+W

ns

Valid^1,2

t_DRLD

t_HDA

t_SDS

t_HDRH

t_DAAK

t_DSAK

t_SAKC

t_HAKC

RDx Low to Data Valid^1,3

Data Hold from Address, Selects⁴

Data Setup to RDx High¹

Data Hold from RDx High^3,4

ACK Delay from Address, Selects^2,5

ACK Delay from RDx Low^3,5

ACK Setup to CLKIN^3,5

ACK Hold After CLKIN³

ns

0

8

1

t_CK– 0.5t_CCLK– 12+W

t_CK– 0.75t_CCLK– 11+W

0.5t_CCLK+3

1

Switching Characteristics:

t_DRHA

Address, CIF, Selects Hold After RDx

0.25t_CCLK– 1+H

ns

High³

t_DARL

t_RW

t_RWR

Address, CIF, Selects to RDx Low²

RDx Pulse width³

0.25t_CCLK– 3

t_CK– 0.5t_CCLK– 1+W

0.5t_CCLK– 1+HI

ns

RDx High to WRx, RDx, DMAGx Low³

W = (number of wait states specified in WAIT register)

؋

t_CK.

HI = t_CK(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

H = t_CK(if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).

¹Data Delay/Setup: User must meet t_DAD, t_DRLD, or t_SDS.

²The falling edge of MSx, BMS is referenced.

³Note that timing for ACK, DATA, RDx, WRx, and DMAG strobe timing parameters only applies to asynchronous access mode.

⁴Data Hold: User must meet t_HDAor t_HDRHin asynchronous access mode. See Example System Hold Time Calculation on page 47 for the calculation of

hold times given capacitive and dc loads.

⁵ACK Delay/Setup: User must meet t_DAAK, t_DSAK, or t_SAKCfor deassertion of ACK (Low), all three specifications must be met for assertion of ACK (High).

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ADSP-21160N

ADDRESS

MSx, CIF

BMS

t_DRHA

t_DARL

t_RW

RDX

t_HDA

t_HDRH

t_DRLD

t_SDS

t_DAD

DATA

t_DSAK

t_RWR

t_DAAK

ACK

t_SAKC

t_HAKC

CLKIN

WRx

DMAG

Figure 17. Memory Read—Bus Master

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ADSP-21160N

Memory Write—Bus Master

Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to

CLKIN. These specifications apply when the ADSP-21160N is the bus master accessing external memory space in asyn-

chronous access mode. Note that timing for ACK, DATA, RDx, WRx, and DMAG strobe timing parameters only applies

to asynchronous access mode.

Table 11. Memory Write—Bus Master

Parameter

Min

Max

Unit

Timing Requirements:

t_DAAK

t_DSAK

t_SAKC

t_HAKC

ACK Delay from Address, Selects^1,2

t_CK– 0.5t_CCLK–12+W

t_CK– 0.75t_CCLK– 11+W

ns

ACK Delay from WRx Low^1,3

ACK Setup to CLKIN^1,3

ACK Hold After CLKIN^1,3

0.5t_CCLK+3

1

Switching Characteristics:

t_DAWH

Address, CIF, Selects to WRx

t_CK– 0.25t_CCLK– 3+W

ns

Deasserted^2,3

t_DAWL

t_WW

Address, CIF, Selects to WRx Low²

WRx Pulse width³

0.25t_CCLK– 3

ns

t_CK– 0.5t_CCLK– 1+W

0.25t_CCLK– 1+H

0.25t_CCLK– 2+H

t_DDWH

t_DWHA

t_DWHD

t_DATRWH

t_WWR

Data Setup before WRx High³

Address Hold after WRx Deasserted³

Data Hold after WRx Deasserted³

Data Disable after WRx Deasserted^3,4

0.25t_CCLK+2+H

WRx High to WRx, RDx, DMAGx Low³0.5t_CCLK– 1+HI

Data Disable before WRx or RDx Low 0.25t_CCLK– 1+I

t_DDWR

t_WDE

WRx Low to Data Enabled

–0.25t_CCLK– 1

W = (number of wait states specified in WAIT register) × t_CK.

H = t_CK(if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).

HI = t_CK(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

I = t_CK(if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).

¹ACK Delay/Setup: User must meet t_DAAKor t_DSAKor t_SAKCfor deassertion of ACK (Low), all three specifications must be met for assertion of ACK (High).

²The falling edge of MSx, BMS is referenced.

³Note that timing for ACK, DATA, RDx, WRx, and DMAG strobe timing parameters only applies to asynchronous access mode.

⁴See Example System Hold Time Calculation on page 47 for calculation of hold times given capacitive and dc loads.

ADDRESS

MSx , BMS ,

CIF

t_DAWH

t_DWHA

t_DAWL

t_WW

WRx

t_WWR

t_WDE

t_DATRWH

t_DDWH

t_DDWR

DATA

t_DSAK

t_DWHD

t_DAAK

ACK

t_SAKC

t_HAKC

CLKIN

RDx

DMAG

Figure 18. Memory Write—Bus Master

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ADSP-21160N

Synchronous Read/Write—Bus Master

Use these specifications for interfacing to external memory systems that require CLKIN—relative timing or for accessing

a slave ADSP-21160N (in multiprocessor memory space). These synchronous switching characteristics are also valid during

asynchronous memory reads and writes except where noted (see Memory Read—Bus Master on page 24 and Memory

Write—Bus Master on page 26). When accessing a slave ADSP-21160N, these switching characteristics must meet the

slave’s timing requirements for synchronous read/writes (see Synchronous Read/Write—Bus Slave on page 29). The slave

ADSP-21160N must also meet these (bus master) timing requirements for data and acknowledge setup and hold times.

Table 12. Synchronous Read/Write—Bus Master

Parameter

Min

Max

Unit

Timing Requirements:

t_SSDATI

t_HSDATI

t_SACKC

t_HACKC

Data Setup Before CLKIN¹

5.5

1

0.5t_CCLK+3

1

ns

Data Hold After CLKIN¹

ACK Setup Before CLKIN¹

ACK Hold After CLKIN¹

Switching Characteristics:

t_DADDO

t_HADDO

t_DPGO

t_DRDO

t_DWRO

t_DRWL

t_DDATO

t_HDATO

t_DACKMO

t_ACKMTR

t_DCKOO

t_CKOP

Address, MSx, BMS, BRST, CIF Delay After CLKIN

10

ns

Address, MSx, BMS, BRST, CIF Hold After CLKIN

PAGE Delay After CLKIN

RDx High Delay After CLKIN¹

WRx High Delay After CLKIN¹

RDx/WRx Low Delay After CLKIN

Data Delay After CLKIN

1.5

0.25t_CCLK– 1

11

0.25t_CCLK+9

Data Hold After CLKIN

1.5

3

– 3

1

t_CK– 1

t_CK/2 – 2

ACK Delay After CLKIN²

9

ACK Disable Before CLKIN²

CLKOUT Delay After CLKIN

CLKOUT Period

5

t_CK³+1

t_CK/2+2³

t_CKWH

t_CKWL

CLKOUT Width High

CLKOUT Width Low

¹Note that timing for ACK, DATA, RDx, WRx, and DMAG strobe timing parameters only applies to synchronous access mode.

²Applies to broadcast write, master precharge of ACK.

³Applies only when the DSP drives a bus operation; CLKOUT held inactive or three-state otherwise, For more information, see the System Design chapter

in the ADSP-2116x SHARC DSP Hardware Reference.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

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ADSP-21160N

CLKIN

t_CKOP

t_CKWH

t_DCKOO

t_CKWL

CLKOUT

t_DADDO

t_HADDO

ADDRESS

MSX, BRST,

CIF

t_DPGO

PAGE

t_HACKC

t_SACKC

ACK

(IN)

t_DACKMO

t_ACKMTR

ACK

(OUT)

READ CYCLE

t_DRWL

t_DRDO

⌹⌬␹

t_HSDATI

t_SSDATI

DATA

(IN)

WRITE CYCLE

t_DWRO

t_DRWL

⑁ ⌹␹

t_HDATO

t_DDATO

DATA

(OUT)

Figure 19. Synchronous Read/Write—Bus Master

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ADSP-21160N

Synchronous Read/Write—Bus Slave

Use these specifications for ADSP-21160N bus master accesses of a slave’s IOP registers or internal memory (in multipro-

cessor memory space). The bus master must meet these (bus slave) timing requirements.

Table 13. Synchronous Read/Write—Bus Slave

Parameter

Min

Max

Unit

Timing Requirements:

t_SADDI

t_HADDI

t_SRWI

t_HRWI

t_SSDATI

t_HSDATI

Address, BRST Setup Before CLKIN

5

1

5

1

5.5

1

ns

Address, BRST Hold After CLKIN

RDx/WRx Setup Before CLKIN

RDx/WRx Hold After CLKIN

Data Setup Before CLKIN

Data Hold After CLKIN

Switching Characteristics:

t_DDATO

t_HDATO

t_DACKC

t_HACKO

Data Delay After CLKIN

0.25 t_CCLK+ 9

10

ns

Data Hold After CLKIN

ACK Delay After CLKIN

ACK Hold After CLKIN

1.5

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

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ADSP-21160N

CLKIN

t_SADDI

t_HADDI

ADDRESS

ACK

t_HACKO

t_DACKC

t_SRWI

READ ACCESS

t_HRWI

RDx

t_HDATO

t_DDATO

DATA

(OUT)

WRITE ACCESS

t_HRWI

t_SRWI

WRx

t_HSDATI

t_SSDATI

DATA

(IN)

Figure 20. Synchronous Read/Write—Bus Slave

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ADSP-21160N

Multiprocessor Bus Request and Host Bus Request

Use these specifications for passing of bus mastership between multiprocessing ADSP-21160Ns (BRx) or a host processor

(HBR, HBG).

Table 14. Multiprocessor Bus Request and Host Bus Request

Parameter

Min

Max

Unit

Timing Requirements:

t_HBGRCSV

HBG Low to RDx/WRx/CS Valid

6.5 + t_CK+ t_CCLK

12.5CR

-

ns

t_SHBRI

t_HHBRI

t_SHBGI

t_HHBGI

t_SBRI

HBR Setup Before CLKIN¹

HBR Hold After CLKIN¹

6

1

6

1

9

1

6

2

ns

HBG Setup Before CLKIN

HBG Hold After CLKIN High

BRx, PA Setup Before CLKIN

BRx, PA Hold After CLKIN High

RPBA Setup Before CLKIN

RPBA Hold After CLKIN

t_HBRI

t_SRPBAI

t_HRPBAI

Switching Characteristics:

t_DHBGO

t_HHBGO

t_DBRO

HBG Delay After CLKIN

HBG Hold After CLKIN

BRx Delay After CLKIN

BRx Hold After CLKIN

7

ns

2

8

t_HBRO

1.5

t_DPASO

t_TRPAS

t_DPAMO

t_PATR

t_DRDYCS

t_TRDYHG

t_ARDYTR

PA Delay After CLKIN, Slave

PA Disable After CLKIN, Slave

PA Delay After CLKIN, Master

PA Disable Before CLKIN, Master

REDY (O/D) or (A/D) Low from CS and HBR Low²

8

1.5

0.25t_CCLK+9

0.5t_CK

0.25t_CCLK– 5

REDY (O/D) Disable or REDY (A/D) High from HBG²t_CK+20

REDY (A/D) Disable from CS or HBR High²

11

¹Only required for recognition in the current cycle.

²(O/D) = open drain, (A/D) = active drive.

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ADSP-21160N

CLKIN

t_{S HBRI}

t_HHBRI

HBR

t_DHBGO

t_{HHBG O}

HBG (OUT)

BRx (OUT)

t_DBRO

t_HBRO

t_{TRP AS}

t_{DPAS O}

PA (OUT)

(SLAVE)

t_{P ATR}

t_{DPAM O}

PA (OUT)

(MASTER)

t_SHBGI

t_HHBGI

HBG (IN)

BRx (IN)

t_SBRI

t_HBRI

t_{S PAI}

t_HPAI

PA (I N)

(O/D)

t_{S RP BAI}

t_HRPBAI

RPBA

HBR

CS

t_TRDYHG

t_DRDYCS

REDY

(O /D)

t_{ARDY TR}

REDY

(A/D)

t_{HBGRCS V}

HBG (OUT)

RDx

WRx

CS

O/D = OPEN DRAIN, A/D = ACTIVE

DRIV E

Figure 21. Multiprocessor Bus Request and Host Bus Request

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ADSP-21160N

Asynchronous Read/Write—Host to ADSP-21160N

Use these specifications (Table 15 and Table 16) for asynchronous host processor accesses of an ADSP-21160N, after the

host has asserted CS and HBR (low). After HBG is returned by the ADSP-21160N, the host can drive the RDx and WRx

pins to access the ADSP-21160N’s internal memory or IOP registers. HBR and HBG are assumed low for this timing

Table 15. Read Cycle

Parameter

Min

Max

Unit

Timing Requirements:

t_SADRDL

t_HADRDH

t_WRWH

t_DRDHRDY

Address Setup/CS Low Before RDx Low

Address Hold/CS Hold Low After RDx

RDx/WRx High Width

RDx High Delay After REDY (O/D) Disable

RDx High Delay After REDY (A/D) Disable

0

2

5

0

ns

Switching Characteristics:

t_SDATRDY

t_DRDYRDL

t_RDYPRD

Data Valid Before REDY Disable from Low

2

ns

REDY (O/D) or (A/D) Low Delay After RDx Low

REDY (O/D) or (A/D) Low Pulsewidth for Read

Data Disable After RDx High

11

6

t_CK- 3

2

t_HDARWH

RE AD CY CLE

ADDRESS/CS

t_HADRDH

t_SADRDL

t_WRWH

RDx

t_HDARWH

DATA (OUT)

t_SDATRDY

t_{RDY PR D}

t_DRDHRDY

t_{DRD YRD L}

REDY (O/D)

REDY (A/D)

Figure 22. Read Cycle (Asynchronous Read—Host to ADSP-21160N)

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ADSP-21160N

Table 16. Write Cycle

Parameter

Min

Max

Unit

Timing Requirements:

t_SCSWRL

t_HCSWRH

t_SADWRH

t_HADWRH

t_WWRL

CS Low Setup Before WRx Low

0

6

2

7

5

0

5

4

ns

CS Low Hold After WRx High

Address Setup Before WRx High

Address Hold After WRx High

WRx Low Width

t_WRWH

RDx/WRx High Width

t_DWRHRDY

t_SDATWH

t_HDATWH

WRx High Delay After REDY (O/D) or (A/D) Disable

Data Setup Before WRx High

Data Hold After WRx High

Switching Characteristics:

t_DRDYWRLREDY (O/D) or (A/D) Low Delay After WRx/CS Low

t_RDYPWRREDY (O/D) or (A/D) Low Pulsewidth for Write

11

ns

5.75 + 0.5t_CCLK

WRITE CYCLE

ADDRESS

t_SADWRH

t_{HADW RH}

t_{S CSWRL}

T HCS WRH

CS

t_WWRL

t_WRWH

WRx

t_HDATWH

t_SDATWH

DATA (IN)

t_{DRDYW RL}

t_{RDYP WR}

t_DWRHRDY

REDY (O/D)

REDY (A/D)

O/D = OPEN DRAIN, A/D = ACTIVE

DRIVE

Figure 23. Write Cycle (Asynchronous Write—Host to ADSP-21160N)

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ADSP-21160N

Three-State Timing—Bus Master and Bus Slave

These specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to

CLKIN and the SBTS pin. This timing is applicable to bus master transition cycles (BTC) and host transition cycles (HTC)

as well as the SBTS pin.

Table 17. Three-State Timing—Bus Slave, HBR, SBTS

Parameter

Min

Max

Unit

Timing Requirements:

t_STSCK

t_HTSCK

Switching Characteristics:

SBTS Setup Before CLKIN

SBTSHold After CLKIN

6

2

ns

t_MIENA

t_MIENS

t_MIENHG

t_MITRA

t_MITRS

t_MITRHG

t_DATEN

t_DATTR

t_ACKEN

t_ACKTR

Address/Select Enable After CLKIN

1.5

0.25t_CCLK– 4

3.5

0.25t_CCLK+1

1.5

9

ns

Strobes Enable After CLKIN¹

HBG Enable After CLKIN

Address/Select Disable After CLKIN

Strobes Disable After CLKIN^1,2

HBG Disable After CLKIN

0.25t_CCLK

8

0.25t_CCLK+ 7

5

9

5

9

t_CCLK+1

1.5t_CK+ 5

t_CK+ 0.25t_CCLK+ 5 ns

t_CK+ 5

0.5t_CK+ 1.5

t_CK+5

Data Enable After CLKIN³

Data Disable After CLKIN³

ACK Enable After CLKIN³

ACK Disable After CLKIN³

CLKOUT Enable After CLKIN

CLKOUT Disable After CLKIN

Address, MSx Disable Before HBG Low

t_CDCEN

t_CDCTR

1.5

t_CCLK– 3

1.5t_CK+ 1.5

t_ATRHBG

t_STRHBG

t_PTRHBG

t_BTRHBG

t_MENHBG

RDx, WRx, DMAGx Disable Before HBG Low t_CK+ 0.25t_CCLK+ 1.5

Page Disable Before HBG Low

t_CK+ 1.5

0.5t_CK+ 1.5

t_CK– 5

ns

BMS Disable Before HBG Low

Memory Interface Enable After HBG High⁴

¹Strobes = RDx, WRx, DMAGx.

²If access aborted by SBTS, then strobes disable before CLKIN [0.25t_CCLK+ 1.5 (min.), 0.25t_CCLK+ 5 (max.)]

³In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.

⁴Memory Interface = Address, RDx, WRx, MSx, PAGE, DMAGx, and BMS (in EPROM boot mode).

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ADSP-21160N

CLKIN

t_STSCK

t_HTSCK

SBTS

t_MIENA,t_MIENS,t_MIENHG

t_MITRA,t_MITRS,t_MITRHG

MEMORY

INTERFACE

t_DATTR

t_DATEN

DATA

ACK

t_ACKTR

t_ACKEN

t_CDCEN

t_CDCTR

CLKOUT

t_ATRHBG

t_STRHBG

t_PTRHBG

t_BTRHBG

HBG

t_MENHBG

MEMORY

INTERFACE

MEMORY INTERFACE = ADDRESS, RDx, WRx, MSx, PAGE, DMAGx. BMS (IN EPROM BOOT MODE)

Figure 24. Three-State Timing—Bus Slave, HBR, SBTS

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ADSP-21160N

DMA Handshake

These specifications describe the three DMA handshake modes. In all three modes DMAR is used to initiate transfers. For

handshakemode, DMAG controlsthelatchingorenablingofdataexternally. Forexternalhandshake mode, thedatatransfer

is controlled by the ADDR31–0, RDx, WRx, PAGE, MS3–0, ACK, and DMAG signals. For Paced Master mode, the data

transfer is controlled by ADDR31–0, RDx, WRx, MS3–0, and ACK (not DMAG). For Paced Master mode, the Memory

Read-Bus Master, Memory Write-Bus Master, and Synchronous Read/Write-Bus Master timing specifications for

ADDR31–0, RDx, WRx, MS3–0, PAGE, DATA63–0, and ACK also apply.

Table 18. DMA Handshake

Parameter

Min

Max

Unit

Timing Requirements:

t_SDRC

t_WDR

DMARx Setup Before CLKIN¹

3

DMARx Width Low (Nonsynchronous)²0.5t_CCLK+1

Data Setup After DMAGx Low³

ns

t_SDATDGL

t_HDATIDG

t_DATDRH

t_DMARLL

t_DMARH

t_CK– 0.5t_CCLK–7

t_CK+3

Data Hold After DMAGx High

Data Valid After DMARx High³

DMARx Low Edge to Low Edge⁴

DMARx Width High²

2

t_CK

0.5t_CCLK+1

Switching Characteristics:

t_DDGL

t_WDGH

t_WDGL

t_HDGC

t_VDATDGH

t_DATRDGH

t_DGWRL

t_DGWRH

t_DGWRR

t_DGRDL

t_DRDGH

t_DGRDR

t_DGWR

DMAGx Low Delay After CLKIN

DMAGx High Width

DMAGx Low Width

0.25t_CCLK+1

0.5t_CCLK– 1+HI

t_CK– 0.5t_CCLK– 1

t_CK– 0.25t_CCLK+1.5

t_CK– 0.25t_CCLK– 8

0.25t_CCLK– 3

–1.5

t_CK– 0.5t_CCLK– 2 +W

–1.5

0.25t_CCLK+9

ns

DMAGx High Delay After CLKIN

Data Valid Before DMAGx High⁵

Data Disable After DMAGx High⁶

WRx Low Before DMAGx Low

DMAGx Low Before WRx High

WRx High Before DMAGx High⁷

RDx Low Before DMAGx Low

RDx Low Before DMAGx High

RDx High Before DMAGx High⁷

DMAGx High to WRx, RDx, DMAGx

Low

t_CK– 0.25t_CCLK+9

t_CK– 0.25t_CCLK+5

0.25t_CCLK+1.5

2

t_CK– 0.5t_CCLK–2+W

–1.5

0.5t_CCLK– 2+HI

2

t_DADGH

t_DDGHA

Address/Select Valid to DMAGx High

Address/Select Hold after DMAGx High

18

1

ns

W = (number of wait states specified in WAIT register)

؋

t_CK.

HI = t_CK(if data bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

¹Only required for recognition in the current cycle.

²Maximum throughput using DMARx/DMAGx handshaking equals t_WDR+ t_DMARH= (0.5t_CCLK+1) + (0.5t_CCLK+1)=12.5 ns (80 MHz). This throughput

limit applies to non-synchronous access mode only.

³t_SDATDGLis the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of

the write, the data can be driven t_DATDRHafter DMARx is brought high.

⁴Use t_DMARLLif DMARx transitions synchronous with CLKIN. Otherwise, use t_WDRand t_DMARH

.

⁵t_VDATDGHis valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then

t_VDATDGH= t_CK– .25t_CCLK– 8 + (n × t_CK) where n equals the number of extra cycles that the access is prolonged.

⁶See Example System Hold Time Calculation on page 47 for calculation of hold times given capacitive and dc loads.

⁷This parameter applies for synchronous access mode only.

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ADSP-21160N

CLKIN

t_SDRC

t_DMARLL

t_SDRC

t_WDR

t_DMARH

DMARx

DMAGx

t_HDGC

t_DDGL

t_WDGL

t_WDGH

TRANSFERS BETWEEN ADSP-2116X

INTERNAL MEMORY AND EXTERNAL DEVICE

t_DATRDGH

t_VDATDGH

DATA

(FROM ADSP-2116X TO EXTERNAL DRIVE)

t_DATDRH

t_SDATDGL

t_HDATIDG

(FROM EXTERNAL DRIVE TO ADSP-2116X)

TRANSFERS BETWEEN EXTERNAL DEVICE AND

EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE)

t_DGWRL

t_DGWRR

t_DGWRH

WRx

(EXTERNAL DEVICE TO EXTERNAL MEMORY)

(EXTERNAL MEMORY TO EXTERNAL DEVICE)

t_DGRDR

t_DGRDL

RDx

t_DRDGH

t_DADGH

t_DDGHA

ADDR

MSX

* MEMORY READ BUS MASTER, MEMORY WRITE BUS MASTER, OR SYNCHRONOUS READ/WRITE BUS MASTER

TIMING SPECIFICATIONS FOR ADDR31–0, RDX, WRX, MS3–0 AND ACK ALSO APPLY HERE.

Figure 25. DMA Handshake Timing

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ADSP-21160N

Link Ports

Calculation of link receiver data setup and hold, relative to link clock, is required to determine the maximin allowable skew

that can be introduced in the transmission path, between LDATA and LCLK. Setup skew is the maximum delay that can

be introduced in LDATA, relative to LCLK (setup skew = t_LCLKTWHminimum – t_DLDCH– t_SLDCL). Hold skew is the maximum

delay that can be introduced in LCLK, relative to LDATA (hold skew = t_LCLKTWLminimum + t_HLDCH– t_HLDCL).Calculations

made directly from speed specifications result in unrealistically small skew times, because they include multiple tester

guardbands.

Note that there is a two-cycle effect latency between the link port enable instruction and the DSP enabling the link port.

Table 19. Link Ports—Receive

Parameter

Min

Max

Unit

Timing Requirements:

t_SLDCL

t_HLDCL

t_LCLKIW

t_LCLKRWL

t_LCLKRWH

Data Setup Before LCLK Low

Data Hold After LCLK Low

LCLK Period

LCLK Width Low

LCLK Width High

2.5

t_LCLK

4

ns

4

Switching Characteristics:

t_DLALC

LACK Low Delay After LCLK High¹

12

17

ns

¹LACK goes low with t_DLALCrelative to rise of LCLK after first nibble, but doesn’t go low if the receiver’s link buffer is not about to fill.

RECEIVE

t_LCLKIW

t_LCLKRWH

t_LCLKRWL

LCLK

t_HLDCL

t_SLDCL

IN

LDAT(7:0)

t_DLALC

LACK (OUT)

Figure 26. Link Ports—Receive

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Table 20. Link Ports—Transmit

Parameter

Min

Max

Unit

Timing Requirements:

t_SLACH

t_HLACH

Switching Characteristics:

LACK Setup Before LCLK High

LACK Hold After LCLK High

14

–2

ns

t_DLDCH

t_HLDCH

t_LCLKTWL

t_LCLKTWH

t_DLACLK

Data Delay After LCLK High

Data Hold After LCLK High

LCLK Width Low

LCLK Width High

LCLK Low Delay After LACK High

6.0

ns

–2

0.5t_LCLK– .5

0.5t_LCLK+5

0.5t_LCLK+.5

3

t_LCLK+11

/

2

TRANSMIT

t_LCLKTWL

t_LCLKTWH

LAST NIBBLE/BYTE

TRANSMITTED

FIRST NIBBLE/BYTE

TRANSMITTED

LCLK INACTIVE

(HIGH)

LCLK

t_DLDCH

t_HLDCH

LDAT(7:0)

LACK (IN)

OUT

t_DLACLK

t_SLACH

t_HLACH

THE t_SLACHREQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED.

Figure 27. Link Ports—Transmit

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ADSP-21160N

Serial Ports

To determine whether communication is possible between two devices at clock speed n, the following specifications must

be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width.

Table 21. Serial Ports—External Clock

Parameter

Min

Max

Unit

Timing Requirements:

t_SFSE

TFS/RFS Setup Before TCLK/RCLK¹

3.5

4

1.5

4

ns

t_HFSE

t_SDRE

t_HDRE

t_SCLKW

t_SCLK

TFS/RFS Hold After TCLK/RCLK^1,2

Receive Data Setup Before RCLK¹

Receive Data Hold After RCLK¹

TCLK/RCLK Width

8

TCLK/RCLK Period

2t_CCLK

¹Referenced to sample edge.

²RFShold after RCK when MCE = 1, MFD = 0 is 0 ns minimum fromdrive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.

Table 22. Serial Ports—Internal Clock

Parameter

Min

Max

Unit

Timing Requirements:

t_SFSI

TFS Setup Before TCLK¹; RFS Setup Before RCLK¹

8

ns

t_HFSI

t_SDRI

t_HDRI

TFS/RFS Hold After TCLK/RCLK^1,2

Receive Data Setup Before RCLK¹

Receive Data Hold After RCLK¹

t_CCLK/2 + 1

6.5

3

¹Referenced to sample edge.

²RFSholdafter RCKwhen MCE= 1, MFD =0is0 nsminimumfrom drive edge. TFShold after TCK for late external TFS is 0 ns minimumfrom drive edge.

Table 23. Serial Ports—External or Internal Clock

Parameter

Min

Max

Unit

Switching Characteristics:

t_DFSE

t_HOFSE

RFS Delay After RCLK (Internally Generated RFS)¹

13

ns

RFS Hold After RCLK (Internally Generated RFS)¹

3

¹Referenced to drive edge.

Table 24. Serial Ports—External Clock

Parameter

Min

Max

Unit

Switching Characteristics:

t_DFSE

TFS Delay After TCLK (Internally Generated TFS)¹

13

16

ns

t_HOFSE

t_DDTE

t_HDTE

TFS Hold After TCLK (Internally Generated TFS)¹

Transmit Data Delay After TCLK¹

3

0

Transmit Data Hold After TCLK¹

¹Referenced to drive edge.

Table 25. Serial Ports—Internal Clock

Parameter

Min

Max

Unit

Switching Characteristics:

t_DFSI

t_HOFSI

TFS Delay After TCLK (Internally Generated TFS)¹

4.5

ns

TFS Hold After TCLK (Internally Generated TFS)¹

–1.5

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Table 25. Serial Ports—Internal Clock (Continued)

Parameter

Min

Max

Unit

t_DDTI

t_HDTI

t_SCLKIW

Transmit Data Delay After TCLK¹

Transmit Data Hold After TCLK¹

TCLK/RCLK Width

7.5

ns

0

0.5t_SCLK–1.5

0.5t_SCLK+1.5

¹Referenced to drive edge.

Table 26. Serial Ports—Enable and Three-State

Parameter

Min

Max

Unit

Switching Characteristics:

t_DDTEN

t_DDTTE

t_DDTIN

t_DDTTI

Data Enable from External TCLK¹

Data Disable from External TCLK¹

Data Enable from Internal TCLK¹

Data Disable from Internal TCLK¹

4

0

ns

10

3

¹Referenced to drive edge.

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DATA RECEIVE— INTERNAL CLOCK

DATA RECEIVE— EXTERNAL CLOCK

DRIVE

EDGE

SAMPLE

EDGE

DRIVE

EDGE

SAMPLE

EDGE

t_SCLKW

t_SCLKIW

RCLK

t_DFSE

t_HOFSE

t_HFSE

t_SFSI

t_HFSI

t_SFSE

t_HOFSE

RFS

DR

t_SDRI

t_SDRE

t_HDRI

t_HDRE

DR

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DATA TRANSMIT— INTERNAL CLOCK

DATA TRANSMIT— EXTERNAL CLOCK

DRIVE

EDGE

SAMPLE

EDGE

DRIVE

EDGE

SAMPLE

EDGE

t_SCLKIW

t_SCLKW

TCLK

t_DFSE

t_DFSI

t_HOFSI

t_SFSI

t_HFSI

t_HOFSE

t_SFSE

t_HFSE

TFS

DT

t_DDTI

t_DDTE

t_HDTE

t_HDTI

DT

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DRIVE EDGE DRIVE EDGE

TCLK /

RCLK

TCLK

(EXT)

t_DDTTE

t_DDTEN

DT

DRIVE

EDGE

DRIVE

EDGE

TCLK /

RCLK

TCLK

(INT)

t_DDTIN

t_DDTTI

DT

Figure 28. Serial Ports

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Table 27. Serial Ports—External Late Frame Sync

Parameter

Min

Max

13

Unit

Switching Characteristics:

t_DDTLFSE

Data Delay from Late External TFS or External RFS with

ns

MCE = 1, MFD = 0¹

t_DDTENFS

Data Enable from late FS or MCE = 1, MFD = 0¹

1.0

¹MCE = 1, TFS enable and TFS valid follow t_DDTLFSEand t_DDTENFS

.

EXTERNAL RFS WITH MCE = 1, MFD = 0

DRIVE

SAMPLE

DRIVE

RCLK

RFS

t_SFSE/I

t_HOFSE/I

(SEE NOTE 2)

t_DDTE/I

t_HDTE/I

1ST BIT

t_DDTENFS

DT

2ND BIT

t_DDTLFSE

LATE EXTERNAL TFS

DRIVE

SAMPLE

DRIVE

TCLK

t_HOFSE/I

t_SFSE/I

(SEE NOTE 2)

TFS

t_DDTE/I

TDDTENFS

t_HDTE/I

1ST BIT

DT

2ND BIT

t_DDTLFSE

Figure 29. External Late Frame Sync

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JTAG Test Access Port and Emulation

Table 28. JTAG Test Access Port and Emulation

Parameter

Min

Max

Unit

Timing Requirements:

t_TCK

TCK Period

t_CK

5

6

7

18

4t_CK

ns

t_STAP

t_HTAP

t_SSYS

TDI, TMS Setup Before TCK High

TDI, TMS Hold After TCK High

System Inputs Setup Before TCK Low¹

System Inputs Hold After TCK Low¹

TRST Pulsewidth

t_HSYS

t_TRSTW

Switching Characteristics:

t_DTDOTDO Delay from TCK Low

t_DSYS

System Outputs Delay After TCK Low²

13

30

ns

¹System Inputs = DATA63–0, ADDR31–0, RDx, WRx, ACK, SBTS, HBR, HBG, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, IRQ2–0, FLAG3–0,

PA, BRST, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, EBOOT, LBOOT, BMS,

CLKIN, RESET.

²System Outputs = DATA63–0, ADDR31–0, MS3–0, RDx, WRx, ACK, PAGE, CLKOUT, HBG, REDY, DMAG1, DMAG2, BR6–1, PA, BRST, CIF,

FLAG3–0, TIMEXP, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, BMS.

t_TCK

TCK

t_STAP

t_HTAP

TMS

TDI

t_DTDO

TDO

t_SSYS

t_HSYS

SYSTEM

INPUTS

t_DSYS

SYSTEM

OUTPUTS

Figure 30. IEEE 11499.1 JTAG Test Access Port

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from Electrical Characteristics on page 13 and the cur-

rent-versus-operation information in Table 29, engineers

can estimate the ADSP-21160N’s internal power supply

(V_DDINT) input current for a specific application, according

to the following formula:

Output Drive Currents

Figure 31 shows typical I–V characteristics for the output

drivers of the ADSP-21160N. The curves represent the

current drive capability of the output drivers as a function

of output voltage.

% Peak × I_DDINPEAK

% High × I_DDINHIGH

% Low × I_DDINLOW

120

100

V_DDEXT=3.47V, –40°C

80

V_DDEXT=3.3V, 25°C

60

+ % Idle × I_DDIDLE

-------------------------------------------------

I_DDINT

V_DDEXT= 3.13V, 100°C

40

20

Theexternalcomponentoftotalpowerdissipationiscaused

by the switching of output pins. Its magnitude depends on:

0

–20

–40

• the number of output pins that switch during each

cycle (O)

V_DDEXT= 3.47V, –40°C

_DDEXT=3.3V, 25°C

V_DDEXT=3.13V, 100°C

–60

V

–80

• the maximum frequency at which they can switch (f)

• their load capacitance (C)

–100

–120

0

0.5

1

1.5

2

2.5

3

3.5

• their voltage swing (VDD)

SOURCE (V_DDEXT) VOLTAGE – V

and is calculated by:

_EXT= O × C × V_DD²× f

Figure 31. ADSP-21160N Typical Drive Currents

P

The load capacitance should include the processor’s

package capacitance (C_IN). The switching frequency

includes driving the load high and then back low. Address

and data pins can drive high and low at a maximum rate of

1/(2t_CK). The write strobe can switch every cycle at a

frequency of 1/t_CK. Select pins switch at 1/(2t_CK), but selects

can switch on each cycle.

Power Dissipation

Total power dissipation has two components, one due to

internal circuitry and one due to the switching of external

output drivers.

Internal power dissipation is dependent on the instruction

execution sequence and the data operands involved. Using

the current specifications (I_DDINPEAK, I_DDINHIGH, I_DDINLOW, I_DDIDLE

)

Table 29. ADSP-21160N Operation Types vs. Input Current

Operation

Peak Activity¹

High Activity¹

Low Activity¹

Instruction Type

Multifunction

Cache

2 per t_CKcycle

(DM

؋

64 and PM

؋

64)

1 per 2 t_CCLKcycles

Multifunction

Internal Memory

1 per t_CKcycle

(DM

؋

64)

Single Function

Internal Memory

None

Instruction Fetch

Core Memory Access²

Internal Memory DMA

External Memory DMA

Data bit pattern for core

memory access and DMA

1 per 2 t_CCLKcycles

None

1 per external port cycle (

؋

64) 1 per external port cycle (

؋

64) None

Worst case Random N/A

¹Peak Activity=I_DDINPEAK, High Activity=I_DDINHIGH, and Low Activity=I_DDINLOW. The state of the PEYEN bit (SIMD versus SISD mode) does not influence

these calculations.

²These assume a 2:1 core clock ratio. For more information on ratios and clocks (t_CKand t_CCLK), see the timing ratio definitions on page 16.

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• External data memory writes occur every other cycle, a

rate of 1/(2 t_CK), with 50% of the pins switching

Example: Estimate P_EXTwith the following assumptions:

• A system with one bank of external data memory—asyn-

chronous RAM (64-bit)

• The bus cycle time is 47.5 MHz (t_CK= 21 ns).

The P_EXTequation is calculated for each class of pins that

can drive:

• Four 64K × 16 RAM chips are used, each with a load of

10 pF

Table 30. External Power Calculations (3.3 V Device)

Pin Type

# of Pins

% Switching

× C

× f

× VDD²

= P_EXT

Address

MS0

WRx

Data

CLKOUT

15

1

2

64

1

50

0

–

50

–

× 44.7 pF

× 14.7 pF

× 4.7 pF

× 24 MHz

× 48 MHz

× 10.9 V

= 0.088 W

= 0.000 W

= 0.023 W

= 0.123 W

= 0.003 W

P

_EXT= 0.237 W

Output Enable Time

A typical power consumption can now be calculated for

these conditions by adding a typical internal power

dissipation:

Output pins are considered to be enabled when they have

made a transition from a high impedance state to when they

startdriving. Theoutputenable timet_ENAistheintervalfrom

when a reference signal reaches a high or low voltage level

to when the output has reached a specified high or low trip

point, as shown in the Output Enable/Disable diagram

(Figure 32). If multiple pins (such as the data bus) are

enabled, the measurement value is that of the first pin to

start driving.

P

_TOTAL= P_EXT+ P_INT+ P_PLL

Where:

• P_EXTis from Table 30

• P_INTis I_DDINT× 1.9 V, using the calculation I_DDINTlisted in

Power Dissipation on page 46

• P_PLLis AI_DD× 1.9 V, using the value for AI_DDlisted in

ABSOLUTE MAXIMUM RATINGS on page 15

Example System Hold Time Calculation

To determine the data output hold time in a particular

system, first calculate t_DECAYusing the equation given above.

Choose ⌬V to be the difference between the

ADSP-21160N’s output voltage and the input threshold for

the device requiring the hold time. A typical ⌬V will be

0.4 V. C_Lis the total bus capacitance (per data line), and I_L

is the total leakage or three-state current (per dataline). The

hold time will be t_DECAYplus the minimum disable time (i.e.,

t_DATRWHfor the write cycle).

Note that the conditions causing a worst-case P_EXTare

different from those causing a worst-case P_INT. Maximum

P_INTcannot occur while 100% of the output pins are

switching from all ones to all zeros. Note also that it is not

common for an application to have 100% or even 50% of

the outputs switching simultaneously.

Test Conditions

The test conditions for timing parameters appearing in

ADSP-21160N specifications on page 13 include output

disable time, output enable time, and capacitive loading.

Output Disable Time

Output pins are considered to be disabled when they stop

driving, go into a high impedance state, and start to decay

from their output high or low voltage. The time for the

voltage on the bus to decay by ∆V is dependent on the

capacitive load, C_Land the load current, I_L. This decay time

can be approximated by the following equation:

REFERENCE

SIGNAL

t_MEASURED

⌻

t_ENA

DIS

V_OH(MEASURED)

V

_OH(MEASURED) – ⌬V

2.0V

1.0V

V_OL(MEASURED) + ⌬V

t

_DECAY= (C_L∆V)/I_L

V_OL(MEASURED)

t_DECAY

The output disable time t_DISis the difference between

t_MEASUREDand t_DECAYas shown in Figure 32. The time t_MEASURED

is the interval from when the reference signal switches to

when the output voltage decays ∆V from the measured

output high or output low voltage. t_DECAYis calculated with

test loads C_Land I_L, and with ∆V equal to 0.5 V.

OUTPUT STOPS

DRIVING

OUTPUT STARTS

DRIVING

HIGH-IMPEDANCE STATE.

TEST CONDITIONS CAUSE THIS VOLTAGE

TO BE APPROXIMATELY 1.5V

Figure 32. Output Enable/Disable

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50 ⍀

TO

OUTPUT

1.5V

RISE TIME

12PF

Y = 0.086192X + 2.34

TBD

FALL TIME

Figure 33. Equivalent Device Loading for AC

Measurements (Includes All Fixtures)

Y = 0.076014X +

2.15

INPUT

OR

OUTPUT

1.5V

50

100

150

200

250

LOAD CAPACITANCE – pF

Figure 34. Voltage Reference Levels for AC

Measurements (Except Output Enable/Disable)

Figure 36. Typical Output Rise Time (10%–90%,

V_DDEXT= Min) vs. Load Capacitance

Capacitive Loading

Output delays and holds are based on standard capacitive

loads: 12 pF on all pins (see Figure 33). Figure 35 and

Figure 36 show how output rise time varies with capaci-

tance. Figure 37 graphically shows how output delays and

holds vary with load capacitance. (Note that this graph or

derating does not apply to output disable delays; see Output

Disable Time on page 47.) The graphs of Figure 35,

Figure 36, and Figure 37 may not be linear outside the

ranges shown.

20.00

15.00

10.0

0

Y = 0.085526X – 3.87

5.00

30.00

25.00

0.0

0

–5.00

0

50

100

150

200

250

RISE TIME

LOAD CAPACITANCE – pF

20.00

Y = 0.086687X + 2.18

TBD

Figure 37. Typical Output Delay or Hold vs. Load

Capacitance (at Max Case Temperature)

15.00

FALL TIME

Y = 0.072781X + 1.99

10.00

Thermal Characteristics

The ADSP-21160N is specified for a case temperature

(T_CASE). To ensure that the T_CASEdata sheet specification is

not exceeded, a heatsink and/or an air flow source may be

used. Use the center block of ground pins (PBGA balls:

F7-14, G7-14, H7-14, J7-14, K7-14, L7-14, M-14, N7-14,

P7-14, R7-15) to provide thermal pathways to the printed

circuit board’s ground plane. A heatsink should be attached

to the ground plane (as close as possible to the thermal

pathways) with a thermal adhesive.

5.00

0.0

0

50

100

150

200

250

LOAD CAPACITANCE – pF

Figure 35. Typical Output Rise Time (10%–90%,

V_DDEXT= Max) vs. Load Capacitance

Environmental Conditions

The ADSP-21160NKB-95 and ADSP-21160NCB-TBD

are provided in a 400-Ball Metric PBGA (Plastic Ball Grid

Array) package.

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T_CASE= T_AMB+ (PD × θ_CA

)

• T_CASE= Case temperature (measured on top surface

of package)

• PD = Power dissipation in W (this value depends upon

the specific application; a method for calculating PD is

shown under Power Dissipation).

• θ_CA= Value from Table 31.

• θ = 6.46°C/W

JB

Table 31. Airflow Over Package Versus θ_CA

Airflow (Linear Ft./Min.)

θ_CA(°C/W)¹

0

200

400

8.7

12.13 9.86

¹θ_JC= 3.6 °C/W.

400-BALL METRIC PBGA PIN CONFIGURATIONS

Table 32 lists the pin assignments for the PBGA package,

and the pin configurations diagram on page 53 shows the

pin assignment summary.

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Table 32. 400-ball Metric PBGA Pin Assignments

Pin Name PBGA Pin# Pin Name PBGA Pin# Pin Name

PBGA Pin# Pin Name

PBGA Pin#

DATA[14] A01

DATA[13] A02

DATA[10] A03

DATA[8] A04

DATA[4] A05

DATA[2] A06

DATA[22]

DATA[16]

DATA[15]

DATA[9]

DATA[6]

DATA[3]

DATA[0]

TCK

EMU

IRQ2

FLAG3

FLAG0

NC

DT1

RCLK1

RFS0

TCLK0

L0DAT[5]

L0DAT[2]

DATA[34]

DATA[33]

DATA[27]

DATA[26]

V_DDEXT

V_DDINT

GND

V_DDINT

V_DDEXT

L1DAT[4]

L1DAT[3]

L1DAT[0]

L2DAT[7]

B01

B02

B03

B04

B05

B06

B07

B08

B09

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

F01

F02

F03

F04

F05

F06

F07

F08

F09

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

DATA[24]

DATA[18]

DATA[17]

DATA[11]

DATA[7]

DATA[5]

DATA[1]

TMS

TD0

IRQ1

FLAG2

NC

C01

C02

C03

C04

C05

C06

C07

C08

C09

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

G01

G02

G03

G04

G05

G06

G07

G08

G09

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G20

DATA[28]

DATA[25]

DATA[20]

DATA[19]

DATA[12]

V_DDEXT

V_DDINT

V_DDEXT

D01

D02

D03

D04

D05

D06

D07

D08

D09

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

H01

H02

H03

H04

H05

H06

H07

H08

H09

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

TDI

A07

A08

A09

A10

A11

A12

TRST

RESET

RPBA

IRQ0

V_DDEXT

V_DDINT

V_DDEXT

FLAG1

TIMEXP A13

NC

TFS1

RFS1

RCLK0

DT0

A14

A15

A16

A17

A18

A19

TCLK1

DR1

DR0

TFS0

L1DAT[7]

L0CLK

L0DAT[3]

L0DAT[1]

L1CLK

DATA[40]

DATA[39]

DATA[37]

DATA[36]

V_DDEXT

V_DDINT

GND

L0DAT[7]

L0DAT[6]

L0ACK

L0DAT[0]

DATA[38]

DATA[35]

DATA[32]

DATA[31]

V_DDEXT

V_DDINT

GND

V_DDINT

V_DDEXT

L0DAT[4] A20

DATA[30] E01

DATA[29] E02

DATA[23] E03

DATA[21] E04

V_DDEXT

V_DDINT

GND

V_DDINT

V_DDEXT

E05

E06

E07

E08

E09

E10

E11

E12

E13

E14

E15

E16

GND

V_DDINT

V_DDEXT

L2DAT[5]

L2ACK

L2DAT[3]

L2DAT[1]

L1DAT[6] E17

L1DAT[5] E18

L1DAT[2]

L2DAT[6]

L2DAT[4]

L2CLK

L1ACK

E19

L1DAT[1] E20

DATA[44] J01

DATA[43] J02

DATA[42] J03

DATA[41] J04

CLK_CFG_0 K01

CLKIN

L01

AV_DD

M01

DATA[46]

DATA[45]

DATA[47]

V_DDEXT

K02

K03

K04

K05

K06

K07

K08

CLK_CFG_1 L02

AGND L03

CLK_CFG_2 L04

V_DDEXT

V_DDINT

GND

CLK_CFG_3 M02

CLKOUT

NC

V_DDEXT

V_DDINT

GND

M03

M04

M05

M06

M07

M08

V_DDEXT

V_DDINT

GND

J05

J06

J07

J08

L05

L06

L07

L08

V_DDINT

GND

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Table 32. 400-ball Metric PBGA Pin Assignments (Continued)

Pin Name PBGA Pin# Pin Name PBGA Pin# Pin Name

PBGA Pin# Pin Name

PBGA Pin#

M09

M10

M11

M12

M13

M14

M15

M16

M17

M18

M19

M20

T01

T02

T03

T04

T05

T06

T07

T08

T09

GND

V_DDINT

V_DDEXT

J09

J10

J11

J12

J13

J14

J15

J16

GND

V_DDINT

V_DDEXT

K09

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19

K20

P01

P02

P03

P04

P05

P06

P07

P08

P09

P10

P11

P12

P13

P14

P15

P16

P17

P18

P19

P20

GND

V_DDINT

V_DDEXT

L09

L10

L11

L12

L13

L14

L15

L16

L17

L18

L19

L20

R01

R02

R03

R04

R05

R06

R07

R08

R09

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

GND

V_DDINT

V_DDEXT

PAGE

SBTS

PA

L3DAT[7]

DATA[56]

DATA[58]

DATA[59]

DATA[63]

V_DDEXT

V_DDINT

V_DDEXT

L4DAT[3]

L4ACK

L4CLK

L4DAT[4]

L2DAT[2] J17

L2DAT[0] J18

BR6

BR5

BR2

BR1

HBG

HBR

NC

J19

J20

N01

N02

BR4

BR3

ACK

REDY

DATA[53]

DATA[54]

DATA[57]

DATA[60]

V_DDEXT

V_DDINT

GND

V_DDEXT

DATA[49]

DATA[50]

DATA[52]

DATA[55]

V_DDEXT

V_DDINT

GND

V_DDINT

V_DDEXT

NC

DATA[48] N03

DATA[51] N04

V_DDEXT

V_DDINT

GND

V_DDINT

V_DDEXT

N05

N06

N07

N08

N09

N10

N11

N12

N13

N14

N15

N16

T10

T11

T12

T13

T14

T15

T16

T17

L3DAT[5] N17

L3DAT[6] N18

L3DAT[4] N19

L3DAT[2]

L3DAT[1]

L3DAT[3]

L3ACK

L4DAT[5]

L4DAT[6]

L4DAT[7]

L3DAT[0]

T18

T19

T20

L3CLK

N20

DATA[61] U01

DATA[62] U02

ADDR[3] U03

ADDR[2] U04

ADDR[4]

ADDR[6]

ADDR[7]

ADDR[10]

ADDR[14]

ADDR[18]

ADDR[22]

ADDR[25]

ADDR[28]

ID0

V01

V02

V03

V04

V05

V06

V07

V08

V09

V10

V11

V12

V13

V14

V15

V16

V17

ADDR[5]

ADDR[9]

ADDR[12]

ADDR[15]

ADDR[17]

ADDR[20]

ADDR[23]

ADDR[26]

ADDR[29]

ID1

ADDR[0]

BMS

MS2

CIF

RDH

W01

W02

W03

W04

W05

W06

W07

W08

W09

W10

W11

W12

W13

W14

W15

W16

W17

ADDR[8]

ADDR[11]

ADDR[13]

ADDR[16]

ADDR[19]

ADDR[21]

ADDR[24]

ADDR[27]

ADDR[30]

ADDR[31]

ID2

BRST

MS0

MS3

WRH

WRL

DMAG1

Y01

Y02

Y03

Y04

Y05

Y06

Y07

Y08

Y09

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

V_DDEXT

U05

U06

U07

U08

U09

U10

U11

U12

U13

U14

U15

U16

ADDR[1]

MS1

CS

RDL

DMAR2

L5DAT[0]

L5DAT[2]

DMAG2

LBOOT

L5DAT[7] U17

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrB

51

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

April 2002

ADSP-21160N

Table 32. 400-ball Metric PBGA Pin Assignments (Continued)

Pin Name PBGA Pin# Pin Name PBGA Pin# Pin Name

PBGA Pin# Pin Name

PBGA Pin#

Y18

Y19

L4DAT[0] U18

L4DAT[1] U19

L4DAT[2] U20

L5ACK

L5DAT[4]

L5DAT[6]

V18

V19

V20

L5DAT[1]

L5DAT[3]

L5DAT[5]

W18

W19

W20

DMAR1

EBOOT

L5CLK

Y20

400-BALL METRIC PBGA PIN CONFIGURATIONS (BOTTOM VIEW, SUMMARY)

20

18

16

14

12

10

8

6

4

2

19

17

15

13

11

7

5

3

1

9

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

K EY :

GND*

V

DDINT

A

VDD

AGND

V

I/O SIGNALS

DDEXT

NO CONNECTION

USE THE CENTER BLOCK OF GROUND PINS (PBGA BALLS: F7-14, G7-14, H7-14, J7-14,

K7-14, L7-14, M7-14, N7-14, P7-14, R7-15) TO PROVIDE THERMAL PATHWAYS TO YOUR

PRINTED CIRCUIT BOARD’S GROUND PLANE.

*

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrB

52

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

OUTLINE DIMENSIONS

April 2002

ADSP-21160N

The ADSP-21160N comes in a 27mm

؋

27mm, 400-ball

Metric PBGA package with 20 rows of balls.

400-BALL METRIC PBGA (B-400)

27.20

27.00

26.80

SQ

20 18 16 14 12 10

19 17 15 13 11

8

6

4

2

9

7

5

3

1

A

B

C

D

E

F

G

H

J

24.13

BSC

SQ

24.10

24.00

23.90

K

L

SQ

M

N

P

R

T

U

V

W

Y

1.27 (0.050)

BSC

BALL PITCH

BOTTOM VIEW

TOP VIEW

1.19

2.49

2.32

2.15

1.17

1.15

0.60

0.55

0.50

DETAIL A

0.70

0.60

0.50

NOTES:

SEATING

PLANE

0.90

0.75

0.60

1. ALL DIMENSIONS ARE IN MILLIMETERS, EXCEPT (0.050) DIMENSION AT

BALL

PITCH IS IN INCHES.

0.20 MAX

BALL DIAMETER

2. CENTER FIGURES ARE NOMINAL DIMENSIONS.

3. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.30 OF ITS IDEAL

POSITION RELATIVE TO THE PACKAGE EDGES.

4. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.15 OF ITS IDEAL

POSITION RELATIVE TO THE BALL GRID.

DETAIL A

ORDERING GUIDE

Case Temperature

Range

On-Chip

SRAM

Part Number¹

Instruction Rate

Operating Voltage

ADSP-21160NCB-TBD

ADSP-21160NKB-95

–40°C to 100°C

0°C to 85°C

TBD MHz

95 MHz

4M bits

1.9 INT/3.3 EXT V

¹B = Plastic Ball Grid Array (PBGA) package.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrB

53


型号：	ADSP-21160N
厂家：	ADI
描述：	DSP Microcomputer 微电脑DSP 电脑
文件：	总53页 (文件大小：1556K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-21160N [ADI]

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