ADSP-21161NKCAZ-100_技术文档

ADSP-21161N

KEY FEATURES (continued)

32-48, 16-48, 8-48 Execution Packing for Executing

Instruction Directly from 32-Bit, 16-Bit, or 8-Bit Wide

External Memories

1 M Bit On-Chip Dual-Ported SRAM (0.5 M Bit Block 0,

0.5 M Bit Block 1) for Independent Access by Core

Processor and DMA

200 Million Fixed-Point MACs Sustained Performance

Dual Data Address Generators (DAGs) with Modulo and

Bit-Reverse Addressing

Zero-Overhead Looping with Single-Cycle Loop Setup,

Providing Efficient Program Sequencing

IEEE 1149.1 JTAG Standard Test Access Port and On-Chip

Emulation

Single Instruction Multiple Data (SIMD) Architecture

Provides:

32-48, 16-48, 8-48, 32-32/64, 16-32/64, 8-32/64, Data

Packing for DMA Transfers Directly from 32-Bit,

16-Bit, or 8-Bit Wide External Memories to and from

Internal 32-, 48-, or 64-Bit Internal Memory

Can be Configured to have 48-Bit Wide External Data

Bus, if Link Ports are not Used. The Link Port Data

Lines are Multiplexed with the Data Lines D0 to D15

and are Enabled through Control Bits in SYSCON

SDRAM Controller for Glueless Interface to Low Cost

External Memory

Two Computational Processing Elements

Concurrent Execution—Each Processing Element

Executes the Same Instruction, but Operates on

Different Data

Zero Wait State, 100 MHz Operation for Most Accesses

Extended External Memory Banks (64 M Words) for

SDRAM Accesses

Page Sizes up to 2048 Words

Code Compatibility—At Assembly Level, Uses the

Same Instruction Set as Other SHARC DSPs

An SDRAM Controller Supports SDRAM in Any and All

Memory Banks

Support for Interface to Run at Core Clock and Half the

Core Clock Frequency

Support for 16 M Bits, 64 M Bits, 128 M Bits, and

256 M Bits with SDRAM Data Bus Configurations of

ꢀ4, ꢀ8, ꢀ16, and ꢀ32

254 Mega-Word Address Range for Off-Chip SDRAM

Memory

Multiprocessing Support Provides:

Glueless Connection for Scalable DSP Multiprocessing

Architecture

Distributed On-Chip Bus Arbitration for Parallel Bus

Connect of Up to Six ADSP-21161Ns, Global Memory,

and a Host

Two 8-Bit Wide Link Ports for Point-to-Point

Connectivity Between ADSP-21161Ns

400 M Bytes/s Transfer Rate over Parallel Bus

200 M Bytes/s Transfer Rate Over Link Ports

Serial Ports Provide:

Parallelism in Buses and Computational Units Enables:

Single-Cycle Execution (with or without SIMD) of: a

Multiply Operation, an ALU Operation, a Dual

Memory Read or Write, and an Instruction Fetch

Transfers Between Memory and Core at Up to Four

32-Bit Floating- or Fixed-Point Words Per Cycle,

Sustained 1.6 Gbytes/s Bandwidth

Accelerated FFT Butterfly Computation through a

Multiply with Add and Subtract

DMA Controller Supports:

14 Zero-Overhead DMA Channels for Transfers between

ADSP-21161N Internal Memory and External Memory,

External Peripherals, Host Processor, Serial Ports,

Link Ports, or Serial Peripheral Interface (SPI-

Compatible)

64-Bit Background DMA Transfers at Core Clock Speed,

in Parallel with Full-Speed Processor Execution

800 M Bytes/s Transfer Rate over IOP Bus

Host Processor Interface to 8-, 16-, and 32-Bit

Microprocessors; the Host Can Directly Read/Write

ADSP-21161N IOP Registers

32-Bit (or up to 48-Bit) Wide Synchronous External Port

Provides:

Glueless Connection to Asynchronous, SBSRAM and

SDRAM External Memories

Memory Interface Supports Programmable Wait State

Generation and Wait Mode for Off-Chip Memory

Up to 50 MHz Operation for Non-SDRAM Accesses

1:2, 1:3, 1:4, 1:6, 1:8 Clock into Core Clock Frequency

Multiply Ratios

24-Bit Address, 32-Bit Data Bus. 16 Additional Data

Lines via Multiplexed Link Port Data Pins Allow

Complete 48-Bit Wide Data Bus for Single-Cycle

External Instruction Execution

Four 50 M Bit/s Synchronous Serial Ports with

Companding Hardware

8 Bidirectional Serial Data Pins, Configurable as Either a

Transmitter or Receiver

I²S Support, Programmable Direction for 8

Simultaneous Receive and Transmit Channels, or Up

to Either 16 Transmit Channels or 16 Receive

Channels

128 Channel TDM Support for T1 and E1 Interfaces

Companding Selection on a Per Channel Basis in TDM

Mode

Serial Peripheral Interface (SPI)

Slave Serial Boot through SPI from a Master SPI Device

Full-Duplex Operation

Master-Slave Mode Multimaster Support

Open-Drain Outputs

Programmable Baud Rates, Clock Polarities and Phases

12 Programmable I/O Pins

Direct Reads and Writes of IOP Registers from Host or

Other 21161N DSPs

62.7 Mega-Word Address Range for Off-Chip SRAM and

SBSRAM Memories

1 Programmable Timer

–2–

REV. A

ADSP-21161N

TABLE OF CONTENTS

SPI Interface Specifications . . . . . . . . . . . . . . . . . 47

JTAG Test Access Port and Emulation . . . . . . . . 50

Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . 51

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Output Enable Time . . . . . . . . . . . . . . . . . . . . . . 51

Output Disable Time . . . . . . . . . . . . . . . . . . . . . 51

Example System Hold Time Calculation . . . . . . . 51

Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . 52

Environmental Conditions . . . . . . . . . . . . . . . . . . . 52

Thermal Characteristics . . . . . . . . . . . . . . . . . . . 52

225-BALL METRIC MBGA

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 3

ADSP-21161N Family Core Architecture . . . . . . . . . 5

SIMD Computational Engine . . . . . . . . . . . . . . . . 5

Independent, Parallel Computation Units . . . . . . . 5

Data Register File . . . . . . . . . . . . . . . . . . . . . . . . . 5

Single-Cycle Fetch of Instruction and

Four Operands . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . 5

Data Address Generators With Hardware Circular

Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Flexible Instruction Set . . . . . . . . . . . . . . . . . . . . . 5

ADSP-21161N Memory and I/O Interface Features . 5

Dual-Ported On-Chip Memory . . . . . . . . . . . . . . . 5

Off-Chip Memory and Peripherals Interface . . . . . 6

SDRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . 6

Target Board JTAG Emulator Connector . . . . . . . 7

DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Multiprocessing . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Link Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Serial Peripheral (Compatible) Interface . . . . . . . . 9

Host Processor Interface . . . . . . . . . . . . . . . . . . . . 9

General-Purpose I/O Ports . . . . . . . . . . . . . . . . . . . 9

Program Booting . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Phase-Locked Loop and Crystal Double Enable . . 9

Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Designing an Emulator-Compatible

PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . 53

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . 55

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . 55

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

GENERAL DESCRIPTION

The ADSP-21161N SHARC DSP is the first low cost derivative

of the ADSP-21160 featuring Analog Devices Super Harvard

Architecture. Easing portability, the ADSP-21161N is source

code compatible with the ADSP-21160 and with first generation

ADSP-2106x SHARCs in SISD (Single Instruction, Single

Data) mode. Like other SHARC DSPs, the ADSP-21161N is a

32-bit processor that is optimized for high performance DSP

applications. The ADSP-21161N includes a 100 MHz core, a

dual-ported on-chip SRAM, an integrated I/O processor with

multiprocessingsupport,andmultipleinternalbusestoeliminate

I/O bottlenecks.

DSP Board (Target) . . . . . . . . . . . . . . . . . . . . . 10

Additional Information . . . . . . . . . . . . . . . . . . . . . . 11

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . 12

BOOT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 18

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . 19

ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . 19

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . 20

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . 21

Power-up Sequencing – Silicon

As was first offered in the ADSP-21160, the ADSP-21161N

offers a Single-Instruction-Multiple-Data (SIMD) architecture.

Using two computational units (ADSP-2106x SHARCs have

one), the ADSP-21161N can double cycle performance versus

the ADSP-2106x on a range of DSP algorithms.

Fabricated in a state of the art, high speed, low power CMOS

process, the ADSP-21161N has a 10 ns instruction cycle time.

With its SIMD computational hardware running at 100 MHz,

the ADSP-21161Ncan perform600 million math operationsper

second. Table 1 shows performance benchmarks for the

ADSP-21161N.

Revision 0.3, 1.0, 1.1 . . . . . . . . . . . . . . . . . . . . 22

Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Memory Read – Bus Master . . . . . . . . . . . . . . . . 27

Memory Write – Bus Master . . . . . . . . . . . . . . . . 28

Synchronous Read/Write – Bus Master . . . . . . . . 29

Synchronous Read/Write – Bus Slave . . . . . . . . . . 30

Host Bus Request . . . . . . . . . . . . . . . . . . . . . . . . 31

Asynchronous Read/Write –

Host to ADSP-21161N . . . . . . . . . . . . . . . . . . 33

Three-State Timing – Bus Master, Bus Slave . . . . 35

DMA Handshake . . . . . . . . . . . . . . . . . . . . . . . . 37

SDRAM Interface – Bus Master . . . . . . . . . . . . . 39

Link Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 1. Benchmarks (at 100 MHz)

Speed

Benchmark Algorithm

(at 100 MHz)

1024 Point Complex FFT

(Radix 4, with reversal)

FIR Filter (per tap)¹

IIR Filter (per biquad)¹

Matrix Multiply (pipelined)

[3 × 3] × [3 × 1]

171 µs

5 ns

40 ns¹

30 ns

[4 × 4] × [4 × 1]

Divide (y/x)

Inverse Square Root

DMA Transfers

37 ns

60 ns¹

40 ns¹

800 M bytes/s

¹Specified in SISD mode. Using SIMD, the same benchmark applies for

two sets of computations. For example, two sets of biquad operations can

be performed in the same amount of time as the SISD mode benchmark.

REV. A

–3–

ADSP-21161N

The ADSP-21161N continues SHARC’s industry-leading

standardsofintegrationforDSPs,combiningahighperformance

32-bit DSP core with integrated, on-chip system features. These

features include a 1 M bit dual ported SRAM memory, host

processor interface, I/O processor that supports 14 DMA

channels, four serial ports, two link ports, SDRAM controller,

SPIinterface, externalparallelbus, andgluelessmultiprocessing.

• On-Chip SRAM (1 M bit)

• SDRAM Controller for glueless interface to SDRAMs

• External port that supports:

• Interfacing to off-chip memory peripherals

• Glueless multiprocessing support for six ADSP-

21161N SHARCs

The block diagram of the ADSP-21161N on Page 1 illustrates

the following architectural features:

• Host port read/write of IOP registers

• DMA controller

• Two processing elements, each made up of an ALU, Mul-

tiplier, Shifter, and Data Register File

• Four serial ports

• Two link ports

• Data Address Generators (DAG1, DAG2)

• Program sequencer with instruction cache

• SPI compatible interface

• JTAG test access port

• 12 General-Purpose I/O Pins

• PM and DM buses capable of supporting four 32-bit data

transfers between memory and the core every core

processor cycle

Figure 1showsatypicalsingle-processorsystem. Amultiprocess-

ing system appears in Figure 4 on Page 8.

• Interval timer

ADSP-21161N

CLKIN

CLOCK

XTAL

2

CLK_CFG1-0

BMS

CLKDBL

EBOOT

CS

BOOT

ADDR

DATA

EPROM

(OPTIONAL)

LBOOT

IRQ2-0

BRST

3

12

FLAG11-0

ADDR23-0

ADDR

TIMEXP

RPBA

ID2-0

MEMORY

AND

PERIPHERALS

DATA47-16

RD

DATA

OE

WE

LINK

DEVICES

(2 MAX)

WR

LXCLK

(OPTIONAL)

ACK

MS3-0

ACK

CS

LXACK

(OPTIONAL)

LXDAT7-0

RAS

CAS

RAS

CAS

SCLK0

FS0

D0A

D0B

SERIAL

DEVICE

(OPTIONAL)

SDRAM

(OPTIONAL)

DQM

SDWE

WE

SDCLK1-0

CLK

SCLK1

FS1

D1A

SERIAL

DEVICE

(OPTIONAL)

SDCKE

SDA10

CKE

A10

CS

D1B

ADDR

DATA

SCLK2

FS2

D2A

D2B

SERIAL

DEVICE

(OPTIONAL)

CLKOUT

DMAR2-1

DMA DEVICE

(OPTIONAL)

DMAG2-1

SCLK3

FS3

D3A

D3B

SERIAL

DEVICE

(OPTIONAL)

DATA

CS

HOST

HBR

PROCESSOR

INTERFACE

(OPTIONAL)

HBG

SPICLK

SPIDS

SPI

REDY

COMPATIBLE

DEVICE

(HOST OR SLAVE)

(OPTIONAL)

BR6-1

ADDR

DATA

MOSI

MISO

PA

SBTS

RESET RSTOUT JTAG

7

Figure 1. System Diagram

–4–

REV. A

ADSP-21161N

ADSP-21161N Family Core Architecture

the processor can simultaneously fetch four operands (two over

each data bus) and an instruction (from the cache), all in a

single cycle.

The ADSP-21161N includes the following architectural features

of the ADSP-2116x family core. The ADSP-21161N is code

compatible at the assembly level with the ADSP-21160, ADSP-

21060, ADSP-21061, ADSP-21062, and ADSP-21065L.

Instruction Cache

The ADSP-21161N includes an on-chip instruction cache that

enables three-bus operation for fetching an instruction and four

data values. The cache is selective—only the instructions whose

fetchesconflictwithPMbusdataaccessesarecached. Thiscache

enables full-speed execution of core, looped operations such as

digitalfiltermultiply-accumulates, andFFTbutterflyprocessing.

SIMD Computational Engine

The ADSP-21161N contains two computational processing

elements that operate as a Single Instruction Multiple Data

(SIMD) engine. The processing elements are referred to as PEX

and PEY, and each contains an ALU, multiplier, shifter, and

register file. PEX is always active, and PEY may be enabled by

setting the PEYEN mode bit in the MODE1 register. When this

mode is enabled, the same instruction is executed in both pro-

cessing elements, but each processing element operates on

different data. This architecture is efficient at executing math

intensive DSP algorithms.

Data Address Generators With Hardware Circular

Buffers

The ADSP-21161N’s two data address generators (DAGs) are

used for indirect addressing and implementing circular data

buffersinhardware.Circularbuffersallowefficientprogramming

of delay lines and other data structures required in digital signal

processing, and are commonly used in digital filters and Fourier

transforms. The two DAGs of the ADSP-21161N contain suffi-

cient registers to allow the creation of up to 32 circular buffers

(16 primary register sets, 16 secondary). The DAGs automati-

cally handle address pointer wrap-around, reduce overhead,

increase performance, and simplify implementation. Circular

buffers can start and end at any memory location.

Entering SIMD mode also has an effect on the way data is trans-

ferred between memory and the processing elements. When in

SIMD mode, twice the data bandwidth is required to sustain

computational operation in the processing elements. Because of

this requirement, entering SIMD mode also doubles the

bandwidth between memory and the processing elements. When

using the DAGs to transfer data in SIMD mode, two data values

are transferred with each access of memory or the register file.

Flexible Instruction Set

SIMD is supported only for internal memory accesses and is not

supported for off-chip accesses.

The 48-bit instruction word accommodates a variety of parallel

operations, for concise programming. For example, the ADSP-

21161N can conditionally execute a multiply, an add, and a

subtract in both processing elements, while branching, all in a

single instruction.

Independent, Parallel Computation Units

Within each processing element is a set of computational units.

The computational units consist of an arithmetic/logic unit

(ALU), multiplier, and shifter. These units perform single-cycle

instructions. The three units within each processing element are

arranged in parallel, maximizing computational throughput.

Single multifunction instructions execute parallel ALU and mul-

tiplier operations. In SIMD mode, the parallel ALU and

multiplier operations occur in both processing elements. These

computation units support IEEE 32-bit single-precision floating-

point, 40-bit extended precision floating-point, and 32-bit

fixed-point data formats.

ADSP-21161N Memory and I/O Interface Features

The ADSP-21161N adds the following architectural features to

the ADSP-2116x family core:

Dual-Ported On-Chip Memory

The ADSP-21161N contains one megabit of on-chip SRAM,

organized as two blocks of 0.5 M bits. Each block can be config-

ured for different combinations of code and data storage. Each

memory block is dual-ported for single-cycle, independent

accesses by the core processor and I/O processor. The dual-

portedmemoryincombinationwiththreeseparateon-chipbuses

allow two data transfers from the core and one from the I/O

processor, in a single cycle. On the ADSP-21161N, the memory

can be configured as a maximum of 32K words of 32-bit data,

64K words of 16-bit data, 21K words of 48-bit instructions (or

40-bit data), or combinations of different word sizes up to one

megabit. All of the memory can be accessed as 16-bit, 32-bit,

48-bit, or 64-bit words. A 16-bit floating-point storage format is

supported that effectively doubles the amount of data that may

be stored on-chip. Conversion between the 32-bit floating-point

and 16-bit floating-point formats is done in a single instruction.

While each memory block can store combinations of code and

data, accesses are most efficient when one block stores data using

the DM bus for transfers, and the other block stores instructions

and data using the PM bus for transfers. Using the DM bus and

Data Register File

A general-purpose data register file is contained in each process-

ing element. The register files transfer data between the

computation units and the data buses, and store intermediate

results. These 10-port, 32-register (16 primary, 16 secondary)

registerfiles,combinedwiththeADSP-2116xenhancedHarvard

architecture, allow unconstrained data flow between computa-

tionunitsandinternalmemory. TheregistersinPEXarereferred

to as R0–R15 and in PEY as S0–S15.

Single-Cycle Fetch of Instruction and Four Operands

The ADSP-21161N features an enhanced Harvard architecture

in which the data memory (DM) bus transfers data and the

program memory (PM) bus transfers both instructions and data

(see Figure 1 on Page 4). With the ADSP-21161N’s separate

program and data memory buses and on-chip instruction cache,

REV. A

–5–

ADSP-21161N

PM bus, with one dedicated to each memory block, assures

single-cycle execution with two data transfers. In this case, the

instruction must be available in the cache.

ADDRESS

0x0020 0000

0x0000 0000 - 0x0001 FFFF

IOP REGISTERS

0x0002 0000 - 0x0002 1FFF (BLK 0)

0x0002 8000 - 0x0002 9FFF (BLK 1)

LONG WORD ADDRESSING

NORMAL WORD ADDRESSING

INTERNAL

MEMORY

SPACE

MS0

0x0004 0000 - 0x0004 3FFF (BLK 0)

0x0005 0000 - 0x0005 3FFF (BLK 1)

BANK

0

0x00FF FFFF (NON-SDRAM)

0x03FF FFFF (SDRAM)

0x0008 0000 - 0x0008 7FFF (BLK 0)

0x000A 0000 - 0x000A 7FFF (BLK 1)

SHORT WORD ADDRESSING

0x0400 0000

IOP REGISTERS OF ADSP-21161N

WITH ID = 001

0x0010 0000 - 0x0011 FFFF

0x0012 0000 - 0x0013 FFFF

0x0014 0000 - 0x0015 FFFF

IOP REGISTERS OF ADSP-21161N

WITH ID = 010

MS1

BANK

1

IOP REGISTERS OF ADSP-21161N

WITH ID = 011

0x04FF FFFF (NON-SDRAM)

0x07FF FFFF (SDRAM)

MULTIPROCESSOR

MEMORY

SPACE

IOP REGISTERS OF ADSP-21161N

WITH ID = 100

0x0016 0000 - 0x0017 FFFF

0x0018 0000 - 0x0019 FFFF

0x0800 0000

IOP REGISTERS OF ADSP-21161N

WITH ID = 101

MS2

BANK

2

IOP REGISTERS OF ADSP-21161N

WITH ID = 110

0x001A 0000 - 0x001B FFFF

0x001C 0000

0x08FF FFFF (NON-SDRAM)

0x0BFF FFFF (SDRAM)

RESERVED

0x0C00 0000

0x001F FFFF

MS3

BANK

3

EXTERNAL MEMORY SPACE

0x0CFF FFFF (NON-SDRAM)

0x0FFF FFFF (SDRAM)

NOTE: BANK SIZES ARE FIXED

Figure 2. Memory Map

Off-Chip Memory and Peripherals Interface

The externalport supports asynchronous, synchronous, and syn-

chronous burst accesses. Synchronous burst SRAM can be

interfaced gluelessly. The ADSP-21161N also can interface glue-

lessly to SDRAM. Addressing of external memory devices is

facilitated by on-chip decoding of high-order address lines to

generate memory bank select signals. The ADSP-21161N

provides programmable memory wait states and external

memory acknowledge controls to allow interfacing to memory

and peripherals with variable access, hold, and disable time

requirements.

The ADSP-21161N’s external port provides the processor’s

interface to off-chip memory and peripherals. The 62.7-M word

off-chip address space (254.7-M word if all SDRAM) is included

in the ADSP-21161N’s unified address space. The separate on-

chip buses—for PM addresses, PM data, DM addresses, DM

data,I/Oaddresses,andI/Odata—aremultiplexedattheexternal

port to create an external system bus with a single 24-bit address

bus and asingle32-bit databus. Everyaccess to externalmemory

is based on an address that fetches a 32-bit word. When fetching

an instruction from external memory, two 32-bit data locations

arebeingaccessedforpackedinstructions. Unusedlinkportlines

SDRAM Interface

The SDRAM interface enables the ADSP-21161N to transfer

data to and from synchronous DRAM (SDRAM) at the core

clock frequency or at one-half the core clock frequency. The

can also be used as additional data lines DATA15–DATA0,

allowing single-cycle execution of instructions from external

memory, at up to 100 MHz. Figure 3 on Page 7 shows the

alignment of various accesses to external memory.

–6–

REV. A

ADSP-21161N

synchronous approach, coupled with the core clock frequency,

supports data transfer at a high throughput—up to 400 M bytes/s

for 32-bit transfers and 600 M bytes/s for 48-bit transfers.

Other DMA features include interrupt generation upon comple-

tion of DMA transfers, and DMA chaining for automatic linked

DMA transfers.

The SDRAM interface provides a glueless interface with

standard SDRAMs—16 Mb, 64 Mb, 128 Mb, and 256 Mb—

and includes options to support additional buffers between the

ADSP-21161N and SDRAM. The SDRAM interface is

extremely flexible and provides capability for connecting

SDRAMs to any one of the ADSP-21161N’s four external

memory banks, with up to all four banks mapped to SDRAM.

DATA47–16

32 31

DATA1 5–0

47

40 39

24 23

16 15

L1DATA7–0

DATA15-8

8

7

0

L0DATA7–0

DATA7–0

PROM

BO O T

8-BIT PACKED DMA DATA

8-BIT PACKED INSTRUCTION

EXECUTION

Systems with several SDRAM devices connected in parallel may

require buffering to meet overall system timing requirements.

The ADSP-21161N supports pipelining of the address and

control signals to enable such buffering between itself and

multiple SDRAM devices.

16-BIT PACKED DMA DATA

16-BIT PACKED INSTRUC-

TION EXECUTION

FLOAT OR FIXED, D31–D0,

32-BIT PACKED

32-BIT PACKED INSTRUC-

TION

Target Board JTAG Emulator Connector

48-BIT INSTRUCTION FETCH

(NO PACKING)

Analog Devices DSP Tools product line of JTAG emulators uses

the IEEE 1149.1 JTAG test access port of the ADSP-21161N

processor to monitor and control the target board processor

during emulation. Analog Devices DSP Tools product line of

JTAG emulators provides emulation at full processor speed,

allowing inspection and modification of memory, registers, and

processorstacks. Theprocessor’sJTAGinterfaceensuresthatthe

emulator will not affect target system loading or timing.

NOTE:

EXTRA DATA LINES DATA15–0 ARE ONLY ACCESSIBLE IF LINK PORTS

ARE DISABLED. ENABLE THESE ADDITIONAL DATA LINKS BY SELECT-

ING IPACK1–0 = 01 IN SYSCON.

Figure 3. External Data Alignment Options

Multiprocessing

The ADSP-21161N offers powerful features tailored to

multiprocessing DSP systems. The external port and link ports

provide integrated glueless multiprocessing support.

For complete information on SHARC Analog Devices DSP

Tools product line of JTAG emulator operation, see the appro-

priate Emulator Hardware User’s Guide. For detailed infor-

mation on the interfacing of Analog Devices JTAG emulators

with Analog Devices DSP products with JTAG emulation ports,

please refer to Engineer to Engineer Note EE-68: Analog Devices

JTAGEmulation Technical Reference. Bothofthese documents can

be found on the Analog Devices website:

The external port supports a unified address space (see Figure 2

on Page 6) that enables direct interprocessor accesses of each

ADSP-21161N’s internal memory-mapped (I/O processor) reg-

isters. All other internal memory can be indirectly accessed via

DMA transfers initiated via the programming of the IOP DMA

parameter and control registers. Distributed bus arbitration logic

is included on-chip for simple, glueless connection of systems

containing up to six ADSP-21161Ns and a host processor.

Master processor change over incurs only one cycle of overhead.

Bus arbitration is selectable as either fixed or rotating priority.

Bus lock enables indivisible read-modify-write sequences for

semaphores. A vector interrupt is provided for interprocessor

commands. Maximum throughput for interprocessor data

transfer is 400 M bytes/s over the external port.

http://www.analog.com/dsp/tech_docs.html

DMA Controller

The ADSP-21161N’s on-chip DMA controller enables zero-

overhead data transfers without processor intervention. The

DMA controller operates independently and invisibly to the

processor core, allowing DMA operations to occur while the core

is simultaneously executing its program instructions. DMA

transfers can occur between the ADSP-21161N’s internal

memory and external memory, external peripherals, or a host

processor. DMA transfers can also occur between the ADSP-

21161N’s internal memory and its serial ports, link ports, or the

SPI-compatible (Serial Peripheral Interface) port. External bus

packing and unpacking of 32-, 48-, or 64-bit words in internal

memory is performed during DMA transfers from either 8-,

16-, or 32-bitwideexternalmemory. Fourteen channelsofDMA

are available on the ADSP-21161N—two are shared between the

SPI interface and the link ports, eight via the serial ports, and

four via the processor’s external port (for host processor, other

ADSP-21161Ns, memory, or I/O transfers). Programs can be

downloaded to the ADSP-21161N using DMA transfers. Asyn-

chronous off-chip peripherals can control two DMA channels

Two link ports provide a second method of multiprocessing com-

munications. Each link port can support communications to

another ADSP-21161N. The ADSP-21161N, running at

100 MHz, has a maximum throughput for interprocessor com-

munications over the links of 200 M bytes/s. The link ports and

cluster multiprocessing can be used concurrently or

independently.

Link Ports

The ADSP-21161N features two 8-bit link ports that provide

additional I/O capabilities. With the capability of running at

100 MHz, each link port can support 100 M bytes/s. Link port

I/O is especially useful for point-to-point interprocessor commu-

nication in multiprocessing systems. The link ports can operate

independently and simultaneously, with a maximum data

throughput of 200 M bytes/s. Link port data is packed into

48- or 32-bit words and can be directly read by the core processor

using DMA Request/Grant lines (DMAR2–1, DMAG2–1).

REV. A

–7–

ADSP-21161N

CLOCK

RESET

ADSP-21161N #4

ADSP-21161N #3

ADDR23-0

CLKIN

DATA47-16

RESET

3

ID2-0

CONTROL

ADSP-21161N #2

CLKIN

ADDR23-0

DATA47-16

RESET

ID2-0

2

CONTROL

ADDR

DATA

BOOT

EPROM

(OPTIONAL)

ADSP-21161N #1

CS

BMS

ADDR23-0

ADDR

DATA

CLKIN

RESET

GLOBAL

MEMORY

AND

DATA47-16

RD

OE

PERIPHERALS

(OPTIONAL)

1

ID2-0

WR

ACK

WE

ACK

CS

MS3-0

SBTS

CS

HOST

HBR

HBG

REDY

PROCESSOR

INTERFACE

(OPTIONAL)

ADDR

DATA

BR6-2

BR1

RAS

CAS

RAS

CAS

DQM

SDWE

DQM

WE

SDCLK1-0

CLK

SDCKE

CKE

SDRAM

(OPTIONAL)

SDA10

A10

CS

ADDR

DATA

Figure 4. Shared Memory Multiprocessing System

Serial Ports

or DMA-transferred to on-chip memory. Each link port has its

own double-buffered input and output registers. Clock/acknowl-

edge handshaking controls link port transfers. Transfers are

programmable as either transmit or receive.

The ADSP-21161N features four synchronous serial ports that

provide an inexpensive interface to a wide variety of digital and

mixed-signal peripheral devices. Each serial port is made up of

two data lines, a clock and frame sync. The data lines can be

programmed to either transmit or receive.

–8–

REV. A

ADSP-21161N

Program Booting

The serial ports operate at up to half the clock rate of the core,

providingeachwithamaximumdatarateof50Mbit/s.Theserial

data pins are programmable as either a transmitter or receiver,

providinggreaterflexibilityforserialcommunications.Serialport

data can be automatically transferred to and from on-chip

memory via a dedicated DMA. Each of the serial ports features

a Time Division Multiplex (TDM) multichannel mode, where

two serial ports are TDM transmitters and two serial ports are

TDM receivers (SPORT0 Rx paired with SPORT2 Tx,

SPORT1 Rx paired with SPORT3 Tx). Each of the serial ports

also support the I²S protocol (an industry standard interface

commonly used by audio codecs, ADCs and DACs), with two

data pins, allowing four I²S channels (using two I²S stereo

devices)perserialport, withamaximumofupto16I²Schannels.

The serial ports permit little-endian or big-endian transmission

formats and word lengths selectable from 3 bits to 32 bits. For

I²S mode, data-word lengths are selectable between 8 bits and 32

bits. Serial ports offer selectable synchronization and transmit

modes as well asoptionalµ-law or A-law companding. Serial port

clocks and frame syncs can be internally or externally generated.

The internal memory of the ADSP-21161N can be booted at

system power-up from either an 8-bit EPROM, a host processor,

the SPI interface, or through one of the link ports. Selection of

the boot source is controlled by the Boot Memory Select (BMS),

EBOOT (EPROM Boot), and Link/Host Boot (LBOOT) pins.

8-, 16-, or 32-bit host processors can also be used for booting.

Phase-Locked Loop and Crystal Double Enable

The ADSP-21161N uses an on-chip Phase-Locked Loop (PLL)

to generate the internal clock for the core. The CLK_CFG1–0

pins are used to select ratios of 2:1, 3:1, and 4:1. In addition to

the PLL ratios, the CLKDBL pin can be used for more clock

ratio options. The (1×/2× CLKIN) rate set by the CLKDBL

pin determines the rate of the PLL input clock and the rate at

which the external port operates. With the combination of

CLK_CFG1–0 and CLKDBL, ratios of 2:1, 3:1, 4:1, 6:1, and

8:1 between the core and CLKIN are supported. See also

Figure 10 on Page 20.

Power Supplies

The ADSP-21161N has separate power supply connections for

the analog (AV_DD/AGND), internal (V_DDINT), and external

(V_DDEXT) power supplies. The internal and analog supplies must

meet the 1.8 V requirement. The external supply must meet the

3.3 V requirement. All external supply pins must be connected

to the same supply.

Serial Peripheral (Compatible) Interface

Serial Peripheral Interface (SPI) is an industry standard synchro-

nous serial link, enabling the ADSP-21161N SPI-compatible

port to communicate with other SPI-compatible devices. SPI is

a 4-wire interface consisting of two data pins, one device select

pin, and one clock pin. It is a full-duplex synchronous serial

interface, supporting both master and slave modes. The SPI port

can operate in a multimaster environment by interfacing with up

to four other SPI-compatible devices, either acting as a master or

slave device. The ADSP-21161N SPI-compatible peripheral

implementation also features programmable baud rate and clock

phase/polarities. The ADSP-21161N SPI-compatible port uses

open drain drivers to support a multimaster configuration and to

avoid data contention.

Note that the analog supply (AV_DD) powers the ADSP-21161N’s

clock generator PLL. To produce a stable clock, provide an

external circuit to filter the power input to the AV_DDpin. Place

the filter as close as possible to the pin. For an example circuit,

see Figure 5. To prevent noise coupling, use a wide trace for the

analog ground (AGND) signal and install a decoupling capacitor

as close as possible to the pin.

10 ꢁ

AV

V

Host Processor Interface

DD

DDINT

0.01ꢂF

0.1ꢂF

The ADSP-21161N host interface enables easy connection to

standard 8-bit, 16-bit, or 32-bit microprocessor buses with little

additional hardware required. The host interface is accessed

through the ADSP-21161N’s external port. Four channels of

DMA are available for the host interface; code and data transfers

areaccomplishedwithlowsoftwareoverhead.Thehostprocessor

requests the ADSP-21161N’s external bus with the host bus

request (HBR), host bus grant (HBG), and chip select (CS)

signals. The host can directly read and write the internal IOP

registersoftheADSP-21161N, andcanaccesstheDMAchannel

setup and message registers. DMA setup via a host would allow

it to access any internal memory address via DMA transfers.

Vector interrupt support provides efficient execution of host

commands.

AGND

Figure 5. Analog Power (AV_DD) Filter Circuit

Development Tools

The ADSP-21161N is supported with a complete set of software

and hardware development tools, including Analog Devices

emulators and VisualDSP++¹development environment. The

sameemulatorhardwarethatsupportsotherADSP-21xxxDSPs,

also fully emulates the ADSP-21161N.

The VisualDSP++ project management environment lets pro-

grammers develop and debug an application. This environment

includes an easy-to-use assembler that is based on an algebraic

syntax; an archiver (librarian/library builder), a linker, a loader,

General-Purpose I/O Ports

The ADSP-21161N also contains 12 programmable, general

purpose I/O pins that can function as either input or output. As

output, these pins can signal peripheral devices; as input, these

pins can provide the test for conditional branching.

¹VisualDSP++ is a registered trademark of Analog Devices, Inc.

REV. A

–9–

ADSP-21161N

a cycle-accurate instruction-level simulator, a C/C++ compiler,

and a C/C++ run-time library that includes DSP and mathemat-

ical functions. Two key points for these tools are:

uses the TAP to access the internal features of the DSP, allowing

the developer to load code, set breakpoints, observe variables,

observememory,andexamineregisters.TheDSPmustbehalted

to send data and commands, but once an operation has been

completed by the emulator, the DSP system is set running at full

speed with no impact on system timing.

• Compiled ADSP-21161N C/C++ code efficiency—The

compiler has been developed for efficient translation of

C/C++ code to ADSP-21161N assembly. The DSP has

architectural features that improve the efficiency of

compiled C/C++ code.

To use these emulators, the target’s design must include the

interface between an Analog Devices JTAG DSP and the

emulation header on a custom DSP target board.

• ADSP-2106x family code compatibility—The assembler

has legacy features to ease the conversion of existing

ADSP-2106x applications to the ADSP-21161N.

Target Board Header

The emulator interface to an Analog Devices JTAG DSP is a

14-pin header, as shown in Figure 6. The customer must supply

this header on the target board in order to communicate with the

emulator. The interface consists of a standard dual row 0.025"

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved

source and object information)

square post header, set on 0.1"

× 0.1" spacing, with a minimum

post length of 0.235". Pin 3 is the key position used to prevent

the pod from being inserted backwards. This pin must be clipped

on the target board.

• Insert break points

• Set conditional breakpoints on registers, memory, and

stacks

Also, theclearance (length, width, and height)around theheader

must be considered. Leave a clearance of at least 0.15" and 0.10"

around the length and width of the header, and reserve a height

clearance to attach and detach the pod connector.

• Trace instruction execution

• Perform linear or statistical profiling of program

execution

• Fill, dump, and graphically plot the contents of memory

• Source level debugging

As can be seen in Figure 6, there are two sets of signals on the

header. There are the standard JTAG signals TMS, TCK, TDI,

TDO, TRST, and EMU used for emulation purposes (via an

emulator). There are also secondary JTAG signals BTMS,

BTCK, BTDI, and BTRST that are optionally used for board-

level (boundary scan) testing.

• Create custom debugger windows

The VisualDSP++ IDE lets programmers define and manage

DSP software development. Its dialog boxes and property pages

let programmers configure and manage all of the ADSP-21xxx

development tools, including the syntax highlighting in the

VisualDSP++ editor. This capability permits:

1

2

• Controlling how the development tools process inputs

GND

EMU

and generate outputs.

3

5

4

6

KEY (NO PIN)

• Maintaining a one-to-one correspondence with the tool’s

command line switches.

GND

BTMS

BTCK

TMS

TCK

Analog Devices DSP emulators use the IEEE 1149.1 JTAG test

access port of the ADSP-21161N processor to monitor and

control the target board processor during emulation. The

emulator provides full-speed emulation, allowing inspection and

modification of memory, registers, and processor stacks. Nonin-

trusivein-circuitemulationisassuredbytheuseoftheprocessor’s

JTAG interface—the emulator does not affect target system

loading or timing.

7

9

8

10

12

BTRST

TRST

11

BTDI

TDI

13

14

GND

TDO

In addition to the software and hardware development tools

available from Analog Devices, third parties provide a wide range

of tools supporting the ADSP-21xxx processor family. Hardware

tools include ADSP-21xxx PC plug-in cards. Third Party

softwaretoolsincludeDSPlibraries,real-timeoperatingsystems,

and block diagram design tools.

TOP VIEW

Figure 6. JTAG Target Board Connector for JTAG

Equipped Analog Devices DSP (Jumpers in Place)

Whentheemulatorisnotconnectedtothisheader,placejumpers

across BTMS, BTCK, BTRST, andBTDI as shownin Figure 7.

This holds the JTAG signals in the correct state to allow the DSP

to run free. Remove all the jumpers when connecting the

emulator to the JTAG header.

Designing an Emulator-Compatible DSP Board

(Target)

The Analog Devices DSP Tools family of emulators are tools that

every DSP developer needs to test and debug hardware and

software systems. Analog Devices has supplied an IEEE 1149.1

JTAG Test Access Port (TAP) on each JTAG DSP. The emulator

–10–

REV. A

ADSP-21161N

1

3

5

2

4

6

EMU

GND

TMS

GND

KEY (NO PIN)

BTMS

0.64"

7

9

8

BTCK

TCK

0.88"

10

12

0.24"

BTRST

TRST

9

11

Figure 8. JTAG Pod Connector Dimensions

BTDI

GND

TDI

13

14

TDO

TOP VIEW

0.10"

Figure 7. JTAG Target Board Connector with No

Local Boundary Scan

0.15"

JTAG Emulator Pod Connector

Figure 9. JTAG Pod Connector Keep-Out Area

Figure 8detailsthedimensions of the JTAG pod connector atthe

14-pin target end. Figure 9 displays the keep-out area for a target

board header. The keep-out area enables the pod connector to

properly seat onto the target board header. This board area

shouldcontainnocomponents(chips, resistors, capacitors,etc.).

The dimensions are referenced to the center of the 0.025" square

post pin.

the EE-68: Analog Devices JTAG Emulation Technical Reference on

the Analog Devices website (www.analog.com)—use site search

on “EE-68”. This document is updated regularly to keep pace

with improvements to emulator support.

Additional Information

ThisdatasheetprovidesageneraloverviewoftheADSP-21161N

architecture and functionality. For detailed information on the

ADSP-2116x Family core architecture and instruction set, refer

to the ADSP-21161 SHARC DSP Hardware Reference and the

Design-for-Emulation Circuit Information

For details on target board design issues including mechanical

layout, singleprocessorconnections, multiprocessorscanchains,

signal buffering, signal termination, and emulator pod logic, see

ADSP-21160 SHARC DSP Instruction Set Reference

.

REV. A

–11–

ADSP-21161N

PIN FUNCTION DESCRIPTIONS

The following symbols appear in the Type column of Table 2:

A = Asynchronous, G = Ground, I = Input, O = Output,

P = Power Supply, S = Synchronous, (A/D) = Active Drive,

(O/D) = Open Drain, and T = Three-State (when SBTS is

asserted or when the ADSP-21161N is a bus slave).

ADSP-21161N pin definitions are listed below. Inputs identified

as synchronous (S) must meet timing requirements with respect

to CLKIN (or with respect to TCK for TMS, TDI). Inputs

identified as asynchronous (A) can be asserted asynchronously

to CLKIN (or to TCK for TRST).Tie or pull unused inputs to

V_DDEXTor GND, except for the following:

Unlike previous SHARC processors, the ADSP-21161N

contains internal series resistance equivalent to 50

Ω on all

• ADDR23–0, DATA47–0, BRST, CLKOUT (Note:

These pins have a logic-level hold circuit enabled on the

ADSP-21161N DSP with ID2–0 = 00x.)

input/output drivers except the CLKIN and XTAL pins.

Therefore, for traces longer than six inches, external series

resistors on control, data, clock, or frame sync pins are not

required to dampen reflections from transmission line effects for

point-to-point connections. However, for more complex

networks such as a star configuration, series termination is still

recommended.

• PA, ACK, RD, WR, DMARx, DMAGx, (ID2–0 = 00x)

(Note: These pins have a pull-up enabled on the ADSP-

21161N DSP with ID2–0 = 00x.)

• LxCLK, LxACK, LxDAT7–0 (LxPDRDE = 0) (Note:

See Link Port Buffer Control Register Bit definitions in

the ADSP-21161N SHARC DSP Hardware Reference.)

• DxA, DxB, SCLKx, SPICLK, MISO, MOSI, EMU,

TMS,TRST, TDI (Note: These pins have a pull-up.)

Table 2. Pin Function Descriptions

Type

Function

ADDR23–0

I/O/T

External Bus Address. The ADSP-21161N outputs addresses for external memory and

peripherals on these pins. In a multiprocessor system the bus master outputs addresses for

read/writes of the IOP registers of other ADSP-21161Ns while all other internal memory

resourcescanbeaccessedindirectlyviaDMAcontrol(thatis,accessingIOPDMAparameter

registers). The ADSP-21161N inputs addresses when a host processor or multiprocessing

bus master is reading or writing its IOP registers. A keeper latch on the DSP’s ADDR23-0

pins maintains the input at the level it was last driven. This latch is only enabled on the

ADSP-21161N with ID2–0=00x.

External Bus Data. The ADSP-21161N inputs and outputs data and instructions on these

pins. Pull-up resistors on unused data pins are not necessary. A keeper latch on the DSP’s

DATA47–16 pins maintains the input at the level it was last driven. This latch is only enabled

on the ADSP-21161N with ID2–0=00x.

DATA47–16

I/O/T

Note: DATA15–8 pins (multiplexed with L1DAT7–0) can also be used to extend the data bus if

the link ports are disabled and will not be used. In addition, DATA7–0 pins (multiplexed with

L0DAT7–0) can also be used to extend the data bus if the link ports are not used. This enables

execution of 48-bit instructions from external SBSRAM (system clock speed-external port), SRAM

(system clock speed-external port) and SDRAM (core clock or one-half the core clock speed). The

IPACKx Instruction Packing Mode Bits in SYSCON should be set correctly (IPACK1–0=0x1)

to enable this full instruction Width/No-packing Mode of operation.

MS3–0

I/O/T

Memory Select Lines. These outputs are asserted (low) as chip selects for the corre-

sponding banks of external memory. Memory bank sizes are fixed to 16 M words for non-

SDRAM and 64 M words for SDRAM. The MS3–0 outputs are decoded memory address

lines. In asynchronous access mode, the MS3–0 outputs transition with the other address

outputs. In synchronous access modes, the MS3–0 outputs assert with the other address

lines; however, they deassert after the first CLKIN cycle in which ACK is sampled asserted.

In a multiprocessor system, the MSx signals are tracked by slave SHARCs. The internal

addresses 24 and 25 are zeros and 26 and 27 are decoded into MS3–0.

MemoryReadStrobe.RD isassertedwheneverADSP-21161Nreadsawordfromexternal

memory or from the IOP registers of other ADSP-21161Ns. External devices, including

other ADSP-21161Ns, must assert RD for reading from a word of the ADSP-21161N IOP

register memory. In a multiprocessing system, RD is driven by the bus master. RD has a

20 kΩ internal pull-up resistor that is enabled for DSPs with ID2–0=00x.

RD

–12–

REV. A

ADSP-21161N

Table 2. Pin Function Descriptions (continued)

Type

Function

WR

I/O/T

MemoryWriteLowStrobe. WR isassertedwhenADSP-21161Nwritesawordtoexternal

memory or IOP registers of other ADSP-21161Ns. External devices must assert WR for

writing to ADSP-21161N IOP registers. In a multiprocessing system, the bus master drives

WR. WR has a 20 kΩ internal pull-up resistor that is enabled for DSPs with ID2–0=00x.

Sequential Burst Access. BRST is asserted by ADSP-21161N to indicate that data

associated with consecutive addresses is being read or written. A slave device samples the

initial address and increments an internal address counter after each transfer. The incre-

mented address is not pipelined on the bus. A master ADSP-21161N in a multiprocessor

environment can read slave external port buffers (EPBx) using the burst protocol. BRST is

asserted after the initial access of a burst transfer. It is asserted for every cycle after that,

except for the last data request cycle (denoted by RD or WR asserted and BRST negated).

A keeper latch on the DSP’s BRST pin maintains the input at the level it was last driven.

This latch is only enabled on the ADSP-21161N with ID2–0=00x.

Memory Acknowledge. External devices can de-assert ACK (low) to add wait states to an

external memory access. ACK is used by I/O devices, memory controllers, or other periph-

erals to hold off completion of an external memory access. The ADSP-21161N deasserts

ACK as an output to add wait states to a synchronous access of its IOP registers. ACK has

a 20 kΩ internal pull-up resistor that is enabled during reset or on DSPs with ID2–0=00x.

Suspend Bus and Three-State. External devices can assert SBTS (low) to place the

external bus address, data, selects, and strobes in a high impedance state for the following

cycle. If the ADSP-21161N attempts to access external memory while SBTS is asserted, the

processor will halt and the memory access will not be completed until SBTS is deasserted.

SBTS should only be used to recover from host processor/ADSP-21161N deadlock.

SDRAM Column Access Strobe. In conjunction with RAS, MSx, SDWE, SDCLKx,

and sometimes SDA10, defines the operation for the SDRAM to perform.

SDRAM Row Access Strobe. In conjunction with CAS, MSx, SDWE, SDCLKx, and

sometimes SDA10, defines the operation for the SDRAM to perform.

BRST

I/O/T

ACK

I/O/S

I/S

SBTS

CAS

I/O/T

O/T

RAS

SDWE

DQM

SDRAM Write Enable. In conjunction with CAS, RAS, MSx, SDCLKx, and sometimes

SDA10, defines the operation for the SDRAM to perform.

SDRAM Data Mask. In write mode, DQM has a latency of zero and is used during a

precharge command and during SDRAM power-up initialization.

SDCLK0

SDCLK1

I/O/S/T

O/S/T

SDRAM Clock Output 0. Clock for SDRAM devices.

SDRAMClockOutput1. AdditionalclockforSDRAMdevices. Forsystemswithmultiple

SDRAM devices, handles the increased clock load requirements, eliminating need of off-

chip clock buffers. Either SDCLK1 or both SDCLKx pins can be three-stated.

SDRAM Clock Enable. Enables and disables the CLK signal. For details, see the data

sheet supplied with the SDRAM device.

SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with a non-

SDRAM accesses or hostaccesses. This pin replaces the DSP’s A10 pin only duringSDRAM

accesses.

SDCKE

SDA10

I/O/T

O/T

IRQ2–0

FLAG11–0

TIMEXP

HBR

I/A

I/O/A

O

Interrupt Request Lines. These are sampled on the rising edge of CLKIN and may be

either edge-triggered or level-sensitive.

Flag Pins. Each is configured via control bits as either an input or output. As an input, it

can be tested as a condition. As an output, it can be used to signal external peripherals.

Timer Expired. Asserted for four core clock cycles when the timer is enabled and

TCOUNT decrements to zero.

Host Bus Request. Must be asserted by a host processor to request control of the ADSP-

21161N’s external bus. When HBR is asserted in a multiprocessing system, the ADSP-

21161N that is bus master will relinquish the bus and assert HBG. To relinquish the bus,

the ADSP-21161N places the address, data, select, and strobe lines in a high impedance

state. HBR has priority over all ADSP-21161N bus requests (BR6–1) in a multiprocessing

system.

I/A

REV. A

–13–

ADSP-21161N

Table 2. Pin Function Descriptions (continued)

Type

Function

HBG

I/O

Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor

may take control of the external bus. HBG is asserted (held low) by the ADSP-21161N until

HBR is released. In a multiprocessing system, HBG is output by the ADSP-21161N bus

master and is monitored by all others.

After HBR is asserted, and before HBG is given, HBG will float for 1 t_CK(1 CLKIN cycle).

To avoid erroneous grants, HBG should be pulled up with a 20kΩ to 50kΩ external resistor.

Chip Select. Asserted by host processor to select the ADSP-21161N.

CS

I/A

REDY

O (O/D) Host Bus Acknowledge. The ADSP-21161N deasserts REDY (low) to add wait states to

a host access of its IOP registers when CS and HBR inputs are asserted.

DMAR1

DMAR2

DMAG1

DMAG2

BR6–1

I/A

DMA Request 1 (DMA Channel 11). Asserted by external port devices to request DMA

services. DMAR1 has a 20 kΩ internal pull-up resistor that is enabled for DSPs with

ID2–0=00x.

DMA Request 2 (DMA Channel 12). Asserted by external port devices to request DMA

services. DMAR2 has a 20 kΩ internal pull-up resistor that is enabled for DSPs with

ID2–0=00x.

DMA Grant 1 (DMA Channel 11). Asserted by ADSP-21161N to indicate that the

requested DMA starts on the next cycle. Driven by bus master only. DMAG1 has a 20 kΩ

internal pull-up resistor that is enabled for DSPs with ID2–0=00x.

DMA Grant 2 (DMA Channel 12). Asserted by ADSP-21161N to indicate that the

requested DMA starts on the next cycle. Driven by bus master only. DMAG2 has a 20 kΩ

internal pull-up resistor that is enabled for DSPs with ID2–0=00x.

I/A

O/T

I/O/S

Multiprocessing Bus Requests. Used by multiprocessing ADSP-21161Ns to arbitrate for

bus mastership. An ADSP-21161N only drives its own BRx line (corresponding to the value

of its ID2–0 inputs) and monitors all others. In a multiprocessor system with less than six

ADSP-21161Ns, the unused BRx pins should be pulled high; the processor's own BRx line

must not be pulled high or low because it is an output.

BMSTR

ID2–0

RPBA

O

I

Bus Master Output. In a multiprocessor system, indicates whether the ADSP-21161N is

current bus master of the shared external bus. The ADSP-21161N drives BMSTR high only

while it is the bus master. In a single-processor system (ID=000), the processor drives this

pin high. This pin is used for debugging purposes.

Multiprocessing ID. Determines which multiprocessing bus request (BR6–BR1) is used

by ADSP-21161N. ID=001 corresponds to BR1, ID=010 corresponds to BR2, and so on.

Use ID=000 or ID=001 in single-processor systems. These lines are a system configuration

selection that should be hardwired or only changed at reset.

Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for

multiprocessor bus arbitration is selected. When RPBA is low, fixed priority is selected. This

signal is a system configuration selection that must be set to the same value on every ADSP-

21161N. If the value of RPBA is changed during system operation, it must be changed in

the same CLKIN cycle on every ADSP-21161N.

I/S

PA

I/O/T

Priority Access. Asserting its PA pin enables an ADSP-21161N bus slave to interrupt

background DMA transfers and gain access to the external bus. PA is connected to all ADSP-

21161Ns in the system. If access priority is not required in a system, the PA pin should be

left unconnected. PA has a 20 kΩ internal pull-up resistor that is enabled for DSPs with

ID2–0=00x.

Data Transmit or Receive Channel A (Serial Ports 0, 1, 2, 3). Each DxA pin has an

internal pull-up resistor. Bidirectional data pin. This signal can be configured as an output

to transmit serial data, or as an input to receive serial data.

Data Transmit or Receive Channel B (Serial Ports 0, 1, 2, 3). Each DxB pin has an

internal pull-up resistor. Bidirectional data pin. This signal can be configured as an output

to transmit serial data, or as an input to receive serial data.

Transmit/Receive Serial Clock (Serial Ports 0, 1, 2, 3). Each SCLK pin has an internal

pull-up resistor. This signal can be either internally or externally generated.

DxA

I/O

DxB

SCLKx

–14–

REV. A

ADSP-21161N

Table 2. Pin Function Descriptions (continued)

Type

Function

FSx

I/O

Transmit or Receive Frame Sync (Serial Ports 0, 1, 2, 3). The frame sync pulse initiates

shifting of serial data. This signal is either generated internally or externally. It can be active

high or low or an early or a late frame sync, in reference to the shifting of serial data.

Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls the

rate at which data is transferred. The master may transmit data at a variety of baud rates.

SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that is active during

data transfers, only for the length of the transferred word. Slave devices ignore the serial

clock if the slave select input is driven inactive (HIGH). SPICLK is used to shift out and

shift in the data driven on the MISO and MOSI lines. The data is always shifted out on one

clock edge of the clock and sampled on the opposite edge of the clock. Clock polarity and

clock phase relative to data are programmable into the SPICTL control register and define

the transfer format. SPICLK has a 50 kΩ internal pull-up resistor.

SPICLK

I/O

SPIDS

I

Serial Peripheral Interface Slave Device Select. An active low signal used to enable

slave devices. This input signal behaves like a chip select, and is provided by the master device

for the slave devices. In multimaster mode SPIDS signal can be asserted to a master device

to signal that an error has occurred, as some other device is also trying to be the master

device. If asserted low when the device is in master mode, it is considered a multimaster

error. For a single-master, multiple-slave configuration where FLAG3–0 are used, this pin

must be tied or pulled high to V_DDEXTon the master device. For ADSP-21161N to ADSP-

21161N SPI interaction, any of the master ADSP-21161N’s FLAG3–0 pins can be used to

drive the SPIDS signal on the ADSP-21161N SPI slave device.

MOSI

MISO

I/O (o/d) SPI Master Out Slave. If the ADSP-21161N is configured as a master, the MOSI pin

becomes a data transmit (output) pin, transmitting output data. If the ADSP-21161N is

configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input data.

In an ADSP-21161N SPI interconnection, the data is shifted out from the MOSI output pin

of the master and shifted into the MOSI input(s) of the slave(s). MOSI has an internal pull-

up resistor.

I/O (o/d) SPI Master In Slave Out. If the ADSP-21161N is configured as a master, the MISO pin

becomes a data receive (input) pin, receiving input data. If the ADSP-21161N is configured

as a slave, the MISO pin becomes a data transmit (output) pin, transmitting output data. In

an ADSP-21161N SPI interconnection, the data is shifted out from the MISO output pin

of the slave and shifted into the MISO input pin of the master. MISO has an internal pull-

up resistor. MISO can be configured as o/d by setting the OPD bit in the SPICTL register.

Note: Only one slave is allowed to transmit data at any given time.

LxDAT7–0

[DATA15–0]

I/O

[I/O/T]

Link Port Data (Link Ports 0–1).

For silicon revisions 1.2 and higher, each LxDAT pin has a keeper latch that is enabled when

used as a data pin; or a 20 kΩ internal pull-down resistor that is enabled or disabled by the

LxPDRDE bit of the LCTL register.

Forsiliconrevisions0.3, 1.0, and1.1 eachLxDATpinhasa50kΩ internalpull-downresistor

that is enabled or disabled by the LxPDRDE bit of the LCTL register.

Note: L1DAT7–0 are multiplexed with the DATA15–8 pins L0DAT7–0 are multiplexed with the

DATA7–0 pins. If link ports are disabled and are not used, these pins can be used as additional

data lines for executing instructions at up to the full clock rate from external memory. See

DATA47–16 for more information.

Link Port Clock (Link Ports 0–1). Each LxCLK pin has an internal pull-down 50 kΩ

resistor that is enabled or disabled by the LxPDRDE bit of the LCTL register.

Link Port Acknowledge (Link Ports 0–1). Each LxACK pin has an internal pull-down

50 kΩ resistor that is enabled or disabled by the LxPDRDE bit of the LCTL register.

EPROM Boot Select. For a description of how this pin operates, see the table in the BMS

pin description. This signal is a system configuration selection that should be hardwired.

Link Boot. For a description of how this pin operates, see the table in the BMS pin

description. This signal is a system configuration selection that should be hardwired.

LxCLK

LxACK

EBOOT

LBOOT

I/O

I

REV. A

–15–

ADSP-21161N

Table 2. Pin Function Descriptions (continued)

Type

Function

BMS

I/O/T

Boot Memory Select. Serves as an output or input as selected with the EBOOT and

LBOOT pins (see Table 4). This input is a system configuration selection that should be

hardwired. For Host and PROM boot, DMA channel 10 (EPB0) is used. For Link boot and

SPI boot, DMA channel 8 is used.

Three-state only in EPROM boot mode (when BMS is an output).

CLKIN

I

LocalClockIn.UsedinconjunctionwithXTAL.CLKINistheADSP-21161Nclockinput.

It configures the ADSP-21161N to use either its internal clock generator or an external clock

source. Connecting the necessary components to CLKIN and XTAL enables the internal

clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected

configures the ADSP-21161N to use the external clock source such as an external clock

oscillator.The ADSP-21161N external port cycles at the frequency of CLKIN. The

instruction cycle rate is a multiple of the CLKIN frequency; it is programmable at power-

up via the CLK_CFG1–0 pins. CLKIN may not be halted, changed, or operated below the

specified frequency.

XTAL

O

I

Crystal Oscillator Terminal 2. Used in conjunction with CLKIN to enable the ADSP-

21161N’s internal clock oscillator or to disable it to use an external clock source. See CLKIN.

Core/CLKIN Ratio Control. ADSP-21161N core clock (instruction cycle) rate is equal

to n × PLLICLK where n is user selectable to 2, 3, or 4, using the CLK_CFG1–0 inputs.

These pins can also be used in combination with the CLKDBL pin to generate additional

core clock rates of 6 × CLKIN and 8 × CLKIN (see the Clock Rate Ratios table in the

CLKDBL description).

CLK_CFG1-0

CLKDBL

I

Crystal Double Mode Enable. This pin is used to enable the 2× clock double circuitry,

where CLKOUT can be configured as either 1× or 2× the rate of CLKIN. This CLKIN

double circuit is primarily intended to be used for an external crystal in conjunction with

the internal clock generator and the XTAL pin. The internal clock generator when used in

conjunction with the XTAL pin and an external crystal is designed to support up to a

maximum of 25 MHz external crystal frequency. CLKDBL can be used in XTAL mode to

generate a 50 MHz input into the PLL. The 2× clock mode is enabled (during RESET low)

by tying CLKDBL to GND, otherwise it is connected to V_DDEXTfor 1× clock mode. For

example, this enables the use of a 25 MHz crystal to enable 100 MHz core clock rates and

a 50 MHz CLKOUT operation when CLK_CFG0=0, CLK_CFG1=0 and CLKDBL=0.

This pin can also be used to generate different clock rate ratios for external clock oscillators

as well. The possible clock rate ratio options (up to 100 MHz) for either CLKIN (external

clock oscillator) or XTAL (crystal input) are shown in Table 3 on Page 17. An 8:1 ratio

enables the use of a 12.5 MHz crystal to generate a 100 MHz core (instruction clock) rate

and a 25 MHz CLKOUT (external port) clock rate. See also Figure 10 on Page 20.

Note: When using an external crystal, the maximum crystal frequency cannot exceed 25 MHz.

For all other external clock sources, the maximum CLKIN frequency is 50 MHz.

Local Clock Out. CLKOUT is 1× or 2× and is driven at either 1× or 2× the frequency of

CLKIN frequency by the current bus master. The frequency is determined by the CLKDBL

pin. This output is three-stated when the ADSP-21161N is not the bus master or when the

host controls the bus (HBG asserted). A keeper latch on the DSP’s CLKOUT pin maintains

the output at the level it was last driven. This latch is only enabled on the ADSP-21161N

with ID2–0=00x.

CLKOUT

O/T

If CLKDBL enabled, CLKOUT=2 × CLKIN

If CLKDBL disabled, CLKOUT=1 × CLKIN

Note: CLKOUT is only controlled by the CLKDBL pin and operates at either 1 × CLKIN or

2 × CLKIN.

Do not use CLKOUT in multiprocessing systems. Use CLKIN instead.

Processor Reset. Resets the ADSP-21161N to a known state and begins execution at the

program memory location specified by the hardware reset vector address. The RESET input

must be asserted (low) at power-up.

RESET

I/A

–16–

REV. A

ADSP-21161N

Table 2. Pin Function Descriptions (continued)

Type

Function

RSTOUT¹

O

Reset Out. When RSTOUT is asserted (low), this pin indicates that the core blocks are in

reset. It is deasserted 4080 cycles after RESET is deasserted indicating that the PLL is stable

and locked.

TCK

TMS

I

I/S

Test Clock (JTAG). Provides a clock for JTAG boundary scan.

TestMode Select(JTAG). Usedtocontroltheteststate machine. TMShasa20 kΩ internal

pull-up resistor.

TDI

I/S

Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 kΩ

internal pull-up resistor.

TDO

TRST

O

I/A

Test Data Output (JTAG). Serial scan output of the boundary scan path.

Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)

after power-up or held low for proper operation of the ADSP-21161N. TRST has a 20 kΩ

internal pull-up resistor.

EMU

O (O/D) Emulation Status. Must be connected to the ADSP-21161N Analog Devices DSP Tools

product line of JTAG emulators target board connector only. EMU has a 50 kΩ internal

pull-up resistor.

V_DDINT

V_DDEXT

AVDD

P

Core Power Supply. Nominally +1.8 V dc and supplies the DSP’s core processor (14 pins).

I/O Power Supply. Nominally +3.3 V dc. (13 pins).

Analog Power Supply. Nominally +1.8 V dc and supplies the DSP’s internal PLL (clock

generator). This pin has the same specifications as V_DDINT, except that added filtering

circuitry is required. See Power Supplies on Page 9.

AGND

GND

NC

G

Analog Power Supply Return.

Power Supply Return. (26 pins).

Do Not Connect. Reserved pins that must be left open and unconnected. (5 pins²).

¹RSTOUT exists only for silicon revision 1.2.

²Four NC pins for silicon revision 1.2, because RSTOUT has been added.

Table 3. Clock Rate Ratios

CLKDBL

CLK_CFG1

CLK_CFG0

Core:CLKIN

CLKIN:CLKOUT

1

0

1

0

1

0

1

0

1

0

2:1

3:1

4:1

6:1

8:1

1:1

1:2

BOOT MODES

Table 4. Boot Mode Selection

EBOOT LBOOT BMS

Booting Mode

EPROM (Connect BMS to EPROM chip select.)

1

0

1

0

1

0

1

Output

1 (Input) Host Processor

0 (Input) Serial Boot via SPI

1 (Input) Link Port

0 (Input) No Booting. Processor executes from external memory.

x (Input) Reserved

REV. A

–17–

ADSP-21161N

SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

C Grade

Min Max

K Grade

Min Max

Parameter

Test Conditions

Unit

V_DDINT

AV_DD

V_DDEXT

V_IH

V_IL

T_CASE

Internal (Core) Supply Voltage

Analog (PLL) Supply Voltage

External (I/O) Supply Voltage

High Level Input Voltage¹

1.71 1.89

3.13 3.47

1.71 1.89

3.13 3.47

V

°C

@ V_DDEXT= max

@ V_DDEXT= min

2.0

V_DDEXT+0.5

2.0

V_DDEXT+0.5

Low Level Input Voltage¹

–0.5 +0.8

–40 +105

–0.5 +0.8

Case Operating Temperature²

0

+85

Specifications subject to change without notice.

¹Applies to input and bidirectional pins: DATA47–16, ADDR23–0, MS3–0, RD, WR, ACK, SBTS, IRQ2–0, FLAG11–0, HBG, HBR, CS, DMAR1,

DMAR2, BR6–1, ID2–0, RPBA, PA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE, SDCLK0, LxDAT7–0, LxCLK, LxACK, SPICLK, MOSI,

MISO, SPIDS, EBOOT, LBOOT, BMS, SDCKE, CLK_CFGx, CLKDBL, CLKIN, RESET, TRST, TCK, TMS, TDI.

²See Thermal Characteristics on Page 52 for information on thermal specifications.

ELECTRICAL CHARACTERISTICS

Parameter

Test Conditions

Min Max Unit

V_OH

V_OL

I_IH

I_IL

I_IHC

I_ILC

I_IKH

I_IKL

I_IKH-OD

I_IKL-OD

I_ILPU

I_OZH

High Level Output Voltage¹

@ V_DDEXT= min, I_OH= –2.0 mA²

@ V_DDEXT= min, I_OL= 4.0 mA²

@ V_DDEXT= max, V_IN= V_DDEXTmax

@ V_DDEXT= max, V_IN= 0 V

@ V_DDEXT= max, V_IN= V_DDEXTmax

@ V_DDEXT= max, V_IN= 0 V

@ V_DDEXT= max, V_IN= 2.0 V

@ V_DDEXT= max, V_IN= 0.8 V

@ V_DDEXT= max

2.4

V

µA

Low Level Output Voltage¹

0.4

10

35

High Level Input Current^{3, 4}

Low Level Input Current³

CLKIN High Level Input Current⁵

CLKIN Low Level Input Current⁵

Keeper High Load Current⁶

–250 –100 µA

50

–300

300

Keeper Low Load Current⁶

200

µA

mA

pF

Keeper High Overdrive Current^{6, 7, 8}

Keeper Low Overdrive Current^{6, 7, 8}

Low Level Input Current Pull-Up⁴

Three-State Leakage Current^{9, 10, 11}

Three-State Leakage Current^{9, 12, 13}

Three-State Leakage Current Pull-Up1¹⁰

Three-State Leakage Current Pull-Up2¹¹

Three-State Leakage Current Pull-Down1¹²

Three-State Leakage Current Pull-Down2¹³

@ V_DDEXT= max

@ V_DDEXT= max, V_IN= 0 V

@ V_DDEXT= max, V_IN= V_DDEXTmax

@ V_DDEXT= max, V_IN= 0 V

@ V_DDEXT= max, V_IN= V_DDEXTmax

t_CCLK= 10.0 ns, V_DDINT= max

@ AV_DD= max

350

10

I_OZL

I_OZLPU1

I_OZLPU2

I_OZHPD1

I_OZHPD2

500

350

500

900

650

500

400

10

I_DD-INPEAKSupply Current (Internal)^{14, 15}

I_DD-INHIGHSupply Current (Internal)^{15, 16}

I_DD-INLOW

I_DD-IDLE

AI_DD

Supply Current (Internal)^{15, 17}

Supply Current (Idle)^{15, 18}

Supply Current (Analog)¹⁹

Input Capacitance^{20, 21}

C_IN

f_IN= 1 MHz, T_CASE= 25°C, V_IN= 1.8 V

4.7

Specifications subject to change without notice.

1

Applies to output and bidirectional pins: DATA47–16, ADDR23–0, MS3–0, RD, WR, ACK, DQM, FLAG11–0, HBG, REDY, DMAG1, DMAG2,

BR6–1, BMSTR, PA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE, SDA10, LxDAT7–0, LxCLK, LxACK, SPICLK, MOSI, MISO, BMS,

SDCLKx, SDCKE, EMU, XTAL, TDO, CLKOUT, TIMEXP, RSTOUT.

²See Output Drive Currents on Page 51 for typical drive current capabilities.

³Applies to input pins: DATA47–16, ADDR23–0, MS3–0, SBTS, IRQ2–0, FLAG11–0, HBG, HBR, CS, BR6–1, ID2–0, RPBA, BRST, FSx, DxA, DxB,

SCLKx, RAS, CAS, SDWE, SDCLK0, LxDAT7–0, LxCLK, LxACK, SPICLK, MOSI, MISO, SPIDS, EBOOT, LBOOT, BMS, SDCKE, CLK_CFGx,

CLKDBL, TCK, RESET, CLKIN.

⁴Applies to input pins with 20 kΩ internal pull-ups: RD, WR, ACK, DMAR1, DMAR2, PA, TRST, TMS, TDI.

⁵Applies to CLKIN only.

⁶Applies to all pins with keeper latches: ADDR23–0, DATA47–0, MS3–0, BRST, CLKOUT.

⁷Current required to switch from kept high to low or from kept low to high.

⁸Characterized, but not tested.

–18–

REV. A

ADSP-21161N

⁹Applies to three-statable pins: DATA47–16, ADDR23–0, MS3–0, CLKOUT, FLAG11–0, REDY, HBG, BMS, BR6–1, RAS, CAS, SDWE, DQM,

SDCLKx, SDCKE, SDA10, BRST.

¹⁰Applies to three-statable pins with 20 kΩ pull-ups: RD, WR, DMAG1, DMAG2, PA.

¹¹Applies to three-statable pins with 50 kΩ internal pull-ups: DxA, DxB, SCLKx, SPICLK., EMU, MISO, MOSI

¹²Applies to three-statable pins with 50 kΩ internal pull-downs: LxDAT7–0 (below Revision1.2), LxCLK, LxACK. Use I_OZHPD2for Rev. 1.2 and higher.

¹³Applies to three-statable pins with 20 kΩ internal pull-downs: LxDAT7-0 (Revision 1.2 and higher).

¹⁴The test program used to measure I_DDINPEAKrepresents worst-case processor operation and is not sustainable under normal application conditions. Actual

internal power measurements made using typical applications are less than specified. For more information, see “Power Dissipation” on Page 21.

¹⁵Current numbers are for V_DDINTand AVDD supplies combined.

16

I

is a composite average based on a range of high activity code. See Power Dissipation on Page 21.

is a composite average based on a range of low activity code. See Power Dissipation on Page 21.

DDINHIGH

DDINLOW

17

¹⁸Idle denotes ADSP-21161N state during execution of IDLE instruction. See Power Dissipation on Page 21.

¹⁹Characterized, but not tested.

²⁰Applies to all signal pins.

²¹Guaranteed, but not tested.

ABSOLUTE MAXIMUM RATINGS

Internal (Core) Supply Voltage (V_DDINT)¹. . –0.3 V to +2.2 V

Analog (PLL) Supply Voltage (AV_DD)¹. . . . –0.3 V to +2.2 V

External (I/O) Supply Voltage (V_DDEXT)¹. . –0.3 V to +4.6 V

Input Voltage¹. . . . . . . . . . . . . . . . –0.5 V to V_DDEXT+ 0.5 V

Output Voltage Swing¹. . . . . . . . . –0.5 V to V_DDEXT+ 0.5 V

Load Capacitance¹. . . . . . . . . . . . . . . . . . . . . . . . . .200 pF

Storage Temperature Range¹. . . . . . . . . . .–65°C to +150°C

¹Stresses greater than those listed above may cause permanent damage to the

device. These are stress ratings only; functional operation of the device at these

or any other conditions greater than those indicated in the operational sections

of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

ESD SENSITIVITY

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V

readily accumulate on the human body and test equipment and can discharge without

detection. Although the ADSP-21161N features proprietary ESD protection circuitry,

permanent damage may occur on devices subjected to high energy electrostatic

discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

REV. A

–19–

ADSP-21161N

TIMING SPECIFICATIONS

The ADSP-21161N’s internal clock switches at higher frequen-

cies than the system input clock (CLKIN). To generate the

internal clock, the DSP uses an internal phase-locked loop

(PLL). This PLL-based clocking minimizes the skew between

the system clock (CLKIN) signal and the DSP’s internal clock

(the clock source for the external port logic and I/O pads).

and CLKDBL pins. Even though the internal clock is the clock

source for the external port, it behaves as described in the Clock

Rate Ratio chart in Table 3 on Page 17. To determine switching

frequencies for the serial and link ports, divide down the internal

clock, using the programmable divider control of each port

(DIVx for the serial ports and LxCLKD for the link ports).

The ADSP-21161N’s internal clock (a multiple of CLKIN)

provides the clock signal for timing internal memory, processor

core, link ports, serial ports, and external port (as required for

read/write strobes in asynchronous access mode). During reset,

program the ratio between the DSP’s internal clock frequency

and external (CLKIN) clock frequency with the CLK_CFG1–0

Note the following definitions of various clock periods that are a

function of CLKIN and the appropriate ratio control.

Figure 10 enables Core-to-CLKIN ratios of 2:1, 3:1, 4:1, 6:1,

and 8:1 with external oscillator or crystal. It also shows support

for CLKOUT-to-CLKIN ratios of 1:1 and 2:1.

Table 5. CLKOUT and CCLK Clock Generation Operation

Timing Requirements

Description¹

Calculation

CLKIN

CLKOUT

PLLICLK

CCLK

t_CK

t_CCLK

t_LCLK

t_SCLK

t_SDK

Input Clock

External Port System Clock

PLL Input Clock

1/t_CK

1/t_CKOP

1/t_PLLIN

1/t_CCLK

1/CLKIN

1/CCLK

(t_CCLK) × LR

(t_CCLK) × SR

(t_CCLK) × SDCKR

(t_CCLK) × SPIR

Core Clock

CLKIN Clock Period

(Processor) Core Clock Period

Link Port Clock Period

Serial Port Clock Period

SDRAM Clock Period

SPI Clock Period

t_SPICLK

¹where:

LR = link port-to-core clock ratio (1, 2, 3, or 1:4, determined by LxCLKD)

SR = serial port-to-core clock ratio (wide range, determined by CLKDIV)

SDCKR = SDRAM-to-Core Clock Ratio (1:1 or 1:2, determined by SDCTL register)

SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPICTL register)

LCLK = Link Port Clock

SCLK = Serial Port Clock

SDK = SDRAM Clock

SPICLK = SPI Clock

CORE

I/O PROCESSOR

SYNCHRONOUS EP

ASYNCHRONOUS EP

HARDWARE

INTERRUPT

I/O FLAG

MULTIPROCESSING

SBSRAM

HOST

SRAM

TIMER

LINK PORTS

ꢀ1, ꢀ1/2, ꢀ1/3, ꢀ1/4

SDRAM

ꢀ1, ꢀ1/2

CLKIN

(CRYSTAL OSCILLATOR

4.2–50MHz)

SERIAL PORTS

ꢀ1/2 MAX

CLOCK DOUBLER

RATIOS

ꢀ2, ꢀ3, ꢀ4

ꢀ1, ꢀ2

XTAL

(QUARTZ CRYSTAL

25MHz MAX)

PLL

SPI

ꢀ1/8 MAX

CLKOUT

CLK_CFG1–0

CLKDBL

Figure 10. Core Clock and System Clock Relationship to CLKIN

–20–

REV. A

ADSP-21161N

Power Dissipation

Total power dissipation has two components: one due to internal

circuitry and one due to the switching of external output drivers.

Use the exact timing information given. Do not attempt to derive

parameters from the addition or subtraction of others. While

addition or subtraction would yield meaningful results for an

individual device, the values given in this data sheet reflect sta-

tistical variations and worst cases. Consequently, it is not

meaningful to add parameters to derive longer times.

Internal power dissipation depends on the instruction execution

sequenceandthedataoperands involved. Usingthecurrentspec-

ifications (I_DDINPEAK, I_DDINHIGH, I_DDINLOW, I_DDIDLE) from the

Electrical Characteristics on Page 18 and the current-versus-

operation information in Table 6, the programmer can estimate

the ADSP-21161N’s internal power supply (V_DDINT) input

current for a specific application, according to the following

formula:

See Figure 40 on Page 51 under Test Conditions for voltage

reference levels.

Switching characteristics specify how the processor changes its

signals. Circuitry external to the processor must be designed for

compatibility with these signal characteristics. Switching charac-

teristics describe what the processor will do in a given circum-

stance. Use switching characteristics to ensure that any timing

requirement of a device connected to the processor (such as

memory) is satisfied.

% Peak × I_DDINPEAK

% High × I_DDINHIGH

% Low × I_DDINLOW

+ % Idle × I_DDIDLE

--------------------------------------------------

I_DDINT

Timing requirements apply to signals that are controlled by

circuitry external to the processor, such as the data input for a

read operation. Timing requirements guarantee that the

processor operates correctly with other devices.

Table 6. Operation Types Versus Input Current

Peak Activity¹

High Activity¹

(I_DDINHIGH

Low Activity¹

(I_DDINLOW

Operation

(I_DDINPEAK

)

Instruction Type

Instruction Fetch

Multifunction

Cache

Multifunction

Internal Memory

Single Function

Internal Memory

None

Core Memory Access²

Internal Memory DMA

External Memory DMA

Data bit pattern for core

memory access and DMA

2 per t_CKcycle (DM×64 and PM×64) 1 per t_CKcycle (DM×64)

1 per 2 t_CCLKcycles

1 per external port cycle (×32)

Worst case

1 per 2 t_CCLKcycles

1 per external port cycle (×32) N/A

Random N/A

N/A

¹The state of the PEYEN bit (SIMD versus SISD mode) does not influence these calculations.

²These assume a 2:1 core clock ratio. For more information on ratios and clocks (t_CKand t_CCLK), see the timing ratio definitions on Page 20.

The external component of total power dissipation is caused by

the switching of output pins. Its magnitude depends on:

• External Data Memory writes can occur every cycle at a

rate of 1/t_CKwith 50% of the pins switching

• The bus cycle time is 50 MHz

• The number of output pins that switch during each cycle

(O)

• The external SDRAM clock rate is 100 MHz

• Ignoring SDRAM refresh cycles

• The maximum frequency at which they can switch (f)

• Their load capacitance (C)

• Addresses are incremental and on the same page

• Their voltage swing (V_DD

)

The P_EXTequation is calculated for each class of pins that can

drive, as shown in Table 7.

and is calculated by:

P_EXT= O × C × V_DD²× f

A typical power consumption can now be calculated for these

conditions by adding a typical internal power dissipation:

The load capacitance should include the processor package

capacitance (C_IN). The switching frequency includes driving the

P_TOTAL= P_EXT+ P_INT+ P_PLL

Where:

load high and then back low. At a maximum rate of 1/t_CK

,

P

_EXTis from Table 7.

address and data pins can drive high and low, while writing to a

SDRAM memory.

P

_INTis I_DDINT× 1.8 V, using the calculation I_DDINTlisted in Power

Dissipation on Page 21.

_PLLisAI_DD×1.8V,usingthevalueforAI_DDlistedintheElectrical

Characteristics on Page 18.

Example: Estimate P_EXTwith the following assumptions:

P

• A system with one bank of external memory (32 bit)

• Two 1M ꢀ 16 SDRAM chips are used, each with a load

of 10 pF (ignoring trace capacitance)

REV. A

–21–

ADSP-21161N

Table 7. External Power Calculations (3.3 V Device)

2

Pin Type

Number of Pins

% Switching

ꢀ C

ꢀ f

ꢀ V_DD

= P_EXT

Address

MSx

SDWE

Data

11

4

1

32

1

20

0

50

100

24.7 pF

14.7 pF

24.7 pF

50 MHz

N/A

50 MHz

100 MHz

10.9 V

= 0.030 W

= 0.000 W

= 0.128 W

= 0.027 W

SDCLK0

P

_EXT= 0.185 W

Power-Up Sequencing – Silicon Revision 0.3, 1.0, 1.1

The timing requirements for DSP startup for silicon revision 0.3,

1.0, or 1.1 are given in Table 8.

Note that the conditions causing a worst-case

P

_EXTare different

from those causing a worst-case _INT. Maximum

P

P_INTcannot

occur while 100% of the output pins are switching from all ones

to all zeros. Note also that it is not common for an application to

have 100% or even 50% of the outputs switching simultaneously.

Table 8. Power-Up Sequencing for Revisions 0.3, 1.0, and 1.1 (DSP Startup)

Parameter

Min

Max

Unit

Timing Requirements

t_RSTVDD

t_VDDRAMP

t_IVDDEVDD

t_CLKVDD

t_VDDRST

t_CLKRST

t_PLLRST

RESET Low Before V_DDINT/V_DDEXTon

V_DDINT/V_DDEXTVoltage Ramp Rate¹

V_DDINTon Before V_DDEXT

CLKIN Valid After V_DDINT/V_DDEXTValid

V_DDINT/V_DDEXTValid Before RESET Deasserted²

CLKIN Valid Before RESET Deasserted³

PLL Control Setup Before RESET Deasserted

0

ns

0.0009

–50

0

100

20

9

V/µs

ms

µs

+200

200

¹The minimum 0.9 V/ms is based on the slowest allowable ramp-up time (2 ms) for V_DDINTto ramp from 0 volts to 1.8 volts and (3.6 ms) for V_DDEXTto

ramp from 0 volts to 3.3 volts.

²The minimum time of 0 ns assumes that V_DDINTand V_DDEXTpower supplies are valid. The V_DDINTand V_DDEXTsupplies must be fully ramped to their

1.8 and 3.3 volt rails before RESET can be deasserted.

³The 100 µs minimum assumes a stable CLKIN signal after meeting worst-case start-up timing of crystal oscillator circuits. Refer to the crystal oscillator

manufacturer's data sheet for start-up time. A 25 ms maximum oscillator start-up time can be assumed if using the XTAL pin and internal oscillator

circuit in conjunction with an external crystal. 100 µs is the minimum time required for the PLL to reliably lock to a valid (stable) CLKIN frequency.

RESET

t_VDDRST

t_RSTVDD

VDDINT

VDDEXT

t_VDDRAMP

t_IVDDEVDD

t_CLKVDD

CLKIN

t_CLKRST

CLKDBL

CLK_CFG1-0

t_PLLRST

Figure 11. Power-Up Sequencing for Revisions 0.3, 1.0, and 1.1 (DSP Startup)

–22–

REV. A

ADSP-21161N

Power-Up Sequencing – Silicon Revision 1.2

ThetimingrequirementsforDSPstartupforsiliconwithrevision

1.2 are given in Table 9.

Table 9. Power-Up Sequencing for Revision 1.2 (DSP Startup)

Parameter

Min

Max

Unit

Timing Requirements

t_RSTVDD

t_IVDDEVDD

t_CLKVDD

t_CLKRST

t_PLLRST

t_WRST

RESET Low Before V_DDINT/V_DDEXTon

V_DDINTon Before V_DDEXT

0

–50

0

10

20

4t_CK

ns

ms

µs

ns

+200

200

CLKIN Valid After V_DDINT/V_DDEXTValid¹

CLKIN Valid Before RESET Deasserted²

PLL Control Setup Before RESET Deasserted³

Subsequent RESET Low Pulsewidth⁴

Switching Requirements

t_CORERSTDSP core reset deasserted after RESET deasserted

3, 5

4080t_CK

¹Valid V_DDINT/V_DDEXTassumes that the supplies are fully ramped to their 1.8 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds

of milliseconds depending on the design of the power supply subsystem.

²Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to the crystal oscillator manufacturer's data sheet for

start-up time. Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

³Based on CLKIN cycles

⁴Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly

initialize and propagate default states at all I/O pins.

⁵The 4080 cycle count depends on t_SRSTspecification in Table 11. If setup time is not met, one additional CLKIN cycle may be added to the core reset

time, resulting in 4081 cycles maximum.

RSTOUT does not currently exist for ADSP-21161N revisions

0.3, 1.0, and 1.1. This new signal will be placed on one of the

current no-connect pins: ball B15.

RESET

t_RSTVDD

VDDINT

t_IVDDEVDD

VDDEXT

t_CLKRST

t_CLKVDD

CLKIN

CLKDBL

CLK_CFG1-0

t_PLLRST

t_CORERST

RSTOUT

Figure 12. Power-Up Sequencing for Revision 1.2 (DSP Startup)

During the power-up sequence of the DSP, differences in the

ramp-up rates and activation time between the two supplies can

cause current to flow in the I/O ESD protection circuitry. To

prevent damage to the ESD diode protection circuitry, Analog

Devices recommends including a bootstrap Schottky diode.

The bootstrap Schottky diode is connected between the 1.8 V

and 3.3 V power supplies as shown in Figure 13. It protects the

ADSP-21161N from partially powering the 3.3 V supply.

Including a Schottky diode will shorten the delay between

the supply ramps and thus prevent damage to the ESD diode

REV. A

–23–

ADSP-21161N

protection circuitry. With this technique, if the 1.8 V rail rises

ahead of the 3.3 V rail, the Schottky diode pulls the 3.3 V rail

along with the 1.8 V rail.

DC INPUT

SOURCE

3.3V I/O

VOLTAGE

REGULATOR

V_DDEXT

ADSP-21161N

Clock Input

In systems that use multiprocessing or SBSRAM, CLKDBL

cannot be enabled nor can the systems use an external crystal as

the CLKIN source.

1.8V CORE

VOLTAGE

REGULATOR

V_DDINT

Do not use CLKOUT as the clock source for the SBSRAM

device. Using an external crystal in conjunction with CLKDBL

to generate a CLKOUT frequency is not supported. Negative

hold times can result from the potential skew between CLKIN

and CLKOUT.

Figure 13. Dual Voltage Schottky Diode

Table 10. Clock Input

100 MHz

Parameter

Min

Max

Unit

Timing Requirements

t_CK

CLKIN Period¹

20

7.5

238

119

3

ns

t_CKL

t_CKH

t_CKRF

t_CCLK

CLKIN Width Low¹

CLKIN Width High¹

CLKIN Rise/Fall (0.4 V–2.0 V)

CCLK Period

10

30

Switching Characteristics

t_DCKOOCLKOUT Delay After CLKIN

t_CKOP

t_CKWH

t_CKWL

0

2

ns

CLKOUT Period

CLKOUT Width High

CLKOUT Width Low

t_CKOP–1

t_CKOP/2–2

t_CKOP+1

t_CKOP/2+2

¹CLKIN is dependent on the configuration of the CLKCFGx and CLKDBL pins to achieve desired t_CCLK

.

the necessary components to CLKIN and XTAL. Figure 15

shows the component connections used for a crystal operating in

fundamental mode.

t_CK

CLKIN

t_CKH

t_CKL

CLKIN

XTAL

1

t_CKOP

t_DCKOO

1

t_CKWH

t_CKWL

CLKOUT

X1

C2

27pF

C1

27pF

2

t_DCKOO

2

t_CKOP

t_DCKOO

2

t_CKWL

t_CKWH

SUGGESTED COMPONENTS FOR 100MHz OPERATION:

ECLIPTEK EC2SM-25.000M (SURFACE MOUNT PACKAGE)

ECLIPTEK EC-25.000M (THROUGH-HOLE PACKAGE)

C1 = 27pF

CLKOUT

NOTES:

C2 = 27pF

1. WHEN CLKDBL IS DISABLED, ANY SPECIFICATION TO CLKIN

APPLIES TO THE RISING EDGE, ONLY.

2. WHEN CLKDBL IS ENABLED, ANY SPECIFICATION TO CLKIN

APPLIES TO THE RISING OR FALLING EDGE.

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.

CONTACT CRYSTAL MANUFACTURER FOR DETAILS. THIS 25MHz

CRYSTAL GENERATES A 100MHz CCLK AND A 50MHz EP CLOCK

WITH CLKDBL ENABLED AND A 2:1 PLL MULTIPLY RATIO.

Figure 14. Clock Input

Clock Signals

Figure 15. 100 MHz Operation (Fundamental Mode

Crystal)

The ADSP-21161N can use an external clock or a crystal. See

CLKIN pin description. The programmer can configure the

ADSP-21161N to use its internal clock generator by connecting

–24–

REV. A

ADSP-21161N

Reset

Table 11. Reset

Parameter

Min

Max

Unit

Timing Requirements

t_WRST

t_SRST

RESET Pulsewidth Low¹

4t_CK

8.5

ns

RESET Setup Before CLKIN High²

¹Applies after the power-up sequence is complete.

²Only required if multiple ADSP-21161Ns must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple

ADSP-21161Ns communicating over the shared bus (through the external port), because the bus arbitration logic synchronizes itself automatically

after reset.

CLKIN

t_SRST

t_WRST

RESET

Figure 16. Reset

Interrupts

Table 12. Interrupts

Parameter

Min

Max

Unit

Timing Requirements

t_SIR

t_HIR

t_IPW

IRQ2–0 Setup Before CLKIN¹

IRQ2–0 Hold After CLKIN¹

IRQ2–0 Pulsewidth²

6

0

ns

2 + t_CKOP

¹Only required for IRQx recognition in the following cycle.

²Applies only if t_SIRand t_HIRrequirements are not met.

CLKIN

t_HIR

t_SIR

IRQ2–0

t_IPW

Figure 17. Interrupts

REV. A

–25–

ADSP-21161N

Timer

Table 13. Timer

Parameter

Min

Max

Unit

Switching Characteristic

t_DTEX

CLKIN to TIMEXP

1

7

ns

CLKIN

t_DTEX

TIMEXP

Figure 18. Timer

Flags

Table 14. Flags

Parameter

Min

Max

Unit

Timing Requirement

t_SFI

t_HFI

t_DWRFI

t_HFIWR

FLAG11–0_INSetup Before CLKIN¹

FLAG11–0_INHold After CLKIN¹

4

1

ns

FLAG11–0_INDelay After RD/WR Low¹

12

FLAG11–0_INHold After RD/WR Deasserted¹

0

Switching Characteristics

t_DFO

t_HFO

t_DFOE

t_DFOD

FLAG11–0_OUTDelay After CLKIN

9

5

ns

FLAG11–0_OUTHold After CLKIN

CLKIN to FLAG11–0_OUTEnable

CLKIN to FLAG11–0_OUTDisable

1

¹Flag inputs meeting these setup and hold times for instruction cycle N will affect conditional instructions in instruction cycle N+2.

CLKIN

t_DFO

t_DFOD

t_DFOE

t_HFO

FLAG11–0

CLKIN

OUT

FLAG OUTPUT

t_SFI

t_HFI

FLAG11–0

IN

t_DWRFI

t_HFIWR

WR

RD,

FLAG INPUT

Figure 19. Flags

–26–

REV. A

ADSP-21161N

Memory Read – Bus Master

Use these specifications for asynchronous interfacing to

memories (and memory-mapped peripherals) without reference

to CLKIN. These specifications apply when the ADSP-21161N

is the bus master accessing external memory space in asynchro-

nous access mode.

Table 15. Memory Read – Bus Master

Parameter

Min

Max

Unit

Timing Requirements

t_DAD

t_DRLD

t_HDA

Address, Selects Delay to Data Valid^{1, 2}

RD Low to Data Valid¹

t_CKOP–0.25t_CCLK–11+W ns

0.75t_CKOP–11+W

ns

Data Hold from Address, Selects³

Data Setup to RD High

0

8

1

t_SDS

t_HDRH

t_DAAK

t_DSAK

t_SAKC

t_HAKC

Data Hold from RD High³

ACK Delay from Address, Selects^{2, 4}

ACK Delay from RD Low⁴

ACK Setup to CLKIN⁴

t_CKOP–0.5t_CCLK–12+W

t_CKOP–0.75t_CCLK–11+W ns

0.5t_CCLK+3

1

ns

ACK Hold After CLKIN

Switching Characteristics

t_DRHA

t_DARL

t_RW

Address Selects Hold After RD High

0.25t_CCLK–1+H

0.25t_CCLK–3

t_CKOP–0.5t_CCLK–1+W

0.5t_CCLK–1+HI

ns

Address Selects to RD Low²

RD Pulsewidth

t_RWR

RD High to WR, RD, DMAGx Low

W = (number of wait states specified in WAIT register) × t_CKOP

.

HI = t_CKOP(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

H = t_CKOP(if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).

¹Data Delay/Setup: User must meet t_DAD, t_DRLD, or t_SDS.

²The falling edge of MSx, BMS is referenced.

³Data Hold: User must meet t_HDAor t_HDRHin asynchronous access mode. See Example System Hold Time Calculation on Page 51 for the calculation of

hold times given capacitive and dc loads.

⁴ACK Delay/Setup: User must meet t_DAAK, t_DSAK, or t_SAKCfor deassertion of ACK (Low); all three specifications must be met for assertion of ACK (High).

t_HDA

ADDRESS

MSx, BMS

t_DRHA

t_DARL

t_RW

RD

t_SDS

t_DRLD

t_DAD

t_HDRH

DATA

t_DSAK

t_DAAK

t_RWR

ACK

t_HAKC

t_SAKC

CLKIN

WR, DMAG

Figure 20. Memory Read – Bus Master

REV. A

–27–

ADSP-21161N

Memory Write – Bus Master

Use these specifications for asynchronous interfacing to

memories (and memory-mapped peripherals) without reference

to CLKIN. These specifications apply when the ADSP-21161N

is the bus master accessing external memory space in asynchro-

nous access mode.

Table 16. Memory Write – Bus Master

Parameter

Min

Max

Unit

Timing Requirements

t_DAAK

t_DSAK

t_SAKC

t_HAKC

ACK Delay from Address, Selects^{1, 2}

t_CKOP–0.5t_CCLK–12+W

t_CKOP–0.75t_CCLK–11+W ns

ns

ACK Delay from WR Low¹

ACK Setup to CLKIN¹

ACK Hold After CLKIN¹

0.5t_CCLK+3

1

ns

Switching Characteristics

t_DAWH

t_DAWL

t_WW

t_DDWH

t_DWHA

t_DWHD

t_DATRWH

t_WWR

Address, Selects to WR Deasserted²

t_CKOP– 0.25t_CCLK– 3+W

0.25t_CCLK– 3

t_CKOP– 0.5t_CCLK– 1+W

t_CKOP–0.25t_CCLK– 13.5+W

0.25t_CCLK– 1+H

ns

Address, Selects to WR Low²

WR Pulsewidth

Data Setup Before WR High

Address Hold After WR Deasserted

Data Hold After WR Deasserted

Data Disable After WR Deasserted³

WR High to WR, RD, DMAGx Low 0.5t_CCLK– 1.25+HI

Data Disable Before WR or RD Low 0.25t_CCLK– 3+I

0.25t_CCLK– 1+H

0.25t_CCLK– 2+H

0.25t_CCLK+2.5+H

t_DDWR

t_WDE

W = (number of wait states specified in WAIT register) × t_CKOP

WR Low to Data Enabled

–0.25t_CCLK– 1

.

H = t_CKOP(if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).

HI = t_CKOP(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

I = t_CKOP(if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).

¹ACK Delay/Setup: User must meet t_DAAKor t_DSAKor t_SAKCfor deassertion of ACK (Low); all three specifications must be met for assertion of ACK (High).

²The falling edge of MSx, BMS is referenced.

³See Example System Hold Time Calculation on Page 51 for calculation of hold times given capacitive and dc loads.

ADDRESS

MSx, BMS

t_DAWH

t_DWHA

t_DAWL

t_WW

WR

t_WWR

t_DATRWH

t_DDWR

t_WDE

t_DDWH

DATA

ACK

t_DSAK

t_DWHD

t_DAAK

t_HAKC

t_SAKC

CLKIN

RD, DMAG

Figure 21. Memory Write – Bus Master

–28–

REV. A

ADSP-21161N

Synchronous Read/Write – Bus Master

must meet the slave's timing requirements for synchronous

read/writes (see Synchronous Read/Write – Bus Slave on

Page 30). The slave ADSP-21161N must also meet these (bus

master)timingrequirementsfor data and acknowledgesetupand

hold times.

Use these specifications for interfacing to external memory

systems that require CLKIN, relative to timing or for accessing

aslaveADSP-21161N(inmultiprocessormemoryspace). When

accessing a slave ADSP-21161N, these switching characteristics

Table 17. Synchronous Read/Write – Bus Master

Parameter

Min

Max

Unit

Timing Requirements

t_SSDATI

t_HSDATI

t_SACKC

t_HACKC

Data Setup Before CLKIN

Data Hold After CLKIN

ACK Setup Before CLKIN

ACK Hold After CLKIN

5.5

1

0.5t_CCLK+3

1

ns

Switching Characteristics

t_DADDO

t_HADDO

t_DRDO

t_DWRO

t_DRWL

t_DDATO

t_HDATO

Address, MSx, BMS, BRST, Delay After CLKIN

10

ns

Address, MSx, BMS, BRST, Hold After CLKIN

RD High Delay After CLKIN

WR High Delay After CLKIN

RD/WR Low Delay After CLKIN

Data Delay After CLKIN

1.5

0.25t_CCLK–1

0.25t_CCLK+9

12.5

Data Hold After CLKIN

1.5

CLKIN

t_HADDO

t_DADDO

ADDRESS

MSx, BRST

t_SACKC

t_HACKC

ACK

(IN)

READ CYCLE

t_DRWL

t_DRDO

RD

t_SSDATI

t_HSDATI

DATA

(IN)

WRITE CYCLE

t_DRWL

t_DWRO

WR

t_DDATO

t_HDATO

DATA (OUT)

Figure 22. Synchronous Read/Write – Bus Master

REV. A

–29–

ADSP-21161N

Synchronous Read/Write – Bus Slave

Use these specifications for ADSP-21161N bus master accesses

of a slave’s IOP registers in multiprocessor memory space. The

bus master must meet these (bus slave) timing requirements.

Table 18. Synchronous Read/Write – Bus Slave

Parameter

Min

Max

Unit

Timing Requirements

t_SADDI

t_HADDI

t_SRWI

t_HRWI

t_SSDATI

t_HSDATI

Address, BRST Setup Before CLKIN

Address, BRST Hold After CLKIN

RD/WR Setup Before CLKIN

RD/WR Hold After CLKIN

Data Setup Before CLKIN

5

1

5

1

5.5

1

ns

Data Hold After CLKIN

Switching Characteristics

t_DDATO

t_HDATO

t_DACKC

t_HACKO

Data Delay After CLKIN

12.5

10

ns

Data Hold After CLKIN

ACK Delay After CLKIN

ACK Hold After CLKIN

1.5

CLKIN

t_SADDI

t_HADDI

ADDRESS

ACK

t_HACKO

t_DACKC

READ ACCESS

RD

t_SRWI

t_HRWI

t_DDATO

t_HDATO

DATA

(OUT)

WRITE ACCESS

WR

t_HRWI

t_SRWI

t_SSDATI

t_HSDATI

DATA

(IN)

Figure 23. Synchronous Read/Write – Bus Slave

–30–

REV. A

ADSP-21161N

Host Bus Request

Use these specifications for asynchronous host bus requests of an

ADSP-21161N (HBR, HBG).

Table 19. Host Bus Request

Parameter

Min

Max

Unit

Timing Requirements

t_HBGRCSV

t_SHBRI

t_HHBRI

t_SHBGI

HBG Low to RD/WR/CS Valid

19

ns

HBR Setup Before CLKIN¹

HBR Hold After CLKIN¹

HBG Setup Before CLKIN

HBG Hold After CLKIN

6

1

6

1

t_HHBGI

Switching Characteristics

t_DHBGO

t_HHBGO

t_DRDYCS

t_TRDYHG

t_ARDYTR

HBG Delay After CLKIN

7

ns

HBG Hold After CLKIN

1.5

REDY (O/D) or (A/D) Low from CS and HBR Low²

10

11

REDY (O/D) Disable or REDY (A/D) High from HBG²t_CKOP+14

REDY (A/D) Disable from CS or HBR High²

¹Only required for recognition in the current cycle.

²(O/D) = open drain, (A/D) = active drive.

CLKIN

t_SHBRI

t_HHBRI

HBR

t_{DHBG O}

t_HHBGO

HBG (OUT)

t_SHBGI

t_HHBGI

HBG

(IN)

HBR

CS

t_{DRDY CS}

t_TRDYHG

RE DY

(O/D)

t_ARDYTR

RE DY

(A/D)

t_{HBGRCS V}

HBG (OUT)

RD

WR

CS

O/D = OPEN DRAIN, A/D = ACTIVE DRIVE

Figure 24. Host Bus Request

REV. A

–31–

ADSP-21161N

Multiprocessor Bus Request

Use these specifications for passing of bus mastership between

multiprocessing ADSP-21161Ns (BRx).

Table 20. Multiprocessor Bus Request

Parameter

Min

Max

Unit

Timing Requirements

t_SBRI

t_HBRI

t_SPAI

t_HPAI

t_SRPBAI

t_HRPBAI

BRx, Setup Before CLKIN High

BRx, Hold After CLKIN High

PA Setup Before CLKIN High

PA Hold After CLKIN High

RPBA Setup Before CLKIN High

RPBA Hold After CLKIN High

9

0.5

9

1

6

ns

2

Switching Characteristics

t_DBRO

t_HBRO

t_DPASO

t_TRPAS

t_DPAMO

t_PATR

BRx Delay After CLKIN High

BRx Hold After CLKIN High

PA Delay After CLKIN High, Slave

PA Disable After CLKIN High, Slave

PA Delay After CLKIN High, Master

PA Disable Before CLKIN High, Master

8

ns

1.0

8

1.5

0.25t_CCLK+9

0.25t_CCLK–5

CLKIN

t_DBRO

t_HBRO

BRx (OUT)

t_{DP A SO}

t_TRPAS

PA (OUT)

(S LAV E)

t_DPAMO

t_{P AT R}

PA (OUT)

(MASTER)

t_SBRI

t_HBRI

BRx (IN)

t_{S PAI}

t_HPAI

PA (IN)

(O/D)

t_{S RPBAI}

t_{HR P B AI}

RP BA

O/D = OPEN DRAIN

Figure 25. Multiprocessor Bus Request

–32–

REV. A

ADSP-21161N

Asynchronous Read/Write – Host to ADSP-21161N

Usethesespecificationsforasynchronoushostprocessoraccesses

of an ADSP-21161N, after the host has asserted CS and HBR

(low). AfterHBG isreturnedbytheADSP-21161N, thehostcan

drive the RD and WR pins to access the ADSP-21161N’s IOP

registers. HBR and HBG are assumed low for this timing.

Although the DSP will recognize HBR asserted before reset, a

HBG will not be returned by the DSP until after reset is deas-

serted and the DSP completes bus synchronization.

Note: Host internal memory access is not supported.

Table 21. Read Cycle

Parameter

Min

Max

Unit

Timing Requirements

t_SADRDL

t_HADRDH

t_WRWH

t_DRDHRDY

Address Setup and CS Low Before RD Low

Address Hold and CS Hold Low After RD

RD/WR High Width

RD High Delay After REDY (O/D) Disable

RD High Delay After REDY (A/D) Disable

0

2

3.5

0

ns

Switching Characteristics

t_SDATRDY

t_DRDYRDL

t_RDYPRD

t_HDARWH

Data Valid Before REDY Disable from Low

REDY (O/D) or (A/D) Low Delay After RD Low

REDY (O/D) or (A/D) Low Pulsewidth for Read

2

ns

10

6

1.5t_CCLK

2

Data Disable After RD High

Table 22. Write Cycle

Parameter

Min

Max

Unit

Timing Requirements

t_SCSWRL

t_HCSWRH

t_SADWRH

t_HADWRH

t_WWRL

CS Low Setup Before WR Low

0

6

2

ns

CS Low Hold After WR High

Address Setup Before WR High

Address Hold After WR High

WR Low Width

RD/WR High Width

WR High Delay After REDY (O/D) or (A/D) Disable

Data Setup Before WR High

t

_CCLK+1

t_WRWH

3.5

0

5

t_DWRHRDY

t_SDATWH

t_HDATWH

Data Hold After WR High

4

Switching Characteristics

t_DRDYWRL

REDY (O/D) or (A/D) Low Delay After WR/CS Low¹

t_RDYPWR

REDY (O/D) or (A/D) Low Pulsewidth for Write¹

11

ns

12

¹Only when slave write FIFO is full.

REV. A

–33–

ADSP-21161N

READ CYCLE

ADDRESS/CS

t_SADRDL

t_HADRDH

t_WRWH

RD

t_{HDARW H}

DATA (OUT)

t_{SDAT RDY}

t_DRDYRDL

t_DRDHRDY

t_RDYPRD

REDY (O/D)

REDY (A/D)

WRITE CY CLE

ADDRESS

t_{SADW RH}

t_{HADW RH}

t_{SCS WRL}

t_HCSWRH

CS

t_WWRL

t_{W RW H}

WR

t_SDATWH

t_HDATWH

DATA (IN)

t_DRDYWRL

t_{RDYPW R}

t_DWRHRDY

REDY (O/D)

REDY (A/D)

O/D = OPEN DRAIN, A/D = ACTIVE DRIVE

Figure 26. Asynchronous Read/Write – Host to ADSP-21161N

–34–

REV. A

ADSP-21161N

Three-State Timing – Bus Master, Bus Slave

These specifications show how the memory interface is disabled

(stops driving) or enabled (resumes driving) relative to CLKIN

and the SBTS pin. This timing is applicable to bus master tran-

sition cycles (BTC) and host transition cycles (HTC) as well as

the SBTS pin.

During reset, the DSP will not respond to SBTS, HBR, and

MMS accesses. Although the DSP will recognize HBR asserted

before reset, a HBG will not be returned by the DSP until after

reset is deasserted and the DSP completes bus synchronization.

Table 23. Three-State Timing – Bus Master, Bus Slave

Parameter

Min

Max

Unit

Timing Requirements

t_STSCK

t_HTSCK

SBTS Setup Before CLKIN

SBTS Hold After CLKIN

6

2

ns

Switching Characteristics

t_MIENA

t_MIENS

t_MIENHG

t_MITRA

Address/Select Enable After CLKIN High

1.5

−1.5

1.5

9

+9

9

ns

Strobes Enable After CLKIN High¹

HBG Enable After CLKIN

Address/Select Disable After CLKIN High

Strobes Disable After CLKIN High

HBG Disable After CLKIN²

–0.5t_CKOP–20

t_CKOP– 0.25t_CCLK−17

0.5t_CKOP+N×t_CCLK–20 0.5t_CKOP+N×t_CCLK–15

1.5

–0.5t_CKOP–15

t_CKOP– 0.25t_CCLK−12.5

t_MITRS

t_MITRHG

t_DATEN

t_DATTR

t_ACKEN

t_ACKTR

t_CDCEN

t_CDCTR

t_ATRHBG

t_STRHBG

t_BTRHBG

t_MENHBG

Data Enable After CLKIN³

10

6

9

5

Data Disable After CLKIN³

ACK Enable After CLKIN High

ACK Disable After CLKIN High

CLKOUT Enable After CLKIN²

CLKOUT Disable After CLKIN

Address/Select Disable Before HBG Low⁴

1.5

0.2

0.5t_CKOP+N×t_CCLK

0.5t_CKOP+N×t_CCLK+5

t_CKOP

1.5t_CKOP+2

t_CKOP+ 0.25t_CCLK+3

0.5t_CKOP+2

t_CKOP+5

t

_CKOP−5

1.5t_CKOP–6

RD/WR/DMAGx Disable Before HBG Low⁴t_CKOP+ 0.25t_CCLK−4

BMS Disable Before HBG Low⁴

0.5t_CKOP–4

t_CKOP–5

Memory Interface Enable After HBG High⁴

¹Strobes = RD, WR, DMAGx.

²Where N = 0.5, 1.0, 1.5 for 1:2, 1:3, and 1:4, respectively.

³In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.

⁴Memory Interface = Address, RD, WR, MSx, DMAGx, and BMS (in EPROM boot mode). BMS is only an output in EPROM boot mode.

REV. A

–35–

ADSP-21161N

CLKIN

t_STSCK

t_HTSCK

SBTS

t_MIENA,t_MIENS,t_MIENHG

t_MITRA,t_MITRS,t_MITRHG

MEMORY

INTERFACE

t_DATEN

t_DATTR

DATA

ACK

t_ACKEN

t_ACKTR

CLKIN

t_CDCEN

t_CDCTR

CLKOUT

HBG

t_MENHBG

t_ATRHBG,t_STRHBG,t_BTRHBG

MEMORY

INTERFACE

MEMORY INTERFACE = ADDRESS, RD, WR, MSx, DMAGx, BMS (IN EPROM MODE)

Figure 27. Three-State Timing – Bus Master, Bus Slave

–36–

REV. A

ADSP-21161N

DMA Handshake

DMAG signals. For Paced Master mode, the data transfer is

These specifications describe the three DMA handshake modes.

In all three modes DMAR is used to initiate transfers. For

handshake mode, DMAG controls the latching or enabling of

data externally. For external handshake mode, the data transfer

controlled by ADDR23–0, RD, WR, MS3–0, and ACK (not

DMAG). For Paced Master mode, the Memory Read-Bus

Master, Memory Write-Bus Master, and Synchronous

Read/Write-Bus Master timing specifications for ADDR23

–0,

is controlled by the ADDR23–0, RD, WR, MS3–0, ACK, and

RD

,

WR

,

MS3–0, DATA47

–

16, and ACK also apply.

Table 24. DMA Handshake

Parameter

Min

Max

Unit

Timing Requirements

t_SDRC

t_WDR

DMARx Setup Before CLKIN¹

DMARx Width Low (Nonsynchronous)²

Data Setup After DMAGx Low³

Data Hold After DMAGx High

Data Valid After DMARx High³

DMARx Low Edge to Low Edge⁴

DMARx Width High²

3.5

t_CCLK+4.5

ns

t_SDATDGL

t_HDATIDG

t_DATDRH

t_DMARLL

t_DMARH

t_CKOP– 0.5t_CCLK–7

t_CKOP+3

2

t_CKOP

t_CCLK+4.5

Switching Characteristics

t_DDGL

t_WDGH

t_WDGL

t_HDGC

t_VDATDGH

t_DATRDGH

t_DGWRL

t_DGWRH

t_DGWRR

t_DGRDL

t_DRDGH

t_DGRDR

t_DGWR

DMAGx Low Delay After CLKIN

DMAGx High Width

DMAGx Low Width

0.25t_CCLK+1

0.5t_CCLK– 1+HI

t_CKOP– 0.5t_CCLK– 1

t_CKOP– 0.25t_CCLK+1.0

t_CKOP– 0.25t_CCLK– 8

0.25t_CCLK– 3

–1.5

t_CKOP– 0.5t_CCLK– 2 +W

–1.5

0.25t_CCLK+9

ns

DMAGx High Delay After CLKIN

Data Valid Before DMAGx High⁵

Data Disable After DMAGx High⁶

WRx Low Before DMAGx Low

DMAGx Low Before WRx High

WRx High Before DMAGx High⁷

RDx Low Before DMAGx Low

RDx Low Before DMAGx High

RDx High Before DMAGx High⁷

DMAGx High to WRx, RDx Low

Address/Select Valid to DMAGx High

Address/Select Hold After DMAGx High

t_CKOP– 0.25t_CCLK+9

t_CKOP– 0.25t_CCLK+5

0.25t_CCLK+4

+2

t_CKOP– 0.5t_CCLK–2+W

–1.5

0.5t_CCLK– 2+HI

15

+2

t_DADGH

t_DDGHA

1

W = (number of wait states specified in WAIT register) × t_CKOP

.

HI = t_CKOP(if data bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

¹Only required for recognition in the current cycle.

²Maximum throughput using DMARx/DMAGx handshaking equals t_WDR+ t_DMARH= (t_CCLK+4.5) + (t_CCLK+4.5)=29 ns (34.5 MHz). This throughput

limit applies to non-synchronous access mode only.

³t_SDATDGLis the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of

the write, the data can be driven t_DATDRHafter DMARx is brought high.

⁴Use t_DMARLLif DMARx transitions synchronous with CLKIN. Otherwise, use t_WDRand t_DMARH

.

⁵t_VDATDGHis valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then

t_VDATDGH= t_CKOP– 0.25t_CCLK– 8 + (n × t_CKOP) where n equals the number of extra cycles that the access is prolonged.

⁶See Example System Hold Time Calculation on Page 51 for calculation of hold times given capacitive and dc loads.

⁷This parameter applies for synchronous access mode only.

REV. A

–37–

ADSP-21161N

CLKIN

t_DMARLL

t_SDRC

t_DMARH

t_WDR

DMARx

DMAGx

t_HDGC

t_DDGL

t_WDGL

t_WDGH

TRANSFERS BETWEEN ADSP-21161N

INTERNAL MEMORY AND EXTERNAL DEVICE

t_DATRDGH

t_VDATDGH

DATA

(FROM ADSP-2116x TO EXTERNAL DRIVE)

t_DATDRH

t_HDATIDG

t_SDATDGL

DATA

(FROM EXTERNAL DRIVE TO ADSP-21161N)

TRANSFERS BETWEEN EXTERNAL DEVICE AND

1

EXTERNAL MEMORY (EXTERNAL HANDSHAKE MODE)

t_DGWRL

t_DGWRH

t_DGWR

t_DGWRR

(EXTERNAL DEVICE TO EXTERNAL MEMORY)

WR

RD

t_DGRDR

t_DGRDL

(EXTERNAL MEMORY TO EXTERNAL DEVICE)

t_DRDGH

t_DDGHA

t_DADGH

ADDRESS

MSx

1

MEMORY READ BUS MASTER, MEMORY WRITE BUS MASTER, OR SYNCHRONOUS READ/WRITE BUS MASTER

TIMING SPECIFICATIONS FOR ADDR23–0, RD, WR, MS3-0 AND ACK ALSO APPLY HERE.

Figure 28. DMA Handshake

–38–

REV. A

ADSP-21161N

SDRAM Interface – Bus Master

Use these specifications for ADSP-21161N bus master accesses

of SDRAM:

Table 25. SDRAM Interface – Bus Master

Parameter

Min

Max

Unit

Timing Requirements

t_SDSDK

t_HDSDK

Data Setup Before SDCLK

Data Hold After SDCLK

2.0

2.3

ns

Switching Characteristics

t_DSDK1

First SDCLK Rise Delay After CLKIN^{1, 2}0.75t_CCLK+ 1.5

t_SDK

t_SDKH

t_SDKL

0.75t_CCLK+ 8.0

2 × t_CCLK

ns

SDCLK Period

SDCLK Width High

SDCLK Width Low

t_CCLK

4

t_DCADSDK

Command, Address, Data, Delay After

0.25t_CCLK+2.5

0.5t_CCLK+ 2.0

SDCLK³

t_HCADSDK

Command, Address, Data, Hold After

SDCLK³

2.0

ns

t_SDTRSDK

t_SDENSDK

t_SDCTR

Data Three-State After SDCLK⁴

Data Enable After SDCLK⁵

Command Three-State After CLKIN

Command Enable After CLKIN

SDCLK Three-State After CLKIN

SDCLK Enable After CLKIN

Address Three-State After CLKIN

Address Enable After CLKIN

ns

0.75t_CCLK

0.5t_CCLK–1.5

2

0

0.5t_CCLK+ 6.0

5

3

4

−0.25t_CCLK

+7.2

t_SDCEN

t_SDSDKTR

t_SDSDKEN

t_SDATR

1

−0.25 t_CCLK−5

−0.4

t_SDAEN

¹For the second, third, and fourth rising edges of SDCLK delay from CLKIN, add appropriate number of SDCLK period to the t_DSDK1and t_SSDKC1values,

depending upon the SDCKR value and the core clock to CLKIN ratio.

²Subtract t_CCLKfrom result if value is greater than or equal to t_CCLK

.

³Command = SDCKE, MSx, DQM, RAS, CAS, SDA10, and SDWE

⁴SDRAM Controller adds one SDRAM CLK three-stated cycle delay on a read, followed by a write.

⁵Valid when DSP transitions to SDRAM master from SDRAM slave.

SDRAM Interface – Bus Slave

These timing requirements allow a bus slave to sample the bus

master’s SDRAM command and detect when a refresh occurs:

Table 26. SDRAM Interface – Bus Slave

Parameter

Timing Requirements

Min

Max

Unit

ns

t_SSDKC1

t_SCSDK

t_HCSDK

First SDCLK Rise

SDCK ꢀ t_CCLK−0.5t_CCLK− 0.5

SDCKR ꢀ t_CCLK−0.25t_CCLK+ 2.0

after CLKOUT^{1, 2, 3}

Command Setup

before SDCLK⁴

Command Hold

after SDCLK⁴

2

1

ns

¹For the second, third, and fourth rising edges of SDCLK delay from CLKOUT, add appropriate number of SDCLK period to the t_DSDK1and t_SSDKC1

values, depending upon the SDCKR value and the Core clock to CLKOUT ratio.

²SDCKR = 1 for SDCLK equal to core clock frequency and SDCKR = 2 for SDCLK equal to half core clock frequency.

³Subtract t_CCLKfrom result if value is greater than or equal to t_CCLK

.

⁴Command = SDCKE, RAS, CAS, and SDWE.

REV. A

–39–

ADSP-21161N

CLKIN

t_DSDK1

t_SDKH

t_SDK

SDCLK

t_SDSDK

t_SDKL

t_HDSDK

DATA(IN)

t_SDTRSDK

t_HCADSDK

t_DCADSDK

t_SDENSDK

DATA(OUT)

t_DCADSDK

1

CMND ADDR

(OUT)

t_HCADSDK

t_SDCEN

t_SDCTR

1

CMND (OUT)

ADDR

(OUT)

t_SDAEN

t_SDATR

CLKIN

t_SDSDKTR

t_SDSDKEN

SDCLK

CLKOUT

t_SSDKC1

SDCLK (IN)

t_SCSDK

2

CMND (IN)

t_HCSDK

1

COMMAND = SDCKE, MSx, RAS, CAS, SDWE, DQM, AND SDA10.

COMMAND = SDCKE, RAS, CAS, AND SDWE.

2

Figure 29. SDRAM Interface

–40–

REV. A

ADSP-21161N

Link Ports

willresultinunrealisticallysmallskewtimesbecausetheyinclude

multiple tester guardbands. The setup and hold skew times

shown below are calculated to include only one tester guardband.

Calculation of link receiver data setup and hold relative to link

clock is required to determine the maximum allowable skew that

can be introduced in the transmission path between LDATA and

LCLK. Setup skew is the maximum delay that can be introduced

in LDATA relative to LCLK, (setup skew = t_LCLKTWHmin– t_DLDCH

–t_SLDCL). Holdskewisthemaximumdelaythatcanbeintroduced

in LCLK relative to LDATA, (hold skew = t_LCLKTWLmin – t_HLDCH

– t_HLDCL). Calculations made directly from speed specifications

ADSP-21161N Setup Skew = 1.5 ns max

ADSP-21161N Hold Skew = 1.5 ns max

Note that there is a two-cycle effect latency between the link port

enable instruction and the DSP enabling the link port.

Table 27. Link Ports – Receive

Parameter

Min

Max

Unit

Timing Requirements

t_SLDCL

t_HLDCL

t_LCLKIW

t_LCLKRWL

t_LCLKRWH

Data Setup Before LCLK Low

Data Hold After LCLK Low

LCLK Period

LCLK Width Low

LCLK Width High

1

ns

3.5

t_LCLK

4.0

Switching Characteristics

t_DLALC

LACK Low Delay After LCLK High¹

8

12

ns

¹LACK goes low with t_DLALCrelative to rise of LCLK after first nibble, but does not go low if the receiver's link buffer is not about to fill.

RECEIVE

t_LCLKIW

t_LCLKRWH

t_LCLKRWL

LCLK

t_HLDCL

t_SLDCL

IN

LDAT7-0

t_DLALC

LACK (OUT)

Figure 30. Link Ports—Receive

REV. A

–41–

ADSP-21161N

Table 28. Link Ports – Transmit

Parameter

Min

Max

Unit

Timing Requirements

t_SLACH

t_HLACH

LACK Setup Before LCLK High

LACK Hold After LCLK High

8

–2

ns

Switching Characteristics

t_DLDCH

t_HLDCH

t_LCLKTWL

t_LCLKTWH

t_DLACLK

Data Delay After LCLK High

Data Hold After LCLK High

LCLK Width Low

LCLK Width High

LCLK Low Delay After LACK High

3

ns

0

0.5t_LCLK–1.0

0.5t_LCLK+3

0.5t_LCLK+1.0

3t_LCLK+11

TRANSMIT

LCLK INACTIVE

(HIGH)

LAST NIBBLE/BYTE

TRANSMITTED

FIRST NIBBLE/BYTE

TRANSMITTED

t_LCLKTWH

t_LCLKTWL

LCLK

t_DLDCH

t_HLDCH

LDAT7-0

OUT

t_DLACLK

t_SLACH

t_HLACH

LACK (IN)

THE t_SLACHREQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED.

Figure 31. Link Ports—Transmit

–42–

REV. A

ADSP-21161N

Serial Ports

To determine whether communication is possible between two

devices at clock speed n, the following specifications must be

confirmed: 1) frame sync delay and frame sync setup and hold,

2) data delay and data setup and hold, and 3) SCLK width.

Table 29. Serial Ports – External Clock

Parameter

Min

Max

Unit

Timing Requirements

t_SFSE

Transmit/Receive FS Setup Before Transmit/Receive

3.5

4

ns

SCLK¹

t_HFSE

Transmit/Receive FS Hold After Transmit/Receive

SCLK¹

t_SDRE

t_HDRE

t_SCLKW

t_SCLK

Receive Data Setup Before Receive SCLK¹

Receive Data Hold After Receive SCLK¹

SCLKx Width

1.5

4

7

ns

SCLKx Period

2t_CCLK

¹Referenced to sample edge.

Table 30. Serial Ports – Internal Clock

Parameter

Min

Max

Unit

Timing Requirements

t_SFSI

FS Setup Time Before SCLK (Transmit/Receive Mode)¹

8

ns

t_HFSI

t_SDRI

t_HDRI

FS Hold After SCLK (Transmit/Receive Mode)¹

Receive Data Setup Before SCLK¹

0.5t_CCLK+1

4

3

Receive Data Hold After SCLK¹

¹Referenced to sample edge.

Table 31. Serial Ports – External Clock

Parameter

Min

Max

Unit

Switching Characteristics

t_DFSE

FS Delay After SCLK (Internally Generated FS) ^{1, 2, 3}

13

16

ns

t_HOFSE

t_DDTE

t_HDTE

FS Hold After SCLK (Internally Generated FS)^{1, 2 , 3}

Transmit Data Delay After SCLK ^{1, 2}

3

0

Transmit Data Hold After SCLK ^{1, 2}

¹Referenced to drive edge.

²SCLK/FS Configured as a transmit clock/frame sync with the DDIR bit = 1 in SPCTLx register.

³SCLK/FS Configured as a receive clock/frame sync with the DDIR bit = 0 in SPCTLx register.

Table 32. Serial Ports – Internal Clock

Parameter

Min

Max

Unit

Switching Characteristics

t_DFSI

FS Delay After SCLK (Internally Generated FS)^{1, 2, 3}

4.5

ns

t_HOFSI

t_DDTI

t_HDTI

t_SCLKIW

FS Hold After SCLK (Internally Generated FS)^{1, 2, 3}

Transmit Data Delay After SCLK^{1, 2}

Transmit Data Hold After SCLK^{1, 2}

SCLK Width²

–1.5

7.5

0

0.5t_SCLK–2.5

0.5t_SCLK+2

¹Referenced to drive edge.

²SCLK/FS Configured as a transmit clock/frame sync with the DDIR bit = 1 in SPCTLx register.

³SCLK/FS Configured as a receive clock/frame sync with the DDIR bit = 0 in SPCTLx register.

REV. A

–43–

ADSP-21161N

Table 33. Serial Ports – Enable and Three-State

Parameter

Min

Max

Unit

Switching Characteristics

t_DDTEN

t_DDTTE

t_DDTIN

t_DDTTI

Data Enable from External Transmit SCLK^{1, 2}

4

0

ns

Data Disable from External Transmit SCLK¹

Data Enable from Internal Transmit SCLK¹

Data Disable from Internal Transmit SCLK¹

10

3

¹Referenced to drive edge.

²SCLK/FS Configured as a transmit clock/frame sync with the DDIR bit = 1 in SPCTLx register.

Table 34. Serial Ports – External Late Frame Sync

Parameter

Min

Max

Unit

Switching Characteristics

t_DDTLFSE

Data Delay from Late External Transmit FS or External

13

ns

Receive FS with MCE = 1, MFD = 0¹

t_DDTENFS

Data Enable from Late FS or MCE = 1, MFD = 0¹

0.5

¹MCE = 1, Transmit FS enable and Transmit FS valid follow t_DDTLFSEand t_DDTENFS

.

–44–

REV. A

ADSP-21161N

DATA RECEIVE— INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DATA RECEIVE— EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

t_SCLKIW

t_SCLKW

SCLK

t_DFSI

t_DFSE

t_SFSE

t_HOFSI

t_SFSI

t_HFSI

t_HOFSE

t_HFSE

FS

t_HDRE

t_SDRI

t_HDRI

t_SDRE

D_XA/D_X

B

D_XA/D_X

B

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DATA TRANSMIT — INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DATA TRANSMIT — EXTERNAL CLOCK

DRIVE EDGE

SAMPLE EDGE

t_SCLKIW

t_SCLKW

SCLK

t_DFSI

t_DFSE

t_HOFSI

t_SFSI

t_HFSI

t_HOFSE

t_SFSE

t_HFSE

FS

t_DDTE

t_DDTI

t_HDTE

t_HDTI

D_XA/D_X

B

D_XA/D_X

B

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DRIVE EDGE

SCLK

SCLK (EXT)

t_DDTEN

t_DDTTE

D_XA/D_X

B

DRIVE EDGE

SCLK (INT)

SCLK

t_DDTIN

t_DDTTI

D_XA/D_XB

Figure 32. Serial Ports

REV. A

–45–

ADSP-21161N

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

DRIVE

SAMPLE

DRIVE

SCLK

FS

t_SFSE/I

t_HOFSE/I

t_DDTE/I

t_DDTENFS

t_HDTE/I

D A/D B

1ST BIT

2ND BIT

X

t_DDTLFSE

LATE EXTERNAL TRANSMIT FS

DRIVE

SAMPLE

DRIVE

SCLK

FS

t_SFSE/I

t_HOFSE/I

t_DDTE/I

t_DDTENFS

t_HDTE/I

D A/D B

1ST BIT

2ND BIT

X

t_DDTLFSE

Figure 33. Serial Ports – External Late Frame Sync

–46–

REV. A

ADSP-21161N

SPI Interface Specifications

Table 35. SPI Interface Protocol – Master Switching and Timing

Parameter

Min

Max

Unit

Timing Requirements

t_SSPIDM

Data Input Valid to SPICLK Edge (Data Input Set-up

Time)

0.5t_CCLK+10

ns

t_HSPIDM

t_SPITDM

SPICLK Last Sampling Edge to Data Input Not Valid

Sequential Transfer Delay

0.5t_CCLK+1

2t_CCLK

ns

Switching Characteristics

t_SPICLKMSerial Clock Cycle

t_SPICHM

8 t_CCLK

4t_CCLK–4

ns

Serial Clock High Period

t_SPICLM

Serial Clock Low Period

t_DDSPIDM

t_HDSPIDM

t_{SDSCIM_0}

SPICLK Edge to Data Out Valid (Data Out Delay Time)

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

FLAG3–0 (SPI Device Select) Low to First SPICLK Edge 5t_CCLK

for CPHASE = 0

3

0

t_{SDSCIM_1}

t_HDSM

FLAG3–0 (SPI Device Select) Low to First SPICLK Edge 3t_CCLK

for CPHASE = 1

ns

Last SPICLK Edge to FLAG3–0 High

t_CCLK–3

Table 36. SPI Interface Protocol – Slave Switching and Timing

Parameter

Min

Max

Unit

Timing Requirements

t_SPICLKS

t_SPICHS

t_SPICLS

t_SDSCO

Serial Clock Cycle

8t_CCLK

4t_CCLK–4

ns

Serial Clock High Period

Serial Clock Low Period

SPIDS Assertion to First SPICLK Edge

CPHASE = 0

3.5t_CCLK+8

1.5t_CCLK+8

ns

CPHASE = 1

t_HDS

Last SPICLK Edge to SPIDS Not Asserted

CPHASE = 0

0

ns

t_SSPIDS

t_HSPIDS

t_SDPPW

Data Input Valid to SPICLK Edge (Data Input Set-up Time) 0

SPICLK Last Sampling Edge to Data Input Not Valid

SPIDS Deassertion Pulsewidth (CPHASE = 0)

t_CCLK+1

t_CCLK

Switching Characteristics

t_DSOE

t_DSDHI

SPIDS Assertion to Data Out Active

SPIDS Deassertion to Data High Impedance

2

1.5

0.5t_CCLK+5.5 ns

t_DDSPIDS

SPICLK Edge to Data Out Valid (Data Out Delay Time)

SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 0.25t_CCLK+3

SPICLK Edge to Last Bit Out Not Valid

(Data Out Hold Time) for LSB

SPIDS Assertion to Data Out Valid (CPHASE = 0)

0.75t_CCLK+3

ns

1

t_HDSPIDS

1

t_HDLSBS

0.5t_SPICLK+4.5t_CCLK

2

t_DSOV

1.5t_CCLK+7

ns

¹When CPHASE = 0 and baud rate is greater than 1, t_HDLSBSaffects the length of the last bit transmitted.

²Applies to the first deassertion of SPIDS only.

REV. A

–47–

ADSP-21161N

FLAG3-0

(OUTPUT)

t_SDSCIM

t_SPICHM

t_SPICLM

t_SPICLKM

t_HDSM

t_SPITDM

SPICLK

(CP = 0)

(OUTPUT)

t_SPICLM

t_SPICHM

SPICLK

(CP = 1)

(OUTPUT)

t_HDSPIDM

t_{DD SPID M}

MOSI

(OUTPUT)

MSB

LSB

t_{SSPID M}

CPHASE = 1

t_HSSPIDM

t_HSPIDM

MISO

(INPUT)

MSB

VALID

LSB

VALID

t_{D DSPIDM}

t_{HD SPIDM}

MOSI

(OUTPUT)

MSB

LSB

t_SSPIDM

CPHASE = 0

t_HSPIDM

MSB

VALID

LSB

VALID

MISO

(INPUT)

Figure 34. SPI Interface Protocol – Master Switching and Timing

–48–

REV. A

ADSP-21161N

SPIDS

(INPUT)

t_SPICHS

t_SPICLS

t_SPICLKS

t_HDS

t_SDPPW

SPICLK

(CP = 0)

(INPUT)

t_SDSCO

t_{SPIC LS}

t_SPICHS

SPICLK

(CP = 1)

(INPUT)

t_DDSPIDS

t_{DSO E}

t_HDSPIDS

MSB

t_{D DSPIDS}

t_DSDHI

LSB

MISO

(OUTPUT)

t_{H SPID S}

CPHASE = 1

t_SSPIDS

t_HSPIDS

t_SSPIDS

MOSI

MSB

LSB

(INPUT)

VALID

t_{DSO V}

t_{DSO E}

t_DSDHI

t_{D DSPID S}

t_HDLSBS

LSB

MISO

(OUTPUT)

MSB

t_HSPIDS

CPHASE = 0

t_SSPIDS

LSB

VALID

MOSI

(INPUT)

MSB VALID

Figure 35. SPI Interface Protocol – Slave Switching and Timing

REV. A

–49–

ADSP-21161N

JTAG Test Access Port and Emulation

Table 37. JTAG Test Access Port and Emulation

Parameter

Min

Max

Unit

Timing Requirements

t_TCK

TCK Period

t_CK

5

6

2

15

4t_CK

ns

t_STAP

t_HTAP

t_SSYS

t_HSYS

t_TRSTW

TDI, TMS Setup Before TCK High

TDI, TMS Hold After TCK High

System Inputs Setup Before TCK Low¹

System Inputs Hold After TCK Low¹

TRST Pulsewidth

Switching Characteristics

t_DTDOTDO Delay from TCK Low

t_DSYS

System Outputs Delay After TCK Low²

13

30

ns

¹System Inputs = DATA47–16, ADDR23–0, RD, WR, ACK, RPBA, SPIDS, EBOOT, LBOOT, DMAR2–1, CLK_CFG1–0, CLKDBL, CS, HBR,

SBTS, ID2–0, IRQ2–0, RESET, BMS, MISO, MOSI, SPICLK, DxA, DxB, SCLKx, FSx, LxDAT7–0, LxCLK, LxACK, SDWE, HBG, RAS, CAS,

SDCLK0, SDCKE, BRST, BR6–1, PA, MS3–0, FLAG11–0.

²System Outputs = BMS, MISO, MOSI, SPICLK, DxA, DxB, SCLKx, FSx, LxDAT7–0, LxCLK, LxACK, DATA47–16, SDWE, ACK, HBG, RAS,

CAS, SDCLK1–0, SDCKE, BRST, RD, WR, BR6–1, PA, MS3–0, ADDR23–0, FLAG11–0, DMAG2–1, DQM, REDY, CLKOUT, SDA10,

TIMEXP, EMU, BMSTR, RSTOUT.

t_TCK

TCK

t_STAP

t_HTAP

TMS

TDI

t_DTDO

TDO

t_SSYS

t_HSYS

SYSTEM

INPUTS

t_DSYS

SYSTEM

OUTPUTS

Figure 36. JTAG Test Access Port and Emulation

–50–

REV. A

ADSP-21161N

Output Drive Currents

Figure 37 shows typical I-V characteristics for the output drivers

of the ADSP-21161N. The curves represent the current drive

capability of the output drivers as a function of output voltage.

REFERENCE

SIGNAL

t_MEASURED

t_DIS

V_OH

t_ENA

80

V_OH

(MEASURED)

V

_OH(MEASURED) – ꢃV

60

2.0V

1.0V

(MEASURED)

V_DDEXT= 3.47V, –40°C

V_OL(MEASURED) + ꢃV

50

V_OL

V_DDEXT= 3.3V, +25°C

(MEASURED)

t_DECAY

40

30

V_DDEXT= 3.13V, +105°C

20

OUTPUT STOPS DRIVING

OUTPUT STARTS DRIVING

10

0

HIGH IMPEDANCE STATE.

TEST CONDITIONS CAUSE THIS

–10

–20

–30

VOLTAGE TO BE APPROXIMATELY 1.5V.

Figure 38. Output Enable/Disable

V_DDEXT= 3.47V, –40°C

–40

and the input threshold for the device requiring the hold time. A

typical V will be 0.4 V. C_Lis the total bus capacitance (per data

line), and I_Lis the total leakage or three-state current (per data

line). The hold time will be t_DECAYplus the minimum disable time

(i.e., t_DATRWHfor the write cycle).

V_DDEXT= 3.3V, +25°C

–50

∆

–60

–80

V_DDEXT= 3.13V, +105°C

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

SWEEP (V_DDEXT) VOLTAGE – V

Figure 37. Typical Drive Currents

Test Conditions

50ꢁ

TO

OUTPUT

The DSP is tested for output enable, disable, and hold time.

1.5V

Output Enable Time

Output pins are considered to be enabled when they have made

a transition from a high impedance state to the point when they

start driving. The output enable time t_ENAis the interval from the

point when a reference signal reaches a high or low voltage level

to the point when the output has reached a specified high or low

trip point, as shown in the Output Enable/Disable diagram

(Figure 38). If multiple pins (such as the data bus) are enabled,

the measurement value is that of the first pin to start driving.

30pF

Figure 39. 31Equivalent Device Loading for AC

Measurements (Includes All Fixtures)

Output Disable Time

INPUT

OR

OUTPUT

1.5V

Outputpinsareconsideredtobedisabledwhentheystopdriving,

go into a high impedance state, and start to decay from their

output high or low voltage. The time for the voltage on the bus

to decay by

∆

V is dependent on the capacitive load, C_Land the

Figure 40. Voltage Reference Levels for AC

Measurements (Except Output Enable/Disable)

load current, I_L. This decay time can be approximated by the

following equation:

(C_L∆V)

--------------------

=

t_DECAY

I_L

The output disable time t_DISis the difference between t_MEASURED

and t_DECAYas shown in Figure 38. The time t_MEASUREDis the

interval from when the reference signal switches to when the

output voltage decays

output low voltage. t_DECAYis calculated with test loads C_Land I_L,

and with V equal to 0.5 V.

∆V from the measured output high or

∆

Example System Hold Time Calculation

To determine the data output hold time in a particular system,

first calculate t_DECAYusing the equation given above. Choose ∆V

to be the difference between the ADSP-21161N’s output voltage

REV. A

–51–

ADSP-21161N

225-BALL METRIC MBGA PIN CONFIGURATIONS

Table 39. 225-Ball Metric MBGA Pin Assignments

PBGA

Pin Number Pin Name

PBGA

Pin Number Pin Name

PBGA

Pin Number Pin Name

PBGA

Pin Number

Pin Name

NC

BMSTR

BMS

A01

A02

A03

A04

A05

A06

A07

A08

A09

A10

A11

A12

A13

A14

A15

TRST

TDI

RPBA

MOSI

FS0

SCLK1

D2B

B01

B02

B03

B04

B05

B06

B07

B08

B09

B10

B11

B12

B13

B14

B15

TMS

EMU

GND

SPICLK

D0B

D1A

D2A

FS2

FS3

L0DAT6

L1DAT7

L1DAT3

L1DAT1

DATA45

DATA47

C01

C02

C03

C04

C05

C06

C07

C08

C09

C10

C11

C12

C13

C14

C15

TDO

TCK

FLAG11

MISO

SCLK0

D1B

D01

D02

D03

D04

D05

D06

D07

D08

D09

D10

D11

D12

D13

D14

D15

SPIDS

EBOOT

LBOOT

SCLK2

D3B

L0DAT4

L0ACK

L0DAT2

L1DAT6

L1CLK

L1DAT2

NC

FS1

V_DDINT

D3A

L0DAT7

L0CLK

L0DAT1

L1DAT4

L1ACK

L1DAT0

RSTOUT¹

SCLK3

L0DAT5

L0DAT3

L1DAT5

DATA42

DATA46

DATA44

FLAG10

RESET

FLAG8

D0A

V_DDEXT

V_DDINT

V_DDEXT

V_DDINT

V_DDEXT

V_DDINT

V_DDEXT

L0DAT0

DATA39

DATA43

DATA41

E01

E02

E03

E04

E05

E06

E07

E08

E09

E10

E11

E12

E13

E14

E15

FLAG5

FLAG7

FLAG9

FLAG6

V_DDINT

GND

V_DDINT

DATA37

DATA40

DATA38

DATA36

F01

F02

F03

F04

F05

F06

F07

F08

F09

F10

F11

F12

F13

F14

F15

FLAG1

FLAG2

FLAG4

FLAG3

V_DDEXT

GND

V_DDEXT

DATA34

DATA35

DATA33

DATA32

G01

G02

G03

G04

G05

G06

G07

G08

G09

G10

G11

G12

G13

G14

G15

FLAG0

IRQ0

V_DDINT

IRQ1

V_DDINT

GND

V_DDINT

DATA29

DATA28

DATA30

DATA31

H01

H02

H03

H04

H05

H06

H07

H08

H09

H10

H11

H12

H13

H14

H15

IRQ2

ID1

ID2

J01

J02

J03

J04

J05

J06

J07

J08

J09

J10

J11

TIMEXP

ADDR22

ADDR20

ADDR23

V_DDINT

GND

K01

K02

K03

K04

K05

K06

K07

K08

K09

K10

K11

ADDR19

ADDR17

ADDR21

ADDR2

V_DDEXT

V_DDINT

V_DDEXT

V_DDINT

V_DDEXT

L01

L02

L03

L04

L05

L06

L07

L08

L09

L10

L11

ADDR16

ADDR12

ADDR18

ADDR6

ADDR0

MS1

BR6

V_DDEXT

WR

M01

M02

M03

M04

M05

M06

M07

M08

M09

M10

ID0

V_DDEXT

GND

V_DDEXT

GND

V_DDINT

V_DDEXT

SDA10

RAS

ACK

DATA17

DMAG2

M11

M12

M13

M14

DATA26

DATA24

DATA25

DATA27

J12

J13

J14

J15

DATA22

DATA19

DATA21

DATA23

K12

K13

K14

K15

CAS

DATA20

L12

L13

DATA16

DATA18

L14

L15

DMAG1

M15

REV. A

–53–

ADSP-21161N

Table 39. 225-Ball Metric MBGA Pin Assignments (continued)

PBGA

Pin Name

Pin Number Pin Name

Pin Number

ADDR14

ADDR15

N01

N02

ADDR13

P01

NC

ADDR11

R01

R02

ADDR9

ADDR8

ADDR4

MS2

P02

P03

P04

P05

ADDR10

ADDR5

N03

N04

ADDR7

ADDR3

MS3

R03

R04

R05

ADDR1

MS0

BR5

N05

N06

N07

N08

N09

N10

N11

SBTS

BR4

BR1

SDCLK1

SDCLK0

REDY

CLKIN

DQM

P06

P07

P08

P09

P10

P11

P12

P13

P14

P15

PA

BR3

RD

CLKOUT R09

HBR

R06

R07

R08

BR2

BRST

SDCKE

CS

CLK_CFG1 N12

CLK_CFG0 N13

R10

R11

R12

R13

R14

R15

HBG

CLKDBL

XTAL

SDWE

NC

AVDD

DMAR1

N14

N15

AGND

DMAR2

¹RSTOUT exists only for silicon revisions 1.2 and greater. Leave this pin unconnected for silicon revisions 0.3, 1.0, and 1.1.

14

12

10

8

6

4

2

15

13

11

9

7

5

3

1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

KEY:

*

GND

VDDINT

VDDEXT

AVDD

AGND

SIGNAL

*

USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE THERMAL

PATHWAYS TO YOUR PRINTED CIRCUIT BOARD GROUND PLANE

Figure 44. 225-Ball Metric MBGA Pin Assignments (Bottom View, Summary)

–54–

REV. A

ADSP-21161N

OUTLINE DIMENSIONS

The ADSP-21161N comes in a 17 mm × 17 mm, 225-ball MBGA package with 15 rows of balls.

225-Ball Mini-BGA (CA-225)

17.00

BSC

15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

A

B

C

D

E

F

G

H

J

A1 BALL

INDICATOR

14.00

BSC

SQ

17.00

BSC

K

L

M

N

P

R

1.00

BSC

TOP VIEW

1.00 BSC (BALL PITCH)

BOTTOM VIEW

DETAIL A

1.85 MAX

(SEE NOTE 1)

1.31 MAX

(SEE NOTE 1)

SEATING

PLANE

0.30 MIN

0.20 MAX

0.70

0.60

0.50

(BALL DIAMETER)

DETAIL A

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS AND COMPLY WITH JEDEC STANDARD MO-192-AAF2, EXCEPT FOR HEIGHT

AND THICKNESS DIMENSIONS NOTED.

2. ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.25 OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES.

3. ACTUAL POSITION OF EACH BALL IS WITHIN 0.10 OF ITS IDEAL POSITION RELATIVE TO THE BALL GRID.

ORDERING GUIDE

Case Temperature

Range

On-Chip

SRAM

Part Number¹

Instruction Rate

Operating Voltage

ADSP-21161NKCA-100

ADSP-21161NCCA-100

0°C to +85°C

–40°C to +105°C

100 MHz

1 M bit

1.8 int/3.3 ext V

¹These parts are packaged in a 225-ball Mini-Ball Grid Array (MBGA).

REV. A

–55–

ADSP-21161N

Revision History

Location

Page

5/03—Changed from Rev. 0 to Rev. A

Changes to:

KEY FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

SIMD Computational Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Off-Chip Memory and Peripherals Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Host Processor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Phase-Locked Loop and Crystal Double Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Design-for-Emulation Circuit Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Table 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Table 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Table 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Table 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Figure 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Table 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Memory Read – Bus Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Memory Write – Bus Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Synchronous Read/Write – Bus Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Host BusRequest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Asynchronous Read/Write – Host to ADSP-21161N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Three-State Timing – Bus Master, Bus Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Figure 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

–56–

REV. A

ADSP-21161N

Location

Page

Changes to:

Table 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Changes to formatting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Global

REV. A

–57–

–58–

–59–

–60–


型号：	ADSP-21161NKCAZ-100
厂家：	ADI
描述：	IC 48-BIT, 25 MHz, OTHER DSP, PBGA225, 17 X 17 MM, MBGA-225, Digital Signal Processor 时钟外围集成电路
文件：	总60页 (文件大小：1019K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-21161NKCAZ-100 [ADI]

相关型号：

ADSP-21161NKCAZ100

ADSP-21161NKCAZ100

ADSP-21161NYCAZ110

ADSP-21261

ADSP-21261SKBC-150

ADSP-21261SKBCZ-X

ADSP-21261SKBCZ150

ADSP-21261SKSTZ-X

ADSP-21261SKSTZ150

ADSP-21262

ADSP-21262SBBC-150

ADSP-21262SBBCZ150