ADSP-21364YSWZ-2AA [ADI]
High Precision 32-Bit Floating-Point SHARC Processor for Professional Audio;型号: | ADSP-21364YSWZ-2AA |
厂家: | ADI |
描述: | High Precision 32-Bit Floating-Point SHARC Processor for Professional Audio 时钟 外围集成电路 |
文件: | 总60页 (文件大小:1341K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SHARC Processors
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
SUMMARY
DEDICATED AUDIO COMPONENTS
High performance 32-bit/40-bit floating point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
S/PDIF-compatible digital audio receiver/transmitter
8 channels of asynchronous sample rate converters (SRC)
16 PWM outputs configured as four groups of four outputs
ROM-based security features include:
On-chip memory—3M bits of on-chip SRAM
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
access under program control to sensitive code
PLL has a wide variety of software and hardware multi-
plier/divider ratios
Code compatible with all other members of the SHARC family
The ADSP-2136x processors are available with up to 333 MHz
core instruction rate with unique audiocentric peripherals
such as the digital applications interface, S/PDIF trans-
ceiver, DTCP (digital transmission content protection
protocol), serial ports, precision clock generators, and
more. For complete ordering information, see Ordering
Guide on Page 56.
Available in 136-ball CSP_BGA and 144-lead LQFP_EP
packages
Internal Memory
SIMD Core
Block 0
RAM/ROM
Block 1
RAM/ROM
Block 2
RAM
Block 3
RAM
Instruction
Cache
5 stage
Sequencer
B2D
64-BIT
B0D
64-BIT
B3D
64-BIT
B1D
64-BIT
S
DAG1/2
PEx
Timer
PEy
DMD 64-BIT
PMD 64-BIT
DMD 64-BIT
PMD 64-BIT
Core Bus
Cross Bar
Internal Memory I/F
FLAGx/IRQx/
TMREXP
JTAG
PERIPHERAL BUS
32-BIT
IOD 32-BIT
MTM/
DTCP
IOD BUS
PERIPHERAL BUS
CORE TIMER ASRC S/PDIF PCG
FLAGS Tx/Rx
Core
Flags
PDAP/ SPORT
IDP7-0
PWM
3-0
SPI B
PP
SPI
2
-
0
3-0
A-B
5
-
0
DAI Routing/Pins
PP Pin MUX
DAI Peripherals
Peripherals
Figure 1. Functional Block Diagram
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. J Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
Technical Support
©2013 Analog Devices, Inc. All rights reserved.
www.analog.com
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
TABLE OF CONTENTS
Summary ............................................................... 1
Dedicated Audio Components .................................... 1
General Description ................................................. 3
SHARC Family Core Architecture ............................ 4
Family Peripheral Architecture ................................ 6
I/O Processor Features ........................................... 8
System Design ...................................................... 8
Development Tools ............................................... 9
Additional Information ........................................ 10
Related Signal Chains .......................................... 10
Pin Function Descriptions ....................................... 11
Specifications ........................................................ 14
Operating Conditions .......................................... 14
Electrical Characteristics ....................................... 15
Package Information ........................................... 16
ESD Caution ...................................................... 16
Maximum Power Dissipation ................................. 16
Absolute Maximum Ratings ................................... 16
Timing Specifications ........................................... 16
Output Drive Currents ......................................... 46
Test Conditions .................................................. 46
Capacitive Loading .............................................. 46
Thermal Characteristics ........................................ 47
144-Lead LQFP_EP Pin Configurations ....................... 48
136-Ball BGA Pin Configurations ............................... 50
Package Dimensions ............................................... 53
Surface-Mount Design .......................................... 54
Automotive Products .............................................. 55
Ordering Guide ..................................................... 56
REVISION HISTORY
7/13—Revision I to Revision J
Updated Development Tools .......................................9
Added Nominal Value column in Operating Conditions .. 14
Changed Max values in Table 30 in Pulse-Width Modulation
Generators ............................................................ 35
Updated Ordering Guide .......................................... 56
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GENERAL DESCRIPTION
The ADSP-2136x SHARC® processor is a member of the SIMD
SHARC family of DSPs that feature Analog Devices, Inc., Super
Harvard Architecture. The processor is source code-compatible
with the ADSP-2126x and ADSP-2116x DSPs, as well as with
first generation ADSP-2106x SHARC processors in SISD
(single-instruction, single-data) mode. The ADSP-2136x are
32-/40-bit floating-point processors optimized for high
performance automotive audio applications. They contain a
large on-chip SRAM and ROM, multiple internal buses to elim-
inate I/O bottlenecks, and an innovative digital audio interface
(DAI).
Table 1 shows performance benchmarks for these devices.
Table 2 shows the features of the individual product offerings.
Table 1. Benchmarks (at 333 MHz)
Speed
Benchmark Algorithm
(at 333 MHz)
1024 Point Complex FFT (Radix 4, with reversal) 27.9 μs
FIR Filter (per tap)1
IIR Filter (per biquad)1
1.5 ns
6.0 ns
Matrix Multiply (pipelined)
[3×3] × [3×1]
[4×4] × [4×1]
As shown in the functional block diagram on Page 1, the
ADSP-2136x uses two computational units to deliver a signifi-
cant performance increase over the previous SHARC processors
on a range of signal processing algorithms. With its SIMD com-
putational hardware, the ADSP-2136x can perform two
GFLOPS running at 333 MHz.
13.5 ns
23.9 ns
Divide (y/x)
10.5 ns
16.3 ns
Inverse Square Root
1 Assumes two files in multichannel SIMD mode.
Table 2. ADSP-2136x Family Features
Feature
ADSP-21362
3M bit
4M bit
No
ADSP-21363
3M bit
4M bit
No
ADSP-21364
3M bit
4M bit
No
ADSP-21365
3M bit
4M bit
Yes
ADSP-21366
3M bit
4M bit
Yes
RAM
ROM
Audio Decoders in ROM1
Pulse-Width Modulation
S/PDIF
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
DTCP2
Yes
No
No
Yes
No
SRC SNR Performance
–128 dB
No SRC
–140 dB
–128 dB
–128 dB
1 Audio decoding algorithms include PCM, Dolby Digital EX, Dolby Pro Logic IIx, DTS 96/24, Neo:6, DTS ES, MPEG-2 AAC, MP3, and functions like bass management, delay,
speaker equalization, graphic equalization, and more. Decoder/post-processor algorithm combination support varies depending upon the chip version and the system
configurations. Please visit www.analog.com for complete information.
2 The ADSP-21362 and ADSP-21365 processors provide the Digital Transmission Content Protection protocol, a proprietary security protocol. Contact your Analog Devices
sales office for more information.
The diagram on Page 1 shows the two clock domains that make
up the ADSP-2136x processors. The core clock domain contains
the following features:
The diagram on Page 1 also shows the following architectural
features:
• I/O processor that handles 32-bit DMA for the peripherals
• Six full duplex serial ports
• Two processing elements, each of which comprises an
ALU, multiplier, shifter, and data register file
• Two SPI-compatible interface ports—primary on dedi-
cated pins, secondary on DAI pins
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• 8-bit or 16-bit parallel port that supports interfaces to off-
chip memory peripherals
• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core pro-
cessor cycle
• Digital audio interface that includes two precision clock
generators (PCG), an input data port with eight serial inter-
faces (IDP), an S/PDIF receiver/transmitter, 8-channel
asynchronous sample rate converter (ASRC), DTCP
cipher, six serial ports, a 20-bit parallel input data port
(PDAP), 10 interrupts, six flag outputs, six flag inputs,
three timers, and a flexible signal routing unit (SRU)
• One periodic interval timer with pinout
• On-chip SRAM (3M bit)
• On-chip mask-programmable ROM (4M bit)
• JTAG test access port for emulation and boundary scan.
The JTAG provides software debug through user break-
points, which allow flexible exception handling.
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Entering SIMD mode also has an effect on the way data is trans-
SHARC FAMILY CORE ARCHITECTURE
ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the
bandwidth between memory and the processing elements.
When using the DAGs to transfer data in SIMD mode, two data
values are transferred with each access of memory or
the register file.
The ADSP-2136x is code-compatible at the assembly level with
the ADSP-2126x, ADSP-21160, and ADSP-21161, and with the
first generation ADSP-2106x SHARC processors. The
ADSP-2136x shares architectural features with the ADSP-2126x
and ADSP-2116x SIMD SHARC processors, as shown in
Figure 2 and detailed in the following sections.
SIMD Computational Engine
The processor contains two computational processing elements
that operate as a single-instruction, multiple-data (SIMD)
engine. The processing elements are referred to as PEX and PEY
and each contains an ALU, multiplier, shifter, and register file.
PEX is always active, and PEY can be enabled by setting the
PEYEN mode bit in the MODE1 register. When this mode is
enabled, the same instruction is executed in both processing ele-
ments, but each processing element operates on different data.
This architecture is efficient at executing math intensive signal
processing algorithms.
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all opera-
tions in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing
elements. These computation units support IEEE 32-bit,
single-precision floating-point, 40-bit extended-precision
floating-point, and 32-bit fixed-point data formats.
S
JTAG
FLAG TIMER INTERRUPT CACHE
SIMD Core
PM ADDRESS 24
DMD/PMD 64
5 STAGE
PROGRAM SEQUENCER
PM DATA 48
DAG2
16x32
DAG1
16x32
PM ADDRESS 32
SYSTEM
I/F
DM ADDRESS 32
PM DATA 64
USTAT
4x32-BIT
PX
64-BIT
DM DATA 64
DATA
SWAP
RF
Rx/Fx
PEx
RF
Sx/SFx
PEy
ALU
SHIFTER
MULTIPLIER
MULTIPLIER
ALU
SHIFTER
16x40-BIT
16x40-BIT
MRB
80-BIT
MSB
80-BIT
MRF
80-BIT
MSF
80-BIT
ASTATy
STYKy
ASTATx
STYKx
Figure 2. SHARC Core Block Diagram
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processing, and are commonly used in digital filters and Fourier
transforms. The two DAGs contain sufficient registers to allow
the creation of up to 32 circular buffers (16 primary register sets,
16 secondary). The DAGs automatically handle address pointer
wraparound, reduce overhead, increase performance, and sim-
plify implementation. Circular buffers can start and end at any
memory location.
Data Register File
Each processing element contains a general-purpose data regis-
ter file. The register files transfer data between the computation
units and the data buses, and store intermediate results. These
10-port, 32-register (16 primary, 16 secondary) files, combined
with the ADSP-2136x enhanced Harvard architecture, allow
unconstrained data flow between computation units and inter-
nal memory. The registers in PEX are referred to as R0–R15 and
in PEY as S0–S15.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations for concise programming. For example, the
processor can conditionally execute a multiply, an add, and a
subtract in both processing elements while branching and fetch-
ing up to four 32-bit values from memory—all in a single
instruction.
Context Switch
Many of the processor’s registers have secondary registers that
can be activated during interrupt servicing for a fast context
switch. The data registers in the register file, the DAG registers,
and the multiplier result register all have secondary registers.
The primary registers are active at reset, while the secondary
registers are activated by control bits in a mode control register.
On-Chip Memory
The processor contains 3M bits of internal SRAM and 4M bits
of internal ROM. Each block can be configured for different
combinations of code and data storage (see Table 3). Each
memory block supports single-cycle, independent accesses by
the core processor and I/O processor. The processor’s memory
architecture, in combination with its separate on-chip buses,
allows two data transfers from the core and one from the I/O
processor, in a single cycle.
Universal Registers
The universal registers are general purpose registers. The
USTAT (4) registers allow easy bit manipulations (Set, Clear,
Toggle, Test, XOR) for all system registers (control/status) of
the core.
The data bus exchange register (PX) permits data to be passed
between the 64-bit PM data bus and the 64-bit DM data bus, or
between the 40-bit register file and the PM/DM data bus. These
registers contain hardware to handle the data width difference.
The SRAM can be configured as a maximum of 96K words of
32-bit data, 192K words of 16-bit data, 64K words of 48-bit
instructions (or 40-bit data), or combinations of different word
sizes up to 3M bits. All of the memory can be accessed as 16-bit,
32-bit, 48-bit, or 64-bit words. A 16-bit floating-point storage
format is supported that effectively doubles the amount of data
that can be stored on-chip. Conversion between the 32-bit
floating-point and 16-bit floating-point formats is performed in
a single instruction. While each memory block can store combi-
nations of code and data, accesses are most efficient when one
block stores data using the DM bus for transfers, and the other
block stores instructions and data using the PM bus for
transfers.
Timer
A core timer that can generate periodic software interrupts. The
core timer can be configured to use FLAG3 as a timer expired
signal.
Single-Cycle Fetch of Instruction and Four Operands
The processor features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see Figure 2). With the its separate program and data memory
buses and on-chip instruction cache, the processor can simulta-
neously fetch four operands (two over each data bus) and one
instruction (from the cache), all in a single cycle.
Using the DM bus and PM buses, with one bus dedicated to
each memory block, assures single-cycle execution with two
data transfers. In this case, the instruction must be available in
the cache.
Instruction Cache
On-Chip Memory Bandwidth
The processor includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full-speed execution of core looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.
The internal memory architecture allows three accesses at the
same time to any of the four blocks, assuming no block con-
flicts. The total bandwidth is gained with DMD and PMD buses
(2 × 64-bits, core CLK) and the IOD bus (32-bit, PCLK).
ROM-Based Security
The processor has a ROM security feature that provides hard-
ware support for securing user software code by preventing
unauthorized reading from the internal code. When using this
feature, the processor does not boot-load any external code, exe-
cuting exclusively from internal ROM. Additionally, the
processor is not freely accessible via the JTAG port. Instead, a
unique 64-bit key, which must be scanned in through the JTAG
Data Address Generators with Zero-Overhead Hardware
Circular Buffer Support
The processor’s two data address generators (DAGs) are used
for indirect addressing and implementing circular data buffers
in hardware. Circular buffers allow efficient programming of
delay lines and other data structures required in digital signal
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Table 3. ADSP-2136x Internal Memory Space
IOP Registers 0x0000 0000–0003 FFFF
Extended Precision Normal or
Long Word (64 Bits)
Instruction Word (48 Bits)
Normal Word (32 Bits)
Short Word (16 Bits)
Block 0 ROM
Block 0 ROM
Block 0 ROM
Block 0 ROM
0x0004 0000–0x0004 7FFF
0x0008 0000–0x0008 AAA9
0x0008 0000–0x0008 FFFF
0x0010 0000–0x0011 FFFF
Reserved
Reserved
Reserved
0x0004 8000–0x0004 BFFF
0x0009 0000–0x0009 7FFF
0x0012 0000–0x0012 FFFF
Block 0 SRAM
Block 0 SRAM
Block 0 SRAM
Block 0 SRAM
0x0004 C000–0x0004 FFFF
0x0009 0000–0x0009 5554
0x0009 8000–0x0009 FFFF
0x0013 0000–0x0013 FFFF
Block 1 ROM
Block 1 ROM
Block 1 ROM
Block 1 ROM
0x0005 0000–0x0005 7FFF
0x000A 0000–0x000A AAA9
0x000A 0000–0x000A FFFF
0x0014 0000–0x0015 FFFF
Reserved
Reserved
Reserved
0x0005 8000–0x0005 BFFF
0x000B 0000–0x000B 7FFF
0x0016 0000–0x0016 FFFF
Block 1 SRAM
Block 1 SRAM
Block 1 SRAM
Block 1 SRAM
0x0005 C000–0x0005 FFFF
0x000B 0000–0x000B 5554
0x000B 8000–0x000B FFFF
0x0017 0000–0x0017 FFFF
Block 2 SRAM
Block 2 SRAM
Block 2 SRAM
Block 2 SRAM
0x0006 0000–0x0006 1FFF
0x000C 0000–0x000C 2AA9
0x000C 0000–0x000C 3FFF
0x0018 0000–0x0018 7FFF
Reserved
Reserved
Reserved
0x0006 2000–0x0006 FFFF
0x000C 4000–0x000D FFFF
0x0018 8000–0x001B FFFF
Block 3 SRAM
Block 3 SRAM
Block 3 SRAM
Block 3 SRAM
0x0007 0000–0x0007 1FFF
0x000E 0000–0x000E 2AA9
0x000E 0000–0x000E 3FFF
0x001C 0000–0x001C 7FFF
Reserved
Reserved
Reserved
0x0007 2000–0x0007 FFFF
0x000E 4000–0x000F FFFF
0x001C 8000–0x001F FFFF
Reserved
0x0020 0000–0xFFFF FFFF
or test access port, is assigned to each customer. The device
ignores a wrong key. Emulation features and external boot
modes are only available after the correct key is scanned.
Serial Peripheral (Compatible) Interface
The processors contain two serial peripheral interface ports
(SPIs). The SPI is an industry-standard synchronous serial link,
enabling the processor’s SPI-compatible port to communicate
with other SPI-compatible devices. The SPI consists of two data
pins, one device select pin, and one clock pin. It is a full-duplex
synchronous serial interface, supporting both master and slave
modes and can operate at a maximum baud rate of fPCLK/4.
FAMILY PERIPHERAL ARCHITECTURE
The ADSP-2136x family contains a rich set of peripherals that
support a wide variety of applications, including high quality
audio, medical imaging, communications, military, test equip-
ment, 3D graphics, speech recognition, monitor control,
imaging, and other applications.
The SPI port can operate in a multimaster environment by
interfacing with up to four other SPI-compatible devices, either
acting as a master or slave device. The ADSP-2136x SPI-
compatible peripheral implementation also features program-
mable baud rate, clock phase, and polarities. The SPI-
compatible port uses open drain drivers to support a multimas-
ter configuration and to avoid data contention.
Parallel Port
The parallel port provides interfaces to SRAM and peripheral
devices. The multiplexed address and data pins (AD15–0) can
access 8-bit devices with up to 24 bits of address, or 16-bit
devices with up to 16 bits of address. In either mode, 8-bit or
16-bit, the maximum data transfer rate is fPCLK/4.
Pulse-Width Modulation
DMA transfers are used to move data to and from internal
memory. Access to the core is also facilitated through the paral-
lel port register read/write functions. The RD, WR, and ALE
(address latch enable) pins are the control pins for the
parallel port.
The entire PWM module has four groups of four PWM outputs
each. Therefore, this module generates 16 PWM outputs in
total. Each PWM group produces two pairs of PWM signals on
the four PWM outputs.
The PWM module is a flexible, programmable, PWM waveform
generator that can be programmed to generate the required
switching patterns for various applications related to motor and
engine control or audio power control. The PWM generator can
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generate either center-aligned or edge-aligned PWM wave-
Serial ports operate in four modes:
• Standard DSP serial mode
• Multichannel (TDM) mode
• I2S mode
forms. In addition, it can generate complementary signals on
two outputs in paired mode or independent signals in non-
paired mode (applicable to a single group of four PWM
waveforms).
The PWM generator is capable of operating in two distinct
modes while generating center-aligned PWM waveforms: single
update mode or double update mode. In single update mode,
the duty cycle values are programmable only once per PWM
period. This results in PWM patterns that are symmetrical
about the midpoint of the PWM period. In double update
mode, a second updating of the PWM registers is implemented
at the midpoint of the PWM period. In this mode, it is possible
to produce asymmetrical PWM patterns that produce lower
harmonic distortion in 3-phase PWM inverters.
• Left-justified sample pair mode
S/PDIF-Compatible Digital Audio Receiver/Transmitter
The S/PDIF transmitter has no separate DMA channels. It
receives audio data in serial format and converts it into a
biphase encoded signal. The serial data input to the transmitter
can be formatted as left-justified, I2S, or right-justified with
word widths of 16, 18, 20, or 24 bits.
The serial data, clock, and frame sync inputs to the S/PDIF
transmitter are routed through the signal routing unit (SRU).
They can come from a variety of sources such as the SPORTs,
external pins, the precision clock generators (PCGs), or the
sample rate converters (SRC) and are controlled by the SRU
control registers.
Digital Audio Interface (DAI)
The digital audio interface (DAI) provides the ability to connect
various peripherals to any of the DSP’s DAI pins (DAI_P20–1).
Programs make these connections using the signal routing unit
(SRU, shown in Figure 1).
Digital Transmission Content Protection (DTCP)
The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be intercon-
nected under software control. This allows easy use of the
DAI-associated peripherals for a wider variety of applications by
using a larger set of algorithms than is possible with nonconfig-
urable signal paths.
The DTCP specification defines a cryptographic protocol for
protecting audio entertainment content from illegal copying,
intercepting, and tampering as it traverses high performance
digital buses, such as the IEEE 1394 standard. Only legitimate
entertainment content delivered to a source device via another
approved copy protection system (such as the DVD content
scrambling system) is protected by this copy protection system.
This feature is available on the ADSP-21362 and
The DAI includes six serial ports, an S/PDIF receiver/transmit-
ter, a DTCP cipher, a precision clock generator (PCG), eight
channels of asynchronous sample rate converters, an input data
port (IDP), an SPI port, six flag outputs and six flag inputs, and
three timers. The IDP provides an additional input path to the
ADSP-2136x core, configurable as either eight channels of I2S
serial data or as seven channels plus a single 20-bit wide syn-
chronous parallel data acquisition port. Each data channel has
its own DMA channel that is independent from the processor’s
serial ports.
ADSP-21365 processors only. Licensing through DTLA is
required for these products. Visit www.dtcp.com for more
information.
Memory-to-Memory (MTM)
If the DTCP module is not used, the memory-to-memory DMA
module allows internal memory copies for a standard DMA.
Synchronous/Asynchronous Sample Rate Converter (SRC)
Serial Ports
The sample rate converter (SRC) contains four SRC blocks and
is the same core as that used in the AD1896 192 kHz stereo
asynchronous sample rate converter and provides up to 140 dB
SNR. The SRC block is used to perform synchronous or
asynchronous sample rate conversion across independent stereo
channels, without using internal processor resources. The four
SRC blocks can also be configured to operate together to con-
vert multichannel audio data without phase mismatches.
Finally, the SRC is used to clean up audio data from jittery clock
sources such as the S/PDIF receiver.
The processor features six synchronous serial ports that provide
an inexpensive interface to a wide variety of digital and mixed-
signal peripheral devices such as Analog Devices’ AD183x fam-
ily of audio codecs, ADCs, and DACs. The serial ports are made
up of two data lines, a clock, and a frame sync and they can
operate at maximum fPCLK/4. The data lines can be pro-
grammed to either transmit or receive and each data line has a
dedicated DMA channel.
Serial ports are enabled via 12 programmable and simultaneous
receive or transmit pins that support up to 24 transmit or 24
receive channels of audio data when all six SPORTs are enabled,
or six full duplex TDM streams of 128 channels per frame.
The S/PDIF and SRC are not available on the ADSP-21363
models.
Input Data Port (IDP)
Serial port data can be automatically transferred to and from
on-chip memory via dedicated DMA channels. Each of the
serial ports can work in conjunction with another serial port to
provide TDM support. One SPORT provides two transmit sig-
nals while the other SPORT provides the two receive signals.
The frame sync and clock are shared.
The IDP provides up to eight serial input channels—each with
its own clock, frame sync, and data inputs. The eight channels
are automatically multiplexed into a single 32-bit by eight-deep
FIFO. Data is always formatted as a 64-bit frame and divided
into two 32-bit words. The serial protocol is designed to receive
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audio channels in I2S, left-justified sample pair, or right-justi-
fied mode. One frame sync cycle indicates one 64-bit left/right
pair, but data is sent to the FIFO as 32-bit words (that is, one-
half of a frame at a time). The processor supports 24- and 32-bit
I2S, 24- and 32-bit left-justified, and 24-, 20-, 18- and 16-bit
right-justified formats.
SYSTEM DESIGN
The following sections provide an introduction to system design
options and power supply issues.
Program Booting
The internal memory of the processor boots at system power-up
from an 8-bit EPROM via the parallel port, an SPI master, an
SPI slave, or an internal boot. Booting is determined by the boot
configuration (BOOT_CFG1–0) pins in Table 5. Selection of the
boot source is controlled via the SPI as either a master or slave
device, or it can immediately begin executing from ROM.
Precision Clock Generator (PCG)
The precision clock generators (PCG) consist of two units, each
of which generates a pair of signals (clock and frame sync)
derived from a clock input signal. The units, A and B, are identi-
cal in functionality and operate independently of each other.
The two signals generated by each unit are normally used as a
serial bit clock/frame sync pair.
Table 5. Boot Mode Selection
BOOT_CFG1–0
Booting Mode
Peripheral Timers
00
01
10
11
SPI Slave Boot
The following three general-purpose timers can generate peri-
odic interrupts and be independently set to operate in one of
three modes:
SPI Master Boot
Parallel Port Boot via EPROM
No booting occurs. Processor executes
from internal ROM after reset.
• Pulse waveform generation mode
• Pulse width count/capture mode
• External event watchdog mode
Phase-Locked Loop
Each general-purpose timer has one bidirectional pin and four
registers that implement its mode of operation: a 6-bit configu-
ration register, a 32-bit count register, a 32-bit period register,
and a 32-bit pulse width register. A single control and status
register enables or disables all three general-purpose timers
independently.
The processors use an on-chip phase-locked loop (PLL) to gen-
erate the internal clock for the core. On power-up, the
CLK_CFG1–0 pins are used to select ratios of 32:1, 16:1, and
6:1. After booting, numerous other ratios can be selected via
software control.
The ratios are made up of software configurable numerator val-
ues from 1 to 64 and software configurable divisor values of 1, 2,
4, and 8.
I/O PROCESSOR FEATURES
The processor’s I/O provides many channels of DMA and con-
trols the extensive set of peripherals described in the previous
sections.
Power Supplies
The processor has a separate power supply connection for the
internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS
)
DMA Controller
power supplies. The internal and analog supplies must meet the
1.2 V requirement for K, B, and Y grade models, and the 1.0 V
requirement for Y models. (For information on the temperature
ranges offered for this product, see Operating Conditions on
Page 14, Package Information on Page 16, and Ordering Guide
on Page 56.) The external supply must meet the 3.3 V require-
ment. All external supply pins must be connected to the same
power supply.
The processor’s on-chip DMA controllers allow data transfers
without processor intervention. The DMA controller operates
independently and invisibly to the processor core, allowing
DMA operations to occur while the core is simultaneously exe-
cuting its program instructions. DMA transfers can occur
between the processor’s internal memory and its serial ports, the
SPI-compatible (serial peripheral interface) ports, the IDP
(input data port), the parallel data acquisition port (PDAP), or
the parallel port (PP). See Table 4.
Note that the analog supply pin (AVDD) powers the processor’s
internal clock generator PLL. To produce a stable clock, it is rec-
ommended that PCB designs use an external filter circuit for the
Table 4. DMA Channels
A
VDD pin. Place the filter components as close as possible to the
Peripheral
SPORTs
ADSP-2136x
AVDD/AVSS pins. For an example circuit, see Figure 3. (A
recommended ferrite chip is the muRata BLM18AG102SN1D.)
To reduce noise coupling, the PCB should use a parallel pair of
power and ground planes for VDDINT and GND. Use wide traces
12
8
IDP/PDAP
SPI
2
to connect the bypass capacitors to the analog power (AVDD
and ground (AVSS) pins. Note that the AVDD and AVSS pins
)
MTM/DTCP
Parallel Port
Total DMA Channels
2
1
specified in Figure 3 are inputs to the processor and not the ana-
log ground plane on the board—the AVSS pin should connect
directly to digital ground (GND) at the chip.
25
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features. Also available are various EZ-Extenders®, which are
ADSP-213xx
daughter cards delivering additional specialized functionality,
100nF
10nF
1nF
A
V
VDD
including audio and video processing. For more information
visit www.analog.com and search on “ezkit” or “ezextender”.
DDINT
HIGH-Z FERRITE
BEAD CHIP
EZ-KIT Lite Evaluation Kits
A
VSS
For a cost-effective way to learn more about developing with
Analog Devices processors, Analog Devices offer a range of EZ-
KIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT
Lite evaluation board, directions for downloading an evaluation
version of the available IDE(s), a USB cable, and a power supply.
The USB controller on the EZ-KIT Lite board connects to the
USB port of the user’s PC, enabling the chosen IDE evaluation
suite to emulate the on-board processor in-circuit. This permits
the customer to download, execute, and debug programs for the
EZ-KIT Lite system. It also supports in-circuit programming of
the on-board Flash device to store user-specific boot code,
enabling standalone operation. With the full version of Cross-
Core Embedded Studio or VisualDSP++ installed (sold
separately), engineers can develop software for supported EZ-
KITs or any custom system utilizing supported Analog Devices
processors.
LOCATE ALL COMPONENTS
CLOSE TO A AND A PINS
VDD
VSS
Figure 3. Analog Power (AVDD) Filter Circuit
Target Board JTAG Emulator Connector
Analog Devices’ DSP Tools product line of JTAG emulators
uses the IEEE 1149.1 JTAG test access port of the processor to
monitor and control the target board processor during emula-
tion. Analog Devices’ DSP Tools product line of JTAG
emulators provides emulation at full processor speed, allowing
inspection and modification of memory, registers, and proces-
sor stacks. The processor’s JTAG interface ensures that the
emulator does not affect target system loading or timing.
For complete information on Analog Devices’ SHARC DSP
Tools product line of JTAG emulator operation, refer to the
appropriate emulator user’s guide.
Software Add-Ins for CrossCore Embedded Studio
Analog Devices offers software add-ins which seamlessly inte-
grate with CrossCore Embedded Studio to extend its capabilities
and reduce development time. Add-ins include board support
packages for evaluation hardware, various middleware pack-
ages, and algorithmic modules. Documentation, help,
configuration dialogs, and coding examples present in these
add-ins are viewable through the CrossCore Embedded Studio
IDE once the add-in is installed.
DEVELOPMENT TOOLS
Analog Devices supports its processors with a complete line of
software and hardware development tools, including integrated
development environments (which include CrossCore® Embed-
ded Studio and/or VisualDSP++®), evaluation products,
emulators, and a wide variety of software add-ins.
Integrated Development Environments (IDEs)
Board Support Packages for Evaluation Hardware
For C/C++ software writing and editing, code generation, and
debug support, Analog Devices offers two IDEs.
Software support for the EZ-KIT Lite evaluation boards and EZ-
Extender daughter cards is provided by software add-ins called
Board Support Packages (BSPs). The BSPs contain the required
drivers, pertinent release notes, and select example code for the
given evaluation hardware. A download link for a specific BSP is
located on the web page for the associated EZ-KIT or EZ-
Extender product. The link is found in the Product Download
area of the product web page.
The newest IDE, CrossCore Embedded Studio, is based on the
EclipseTM framework. Supporting most Analog Devices proces-
sor families, it is the IDE of choice for future processors,
including multicore devices. CrossCore Embedded Studio
seamlessly integrates available software add-ins to support real
time operating systems, file systems, TCP/IP stacks, USB stacks,
algorithmic software modules, and evaluation hardware board
support packages. For more information visit
Middleware Packages
www.analog.com/cces.
Analog Devices separately offers middleware add-ins such as
real time operating systems, file systems, USB stacks, and
TCP/IP stacks. For more information see the following web
pages:
The other Analog Devices IDE, VisualDSP++, supports proces-
sor families introduced prior to the release of CrossCore
Embedded Studio. This IDE includes the Analog Devices VDK
real time operating system and an open source TCP/IP stack.
For more information visit www.analog.com/visualdsp. Note
that VisualDSP++ will not support future Analog Devices
processors.
• www.analog.com/ucos3
• www.analog.com/ucfs
• www.analog.com/ucusbd
• www.analog.com/lwip
EZ-KIT Lite Evaluation Board
For processor evaluation, Analog Devices provides wide range
of EZ-KIT Lite® evaluation boards. Including the processor and
key peripherals, the evaluation board also supports on-chip
emulation capabilities and other evaluation and development
Algorithmic Modules
To speed development, Analog Devices offers add-ins that per-
form popular audio and video processing algorithms. These are
available for use with both CrossCore Embedded Studio and
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VisualDSP++. For more information visit www.analog.com and
search on “Blackfin software modules” or “SHARC software
modules”.
Designing an Emulator-Compatible DSP Board (Target)
For embedded system test and debug, Analog Devices provides
a family of emulators. On each JTAG DSP, Analog Devices sup-
plies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit
emulation is facilitated by use of this JTAG interface. The emu-
lator accesses the processor’s internal features via the
processor’s TAP, allowing the developer to load code, set break-
points, and view variables, memory, and registers. The
processor must be halted to send data and commands, but once
an operation is completed by the emulator, the DSP system is set
to run at full speed with no impact on system timing. The emu-
lators require the target board to include a header that supports
connection of the DSP’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, signal buffering, signal ter-
mination, and emulator pod logic, see the Engineer-to-Engineer
Note “Analog Devices JTAG Emulation Technical Reference”
(EE-68) on the Analog Devices website (www.analog.com)—use
site search on “EE-68.” This document is updated regularly to
keep pace with improvements to emulator support.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the
processor’s architecture and functionality. For detailed informa-
tion on the ADSP-2136x family core architecture and
instruction set, refer to the ADSP-2136x SHARC Processor
Hardware Reference and the ADSP-2136x SHARC Processor
Programming Reference.
RELATED SIGNAL CHAINS
A signal chain is a series of signal-conditioning electronic com-
ponents that receive input (data acquired from sampling either
real-time phenomena or from stored data) in tandem, with the
output of one portion of the chain supplying input to the next.
Signal chains are often used in signal processing applications to
gather and process data or to apply system controls based on
analysis of real-time phenomena. For more information about
this term and related topics, see the “signal chain” entry in the
Glossary of EE Terms on the Analog Devices website.
Analog Devices eases signal processing system development by
providing signal processing components that are designed to
work together well. A tool for viewing relationships between
specific applications and related components is available on the
www.analog.com website.
TM
The Circuits from the Lab site
(http://www.analog.com/signalchains) provides:
• Graphical circuit block diagram presentation of signal
chains for a variety of circuit types and applications
• Drill down links for components in each chain to selection
guides and application information
• Reference designs applying best practice design techniques
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PIN FUNCTION DESCRIPTIONS
The processor’s pin definitions are listed below. Inputs identi-
fied as synchronous (S) must meet timing requirements with
respect to CLKIN (or with respect to TCK for TMS and TDI).
Inputs identified as asynchronous (A) can be asserted asynchro-
nously to CLKIN (or to TCK for TRST). Tie or pull unused
inputs to VDDEXT or GND, except for the following:
DAI_Px, SPICLK, MISO, MOSI, EMU, TMS, TRST, TDI, and
AD15–0. Note: These pins have pull-up resistors.
Table 6. Pin Descriptions
State During and
Pin
Type
After Reset
Function
AD15–0
I/O/T
(pu)
Three-state with
pull-up enabled
Parallel Port Address/Data. The ADSP-2136x parallel port and its corresponding DMA
unit output addresses and data for peripherals on these multiplexed pins. The multiplex
state is determined by the ALE pin. The parallel port can operate in either 8-bit or 16-bit
mode. Each AD pin has a 22.5 kΩ internal pull-up resistor. For details about the AD pin
operation, refer to the ADSP-2136x SHARC Processor Hardware Reference.
For 8-bit mode: ALE is automatically asserted whenever a change occurs in the upper 16
external address bits, ADDR23–8; ALE is used in conjunction with an external latch to
retain the values of the ADDR23–8.
For detailed information on I/O operations and pin multiplexing, refer to the ADSP-2136x
SHARC Processor Hardware Reference.
RD
O
(pu)
Three-state, driven Parallel Port Read Enable. RD is asserted low whenever the processor reads 8-bit or 16-
high1
bit data from an external memory device. When AD15–0 are flags, this pin remains
deasserted. RD has a 22.5 kΩ internal pull-up resistor.
WR
ALE
O
(pu)
Three-state, driven Parallel Port Write Enable. WR is asserted low whenever the processor writes 8-bit or
high1
16-bit data to an external memory device. When AD15–0 are flags, this pin remains
deasserted. WR has a 22.5 kΩ internal pull-up resistor.
O
(pd)
Three-state, driven Parallel Port Address Latch Enable. ALE is asserted whenever the processor drives a
low1
new address on the parallel port address pins. On reset, ALE is active high. However, it
can be reconfigured using software to be active low. When AD15–0 are flags, this pin
remains deasserted. ALE has a 20 kΩ internal pull-down resistor.
FLAG[0]/IRQ0/SPI I/O
FLG[0]
FLAG[0] INPUT
FLAG[1] INPUT
FLAG[2] INPUT
FLAG[3] INPUT
FLAG0/Interrupt Request0/SPI0 Slave Select.
FLAG1/Interrupt Request1/SPI1 Slave Select.
FLAG2/Interrupt Request 2/SPI2 Slave Select.
FLAG3/Timer Expired/SPI3 Slave Select.
FLAG[1]/IRQ1/SPI I/O
FLG[1]
FLAG[2]/IRQ2/SPI I/O
FLG[2]
FLAG[3]/TMREXP/ I/O
SPIFLG[3]
DAI_P20–1
I/O/T
(pu)
Three-state with
programmable
pull-up
Digital Audio Interface Pins. These pins provide the physical interface to the SRU. The
SRU configuration registers define the combination of on-chip peripheral inputs or
outputs connected to the pin and to the pin’s output enable. The configuration registers
of these peripherals then determine the exact behavior of the pin. Any input or output
signal present in the SRU can be routed to any of these pins. The SRU provides the
connection from the serial ports, input data port, precision clock generators and timers,
sample rate converters and SPI to the DAI_P20–1 pins. These pins have internal 22.5 kΩ
pull-up resistors that are enabled on reset. These pull-ups can be disabled using the
DAI_PIN_PULLUP register.
The following symbols appear in the Type column of Table 6: A = asynchronous, G = ground, I = input, O = output, P = power supply,
S = synchronous, (A/D) = active drive, (O/D) = open drain, and T = three-state, (pd) = pull-down resistor, (pu) = pull-up resistor.
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Table 6. Pin Descriptions (Continued)
State During and
Pin
Type
After Reset
Function
SPICLK
I/O
(pu)
Three-state with
pull-up enabled,
Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls the
rate at which data is transferred. The master can transmit data at a variety of baud rates.
driven high in SPI- SPICLK cycles once for each bit transmitted. SPICLK is a gated clock active during data
master boot mode transfers, only for the length of the transferred word. Slave devices ignore the serial clock
if the slave select input is driven inactive (high). SPICLK is used to shift out and shift in
the data driven on the MISO and MOSI lines. The data is always shifted out on one clock
edge and sampled on the opposite edge of the clock. Clock polarity and clock phase
relativetodataareprogrammableintotheSPICTLcontrolregisteranddefinethetransfer
format. SPICLK has a 22.5 kΩ internal pull-up resistor.
SPIDS
I
Input only
Serial Peripheral Interface Slave Device Select. An active low signal used to select the
processor as an SPI slave device. This input signal behaves like a chip select, and is
provided by the master device for the slave devices. In multimaster mode the processor’s
SPIDS signal can be driven by a slave device to signal to the processor (as SPI master)
that an error has occurred, as some other device is also trying to be the master device. If
asserted low when the device is in master mode, it is considered a multimaster error. For
a single-master, multiple-slave configuration where flag pins are used, this pin must be
tied or pulled high to VDDEXT on the master device. For processor to processor SPI inter-
action, any of the master processor’s flag pins can be used to drive the SPIDS signal on
the SPI slave device.
MOSI
MISO
I/O (O/D)
(pu)
Three-state with
pull-up enabled,
driven low in SPI-
SPI Master Out Slave In. If the ADSP-2136x is configured as a master, the MOSI pin
becomes a data transmit (output) pin, transmitting output data. If the processor is
configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input
master boot mode data. In an SPI interconnection, the data is shifted out from the MOSI output pin of the
master and shifted into the MOSI input(s) of the slave(s). MOSI has a 22.5 kΩ internal pull-
up resistor.
I/O (O/D)
(pu)
Three-state with
pull-up enabled
SPI Master In Slave Out. If the ADSP-2136x is configured as a master, the MISO pin
becomes a data receive (input) pin, receiving input data. If the processor is configured
as a slave, the MISO pin becomes a data transmit (output) pin, transmitting output data.
In an SPI interconnection, the data is shifted out from the MISO output pin of the slave
and shifted into the MISO input pin of the master. MISO has a 22.5 kΩ internal pull-up
resistor. MISO can be configured as O/D by setting the OPD bit in the SPICTL register.
Note: Only one slave is allowed to transmit data at any given time. To enable broadcast
transmission to multiple SPI slaves, the processor’s MISO pin can be disabled by setting
Bit 5 (DMISO) of the SPICTL register equal to 1.
CLKIN
I
Input only
Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-2136x clock input. It
configures the ADSP-2136x to use either its internal clock generator or an external clock
source. Connecting the necessary components to CLKIN and XTAL enables the internal
clock generator. Connecting the external clock to CLKIN while leaving XTAL uncon-
nected configures the processors to use the external clock source such as an external
clockoscillator. ThecoreisclockedeitherbythePLLoutputorthisclockinputdepending
on the CLK_CFG1–0 pin settings. CLKIN should not be halted, changed, or operated
below the specified frequency.
XTAL
O
I
Output only2
Input only
Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal.
CLK_CFG1–0
Core to CLKIN Ratio Control. These pins set the start up clock frequency. Note that the
operating frequency can be changed by programming the PLL multiplier and divider in
the PMCTL register at any time after the core comes out of reset. The allowed values are:
00 = 6:1
01 = 32:1
10 = 16:1
11 = reserved.
The following symbols appear in the Type column of Table 6: A = asynchronous, G = ground, I = input, O = output, P = power supply,
S = synchronous, (A/D) = active drive, (O/D) = open drain, and T = three-state, (pd) = pull-down resistor, (pu) = pull-up resistor.
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Table 6. Pin Descriptions (Continued)
State During and
After Reset
Pin
Type
Function
BOOT_CFG1–0
I
Input only
Boot Configuration Select. This pin is used to select the boot mode for the processor.
The BOOT_CFG pins must be valid before reset is asserted. For a description of the boot
mode, refer to Table 5, Boot Mode Selection.
RESETOUT
RESET
O
Output only
Input only
Reset Out. Drives out the core reset signal to an external device.
I/A
Processor Reset. Resets the ADSP-2136x to a known state. Upon deassertion, there is a
4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program
execution from the hardware reset vector address. The RESET input must be asserted
(low) at power-up.
TCK
TMS
TDI
I
Input only3
Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted
(pulsed low) after power-up or held low for proper operation of the processors.
I/S
(pu)
Three-state with
pull-up enabled
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 kΩ
internal pull-up resistor.
I/S
(pu)
Three-state with
pull-up enabled
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a
22.5 kΩ internal pull-up resistor.
TDO
TRST
O
Three-state4
Test Data Output (JTAG). Serial scan output of the boundary scan path.
I/A
(pu)
Three-state with
pull-up enabled
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)
after power-up or held low for proper operation of the ADSP-2136x. TRST has a 22.5 kΩ
internal pull-up resistor.
EMU
O (O/D)
(pu)
Three-state with
pull-up enabled
Emulation Status. Must be connected to the processor’s JTAG emulators target board
connector only. EMU has a 22.5 kΩ internal pull-up resistor.
VDDINT
VDDEXT
AVDD
P
P
P
Core Power Supply. Supplies the processor’s core.
I/O Power Supply.
Analog Power Supply. Supplies the processor’s internal PLL (clock generator). This pin
has the same specifications as VDDINT, except that added filtering circuitry is required. For
more information, see Power Supplies on Page 8.
AVSS
G
G
Analog Power Supply Return.
Power Supply Return.
GND
The following symbols appear in the Type column of Table 6: A = asynchronous, G = ground, I = input, O = output, P = power supply,
S = synchronous, (A/D) = active drive, (O/D) = open drain, and T = three-state, (pd) = pull-down resistor, (pu) = pull-up resistor.
1 RD, WR, and ALE are three-stated (and not driven) only when RESET is active.
2 Output only is a three-state driver with its output path always enabled.
3 Input only is a three-state driver with both output path and pull-up disabled.
4 Three-state is a three-state driver with pull-up disabled.
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SPECIFICATIONS
Specifications are subject to change without notice.
OPERATING CONDITIONS
K Grade
B Grade
Y Grade
Parameter Description
Min Nom Max
Min Nom Max
Min Nom Max
Unit
VDDINT
Internal (Core) Supply
Voltage
1.14 1.2
1.26
1.14 1.2
1.26
0.95 1.0
1.05
V
AVDD
Analog (PLL) Supply Voltage 1.14 1.2
External (I/O) Supply Voltage 3.13 3.3
1.26
3.47
1.14 1.2
3.13 3.3
1.26
3.47
0.95 1.0
3.13 3.3
1.05
V
V
V
VDDEXT
3.47
1
VIH
High Level Input Voltage @
DDEXT = Max
2.0
–0.5
1.74
–0.5
0
VDDEXT + 0.5 2.0
+0.8 –0.5
DDEXT + 0.5 1.74
VDDEXT + 0.5 2.0
VDDEXT + 0.5
V
1
VIL
Low Level Input Voltage @
VDDEXT = Min
+0.8
–0.5
+0.8
V
2
VIH_CLKIN
VIL_CLKIN
High Level Input Voltage @
VDDEXT = Max
V
VDDEXT + 0.5 1.74
VDDEXT + 0.5
+1.19
V
Low Level Input Voltage @
VDDEXT = Min
+1.19
+110
+110
–0.5
–40
–40
+1.19
+125
+125
–0.5
–40
–40
V
3, 4
TJ
Junction Temperature
136-Ball CSP_BGA
+125
°C
°C
3, 4
TJ
Junction Temperature
144-Lead LQFP_EP
0
+125
1 Applies to input and bidirectional pins: AD15–0, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOT_CFGx, CLK_CFGx, RESET, TCK, TMS, TDI, and TRST.
2 Applies to input pin CLKIN.
3 See Thermal Characteristics on Page 47 for information on thermal specifications.
4 See the Engineer-to-Engineer Note “Estimating Power for the ADSP-21362 SHARC Processors” (EE-277) for further information.
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ELECTRICAL CHARACTERISTICS
Parameter
Description
Test Conditions
Min
Max
Unit
1
VOH
High Level Output Voltage
Low Level Output Voltage
High Level Input Current
Low Level Input Current
@ VDDEXT = Min, IOH = –1.0 mA2
@ VDDEXT = Min, IOL = 1.0 mA2
@ VDDEXT = Max, VIN = VDDEXT Max
@ VDDEXT = Max, VIN = 0 V
@ VDDEXT = Max, VIN = 0 V
@ VDDEXT = Max, VIN = VDDEXT Max
@ VDDEXT = Max, VIN = 0 V
@ VDDEXT = Max, VIN = 0 V
tCCLK = Min, VDDINT = Nom
AVDD = Max
2.4
V
1
VOL
0.4
10
V
3, 4
IIH
μA
μA
μA
μA
μA
μA
mA
mA
pF
3
IIL
10
4
IILPU
Low Level Input Current Pull-Up
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current Pull-Up
Supply Current (Internal)
Supply Current (Analog)
200
10
5, 6
IOZH
5
IOZL
10
6
IOZLPU
200
800
10
7, 8
IDD-INTYP
9
IAVDD
10, 11
CIN
Input Capacitance
fIN = 1 MHz, TCASE = 25°C, VIN = 1.2 V
4.7
1 Applies to output and bidirectional pins: AD15–0, RD, WR, ALE, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, and XTAL.
2 See Output Drive Currents on Page 46 for typical drive current capabilities.
3 Applies to input pins: SPIDS, BOOT_CFGx, CLK_CFGx, TCK, RESET, and CLKIN.
4 Applies to input pins with 22.5 kΩ internal pull-ups: TRST, TMS, TDI.
5 Applies to three-stateable pins: FLAG3–0.
6 Applies to three-stateable pins with 22.5 kΩ pull-ups: AD15–0, DAI_Px, SPICLK, EMU, MISO, and MOSI.
7 Typical internal current data reflects nominal operating conditions.
8 See the Engineer-to-Engineer Note “Estimating Power for the ADSP-21362 SHARC Processors” (EE-277) for further information.
9 Characterized, but not tested.
10Applies to all signal pins.
11Guaranteed, but not tested.
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this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
PACKAGE INFORMATION
The information presented in Figure 4 provides details about
the package branding for the ADSP-2136x processor. For a
complete listing of product availability, see Ordering Guide on
Page 56.
Table 8. Absolute Maximum Ratings
Parameter
Rating
Internal (Core) Supply Voltage (VDDINT
)
–0.3 V to +1.5 V
–0.3 V to +1.5 V
–0.3 V to +4.6 V
–0.5 V to +3.8 V
–0.5 V to VDDEXT + 0.5 V
200 pF
Analog (PLL) Supply Voltage (AVDD
)
a
External (I/O) Supply Voltage (VDDEXT
Input Voltage
)
ADSP-2136x
tppZ-cc
vvvvvv.x n.n
Output Voltage Swing
#yyww country_of_origin
Load Capacitance
Storage Temperature Range
Junction Temperature While Biased
–65°C to +150°C
125°C
S
Figure 4. Typical Package Brand
TIMING SPECIFICATIONS
Table 7. Package Brand Information
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. For
voltage reference levels, see Figure 39 on Page 46 under Test
Conditions.
Brand Key
Field Description
Temperature Range
Package Type
t
pp
Z
RoHS Compliant Designation
See Ordering Guide
Assembly Lot Code
Silicon Revision
cc
vvvvvv.x
n.n
Switching Characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char-
acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
#
RoHS Compliant Designation
Date Code
yyww
ESD CAUTION
Timing Requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
Core Clock Requirements
The processor’s internal clock (a multiple of CLKIN) provides
the clock signal for timing internal memory, processor core, and
serial ports. During reset, program the ratio between the proces-
sor’s internal clock frequency and external (CLKIN) clock
frequency with the CLK_CFG1–0 pins.
MAXIMUM POWER DISSIPATION
See the Engineer-to-Engineer Note “Estimating Power for the
ADSP-21362 SHARC Processors” (EE-277) for detailed thermal
and power information regarding maximum power dissipation.
For information on package thermal specifications, see Thermal
Characteristics on Page 47.
The processor’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the processor uses an internal phase-locked loop (PLL,
see Figure 5). This PLL-based clocking minimizes the skew
between the system clock (CLKIN) signal and the processor’s
internal clock.
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in Table 8 may cause perma-
nent damage to the device. These are stress ratings only;
functional operation of the device at these or any other condi-
tions greater than those indicated in the operational sections of
Voltage Controlled Oscillator
In application designs, the PLL multiplier value should be
selected in such a way that the VCO frequency never exceeds
f
VCO specified in Table 11.
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• The product of CLKIN and PLLM must never exceed 1/2
fVCO (max) in Table 11 if the input divider is not enabled
(INDIV = 0).
fINPUT = CLKIN ÷ 2 when the input divider is enabled
Note the definitions of the clock periods that are a function of
CLKIN and the appropriate ratio control shown in Table 9. All
of the timing specifications for the ADSP-2136x peripherals are
defined in relation to tPCLK. Refer to the peripheral specific sec-
tion for each peripheral’s timing information.
• The product of CLKIN and PLLM must never exceed fVCO
(max) in Table 11 if the input divider is enabled
(INDIV = 1).
The VCO frequency is calculated as follows:
Table 9. Clock Periods
f
f
VCO = 2 × PLLM × fINPUT
CCLK = (2 × PLLM × fINPUT) ÷ (2 × PLLN)
Timing
Requirements
Description
where:
VCO = VCO output
tCK
CLKIN Clock Period
f
tCCLK
tPCLK
Processor Core Clock Period
Peripheral Clock Period = 2 × tCCLK
PLLM = Multiplier value programmed in the PMCTL register.
During reset, the PLLM value is derived from the ratio selected
using the CLK_CFG pins in hardware.
Figure 5 shows core to CLKIN relationships with external oscil-
lator or crystal. The shaded divider/multiplier blocks denote
where clock ratios can be set through hardware or software
using the power management control register (PMCTL). For
more information, refer to the ADSP-2136x SHARC Processor
Hardware Reference.
PLLN = 1, 2, 4, 8 based on the PLLD value programmed on the
PMCTL register. During reset this value is 1.
f
f
INPUT = Input frequency to the PLL.
INPUT = CLKIN when the input divider is disabled or
PLL
fVCO
LOOP
FILTER
PLL
DIVIDER
CLKIN
BUF
CLKIN
DIVIDER
CCLK
VCO
fINPUT
fCCLK
XTAL
CLK_CFGx/
PMCTL (2 × PLLM)
PMCTL
(2 × PLLN)
DIVIDE
BY 2
PMCTL
(INDIV)
PMCTL
(PLLBP)
PCLK
fVCO ÷ (2 × PLLM)
PMCTL (CLKOUTEN)
CLKOUT (TEST ONLY)*
RESETOUT
BUF
DELAY OF
4096 CLKIN
RESETOUT
RESET
CYCLES
CORERST
*CLKOUT (TEST ONLY) FREQUENCY IS THE SAME AS fINPUT.
THIS SIGNAL IS NOT SPECIFIED OR SUPPORTED FOR ANY DESIGN.
Figure 5. Core Clock and System Clock Relationship to CLKIN
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Power-Up Sequencing
The timing requirements for processor startup are given in
Table 10. Note that during power-up, when the VDDINT power
supply comes up after VDDEXT, a leakage current of the order of
three-state leakage current pull-up, pull-down, may be observed
on any pin, even if that is an input only (for example the RESET
pin) until the VDDINT rail has powered up.
Table 10. Power-Up Sequencing Timing Requirements (Processor Startup)
Parameter
Min
Max
Unit
Timing Requirements
tRSTVDD
RESET Low Before VDDINT/VDDEXT On
VDDINT On Before VDDEXT
0
ns
tIVDDEVDD
–50
0
102
+200
200
ms
ms
μs
1
tCLKVDD
CLKIN Valid After VDDINT/VDDEXT Valid
CLKIN Valid Before RESET Deasserted
PLL Control Setup Before RESET Deasserted
tCLKRST
tPLLRST
20
μs
Switching Characteristic
3, 4
tCORERST
Core Reset Deasserted After RESET Deasserted
4096tCK + 2 tCCLK
1 Valid VDDINT/VDDEXT assumes thatthesuppliesarefullyrampedto their1.2Vrailsand3.3Vrails. Voltagerampratescanvaryfrommicrosecondsto hundredsofmilliseconds,
depending on the design of the power supply subsystem.
2 Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time.
Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3 Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low to properly initialize and propagate
default states at all I/O pins.
4 The 4096 cycle count depends on tSRST specification in Table 12. If setup time is not met, 1 additional CLKIN cycle can be added to the core reset time, resulting in 4097 cycles
maximum.
tRSTVDD
RESET
V
DDINT
tIVDDEVDD
V
DDEXT
tCLKVDD
CLKIN
tCLKRST
CLK_CFG1–0
RESETOUT
tPLLRST
tCORERST
Figure 6. Power-Up Sequencing
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Clock Input
Table 11. Clock Input
200 MHz1
Max
333 MHz2
Max
Parameter
Unit
Min
Min
Timing Requirements
tCK
CLKIN Period
303
100
18
100
ns
tCKL
tCKH
tCKRF
tCCLK
CLKIN Width Low
12.5
12.5
7.5
7.5
ns
CLKIN Width High
CLKIN Rise/Fall (0.4 V to 2.0 V)
CCLK Period
ns
3
3
ns
4
5.0
10
3.0
10
ns
5
tVCO
VCO Frequency
200
–250
600
+250
200
–250
800
+250
MHz
ps
6, 7
tCKJ
CLKIN Jitter Tolerance
1 Applies to all 200 MHz models. See Ordering Guide on Page 56.
2 Applies to all 333 MHz models. See Ordering Guide on Page 56.
3 Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in the PMCTL register.
4 Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK
5 See Figure 5 on Page 17 for VCO diagram.
.
6 Actual input jitter should be combined with AC specifications for accurate timing analysis.
7 Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.
tCKJ
tCK
CLKIN
tCKH
tCKL
Figure 7. Clock Input
Clock Signals
The processor can use an external clock or a crystal. Refer to the
CLKIN pin description in Table 6 on Page 11. The user applica-
tion program can configure the processor to use its internal
clock generator by connecting the necessary components to the
CLKIN and XTAL pins. Figure 8 shows the component connec-
tions used for a fundamental frequency crystal operating in
parallel mode.
ADSP-2136x
R1
XTAL
CLKIN
1MΩ*
R2
47Ω
*
C1
22pF
C2
22pF
Y1
Note that the clock rate is achieved using a 16.67 MHz crystal
and a PLL multiplier ratio 16:1. (CCLK:CLKIN achieves a clock
speed of 266.72 MHz.) To achieve the full core clock rate, pro-
grams need to configure the multiplier bits in the
PMCTL register.
24.576MHz
R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL
DRIVE POWER. REFER TO CRYSTAL
MANUFACTURER’S SPECIFICATIONS.
*TYPICAL VALUES
Figure 8. Recommended Circuit for Fundamental Mode Crystal Operation
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Reset
Table 12. Reset
Parameter
Min
Unit
Timing Requirements
1
tWRST
RESET Pulse Width Low
4 × tCK
8
ns
ns
tSRST
RESET Setup Before CLKIN Low
1 Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable
VDD and CLKIN (not including start-up time of external clock oscillator).
CLKIN
tWRST
tSRST
RESET
Figure 9. Reset
Interrupts
The following timing specification applies to the FLAG0,
FLAG1, and FLAG2 pins when they are configured as IRQ0,
IRQ1, and IRQ2 interrupts.
Table 13. Interrupts
Parameter
Min
Unit
Timing Requirement
tIPW
IRQx Pulse Width
2 × tPCLK +2
ns
INTERRUPT
INPUTS
tIPW
Figure 10. Interrupts
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Core Timer
The following timing specification applies to FLAG3 when it is
configured as the core timer (TMREXP pin).
Table 14. Core Timer
Parameter
Min
Unit
Switching Characteristic
tWCTIM
TMREXP Pulse Width
2 × tPCLK – 1
ns
tWCTIM
FLAG3
(TMREXP)
Figure 11. Core Timer
Timer PWM_OUT Cycle Timing
The following timing specification applies to Timer0, Timer1,
and Timer2 in PWM_OUT (pulse-width modulation) mode.
Timer signals are routed to the DAI_P20–1 pins through the
SRU. Therefore, the timing specifications provided below are
valid at the DAI_P20–1 pins.
Table 15. Timer PWM_OUT Timing
Parameter
Min
Max
Unit
Switching Characteristic
tPWMO
Timer Pulse Width Output
2 × tPCLK – 1
2 × (231 – 1) × tPCLK
ns
tPWMO
PWM
OUTPUTS
Figure 12. Timer PWM_OUT Timing
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Timer WDTH_CAP Timing
The following timing specification applies to Timer0, Timer1,
and Timer2 in WDTH_CAP (pulse width count and capture)
mode. Timer signals are routed to the DAI_P20–1 pins through
the SRU. Therefore, the timing specification provided below are
valid at the DAI_P20–1 pins.
Table 16. Timer Width Capture Timing
Parameter
Min
Max
Unit
Timing Requirement
tPWI
Timer Pulse Width
2 × tPCLK
2 × (231– 1) × tPCLK
ns
tPWI
TIMER
CAPTURE
INPUTS
Figure 13. Timer Width Capture Timing
DAI Pin to Pin Direct Routing
For direct pin connections only (for example, DAI_PB01_I to
DAI_PB02_O).
Table 17. DAI Pin to Pin Routing
Parameter
Min
Max
10
Unit
Timing Requirement
tDPIO
Delay DAI Pin Input Valid to DAI Output Valid
1.5
ns
DAI_Pn
DAI_Pm
tDPIO
Figure 14. DAI Pin to Pin Direct Routing
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inputs and outputs are not directly routed to/from DAI pins (via
pin buffers) there is no timing data available. All timing param-
eters and switching characteristics apply to external DAI pins
(DAI_P01 through DAI_P20).
Precision Clock Generator (Direct Pin Routing)
This timing is only valid when the SRU is configured such that
the precision clock generator (PCG) takes its inputs directly
from the DAI pins (via pin buffers) and sends its outputs
directly to the DAI pins. For the other cases, where the PCG’s
Table 18. Precision Clock Generator (Direct Pin Routing)
K and B Grade
Y Grade
Parameter
Min
Max
Max
Unit
Timing Requirements
tPCGIP
tSTRIG
Input Clock Period
tPCLK × 4
4.5
ns
ns
PCG Trigger Setup Before Falling
Edge of PCG Input Clock
tHTRIG
PCG Trigger Hold After Falling
Edge of PCG Input Clock
3
ns
Switching Characteristics
tDPCGIO PCG Output Clock and Frame Sync
Active Edge Delay After PCG Input 2.5
Clock
10
10
ns
ns
tDTRIGCLK PCG Output Clock Delay After PCG 2.5 + (2.5 × tPCGIP
Trigger
)
10 + (2.5 × tPCGIP
)
12 + (2.5 × tPCGIP)
tDTRIGFS PCG Frame Sync Delay After PCG
2.5 + ((2.5 + D – PH) × tPCGIP) 10 + ((2.5 + D – PH) × tPCGIP) 12 + ((2.5 + D – PH) × tPCGIP) ns
Trigger
1
tPCGOP
Output Clock Period
2 × tPCGIP – 1 ns
D = FSxDIV, PH = FSxPHASE. For more information, refer to the ADSP-2136x SHARC Processor Hardware Reference, “Precision Clock Gener-
ators” chapter.
1 In normal mode, tPCGOP (min) = 2 × tPCGIP
.
tSTRIG
tHTRIG
DAI_Pn
PCG_TRIGx_I
tPCGIP
DAI_Pm
PCG_EXTx_I
(CLKIN)
tDPCGIO
DAI_Py
PCG_CLKx_O
tDTRIGCLK
tPCGOP
tDPCGIO
DAI_Pz
PCG_FSx_O
tDTRIGFS
Figure 15. Precision Clock Generator (Direct Pin Routing)
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Flags
The timing specifications provided below apply to the FLAG3–0
and DAI_P20–1 pins, the parallel port, and the serial peripheral
interface (SPI). See Table 6 on Page 11 for more information on
flag use.
Table 19. Flags
Parameter
Timing Requirement
tFIPW
Min
Unit
ns
FLAG3–0 IN Pulse Width
2 × tPCLK + 3
2 × tPCLK – 1
Switching Characteristic
tFOPW FLAG3–0 OUT Pulse Width
ns
FLAG
INPUTS
tFIPW
FLAG
OUTPUTS
tFOPW
Figure 16. Flags
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Memory Read—Parallel Port
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) when the processor is
accessing external memory space.
Table 20. 8-Bit Memory Read Cycle
K and B Grade
Max
Y Grade
Max
Parameter
Min
Min
Unit
Timing Requirements
tDRS
tDRH
tDAD
AD7–0 Data Setup Before RD High
AD7–0 Data Hold After RD High
AD15–8 Address to AD7–0 Data Valid
3.3
0
4.5
0
ns
ns
D + tPCLK – 5.0
D + tPCLK – 5.0 ns
Switching Characteristics
tALEW ALE Pulse Width
AD15–0 Address Setup Before ALE Deasserted tPCLK – 2.5
2 × tPCLK – 2.0
2 × tPCLK – 2.0
tPCLK – 2.5
ns
ns
ns
1
tADAS
tRRH
Delay Between RD Rising Edge to Next
Falling Edge
H + tPCLK – 1.4
H + tPCLK – 1.4
tALERW
tRWALE
ALE Deasserted to Read Asserted
Read Deasserted to ALE Asserted
AD15–0 Address Hold After ALE Deasserted
ALE Deasserted to AD7–0 Address in High-Z
RD Pulse Width
2 × tPCLK – 3.8
F + H + 0.5
tPCLK – 2.3
tPCLK
2 × tPCLK – 3.8
F + H + 0.5
tPCLK – 2.3
tPCLK
ns
ns
ns
1
tADAH
1
tALEHZ
tRW
tPCLK + 3.0
tPCLK + 3.8
ns
ns
ns
ns
ns
D – 2.0
D – 2.0
tRDDRV
tADRH
tDAWH
AD7–0 ALE Address Drive After Read High
AD15–8 Address Hold After RD High
AD15–8 Address to RD High
F + H + tPCLK – 2.3
H
F + H + tPCLK – 2.3
H
D + tPCLK – 4.0
D + tPCLK – 4.0
D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × tPCLK
H = tPCLK (if a hold cycle is specified, else H = 0)
F = 7 × tPCLK (if FLASH_MODE is set, else F = 0)
1 On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
tRWALE
tALEW
tALERW
ALE
tRRH
tRW
RD
WR
tRDDRV
tDAWH
tADAS
tADAH
tADRH
VALID
AD15–8
VALID ADDRESS
VALID ADDRESS
VALID ADDRESS
VALID ADDRESS
ADDRESS
tDAD
tDRS tDRH
VALID
VALID
DATA
VALID
DATA
AD7–0
ADDRESS
tALEHZ
NOTE: MEMORY READS ALWAYS OCCUR IN GROUPS OF FOUR BETWEEN ALE CYCLES. THIS FIGURE SHOWS ONLY
TWO MEMORY READS TO PROVIDE THE NECESSARY TIMING INFORMATION.
Figure 17. Read Cycle for 8-Bit Memory Timing
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Table 21. 16-Bit Memory Read Cycle
K and B Grade
Y Grade
Max
Parameter
Min
Max
Min
Unit
Timing Requirements
tDRS
tDRH
Switching Characteristics
tALEW ALE Pulse Width
AD15–0 Data Setup Before RD High
3.3
0
4.5
0
ns
ns
AD15–0 Data Hold After RD High
2 × tPCLK – 2.0
2 × tPCLK – 2.0
tPCLK – 2.5
ns
ns
ns
ns
1
tADAS
AD15–0 Address Setup Before ALE Deasserted tPCLK – 2.5
tALERW
ALE Deasserted to Read Asserted
2 × tPCLK – 3.8
H + tPCLK – 1.4
2 × tPCLK – 3.8
H + tPCLK – 1.4
2
tRRH
Delay Between RD Rising Edge to Next Falling
Edge
tRWALE
Read Deasserted to ALE Asserted
F + H + 0.5
F + H + 0.5
ns
ns
ns
tRDDRV
ALE Address Drive After Read High
AD15–0 Address Hold After ALE Deasserted
F + H + tPCLK – 2.3
tPCLK – 2.3
F + H + tPCLK – 2.3
tPCLK – 2.3
1
tADAH
tALEHZ1
tRW
ALE Deasserted to Address/Data15–0 in High-Z tPCLK
RD Pulse Width D – 2.0
tPCLK + 3.0 tPCLK
D – 2.0
tPCLK + 3.8 ns
ns
D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × tPCLK
H = tPCLK (if a hold cycle is specified, else H = 0)
F = 7 × tPCLK (if FLASH_MODE is set, else F = 0)
1 On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
2 This parameter is only available when in EMPP = 0 mode.
tRWALE
tALEW
tALERW
ALE
tRRH
tRW
RD
WR
tRDDRV
tALEHZ
tADAH
tDRS
tDRH
tADAS
VALID
AD15–0
VALID ADDRESS
VALID DATA
VALID DATA
ADDRESS
NOTE: FOR 16-BIT MEMORY READS, WHEN EMPP ϶ 0, ONLY ONE RD PULSE OCCURS BETWEEN ALE CYCLES.
WHEN EMPP = 0, MULTIPLE RD PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION,
SEE THE ADSP-2136x SHARC PROCESSOR HARDWARE REFERENCE.
Figure 18. Read Cycle for 16-Bit Memory Timing
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Memory Write—Parallel Port
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) when the processor is
accessing external memory space.
Table 22. 8-Bit Memory Write Cycle
K and B Grade
Min
Y Grade
Parameter
Min
Unit
Switching Characteristics
tALEW
ALE Pulse Width
2 × tPCLK – 2.0
tPCLK – 2.8
2 × tPCLK – 3.8
H + 0.5
2 × tPCLK – 2.0
tPCLK – 2.8
2 × tPCLK – 3.8
H + 0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
tADAS
tALERW
tRWALE
tWRH
AD15–0 Address Setup Before ALE Deasserted
ALE Deasserted to Write Asserted
Write Deasserted to ALE Asserted
Delay Between WR Rising Edge to Next WR Falling Edge
AD15–0 Address Hold After ALE Deasserted
WR Pulse Width
F + H + tPCLK – 2.3
tPCLK – 0.5
D – F – 2.0
tPCLK – 2.8
H
F + H + tPCLK – 2.3
tPCLK – 0.5
D – F – 2.0
tPCLK – 3.5
H
1
tADAH
tWW
tADWL
tADWH
tDWS
AD15–8 Address to WR Low
AD15–8 Address Hold After WR High
AD7–0 Data Setup Before WR High
AD7–0 Data Hold After WR High
AD15–8 Address to WR High
D – F + tPCLK – 4.0
H
D – F + tPCLK – 4.0
H
tDWH
tDAWH
D – F + tPCLK – 4.0
D – F + tPCLK – 4.0
D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × tPCLK
H = tPCLK (if a hold cycle is specified, else H = 0)
.
F = 7 × tPCLK (if FLASH_MODE is set, else F = 0). If FLASH_MODE is set, D must be 9 × tPCLK
.
1 On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
tALERW
tALEW
ALE
tRWALE
tWW
WR
tWRH
tADWL
tDAWH
RD
tADAS
tADAH
tADWH
VALID
ADDRESS
AD15
AD7
-8
VALID ADDRESS
VALID ADDRESS
tDWH
tDWS
VALID
ADDRESS
VALID DATA
VALID DATA
-0
NOTE: MEMORY WRITES ALWAYS OCCUR IN GROUPS OF FOUR BETWEEN ALE CYCLES. THIS FIGURE
SHOWS ONLY TWO MEMORY WRITES TO PROVIDE THE NECESSARY TIMING INFORMATION.
Figure 19. Write Cycle for 8-Bit Memory Timing
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Table 23. 16-Bit Memory Write Cycle
K and B Grade
Y Grade
Parameter
Min
Min
Unit
Switching Characteristics
tALEW
ALE Pulse Width
2 × tPCLK – 2.0
tPCLK – 2.5
2 × tPCLK – 2.0
tPCLK – 2.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
tADAS
AD15–0 Address Setup Before ALE Deasserted
ALE Deasserted to Write Asserted
tALERW
2 × tPCLK – 3.8
H + 0.5
2 × tPCLK – 3.8
H + 0.5
tRWALE
Write Deasserted to ALE Asserted
2
tWRH
Delay Between WR Rising Edge to Next WR Falling Edge
AD15–0 Address Hold After ALE Deasserted
WR Pulse Width
F + H + tPCLK – 2.3
tPCLK – 2.3
F + H + tPCLK – 2.3
tPCLK – 2.3
1
tADAH
tWW
D – F – 2.0
D – F + tPCLK – 4.0
H
D – F – 2.0
D – F + tPCLK – 4.0
H
tDWS
tDWH
AD15–0 Data Setup Before WR High
AD15–0 Data Hold After WR High
D = (the value set by the PPDUR Bits (5–1) in the PPCTL register) × tPCLK
H = tPCLK (if a hold cycle is specified, else H = 0)
.
F = 7 × tPCLK (if FLASH_MODE is set, else F = 0). If FLASH_MODE is set, D must be 9 × tPCLK
PCLK = (peripheral) clock period = 2 × tCCLK
.
t
1 On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
2 This parameter is only available when in EMPP = 0 mode.
tALEW
tALERW
ALE
tRWALE
tWW
WR
RD
tWRH
tDWH
tADAS
tADAH
VALID
ADDRESS
VALID
ADDRESS
AD15-0
VALID DATA
tDWS
VALID DATA
NOTE: FOR 16-BIT MEMORY WRITES, WHEN EMPP 0, ONLY ONE WR PULSE OCCURS BETWEEN ALE CYCLES.
WHEN EMPP = 0, MULTIPLE WR PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION,
SEE THE ADSP-2136x SHARC PROCESSOR HARDWARE REFERENCE.
Figure 20. Write Cycle for 16-Bit Memory Timing
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync (FS) delay and frame sync setup and
hold, 2) data delay and data setup and hold, and 3) serial clock
(SCLK) width.
Serial port signals are routed to the DAI_P20–1 pins using the
SRU. Therefore, the timing specifications provided below are
valid at the DAI_P20–1 pins.
Table 24. Serial Ports—External Clock
K and B Grade
Max
Y Grade
Max
Parameter
Min
Unit
Timing Requirements
1
tSFSE
Frame Sync Setup Before SCLK
(Externally Generated Frame Sync in Either Transmit or Receive Mode)
2.5
ns
1
1
tHFSE
Frame Sync Hold After SCLK
(Externally Generated Frame Sync in Either Transmit or Receive Mode)
2.5
2.5
2.5
ns
ns
ns
ns
ns
tSDRE
Receive Data Setup Before Receive SCLK
Receive Data Hold After SCLK
SCLK Width
1
tHDRE
tSCLKW
tSCLK
(tPCLK × 4) ÷ 2 – 2
tPCLK × 4
SCLK Period
Switching Characteristics
2
tDFSE
Frame Sync Delay After SCLK
(Internally Generated Frame Sync in Either Transmit or Receive Mode)
9.5
9.5
11
11
ns
2
tHOFSE
Frame Sync Hold After SCLK
(Internally Generated Frame Sync in Either Transmit or Receive Mode)
2
2
ns
ns
ns
2
tDDTE
Transmit Data Delay After Transmit SCLK
Transmit Data Hold After Transmit SCLK
2
tHDTE
1 Referenced to sample edge.
2 Referenced to drive edge.
Table 25. Serial Ports—Internal Clock
K and B Grade
Max
Y Grade
Max
Parameter
Min
Unit
Timing Requirements
1
tSFSI
Frame Sync Setup Before SCLK
(Externally Generated Frame Sync in Either Transmit or Receive Mode)
7
ns
1
tHFSI
Frame Sync Hold After SCLK
(Externally Generated Frame Sync in Either Transmit or Receive Mode)
2.5
7
ns
ns
ns
1
tSDRI
Receive Data Setup Before SCLK
Receive Data Hold After SCLK
1
tHDRI
2.5
Switching Characteristics
2
tDFSI
Frame Sync Delay After SCLK (Internally Generated Frame Sync in Transmit Mode)
3
8
3
3.5
9.5
4.0
ns
ns
ns
ns
ns
ns
2
tHOFSI
Frame Sync Hold After SCLK (Internally Generated Frame Sync in Transmit Mode) –1.0
Frame Sync Delay After SCLK (Internally Generated Frame Sync in Receive Mode)
2
tDFSIR
2
tHOFSIR Frame Sync Hold After SCLK (Internally Generated Frame Sync in Receive Mode) –1.0
2
tDDTI
Transmit Data Delay After SCLK
Transmit Data Hold After SCLK
2
tHDTI
–1.0
tSCLKIW Transmit or Receive SCLK Width
2 × tPCLK – 2 2 × tPCLK + 2 2 × tPCLK + 2 ns
1 Referenced to the sample edge.
2 Referenced to drive edge.
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
DATA RECEIVE—INTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
DATA RECEIVE—EXTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
tSCLKIW
tSCLKW
DAI_P20–1
(SCLK)
DAI_P20–1
(SCLK)
tDFSI
tDFSE
tHOFSI
tSFSI
tHFSI
tHOFSE
tSFSE
tHFSE
DAI_P20–1
(FS)
DAI_P20–1
(FS)
tSDRI
tHDRI
tSDRE
tHDRE
DAI_P20–1
(DATA
CHANNEL A/B)
DAI_P20–1
(DATA
CHANNEL A/B)
DATA TRANSMIT—INTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
DATA TRANSMIT—EXTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
tSCLKIW
tSCLKW
DAI_P20–1
(SCLK)
DAI_P20–1
(SCLK)
tDFSI
tDFSE
tHOFSI
tSFSI
tHFSI
tHOFSE
tSFSE
tHFSE
DAI_P20–1
(FS)
DAI_P20–1
(FS)
tDDTI
tDDTE
tHDTI
tHDTE
DAI_P20–1
(DATA
CHANNEL A/B)
DAI_P20–1
(DATA
CHANNEL A/B)
Figure 21. Serial Ports
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Table 26. Serial Ports—External Late Frame Sync
K and B Grade
Max
Y Grade
Parameter
Min
Max
Unit
Switching Characteristics
1
tDDTLFSE
Data Delay from Late External Transmit Frame Sync
or External Receive FS with MCE = 1, MFD = 0
9
10.5
ns
ns
1
tDDTENFS
Data Enable for MCE = 1, MFD = 0
0.5
1 The tDDTLFSE and tDDTENFS parameters apply to left-justified sample pair as well as serial mode, and MCE = 1, MFD = 0.
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
DRIVE
SAMPLE
DRIVE
DAI_P20–1
(SCLK)
tHFSE/I
tSFSE/I
DAI_P20–1
(FS)
tDDTE/I
tDDTENFS
tHDTE/I
DAI_P20–1
(DATA CHANNEL
A/B)
1ST BIT
2ND BIT
tDDTLFSE
LATE EXTERNAL TRANSMIT FS
SAMPLE DRIVE
DRIVE
DAI_P20–1
(SCLK)
tHFSE/I
tSFSE/I
DAI_P20–1
(FS)
tDDTE/I
tDDTENFS
tHDTE/I
DAI_P20–1
(DATA CHANNEL
A/B)
1ST BIT
2ND BIT
tDDTLFSE
Figure 22. External Late Frame Sync
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Table 27. Serial Ports—Enable and Three-State
K and B Grade
Y Grade
Parameter
Min
2
Max
Max
Unit
Switching Characteristics
1
tDDTEN
Data Enable from External Transmit SCLK
ns
ns
ns
1
tDDTTE
Data Disable from External Transmit SCLK
7
8.5
1
tDDTIN
Data Enable from Internal Transmit SCLK
–1
1 Referenced to drive edge.
DRIVE EDGE
DRIVE EDGE
DAI_P20–1
(SCLK, EXT)
tDDTEN
tDDTTE
DAI_P20–1
(DATA
CHANNEL A/B)
DRIVE EDGE
DAI_P20–1
(SCLK, INT)
tDDTIN
DAI_P20–1
(DATA
CHANNEL A/B)
Figure 23. Enable and Three-State
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Input Data Port (IDP)
The timing requirements for the IDP are given in Table 28. IDP
signals are routed to the DAI_P20–1 pins using the SRU. There-
fore, the timing specifications provided below are valid at the
DAI_P20–1 pins.
Table 28. IDP
Parameter
Min
Unit
Timing Requirements
1
tSISFS
Frame Sync Setup Before Clock Rising Edge
Frame Sync Hold After Clock Rising Edge
Data Setup Before Clock Rising Edge
Data Hold After Clock Rising Edge
Clock Width
3
ns
ns
ns
ns
ns
ns
1
tSIHFS
3
1
tSISD
3
1
tSIHD
tIDPCLKW
tIDPCLK
3
(tPCLK × 4) ÷ 2 – 1
tPCLK × 4
Clock Period
1
The data, clock, and frame sync signals can come from any of the DAI pins. Clock and frame sync can also come via the PCGs or SPORTs. The PCG’s input can be either
CLKIN or any of the DAI pins.
SAMPLE EDGE
tIDPCLK
tIDPCLKW
DAI_P20–1
(SCLK)
tSISFS
tSIHFS
DAI_P20–1
(FS)
tSISD
tSIHD
DAI_P20–1
(SDATA)
Figure 24. IDP Master Timing
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table 29. PDAP is the parallel mode operation of Channel 0 of
the IDP. For details on the operation of the IDP, refer to the
ADSP-2136x SHARC Processor Hardware Reference, “Input
Data Port” chapter.
Note that the most significant 16 bits of external 20-bit PDAP
data can be provided through either the parallel port AD15–0
pins or the DAI_P20–5 pins. The remaining 4 bits can only be
sourced through DAI_P4–1. The timing below is valid at the
DAI_P20–1 pins or at the AD15–0 pins.
Table 29. Parallel Data Acquisition Port (PDAP)
Parameter
Min
Unit
Timing Requirements
1
tSPCLKEN
PDAP_CLKEN Setup Before PDAP_CLK Sample Edge
PDAP_CLKEN Hold After PDAP_CLK Sample Edge
PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge
PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge
Clock Width
2.5
ns
ns
ns
ns
ns
ns
1
tHPCLKEN
2.5
1
tPDSD
3.0
1
tPDHD
2.5
tPDCLKW
tPDCLK
(tPCLK × 4) ÷ 2 – 3
tPCLK × 4
Clock Period
Switching Characteristics
tPDHLDD Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word
tPDSTRB PDAP Strobe Pulse Width
2 × tPCLK – 1
ns
ns
2 × tPCLK – 1.5
1 Data source pins are AD15–0 and DAI_P4–1, or DAI pins. Source pins for serial clock and frame sync are DAI pins.
SAMPLE EDGE
tPDCLK
tPDCLKW
DAI_P20–1
(PDAP_CLK)
tHPHOLD
tSPHOLD
DAI_P20–1
(PDAP_HOLD)
tPDHD
tPDSD
DAI_P20–1/
ADDR23–4
(PDAP_DATA)
tPDHLDD
tPDSTRB
DAI_P20–1
(PDAP_STROBE)
Figure 25. PDAP Timing
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Pulse-Width Modulation Generators
Table 30. PWM Timing1
Parameter
Min
Max
Unit
Switching Characteristics
tPWMW
tPWMP
PWM Output Pulse Width
PWM Output Period
tPCLK – 2
(216 – 2) × tPCLK
(216 – 1) × tPCLK
ns
ns
2 × tPCLK – 1.5
1 Note that the PWM output signals are shared on the parallel port bus (AD15-0 pins).
tPWMW
PWM
OUTPUTS
tPWMP
Figure 26. PWM Timing
Sample Rate Converter—Serial Input Port
The SRC input signals are routed from the DAI_P20–1 pins
using the SRU. Therefore, the timing specifications provided in
Table 31 are valid at the DAI_P20–1 pins. This feature is not
available on the ADSP-21363 models.
Table 31. SRC, Serial Input Port
Parameter
Min
Unit
Timing Requirements
1
tSRCSFS
Frame Sync Setup Before Serial Clock Rising Edge
Frame Sync Hold After Serial Clock Rising Edge
SDATA Setup Before Serial Clock Rising Edge
SDATA Hold After Serial Clock Rising Edge
Clock Width
3
ns
ns
ns
ns
ns
ns
1
tSRCHFS
3
1
tSRCSD
3
1
tSRCHD
tSRCCLKW
tSRCCLK
3
36
80
Clock Period
1
The data, serial clock, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via the PCGs or SPORTs. The PCG’s
input can be either CLKIN or any of the DAI pins.
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SAMPLE EDGE
tSRCCLK
DAI_P20–1
(SCLK)
tSRCCLKW
tSRCSFS
tSRCHFS
DAI_P20–1
(FS)
tSRCSD
tSRCHD
DAI_P20–1
(SDATA)
Figure 27. SRC Serial Input Port Timing
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Sample Rate Converter—Serial Output Port
For the serial output port, the frame-sync is an input and should
meet setup and hold times with regard to the serial clock on the
output port. The serial data output has a hold time and delay
specification with regard to serial clock. Note that the serial
clock rising edge is the sampling edge and the falling edge is the
drive edge.
Table 32. SRC, Serial Output Port
K and B Grade
Max
Y Grade
Parameter
Min
Max
Unit
Timing Requirements
1
tSRCSFS
Frame Sync Setup Before Serial Clock Rising Edge
Frame Sync Hold After Serial Clock Rising Edge
3
3
ns
ns
1
tSRCHFS
Switching Characteristics
1
tSRCTDD
Transmit Data Delay After Serial Clock Falling Edge
Transmit Data Hold After Serial Clock Falling Edge
10.5
12.5
ns
ns
1
tSRCTDH
2
1
The data, serial clock, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync can also come via PCG or SPORTs. PCG’s input can be
either CLKIN or any of the DAI pins.
SAMPLE EDGE
tSRCCLK
DAI_P20–1
(SCLK)
tSRCCLKW
tSRCSFS
tSRCHFS
DAI_P20–1
(FS)
tSRCTDD
tSRCTDH
DAI_P20–1
(SDATA)
Figure 28. SRC Serial Output Port Timing
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
S/PDIF Transmitter
Serial data input to the S/PDIF transmitter can be formatted as
left justified, I2S, or right justified with word widths of 16-, 18-,
20-, or 24-bits. The following sections provide timing for the
transmitter.
S/PDIF Transmitter-Serial Input Waveforms
Figure 29 shows the right-justified mode. Frame sync is high for
the left channel and low for the right channel. Data is valid on
the rising edge of serial clock. The MSB is delayed the minimum
in 24-bit output mode or the maximum in 16-bit output mode
from a frame sync transition, so that when there are 64 serial
clock periods per frame sync period, the LSB of the data is right-
justified to the next frame sync transition.
Table 33. S/PDIF Transmitter Right-Justified Mode
Parameter
Timing Requirement
tRJD
Nominal
Unit
FS to MSB Delay in Right-Justified Mode
16-Bit Word Mode
18-Bit Word Mode
20-Bit Word Mode
24-Bit Word Mode
16
14
12
8
SCLK
SCLK
SCLK
SCLK
LEFT/RIGHT CHANNEL
DAI_P20–1
FS
DAI_P20–1
SCLK
tRJD
DAI_P20–1
SDATA
LSB
MSB
MSB–1 MSB–2
LSB+2 LSB+1
LSB
Figure 29. Right-Justified Mode
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Figure 30 shows the default I2S-justified mode. The frame sync
is low for the left channel and high for the right channel. Data is
valid on the rising edge of serial clock. The MSB is left-justified
to the frame sync transition but with a delay.
Table 34. S/PDIF Transmitter I2S Mode
Parameter
Nominal
Unit
Timing Requirement
tI2SD
FS to MSB Delay in I2S Mode
1
SCLK
LEFT/RIGHT CHANNEL
DAI_P20–1
FS
DAI_P20–1
SCLK
tI2SD
DAI_P20–1
SDATA
MSB
MSB–1 MSB–2
LSB+2 LSB+1
LSB
Figure 30. I2S-Justified Mode
Figure 31 shows the left-justified mode. The frame sync is high
for the left channel and low for the right channel. Data is valid
on the rising edge of serial clock. The MSB is left-justified to the
frame sync transition with no delay.
Table 35. S/PDIF Transmitter Left-Justified Mode
Parameter
Nominal
Unit
Timing Requirement
tLJD
FS to MSB Delay in Left-Justified Mode
0
SCLK
DAI_P20–1
FS
LEFT/RIGHT CHANNEL
DAI_P20–1
SCLK
tLJD
DAI_P20–1
SDATA
MSB
MSB–1 MSB–2
LSB+2 LSB+1
LSB
Figure 31. Left-Justified Mode
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S/PDIF Transmitter Input Data Timing
The timing requirements for the S/PDIF transmitter are given
in Table 36. Input signals are routed to the DAI_P20–1 pins
using the SRU. Therefore, the timing specifications provided
below are valid at the DAI_P20–1 pins.
Table 36. S/PDIF Transmitter Input Data Timing
K Grade
Y Grade
Max
Parameter
Min
Max
Min
Unit
Timing Requirements
1
tSISFS
Frame Sync Setup Before Serial Clock Rising Edge
3
3
ns
ns
ns
ns
ns
ns
ns
ns
1
tSIHFS
Frame Sync Hold After Serial Clock Rising Edge
Data Setup Before Serial Clock Rising Edge
Data Hold After Serial Clock Rising Edge
Transmit Clock Width
3
3
1
tSISD
3
3
1
tSIHD
3
3
tSITXCLKW
tSITXCLK
tSISCLKW
tSISCLK
9
9.5
20
36
80
Transmit Clock Period
20
36
80
Clock Width
Clock Period
1
The serial clock, data and frame sync signals can come from any of the DAI pins.The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can
be either CLKIN or any of the DAI pins.
SAMPLE EDGE
tSITXCLKW
tSITXCLK
DAI_P20–1
(TxCLK)
tSISCLK
tSISCLKW
DAI_P20–1
(SCLK)
tSISFS
tSIHFS
DAI_P20–1
(FS)
tSISD
tSIHD
DAI_P20–1
(SDATA)
Figure 32. S/PDIF Transmitter Input Timing
Oversampling Clock (TxCLK) Switching Characteristics
The S/PDIF transmitter requires an oversampling clock input.
This high frequency clock (TxCLK) input is divided down to
generate the internal biphase clock.
Table 37. Oversampling Clock (TxCLK) Switching Characteristics
Parameter
Max
Unit
Frequency for TxCLK = 384 × Frame Sync
Frequency for TxCLK = 256 × Frame Sync
Frame Rate (FS)
Oversampling Ratio × Frame Sync <= 1/tSITXCLK MHz
49.2
MHz
kHz
192.0
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S/PDIF Receiver
The following section describes timing as it relates to the
S/PDIF receiver. This feature is not available on the
ADSP-21363 processors.
Internal Digital PLL Mode
In the internal digital phase-locked loop mode the internal PLL
(digital PLL) generates the 512 × FS clock.
Table 38. S/PDIF Receiver Output Timing (Internal Digital PLL Mode)
Parameter
Min
Max
Unit
Switching Characteristics
tDFSI
Frame Sync Delay After Serial Clock
Frame Sync Hold After Serial Clock
Transmit Data Delay After Serial Clock
Transmit Data Hold After Serial Clock
Transmit Serial Clock Width
5
5
ns
ns
ns
ns
ns
tHOFSI
tDDTI
–2
tHDTI
–2
38
1
tSCLKIW
1 Serial clock frequency is 64 ×FS where FS = the frequency of frame sync.
DRIVE EDGE
SAMPLE EDGE
tSCLKIW
DAI_P20–1
(SCLK)
tDFSI
tHOFSI
DAI_P20–1
(FS)
tDDTI
tHDTI
DAI_P20–1
(DATA CHANNEL
A/B)
Figure 33. S/PDIF Receiver Internal Digital PLL Mode Timing
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
SPI Interface—Master
The processor contains two SPI ports. The primary has dedi-
cated pins and the secondary is available through the DAI. The
timing provided in Table 39 and Table 40 applies to both ports.
Table 39. SPI Interface Protocol—Master Switching and Timing Specifications
K and B Grade
Y Grade
Parameter
Min
Max Min
Max
Unit
Timing Requirements
tSSPIDM
tSSPIDM
tHSPIDM
Data Input Valid to SPICLK Edge (Data Input Setup Time)
5.2
8.2
2
6.2
9.5
2
ns
ns
ns
Data Input Valid to SPICLK Edge (Data Input Setup Time) (SPI2)
SPICLK Last Sampling Edge to Data Input Not Valid
Switching Characteristics
tSPICLKM
tSPICHM
tSPICLM
tDDSPIDM
tDDSPIDM
tHDSPIDM
tSDSCIM
tSDSCIM
tHDSM
Serial Clock Cycle
8 × tPCLK – 2
4 × tPCLK – 2
4 × tPCLK – 2
8 × tPCLK – 2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Serial Clock High Period
4 × tPCLK – 2
4 × tPCLK – 2
Serial Clock Low Period
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Valid (Data Out Delay Time) (SPI2)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge
FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge (SPI2)
Last SPICLK Edge to FLAG3–0IN High
3.0
8.0
3.0
9.5
4 × tPCLK – 2
4 × tPCLK – 2.5
4 × tPCLK – 2.5
4 × tPCLK – 2
4 × tPCLK – 1
4 × tPCLK – 2
4 × tPCLK – 3.0
4 × tPCLK – 3.0
4 × tPCLK – 2
4 × tPCLK – 1
tSPITDM
Sequential Transfer Delay
DPI
(OUTPUT)
tSDSCIM
tSPICHM
tSPICLM
tSPICLKM
tHDSM
tSPITDM
SPICLK
(CP = 0,
CP = 1)
(OUTPUT)
tHDSPIDM
tDDSPIDM
MOSI
(OUTPUT)
tSSPIDM
tHSPIDM
tSSPIDM
CPHASE = 1
tHSPIDM
MISO
(INPUT)
tDDSPIDM
tHDSPIDM
MOSI
(OUTPUT)
tSSPIDM
tHSPIDM
CPHASE = 0
MISO
(INPUT)
Figure 34. SPI Master Timing
Rev. J
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July 2013
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
SPI Interface—Slave
Table 40. SPI Interface Protocol—Slave Switching and Timing Specifications
K and B Grade
Max
Y Grade
Parameter
Min
Max
Unit
Timing Requirements
tSPICLKS
tSPICHS
tSPICLS
tSDSCO
Serial Clock Cycle
4 × tPCLK – 2
2 × tPCLK – 2
2 × tPCLK – 2
ns
ns
ns
Serial Clock High Period
Serial Clock Low Period
SPIDS Assertion to First SPICLK Edge
CPHASE = 0
CPHASE = 1
2 × tPCLK
2 × tPCLK
ns
ns
tHDS
Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0
Data Input Valid to SPICLK Edge (Data Input Setup Time)
SPICLK Last Sampling Edge to Data Input Not Valid
SPIDS Deassertion Pulse Width (CPHASE = 0)
2 × tPCLK
ns
ns
ns
ns
tSSPIDS
tHSPIDS
tSDPPW
2
2
2 × tPCLK
Switching Characteristics
tDSOE SPIDS Assertion to Data Out Active
0
0
0
0
5
5
ns
ns
ns
ns
ns
ns
ns
1
tDSOE
tDSDHI
SPIDS Assertion to Data Out Active (SPI2)
8
9
SPIDS Deassertion to Data High Impedance
SPIDS Deassertion to Data High Impedance (SPI2)
SPICLK Edge to Data Out Valid (Data Out Delay Time)
5
5.5
10
11.0
1
tDSDHI
8.6
9.5
tDDSPIDS
tHDSPIDS
tDSOV
SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 2 × tPCLK
SPIDS Assertion to Data Out Valid (CPHASE = 0)
5 × tPCLK
5 × tPCLK
1 The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, refer to the ADSP-2136x SHARC Processor Hardware
Reference, “Serial Peripheral Interface Port” chapter.
Rev. J
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July 2013
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
SPIDS
(INPUT)
tSPICHS
tSPICLS
tSPICLKS
tHDS
tSDPPW
SPICLK
(CP = 0,
CP = 1)
(INPUT)
tSDSCO
tDSOE
tDSDHI
tHDSPIDS
tDDSPIDS
tDDSPIDS
MISO
(OUTPUT)
tSSPIDS tHSPIDS
CPHASE = 1
MOSI
(INPUT)
tHDSPIDS
tDSDHI
MISO
(OUTPUT)
tDSOV
tHSPIDS
CPHASE = 0
tSSPIDS
MOSI
(INPUT)
Figure 35. SPI Slave Timing
Rev. J
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July 2013
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
JTAG Test Access Port and Emulation
Table 41. JTAG Test Access Port and Emulation
Parameter
Min
Max
Unit
Timing Requirements
tTCK
TCK Period
tCK
ns
ns
ns
ns
ns
ns
tSTAP
tHTAP
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK High
System Inputs Hold After TCK High
TRST Pulse Width
5
6
1
tSSYS
7
1
tHSYS
tTRSTW
Switching Characteristics
tDTDO TDO Delay from TCK Low
System Outputs Delay After TCK Low
18
4 × tCK
7
ns
ns
2
tDSYS
tCK ÷ 2 + 7
1 System Inputs = ADDR15–0, SPIDS, CLK_CFG1–0, RESET, BOOT_CFG1–0, MISO, MOSI, SPICLK, DAI_Px, and FLAG3–0.
2 System Outputs = MISO, MOSI, SPICLK, DAI_Px, ADDR15–0, RD, WR, FLAG3–0, EMU, and ALE.
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 36. IEEE 1149.1 JTAG Test Access Port
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July 2013
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
OUTPUT DRIVE CURRENTS
CAPACITIVE LOADING
Figure 37 shows typical I-V characteristics for the output driv-
ers of the processor. The curves represent the current drive
capability of the output drivers as a function of output voltage.
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 38). Figure 42 shows graphically
how output delays and holds vary with load capacitance. The
graphs of Figure 40, Figure 41, and Figure 42 may not be linear
outside the ranges shown for Typical Output Delay versus Load
Capacitance and Typical Output Rise Time (20% to 80%,
V = Min) versus Load Capacitance.
40
V
OH
30
3.3V, +25°C
3.47V, -45°C
20
12
10
10
0
3.11V, +125°C
RISE
y = 0.0467x + 1.6323
FALL
-
10
8
3.11V, +125°C
-
20
3.3V, +25°C
3.5
6
V
-
-
30
OL
0.5
3.47V,
-
45°C
4
40
y = 0.045x + 1.524
0
1.0
1.5
2.0
2.5
3.0
SWEEP (V
) VOLTAGE (V)
DDEXT
2
0
Figure 37. ADSP-2136x Typical Drive
50
100
150
200
250
0
TEST CONDITIONS
LOAD CAPACITANCE (pF)
The ac signal specifications (timing parameters) appear in
Table 12 on Page 20 through Table 41 on Page 45. These include
output disable time, output enable time, and capacitive loading.
The timing specifications for the SHARC apply for the voltage
reference levels in Figure 38.
Figure 40. Typical Output Rise/Fall Time
(20% to 80%, VDDEXT = Max)
12
10
Timing is measured on signals when they cross the 1.5 V level as
described in Figure 39. All delays (in nanoseconds) are mea-
sured between the point that the first signal reaches 1.5 V and
the point that the second signal reaches 1.5 V.
RISE
y = 0.049x + 1.5105
FALL
8
6
TO
OUTPUT
PIN
ꢀꢁȍ
V
LOAD
y = 0.0482x + 1.4604
30pF
4
2
Figure 38. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
INPUT
OR
1.5V
1.5V
OUTPUT
Figure 41. Typical Output Rise/Fall Time
(20% to 80%, VDDEXT = Min)
Figure 39. Voltage Reference Levels for AC Measurements
Rev. J
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July 2013
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Values of θJC are provided for package comparison and PCB
design considerations when an exposed pad is required. Note
that the thermal characteristics values provided in Table 42
through Table 44 are modeled values.
10
8
y = 0.0488x
-1.5923
6
Table 42. Thermal Characteristics for BGA (No Thermal vias
in PCB)
4
Parameter
θJA
Condition
Typical
25.40
21.90
20.90
5.07
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
2
0
Airflow = 0 m/s
Airflow = 1 m/s
Airflow = 2 m/s
θJMA
θJMA
θJC
-
-
2
4
ΨJT
Airflow = 0 m/s
Airflow = 1 m/s
Airflow = 2 m/s
0.140
0.330
0.410
0
50
100
150
200
ΨJMT
ΨJMT
LOAD CAPACITANCE (pF)
Figure 42. Typical Output Delay or Hold versus Load Capacitance
(at Ambient Temperature)
Table 43. Thermal Characteristics for BGA (Thermal vias in
PCB)
Parameter
θJA
Condition
Typical
23.40
20.00
19.20
5.00
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
THERMAL CHARACTERISTICS
Airflow = 0 m/s
Airflow = 1 m/s
Airflow = 2 m/s
The processor is rated for performance over the temperature
range specified in Operating Conditions on Page 14.
θJMA
θJMA
θJC
Table 42 through Table 44 airflow measurements comply with
JEDEC standards JESD51-2 and JESD51-6 and the junction-to-
board measurement complies with JESD51-8. Test board and
thermal via design comply with JEDEC standards JESD51-9
(BGA) and JESD51-5 (LQFP_EP). The junction-to-case mea-
surement complies with MIL-STD-883. All measurements use a
2S2P JEDEC test board.
ΨJT
Airflow = 0 m/s
Airflow = 1 m/s
Airflow = 2 m/s
0.130
0.300
0.360
ΨJMT
ΨJMT
Table 44. Thermal Characteristics for LQFP_EP (with
Exposed Pad Soldered to PCB)
Industrial applications using the BGA package require thermal
vias, to an embedded ground plane, in the PCB. Refer to JEDEC
standard JESD51-9 for printed circuit board thermal ball land
and thermal via design information.
Parameter
θJA
Condition
Typical
16.80
14.20
13.50
7.25
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Airflow = 0 m/s
Airflow = 1 m/s
Airflow = 2 m/s
θJMA
θJMA
θJC
Industrial applications using the LQFP_EP package require
thermal trace squares and thermal vias, to an embedded ground
plane, in the PCB. Refer to JEDEC standard JESD51-5 for more
information.
ΨJT
Airflow = 0 m/s
Airflow = 1 m/s
Airflow = 2 m/s
0.51
To determine the junction temperature of the device while on
the application PCB, use:
ΨJMT
ΨJMT
0.72
0.80
TJ = TT + JT PD
where:
TJ = junction temperature (°C)
TT = case temperature (°C) measured at the top center of the
package
ΨJT = junction-to-top (of package) characterization parameter
is the typical value from Table 42 through Table 44.
P
D = power dissipation. See the Engineer-to-Engineer Note
“Estimating Power for the ADSP-21362 SHARC Processors”
(EE-277) for more information.
Values of θJA are provided for package comparison and PCB
design considerations.
Rev. J
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July 2013
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
144-LEAD LQFP_EP PIN CONFIGURATIONS
The following table shows the processor’s pin names and, when
applicable, their default function after reset in parentheses.
Table 45. LQFP_EP Pin Assignments
Pin Name
VDDINT
CLK_CFG0
CLK_CFG1
BOOT_CFG0
BOOT_CFG1
GND
Pin No.
1
Pin Name
VDDINT
GND
Pin No.
37
Pin Name
VDDEXT
Pin No.
73
Pin Name
GND
Pin No.
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145*
2
38
GND
74
VDDINT
GND
3
RD
39
VDDINT
75
4
ALE
40
GND
76
VDDINT
GND
5
AD15
AD14
AD13
GND
41
DAI_P10 (SD2B)
DAI_P11 (SD3A)
DAI_P12 (SD3B)
DAI_P13 (SCLK3)
DAI_P14 (SFS3)
DAI_P15 (SD4A)
VDDINT
77
6
42
78
VDDINT
GND
VDDEXT
GND
7
43
79
8
44
80
VDDEXT
GND
VDDINT
GND
9
VDDEXT
AD12
VDDINT
GND
45
81
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
46
82
VDDINT
GND
VDDINT
GND
47
83
48
GND
84
VDDINT
RESET
SPIDS
GND
VDDINT
GND
AD11
AD10
AD9
49
GND
85
50
DAI_P16 (SD4B)
DAI_P17 (SD5A)
DAI_P18 (SD5B)
DAI_P19 (SCLK5)
VDDINT
86
FLAG0
FLAG1
AD7
51
87
AD8
52
88
VDDINT
SPICLK
MISO
MOSI
GND
DAI_P1 (SD0A) 53
89
GND
VDDINT
GND
54
55
90
VDDINT
GND
GND
91
DAI_P2 (SD0B) 56
DAI_P3 (SCLK0) 57
GND
92
VDDEXT
GND
VDDEXT
93
VDDINT
VDDEXT
Avdd
GND
58
59
60
61
62
DAI_P20 (SFS5)
GND
94
VDDINT
AD6
VDDEXT
95
VDDINT
VDDINT
96
Avss
AD5
GND
FLAG2
97
GND
AD4
DAI_P4 (SFS0)
FLAG3
98
RESETOUT
EMU
VDDINT
GND
DAI_P5 (SD1A) 63
DAI_P6 (SD1B) 64
DAI_P7 (SCLK1) 65
VDDINT
99
GND
100
101
102
103
104
105
106
107
108
TDO
AD3
VDDINT
TDI
AD2
VDDINT
66
67
68
69
70
GND
TRST
VDDEXT
GND
GND
VDDINT
TCK
VDDINT
GND
TMS
AD1
GND
VDDINT
GND
AD0
DAI_P8 (SFS1)
GND
CLKIN
XTAL
WR
DAI_P9 (SD2A) 71
VDDINT 72
VDDINT
VDDINT
VDDINT
VDDEXT
GND
*The ePAD is electrically connected to GND inside the chip (see Figure 43 and Figure 44), therefore connecting the pad to GND is optional.
For better thermal performance the ePAD should be soldered to the board and thermally connected to the GND plane with vias.
Rev. J
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Page 48 of 60
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July 2013
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Figure 43 shows the top view of the 144-lead LQFP_EP pin con-
figuration. Figure 44 shows the bottom view of the 144-lead
LQFP_EP lead configuration.
LEAD 144
LEAD 1
LEAD 109
LEAD 108
LEAD 1 INDICATOR
ADSP-2136x
144-LEAD LQFP_EP
TOP VIEW
LEAD 36
LEAD 73
LEAD 37
LEAD 72
Figure 43. 144-Lead LQFP_EP Lead Configuration (Top View)
LEAD 109
LEAD 144
LEAD 108
LEAD 1
ADSP-2136x
144-LEAD LQFP_EP
GND PAD
LEAD 1 INDICATOR
(LEAD 145)
BOTTOM VIEW
LEAD 73
LEAD 36
LEAD 72
LEAD 37
Figure 44. 144-Lead LQFP_EP Lead Configuration (Bottom View)
Rev. J
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July 2013
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
136-BALL BGA PIN CONFIGURATIONS
The following table shows the processor’s ball names and, when
applicable, their default function after reset in parentheses.
Table 46. BGA Pin Assignments
Ball Name
CLK_CFG0
XTAL
Ball No. Ball Name
Ball No. Ball Name
Ball No. Ball Name
Ball No.
D01
D02
D04
D05
D06
D09
D10
D11
D13
D14
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
E01
E02
E04
E05
E06
E09
E10
E11
E13
E14
CLK_CFG1
GND
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
F01
F02
F04
F05
F06
F09
F10
F11
F13
F14
BOOT_CFG1
BOOT_CFG0
GND
C01
C02
C03
C12
C13
C14
VDDINT
GND
GND
GND
GND
GND
GND
GND
GND
VDDINT
TMS
VDDEXT
CLKIN
TRST
TCK
GND
TDI
GND
RESETOUT
TDO
AVSS
VDDINT
AVDD
EMU
VDDEXT
SPICLK
RESET
VDDINT
GND
MOSI
MISO
SPIDS
VDDINT
GND
GND
GND
GND
VDDINT
GND
FLAG1
FLAG0
GND
AD7
G01
G02
G13
G14
AD6
H01
H02
H13
H14
VDDINT
VDDEXT
GND
VDDEXT
DAI_P18 (SD5B)
DAI_P17 (SD5A)
GND
GND
DAI_P19 (SCLK5)
GND
GND
GND
GND
GND
GND
GND
GND
GND
FLAG2
DAI_P20 (SFS5)
FLAG3
Rev. J
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Table 46. BGA Pin Assignments (Continued)
Ball Name
AD5
Ball No. Ball Name
Ball No. Ball Name
Ball No. Ball Name
Ball No.
M01
J01
AD3
K01
K02
K04
K05
K06
K09
K10
K11
K13
K14
P01
P02
P03
P04
P05
P06
P07
P08
P09
P10
P11
P12
P13
P14
AD2
L01
L02
L04
L05
L06
L09
L10
L11
L13
L14
AD0
AD4
J02
VDDINT
AD1
WR
M02
GND
J04
GND
GND
GND
M03
GND
J05
GND
GND
GND
M12
GND
J06
GND
GND
DAI_P12 (SD3B)
DAI_P13 (SCLK3)
M13
GND
J09
GND
GND
M14
GND
J10
GND
GND
GND
J11
GND
GND
VDDINT
J13
GND
GND
DAI_P16 (SD4B)
AD15
J14
DAI_P15 (SD4A)
AD14
DAI_P14 (SFS3)
N01
N02
N03
N04
N05
N06
N07
N08
N09
N10
N11
N12
N13
N14
ALE
AD13
RD
AD12
VDDINT
AD11
VDDEXT
AD8
AD10
AD9
VDDINT
DAI_P1 (SD0A)
DAI_P3 (SCLK0)
DAI_P5 (SD1A)
DAI_P6 (SD1B)
DAI_P7 (SCLK1)
DAI_P8 (SFS1)
DAI_P9 (SD2A)
DAI_P11 (SD3A)
DAI_P2 (SD0B)
VDDEXT
DAI_P4 (SFS0)
VDDINT
VDDINT
GND
DAI_P10 (SD2B)
Figure 45 and Figure 46 show BGA pin assignments from the
bottom and top, respectively.
Note: Use the center block of ground pins to provide thermal
pathways to your printed circuit board’s ground plane.
Rev. J
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
1
2
3
4
5
6
7
8
9
10 11 12 13 14
14 13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
K
L
M
N
P
M
N
P
KEY
KEY
V
V
A
VDD
DDINT
V
A
VDD
GND
DDINT
GND
A
A
I/O SIGNALS
DDEXT
VSS
V
I/O SIGNALS
DDEXT
VSS
Figure 45. BGA Pin Assignments (Bottom View, Summary)
Figure 46. BGA Pin Assignments (Top View, Summary)
Rev. J
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July 2013
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
PACKAGE DIMENSIONS
The processor is available in 136-ball BGA and 144-lead
exposed pad (LQFP_EP) packages.
22.20
22.00 SQ
21.80
20.20
20.00 SQ
19.80
1.60 MAX
0.75
0.60
0.45
109
108
109
108
144
144
1
1
SEATING
PLANE
PIN 1
EXPOSED*
PAD
8.80 SQ
1.45
1.40
1.35
0.20
0.15
0.09
0.15
0.10
0.05
TOP VIEW
BOTTOM VIEW
(PINS UP)
7°
3.5°
0°
(PINS DOWN)
36
73
73
36
72
72
0.08
37
37
COPLANARITY
0.27
0.22
0.17
VIEW A
0.50
VIEW A
BSC
LEAD PITCH
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BFB-HD
*
EXPOSED PAD IS COINCIDENT WITH BOTTOM SURFACE AND
DOES NOT PROTRUDE BEYOND IT. EXPOSED PAD IS CENTERED.
Figure 47. 144-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP1]
(SW-144-1)
Dimensions shown in millimeters
1 For information relating to the exposed pad on the SW-144-1 package, see the table endnote on Page 48.
Rev. J
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
12.10
12.00 SQ
11.90
A1 BALL
CORNER
A1 BALL
CORNER
13
11
9
7
5
3
1
2
14
12
10
8
6
4
A
B
C
D
E
F
10.40
BSC SQ
G
H
J
0.80
BSC
K
L
M
N
P
BOTTOM VIEW
DETAIL A
TOP VIEW
1.31
1.21
1.10
DETAIL A
1.70 MAX
0.25 MIN
*
0.50
0.45
0.40
COPLANARITY
0.12
SEATING
PLANE
BALL DIAMETER
*
COMPLIANT WITH JEDEC STANDARDS MO-275-GGAA-1
WITH EXCEPTION TO BALL DIAMETER.
Figure 48. 136-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-136-1)
Dimensions shown in millimeters
SURFACE-MOUNT DESIGN
Table 47 is provided as an aid to PCB design. For industry stan-
dard design recommendations, refer to IPC-7351, Generic
Requirements for Surface-Mount Design and Land Pattern
Standard.
Table 47. BGA Data for Use with Surface-Mount Design
Package Solder Mask
Package
Package Ball Attach Type
Opening
Package Ball Pad Size
0.53 mm diameter
136-Ball CSP_BGA (BC-136-1)
Solder Mask Defined
0.40 mm diameter
Rev. J
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
AUTOMOTIVE PRODUCTS
Some ADSP-2136x models are available for automotive applica-
tions with controlled manufacturing. Note that these special
models may have specifications that differ from the general
release models.
The automotive grade products shown in Table 48 are available
for use in automotive applications. Contact your local ADI
account representative or authorized ADI product distributor
for specific product ordering information. Note that all automo-
tive products are RoHS compliant.
Table 48. Automotive Products
Temperature
Range1
Instruction On-Chip
Package
Option
Model
Notes
2
Rate
SRAM
3M Bit
3M Bit
3M Bit
3M Bit
3M Bit
3M Bit
3M Bit
3M Bit
3M Bit
3M Bit
3M Bit
3M Bit
3M Bit
3M Bit
3M Bit
ROM
Package Description
136-Ball CSP_BGA
144-Lead LQFP_EP
144-Lead LQFP_EP
136-Ball CSP_BGA
144-Lead LQFP_EP
144-Lead LQFP_EP
136-Ball CSP_BGA
144-Lead LQFP_EP
144-Lead LQFP_EP
144-Lead LQFP_EP
144-Lead LQFP_EP
144-Lead LQFP_EP
136-Ball CSP_BGA
144-Lead LQFP_EP
144-Lead LQFP_EP
AD21362WBBCZ1xx
AD21362WBSWZ1xx
AD21362WYSWZ2xx
AD21363WBBCZ1xx
AD21363WBSWZ1xx
AD21363WYSWZ2xx
AD21364WBBCZ1xx
AD21364WBSWZ1xx
AD21364WYSWZ2xx
AD21365WBSWZ1xxA
AD21365WBSWZ1xxF
AD21365WYSWZ2xxA
AD21366WBBCZ1xxA
AD21366WBSWZ1xxA
AD21366WYSWZ2xxA
–40°C to +85°C
–40°C to +85°C
–40°C to +105°C
–40°C to +85°C
–40°C to +85°C
–40°C to +105°C
–40°C to +85°C
–40°C to +85°C
–40°C to +105°C
–40°C to +85°C
–40°C to +85°C
–40°C to +105°C
–40°C to +85°C
–40°C to +85°C
–40°C to +105°C
333 MHz
333 MHz
200 MHz
333 MHz
333 MHz
200 MHz
333 MHz
333 MHz
200 MHz
333 MHz
333 MHz
200 MHz
333 MHz
333 MHz
200 MHz
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
BC-136-1
SW-144-1
SW-144-1
BC-136-1
SW-144-1
SW-144-1
BC-136-1
SW-144-1
SW-144-1
SW-144-1
SW-144-1
SW-144-1
BC-136-1
SW-144-1
SW-144-1
2
2
2, 3, 4
2, 3, 4
2, 3, 4
3, 4
3, 4
3, 4
1 Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 14 for junction temperature (TJ)
specification which is the only temperature specification.
2 License from DTLA required for these products.
3 Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at
www.analog.com/sharc.
4 License from Dolby Laboratories, Inc., and Digital Theater Systems (DTS) required for these products.
Rev. J
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
ORDERING GUIDE
Temperature
Range2
Instruction
Rate
On-Chip
SRAM
Package
Description
Package
Option
Model1
Notes
ROM
ADSP-21363KBC-1AA
ADSP-21363KBCZ-1AA
ADSP-21363KSWZ-1AA
ADSP-21363BBC-1AA
ADSP-21363BBCZ-1AA
ADSP-21363BSWZ-1AA
ADSP-21363YSWZ-2AA
ADSP-21364KBCZ-1AA
ADSP-21364KSWZ-1AA
ADSP-21364BBCZ-1AA
ADSP-21364BSWZ-1AA
ADSP-21364YSWZ-2AA
ADSP-21366KBCZ-1AR
ADSP-21366KBCZ-1AA
ADSP-21366KSWZ-1AA
1 Z = RoHS compliant part.
0°C to +70°C
333 MHz
333 MHz
333 MHz
333 MHz
333 MHz
333 MHz
200 MHz
333 MHz
333 MHz
333 MHz
333 MHz
200 MHz
333 MHz
333 MHz
333 MHz
3M Bit
3M Bit
3M Bit
3M Bit
3M Bit
3M Bit
3M Bit
3M Bit
3M Bit
3M Bit
3M Bit
3M Bit
3M Bit
3M Bit
3M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
136-Ball CSP_BGA
136-Ball CSP_BGA
BC-136-1
BC-136-1
0°C to +70°C
0°C to +70°C
144-Lead LQFP_EP SW-144-1
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +105°C
0°C to +70°C
136-Ball CSP_BGA
136-Ball CSP_BGA
BC-136-1
BC-136-1
144-Lead LQFP_EP SW-144-1
144-Lead LQFP_EP SW-144-1
3
136-Ball CSP_BGA
144-Lead LQFP_EP SW-144-1
136-Ball CSP_BGA BC-136-1
BC-136-1
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
–40°C to +105°C
0°C to +70°C
144-Lead LQFP_EP SW-144-1
144-Lead LQFP_EP SW-144-1
3, 4, 5
3, 4
136-Ball CSP_BGA
136-Ball CSP_BGA
BC-136-1
BC-136-1
0°C to +70°C
3, 4
0°C to +70°C
144-Lead LQFP_EP SW-144-1
2 Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 14 for junction temperature (TJ)
specification which is the only temperature specification.
3 License from Dolby Laboratories, Inc., and Digital Theater Systems (DTS) required for these products.
4 Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at
www.analog.com/sharc.
5 R = Tape and reel.
Rev. J
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July 2013
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Rev. J
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Page 57 of 60
|
July 2013
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Rev. J
|
Page 58 of 60
|
July 2013
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Rev. J
|
Page 59 of 60
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July 2013
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06359-0-7/13(J)
Rev. J
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Page 60 of 60
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July 2013
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