ADSP-2163KS-100_技术文档

a

DSP Microcomputers with ROM

ADSP-216x

FUNCTIONAL BLOCK DIAGRAM

SUMMARY

16-Bit Fixed-Point DSP Microprocessors with

On-Chip Memory

Enhanced Harvard Architecture for Three-Bus

Performance: Instruction Bus and Dual Data Buses

Independent Computation Units: ALU, Multiplier/

Accumulator and Shifter

Single-Cycle Instruction Execution and Multifunction

Instructions

On-Chip Program Memory ROM and Data Memory RAM

Integrated I/O Peripherals: Serial Ports, Timer

MEMORY

DATA ADDRESS

PROGRAM

SEQUENCER

GENERATORS

DATA

MEMORY

PROGRAM

MEMORY

DAG 2

DAG 1

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

EXTERNAL

ADDRESS

BUS

PROGRAM MEMORY DATA

DATA MEMORY DATA

EXTERNAL

DATA

BUS

FEATURES

ARITHMETIC UNITS

SERIAL PORTS

SPORT 0 SPORT 1

TIMER

25 MIPS, 40 ns Maximum Instruction Rate (5 V)

Separate On-Chip Buses for Program and Data Memory

Program Memory Stores Both Instructions and Data

(Three-Bus Performance)

ALU MAC SHIFTER

ADSP-2100 CORE

Dual Data Address Generators with Modulo and

Bit-Reverse Addressing

Efficient Program Sequencing with Zero-Overhead

Looping: Single-Cycle Loop Setup

Double-Buffered Serial Ports with Companding Hardware,

Automatic Data Buffering and Multichannel Operation

Three Edge- or Level-Sensitive Interrupts

Low Power IDLE Instruction

Fabricated in a high speed, submicron, double-layer metal

CMOS process, the highest-performance ADSP-216x proces-

sors operate at 25 MHz with a 40 ns instruction cycle time.

Every instruction can execute in a single cycle. Fabrication in

CMOS results in low power dissipation.

PLCC and MQFP Packages

The ADSP-2100 Family’s flexible architecture and compre-

hensive instruction set support a high degree of parallelism.

In one cycle the ADSP-216x can perform all of the following

operations:

GENERAL DESCRIPTION

The ADSP-216x Family processors are single-chip micro-

computers optimized for digital signal processing (DSP)

and other high speed numeric processing applications. The

ADSP-216x processors are all built upon a common core with

ADSP-2100. Each processor combines the core DSP architec-

ture—computation units, data address generators and program

sequencer—with features such as on-chip program ROM and

data memory RAM, a programmable timer and two serial ports.

The ADSP-2165/ADSP-2166 also adds program memory and

power-down mode.

•

Generate the next program address

Fetch the next instruction

Perform one or two data moves

Update one or two data address pointers

Perform a computation

Receive and transmit data via one or two serial ports

Table I shows the features of each ADSP-216x processor.

The ADSP-216x series are memory-variant versions of the

ADSP-2101 and ADSP-2103 that contain factory-programmed

on-chip ROM program memory. These devices offer different

amounts of on-chip memory for program and data storage.

Table I shows the features available in the ADSP-216x series of

custom ROM-coded processors.

This data sheet describes the following ADSP-216x Family

processors:

ADSP-2161/ADSP-2162/

ADSP-2163/ADSP-2164

ADSP-2165/ADSP-2166

Custom ROM-programmed DSPs:

ROM-programmed ADSP-216x

processors with power-down and

larger on-chip memories (12K Pro-

gram Memory ROM, 1K Program

Memory RAM, 4K Data Memory

RAM)

The ADSP-216x products eliminate the need for an external

boot EPROM in your system, and can also eliminate the need

for any external program memory by fitting the entire applica-

tion program in on-chip ROM. These devices thus provide an

excellent option for volume applications where board space and

system cost constraints are of critical concern.

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

ADSP-216x

TABLE OF CONTENTS

TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Output Disable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Output Enable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

TIMING PARAMETERS

SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . .

Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . .

1

3

(ADSP-2161/ADSP-2163/ADSP-2165) . . . . . . . . . . . . . . 21

GENERAL NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

TIMING NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

MEMORY REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . 21

CLOCK SIGNALS AND RESET . . . . . . . . . . . . . . . . . . . 22

INTERRUPTS AND FLAGS . . . . . . . . . . . . . . . . . . . . . . 23

BUS REQUEST/BUS GRANT . . . . . . . . . . . . . . . . . . . . . 24

MEMORY READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

MEMORY WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

SERIAL PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

TIMING PARAMETERS

(ADSP-2162/ADSP-2164/ADSP-2166) . . . . . . . . . . . . . . 28

GENERAL NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

TIMING NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

MEMORY REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . 28

CLOCK SIGNALS AND RESET . . . . . . . . . . . . . . . . . . . 29

INTERRUPTS AND FLAGS . . . . . . . . . . . . . . . . . . . . . . . 30

BUS REQUEST/BUS GRANT . . . . . . . . . . . . . . . . . . . . . 31

MEMORY READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

MEMORY WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

SERIAL PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

PIN CONFIGURATIONS

Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 6

Program Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Program Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Data Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Data Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Power-Down Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Entering Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Exiting Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Low Power IDLE Instruction . . . . . . . . . . . . . . . . . . . . . . . 10

ADSP-216x Prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Ordering Procedure for ADSP-216x ROM Processors . . . . 10

Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

SPECIFICATIONS–RECOMMENDED OPERATING

CONDITIONS

(ADSP-2161/ADSP-2163/ADSP-2165) . . . . . . . . . . . . . . 13

ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . 13

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 13

SPECIFICATIONS–SUPPLY CURRENT AND POWER

(ADSP-2161/ADSP-2163/ADSP-2165) . . . . . . . . . . . . . . 14

POWER DISSIPATION EXAMPLE . . . . . . . . . . . . . . . . . 15

ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . . 15

CAPACITIVE LOADING . . . . . . . . . . . . . . . . . . . . . . . . . 15

SPECIFICATIONS–

68-Lead PLCC (ADSP-216x) . . . . . . . . . . . . . . . . . . . . . 35

80-Lead MQFP (ADSP-216x) . . . . . . . . . . . . . . . . . . . . . 36

PACKAGE OUTLINE DIMENSIONS

68-Lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

80-Lead MQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

(ADSP-2161/ADSP-2163/ADSP-2165) . . . . . . . . . . . . . . 16

TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Output Disable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Output Enable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

SPECIFICATIONS–RECOMMENDED OPERATING

CONDITIONS

(ADSP-2162/ADSP-2164/ADSP-2166) . . . . . . . . . . . . . . 17

ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . 17

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 17

SPECIFICATIONS–SUPPLY CURRENT AND POWER

(ADSP-2162/ADSP-2164/ADSP-2166) . . . . . . . . . . . . . . 18

POWER DISSIPATION EXAMPLE . . . . . . . . . . . . . . . . . 19

ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . . 19

CAPACITIVE LOADING . . . . . . . . . . . . . . . . . . . . . . . . . 19

–2–

REV. 0

ADSP-216x

Table I. ADSP-216x ROM-Programmed Processor Features

Feature

2161

2162

2163

2164

2165

2166

Data Memory (RAM)

Program Memory (ROM)

Program Memory (RAM)

Timer

Serial Port 0 (Multichannel)

Serial Port 1

1/2K

8K

1/2K

8K

1/2K

4K

1/2K

4K

12K

1K

•

4K

12K

1K

•

Supply Voltage

5 V

3.3 V

5 V

3.3 V

5 V

3.3 V

Speed Grades (Instruction Cycle Time)

10.24 MHz (97.6 ns)

13.00 MHz (76.9 ns)

16.67 MHz (60 ns)

20.00 MHz (50 ns)

25 MHz (40 ns)

•

Packages

68-Lead PLCC

80-Lead MQFP

Temperature Grades

K Commercial, 0°C to +70°C

B Industrial, –40°C to +85°C

•

ARCHITECTURE OVERVIEW

Development Tools

Figure 1 shows a block diagram of the ADSP-216x architecture.

The processors contain three independent computational units:

the ALU, the multiplier/accumulator (MAC), and the shifter.

The computational units process 16-bit data directly and have

provisions to support multiprecision computations. The ALU

performs a standard set of arithmetic and logic operations;

division primitives are also supported. The MAC performs

single-cycle multiply, multiply/add, and multiply/subtract opera-

tions. The shifter performs logical and arithmetic shifts, normal-

ization, denormalization, and derive exponent operations. The

shifter can be used to efficiently implement numeric format control

including multiword floating-point representations.

The ADSP-216x processors are supported by a complete set of

tools for system development. The ADSP-2100 Family Devel-

opment Software includes C and assembly language tools that

allow programmers to write code for any of the ADSP-216x

processors. The ANSI C compiler generates ADSP-216x assem-

bly source code, while the runtime C library provides ANSI-

standard and custom DSP library routines. The ADSP-216x

assembler produces object code modules that the linker com-

bines into an executable file. The processor simulators provide

an interactive instruction-level simulation with a reconfigurable,

windowed user interface. A PROM splitter utility generates

PROM programmer compatible files.

EZ-ICE^®in-circuit emulators allow debugging of ADSP-21xx

systems by providing a full range of emulation functions such

as modification of memory and register values and execution

breakpoints. EZ-LAB^®demonstration boards are complete DSP

systems that execute EPROM-based programs.

The internal result (R) bus directly connects the computational

units so that the output of any unit may be used as the input of

any unit on the next cycle.

A powerful program sequencer and two dedicated data address

generators ensure efficient use of these computational units.

The sequencer supports conditional jumps, subroutine calls,

and returns in a single cycle. With internal loop counters and

loop stacks, the ADSP-216x executes looped code with zero

overhead—no explicit jump instructions are required to main-

tain the loop.

The EZ-Kit Lite is a very low-cost evaluation/development

platform that contains both the hardware and software needed

to evaluate the ADSP-21xx architecture.

Additional details and ordering information are available in the

ADSP-2100 Family Software & Hardware Development Tools data

sheet (ADDS-21xx-TOOLS). This data sheet can be requested

from any Analog Devices sales office or distributor.

Two data address generators (DAGs) provide addresses for

simultaneous dual operand fetches (from data memory and

program memory). Each DAG maintains and updates four

address pointers. Whenever the pointer is used to access data

(indirect addressing), it is post-modified by the value of one of

four modify registers. A length value may be associated with

each pointer to implement automatic modulo addressing for

circular buffers. The circular buffering feature is also used by

the serial ports for automatic data transfers to (and from) on-

chip memory.

Additional Information

This data sheet provides a general overview of ADSP-216x

processor functionality. For detailed design information on the

architecture and instruction set, refer to the ADSP-2100 Family

User’s Manual, Third Edition, available from Analog Devices.

EZ-ICE and EZ-LAB are registered trademarks of Analog Devices, Inc.

REV. 0

–3–

ADSP-216x

INSTRUCTION

REGISTER

PROGRAM

MEMORY

DATA

MEMORY

BOOT

ADDRESS

GENERATOR

DATA

SRAM

& ROM

SRAM

ADDRESS

GENERATOR

#2

ADDRESS

GENERATOR

#1

TIMER

PROGRAM

SEQUENCER

24

16

PMA BUS

DMA BUS

14

EXTERNAL

ADDRESS

BUS

MUX

14

PMD BUS

DMD BUS

PMA BUS

24

16

24

EXTERNAL

DATA

BUS

EXCHANGE

16

COMPANDING

CIRCUITRY

INPUT REGS

SHIFTER

INPUT REGS

ALU

MAC

OUTPUT REGS

16

TRANSMIT REG

RECEIVE REG

OUTPUT REGS

SERIAL

PORT 1

SERIAL

PORT 0

R BUS

5

Figure 1. ADSP-216x Block Diagram

Efficient data transfer is achieved with the use of five internal

buses:

external boot memory. Multiple programs can be selected and

loaded from the EPROM with no additional hardware.

•

Program Memory Address (PMA) Bus

Program Memory Data (PMD) Bus

Data Memory Address (DMA) Bus

Data Memory Data (DMD) Bus

Result (R) Bus

The data receive and transmit pins on SPORT1 (Serial Port 1)

can be alternatively configured as a general-purpose input flag

and output flag. You can use these pins for event signalling to

and from an external device.

A programmable interval timer can generate periodic interrupts.

A 16-bit count register (TCOUNT) is decremented every n

cycles, where n–1 is a scaling value stored in an 8-bit register

(TSCALE). When the value of the count register reaches zero,

an interrupt is generated and the count register is reloaded from

a 16-bit period register (TPERIOD).

The two address buses (PMA, DMA) share a single external

address bus, allowing memory to be expanded off-chip, and the

two data buses (PMD, DMD) share a single external data bus.

The BMS, DMS and PMS signals indicate which memory space

is using the external buses.

Program memory can store both instructions and data, permit-

ting the ADSP-216x to fetch two operands in a single cycle,

one from program memory and one from data memory. The

processor can fetch an operand from on-chip program memory

and the next instruction in the same cycle.

Serial Ports

The ADSP-216x processors include two synchronous serial

ports (SPORTs) for serial communications and multiprocessor

communication. All of the ADSP-216x processors have two

serial ports (SPORT0, SPORT1).

The memory interface supports slow memories and memory-

mapped peripherals with programmable wait state generation.

External devices can gain control of the processor’s buses with

the use of the bus request/grant signals (BR, BG).

The serial ports provide a complete synchronous serial interface

with optional companding in hardware. A wide variety of

framed or frameless data transmit and receive modes of opera-

tion are available. Each SPORT can generate an internal pro-

grammable serial clock or accept an external serial clock.

One bus grant execution mode (GO Mode) allows the ADSP-

216x to continue running from internal memory. A second

execution mode requires the processor to halt while buses are

granted.

Each serial port has a 5-pin interface consisting of the following

signals:

Signal Name

Function

Each ADSP-216x processor can respond to several different

interrupts. There can be up to three external interrupts,

configured as edge- or level-sensitive. Internal interrupts can be

generated by the timer and serial ports. There is also a master

RESET signal.

SCLK

RFS

TFS

DR

Serial Clock (I/O)

Receive Frame Synchronization (I/O)

Transmit Frame Synchronization (I/O)

Serial Data Receive

DT

Serial Data Transmit

Booting circuitry provides for loading on-chip program memory

automatically from byte-wide external memory. After reset,

three wait states are automatically generated. This allows, for

example, a 60 ns ADSP-2161 to use a 200 ns EPROM as

–4–

REV. 0

ADSP-216x

The ADSP-216x uses a vectored interrupt scheme: when an

interrupt is acknowledged, the processor shifts program control

to the interrupt vector address corresponding to the interrupt

received. Interrupts can be optionally nested so that a higher

priority interrupt can preempt the currently executing interrupt

service routine. Each interrupt vector location is four instruc-

tions in length so that simple service routines can be coded

entirely in this space. Longer service routines require an addi-

tional JUMP or CALL instruction.

The ADSP-216x serial ports offer the following capabilities:

Bidirectional—Each SPORT has a separate, double-buffered

transmit and receive function.

Flexible Clocking—Each SPORT can use an external serial

clock or generate its own clock internally.

Flexible Framing—The SPORTs have independent framing

for the transmit and receive functions; each function can run in

a frameless mode or with frame synchronization signals inter-

nally generated or externally generated; frame sync signals may

be active high or inverted, with either of two pulsewidths and

timings.

Individual interrupt requests are logically ANDed with the bits

in the IMASK register; the highest-priority unmasked interrupt

is then selected.

Different Word Lengths—Each SPORT supports serial data

word lengths from 3 to 16 bits.

The interrupt control register, ICNTL, allows the external

interrupts to be set as either edge- or level-sensitive. Depending

on Bit 4 in ICNTL, interrupt service routines can either be

nested (with higher priority interrupts taking precedence) or be

processed sequentially (with only one interrupt service active at

a time).

Companding in Hardware—Each SPORT provides optional

A-law and µ-law companding according to CCITT recommen-

dation G.711.

Flexible Interrupt Scheme—Receive and transmit functions

can generate a unique interrupt upon completion of a data word

transfer.

The interrupt force and clear register, IFC, is a write-only regis-

ter that contains a force bit and a clear bit for each interrupt.

When responding to an interrupt, the ASTAT, MSTAT and

IMASK status registers are pushed onto the status stack and

the PC counter is loaded with the appropriate vector address.

The status stack is seven levels deep to allow interrupt nesting.

The stack is automatically popped when a return from the inter-

rupt instruction is executed.

Autobuffering with Single-Cycle Overhead—Each SPORT

can automatically receive or transmit the contents of an entire

circular data buffer with only one overhead cycle per data word;

an interrupt is generated after the transfer of the entire buffer is

completed.

Multichannel Capability (SPORT0 Only)—SPORT0 pro-

vides a multichannel interface to selectively receive or transmit a

24-word or 32-word, time-division multiplexed serial bit stream;

this feature is especially useful for T1 or CEPT interfaces, or as

a network communication scheme for multiple processors.

Pin Definitions

Pin Function Descriptions show pin definitions for the ADSP-

216x processors. Any inputs not used must be tied to V_DD

.

SYSTEM INTERFACE

Alternate Configuration—SPORT1 can be alternatively

configured as two external interrupt inputs (IRQ0, IRQ1) and

the Flag In and Flag Out signals (FI, FO).

Figure 3 shows a typical system for the ADSP-216x with two

serial I/O devices, an optional external program and data

memory. A total of 12K words of data memory and 15K words

of program memory is addressable.

Interrupts

The ADSP-216x’s interrupt controller lets the processor re-

spond to interrupts with a minimum of overhead. Up to three

external interrupt input pins, IRQ0, IRQ1 and IRQ2, are pro-

vided. IRQ2 is always available as a dedicated pin; IRQ1 and

IRQ0 may be alternately configured as part of Serial Port 1. The

ADSP-216x also supports internal interrupts from the timer and

the serial ports. The interrupts are internally prioritized and

individually maskable (except for RESET which is nonmaskable).

The IRQx input pins can be programmed for either level- or

edge-sensitivity. The interrupt priorities for each ADSP-216x

processor are shown in Table II.

Programmable wait-state generation allows the processors to

easily interface to slow external memories.

The ADSP-216x processors also provide either: one external

interrupt (IRQ2) and two serial ports (SPORT0, SPORT1), or

three external interrupts (IRQ2, IRQ1, IRQ0) and one serial

port (SPORT0).

Clock Signals

The ADSP-216x processors’ CLKIN input may be driven by a

crystal or by a TTL-compatible external clock signal. The

CLKIN input may not be halted or changed in frequency during

operation, nor operated below the specified low frequency limit.

Table II. Interrupt Vector Addresses and Priority

Interrupt

If an external clock is used, it should be a TTL-compatible

signal running at the instruction rate. The signal should be

connected to the processor’s CLKIN input; in this case, the

XTAL input must be left unconnected.

ADSP-216x Interrupt Source

Vector Address

RESET Startup

0x0000

Because the ADSP-216x processors include an on-chip oscilla-

tor circuit, an external crystal may also be used. The crystal

should be connected across the CLKIN and XTAL pins, with

two capacitors connected as shown in Figure 2. A parallel-

resonant, fundamental frequency, microprocessor-grade crystal

should be used.

IRQ2 or Power-Down

SPORT0 Transmit

SPORT0 Receive

SPORT1 Transmit or IRQ1

SPORT1 Receive or IRQ0

Timer

0x0004 (High Priority)

0x0008

0x000C

0x0010

0x0014

0x0018 (Low Priority)

REV. 0

–5–

ADSP-216x

The power-up sequence is defined as the total time required for

the crystal oscillator circuit to stabilize after a valid V_DDis

applied to the processor and for the internal phase-locked loop

(PLL) to lock onto the specific crystal frequency. A minimum of

2000 t_CKcycles will ensure that the PLL has locked (this does

not, however, include the crystal oscillator start-up time).

During this power-up sequence the RESET signal should be

held low. On any subsequent resets, the RESET signal must

XTAL

CLKIN

CLKOUT

ADSP-216x

Figure 2. External Crystal Connections

meet the minimum pulsewidth specification, t_RSP

.

A clock output signal (CLKOUT) is generated by the processor,

synchronized to the processor’s internal cycles.

To generate the RESET signal, use either an RC circuit with an

external Schmidt trigger or a commercially available reset IC.

(Do not use only an RC circuit.)

Reset

The RESET signal initiates a complete reset of the ADSP-216x.

The RESET signal must be asserted when the chip is powered

up to assure proper initialization. If the RESET signal is applied

during initial power-up, it must be held long enough to allow

the processor’s internal clock to stabilize. If RESET is activated

at any time after power-up and the input clock frequency does

not change, the processor’s internal clock continues and does

not require this stabilization time.

The RESET input resets all internal stack pointers to the empty

stack condition, masks all interrupts, and clears the MSTAT

register. When RESET is released, the boot loading sequence is

performed (provided there is no pending bus request and the chip

is configured for booting, with MMAP = 0). The first instruction is

then fetched from internal program memory location 0x0000.

PIN FUNCTION DESCRIPTIONS

Name(s)

# of

Pins

Input/

Output

Function

Address

Data¹

14

24

O

I/O

Address outputs for program, data and boot memory.

Data I/O pins for program and data memories. Input only for

boot memory, with two MSBs used for boot memory addresses.

Unused data lines may be left floating.

Processor Reset Input

External Interrupt Request #2

External Bus Request Input

External Bus Grant Output

External Program Memory Select

External Data Memory Select

Boot Memory Select

External Memory Read Enable

External Memory Write Enable

Memory Map Select Input

External Clock or Quartz Crystal Input

Processor Clock Output

Power Supply Pins

RESET

1

2

1

I

O

I

IRQ2

BR²

BG

PMS

DMS

BMS

RD

WR

MMAP

CLKIN, XTAL

CLKOUT

V_DD

I

O

GND

Ground Pins

SPORT0

SPORT1

or Interrupts and Flags:

IRQ0 (RFS1)

IRQ1 (TFS1)

FI (DR1)

FO (DT1)

PWDACK³

PWDFLAG³

5

I/O

Serial Port 0 Pins (TFS0, RFS0, DT0, DR0, SCLK0)

Serial Port 1 Pins (TFS1, RFS1, DT1, DR1, SCLK1)

1

I

O

I

External Interrupt Request #0

External Interrupt Request #1

Flag Input Pin

Flag Output Pin

Indicates when the processor has entered power-down.

Low-to-High Transition of the Power-Down Flag. Input pin can

be used to terminate power-down.

NOTES

¹Unused data bus lines may be left floating.

²BR must be tied high (to V_DD) if not used.

³Only on ADSP-2165/ADSP-2166.

–6–

REV. 0

ADSP-216x

ADSP-2165/ADSP-2166

CLOCK OR

CRYSTAL

When MMAP = 0, on-chip program memory ROM occupies

12K words beginning at address 0x0000. Internal program

memory RAM occupies 1K words beginning at address 0x3000.

Off-chip program memory uses the 2K words beginning at

address 0x3800. The ADSP-2165/ADSP-2166 does not support

boot memory.

3

4

SCLK

RFS

TFS

DT

CLKIN

XTAL CLKOUT

V

GND

DD

SERIAL

DEVICE

(OPTIONAL)

SERIAL

PORT 0

RESET

IRQ2

BR

DR

When MMAP = 1, 2K words of off-chip program memory begin

at address 0x0000. 10K words of on-chip program memory

ROM at 0x800 to 0x2FFF, and the remainder 2K words of

program memory ROM is at 0x3800 to 0x3FFF. Internal pro-

gram memory RAM occupies 1K words at address 0x300 to

0x33FF.

ADSP-216x

SCLK

RFS OR IRQ0

TFS OR IRQ1

DT OR FO

BG

SERIAL

DEVICE

(OPTIONAL)

SERIAL

PORT 1

MMAP

DR OR FI

PMS

RD RW ADDRESS DATA DMS BMS

14

24

0x0000

2K

D23-8

EXTERNAL

0x07FF

0x0800

16

12K

؋

24

INTERNAL

ROM

A

D

A

D

CS

10K

؋

24

INTERNAL

ROM

OE

WE

PROGRAM

MEMORY

WE

DATA

MEMORY

&

0x2FFF

0x3000

0x2FFF

0x3000

(OPTIONAL)

PERIPHERALS

1K

؋

24 RAM

1K

؋

24 RAM

0x33FF

0x3400

0x33FF

0x3400

Figure 3. Basic System Configuration

Program Memory Interface

The on-chip program memory address bus (PMA) and on-chip

program memory data bus (PMD) are multiplexed with the on-

chip data memory buses (DMA, DMD), creating a single exter-

nal data bus and a single external address bus. The external

data bus is bidirectional and is 24 bits wide to allow instruction

fetches from external program memory. Program memory may

contain code and data.

RESERVED

0x37FF

0x3800

0x37FF

0x3800

2K

؋

24

INTERNAL

ROM

2K

؋

24

EXTERNAL

0x3FFF

MMAP = 0

MMAP = 1

Figure 4. ADSP-2165/ADSP-2166 Program Memory Maps

ADSP-2161/ADSP-2162

When MMAP = 0, on-chip program memory ROM occupies

8K words beginning at address 0x0000. Off-chip program

memory uses the remaining 8K words beginning at address

0x2000.

The external address bus is 14 bits wide. For the ADSP-216x,

these lines can directly address up to 16K words, of which 2K

are on-chip.

When MMAP = 1, 2K words of off-chip program memory begin

at address 0x0000. 6K words of on-chip program memory ROM

are at 0x0800 to 0x1FF0, and the remainder 2K words of pro-

gram memory ROM is at 0x3800 to 0x3FFF. An additional 6K

of off-chip program memory is at 0x2000 to 0x37FF.

The data lines are bidirectional. The program memory select

(PMS) signal indicates accesses to program memory and can be

used as a chip select signal. The write (WR) signal indicates a

write operation and is used as a write strobe. The read (RD)

signal indicates a read operation and is used as a read strobe or

output enable signal.

0x0000

2K

The ADSP-216x processors write data from their 16-bit regis-

ters to 24-bit program memory using the PX register to provide

the lower eight bits. When the processor reads 16-bit data from

24-bit program memory to a 16-bit data register, the lower eight

bits are placed in the PX register.

EXTERNAL

0x7FFF

0x0800

8K

INTERNAL

ROM

6K

INTERNAL

ROM

0x1FF0

RESERVED

The program memory interface can generate 0 to 7 wait states for

external memory devices; default is to 7 wait states after RESET.

0x1FFF

0x2000

0x1FFF

0x2000

6K

Program Memory Maps

EXTERNAL

8K

EXTERNAL

Program memory can be mapped in two ways, depending on the

state of the MMAP pin. Figure 4 shows the program memory

map for the ADSP-2165/ADSP-2166. Figures 5 and 6 show the

program memory maps for the ADSP-2161/ADSP-2162 and

ADSP-2163/ADSP-2164, respectively.

0x37FF

0x3800

2K

INTERNAL

ROM

0x3FFF

MMAP = 0

MMAP = 1

Figure 5. ADSP-2161/ADSP-2162 Program Memory Maps

REV. 0

–7–

ADSP-216x

ADSP-2163/ADSP-2164

When MMAP = 0, on-chip program memory ROM occupies

4K words beginning at address 0x0000. Off-chip program

memory uses the remaining 12K words beginning at address

0x1000.

ADDRESS (HEX)

0x0000

1K EXTERNAL

DWAIT0

0x0400

0x0800

1K EXTERNAL

DWAIT1

EXTERNAL

RAM

When MMAP = 1, 2K words of off-chip program memory begin

at address 0x0000. 2K words of on-chip program memory ROM

is at 0x0800 to 0x0FF0, and the remainder 2K words of pro-

gram memory ROM is at 0x3800 to 0x3FFF. An additional

10K of off-chip program memory is at 0x1000 to 0x37FF.

6K EXTERNAL

DWAIT2

0x2000

4K

؋

16 INTERNAL

0x0000

2K

EXTERNAL

4K

INTERNAL

ROM

INTERNAL

RAM

0x07FF

0x0800

0x3000

0x3FFF

2K

INTERNAL

ROM

4K

؋

16

MEMORY-MAPPED

REGISTERS

0x0FF0

RESERVED

& RESERVED

0x0FFF

0x1000

0x0FFF

0x1000

Figure 7. ADSP-2165/ADSP-2166 Data Memory Map

10K

EXTERNAL

ADSP-2161/ADSP-2162/ADSP-2163/ADSP-2164

12K

EXTERNAL

For the ADSP-2161/ADSP-2162/ADSP-2163/ADSP-2164, on-

chip data memory RAM resides in the 512 words beginning at

address 0x3800, also shown in Figure 8. Data memory locations

from 0x3A00 to the end of data memory at 0x3FFF are reserved.

Control and status registers for the system, timer, wait-state

configuration, and serial port operations are located in this

region of memory.

0x37FF

0x3800

2K

INTERNAL

ROM

0x3FFF

MMAP = 0

MMAP = 1

Figure 6. ADSP-2163/ADSP-2164 Program Memory Maps

Data Memory Interface

The data memory address bus (DMA) is 14 bits wide. The

bidirectional external data bus is 24 bits wide, with the upper 16

bits used for data memory data (DMD) transfers.

ADDRESS (HEX)

0x0000

1K EXTERNAL

DWAIT0

0x0400

The data memory select (DMS) signal indicates access to data

memory and can be used as a chip select signal. The write (WR)

signal indicates a write operation and can be used as a write

strobe. The read (RD) signal indicates a read operation and can

be used as a read strobe or output enable signal.

1K EXTERNAL

DWAIT1

0x0800

EXTERNAL

10K EXTERNAL

RAM

DWAIT2

The ADSP-216x processors support memory-mapped I/O, with

the peripherals memory-mapped into the data memory address

space and accessed by the processor in the same manner as data

memory.

0x3000

1K EXTERNAL

DWAIT3

0x3400

1K EXTERNAL

DWAIT4

Data Memory Map

0x3800

512

For the ADSP-2165/ADSP-2166, on-chip data memory RAM

resides in the 4K words beginning at address 0x2000, as shown

in Figure 7. Data memory locations from 0x3000 to the end of

data memory at 0x3FFF are reserved. Control and status regis-

ters for the system, timer, wait-state configuration, and serial port

operations are located in this region of memory.

ADSP-2161/62/63/64

0x3A00

INTERNAL

RAM

0x3C00

0x3FFF

MEMORY-MAPPED

CONTROL REGISTERS

& RESERVED

The remaining 8K of data memory is located off-chip. This

external data memory is divided into three zones, each associ-

ated with its own wait-state generator. This allows slower pe-

ripherals to be memory-mapped into data memory for which

wait states are specified. By mapping peripherals into different

zones, you can accommodate peripherals with different wait-

state requirements. All zones default to 7 wait states after

RESET.

Figure 8. ADSP-2161/ADSP-2162/ADSP-2163/ADSP-2164

Data Memory Map

The remaining 14K of data memory is located off-chip. This

external data memory is divided into five zones, each associated

with its own wait-state generator. This allows slower peripherals

to be memory-mapped into data memory for which wait states

are specified. By mapping peripherals into different zones, you

can accommodate peripherals with different wait-state require-

ments. All zones default to seven wait states after RESET.

–8–

REV. 0

ADSP-216x

Bus Interface

•

Low-to-high transition of the power-down flag input pin

(PWDFLAG) can be used to terminate power-down.

The ADSP-216x processors can relinquish control of their data

and address buses to an external device. When the external

device requires control of the buses, it asserts the bus request

signal (BR). If the ADSP-216x is not performing an external

memory access, it responds to the active BR input in the next

cycle by:

The RESET pin also can also be used to terminate

power-down.

Power-Down Control

Several parameters of power-down operation can be controlled

through control bits of the “power-down/sportl autobuffer con-

trol register.” This control register is memory-mapped at loca-

tion 0x3FEF and the power-down control bits are as follows:

•

Three-stating the data and address buses and the PMS,

DMS, BMS, RD, WR output drivers,

•

Asserting the bus grant (BG) signal, and halting program

execution.

bit[15] xtal: xtal pin disable during power-down

1 = disabled, 0 = enable (default)

If the Go mode is set, however, the ADSP-216x will not halt

program execution until it encounters an instruction that

requires an external memory access.

bit[14] pwdflag: (read only )

when pwdena = 1, the value of bit [14] pwdflag is equal to the

status of the pwdflag input pin.

If the ADSP-216x is performing an external memory access

when the external device asserts the BR signal, it will not three-

state the memory interfaces or assert the BG signal until the

cycle after the access completes (up to eight cycles later depend-

ing on the number of wait states). The instruction does not need

to be completed when the bus is granted; the ADSP-21xx will

grant the bus between two memory accesses if an instruction

requires more than one external memory access.

when pwdena = 0, the value of bit [14] pwdflag is equal to 0.

bit[13] pwdena: power-down enable

1 = enable, 0 = disable (default)

if pwdena is set to 0, then the output pin PWDACK is driven

low and the input pin PWDFLAG is disabled

Note: It is not recommended that power-down enable be set or

cleared during an IRQ2 interrupt.

When the BR signal is released, the processor releases the BG

signal, re-enables the output drivers and continues program

execution from the point at which it stopped.

bit[12] pucr: power-up context reset

1 = soft reset, 0 = resume execution (default)

Entering Power-Down

The bus request feature operates at all times, including when the

processor is booting and when RESET is active. If this feature is

not used, the BR input should be tied high (to V_DD).

The power-down sequence is defined as follows:

•

Enable power-down logic by setting the pwdena bit in the

power-down/sportl autobuffer control register.

Note: In order to power-down, the PWDENA bit must be set

before the IRQ2 interrupt is initiated.

POWER-DOWN

The ADSP-2165/ADSP-2166 processors have a low power

feature that lets the processor enter a very low power dormant

state through hardware or software control. A list of power-

down features follows:

•

Initiate the power-down sequence by generating an IRQ2

interrupt either externally or by software use of the IFC

register.

•

Processor registers and on-chip memory contents are main-

tained during power-down.

•

The processor vectors to the IRQ2 interrupt vector located at

0x0004.

Power-down mode holds the processor in CMOS standby

with a maximum current of less than 100 µA in some modes.

Any number of housekeeping instructions, starting at loca-

tion 0x0004 can be executed prior to the processor entering

the power-down mode.

Support for an externally generated TTL or CMOS proces-

sor clock. The external clock can continue running during

power-down without affecting the lowest power rating.

•

The processor enters the power-down mode when the pro-

cessor executes an IDLE instruction while executing the

IRQ2 interrupt routine.

•

Support for crystal operation includes disabling the oscillator

to save power. (The processor automatically waits 4096

CLKIN cycles for the crystal oscillator to start and stabilize).

Notes:

•

If an RTI instruction is executed before the processor en-

When power-down mode is enabled, powering down of the

processor can be initiated either by externally generated

IRQ2 interrupt or by using the IRQ2 force bit in the IFC

register.

counter an IDLE instruction, then the processor returns

from the IRQ2 interrupt and the power-down sequence is

aborted.

•

The user can differentiate between a “normal” IRQ2 inter-

rupt and a “power-down” IRQ2 interrupt by resetting the

PWDFLAG pin and checking the status of this pin by testing

the PWDFLAG bit in the power-down/SPORT1 autobuffer

control register located at DM[0x3FEF].

•

Power-Down Acknowledge Pin (PWDACK) indicates when

the processor has entered power-down.

Interrupt support allows an unlimited number of instructions

to be executed before optionally powering down.

Context clear/save control allows the processor to continue

where it left off or start with a clean context when leaving the

power-down state.

REV. 0

–9–

ADSP-216x

Exiting Power-Down

ADSP-216x Prototyping

The power-down mode can be exited with the use of the

PWDFLAG or RESET pin. Applying a low-to-high transition to

the PWDFLAG pin takes the processor out of power-down

mode. In this case, a delay of 4096 cycles is automatically in-

duced by the processor. Also, depending on the status of the

power-up context reset bit (pucr), the processor either

You can prototype your ADSP-216x system with either ADSP-

2101 or ADSP-2103 RAM-based processors. When code is fully

developed and debugged, it can be submitted to Analog Devices

for conversion into an ADSP-216x ROM product.

The ADSP-2101 EZ-ICE emulator can be used for development

of ADSP-216x systems. For the 3.3 V ADSP-2162/ADSP-2164

and ADSP-2166, a voltage converter interface board provides

3.3 V emulation.

1) continues to execute instructions following the IDLE instruc-

tion that caused the power-down. A RTI instruction is re-

quired to pass control back to the main routine (pucr = 0)

Additional overlay memory is used for emulation of ADSP-

2161/ADSP-2162 systems. It should be noted that due to the

use of off-chip overlay memory to emulate the ADSP-2161/

ADSP-2162, a performance loss may be experienced when both

executing instructions and fetching program memory data from

the off-chip overlay memory in the same cycle. This can be

overcome by locating program memory data in on-chip memory.

or

2) resumes operation from power-down by clearing the PC,

STATUS, LOOP and CNTR stack. The IMASK and

ASTAT registers are set to 0 and the SSTAT goes to 0x55.

The processor then starts executing instructions from the

address zero (pucr = 1).

Ordering Procedure for ADSP-216x ROM Processors

To place an order for a custom ROM-coded ADSP-2161,

ADSP-2162, ADSP-2163, ADSP-2164 , ADSP-2165 or ADSP-

2166 processor, you must:

In the case where the power-down mode is exited by asserting

the RESET pin, the processor state is reset and instruction are

executed from address 0x0000. The RESET pin in this case

must be held low long enough for the external crystal (if any)

and the on-chip PLL to stabilize and lock.

1. Complete the following forms contained in the ADSP ROM

Ordering Package, available from your Analog Devices sales

representative:

ADSP-216x ROM Specification Form

ROM Release Agreement

Low Power IDLE Instruction

The IDLE instruction places the ADSP-216x processor in low

power state in which it waits for an interrupt. When an interrupt

occurs, it is serviced and execution continues with instruction

following IDLE. Typically this next instruction will be a JUMP

back to the IDLE instruction. This implements a low power

standby loop.

ROM NRE Agreement & Minimum Quantity Order (MQO)

Acceptance Agreement for Preproduction ROM Products

2. Return the forms to Analog Devices along with two copies of the

Memory Image File (.EXE file) of your ROM code. The files must

be supplied on two 3.5" or 5.25" floppy disks for the IBM PC

(DOS 2.01 or higher).

The IDLE n instruction is a special version of IDLE that slows

the processor’s internal clock signal to further reduce power

consumption. The reduced clock frequency, a programmable

fraction of the normal clock rate, is specified by a selectable

divisor, n, given in the IDLE instruction. The syntax of the

instruction is:

3. Place a purchase order with Analog Devices for nonrecurring

engineering changes (NRE) associated with ROM product

development.

IDLE n;

After this information is received, it is entered into Analog

Devices’ ROM Manager System which assigns a custom ROM

model number to the product. This model number will be

branded on all prototype and production units manufactured to

these specifications.

where n = 16, 32, 64 or 128.

The instruction leaves the chip in an idle state, operating at the

slower rate. While it is in this state, the processor’s other inter-

nal clock signals, such as SCLK, CLKOUT, and the timer

clock, are reduced by the same ratio. Upon receipt of an en-

abled interrupt, the processor will stay in the IDLE state for up

to a maximum of n CLKIN cycles, where n is the divisor speci-

fied in the instruction, before resuming normal operation.

To minimize the risk of code being altered during this process,

Analog Devices verifies that the .EXE files on both floppy disks

are identical, and recalculates the checksums for the .EXE file

entered into the ROM Manager System. The checksum data, in

the form of a ROM Memory Map, a hard copy of the .EXE file,

and a ROM Data Verification form are returned to you for

inspection.

When the IDLE n instruction is used, it slows the processor’s

internal clock and thus its response time to incoming interrupts–

the 1-cycle response time of the standard IDLE state is increased

by n, the clock divisor. When an enabled interrupt is received,

the ADSP-216x will remain in the IDLE state for up to a maxi-

mum of n CLKIN cycles (where n = 16, 32, 64 or 128) before

resuming normal operation.

A signed ROM Verification Form and a purchase order for

production units are required prior to any product being manu-

factured. Prototype units may be applied toward the minimum

order quantity.

Upon completion of prototype manufacture, Analog Devices

will ship prototype units and a delivery schedule update for

production units. An invoice against your purchase order for the

NRE charges is issued at this time.

When the IDLE n instruction is used in systems that have an

externally generated serial clock (SCLK), the serial clock rate

may be faster than the processor’s reduced internal clock rate.

Under these conditions, interrupts must not be generated at a

faster rate than can be serviced, due to the additional time the

processor takes to come out of the IDLE state (a maximum of n

CLKIN cycles).

There is a charge for each ROM mask generated and a mini-

mum order quantity. Consult your sales representative for de-

tails. A separate order must be placed for parts of a specific

package type, temperature range, and speed grade.

–10–

REV. 0

ADSP-216x

Instruction Set

parallelism. There are five basic categories of instructions: data

move instructions, computational instructions, multifunction

instructions, program flow control instructions and miscella-

neous instructions. Multifunction instructions perform one or

two data moves and a computation.

The ADSP-216x assembly language uses an algebraic syntax for

ease of coding and readability. The sources and destinations of

computations and data movements are written explicitly in each

assembly statement, eliminating cryptic assembler mnemonics.

Every instruction assembles into a single 24-bit word and executes

in a single cycle. The instructions encompass a wide variety of

instruction types along with a high degree of operational

The instruction set is summarized below. The ADSP-2100

Family Users Manual contains a complete reference to the

instruction set.

ALU Instructions

[IF cond]

AR|AF

=

xop + yop [+ C] ;

xop – yop [+ C– 1] ;

yop – xop [+ C– 1] ;

xop AND yop ;

xop OR yop ;

xop XOR yop ;

PASS xop ;

– xop ;

NOT xop ;

ABS xop ;

yop + 1 ;

Add/Add with Carry

Subtract X – Y/Subtract X – Y with Borrow

Subtract Y – X/Subtract Y – X with Borrow

AND

OR

XOR

Pass, Clear

Negate

NOT

Absolute Value

Increment

Decrement

Divide

yop – 1 ;

DIVS yop, xop ;

DIVQ xop ;

MAC Instructions

[IF cond]

MR|MF =

xop _*yop ;

MR + xop _*yop ;

MR – xop _*yop ;

MR ;

Multiply

=

Multiply/Accumulate

Multiply/Subtract

Transfer MR

0 ;

Clear

IF MV SAT MR ;

Conditional MR Saturation

Shifter Instructions

[IF cond]

SR = [SR OR] ASHIFT xop ;

SR = [SR OR] LSHIFT xop ;

SR = [SR OR] ASHIFT xop BY <exp>;

SR = [SR OR] LSHIFT xop BY <exp>;

SE = EXP xop ;

Arithmetic Shift

Logical Shift

Arithmetic Shift Immediate

Logical Shift Immediate

Derive Exponent

Block Exponent Adjust

Normalize

[IF cond]

SB = EXPADJ xop

;

SR = [SR OR] NORM xop ;

Data Move Instructions

reg = reg ;

reg = <data> ;

Register-to-Register Move

Load Register Immediate

reg = DM (<addr>) ;

dreg = DM (Ix , My) ;

dreg = PM (Ix , My) ;

DM (<addr>) = reg ;

DM (Ix , My) = dreg ;

PM (Ix , My) = dreg ;

Data Memory Read (Direct Address)

Data Memory Read (Indirect Address)

Program Memory Read (Indirect Address)

Data Memory Write (Direct Address)

Data Memory Write (Indirect Address)

Program Memory Write (Indirect Address)

Multifunction Instructions

<ALU>|<MAC>|<SHIFT> , dreg = dreg ;

Computation with Register-to-Register Move

Computation with Memory Read

Computation with Memory Write

Data & Program Memory Read

ALU/MAC with Data & Program Memory Read

<ALU>|<MAC>|<SHIFT> , dreg = DM (Ix , My) ;

<ALU>|<MAC>|<SHIFT> , dreg = PM (Ix , My) ;

DM (Ix , My) = dreg , <ALU>|<MAC>|<SHIFT> ;

PM (Ix , My) = dreg , <ALU>|<MAC>|<SHIFT> ;

dreg = DM (Ix , My) , dreg = PM (Ix , My) ;

<ALU>|<MAC> , dreg = DM (Ix , My) , dreg = PM (Ix , My) ;

REV. 0

–11–

ADSP-216x

Program Flow Instructions

DO <addr> [UNTIL term] ;

[IF cond] JUMP (Ix) ;

Do Until Loop

Jump

[IF cond] JUMP <addr>;

[IF cond] CALL (Ix) ;

Call Subroutine

[IF cond] CALL <addr>;

IF [NOT ] FLAG_IN

JUMP <addr>;

CALL <addr>;

Jump/Call on Flag In Pin

[IF cond] SET|RESET|TOGGLE

[IF cond] RTS ;

[IF cond] RTI ;

FLAG_OUT [, ...] ;

Modify Flag Out Pin

Return from Subroutine

Return from Interrupt Service Routine

Idle

IDLE [(n)] ;

Miscellaneous Instructions

NOP ;

MODIFY (Ix , My);

No Operation

Modify Address Register

Stack Control

[PUSH STS] [, POP CNTR] [, POP PC] [, POP LOOP] ;

ENA|DIS

SEC_REG [, ...] ;

BIT_REV

Mode Control

AV_LATCH

AR_SAT

M_MODE

TIMER

G_MODE

Notation Conventions

Ix

My

Index registers for indirect addressing

Modify registers for indirect addressing

Immediate data value

Immediate address value

Exponent (shift value) in shift immediate instructions (8-bit signed number)

Any ALU instruction (except divide)

<data>

<addr>

<exp>

<ALU>

<MAC>

<SHIFT>

cond

term

Any multiply-accumulate instruction

Any shift instruction (except shift immediate)

Condition code for conditional instruction

Termination code for DO UNTIL loop

Data register (of ALU, MAC, or Shifter)

Any register (including dregs)

dreg

reg

;

,

[

A semicolon terminates the instruction

Commas separate multiple operations of a single instruction

Optional part of instruction

]

[, ...]

option1 | option2

Optional, multiple operations of an instruction

List of options; choose one.

Assembly Code Example

The following example is a code fragment that performs the filter tap update for an adaptive filter based on a least-mean-squared

algorithm. Notice that the computations in the instructions are written like algebraic equations.

MF=MX0 MY1(RND), MX0=DM(I2,M1);

{MF=error beta}

*

MR=MX0 MF(RND), AY0=PM(I6,M5);

*

DO adapt UNTIL CE;

AR=MR1+AY0, MX0=DM(I2,M1), AY0=PM(I6,M7);

adapt:

PM(I6,M6)=AR, MR=MX0 MF(RND);

*

MODIFY(I2,M3);

MODIFY(I6,M7);

{Point to oldest data}

{Point to start of data}

–12–

REV. 0

ADSP-216x

SPECIFICATIONS

ADSP-2161/ADSP-2163/ADSP-2165–RECOMMENDED OPERATING CONDITIONS

K Grade

B Grade

Max

Parameter

Min

Max

Min

Unit

V_DD

T_AMB

Supply Voltage

Ambient Operating Temperature

4.50

0

5.50

+70

4.50

–40

5.50

+85

V

°C

See “Environmental Conditions” for information on thermal specifications.

ELECTRICAL CHARACTERISTICS

Parameter

Test Conditions

Min

Max

Unit

V_IH

V_IL

Hi-Level Input Voltage^{1, 2}

@ V_DD= max

2.0

2.2

V

µA

pF

Hi-Level CLKIN and Reset Voltage @ V_DD= max

Lo-Level Input Voltage^{1, 3}

@ V_DD= min

0.8

V_OH

Hi-Level Output Voltage^{1, 4, 5}

@ V_DD= min, I_OH= –0.5 mA

@ V_DD= min, I_OH= –100 µA⁶

@ V_DD= min, I_OL= 2 mA

2.4

V_DD– 0.3

V_OL

I_IH

I_IL

I_OZH

I_OZL

C_I

Lo-Level Output Voltage^{1, 4, 5}

Hi-Level Input Current³

0.4

10

8

@ V_DD= max, V_IN= V_DDmax

@ V_DD= max, V_IN= 0 V

Lo-Level Input Current³

Three-State Leakage Current⁷

Input Pin Capacitance^{3, 6, 9}

Output Pin Capacitance^{6, 7, 9, 10}

@ V_DD= max, V_IN= V_DDmax⁸

@ V_DD= max, V_IN= 0 V⁸

@ V_IN= 2.5 V, f_IN= 1.0 MHz, T_AMB= 25°C

C_O

8

NOTES

¹Bidirectional pins: D0–D23, SCLK1, RFS1, TFS1, SCLK0, RFS0, TFS0.

²Input-only pins: RESET, IRQ2, BR, MMAP, DR1, DR0.

³Input-only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR1, DR0.

⁴Output pins: BG, PMS, DMS, BMS, RD, WR, A0–A13, CLKOUT, DT1, DT0.

⁵Although specified for TTL outputs, all ADSP-21xx outputs are CMOS-compatible and will drive to V_DDand GND, assuming no dc loads.

⁶Guaranteed but not tested.

⁷Three-stateable pins: A0–A13, D0–D23, PMS, DMS, BMS, RD, WR, DT1, SCLK1, RFS1, TFS1, DT0, SCLK0, RFS0, TFS0.

⁸0 V on BR, CLKIN Active (to force three-state condition).

⁹Applies to PLCC, MQFP package types.

¹⁰Output pin capacitance is the capacitive load for any three-stated output pin.

Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Input Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to V_DD+ 0.3 V

Output Voltage Swing . . . . . . . . . . . . . –0.3 V to V_DD+ 0.3 V

Operating Temperature Range (Ambient) . . . –40°C to +85°C

(No Extended Temperature Range)

Storage Temperature Range . . . . . . . . . . . . –65ºC to +150ºC

Lead Temperature (10 sec) PGA . . . . . . . . . . . . . . . . .+300ºC

Lead Temperature (5 sec) PLCC, MQFP, TQFP . . . .+280ºC

*Stresses greater than those listed above may cause permanent damage to the

device. These are stress ratings only; functional operation of the device at these or

any other conditions greater than those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

WARNING!

accumulate on the human body and test equipment and can discharge without detection. Although

the ADSP-216x features proprietary ESD protection circuitry, permanent damage may occur on

devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

ESD SENSITIVE DEVICE

REV. 0

–13–

ADSP-216x

SPECIFICATIONS

ADSP-2161/ADSP-2163/ADSP-2165–SUPPLY CURRENT AND POWER

Parameter

I_DD

Test Conditions

Min

Max

Unit

Supply Current (Dynamic)¹

@ V_DD= max, t_CK= 40 ns²

@ V_DD= max, t_CK= 50 ns²

@ V_DD= max, t_CK= 60 ns²

@ V_DD= max, t_CK= 40 ns

@ V_DD= max, t_CK= 50 ns

@ V_DD= max, t_CK= 60 ns

38

31

27

12

11

10

mA

I_DD

Supply Current (Idle)^{1, 3}

NOTES

¹Current reflects device operating with no output loads.

²V_IN= 0.4 V and 2.4 V.

³Idle refers to ADSP-21xx state of operation during execution of IDLE instruction. Deasserted pins are driven to either V _DDor GND.

For typical supply current (internal power dissipation) figures, see Figure 9.

Specifications subject to change without notice.

1

IDD DYNAMIC

220

205mW

200

180

V

= 5.5V

DD

160

140

120

157mW

129mW

V

= 5.0V

118mW

DD

100

80

100mW

74mW

V

= 4.5V

DD

60

10.00

13.83

20.00

25.00

30.00

FREQUENCY – MHz

1,2

3

IDD IDLE n MODES

IDD IDLE

70

65

60

64mW

60

50

40

V

= 5.5V

DD

IDD IDLE

51mW

55

50

45

40

49mW

35mW

51mW

V

= 5.0

DD

38mW

28mW

30

20

V

= 4.5V

DD

IDLE 16

43mW

42mW

41mW

40mW

IDLE 128

10

0

35

30

10.00

13.83

20.00

25.00

30.00

10.00

13.83

20.00

25.00

30.00

FREQUENCY – MHz

VALID FOR ALL TEMPERATURE GRADES.

1

POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.

IDLE REFERS TO ADSP-216x OPERATION DURING EXECUTION OF IDLE INSTRUCTION.

2

DEASSERTED PINS ARE DRIVEN TO EITHER V OR GND.

DD

3

MAXIMUM POWER DISSIPATION AT V = 5.5V DURING EXECUTION OF IDLE n INSTRUCTION.

DD

Figure 9. ADSP-2161/ADSP-2163/ADSP-2165 (Typical) vs. Frequency

–14–

REV. 0

ADSP-216x

ADSP-2161/ADSP-2163/ADSP-2165

POWER DISSIPATION EXAMPLE

CAPACITIVE LOADING

To determine total power dissipation in a specific application,

the following equation should be applied for each output:

Figures 10 and 11 show capacitive loading characteristics for the

ADSP-2161/ADSP-2163/ADSP-2165.

C × V_DD²× f

8

7

6

C = load capacitance, f = output switching frequency.

Example:

In an ADSP-2161 application where external data memory is

used and no other outputs are active, power dissipation is calcu-

lated as follows:

V

= 4.5V

DD

5

Assumptions:

4

3

•

External data memory is accessed every cycle with 50% of

the address pins switching.

2

External data memory writes occur every other cycle with

50% of the data pins switching.

1

0

•

Each address and data pin has a 10 pF total load at the pin.

The application operates at V_DD= 5.0 V and t_CK= 50 ns.

0

25

50

75

100

125

150

175

C

– pF

L

Figure 10. Typical Output Rise Time vs. Load Capacitance, C_L

(at Maximum Ambient Operating Temperature)

Total Power Dissipation = P_INT+ (C × V_DD²× f)

P

_INT= internal power dissipation (from Figure 9).

2

5

4

3

(C × V_DD× f) is calculated for each output:

# of

2

Output

Pins

؋

C

؋

V_DD

؋

f

V

= 4.5V

DD

Address, DMS 8

× 10 pF × 5²V × 20 MHz =40.0 mW

× 10 pF × 5²V × 10 MHz =22.5 mW

× 10 pF × 5²V × 10 MHz = 2.5 mW

× 10 pF × 5²V × 20 MHz = 5.0 mW

2

1

Data, WR

RD

CLKOUT

9

1

0

70.0 mW

–1

–2

–3

Total power dissipation for this example = P_INT+ 70.0 mW.

ENVIRONMENTAL CONDITIONS

0

25

50

75

100

– pF

125

150

175

Ambient Temperature Rating:

C

L

T

_AMB= T_CASE– (PD × θ_CA)

Figure 11. Typical Output Valid Delay or Hold vs. Load

Capacitance, C_L(at Maximum Ambient Operating

Temperature)

T_CASE= Case Temperature in °C

PD = Power Dissipation in W

θ_CA= Thermal Resistance (Case-to-Ambient)

θ_JA= Thermal Resistance (Junction-to-Ambient)

θ_JC= Thermal Resistance (Junction-to-Case)

Package

␪

CA

JA

JC

PLCC

MQFP

27°C/W

60°C/W

16°C/W

18°C/W

11°C/W

42°C/W

REV. 0

–15–

ADSP-216x

SPECIFICATIONS

ADSP-2161/ADSP-2163/ADSP-2165

Figure 12 shows voltage reference levels for ac measurements.

TEST CONDITIONS

Output Enable Time

Output pins are considered to be enabled when they have made

a transition from a high-impedance state to when they start

driving. The output enable time (t_ENA) is the interval from when

a reference signal reaches a high or low voltage level to when the

output has reached a specified high or low trip point, as shown

in Figure 13. If multiple pins (such as the data bus) are enabled,

the measurement value is that of the first pin to start driving.

3.0V

1.5V

0.0V

INPUT

2.0V

1.5V

0.8V

OUTPUT

REFERENCE

SIGNAL

Figure 12. Voltage Reference Levels for AC Measurements

(Except Output Enable/Disable)

t_MEASURED

t_DIS

t_ENA

V

OH

(MEASURED)

OH

Output Disable Time

(MEASURED)

Output pins are considered to be disabled when they have

stopped driving and started a transition from the measured out-

put high or low voltage to a high impedance state. The output

disable time (t_DIS) is the difference of t_MEASUREDand t_DECAY, as

shown in Figure 13. The time t_MEASUREDis the interval from

when a reference signal reaches a high or low voltage level to

when the output voltages have changed by 0.5 V from the mea-

sured output high or low voltage.

V

(MEASURED) – 0.5V

(MEASURED) +0.5V

2.0V

1.0V

OH

OUTPUT

OL

V

OL

t_DECAY

(MEASURED)

OUTPUT STARTS

DRIVING

OUTPUT STOPS

DRIVING

HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE

THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.

Figure 13. Output Enable/Disable

The decay time, t_DECAY, is dependent on the capacitative load,

C_L, and the current load, i_L, on the output pin. It can be ap-

proximated by the following equation:

I

OL

C_L×0.5V

t_DECAY

=

i_L

TO

OUTPUT

from which

+1.5V

t_DIS= t_MEASURED– t_DECAY

50pF

is calculated. If multiple pins (such as the data bus) are disabled,

the measurement value is that of the last pin to stop driving.

I

OH

Figure 14. Equivalent Device Loading for AC

Measurements (Except Output Enable/Disable)

–16–

REV. 0

ADSP-216x

ADSP-2162/ADSP-2164/ADSP-2166–RECOMMENDED OPERATING CONDITIONS

K Grade

Min

B Grade

Parameter

Max

Min

Max

Unit

V_DD

T_AMB

Supply Voltage

Ambient Operating Temperature

3.00

0

3.60

+70

3.00

–40

3.60

+85

V

°C

See “Environmental Conditions” for information on thermal specifications.

ELECTRICAL CHARACTERISTICS

Parameter

Test Conditions

Min

Max

Unit

V_IH

V_IL

V_OH

V_OL

I_IH

Hi-Level Input Voltage^{1, 2}

@ V_DD= max

@ V_DD= min

2.0

2.2

V

Hi-Level CLKIN and Reset Voltage

Lo-Level Input Voltage^{1, 3}

0.4

Hi-Level Output Voltage^{2, 3, 4}

Lo-Level Output Voltage^{2, 3, 4}

Hi-Level Input Current³

@ V_DD= min, I_OH= –0.5 mA⁴

2.4

@ V_DD= min, I_OL= 2 mA⁴

0.4

10

8

V

@ V_DD= max, V_IN= V_DDmax

@ V_DD= max, V_IN= 0 V

µA

pF

I_IL

Lo-Level Input Current³

I_OZH

I_OZL

C_I

Three-State Leakage Current⁵

Input Pin Capacitance^{1, 7, 8}

Output Pin Capacitance^{2, 7, 8, 9}

@ V_DD= max, V_IN= V_DDmax⁶

@ V_DD= max, V_IN= 0 V⁶

@ V_IN= 2.5 V, f_IN= 1.0 MHz, T_AMB= 25°C

C_O

8

NOTES

¹Input-only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR1, DR0.

²Bidirectional pins: D0–D23, SCLK1, RFS1, TFS1, SCLK0, RFS0, TFS0.

³Output pins: BG, PMS, DMS, BMS, RD, WR, A0–A13, CLKOUT, DT1, DT0.

⁴All ADSP-2162, ADSP-2164 and ADSP-2166 outputs are CMOS and will drive to V _DDand GND with no dc loads.

⁵Three-stateable pins: A0–A13, D0–D23, PMS, DMS, BMS, RD, WR, DT1, SCLK1, RFS1, TFS1, DT0, SCLK0, RFS0, TFS0.

⁶0 V on BR, CLKIN Active (to force three-state condition).

⁷Guaranteed but not tested.

⁸Applies to PLCC and MQFP package types.

⁹Output pin capacitance is the capacitive load for any three-stated output pin.

Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.5 V

Input Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to V_DD+ 0.3 V

Output Voltage Swing . . . . . . . . . . . . . –0.3 V to V_DD+ 0.3 V

Operating Temperature Range (Ambient) . . . –40ºC to +85ºC

Storage Temperature Range . . . . . . . . . . . . –65ºC to +150ºC

Lead Temperature (5 sec) PLCC, MQFP . . . . . . . . . . +280ºC

*Stresses greater than those listed above may cause permanent damage to the

device. These are stress ratings only, and functional operation of the device at

these or any other conditions greater than those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

REV. 0

–17–

ADSP-216x

SPECIFICATIONS

ADSP-2162/ADSP-2164/ADSP-2166–SUPPLY CURRENT AND POWER

Parameter

Test Conditions

Min

Max

Unit

I_DD

Supply Current (Dynamic)¹

@ V_DD= max, t_CK= 60 ns²

@ V_DD= max, t_CK= 76.9 ns

@ V_DD= max, t_CK= 97.6 ns

@ V_DD= max, t_CK= 60 ns

@ V_DD= max, t_CK= 76.9 ns

@ V_DD= max, t_CK= 97.6 ns

16

15

14

5

4

mA

I_DD

Supply Current (Idle)^{1, 3}

NOTES

¹Current reflects device operating with no output loads.

²V_IN= 0.4 V and 2.4 V.

³Idle refers to ADSP-216x state of operation during execution of IDLE instruction. Deasserted pins are driven to either V_DDor GND.

For typical supply current (internal power dissipation) figures, see Figure 15.

Specifications subject to change without notice.

1,2

IDD DYNAMIC

50

48mW

45

V

= 3.6V

DD

V

= 3.30V

37mW

DD

40

35

30

29mW

25

20

24mW

V

= 3.0V

DD

19mW

15mW

15

10

5

0

5.00

7.00

10.00

13.83

15.00

FREQUENCY – MHz

1

3

IDD IDLE

= 3.6V

IDD IDLE n MODES

14

13mW

12

10

8

12

10

8

V

DD

IDD IDLE

10mW

V

= 3.30V

9mW

DD

9mW

8mW

IDLE 16

7mW

6mW

6

4

6mW

5mW

6

4

V

= 3.0V

DD

5mW

4mW

IDLE 128

2

0

2

0

5.00

7.00

10.00

13.83

15.00

5.00

7.00

10.00

13.83

15.00

FREQUENCY – MHz

VALID FOR ALL TEMPERATURE GRADES.

1

POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.

2

IDLE REFERS TO ADSP-216x OPERATION DURING EXECUTION OF IDLE INSTRUCTION.

DEASSERTED PINS ARE DRIVEN TO EITHER V OR GND.

DD

3

MAXIMUM POWER DISSIPATION AT V = 3.6V DURING EXECUTION OF IDLE n INSTRUCTION.

DD

Figure 15. ADSP-2162 Power (Typical) vs. Frequency)

–18–

REV. 0

ADSP-216x

ADSP-2162/ADSP-2164/ADSP-2166

CAPACITIVE LOADING

POWER DISSIPATION EXAMPLE

Figures 16 and 17 show capacitive loading characteristics for

the ADSP-2162 and ADSP-2164.

To determine total power dissipation in a specific application,

the following equation should be applied for each output:

2

C × V_DD× f

35

30

25

20

C = load capacitance, f = output switching frequency.

Example:

In an ADSP-2162 application where external data memory is

used and no other outputs are active, power dissipation is calcu-

lated as follows:

V

= 3.0V

DD

Assumptions:

15

10

5

• External data memory is accessed every cycle with 50% of the

address pins switching.

• External data memory writes occur every other cycle with

50% of the data pins switching.

0

• Each address and data pin has a 10 pF total load at the pin.

• The application operates at V_DD= 3.3 V and t_CK= 100 ns.

0

25

50

75

100

– pF

125

150

175

C

L

Figure 16. Typical Output Rise Time vs. Load Capaci-

tance, C_L(at Maximum Ambient Operating Temperature)

Total Power Dissipation = P_INT+ (C × V_DD²× f)

P

_INT= internal power dissipation (from Figure 15).

10

8

2

(C × V_DD× f) is calculated for each output:

# of

Pins

؋

C

6

4

2

Output

؋

V_DD

؋

f

Address, DMS 8

× 10 pF × 3.3²V × 10 MHz = 8.71 mW

× 10 pF × 3.3²V × 5 MHz = 4.90 mW

× 10 pF × 3.3²V × 5 MHz = 0.55 mW

× 10 pF × 3.3²V × 10 MHz = 1.09 mW

V

= 3.0V

DD

Data, WR

RD

CLKOUT

9

1

2

NOMINAL

–2

15.25 mW

Total power dissipation for this example = P_INT+ 15.25 mW.

–4

0

25

50

75

C

100

– pF

125

150

175

ENVIRONMENTAL CONDITIONS

L

Ambient Temperature Rating:

Figure 17. Typical Output Valid Delay or Hold vs. Load

Capacitance, C_L(at Maximum Ambient Operating

Temperature)

T

_AMB= T_CASE– (PD × θ_CA)

T_CASE= Case Temperature in °C

PD = Power Dissipation in W

θ_CA= Thermal Resistance (Case-to-Ambient)

θ_JA= Thermal Resistance (Junction-to-Ambient)

θ_JC= Thermal Resistance (Junction-to-Case)

Package

␪

CA

JA

JC

MQFP

60°C/W

18°C/W

42°C/W

REV. 0

–19–

ADSP-216x

SPECIFICATIONS

ADSP-2162/ADSP-2164/ADSP-2166

TEST CONDITIONS

Output Enable Time

Figure 18 shows voltage reference levels for ac measurements.

Output pins are considered to be enabled when they have made

a transition from a high-impedance state to when they start

driving. The output enable time (t_ENA) is the interval from when

a reference signal reaches a high or low voltage level to when the

output has reached a specified high or low trip point, as shown

in Figure 19. If multiple pins (such as the data bus) are enabled,

the measurement value is that of the first pin to start driving.

V

DD

INPUT

2

V

DD

OUTPUT

2

REFERENCE

SIGNAL

Figure 18. Voltage Reference Levels for AC Measurements

(Except Output Enable/Disable)

t_MEASURED

t_DIS

t_ENA

V

OH

(MEASURED)

Output Disable Time

OH

(MEASURED)

Output pins are considered to be disabled when they have

stopped driving and started a transition from the measured

output high or low voltage to a high impedance state. The out-

put disable time (t_DIS) is the difference of t_MEASUREDand t_DECAY

as shown in Figure 19. The time t_MEASUREDis the interval from

when a reference signal reaches a high or low voltage level to

when the output voltages have changed by 0.5 V from the mea-

sured output high or low voltage.

V

(MEASURED) – 0.5V

(MEASURED) +0.5V

2.0V

1.0V

OH

OUTPUT

OL

V

OL

t_DECAY

,

(MEASURED)

OUTPUT STARTS

DRIVING

OUTPUT STOPS

DRIVING

HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE

THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.

The decay time, t_DECAY, is dependent on the capacitative load,

C_L, and the current load, i_L, on the output pin. It can be ap-

proximated by the following equation:

Figure 19. Output Enable/Disable

I

OL

C_L×0.5V

t_DECAY

=

i_L

from which

TO

OUTPUT

V

DD

2

t

_DIS= t_MEASURED– t_DECAY

50pF

is calculated. If multiple pins (such as the data bus) are disabled,

the measurement value is that of the last pin to stop driving.

I

OH

Figure 20. Equivalent Device Loading for AC

Measurements (Except Output Enable/Disable)

–20–

REV. 0

ADSP-216x

TIMING PARAMETERS (ADSP-2161/ADSP-2163/ADSP-2165)

switching characteristics to ensure that any timing requirement

of a device connected to the processor (such as memory) is

satisfied.

GENERAL NOTES

Use the exact timing information given. Do not attempt to de-

rive parameters from the addition or subtraction of others. While

addition or subtraction would yield meaningful results for an

individual device, the values given in this data sheet reflect sta-

tistical variations and worst cases. Consequently, you cannot

Timing Requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices.

meaningfully add parameters to derive longer times.

TIMING NOTES

MEMORY REQUIREMENTS

Switching Characteristics specify how the processor changes its

signals. You have no control over this timing—circuitry external

to the processor must be designed for compatibility with these

signal characteristics. Switching characteristics tell you what the

processor will do in a given circumstance. You can also use

The table below shows common memory device specifications

and the corresponding ADSP-216x timing parameters, for your

convenience.

ADSP-216x

Timing Parameter

Memory Device Specification

Timing Parameter Definition

Address Setup to Write Start

Address Setup to Write End

Address Hold Time

Data Setup Time

t_ASW

t_AW

t_WRA

t_DW

t_DH

A0–A13, DMS, PMS Setup Before WR Low

A0–A13, DMS, PMS Setup Before WR Deasserted

A0–A13, DMS, PMS Hold After WR Deasserted

Data Setup Before WR High

Data Hold Time

Data Hold After WR High

OE to Data Valid

Address Access Time

t_RDD

t_AA

RD Low to Data Valid

A0–A13, DMS, PMS, BMS to Data Valid

REV. 0

–21–

ADSP-216x

TIMING PARAMETERS (ADSP-2161/ADSP-2163/ADSP-2165)

CLOCK SIGNALS AND RESET

16.67 MHz

Min Max

20 MHz

Min Max

25 MHz

Min Max

Frequency Dependency

Parameter

Min

Max

Unit

Timing Requirements:

t_CK

t_CKL

CLKIN Period

CLKIN Width Low

60

20

300

150

50

20

250

150

40

15

200

150

t_CK

20

150

ns

t_CKHCLKIN Width High

t_RSPRESET Width Low

Switching Characteristics:

t_CPLCLKOUT Width Low

t_CPHCLKOUT Width High

1

5t_CK

20

0

15

0

10

0

0.5t_CK– 10

0

ns

t_CKOHCLKIN High to CLKOUT High

20

15²

20²

NOTES

¹Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles, assuming stable CLKIN (not including crystal

oscillator startup time).

²For 25 MHz only, the maximum frequency dependency for t_CKOH= 15 ns.

t_CK

t_CKH

CLKIN

t_CKL

t_CHOK

t_CPH

CLKOUT

t_CPL

Figure 21. Clock Signals

–22–

REV. 0

ADSP-216x

TIMING PARAMETERS (ADSP-2161/ADSP-2163/ADSP-2165)

INTERRUPTS AND FLAGS

16.67 MHz

Min Max

20 MHz

25 MHz

Min Max

Frequency Dependency

Parameter

Min

Max

Min

Max

Unit

Timing Requirements:

t_IFS

t_IFH

IRQx¹or FI Setup Before

30

33

15

27.5

30.5

12.5

25

28

10

0.25t_CK+ 15

0.25t_CK+ 18

0.25t_CK

ns

CLKOUT Low^{2, 3}

IRQx¹or FI Setup Before

CLKOUT Low^{2, 3}

IRQx¹or FI Hold After CLKOUT

High^{2, 3}

Switching Characteristics:

t_FOHFO Hold After CLKOUT High

t_FODFO Delay from CLKOUT High

0

ns

15

12⁴

15⁴

NOTES

¹IRQx = IRQ0, IRQ1, and IRQ2.

²If IRQx and FI inputs meet t_IFSand t_IFHsetup/hold requirements, they will be recognized during the current clock cycle; otherwise they will be recognized during the

following cycle. (Refer to the “Interrupt Controller” section in Chapter 3, Program Control, of the ADSP-2100 Family User’s Manual, Third Edition for further

information on interrupt servicing.)

³Edge-sensitive interrupts require pulsewidths greater than 10 ns. Level-sensitive interrupts must be held low until serviced.

⁴For 25 MHz only, the maximum frequency dependency for t_FOD= 12 ns.

CLKOUT

t_FOD

t_FOH

FLAG

OUTPUT(S)

t_IFH

IRQx

FI

t_IFS

Figure 22. Interrupts and Flags

REV. 0

–23–

ADSP-216x

TIMING PARAMETERS (ADSP-2161/ADSP-2163/ADSP-2165)

BUS REQUEST/BUS GRANT

16.67 MHz

Min Max

20 MHz

Min Max

25 MHz

Min Max

Frequency Dependency

Parameter

Min

Max

Unit

BR Hold After CLKOUT High¹

20

17.5

32.5

15

30

0.25t_CK+ 5

0.25t_CK+ 20

ns

Switching Characteristics:

t_SD

CLKOUT High to DMS,

35

32.5

30

0.25t_CK+ 20 ns

PMS, BMS, RD, WR Disable

DMS, PMS, BMS, RD, WR

Disable to BG Low

BG High to DMS, PMS,

BMS, RD, WR Enable

DMS, PMS, BMS, RD, WR

Enable to CLKOUT High

t_SDB

t_SE

0

5

0

ns

0

t_SEC

2.5

1.5²

0.25t_CK– 10²

NOTES

¹If BR meets the t_BSand t_BHsetup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle. BR requires

a pulsewidth greater than 10 ns.

²For 25 MHz only, the minimum frequency dependency formula for t_SEC= (0.25t_CK– 8.5).

Section 10.2.4, “Bus Request/Grant,” on page 212 of the ADSP-2100 Family User’s Manual, Third Edition, states that “When BR is recognized, the processor responds

immediately by asserting BG during the same cycle.” This is incorrect for the current versions of all ADSP-21xx processors: BG is asserted in the cycle after BR is

recognized. No external synchronization circuit is needed when BR is generated as an asynchronous signal.

t_BH

CLKOUT

BR

t_BS

CLKOUT

PMS, DMS

BMS, RD

t_SD

t_SEC

WR

BG

t_SDB

t_SE

Figure 23. Bus Request/Bus Grant

–24–

REV. 0

ADSP-216x

TIMING PARAMETERS (ADSP-2161/ADSP-2163/ADSP-2165)

MEMORY READ

16.67 MHz

20 MHz

Min Max

25 MHz

Parameter

Min

Max

Min

Max

Unit

17

27

12

19.5

7

12

ns

0

Switching Characteristics:

t_RP

RD Pulsewidth

CLKOUT High to RD Low

22

10

5

6

25

17

12

5

ns

t_CRD

t_ASR

t_RDA

t_RWR

25

7.5

2.5

3.5

20

22.5

20

A0–A13, PMS, DMS, BMS Setup Before RD Low

A0–A13, PMS, DMS, BMS Hold After RD Deasserted

RD High to RD or WR Low

1.5¹

1

15

Frequency Dependency

(CLKIN

≤

25 MHz)

Max

Parameter

Min

Unit

Timing Requirements:

t_RDD

t_AA

RD Low to Data Valid

A0–A13, PMS, DMS, BMS to Data Valid

Data Hold from RD High

0.5t_CK– 13 + w

0.75t_CK– 18 + w

ns

t_RDH

0

0.5t_CK– 8 + w

0.25t_CK– 5

0.25t_CK– 10¹

0.25t_CK– 9

0.5t_CK– 5

ns

0.25t_CK+ 10

NOTES

¹For 25 MHz only, minimum frequency dependency formula for t_ASR= (0.25t_CK– 8.5).

w = wait states × t_CK.

CLKOUT

A0–A13

DMS, PMS,

BMS

t_RDA

RD

t_ASR

t_RP

t_RWR

t_CRD

D

t_RDD

t_RDH

t_AA

WR

Figure 24. Memory Read

REV. 0

–25–

ADSP-216x

TIMING PARAMETERS (ADSP-2161/ADSP-2163/ADSP-2165)

MEMORY WRITE

16.67 MHz

Max

20 MHz

25 MHz

Parameter

Min

Max

Min

Max

Unit

Switching Characteristics:

t_DW

t_DH

Data Setup Before WR High

Data Hold After WR High

17

5

22

0

5

12

2.5

17

7

0

ns

t_WP

WR Pulsewidth

WR Low to Data Enabled

12

0

t_WDE

t_ASW

t_DDR

t_CWR

t_AW

t_WRA

t_WWR

0

A0–A13, DMS, PMS Setup Before WR Low

Data Disable Before WR or RD Low

CLKOUT High to WR Low

A0–A13, DMS, PMS, Setup Before WR Deasserted

A0–A13, DMS, PMS Hold After WR Deasserted

WR High to RD or WR Low

2.5

7.5

15.5

3.5

20

1.5¹

5

10

23

6

25

22.5

20

8

1

15

25

Frequency Dependency

(CLKIN 25 MHz)

Max

≤

Parameter

Min

Unit

Switching Characteristics:

t_DW

t_DH

Data Setup Before WR High

Data Hold After WR High

0.5t_CK– 13 + w

0.25t_CK– 10

0.5t_CK– 8 + w

0

ns

t_WP

WR Pulsewidth

WR Low to Data Enabled

t_WDE

t_ASW

t_DDR

t_CWR

t_AW

t_WRA

t_WWR

A0–A13, DMS, PMS Setup Before WR Low

Data Disable Before WR or RD Low

CLKOUT High to WR Low

A0–A13, DMS, PMS, Setup Before WR Deasserted

A0–A13, DMS, PMS Hold After WR Deasserted

WR High to RD or WR Low

0.25t_CK– 10¹

0.25t_CK– 5

ns

0.25t_CK+ 10

0.75t_CK– 22 + w

0.25t_CK– 9

0.5t_CK– 5

NOTES

¹For 25 MHz only, the minimum frequency dependency formula for t_ASWand t_DDR= (0.25t_CK– 8.5).

w = wait states × t_CK

.

CLKOUT

A0–A13

DMS, PMS,

BMS

t_WRA

WR

t_WWR

t_ASW

t_WP

t_AW

t_DH

t_DDR

t_CWR

D

t_DW

t_WDE

RD

Figure 25. Memory Write

–26–

REV. 0

ADSP-216x

TIMING PARAMETERS (ADSP-2161/ADSP-2163/ADSP-2165)

SERIAL PORTS

13.824 MHz*

Frequency Dependency

Parameter

Min

Max

Min

Max

Unit

Timing Requirements:

t_SCK

t_SCS

t_SCH

t_SCP

SCLK Period

72.3

8

10

28

72.3

8

10

28

ns

DR/TFS/RFS Setup Before SCLK Low

DR/TFS/RFS Hold After SCLK Low

SCLK_INWidth

18.1

0

33.1

20

0.25t_CK

0

0.25t_CK+ 15

ns

20

0

20

0

18

25

20

18

25

20

*Maximum serial port operating frequency is 13.824 MHz for all processor speed grades.

CLKOUT

t_CC

t_SCK

SCLK

t_SCP

t_SCS

t_SCH

DR

TFS

IN

RFS

IN

t_RD

t_RH

RFS

TFS

OUT

t_SCDD

t_SCDV

t_SCDH

t_SCDE

DT

t_TDE

t_TDV

TFS

(ALTERNATE

FRAME MODE)

t_RDV

RFS

(MULTICHANNEL MODE,

FRAME DELAY 0 {MFD = 0})

Figure 26. Serial Ports

REV. 0

–27–

ADSP-216x

TIMING PARAMETERS (ADSP-2162/ADSP-2164/ADSP-2166)

switching characteristics to ensure that any timing requirement

of a device connected to the processor (such as memory) is

satisfied.

GENERAL NOTES

Use the exact timing information given. Do not attempt to de-

rive parameters from the addition or subtraction of others. While

addition or subtraction would yield meaningful results for an

individual device, the values given in this data sheet reflect sta-

tistical variations and worst cases. Consequently, you cannot

Timing Requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices.

meaningfully add parameters to derive longer times.

TIMING NOTES

MEMORY REQUIREMENTS

Switching Characteristics specify how the processor changes its

signals. You have no control over this timing—circuitry external

to the processor must be designed for compatibility with these

signal characteristics. Switching characteristics tell you what the

processor will do in a given circumstance. You can also use

The table below shows common memory device specifications

and the corresponding ADSP-216x timing parameters, for your

convenience.

ADSP-216x

Timing Parameter

Memory Device Specification

Timing Parameter Definition

Address Setup to Write Start

Address Setup to Write End

Address Hold Time

Data Setup Time

t_ASW

t_AW

t_WRA

t_DW

t_DH

A0–A13, DMS, PMS Setup Before WR Low

A0–A13, DMS, PMS Setup Before WR Deasserted

A0–A13, DMS, PMS Hold After WR Deasserted

Data Setup Before WR High

Data Hold Time

Data Hold After WR High

OE to Data Valid

Address Access Time

t_RDD

t_AA

RD Low to Data Valid

A0–A13, DMS, PMS, BMS to Data Valid

–28–

REV. 0

ADSP-216x

TIMING PARAMETERS (ADSP-2162/ADSP-2164/ADSP-2166)

CLOCK SIGNALS AND RESET

Frequency

Dependency

10.24 MHz

Min Max

Parameter

Min

Max

Unit

Timing Requirements:

t_CK

t_CKL

CLKIN Period

CLKIN Width Low

97.6

20

150

76.9

20

150

60.0

20

150

t_CK

20

150

ns

t_CKHCLKIN Width High

t_RSPRESET Width Low

Switching Characteristics:

t_CPLCLKOUT Width Low

t_CPHCLKOUT Width High

1

488

384.5

300

5t_CK

38.8

0

28.5

0

20

0

0.5t_CK– 10

0

ns

t_CKOHCLKIN High to CLKOUT High

20

NOTE

¹Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal

oscillator startup time).

t_CK

t_CKH

CLKIN

t_CKL

t_CHOK

t_CPH

CLKOUT

t_CPL

Figure 27. Clock Signals

REV. 0

–29–

ADSP-216x

TIMING PARAMETERS (ADSP-2162/ADSP-2164/ADSP-2166)

INTERRUPTS AND FLAGS

Frequency

Dependency

10.24 MHz

13.0 MHz

16.67 MHz

Parameter

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Timing Requirements:

t_IFS

IRQx¹or FI Setup Before

CLKOUT Low^{2, 3}

44.4

24.4

0

39.2

19.2

0

35.0

15.0

0

0.25t_CK+ 20

0.25t_CK

0

ns

t_IFH

IRQx¹or FI Hold After

CLKOUT High^{2, 3}

Switching Characteristics:

t_FOHFO Hold After CLKOUT High

t_FODFO Delay from CLKOUT High

ns

15

NOTES

¹IRQx = IRQ0, IRQ1, and IRQ2.

²If IRQx and FI inputs meet t_IFSand t_IFHsetup/hold requirements, they will be recognized during the current clock cycle; otherwise they will be recognized during the

following cycle. (Refer to the “Interrupt Controller” section in Chapter 3, Program Control, of the ADSP-2100 Family User’s Manual, Third Edition, for further

information on interrupt servicing.)

³Edge-sensitive interrupts require pulse widths greater than 10 ns. Level-sensitive interrupts must be held low until serviced.

CLKOUT

t_FOD

t_FOH

FLAG

OUTPUT(S)

t_IFH

IRQx

FI

t_IFS

Figure 28. Interrupts and Flags

–30–

REV. 0

ADSP-216x

TIMING PARAMETERS (ADSP-2162/ADSP-2164/ADSP-2166)

BUS REQUEST/BUS GRANT

10.24 MHz

13.0 MHz

Min Max

16.67 MHz

Frequency Dependency

Parameter

Min

Max

Min

Max

Min

Max

Unit

Timing Requirements:

t_BH

t_BS

BR Hold After CLKOUT High¹

29.4

24.2

39.2

20.0

35.0

0.25t_CK+ 5

0.25t_CK+ 20

ns

BR Setup Before CLKOUT Low¹44.4

Switching Characteristics:

t_SD

CLKOUT High to DMS, PMS,

BMS, RD, WR Disable

DMS, PMS, BMS, RD, WR

Disable to BG Low

BG High to DMS, PMS, BMS,

RD, WR Enable

DMS, PMS, BMS, RD, WR

Enable to CLKOUT High

44.4

39.2

35.0

0.25t_CK+ 20 ns

t_SDB

t_SE

0

ns

0

t_SEC

14.4

9.2

5.0

0.25t_CK– 10

NOTES

¹If BR meets the t_BSand t_BHsetup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle. BR

requires a pulsewidth greater than 10 ns.

Section 10.2.4, “Bus Request/Grant,” of the ADSP-2100 Family User’s Manual, Third Edition, states that, “When BR is recognized, the processor responds immedi-

ately by asserting BG during the same cycle.” This is incorrect for the current versions of all ADSP-21xx processors: BG is asserted in the cycle after BR is recognized.

No external synchronization circuit is needed when BR is generated as an asynchronous signal.

t_BH

CLKOUT

BR

t_BS

CLKOUT

PMS, DMS

BMS, RD

t_SD

t_SEC

WR

BG

t_SDB

t_SE

Figure 29. Bus Request/Grant

REV. 0

–31–

ADSP-216x

TIMING PARAMETERS (ADSP-2162/ADSP-2164/ADSP-2166)

MEMORY READ

10.24 MHz

13.0 MHz

16.67 MHz

Frequency Dependency

Parameter

Min

Max Min Max

Min

Max

Min

Max

Unit

Timing Requirements:

t_RDDRD Low to Data Valid

33.8

49.2

23.5

33.7

15

21

0.5t_CK– 15 + w

ns

t_AA

A0–A13, PMS, DMS, BMS to

Data Valid

0.75t_CK– 24 + w ns

ns

t_RDHData Hold from RD High

0

Switching Characteristics:

t_RP

RD Pulsewidth

43.8

19.4

33.25

34.4 14.2

25

10.0

0.5t_CK– 5 + w

0.25t_CK– 5

ns

t_CRDCLKOUT High to RD Low

29.2

25.0

0.25t_CK+ 10

t_ASR

t_RDA

A0–A13, PMS, DMS, BMS

Setup Before RD Low

A0–A13, PMS, DMS, BMS

Hold After RD Deasserted

12.4

7.2

3.0

0.25t_CK– 12

ns

14.4

38.8

9.2

28.5

5.0

20.0

0.25t_CK– 10

0.5t_CK– 10

ns

t_RWRRD High to RD or WR Low

w = wait states × t_CK.

CLKOUT

A0–A13

DMS, PMS,

BMS

t_RDA

RD

t_ASR

t_CRD

t_RP

t_RWR

D

t_RDD

t_RDH

t_AA

WR

Figure 30. Memory Read

–32–

REV. 0

ADSP-216x

TIMING PARAMETERS (ADSP-2162/ADSP-2164/ADSP-2166)

MEMORY WRITE

Frequency

Dependency

10.24 MHz

13.0 MHz

16.67 MHz

Parameter

Min

Max Min Max

Min

Max

Min

Max

Unit

Switching Characteristics:

t_DW

t_DH

t_WP

Data Setup Before WR High

Data Hold After WR High

WR Pulsewidth

38.8

14.4

43.8

0

28.25

9.2

33.25

0

20

5.0

25

0

0.5t_CK– 10 + w

0.25t_CK– 10

0.5t_CK– 5 + w

0

ns

t_WDEWR Low to Data Enabled

t_ASWA0–A13, DMS, DMS Setup

Before WR Low

t_DDRData Disable Before WR

or RD Low

12.4

7.2

3.0

0.25t_CK– 12

ns

14.4

19.4

9.2

34.4 14.2

5.0

10.0

0.25t_CK– 10

0.25t_CK– 5

t_CWRCLKOUT High to WR Low

29.2

25.0

0.25t_CK+ 10 ns

t_AW

A0–A13, DMS, PMS, Setup

Before WR Deasserted

58.2

42.7

30

0.75t_CK– 15 + w

ns

t_WRAA0–A13, DMS, PMS Hold

After WR Deasserted

t_WWRWR High to RD or WR Low

14.4

38.8

9.2

28.25

5.0

20

0.25t_CK– 10

0.5t_CK– 10

ns

w = wait states × t_CK.

CLKOUT

A0–A13

DMS, PMS,

BMS

t_WRA

WR

t_WWR

t_ASW

t_WP

t_AW

t_DH

t_DDR

t_CWR

D

t_DW

t_WDE

RD

Figure 31. Memory Write

REV. 0

–33–

ADSP-216x

TIMING PARAMETERS (ADSP-2162/ADSP-2164/ADSP-2166)

SERIAL PORTS

10.24 MHz

Min Max

13.0 MHz

Min Max

13.824 MHz¹

Frequency Dependency

Parameter

Min

Max

Min

Max

Unit

Timing Requirements:

72.3¹

8

t_CK

ns

1

t_SCK

t_SCS

SCLK Period

97.6

8

76.9

8

DR/TFS/RFS Setup

Before SCLK Low

DR/TFS/RFS Hold After

SCLK Low

8

t_SCH

t_SCP

10

28

10

28

10

28

10

28

ns

SCLK_INWidth

Switching Characteristics:

t_CCCLKOUT High to SCLK_OUT24.4 39.4

t_SCDESCLK High to DT Enable

t_SCDVSCLK High to DT Valid

19.2 34.2

18.1

0

33.1

20

0.25t_CK0.25t_CK+ 15

ns

0

28²

20

20²

t_RH

TFS/RFS_OUTHold After

SCLK High

0

ns

t_RD

TFS/RFS_OUTDelay from

SCLK High

20

20²

ns

t_SCDHDT Hold After SCLK High

t_TDETFS (Alt) to DT Enable

t_TDVTFS (Alt) to DT Valid

0

18

25

18

25

18

25²

t_SCDDSCLK High to DT Disable

30²

t_RDV

RFS (Multichannel, Frame 20

Delay Zero) to DT Valid

20

ns

NOTES

¹Maximum serial port operating frequency is 13.824 MHz for all processor speed grades faster then 13.824 MHz.

²For 10.24 MHz only, the maximum frequency dependency for t_SCDV= 28 ns, t_RD= 28 ns, t_SCDD= 30 ns.

CLKOUT

t_CC

t_SCK

SCLK

t_SCP

t_SCS

t_SCH

DR

TFS

IN

RFS

IN

t_RD

t_RH

RFS

TFS

OUT

t_SCDD

t_SCDV

t_SCDH

t_SCDE

DT

t_TDE

t_TDV

TFS

(ALTERNATE

FRAME MODE)

t_RDV

RFS

(MULTICHANNEL MODE,

FRAME DELAY 0 {MFD = 0})

Figure 32. Serial Ports

–34–

REV. 0

ADSP-216x

PIN CONFIGURATIONS

68-Lead PLCC

9

8

7

6

5

4

3

2

1

68 67 66 65 64 63 62 61

10

11

12

13

14

15

16

17

18

19

20

21

PIN 1

GND

D19

D20

60

59

58

57

56

55

54

53

52

51

50

49

48

D2

IDENTIFIER

D1

D0

D21

V

DD

D22

D23

SCLK1

FI

V

DD

IRQ0

IRQ1

FO

MMAP

ADSP-216x

TOP VIEW

(Not to Scale)

BR

IRQ2

RESET

A0

SCLK0

DR0

GND

A1 22

RFS0

23

24

A2

A3

47 TFS0

46

45

44

DT0

RD

A4 25

26

V

DD

WR

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

PLCC

Number

Name

PLCC

Number

Name

PLCC

Number Name

PLCC

Number

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

A12

A13

1

2

3

4

5

6

7

8

D11

GND

D12

D13

D14

D15

D16

D17

D18

GND

D19

D20

D21

D22

D23

V_DD

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

FO

(DT1)

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

BR

IRQ2

RESET

A0

A1

A2

A3

A4

V_DD

A5

A6

GND

A7

A8

A9

A10

IRQ1 (TFS1)

IRQ0 (RFS1)

FI

SCLK1

V_DD

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

PMS

DMS

BMS

BG

XTAL

CLKIN

CLKOUT

WR

RD

DT0

TFS0

RFS0

GND

DR0

(DR1)

9

10

11

12

13

14

15

16

17

51

SCLK0

MMAP

A11

REV. 0

–35–

ADSP-216x

PIN CONFIGURATIONS

80-Lead MQFP

60 D18

59 D17

1

2

A5

A6

PIN 1

IDENTIFIER

GND

3

58

D16

57 D15

56 D14

4

A7

5

55

6

A8

A9

D13

54 D12

7

53

52

51

50

A10

A11

8

GND

D11

9

ADSP-216x

TOP VIEW

(Not to Scale)

A12

A13

10

11

12

13

14

15

16

17

18

19

20

D10

49 D9

48

PMS

D8

47 D7

DMS

BMS

46

45

44

43

42

D6

BG

XTAL

D5

D4

CLKIN

*PWDACK

NC

*PWDFLAG

NC

41 NC

NC = NO CONNECT

MQFP

Number

Name

MQFP

Number Name

MQFP

Number Name

MQFP

Number

Name

1

2

3

4

5

6

7

8

A5

A6

GND

A7

A8

A9

A10

A11

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

CLKOUT

WR

RD

DT0

TFS0

RFS0

GND

DR0

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

GND

D19

D20

D21

D22

D23

V_DD

MMAP

BR

IRQ2

RESET

A0

A1

A2

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

NC

D4

D5

D6

D7

D8

9

D9

10

11

12

13

14

15

16

17

18

19

20

A12

A13

SCLK0

FO

D10

D11

GND

D12

D13

D14

D15

D16

D17

D18

(DT1)

PMS

DMS

BMS

BG

XTAL

CLKIN

PWDACK*

PWDFLAG*

NC

IRQ1 (TFS1)

IRQ0 (RFS1)

FI

(DR1)

SCLK1

V_DD

D0

D1

D2

A3

A4

V_DD

D3

*ADSP-2165/ADSP-2166 only.

Others “NC”.

–36–

REV. 0

ADSP-216x

OUTLINE DIMENSIONS

ADSP-216x

68-Lead Plastic Leaded Chip Carrier (PLCC)

0.175 (4.45)

0.169 (4.29)

0.995 (25.27)

0.985 (25.02)

SQ

9

61

10

60

PIN 1

IDENTIFIER

0.050

(1.27)

TYP

PIN 1

IDENTIFIER

0.925 (23.50)

0.895 (22.73)

TOP VIEW

(PINS DOWN)

BOTTOM VIEW

(PINS UP)

0.019 (0.48)

0.017 (0.43)

0.029 (0.74)

0.027 (0.69)

26

44

43

27

0.954 (24.23)

0.950 (24.13)

SQ

0.104 (2.64) TYP

REV. 0

–37–

ADSP-216x

OUTLINE DIMENSIONS

ADSP-216x

80-Lead Plastic Quad Flatpack (MQFP)

0.690 (17.45)

0.667 (16.95)

0.134 (3.40)

MAX

0.555 (14.10)

0.547 (13.90)

0.486 (12.35) BSC

0.041 (1.03)

0.031 (0.78)

80

61

60

1

SEATING

PLANE

TOP VIEW

(PINS DOWN)

0.004 (0.10)

MAX

20

21

41

40

0.010 (0.25)

MIN

0.026 (0.65) 0.014 (0.35)

BSC

0.010 (0.25)

0.120 (3.05)

0.100 (2.55)

THE ACTUAL POSITION OF EACH LEAD

IS WITHIN 0.0047 (0.12) FROM ITS IDEAL

POSITION WHEN MEASURED IN THE

LATERAL DIRECTION.

–38–

REV. 0

ADSP-216x

ORDERING GUIDE

Ambient

Temperature

Range

Instruction

Rate (MHz)

Package

Description

Package

Option

Part Number¹

ADSP-2161KP-66²

ADSP-2161BP-66²

ADSP-2161KS-66²

ADSP-2161BS-66²

0°C to +70°C

–40°C to +85°C

0°C to +70°C

–40°C to +85°C

16.67

68-Lead PLCC

80-Lead MQFP

P-68A

S-80

ADSP-2162KP-40 (3.3 V)²

ADSP-2162BP-40 (3.3 V)²

ADSP-2162KS-40 (3.3 V)²

0°C to +70°C

–40°C to +85°C

0°C to +70°C

10.24

68-Lead PLCC

80-Lead MQFP

P-68A

S-80

ADSP-2163KP-66²

ADSP-2163BP-66²

ADSP-2163KS-66²

ADSP-2163BS-66²

0°C to +70°C

–40°C to +85°C

0°C to +70°C

–40°C to +85°C

16.67

68-Lead PLCC

80-Lead MQFP

P-68A

S-80

ADSP-2163KP-100²

ADSP-2163BP-100²

ADSP-2163KS-100²

ADSP-2163BS-100²

0°C to +70°C

–40°C to +85°C

0°C to +70°C

–40°C to +85°C

25

68-Lead PLCC

80-Lead MQFP

P-68A

S-80

ADSP-2164KP-40 (3.3 V)²

ADSP-2164BP-40 (3.3 V)²

ADSP-2164KS-40 (3.3 V)²

ADSP-2164BS-40 (3.3 V)²

0°C to +70°C

–40°C to +85°C

0°C to +70°C

–40°C to +85°C

10.24

68-Lead PLCC

80-Lead MQFP

P-68A

S-80

ADSP-2165KS-80

ADSP-2165KS-100

ADSP-2165BS-80

ADSP-2165BS-100

0°C to +70°C

–40°C to +85°C

20.00

25.00

20.00

25.00

80-Lead MQFP

S-80

ADSP-2166KS-52 (3.3 V)

ADSP-2166KS-66 (3.3 V)

ADSP-2166BS-52 (3.3 V)

ADSP-2166BS-66 (3.3 V)

0°C to +70°C

–40°C to +85°C

13.00

16.67

13.00

16.67

80-Lead MQFP

S-80

NOTES

¹K = Commercial Temperature Range (0°C to +70°C).

B = Industrial Temperature Range (–40°C to +85°C).

P = PLCC (Plastic Leaded Chip Carrier).

S

= MQFP (Plastic Quad Flatpack).

²Minimum order quantities required. Contact factory for further information.

³Refer to the section titled “Ordering Procedure for ROM-Coded ADSP-216x Processors” for information about ROM coded parts.

REV. 0

–39–


型号：	ADSP-2163KS-100
厂家：	ADI
描述：	DSP Microcomputers with ROM DSP与微型计算机的ROM 计算机
文件：	总39页 (文件大小：245K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-2163KS-100 [ADI]

相关型号：

ADSP-2163KS-1002

ADSP-2163KS-66

ADSP-2163KS-662

ADSP-2163_15

ADSP-2164

ADSP-2164BP-40

ADSP-2164BP-40(3.3V)

ADSP-2164BS-40

ADSP-2164BS-40(3.3V)

ADSP-2164KP-40

ADSP-2164KP-40(3.3V)

ADSP-2164KS-40